On Wed, 27 Nov 2019 at 19:44, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>
> Fix some issues in the ACPI and DT descriptions of the SMMU routing,
> in particular the routing of the CCP crypto accelerator, which sits
> behind an SMMU as well on B1 silicon (but not on B0, strangely enough)
>
> Changes since v1:
> - add Leif's ack to patches #1, #2 and #4
> - add patches to fix some errors and inaccuracies in the DT
> - update the DT generation code to emit interrupt affinity for the PMU node
> - update the DT generation code to emit a description of the cache topology
> - stop emitting the obsolete linux,phandle properties
>
> Ard Biesheuvel (8):
> Platform/Overdrive: add missing resolution for FileHandleLib
> Platform/Overdrive: clean up stream ID descriptions in DT
> Platform/Overdrive: fix a typo in the DT
> Silicon/AMD/Styx: clean up stream ID mappings for SMMU
> Silicon/AMD/StyxDtbLoaderLib: add interrupt-affinity property to PMU
> node
> Silicon/AMD/StyxDtbLoaderLib: add description of the cache topology
> Silicon/AMD/StyxDtbLoaderLib: use Cortex-A57 IDs instead of generic
> ARMv8
> Silicon/AMD/StyxDtbLoaderLib: omit linux,phandle properties
>
Series pushed as 04889ec1198b..6bde2876c3aa
Thanks,
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