From nobody Mon Feb 9 14:02:51 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+50637+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+50637+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1573712560; cv=none; d=zoho.com; s=zohoarc; b=HnhkOiP1jhXucgKfwUKK2L18IgasteA3+AK1+jGNCRaydFuxersTW/gseMjWxa8jlngbqYcLrkqENrnQotGeh7Krr26VnBKvjzQc4F0pXzAnfpfmDiAhCaw2yBv25F+KWLg/YOnXpUNzSclFaH6pQC2A3Qbc4xv+1J3J8CrkBYQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1573712560; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=04UtxAC13e1yWldgVLiYUtW0gHtoXBFrmXFmCDgZ9q4=; b=gNMfmHnqXqsyvUnBd8mYQy/SKnTNn+mrRVMdaphN75kfLduU2Y9As+kJGB4G/WQRzqg3DlvM5eefXACv8iV6lR9E8zaK3lUgm+Y8Awo81vx1n4TRvAlmIBWI++pOClo/brO4N1OZyWmtu3iQgQ39L/qHMIvsVk0yafSufls2wAg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+50637+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1573712560522305.42376639499525; Wed, 13 Nov 2019 22:22:40 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ydXjYY1788612xUS096KF5QW; Wed, 13 Nov 2019 22:22:40 -0800 X-Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web11.412.1573712556165867066 for ; Wed, 13 Nov 2019 22:22:37 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Nov 2019 22:22:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,302,1569308400"; d="scan'208";a="216641623" X-Received: from nldesimo-desk1.amr.corp.intel.com ([10.7.159.63]) by orsmga002.jf.intel.com with ESMTP; 13 Nov 2019 22:22:34 -0800 From: "Nate DeSimone" To: devel@edk2.groups.io Cc: Michael Kubacki , Chasel Chiu , Liming Gao Subject: [edk2-devel] [edk2-platforms] [PATCH V1 09/13] MinPlatformPkg: FSP Dispatch Mode Support for PlatformSecLib Date: Wed, 13 Nov 2019 22:06:51 -0800 Message-Id: <20191114060655.5161-10-nathaniel.l.desimone@intel.com> In-Reply-To: <20191114060655.5161-1-nathaniel.l.desimone@intel.com> References: <20191114060655.5161-1-nathaniel.l.desimone@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,nathaniel.l.desimone@intel.com X-Gm-Message-State: C5qsfPdhdQLRNNb2Raf5gB4Hx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1573712560; bh=0w6GOHZUoWE0e6paTOzEL6IvFgKvzfSVKwycIQ+6j7A=; h=Cc:Date:From:Reply-To:Subject:To; b=iOScnzzsNEwTr7zg4Wj5HY6fjwKZdzXjpO6IIxsoH34bL9rcxw1zaJekxuddaN+RnLH iitdzKD0gShCteuyWphy37JItCbnA3kkI8MXjTUldITJZ/LzENaNSbnx72tB/0q7q0GGZ kwmlQYg1h8DU3+3UUu7v/vGN6fXfYWOVMEw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: Michael Kubacki Cc: Chasel Chiu Cc: Liming Gao Signed-off-by: Nate DeSimone Reviewed-by: Chasel Chiu Reviewed-by: Michael Kubacki --- .../FspWrapperPlatformSecLib.c | 34 ++++++++++++--- .../SecFspWrapperPlatformSecLib.inf | 7 +++- .../SecTempRamDone.c | 42 +++++++++++++++---- .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 28 ++++++++++++- 4 files changed, 95 insertions(+), 16 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/MinPlatformPkg/F= spWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c index 303f3aac40..876c073fc4 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FspWrapperPlatformSecLib.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FspWrapperPlatformSecLib.c @@ -1,7 +1,7 @@ /** @file Provide FSP wrapper platform sec related function. =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -12,6 +12,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include =20 #include @@ -66,6 +67,18 @@ PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi =3D { SecGetPerformance }; =20 +EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi =3D { + (VOID *) (UINTN) FixedPcdGet32 (PcdFspmBaseAddress) +}; + +EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiPeiCoreFvLocationPpiGuid, + &mPeiCoreFvLocationPpi + } +}; + EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D { { EFI_PEI_PPI_DESCRIPTOR_PPI, @@ -129,6 +142,8 @@ SecPlatformMain ( ) { EFI_PEI_PPI_DESCRIPTOR *PpiList; + UINT8 TopOfTemporaryRamPpiIndex; + UINT8 *CopyDestinationPointer; =20 DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCo= reData->BootFirmwareVolumeBase)); DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCo= reData->BootFirmwareVolumeSize)); @@ -150,13 +165,22 @@ SecPlatformMain ( // Use middle of Heap as temp buffer, it will be copied by caller. // Do not use Stack, because it will cause wrong calculation on stack by= PeiCore // - PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + (UINTN)Se= cCoreData->PeiTemporaryRamSize/2); - CopyMem (PpiList, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi)); - + PpiList =3D (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) = SecCoreData->PeiTemporaryRamSize/2); + CopyDestinationPointer =3D (UINT8 *) PpiList; + TopOfTemporaryRamPpiIndex =3D 0; + if ((PcdGet8 (PcdFspModeSelection) =3D=3D 0) && PcdGetBool (PcdFspDispat= chModeUseFspPeiMain)) { + // + // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi. + // + CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mP= eiCoreFvLocationPpiList)); + TopOfTemporaryRamPpiIndex =3D 1; + CopyDestinationPointer +=3D sizeof (mPeiCoreFvLocationPpiList); + } + CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof(mPeiSecPlatf= ormPpi)); // // Patch TopOfTemporaryRamPpi // - PpiList[0].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCo= reData->TemporaryRamSize); + PpiList[TopOfTemporaryRamPpiIndex].Ppi =3D (VOID *)((UINTN) SecCoreData-= >TemporaryRamBase + SecCoreData->TemporaryRamSize); =20 return PpiList; } diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatform= Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSec= Lib.inf index 3f5a63f273..02c720c73d 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf @@ -72,18 +72,20 @@ BoardInitLib SecBoardInitLib TestPointCheckLib + PeiServicesTablePointerLib =20 [Ppis] gEfiSecPlatformInformationPpiGuid ## CONSUMES gPeiSecPerformancePpiGuid ## CONSUMES gTopOfTemporaryRamPpiGuid ## PRODUCES gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES + gFspTempRamExitPpiGuid ## CONSUMES =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## C= ONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## C= ONSUMES gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## C= ONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONS= UMES + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## C= ONSUMES =20 [FixedPcd] gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C= ONSUMES @@ -91,3 +93,6 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## C= ONSUMES diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecTempRamDone.c b/Platform/Intel/MinPlatformPkg/FspWrapper/= Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c index cde8a80a4e..922e4ec204 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecTempRamDone.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecTempRamDone.c @@ -1,7 +1,7 @@ /** @file Provide SecTemporaryRamDone function. =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -9,6 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include =20 #include +#include =20 #include #include @@ -17,6 +18,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** This interface disables temporary memory in SEC Phase. @@ -29,17 +31,41 @@ SecPlatformDisableTemporaryMemory ( { EFI_STATUS Status; VOID *TempRamExitParam; + CONST EFI_PEI_SERVICES **PeiServices; + FSP_TEMP_RAM_EXIT_PPI *TempRamExitPpi; + + DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n")); =20 - DEBUG((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n")); - =20 Status =3D BoardInitBeforeTempRamExit (); ASSERT_EFI_ERROR (Status); =20 - TempRamExitParam =3D UpdateTempRamExitParam (); - Status =3D CallTempRamExit (TempRamExitParam); - DEBUG((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status)); - ASSERT_EFI_ERROR(Status); - =20 + if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) { + // + // FSP API mode + // + TempRamExitParam =3D UpdateTempRamExitParam (); + Status =3D CallTempRamExit (TempRamExitParam); + DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status)); + ASSERT_EFI_ERROR (Status); + } else { + // + // FSP Dispatch mode + // + PeiServices =3D GetPeiServicesTablePointer (); + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gFspTempRamExitPpiGuid, + 0, + NULL, + (VOID **) &TempRamExitPpi + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return; + } + TempRamExitPpi->TempRamExit (NULL); + } + Status =3D BoardInitAfterTempRamExit (); ASSERT_EFI_ERROR (Status); =20 diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index a851021c0b..856c17f737 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -69,8 +69,6 @@ SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h =20 [PcdsFixedAtBuild, PcdsPatchableInModule] =20 -gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x800000= 08 - gMinPlatformPkgTokenSpaceGuid.PcdFspMaxUpdSize|0x00000000|UINT32|0x80000000 gMinPlatformPkgTokenSpaceGuid.PcdFspReservedSizeOnStackTop|0x00000040|UINT= 32|0x80000001 gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0x00000000|UINT32|0x8000= 0002 @@ -272,6 +270,32 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UI= NT32|0x90000019 # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4|UINT8|0xF00000A0 =20 + ## FSP Boot Mode Selector + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x8000= 0008 + + ## FSP Dispatch Mode: Use the PEI Main Binary Included in FSP-M + # FALSE: The PEI Main included in FvPreMemory is used to dispatch all PE= IMs + # (both inside FSP and outside FSP). + # Pros: + # * PEI Main is re-built from source and is always the latest v= ersion + # * Platform code can link any desired LibraryClass to PEI Main + # (Ex: Custom DebugLib instance, SerialPortLib, etc.) + # Cons: + # * The PEI Main being used to execute FSP PEIMs is not the PEI= Main + # that the FSP PEIMs were tested with, adding risk of breakag= e. + # * Two copies of PEI Main will exist in the final binary, + # #1 in FSP-M, #2 in FvPreMemory. The copy in FSP-M is never + # executed, wasting space. + # + # TRUE: The PEI Main included in FSP is used to dispatch all PEI= Ms + # (both inside FSP and outside FSP). PEI Main will not be include= d in + # FvPreMemory. This is the default and is the recommended choice. + # + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|BOOLE= AN|0xF00000A8 + [PcdsFeatureFlag] =20 gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE|BOOLEAN|0= xF00000A1 --=20 2.23.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#50637): https://edk2.groups.io/g/devel/message/50637 Mute This Topic: https://groups.io/mt/57059579/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-