From nobody Mon Feb 9 05:41:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49811+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49811+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621021; cv=none; d=zoho.com; s=zohoarc; b=KNwiV/8PRExkCXpd9E3sc9sNOk3f6FUZqA1vgOSTs4rAJLqCdiexpLzOM4F8UOXFspyT84mZM7FUzxDjmB8noHaOgYKmuitYIvRF7iGaPThFTGcuBAfk3wxchiXX6NLepWoHVTfQYO4Vr0R1aXbN6fIZ1jqQDpiVpX1bEwNKjeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621021; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OhhsxvNVeo+fewHMUDy5IT++bDZGqy0OmiKJM9zuid0=; b=cBL6NPwN/xW2niVo6J5+Om0nbJENr9C2v/Xvc+lyk5+9bqN6gzIgJRDFAzK7pgEuhP77AhCr6chJf5QwpbhnZY0QYzktIttrbcPEtJ6ndwqQ9rQJe88reKGBfS2FUHR3qmBxHiTaeMrRRsVvjuzg47SlMHK5aJ3XtfeZevBkNag= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49811+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621021183237.14150354237267; Fri, 1 Nov 2019 08:10:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:20 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:20 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687147" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:17 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure Date: Fri, 1 Nov 2019 20:39:47 +0530 Message-Id: <20191101150952.3340-8-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621020; bh=nP7ZbRW7YXTPD1TCopJ4YMqPum5yJt8BOmVLULmhLFo=; h=Cc:Date:From:Reply-To:Subject:To; b=d5+tmJjEbhLKsxCfFpzLaExUhT+b5NtXjjgwkiWJEwaCmLqHqrFMGQyQgSpKvfNEA9D FR7soTEKHreXHWcFijm6d+GbN/VcfFeI0LyJv9cjsZkOKiZTr94rUSMjwt+tNJ7viNHp9 w5h5w8PTRVGtFrv8ECTSiaEn2jGt3E0rHWY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The code changes are made to record the PCI device's PCI-Express Capability Structure register set during early PCI enumeration phase. This data shall be used during PCI feature enumeration phase. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 6 +++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 34 +++++++++++++++= +++++++------------ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 51 +++++++++++++++= ++++++++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 13 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 95a677b..dc29ef3 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -266,9 +266,13 @@ struct _PCI_IO_DEVICE { =20 BOOLEAN IsPciExp; // - // For SR-IOV + // For PCI Express Capability List Structure // UINT8 PciExpressCapabilityOffset; + PCI_CAPABILITY_PCIEXP PciExpStruct; + // + // For SR-IOV + // UINT32 AriCapabilityOffset; UINT32 SrIovCapabilityOffset; UINT32 MrIovCapabilityOffset; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index c7eafff..2343702 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -230,7 +230,7 @@ PciSearchDevice ( PciIoDevice =3D NULL; =20 DEBUG (( - EFI_D_INFO, + DEBUG_INFO, "PciBus: Discovered %s @ [%02x|%02x|%02x]\n", IS_PCI_BRIDGE (Pci) ? L"PPB" : IS_CARDBUS_BRIDGE (Pci) ? L"P2C" : @@ -397,7 +397,7 @@ DumpPpbPaddingResource ( =20 if ((Type !=3D PciBarTypeUnknown) && ((ResourceType =3D=3D PciBarTypeU= nknown) || (ResourceType =3D=3D Type))) { DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " Padding: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%lx\n= ", mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor->AddrLen )); @@ -424,7 +424,7 @@ DumpPciBars ( } =20 DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " BAR[%d]: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%lx;\tO= ffset =3D 0x%02x\n", Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTy= peMaxType)], PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Len= gth, PciIoDevice->PciBar[Index].Offset @@ -437,13 +437,13 @@ DumpPciBars ( } =20 DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " VFBAR[%d]: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%lx;\tO= ffset =3D 0x%02x\n", Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBar= TypeMaxType)], PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index]= .Length, PciIoDevice->VfPciBar[Index].Offset )); } - DEBUG ((EFI_D_INFO, "\n")); + DEBUG ((DEBUG_INFO, "\n")); } =20 /** @@ -1903,7 +1903,7 @@ PciParseBar ( // Fix the length to support some special 64 bit BAR // if (Value =3D=3D 0) { - DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 = BAR returns 0, change to 0xFFFFFFFF.\n")); + DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 = BAR returns 0, change to 0xFFFFFFFF.\n")); Value =3D (UINT32) -1; } else { Value |=3D ((UINT32)(-1) << HighBitSet32 (Value)); @@ -2153,7 +2153,17 @@ CreatePciIoDevice ( NULL ); if (!EFI_ERROR (Status)) { - PciIoDevice->IsPciExp =3D TRUE; + PciIoDevice->IsPciExp =3D TRUE; + // + // read the PCI device's entire PCI Express Capability structure + // + PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint8, + PciIoDevice->PciExpressCapabilityOffset, + sizeof (PCI_CAPABILITY_PCIEXP) / sizeof (UINT8), + &PciIoDevice->PciExpStruct + ); } =20 if (PcdGetBool (PcdAriSupport)) { @@ -2206,7 +2216,7 @@ CreatePciIoDevice ( &Data32 ); DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n", Bridge->BusNumber, Bridge->DeviceNumber, @@ -2215,7 +2225,7 @@ CreatePciIoDevice ( } } =20 - DEBUG ((EFI_D_INFO, " ARI: CapOffset =3D 0x%x\n", PciIoDevice->AriCa= pabilityOffset)); + DEBUG ((DEBUG_INFO, " ARI: CapOffset =3D 0x%x\n", PciIoDevice->AriCa= pabilityOffset)); } } =20 @@ -2325,12 +2335,12 @@ CreatePciIoDevice ( PciIoDevice->ReservedBusNum =3D (UINT16)(EFI_PCI_BUS_OF_RID (LastVF)= - Bus + 1); =20 DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " SR-IOV: SupportedPageSize =3D 0x%x; SystemPageSize =3D 0x%x; Fir= stVFOffset =3D 0x%x;\n", SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset )); DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " InitialVFs =3D 0x%x; ReservedBusNum =3D 0x%x; CapOffset = =3D 0x%x\n", PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice-= >SrIovCapabilityOffset )); @@ -2345,7 +2355,7 @@ CreatePciIoDevice ( NULL ); if (!EFI_ERROR (Status)) { - DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset =3D 0x%x\n", PciIoDevice->Mr= IovCapabilityOffset)); + DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset =3D 0x%x\n", PciIoDevice->Mr= IovCapabilityOffset)); } } =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index 9e6671d..df9e696 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -467,6 +467,14 @@ GetPciFeaturesConfigurationTable ( return EFI_SUCCESS; } =20 + // + // The PCI features configuration table is not built for RCiEP, return N= ULL + // + if (PciDevice->PciExpStruct.Capability.Bits.DevicePortType =3D=3D \ + PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) { + *PciFeaturesConfigTable =3D NULL; + return EFI_SUCCESS; + } =20 if (IsDevicePathEnd (PciDevice->DevicePath)){ // @@ -575,6 +583,45 @@ IsPciRootPortEmpty ( } =20 =20 +/** + helper routine to dump the PCIe Device Port Type +**/ +VOID +DumpDevicePortType ( + IN UINT8 DevicePortType + ) +{ + switch (DevicePortType){ + case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT: + DEBUG (( DEBUG_INFO, "PCIe endpoint found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT: + DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_ROOT_PORT: + DEBUG (( DEBUG_INFO, "PCIe Root Port found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT: + DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT: + DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE: + DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE: + DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT: + DEBUG (( DEBUG_INFO, "RCiEP found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR: + DEBUG (( DEBUG_INFO, "RC Event Collector found\n")); + break; + } +} + /** Process each PCI device as per the pltaform and device-specific policy. =20 @@ -590,8 +637,12 @@ SetupDevicePciFeatures ( ) { EFI_STATUS Status; + PCI_REG_PCIE_CAPABILITY PcieCap; OTHER_PCI_FEATURES_CONFIGURATION_TABLE *OtherPciFeaturesConfigTable; =20 + PcieCap.Uint16 =3D PciDevice->PciExpStruct.Capability.Uint16; + DumpDevicePortType ((UINT8)PcieCap.Bits.DevicePortType); + OtherPciFeaturesConfigTable =3D NULL; Status =3D GetPciFeaturesConfigurationTable (PciDevice, &OtherPciFeature= sConfigTable); if (EFI_ERROR( Status)) { --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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