From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49805+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49805+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621013; cv=none; d=zoho.com; s=zohoarc; b=aPvZ1rtSLxBiXjv8n3uTNtX3jv1iMGd9hmmjS5935sq9zieNCjPdW6cpE9kfvhLq/EnN7sCFaVJ/jabFmmGk3z0PoBUyBX6tja8UIc9BD+bMWZ0v4jVkrZL1ZzgGQI+lMybMHPdEDyhOL0jCF5LYuUEG1ekD8ykdEKw/cCHYdkg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621013; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=8MA5dEA8I5wiRN1ciU9DiHtuTEBBnOJk89PdBmx8m9o=; b=P7Tr1fX4ktgnRfsFurJz8lo/G0fuyhCv80OGpqa1/4PmfqDx4sR9ioVgM2zEs5pDFpmoodmCAM1omOA+Cha4OdW8FdTPzCcAcdZOQHsYQmK2N5/wv9i1AYtpFwBNsHCuYu5pAaWW5YtkJARhM9XHp9WsUUwmGf2x1D4UhDen3uY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49805+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621013453239.6593190888501; Fri, 1 Nov 2019 08:10:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:12 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5161.1572621011267459384 for ; Fri, 01 Nov 2019 08:10:11 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194686957" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:02 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12] MdeModulePkg/PciBusDxe:New PCI features separation with PCD Date: Fri, 1 Nov 2019 20:39:41 +0530 Message-Id: <20191101150952.3340-2-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621012; bh=RyHOux6QsgbObHyheDGQjx0hzYpmz9Ugvs1a9YTKTP8=; h=Cc:Date:From:Reply-To:Subject:To; b=EnlbKV2/X1JqzqPoOw+oib3A3sM2TwOy3LjZ3BYUyUUjJ+WxGx+WsP7AN4CMNFiShwn BGOREWqCuGDLtkxyawmYxAALfHq7Ok0+8x/UMkqnwAPLmJWAdli7+hSeUkAfR7EwvcKQ6 RGO3/Ytf98px6WsWJ/c3z7DCtatV7vlatZs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 Definition of bit masks for the new PCD for the following new PCI feature set:- 1. Maximum Payload Size (MPS) 2. Maximum Read Request Size (MRRS) 3. Completion Timeout (CTO) 4. Relax Order (RO) Enable 5. No Snoop (NS) Enable 6. Extended Tag 7. ASPM support 8. Common Clock Configuration 9. Extended SYNC 10. Atomic Op 11. LTR Enable 12. PTM support Code changes made to the PCI Bus driver to adopt to these new PCD defini- tion, helper routines defined for features that needs to be supported in. future. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 5 ++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 177 +++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 26 +++++++++++++++++= +++++++++ MdeModulePkg/MdeModulePkg.dec | 22 +++++++++++++++++= +++++ 4 files changed, 229 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index 05c2202..6dab970 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -2,7 +2,7 @@ # The PCI bus driver will probe all PCI devices and allocate MMIO and IO = space for these devices. # Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable hot= plug supporting. # -# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -57,6 +57,8 @@ PciCommand.h PciIo.h PciBus.h + PciFeatureSupport.c + PciFeatureSupport.h =20 [Packages] MdePkg/MdePkg.dec @@ -104,6 +106,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## SOMETIM= ES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdOtherPciFeatures ## CONSUMES =20 [UserExtensions.TianoCore."ExtraFiles"] PciBusDxeExtra.uni diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c new file mode 100644 index 0000000..8be227a --- /dev/null +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -0,0 +1,177 @@ +/** @file + PCI standard feature support functions implementation for PCI Bus module= .. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PciBus.h" +#include "PciFeatureSupport.h" + +/** + Main routine to indicate whether the platform has selected the Max_Paylo= ad_Size + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Max_Payload_Size to be configu= red + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupMaxPayloadSize ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_MPS) ?= TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the Max_Read_= Req_Size + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Max_Read_Req_Size to be config= ured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupMaxReadReqSize ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_MRRS) = ? TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the Relax Ord= ering + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Relax Ordering to be configured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupRelaxOrder ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_RO) ? = TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the No-Snoop + PCI feature to be configured by this driver + + @retval TRUE platform has selected the No-Snoop to be configured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupNoSnoop ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_NS) ? = TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the Completio= n Timeout + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Completion Timeout to be confi= gured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupCompletionTimeout ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_CTO) ?= TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the Extended = Tag + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Completion Timeout to be confi= gured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupExtendedTag ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_ETAG) = ? TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the Atomic Op + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Completion Timeout to be confi= gured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupAtomicOp ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_AOP) ?= TRUE : FALSE; +} +/** + Main routine to indicate whether the platform has selected the LTR + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Completion Timeout to be confi= gured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupLtr ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_LTR) ?= TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the ASPM state + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Completion Timeout to be confi= gured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupAspm ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_ASPM) = ? TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the Common Cl= ock Configuration + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Completion Timeout to be confi= gured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupCommonClkCfg ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_CCC) ?= TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the Extended = Synch + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Completion Timeout to be confi= gured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupExtendedSynch ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_ESYN) = ? TRUE : FALSE; +} + +/** + Main routine to indicate whether the platform has selected the PIM Contr= ol + PCI feature to be configured by this driver + + @retval TRUE platform has selected the Completion Timeout to be confi= gured + FALSE platform has not selected this feature +**/ +BOOLEAN +SetupPtm ( + ) +{ + return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_PTM) ?= TRUE : FALSE; +} diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h new file mode 100644 index 0000000..d06a5e8 --- /dev/null +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -0,0 +1,26 @@ +/** @file + PCI standard feature support functions implementation for PCI Bus module= .. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _EFI_PCI_FEATURES_SUPPORT_H_ +#define _EFI_PCI_FEATURES_SUPPORT_H_ +// +// Macro definitions for the PCI Features support PCD +// +#define PCI_FEATURE_SUPPORT_FLAG_MPS BIT0 +#define PCI_FEATURE_SUPPORT_FLAG_MRRS BIT1 +#define PCI_FEATURE_SUPPORT_FLAG_RO BIT2 +#define PCI_FEATURE_SUPPORT_FLAG_NS BIT3 +#define PCI_FEATURE_SUPPORT_FLAG_CTO BIT4 +#define PCI_FEATURE_SUPPORT_FLAG_ETAG BIT5 +#define PCI_FEATURE_SUPPORT_FLAG_AOP BIT6 +#define PCI_FEATURE_SUPPORT_FLAG_LTR BIT7 +#define PCI_FEATURE_SUPPORT_FLAG_ASPM BIT12 +#define PCI_FEATURE_SUPPORT_FLAG_CCC BIT13 +#define PCI_FEATURE_SUPPORT_FLAG_ESYN BIT14 +#define PCI_FEATURE_SUPPORT_FLAG_PTM BIT20 +#endif diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 12e0bbf..ed82e85 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -1036,6 +1036,28 @@ # @Prompt Enable UEFI Stack Guard. gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard|FALSE|BOOLEAN|0x30001055 =20 + ## This PCD is to indicate the PCI Bus driver to setup other new PCI fea= tures. + # Each PCI feature is represented by its mask bit position and it confi= gures + # if that bit is set. + # + # Bit 0 - if set, the PCI Bus driver programs the device's Max_Payload= _Size.
+ # Bit 1 - if set, the PCI Bus driver programs the device's Max_Read_Re= q_Size.
+ # Bit 2 - if set, the PCI Bus driver programs the device's Relax Order= ing state.
+ # Bit 3 - if set, the PCI Bus driver programs the device's No-Snoop st= ate.
+ # Bit 4 - if set, the PCI Bus driver programs the device's Completion = Timeout range.
+ # Bit 5 - if set, the PCI Bus driver programs the device's Extended Ta= g range.
+ # Bit 6 - if set, the PCI Bus driver programs the device's AtomicOp fe= ature.
+ # Bit 7 - if set, the PCI Bus driver programs the device's LTR feature= .
+ # Bit 8 to 11 - Reserved for future use by the PCI Bus driver.
+ # Bit 12 - if set, the PCI Bus driver programs the PCIe link ASPM stat= e.
+ # Bit 13 - if set, the PCI Bus driver programs the PCIe link Common Cl= ock Configuration.
+ # Bit 14 - if set, the PCI Bus driver programs the PCIe link Extended = Synch state.
+ # Bit 15 to 19 - Reserved for future use by the PCI Bus driver.
+ # Bit 20 - if set, the PCI Bus driver programs the device's PTM featur= e.
+ # Bit 21 to 31 - Reserved for future use by the PCI Bus driver.
+ # @Prompt The UEFI PCI Bus driver enables the new set of other PCI Featu= res. + gEfiMdeModulePkgTokenSpaceGuid.PcdOtherPciFeatures|0x001070FF|UINT32|0x3= 0001056 + [PcdsFixedAtBuild, PcdsPatchableInModule] ## Dynamic type PCD can be registered callback function for Pcd setting = action. # PcdMaxPeiPcdCallBackNumberPerPcdEntry indicates the maximum number of= callback function --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49805): https://edk2.groups.io/g/devel/message/49805 Mute This Topic: https://groups.io/mt/40419681/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49807+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49807+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621014; cv=none; d=zoho.com; s=zohoarc; b=QT0FkiMndq/ARPcXzunJLz/z4wvZOyfo5gyLKi4TXi8HMU3Hpn43AvJWeansIbZTj1317fQK/sYghywtyfxrQ2Qj5KY5RTwqCThqTppaHS/yT3T1U6AIUC1l/wyXNoxUHrVMs/1lEx4h457mKsnsAe3PeDKf5rY9mR5YKoBaZMI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621014; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=PrMQE7rYWAm8Cn9Z7sp14TxIARkLgXOtw+1SJVIhzd0=; b=T1AOzfYOCQRdi3lmTKSdEmpo3Drhy05ad1EPNGjon2pGL303WZsNwRZxFmbUpDq5h3LdOol8jkAakDwH/pm86AmB977nrfHl+gcH50wnoioJiS9hvJvyDHlfYepXgEyilttTV1N6Z5stcnKp74HW4l49KPExmtehyML5RUKBVK8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49807+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621014366287.99970775361544; Fri, 1 Nov 2019 08:10:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:13 -0700 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web11.5030.1572621012589427381 for ; Fri, 01 Nov 2019 08:10:12 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687009" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:04 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12] PciBusDxe: Reorganize the PCI Platform Protocol usage code Date: Fri, 1 Nov 2019 20:39:42 +0530 Message-Id: <20191101150952.3340-3-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621013; bh=8lPjuZ3hiQaIQiDKRokZFt0c5/828BWrxhesoglkBFA=; h=Cc:Date:From:Reply-To:Subject:To; b=mqB1ryYgIN/5swu1T65nQfeiKyhPtCh5LScQjwLDrDSfrc7+akAUJE/MV735/iPFgfj Cfumo323gBiZHOQdqZ77sWDZv80BACDJOnNZ4+YjbY1rzrH82SrXPDsHQbqyDl3dvHOsF HXkJojTrtrXlqPtAxAhKOMZy9+/D7TAZItU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The following legacy PCI Platform Protocol usage is reorganized in the separate source files:- (1) PlatformPrepController (2) PlatformNotify (3) GetPlatformPolicy (4) GetPciRom This code changes are made to support the new PCI Platform Protocol along with the existing legacy interface in the PCI Bus driver. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 23 ++--------------= ------- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 3 +-- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 2 ++ MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 58 +++++++++++-----= ------------------------------------------ MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c | 139 ++++++++++++++++= +++++++++++++++++----------------------------------------------------------= ------------------------------------------------ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 254 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 109 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 15 +-------------- 8 files changed, 413 insertions(+), 190 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.c index b020ce5..45cd64d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c @@ -8,7 +8,7 @@ PCI Root Bridges. So it means platform needs install PCI Root Bridge IO = protocol for each PCI Root Bus and install PCI Host Bridge Resource Allocation Protocol. =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -34,8 +34,6 @@ BOOLEAN gFullEnumer= ation =3D TRUE; UINT64 gAllOne =3D 0xF= FFFFFFFFFFFFFFFULL; UINT64 gAllZero =3D 0; =20 -EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; -EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; EDKII_IOMMU_PROTOCOL *mIoMmuProtocol; =20 =20 @@ -266,24 +264,7 @@ PciBusDriverBindingStart ( // If PCI Platform protocol is available, get it now. // If the platform implements this, it must be installed before BDS phase // - gPciPlatformProtocol =3D NULL; - gBS->LocateProtocol ( - &gEfiPciPlatformProtocolGuid, - NULL, - (VOID **) &gPciPlatformProtocol - ); - - // - // If PCI Platform protocol doesn't exist, try to Pci Override Protocol. - // - if (gPciPlatformProtocol =3D=3D NULL) { - gPciOverrideProtocol =3D NULL; - gBS->LocateProtocol ( - &gEfiPciOverrideProtocolGuid, - NULL, - (VOID **) &gPciOverrideProtocol - ); - } + LocatePciPlatformProtocol (); =20 if (mIoMmuProtocol =3D=3D NULL) { gBS->LocateProtocol ( diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 504a1b1..141c158 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -79,6 +79,7 @@ typedef enum { #include "PciPowerManagement.h" #include "PciHotPlugSupport.h" #include "PciLib.h" +#include "PciPlatformSupport.h" =20 #define VGABASE1 0x3B0 #define VGALIMIT1 0x3BB @@ -307,8 +308,6 @@ extern UINTN gPc= iHostBridgeNumber; extern EFI_HANDLE gPciHostBrigeHandles[P= CI_MAX_HOST_BRIDGE_NUM]; extern UINT64 gAllOne; extern UINT64 gAllZero; -extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; -extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; extern BOOLEAN mReserveIsaAliases; extern BOOLEAN mReserveVgaAliases; =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index 6dab970..4ce99ce 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -59,6 +59,8 @@ PciBus.h PciFeatureSupport.c PciFeatureSupport.h + PciPlatformSupport.c + PciPlatformSupport.h =20 [Packages] MdePkg/MdePkg.dec diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModuleP= kg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index b7832c6..149a120 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -208,8 +208,6 @@ RegisterPciDevice ( ) { EFI_STATUS Status; - VOID *PlatformOpRomBuffer; - UINTN PlatformOpRomSize; EFI_PCI_IO_PROTOCOL *PciIo; UINT8 Data8; BOOLEAN HasEfiImage; @@ -244,49 +242,16 @@ RegisterPciDevice ( // // Get the OpRom provided by platform // - if (gPciPlatformProtocol !=3D NULL) { - Status =3D gPciPlatformProtocol->GetPciRom ( - gPciPlatformProtocol, - PciIoDevice->Handle, - &PlatformOpRomBuffer, - &PlatformOpRomSize - ); - if (!EFI_ERROR (Status)) { - PciIoDevice->EmbeddedRom =3D FALSE; - PciIoDevice->RomSize =3D (UINT32) PlatformOpRomSize; - PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; - PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; - // - // For OpROM read from gPciPlatformProtocol: - // Add the Rom Image to internal database for later PCI light enum= eration - // - PciRomAddImageMapping ( - NULL, - PciIoDevice->PciRootBridgeIo->SegmentNumber, - PciIoDevice->BusNumber, - PciIoDevice->DeviceNumber, - PciIoDevice->FunctionNumber, - PciIoDevice->PciIo.RomImage, - PciIoDevice->PciIo.RomSize - ); - } - } else if (gPciOverrideProtocol !=3D NULL) { - Status =3D gPciOverrideProtocol->GetPciRom ( - gPciOverrideProtocol, - PciIoDevice->Handle, - &PlatformOpRomBuffer, - &PlatformOpRomSize - ); - if (!EFI_ERROR (Status)) { - PciIoDevice->EmbeddedRom =3D FALSE; - PciIoDevice->RomSize =3D (UINT32) PlatformOpRomSize; - PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; - PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; - // - // For OpROM read from gPciOverrideProtocol: - // Add the Rom Image to internal database for later PCI light enum= eration - // - PciRomAddImageMapping ( + Status =3D GetPlatformPciOptionRom ( + Controller, + PciIoDevice + ); + if (!EFI_ERROR (Status)) { + // + // For OpROM read from the PCI Platform Protocol: + // Add the Rom Image to internal database for later PCI light enumer= ation + // + PciRomAddImageMapping ( NULL, PciIoDevice->PciRootBridgeIo->SegmentNumber, PciIoDevice->BusNumber, @@ -294,8 +259,7 @@ RegisterPciDevice ( PciIoDevice->FunctionNumber, PciIoDevice->PciIo.RomImage, PciIoDevice->PciIo.RomSize - ); - } + ); } } =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c b/MdeModulePkg/= Bus/Pci/PciBusDxe/PciEnumerator.c index 8db1ebf..aef8a3b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumerator.c @@ -1003,7 +1003,7 @@ PciHostBridgeAdjustAllocation ( Status =3D RejectPciDevice (PciResNode->PciDev); if (Status =3D=3D EFI_SUCCESS) { DEBUG (( - EFI_D_ERROR, + DEBUG_ERROR, "PciBus: [%02x|%02x|%02x] was rejected due to resource confliction= .\n", PciResNode->PciDev->BusNumber, PciResNode->PciDev->DeviceNumber, P= ciResNode->PciDev->FunctionNumber )); @@ -1746,7 +1746,7 @@ NotifyPhase ( =20 HostBridgeHandle =3D NULL; RootBridgeHandle =3D NULL; - if (gPciPlatformProtocol !=3D NULL) { + if (CheckPciPlatformProtocolInstall()) { // // Get Host Bridge Handle. // @@ -1770,42 +1770,11 @@ NotifyPhase ( // // Call PlatformPci::PlatformNotify() if the protocol is present. // - gPciPlatformProtocol->PlatformNotify ( - gPciPlatformProtocol, - HostBridgeHandle, - Phase, - ChipsetEntry - ); - } else if (gPciOverrideProtocol !=3D NULL){ - // - // Get Host Bridge Handle. - // - PciResAlloc->GetNextRootBridge (PciResAlloc, &RootBridgeHandle); - - // - // Get the rootbridge Io protocol to find the host bridge handle - // - Status =3D gBS->HandleProtocol ( - RootBridgeHandle, - &gEfiPciRootBridgeIoProtocolGuid, - (VOID **) &PciRootBridgeIo - ); - - if (EFI_ERROR (Status)) { - return EFI_NOT_FOUND; - } - - HostBridgeHandle =3D PciRootBridgeIo->ParentHandle; - - // - // Call PlatformPci::PhaseNotify() if the protocol is present. - // - gPciOverrideProtocol->PlatformNotify ( - gPciOverrideProtocol, - HostBridgeHandle, - Phase, - ChipsetEntry - ); + PciPlatformNotifyPhase ( + HostBridgeHandle, + Phase, + ChipsetEntry + ); } =20 Status =3D PciResAlloc->NotifyPhase ( @@ -1813,27 +1782,15 @@ NotifyPhase ( Phase ); =20 - if (gPciPlatformProtocol !=3D NULL) { + if (CheckPciPlatformProtocolInstall()) { // // Call PlatformPci::PlatformNotify() if the protocol is present. // - gPciPlatformProtocol->PlatformNotify ( - gPciPlatformProtocol, - HostBridgeHandle, - Phase, - ChipsetExit - ); - - } else if (gPciOverrideProtocol !=3D NULL) { - // - // Call PlatformPci::PhaseNotify() if the protocol is present. - // - gPciOverrideProtocol->PlatformNotify ( - gPciOverrideProtocol, - HostBridgeHandle, - Phase, - ChipsetExit - ); + PciPlatformNotifyPhase ( + HostBridgeHandle, + Phase, + ChipsetExit + ); } =20 return Status; @@ -1914,31 +1871,16 @@ PreprocessController ( RootBridgePciAddress.Bus =3D Bus; RootBridgePciAddress.ExtendedRegister =3D 0; =20 - if (gPciPlatformProtocol !=3D NULL) { - // - // Call PlatformPci::PrepController() if the protocol is present. - // - gPciPlatformProtocol->PlatformPrepController ( - gPciPlatformProtocol, - HostBridgeHandle, - RootBridgeHandle, - RootBridgePciAddress, - Phase, - ChipsetEntry - ); - } else if (gPciOverrideProtocol !=3D NULL) { - // - // Call PlatformPci::PrepController() if the protocol is present. - // - gPciOverrideProtocol->PlatformPrepController ( - gPciOverrideProtocol, - HostBridgeHandle, - RootBridgeHandle, - RootBridgePciAddress, - Phase, - ChipsetEntry - ); - } + // + // Call PlatformPci::PrepController() if the protocol is present. + // + PciPlatformPreprocessController ( + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ChipsetEntry + ); =20 Status =3D PciResAlloc->PreprocessController ( PciResAlloc, @@ -1947,31 +1889,16 @@ PreprocessController ( Phase ); =20 - if (gPciPlatformProtocol !=3D NULL) { - // - // Call PlatformPci::PrepController() if the protocol is present. - // - gPciPlatformProtocol->PlatformPrepController ( - gPciPlatformProtocol, - HostBridgeHandle, - RootBridgeHandle, - RootBridgePciAddress, - Phase, - ChipsetExit - ); - } else if (gPciOverrideProtocol !=3D NULL) { - // - // Call PlatformPci::PrepController() if the protocol is present. - // - gPciOverrideProtocol->PlatformPrepController ( - gPciOverrideProtocol, - HostBridgeHandle, - RootBridgeHandle, - RootBridgePciAddress, - Phase, - ChipsetExit - ); - } + // + // Call PlatformPci::PrepController() if the protocol is present. + // + PciPlatformPreprocessController ( + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ChipsetExit + ); =20 return EFI_SUCCESS; } diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c new file mode 100644 index 0000000..6f95794 --- /dev/null +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -0,0 +1,254 @@ +/** @file + This file encapsulate the usage of PCI Platform Protocol + + This file define the necessary hooks used to obtain the platform + level data and policies which could be used in the PCI Enumeration phases + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PciBus.h" + +EFI_PCI_PLATFORM_PROTOCOL *mPciPlatformProtocol; +EFI_PCI_OVERRIDE_PROTOCOL *mPciOverrideProtocol; + + + +/** + This function retrieves the PCI Platform Protocol published by platform = driver + +**/ +VOID +LocatePciPlatformProtocol ( + ) +{ + mPciPlatformProtocol =3D NULL; + gBS->LocateProtocol ( + &gEfiPciPlatformProtocolGuid, + NULL, + (VOID **) &mPciPlatformProtocol + ); + + // + // If PCI Platform protocol doesn't exist, try to get Pci Override Pr= otocol. + // + if (mPciPlatformProtocol =3D=3D NULL) { + mPciOverrideProtocol =3D NULL; + gBS->LocateProtocol ( + &gEfiPciOverrideProtocolGuid, + NULL, + (VOID **) &mPciOverrideProtocol + ); + } +} + +/** + This function indicates the presence of PCI Platform driver + @retval TRUE or FALSE +**/ +BOOLEAN +CheckPciPlatformProtocolInstall ( + ) +{ + + if (mPciPlatformProtocol !=3D NULL) { + return TRUE; + } else if (mPciOverrideProtocol !=3D NULL){ + return TRUE; + } + + return FALSE; +} + +/** + Provides the hooks from the PCI bus driver to every PCI controller (devi= ce/function) at various + stages of the PCI enumeration process that allow the host bridge driver = to preinitialize individual + PCI controllers before enumeration. + + This function is called during the PCI enumeration process. No specific = action is expected from this + member function. It allows the host bridge driver to preinitialize indiv= idual PCI controllers before + enumeration. + + @param[in] HostBridgeHandle The associated PCI host bridge handle. + @param[in] RootBridgeHandle The associated PCI root bridge handle. + @param[in] RootBridgePciAddress The address of the PCI device on the PCI= bus. + @param[in] Phase The phase of the PCI controller enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset= driver. + + @retval Status returns the status from the PCI Platform proto= col as is + +**/ +EFI_STATUS +PciPlatformPreprocessController ( + IN EFI_HANDLE HostBridgeHandle, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ) +{ + EFI_STATUS Status; + if (mPciPlatformProtocol !=3D NULL) { + // + // Call PlatformPci::PrepController() if the protocol is present. + // + Status =3D mPciPlatformProtocol->PlatformPrepController ( + mPciPlatformProtocol, + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ExecPhase + ); + } else if (mPciOverrideProtocol !=3D NULL) { + // + // Call PlatformPci::PrepController() if the protocol is present. + // + Status =3D mPciOverrideProtocol->PlatformPrepController ( + mPciOverrideProtocol, + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ExecPhase + ); + } else { + // + // return PCI Platform Protocol not found + // + return EFI_NOT_FOUND; + } + return Status; +} + +/** + This function notifies the PCI Platform driver about the PCI host bridge= resource + allocation phase and PCI execution phase. + + @param[in] HostBridge The handle of the host bridge controller. + @param[in] Phase The phase of the PCI bus enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipse= t driver. + @retval Status returns the status from the PCI Platform pro= tocol as is + +**/ +EFI_STATUS +PciPlatformNotifyPhase ( + IN EFI_HANDLE HostBridgeHandle, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ) +{ + EFI_STATUS Status; + + + if (mPciPlatformProtocol !=3D NULL) { + Status =3D mPciPlatformProtocol->PlatformNotify ( + mPciPlatformProtocol, + HostBridgeHandle, + Phase, + ExecPhase + ); + } else if (mPciOverrideProtocol !=3D NULL){ + Status =3D mPciOverrideProtocol->PlatformNotify ( + mPciOverrideProtocol, + HostBridgeHandle, + Phase, + ExecPhase + ); + } else { + // + // return PCI Platform Protocol not found + // + return EFI_NOT_FOUND; + } + return Status; +} + +/** + This function retrieves the PCI platform policy. + + @param PciPolicy pointer to the legacy EFI_PCI_PLATFORM_POLICY + @retval Status returns the status from the PCI Platform protocol = as is + +**/ +EFI_STATUS +PciGetPlatformPolicy ( + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + EFI_STATUS Status; + if (mPciPlatformProtocol !=3D NULL) { + Status =3D mPciPlatformProtocol->GetPlatformPolicy ( + mPciPlatformProtocol, + PciPolicy + ); + } + + if (mPciOverrideProtocol !=3D NULL) { + Status =3D mPciOverrideProtocol->GetPlatformPolicy ( + mPciOverrideProtocol, + PciPolicy + ); + } else { + // + // return PCI Platform Protocol not found + // + return EFI_NOT_FOUND; + } + return Status; +} + +/** + This function retrieves the Option ROM image and size from the Platform. + + It uses the PCI_IO_DEVICE internal fields are used to store OpROM image/= size + + @param Controller An EFI handle for the PCI bus controller. + @param PciIoDevice A PCI_IO_DEVICE pointer to the PCI IO device to be= registered. + + @retval EFI_SUCCESS The option ROM was available for this dev= ice and loaded into memory. + @retval EFI_NOT_FOUND No option ROM was available for this devi= ce. + @retval EFI_OUT_OF_RESOURCES No memory was available to load the optio= n ROM. + @retval EFI_DEVICE_ERROR An error occurred in obtaining the option= ROM. + +**/ +EFI_STATUS +GetPlatformPciOptionRom ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *PciIoDevice + ) +{ + EFI_STATUS Status; + VOID *PlatformOpRomBuffer; + UINTN PlatformOpRomSize; + if (mPciPlatformProtocol !=3D NULL) { + Status =3D mPciPlatformProtocol->GetPciRom ( + mPciPlatformProtocol, + PciIoDevice->Handle, + &PlatformOpRomBuffer, + &PlatformOpRomSize + ); + } else if (mPciOverrideProtocol !=3D NULL) { + Status =3D mPciOverrideProtocol->GetPciRom ( + mPciOverrideProtocol, + PciIoDevice->Handle, + &PlatformOpRomBuffer, + &PlatformOpRomSize + ); + } else { + // + // return PCI Platform Protocol not found + // + return EFI_NOT_FOUND; + } + + if (!EFI_ERROR (Status)) { + PciIoDevice->EmbeddedRom =3D FALSE; + PciIoDevice->RomSize =3D (UINT32)PlatformOpRomSize; + PciIoDevice->PciIo.RomSize =3D PlatformOpRomSize; + PciIoDevice->PciIo.RomImage =3D PlatformOpRomBuffer; + } + return Status; +} diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h new file mode 100644 index 0000000..c0d3b49 --- /dev/null +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h @@ -0,0 +1,109 @@ +/** @file + This file encapsulate the usage of PCI Platform Protocol + + This file define the necessary hooks used to obtain the platform + level data and policies which could be used in the PCI Enumeration phases + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _EFI_PCI_PLATFORM_SUPPORT_H_ +#define _EFI_PCI_PLATFORM_SUPPORT_H_ + +/** + This function retrieves the PCI Platform Protocol published by platform = driver + +**/ +VOID +LocatePciPlatformProtocol ( + ); + +/** + This function indicates the presence of PCI Platform driver + @retval TRUE or FALSE +**/ +BOOLEAN +CheckPciPlatformProtocolInstall ( + ); + + +/** + Provides the hooks from the PCI bus driver to every PCI controller (devi= ce/function) at various + stages of the PCI enumeration process that allow the host bridge driver = to preinitialize individual + PCI controllers before enumeration. + + This function is called during the PCI enumeration process. No specific = action is expected from this + member function. It allows the host bridge driver to preinitialize indiv= idual PCI controllers before + enumeration. + + @param[in] HostBridgeHandle The associated PCI host bridge handle. + @param[in] RootBridgeHandle The associated PCI root bridge handle. + @param[in] RootBridgePciAddress The address of the PCI device on the PCI= bus. + @param[in] Phase The phase of the PCI controller enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipset= driver. + + @retval Status returns the status from the PCI Platform proto= col as is + +**/ +EFI_STATUS +PciPlatformPreprocessController ( + IN EFI_HANDLE HostBridgeHandle, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS RootBridgePciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ); + +/** + This function notifies the PCI Platform driver about the PCI host bridge= resource + allocation phase and PCI execution phase. + + @param[in] HostBridge The handle of the host bridge controller. + @param[in] Phase The phase of the PCI bus enumeration. + @param[in] ExecPhase Defines the execution phase of the PCI chipse= t driver. + @retval Status returns the status from the PCI Platform pro= tocol as is + +**/ +EFI_STATUS +PciPlatformNotifyPhase ( + IN EFI_HANDLE HostBridgeHandle, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_EXECUTION_PHASE ExecPhase + ); + +/** + This function retrieves the PCI platform policy. + + @param PciPolicy pointer to the legacy EFI_PCI_PLATFORM_POLICY + @retval Status returns the status from the PCI Platform protocol = as is + +**/ +EFI_STATUS +PciGetPlatformPolicy ( + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ); + +/** + This function retrieves the Option ROM image and size from the Platform. + + It uses the PCI_IO_DEVICE internal fields are used to store OpROM image/= size + + @param Controller An EFI handle for the PCI bus controller. + @param PciIoDevice A PCI_IO_DEVICE pointer to the PCI IO device to be= registered. + + @retval EFI_SUCCESS The option ROM was available for this dev= ice and loaded into memory. + @retval EFI_NOT_FOUND No option ROM was available for this devi= ce. + @retval EFI_OUT_OF_RESOURCES No memory was available to load the optio= n ROM. + @retval EFI_DEVICE_ERROR An error occurred in obtaining the option= ROM. + +**/ +EFI_STATUS +GetPlatformPciOptionRom ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *PciIoDevice + ); + +#endif diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index 4969ee0..be6f42a 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -198,20 +198,7 @@ CalculateApertureIo16 ( // Status =3D EFI_NOT_FOUND; PciPolicy =3D 0; - if (gPciPlatformProtocol !=3D NULL) { - Status =3D gPciPlatformProtocol->GetPlatformPolicy ( - gPciPlatformProtocol, - &PciPolicy - ); - } - - if (EFI_ERROR (Status) && gPciOverrideProtocol !=3D NULL) { - Status =3D gPciOverrideProtocol->GetPlatformPolicy ( - gPciOverrideProtocol, - &PciPolicy - ); - } - + Status =3D PciGetPlatformPolicy (&PciPolicy); if (!EFI_ERROR (Status)) { if ((PciPolicy & EFI_RESERVE_ISA_IO_ALIAS) !=3D 0) { mReserveIsaAliases =3D TRUE; --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49807): https://edk2.groups.io/g/devel/message/49807 Mute This Topic: https://groups.io/mt/40419684/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49806+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49806+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621013; cv=none; d=zoho.com; s=zohoarc; b=RR8hkyBD2yUSfaYsSE6/6U8/MLmUkTvnsVltUoK01RUUDY53zJbppw82TSqEANkJpb729FwUpGJ37QXr1PMKtTjmoPr3xYWPCYWkvvAWq+3AXQE5TQBzdIJ8klSzmNwKNF62/7/7vKlt0iErmwZaaRsZ6RFKm2g2ZKBDdbV21Jk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621013; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6bX3YafHNZaR+BSzJN0KH1j4L712uS03RICjiIZ72O4=; b=N0qritToEGKbLWxCG4cO/FnuMpOs8lCFcesR9WSKN8e/3df0zl3RJQN1lbx9eAXEtPOjCNVIHE5tp8BqDSeQouu6+a/PFh0SAvBOo0bIO0h5RsfMbLZVaTs/oYmufTSoWNzbp1HzsWyMwluLa4n02/xxaRiJ5YIpcH0vbZVK2WA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49806+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621013916287.1909581888109; Fri, 1 Nov 2019 08:10:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:12 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5161.1572621011267459384 for ; Fri, 01 Nov 2019 08:10:12 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687034" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:07 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 03/12] PciBusDxe: Separation of the PCI device registration and start Date: Fri, 1 Nov 2019 20:39:43 +0530 Message-Id: <20191101150952.3340-4-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621012; bh=K8NtiL4nN4trqE7vf1IOxawEV8leq2l7jhSkzWzJh6M=; h=Cc:Date:From:Reply-To:Subject:To; b=AzWHxtDs4VSpq+LABLtcjdHrW5uscoerl6puhka5ZJ+v+bbvzvrKzanvb+jlwttNblJ LKtk/uQ1gkWuqdVe9cHyon1b950klVCQ3WbEGlZ3dPU6YuEbw8MtNcfmgxbRdk5a3H4t2 x9RyiVwKnIhU+PuQxFtj4yE/Gfo11crtdhk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The separation of the PCI device registration phase includes only the installation of the PCI IO Protocol on the PCI node to acquire the EFI handles, and loading of its applicable PCI Option ROM. The separation of the PCI device start phase only includes the code that enables the PCI Bridge device as a Bus Master. This code change is made in order to introduce the enabling of the other PCI features in the PCI Bus driver. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 164 ++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++---------------------------------- 1 file changed, 130 insertions(+), 34 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModuleP= kg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index 149a120..33a0e94 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -561,7 +561,7 @@ DeRegisterPciDevice ( } =20 /** - Start to manage the PCI device on the specified root bridge or PCI-PCI B= ridge. + Start the PCI root Ports or PCI-PCI Bridge only. =20 @param Controller The root bridge handle. @param RootBridge A pointer to the PCI_IO_DEVICE. @@ -576,7 +576,82 @@ DeRegisterPciDevice ( =20 **/ EFI_STATUS -StartPciDevicesOnBridge ( +StartPciRootPortsOnBridge ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *RootBridge + ) + +{ + PCI_IO_DEVICE *PciIoDevice; + EFI_STATUS Status; + LIST_ENTRY *CurrentLink; + UINT64 Supports; + + PciIoDevice =3D NULL; + CurrentLink =3D RootBridge->ChildList.ForwardLink; + + while (CurrentLink !=3D NULL && CurrentLink !=3D &RootBridge->ChildList)= { + + PciIoDevice =3D PCI_IO_DEVICE_FROM_LINK (CurrentLink); + + // + // check if the device has been assigned with required resource + // and registered + // + if (!PciIoDevice->Registered && !PciIoDevice->Allocated) { + return EFI_NOT_READY; + } + + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { + Status =3D StartPciRootPortsOnBridge ( + Controller, + PciIoDevice + ); + + PciIoDevice->PciIo.Attributes ( + &(PciIoDevice->PciIo), + EfiPciIoAttributeOperationSupported, + 0, + &Supports + ); + Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; + PciIoDevice->PciIo.Attributes ( + &(PciIoDevice->PciIo), + EfiPciIoAttributeOperationEnable, + Supports, + NULL + ); + + } + + CurrentLink =3D CurrentLink->ForwardLink; + } + + if (PciIoDevice =3D=3D NULL) { + return EFI_NOT_FOUND; + } else { + return EFI_SUCCESS; + } +} + + +/** + Register to manage the PCI device on the specified root bridge or PCI-PC= I Bridge. + + @param Controller The root bridge handle. + @param RootBridge A pointer to the PCI_IO_DEVICE. + @param RemainingDevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL. + @param NumberOfChildren Children number. + @param ChildHandleBuffer A pointer to the child handle buffer. + + @retval EFI_NOT_READY Device is not allocated. + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge. + @retval EFI_NOT_FOUND Can not find the specific device. + @retval EFI_SUCCESS Success to start Pci devices on bridge. + +**/ +EFI_STATUS +RegisterPciDevicesOnBridge ( IN EFI_HANDLE Controller, IN PCI_IO_DEVICE *RootBridge, IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, @@ -590,7 +665,6 @@ StartPciDevicesOnBridge ( EFI_DEVICE_PATH_PROTOCOL *CurrentDevicePath; EFI_STATUS Status; LIST_ENTRY *CurrentLink; - UINT64 Supports; =20 PciIoDevice =3D NULL; CurrentLink =3D RootBridge->ChildList.ForwardLink; @@ -645,7 +719,7 @@ StartPciDevicesOnBridge ( // If it is a PPB // if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { - Status =3D StartPciDevicesOnBridge ( + Status =3D RegisterPciDevicesOnBridge ( Controller, PciIoDevice, CurrentDevicePath, @@ -653,20 +727,6 @@ StartPciDevicesOnBridge ( ChildHandleBuffer ); =20 - PciIoDevice->PciIo.Attributes ( - &(PciIoDevice->PciIo), - EfiPciIoAttributeOperationSupported, - 0, - &Supports - ); - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; - PciIoDevice->PciIo.Attributes ( - &(PciIoDevice->PciIo), - EfiPciIoAttributeOperationEnable, - Supports, - NULL - ); - return Status; } else { =20 @@ -697,28 +757,13 @@ StartPciDevicesOnBridge ( } =20 if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { - Status =3D StartPciDevicesOnBridge ( + Status =3D RegisterPciDevicesOnBridge ( Controller, PciIoDevice, RemainingDevicePath, NumberOfChildren, ChildHandleBuffer ); - - PciIoDevice->PciIo.Attributes ( - &(PciIoDevice->PciIo), - EfiPciIoAttributeOperationSupported, - 0, - &Supports - ); - Supports &=3D (UINT64)EFI_PCI_DEVICE_ENABLE; - PciIoDevice->PciIo.Attributes ( - &(PciIoDevice->PciIo), - EfiPciIoAttributeOperationEnable, - Supports, - NULL - ); - } =20 CurrentLink =3D CurrentLink->ForwardLink; @@ -732,6 +777,57 @@ StartPciDevicesOnBridge ( } } =20 +/** + Start to manage the PCI device on the specified root bridge or PCI-PCI B= ridge. + + @param Controller The root bridge handle. + @param RootBridge A pointer to the PCI_IO_DEVICE. + @param RemainingDevicePath A pointer to the EFI_DEVICE_PATH_PROTOCOL. + @param NumberOfChildren Children number. + @param ChildHandleBuffer A pointer to the child handle buffer. + + @retval EFI_NOT_READY Device is not allocated. + @retval EFI_UNSUPPORTED Device only support PCI-PCI bridge. + @retval EFI_NOT_FOUND Can not find the specific device. + @retval EFI_SUCCESS Success to start Pci devices on bridge. + +**/ +EFI_STATUS +StartPciDevicesOnBridge ( + IN EFI_HANDLE Controller, + IN PCI_IO_DEVICE *RootBridge, + IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath, + IN OUT UINT8 *NumberOfChildren, + IN OUT EFI_HANDLE *ChildHandleBuffer + ) + +{ + EFI_STATUS Status; + + // + // first register all the PCI devices + // + Status =3D RegisterPciDevicesOnBridge ( + Controller, + RootBridge, + RemainingDevicePath, + NumberOfChildren, + ChildHandleBuffer + ); + + if (EFI_ERROR (Status) =3D=3D EFI_NOT_FOUND) { + return Status; + } else { + // + // finally start those PCI bridge port devices only + // + return StartPciRootPortsOnBridge ( + Controller, + RootBridge + ); + } +} + /** Start to manage all the PCI devices it found previously under the entire host bridge. --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49806): https://edk2.groups.io/g/devel/message/49806 Mute This Topic: https://groups.io/mt/40419682/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49808+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49808+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621013; cv=none; d=zoho.com; s=zohoarc; b=AYjnuOGAHUlFGy7aof76AIteKM/k1j4esVBi+hYgKoJP8lrFdG6GJeIDmAd6nYq/ZO+5s/GL5ewIhRnETJWwE+13LF56/1wnoHZ9Co2vnIUV6zevIxEvJDAWPBUV8THQtoJJsMZFVnCHunyZyV79rwLe98s0/LbIvngGXiA11+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621013; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=hr3z+X4YQRdEVz9CutZotFRuYkmfMyqFcsP/RhZBXfk=; b=RxnWLLEpo1bSmfaxxlXWwgfp+1Ovqj8y7O9BgGNd001WtGO2YNR60kCi5VRqMTX3MFisTKjm8UVwnzx/6Dv0Xk3F4vaHJ5pvSc57Gh68LFx05L1b96GZ8teU7S733RLCqbleN3yJpV9t2Rc+7hMzWI5Tgp+XgyDIjDyNqgq1F98= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49808+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621013707482.7583348168275; Fri, 1 Nov 2019 08:10:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:13 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5161.1572621011267459384 for ; Fri, 01 Nov 2019 08:10:12 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687061" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:10 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 04/12] PciBusDxe: Inclusion of new PCI Platform Protocol 2 Date: Fri, 1 Nov 2019 20:39:44 +0530 Message-Id: <20191101150952.3340-5-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621013; bh=hMybX39Tre4zXDIvGZKgYq55VtcReffju9r0g6U/8e8=; h=Cc:Date:From:Reply-To:Subject:To; b=i5b5+9cPbiR4za4e3+79bX2Tj82ZQE3T479fDqvcy7lRadLWm+cTkx8T7zkkFXGfH+c aK9XOrqcCjunJ2Is4tXgmoirQwPe6yHnTzWFGgDESvpuWHRNk631/1MNgOrMMBZ43XDk3 3OMQN7JwDd7LjvY+0jFYpzIqNkvIkO0Vtj0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The code changes are made to support the new PCI Platform Protocol, as well as the legacy PCI Platform Protocol interfaces. The code change is made to consume the new interface to acquire the PCI device-specific platform policy. This code change is made to support the enabling of the other PCI features in the PCI Bus driver. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 2 ++ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 2 ++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 208 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++-- MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 18 ++++++++++++++++= ++ 4 files changed, 228 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 141c158..95a677b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -27,6 +27,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include +#include =20 #include #include diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index 4ce99ce..44dec53 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -95,6 +95,8 @@ gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES gEdkiiIoMmuProtocolGuid ## SOMETIMES_CONSUMES gEfiLoadedImageDevicePathProtocolGuid ## CONSUMES + gEfiPciPlatformProtocol2Guid ## SOMETIMES_CONSUMES + gEfiPciOverrideProtocol2Guid ## SOMETIMES_CONSUMES =20 [FeaturePcd] gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport ## CON= SUMES diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index 6f95794..238959e 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -14,6 +14,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent EFI_PCI_PLATFORM_PROTOCOL *mPciPlatformProtocol; EFI_PCI_OVERRIDE_PROTOCOL *mPciOverrideProtocol; =20 +EFI_PCI_PLATFORM_PROTOCOL2 *mPciPlatformProtocol2; +EFI_PCI_OVERRIDE_PROTOCOL2 *mPciOverrideProtocol2; =20 =20 /** @@ -24,6 +26,29 @@ VOID LocatePciPlatformProtocol ( ) { + mPciPlatformProtocol2 =3D NULL; + gBS->LocateProtocol ( + &gEfiPciPlatformProtocol2Guid, + NULL, + (VOID **) &mPciPlatformProtocol2 + ); + + // + // If PCI Platform protocol doesn't exist, try to get Pci Override Proto= col. + // + if (mPciPlatformProtocol2 =3D=3D NULL) { + mPciOverrideProtocol2 =3D NULL; + gBS->LocateProtocol ( + &gEfiPciOverrideProtocol2Guid, + NULL, + (VOID **) &mPciOverrideProtocol2 + ); + } + // + // fetch the old PCI Platform Protocols if new are not installed + // + if (mPciOverrideProtocol2 =3D=3D NULL) { + mPciPlatformProtocol =3D NULL; gBS->LocateProtocol ( &gEfiPciPlatformProtocolGuid, @@ -42,6 +67,7 @@ LocatePciPlatformProtocol ( (VOID **) &mPciOverrideProtocol ); } + } } =20 /** @@ -52,13 +78,17 @@ BOOLEAN CheckPciPlatformProtocolInstall ( ) { - + if (mPciPlatformProtocol2 !=3D NULL) { + return TRUE; + } else if (mPciOverrideProtocol2 !=3D NULL) { + return TRUE; + } else { if (mPciPlatformProtocol !=3D NULL) { return TRUE; } else if (mPciOverrideProtocol !=3D NULL){ return TRUE; } - + } return FALSE; } =20 @@ -90,6 +120,32 @@ PciPlatformPreprocessController ( ) { EFI_STATUS Status; + + if (mPciPlatformProtocol2 !=3D NULL) { + // + // Call PlatformPci::PrepController() if the protocol is present. + // + Status =3D mPciPlatformProtocol2->PlatformPrepController ( + mPciPlatformProtocol2, + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ExecPhase + ); + } else if (mPciOverrideProtocol2 !=3D NULL) { + // + // Call PlatformPci::PrepController() if the protocol is present. + // + Status =3D mPciOverrideProtocol2->PlatformPrepController ( + mPciOverrideProtocol2, + HostBridgeHandle, + RootBridgeHandle, + RootBridgePciAddress, + Phase, + ExecPhase + ); + } else { if (mPciPlatformProtocol !=3D NULL) { // // Call PlatformPci::PrepController() if the protocol is present. @@ -120,6 +176,7 @@ PciPlatformPreprocessController ( // return EFI_NOT_FOUND; } + } return Status; } =20 @@ -142,6 +199,21 @@ PciPlatformNotifyPhase ( { EFI_STATUS Status; =20 + if (mPciPlatformProtocol2 !=3D NULL) { + Status =3D mPciPlatformProtocol2->PlatformNotify ( + mPciPlatformProtocol2, + HostBridgeHandle, + Phase, + ExecPhase + ); + } else if (mPciOverrideProtocol2 !=3D NULL) { + Status =3D mPciOverrideProtocol2->PlatformNotify ( + mPciOverrideProtocol2, + HostBridgeHandle, + Phase, + ExecPhase + ); + } else { =20 if (mPciPlatformProtocol !=3D NULL) { Status =3D mPciPlatformProtocol->PlatformNotify ( @@ -163,6 +235,7 @@ PciPlatformNotifyPhase ( // return EFI_NOT_FOUND; } + } return Status; } =20 @@ -179,6 +252,18 @@ PciGetPlatformPolicy ( ) { EFI_STATUS Status; + + if (mPciPlatformProtocol2 !=3D NULL) { + Status =3D mPciPlatformProtocol2->GetPlatformPolicy ( + mPciPlatformProtocol2, + PciPolicy + ); + } else if (mPciOverrideProtocol2 !=3D NULL) { + Status =3D mPciOverrideProtocol2->GetPlatformPolicy ( + mPciOverrideProtocol2, + PciPolicy + ); + } else { if (mPciPlatformProtocol !=3D NULL) { Status =3D mPciPlatformProtocol->GetPlatformPolicy ( mPciPlatformProtocol, @@ -197,6 +282,7 @@ PciGetPlatformPolicy ( // return EFI_NOT_FOUND; } + } return Status; } =20 @@ -223,6 +309,22 @@ GetPlatformPciOptionRom ( EFI_STATUS Status; VOID *PlatformOpRomBuffer; UINTN PlatformOpRomSize; + + if (mPciPlatformProtocol2 !=3D NULL) { + Status =3D mPciPlatformProtocol2->GetPciRom ( + mPciPlatformProtocol2, + PciIoDevice->Handle, + &PlatformOpRomBuffer, + &PlatformOpRomSize + ); + } else if (mPciOverrideProtocol2 !=3D NULL) { + Status =3D mPciOverrideProtocol2->GetPciRom ( + mPciOverrideProtocol2, + PciIoDevice->Handle, + &PlatformOpRomBuffer, + &PlatformOpRomSize + ); + } else { if (mPciPlatformProtocol !=3D NULL) { Status =3D mPciPlatformProtocol->GetPciRom ( mPciPlatformProtocol, @@ -243,6 +345,7 @@ GetPlatformPciOptionRom ( // return EFI_NOT_FOUND; } + } =20 if (!EFI_ERROR (Status)) { PciIoDevice->EmbeddedRom =3D FALSE; @@ -252,3 +355,104 @@ GetPlatformPciOptionRom ( } return Status; } + +/** + Generic routine to setup the PCI features as per its predetermined defau= lts. +**/ +VOID +SetupDefaultsDevicePlatformPolicy ( + IN PCI_IO_DEVICE *PciDevice + ) +{ +} + +/** + Intermediate routine to either get the PCI device specific platform poli= cies + through the PCI Platform Protocol, or its alias the PCI Override Protoco= l. + + @param PciIoDevice A pointer to PCI_IO_DEVICE + @param PciPlatformProtocol A pointer to EFI_PCI_PLATFORM_PROTOCOL2 + + @retval EFI_STATUS The direct status from the PCI Platform Prot= ocol + @retval EFI_SUCCESS if on returning predetermined PCI features d= efaults, + for the case when protocol returns as EFI_UN= SUPPORTED + to indicate PCI device exist and it has no p= latform + policy defined. +**/ +EFI_STATUS +GetPciDevicePlatformPolicyEx ( + IN PCI_IO_DEVICE *PciIoDevice, + IN EFI_PCI_PLATFORM_PROTOCOL2 *PciPlatformProtocol + ) +{ + EFI_PCI_PLATFORM_EXTENDED_POLICY PciPlatformExtendedPolicy; + EFI_STATUS Status; + + ZeroMem (&PciPlatformExtendedPolicy, sizeof (EFI_PCI_PLATFORM_EXTENDED_P= OLICY)); + Status =3D PciPlatformProtocol->GetDevicePolicy ( + PciPlatformProtocol, + PciIoDevice->Handle, + &PciPlatformExtendedPolicy + ); + switch (Status) { + case EFI_SUCCESS: + // + // platform chipset policies are returned for this PCI device + // + + DEBUG (( + DEBUG_INFO, "[device policy: platform]" + )); + return Status; + + case EFI_UNSUPPORTED: + // + // platform chipset policies are not provided for this PCI device + // let the enumeration happen as per the PCI standard way + // + SetupDefaultsDevicePlatformPolicy (PciIoDevice); + DEBUG (( + DEBUG_INFO, "[device policy: default]" + )); + return EFI_SUCCESS; + + default: + DEBUG (( + DEBUG_ERROR, "[device policy: none (error)]" + )); + return Status; + } +} + +/** + Gets the PCI device-specific platform policy from the PCI Platform Proto= col. + If no PCI Platform protocol is published than setup the PCI feature to p= redetermined + defaults, in order to align all the PCI devices in the PCI hierarchy, as= applicable. + + @param PciDevice A pointer to PCI_IO_DEVICE + + @retval EFI_STATUS The direct status from the PCI Platform Protocol + @retval EFI_SUCCESS On return of predetermined PCI features defaults, = for + the case when protocol returns as EFI_UNSUPPORTED = to + indicate PCI device exist and it has no platform p= olicy + defined. Also, on returns when no PCI Platform Pro= tocol + exist. +**/ +EFI_STATUS +GetPciDevicePlatformPolicy ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + if (mPciPlatformProtocol2 !=3D NULL) { + return GetPciDevicePlatformPolicyEx (PciDevice, mPciPlatformProtocol2); + } else if (mPciOverrideProtocol2 !=3D NULL) { + return GetPciDevicePlatformPolicyEx (PciDevice, mPciOverrideProtocol2); + } else { + // + // new PCI Platform Protocol 2 is not installed; let the enumeration h= appen + // as per PCI standard way + // + SetupDefaultsDevicePlatformPolicy (PciDevice); + return EFI_SUCCESS; + } +} diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h index c0d3b49..a13131c 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h @@ -106,4 +106,22 @@ GetPlatformPciOptionRom ( IN PCI_IO_DEVICE *PciIoDevice ); =20 +/** + Gets the PCI device-specific platform policy from the PCI Platform Proto= col. + If no PCI Platform protocol is published than setup the PCI feature to p= redetermined + defaults, in order to align all the PCI devices in the PCI hierarchy, as= applicable. + + @param PciDevice A pointer to PCI_IO_DEVICE + + @retval EFI_STATUS The direct status from the PCI Platform Protocol + @retval EFI_SUCCESS On return of predetermined PCI features defaults, = for + the case when protocol returns as EFI_UNSUPPORTED = to + indicate PCI device exist and it has no platform p= olicy + defined. Also, on returns when no PCI Platform Pro= tocol + exist. +**/ +EFI_STATUS +GetPciDevicePlatformPolicy ( + IN PCI_IO_DEVICE *PciDevice + ); #endif --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49808): https://edk2.groups.io/g/devel/message/49808 Mute This Topic: https://groups.io/mt/40419685/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49809+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49809+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621017; cv=none; d=zoho.com; s=zohoarc; b=De54z56/5UKJW/uyqcOnJY0qjhzpx1Tzlx0WPFg3aAs7aFehUa2hF9XtaSubWAAEXneyaUoqr8al2JG+D5xM/DrXG3s9nrPNNxFGJi/z7bTu3WvGEomAf5XNiShuzUwWQGI1SxGbYPmAvwXWzMVm3lxRZm0Vz1JkPn4YBM6xnY0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621017; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=d6XdDadW9ERFZQi642O1hN/K1BzWuJL0Lske+AV1Xb0=; b=ZUAYd5vxtJpDpwiS5Ed+tejXwLQCKFbW/HlYQyMw/Sie0/sTy7tLteYkK55yW4bdblwH26nLK8zRKQ/ohgzIYhLQDd8hHe9wo+C+qMH6tcHMDPgFOjZiStvP/zVorzDoQKrC+Ssyeam82X/DTKmumh0EMQVXvdN3syCPvQLPYzc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49809+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621017629571.1858063221896; Fri, 1 Nov 2019 08:10:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:17 -0700 X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:16 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687097" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:12 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration Date: Fri, 1 Nov 2019 20:39:45 +0530 Message-Id: <20191101150952.3340-6-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621017; bh=Q3DbXnbV5rsDZbLeK73wJehuxBeUBlbTM185nR7c9Do=; h=Cc:Date:From:Reply-To:Subject:To; b=rMyKbettmCpi6tl25od9x181a6Ip/daK4/HnG4sNwPqkhwbRzLTpagaiJa5CHgeNKRR XXWPo0jpDsXNTodhe6u8NIHiH/p2st7mZ9bwMZon5zXlz0zcWIZjuNJLiRxIWc5aRQj4a XSjyHRzaHVC92QAa71jangtma7FcU0LPXpk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The code changes are made to setup the following internal sub-phases for enumerating the PCI features in the late phase of the PCI Bus driver. (1) PciFeatureRootBridgeScan - initial phase in configuring the other PCI features to record the primary root ports (2) PciFeatureGetDevicePolicy - get the PCI device-specific platform pol- icies and align with device capabilities (3) PciFeatureSetupPhase - align all PCI nodes in the PCI heirarchical tree (if required for that PCI feature) (4) PciFeatureConfigurationPhase - finally override to complete configu- ration of the PCI feature The code changes are made to support the configuration of other PCIe features, like MPS, which require a common value to be assigned among all the child PCI devices and its parent root port device. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 859 +++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 146 +++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 1005 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index 8be227a..ab0e096 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -9,6 +9,23 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include "PciBus.h" #include "PciFeatureSupport.h" =20 +/** + A gobal pointer to PRIMARY_ROOT_PORT_NODE buffer to track all the primar= y physical + PCI Root Ports (PCI Controllers) for a given PCI Root Bridge instance wh= ile + enumerating to configure the PCI features +**/ +PRIMARY_ROOT_PORT_NODE *mPrimaryRootPortList; + +/** + A global pointer to PCI_FEATURE_CONFIGURATION_COMPLETION_LIST, which sto= res all + the PCI Root Bridge instances that are enumerated for the other PCI feat= ures, + like MaxPayloadSize & MaxReadReqSize; during the the Start() interface o= f the + driver binding protocol. The records pointed by this pointer would be de= stroyed + when the DXE core invokes the Stop() interface. +**/ +PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *mPciFeaturesConfigurationComp= letionList =3D NULL; + + /** Main routine to indicate whether the platform has selected the Max_Paylo= ad_Size PCI feature to be configured by this driver @@ -175,3 +192,845 @@ SetupPtm ( { return (PcdGet32 (PcdOtherPciFeatures) & PCI_FEATURE_SUPPORT_FLAG_PTM) ?= TRUE : FALSE; } + +/** + Helper routine to determine the existence of previously enumerated PCI de= vice + + @retval TRUE PCI device exist + FALSE does not exist +**/ +BOOLEAN +DeviceExist ( + PCI_IO_DEVICE *PciDevice + ) +{ + EFI_PCI_IO_PROTOCOL *PciIoProtocol =3D &PciDevice->PciIo; + UINT16 VendorId =3D 0xFFFF; + + PciIoProtocol->Pci.Read ( + PciIoProtocol, + EfiPciIoWidthUint16, + PCI_VENDOR_ID_OFFSET, + 1, + &VendorId + ); + if (VendorId =3D=3D 0 || VendorId =3D=3D 0xFFFF) { + return FALSE; + } else { + return TRUE; + } +} + +/** + Helper routine which determines whether the given PCI Root Bridge instan= ce + record already exist. This routine shall help avoid duplicate record cre= ation + in case of re-enumeration of PCI configuation features. + + @param RootBridge A pointer to the PCI_IO_DEVICE for the R= oot Bridge + @param PciFeatureConfigRecord A pointer to a pointer for type + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST + record, Use to return the specific recor= d. + + @retval TRUE Record already exist + FALSE Record does not exist for the given PCI = Root Bridge +**/ +BOOLEAN +CheckPciFeatureConfigurationRecordExist ( + IN PCI_IO_DEVICE *RootBridge, + OUT PCI_FEATURE_CONFIGURATION_COMPLETION_LIST **PciFeatureConfigRecord + ) +{ + LIST_ENTRY *Link; + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *Temp; + + if (mPciFeaturesConfigurationCompletionList) { + Link =3D &mPciFeaturesConfigurationCompletionList->RootBridgeLink; + + do { + Temp =3D PCI_FEATURE_CONFIGURATION_COMPLETION_LIST_FROM_LINK (Link); + if (Temp->RootBridgeHandle =3D=3D RootBridge->Handle) { + *PciFeatureConfigRecord =3D Temp; + return TRUE; + } + Link =3D Link->ForwardLink; + } while (Link !=3D &mPciFeaturesConfigurationCompletionList->RootBridg= eLink); + } + // + // not found on the PCI feature configuration completion list + // + *PciFeatureConfigRecord =3D NULL; + return FALSE; +} + +/** + This routine is primarily to avoid multiple configuration of PCI features + to the same PCI Root Bridge due to EDK2 core's ConnectController calls on + all the EFI handles. This routine also provide re-enumeration of the PCI + features on the same PCI Root Bridge based on the policy of ReEnumerateP= ciFeatureConfiguration + of the PCI_FEATURE_CONFIGURATION_COMPLETION_LIST. + + @param RootBridge A pointer to the PCI_IO_DEVICE for the R= oot Bridge + + @retval TRUE PCI Feature configuration required for t= he PCI + Root Bridge + FALSE PCI Feature configuration is not require= d to be + re-enumerated for the PCI Root Bridge +**/ +BOOLEAN +CheckPciFeaturesConfigurationRequired ( + IN PCI_IO_DEVICE *RootBridge + ) +{ + LIST_ENTRY *Link; + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *Temp; + + if (mPciFeaturesConfigurationCompletionList) { + Link =3D &mPciFeaturesConfigurationCompletionList->RootBridgeLink; + + do { + Temp =3D PCI_FEATURE_CONFIGURATION_COMPLETION_LIST_FROM_LINK (Link); + if (Temp->RootBridgeHandle =3D=3D RootBridge->Handle) { + return Temp->ReEnumeratePciFeatureConfiguration; + } + Link =3D Link->ForwardLink; + } while (Link !=3D &mPciFeaturesConfigurationCompletionList->RootBridg= eLink); + } + // + // not found on the PCI feature configuration completion list, return as= required + // + return TRUE; +} + +/** + This routine finds the duplicate record if exist and assigns the re-enum= eration + requirement flag, as passed as input. It creates new record for the PCI = Root + Bridge and appends the list after updating its re-enumeration flag. + + @param RootBridge A pointer to PCI_IO_DEVICE of the Root Bri= dge + @param ReEnumerationRequired A BOOLEAN for recording the re-enumeration= requirement + + @retval EFI_SUCCESS new record inserted into the list or updat= ed the + existing record + EFI_INVALID_PARAMETER Unexpected error as CheckPciFeatureConfigu= rationRecordExist + reports as record exist but does not retur= n its pointer + EFI_OUT_OF_RESOURCES Not able to create PCI features configurat= in complete + record for the RootBridge +**/ +EFI_STATUS +AddRootBridgeInPciFeaturesConfigCompletionList ( + IN PCI_IO_DEVICE *RootBridge, + IN BOOLEAN ReEnumerationRequired + ) +{ + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *Temp; + + if (CheckPciFeatureConfigurationRecordExist (RootBridge, &Temp)) { + // + // this PCI Root Bridge record already exist; it may have been re-enum= erated + // hence just update its enumeration required flag again to exit + // + if (Temp) { + Temp->ReEnumeratePciFeatureConfiguration =3D ReEnumerationRequired; + return EFI_SUCCESS; + } else { + // + // PCI feature configuration complete record reported as exist and no + // record pointer returned + // + return EFI_INVALID_PARAMETER; + } + + } else { + + Temp =3D AllocateZeroPool (sizeof (PCI_FEATURE_CONFIGURATION_COMPLETIO= N_LIST)); + if (Temp =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + Temp->Signature =3D PCI_FEATURE_CONFIGURATIO= N_SIGNATURE; + Temp->RootBridgeHandle =3D RootBridge->Handle; + Temp->ReEnumeratePciFeatureConfiguration =3D ReEnumerationRequired; + if (mPciFeaturesConfigurationCompletionList) { + InsertTailList ( + &mPciFeaturesConfigurationCompletionList->RootBridgeLink, + &Temp->RootBridgeLink + ); + } else { + // + // init the very first node of the Root Bridge + // + mPciFeaturesConfigurationCompletionList =3D Temp; + InitializeListHead (&mPciFeaturesConfigurationCompletionList->RootBr= idgeLink); + } + } + return EFI_SUCCESS; +} + +/** + Free up memory alloted for the primary physical PCI Root ports of the PC= I Root + Bridge instance. Free up all the nodes of type PRIMARY_ROOT_PORT_NODE. +**/ +VOID +DestroyPrimaryRootPortNodes () +{ + LIST_ENTRY *Link; + PRIMARY_ROOT_PORT_NODE *Temp; + + if (mPrimaryRootPortList) { + Link =3D &mPrimaryRootPortList->NeighborRootPort; + + if (IsListEmpty (Link)) { + FreePool (mPrimaryRootPortList->OtherPciFeaturesConfigurationTable); + FreePool (mPrimaryRootPortList); + } else { + do { + if (Link->ForwardLink !=3D &mPrimaryRootPortList->NeighborRootPort= ) { + Link =3D Link->ForwardLink; + } + Temp =3D PRIMARY_ROOT_PORT_NODE_FROM_LINK (Link); + Link =3D RemoveEntryList (Link); + FreePool (Temp->OtherPciFeaturesConfigurationTable); + FreePool (Temp); + } while (!IsListEmpty (Link)); + FreePool (mPrimaryRootPortList->OtherPciFeaturesConfigurationTable); + FreePool (mPrimaryRootPortList); + } + mPrimaryRootPortList =3D NULL; + } +} + +/** + Routine meant for initializing any global variables used. It primarily c= leans + up the internal data structure memory allocated for the previous PCI Roo= t Bridge + instance. This should be the first routine to call for any virtual PCI R= oot + Bridge instance. +**/ +VOID +SetupPciFeaturesConfigurationDefaults () +{ + // + // delete the primary root port list + // + if (mPrimaryRootPortList) { + DestroyPrimaryRootPortNodes (); + } +} + +/** + Main routine to determine the child PCI devices of a PCI bridge device + and group them under a common internal PCI features Configuration table. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciFeaturesConfigTable A pointer to a pointer to the + OTHER_PCI_FEATURES_CONFIGURATION= _TABLE. + Returns NULL in case of RCiEP or= the PCI + device does match with any of th= e physical + Root ports, or it does not belon= g to any + Root port's PCI bus range (not a= child) + + @retval EFI_SUCCESS able to determine the PCI feature + configuration table. For RCiEP s= ince + since it is not prepared. + EFI_DEVICE_ERROR the PCI device has invalid EFI d= evice + path +**/ +EFI_STATUS +GetPciFeaturesConfigurationTable ( + IN PCI_IO_DEVICE *PciDevice, + OUT OTHER_PCI_FEATURES_CONFIGURATION_TABLE **PciFeaturesConfigTable + ) +{ + LIST_ENTRY *Link; + PRIMARY_ROOT_PORT_NODE *Temp; + BOOLEAN NodeMatch; + EFI_DEVICE_PATH_PROTOCOL *RootPortPath; + EFI_DEVICE_PATH_PROTOCOL *PciDevicePath; + + if (mPrimaryRootPortList =3D=3D NULL) { + // + // no populated PCI primary root ports to parse and match the PCI feat= ures + // configuration table + // + *PciFeaturesConfigTable =3D NULL; + return EFI_SUCCESS; + } + + + if (IsDevicePathEnd (PciDevice->DevicePath)){ + // + // the given PCI device does not have a valid device path + // + *PciFeaturesConfigTable =3D NULL; + return EFI_DEVICE_ERROR; + } + + + Link =3D &mPrimaryRootPortList->NeighborRootPort; + do { + Temp =3D PRIMARY_ROOT_PORT_NODE_FROM_LINK (Link); + RootPortPath =3D Temp->RootPortDevicePath; + PciDevicePath =3D PciDevice->DevicePath; + NodeMatch =3D FALSE; + // + // match the device path from the list of primary Root Ports with the = given + // device; the initial nodes matching in sequence indicate that the gi= ven PCI + // device belongs to that PCI tree from the root port + // + if (IsDevicePathEnd (RootPortPath)) { + // + // critical error as no device path available in root + // + *PciFeaturesConfigTable =3D NULL; + return EFI_DEVICE_ERROR; + } + + if (EfiCompareDevicePath (RootPortPath, PciDevicePath)) { + // + // the given PCI device is the primary root port itself + // + *PciFeaturesConfigTable =3D Temp->OtherPciFeaturesConfigurationTable; + return EFI_SUCCESS; + } + // + // check this PCI device belongs to the primary root port of the root = bridge + // any child PCI device will have the same initial device path nodes = as + // its parent root port + // + while (!IsDevicePathEnd (RootPortPath)){ + + if (DevicePathNodeLength (RootPortPath) !=3D DevicePathNodeLength (P= ciDevicePath)) { + // + // break to check the next primary root port nodes as does not mat= ch + // + NodeMatch =3D FALSE; + break; + } + if (CompareMem (RootPortPath, PciDevicePath, DevicePathNodeLength (R= ootPortPath)) !=3D 0) { + // + // node does not match, break to check next node + // + NodeMatch =3D FALSE; + break; + } + NodeMatch =3D TRUE; + // + // advance to next node + // + RootPortPath =3D NextDevicePathNode (RootPortPath); + PciDevicePath =3D NextDevicePathNode (PciDevicePath); + } + + if (NodeMatch =3D=3D TRUE) { + // + // device belongs to primary root port, return its PCI feature confi= guration + // table + // + *PciFeaturesConfigTable =3D Temp->OtherPciFeaturesConfigurationTable; + return EFI_SUCCESS; + } + + // + // advance to next Root port node + // + Link =3D Link->ForwardLink; + } while (Link !=3D &mPrimaryRootPortList->NeighborRootPort); + // + // the PCI device must be RCiEP, does not belong to any primary root port + // + *PciFeaturesConfigTable =3D NULL; + return EFI_SUCCESS; +} + +/** + This routine determines the existance of the child PCI device for the gi= ven + PCI Root / Bridge Port device. Always assumes the input PCI device is th= e bridge + or PCI-PCI Bridge device. This routine should not be used with PCI endpo= int device. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + + @retval TRUE child device exist + FALSE no child device +**/ +BOOLEAN +IsPciRootPortEmpty ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + if (IsListEmpty (&PciDevice->ChildList)){ + return TRUE; + } + return FALSE; +} + + +/** + Process each PCI device as per the pltaform and device-specific policy. + + @param RootBridge A pointer to the PCI_IO_DEVICE. + + @retval EFI_SUCCESS processing each PCI feature as per policy = defined + was successful. + **/ +EFI_STATUS +SetupDevicePciFeatures ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase + ) +{ + EFI_STATUS Status; + OTHER_PCI_FEATURES_CONFIGURATION_TABLE *OtherPciFeaturesConfigTable; + + OtherPciFeaturesConfigTable =3D NULL; + Status =3D GetPciFeaturesConfigurationTable (PciDevice, &OtherPciFeature= sConfigTable); + if (EFI_ERROR( Status)) { + DEBUG (( + DEBUG_WARN, "[Cfg group: 0 {error in dev path}]" + )); + } else if (OtherPciFeaturesConfigTable =3D=3D NULL) { + DEBUG (( + DEBUG_INFO, "[Cfg group: 0]" + )); + } else { + DEBUG (( + DEBUG_INFO, "[Cfg group: %d]", + OtherPciFeaturesConfigTable->ID + )); + } + + if (PciConfigPhase =3D=3D PciFeatureGetDevicePolicy) { + Status =3D GetPciDevicePlatformPolicy (PciDevice); + if (EFI_ERROR(Status)) { + DEBUG (( + DEBUG_ERROR, "Error in obtaining PCI device policy!!!\n" + )); + } + } + + return Status; +} + +/** + Traverse all the nodes from the root bridge or PCI-PCI bridge instance, = to + configure the PCI features as per the device-specific platform policy, a= nd + as per the device capability, as applicable. + + @param RootBridge A pointer to the PCI_IO_DEVICE. + + @retval EFI_SUCCESS Traversing all the nodes of the root bridge + instances were successfull. +**/ +EFI_STATUS +SetupPciFeatures ( + IN PCI_IO_DEVICE *RootBridge, + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase + ) +{ + EFI_STATUS Status; + LIST_ENTRY *Link; + PCI_IO_DEVICE *Device; + + for ( Link =3D RootBridge->ChildList.ForwardLink + ; Link !=3D &RootBridge->ChildList + ; Link =3D Link->ForwardLink + ) { + Device =3D PCI_IO_DEVICE_FROM_LINK (Link); + if (!DeviceExist (Device)) { + DEBUG (( + DEBUG_ERROR, "::Device [%02x|%02x|%02x] - does not exist!!!\n", + Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber + )); + continue; + } + if (IS_PCI_BRIDGE (&Device->Pci)) { + DEBUG (( + DEBUG_INFO, "::Bridge [%02x|%02x|%02x] -", + Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber + )); + if (Device->IsPciExp) { + Status =3D SetupDevicePciFeatures (Device, PciConfigPhase); + } else { + DEBUG (( DEBUG_INFO, "Not a PCIe capable device!\n")); + // + // PCI Bridge which does not have PCI Express Capability structure + // cannot process this kind of PCI Bridge device + // + + } + + SetupPciFeatures (Device, PciConfigPhase); + } else { + DEBUG (( + DEBUG_INFO, "::Device [%02x|%02x|%02x] -", + Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber + )); + if (Device->IsPciExp) { + + Status =3D SetupDevicePciFeatures (Device, PciConfigPhase); + } else { + DEBUG (( DEBUG_INFO, "Not a PCIe capable device!\n")); + // + // PCI Device which does not have PCI Express Capability structure + // cannot process this kind of PCI device + // + } + } + } + + return EFI_SUCCESS; +} + +/** + Program the PCI device, to override the PCI features as per the policy, + resolved from previous traverse. + + @param RootBridge A pointer to the PCI_IO_DEVICE. + + @retval EFI_SUCCESS The other PCI features configuration durin= g enumeration + of all the nodes of the PCI root bridge in= stance were + programmed in PCI-compliance pattern along= with the + device-specific policy, as applicable. + @retval EFI_UNSUPPORTED One of the override operation maong the no= des of + the PCI hierarchy resulted in a incompatib= le address + range. + @retval EFI_INVALID_PARAMETER The override operation is performed with i= nvalid input + parameters. +**/ +EFI_STATUS +ProgramDevicePciFeatures ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + EFI_STATUS Status; + + return Status; +} + +/** + Program all the nodes of the specified root bridge or PCI-PCI Bridge, to + override the PCI features. + + @param RootBridge A pointer to the PCI_IO_DEVICE. + + @retval EFI_SUCCESS The other PCI features configuration durin= g enumeration + of all the nodes of the PCI root bridge in= stance were + programmed in PCI-compliance pattern along= with the + device-specific policy, as applicable. + @retval EFI_UNSUPPORTED One of the override operation maong the no= des of + the PCI hierarchy resulted in a incompatib= le address + range. + @retval EFI_INVALID_PARAMETER The override operation is performed with i= nvalid input + parameters. +**/ +EFI_STATUS +ProgramPciFeatures ( + IN PCI_IO_DEVICE *RootBridge + ) +{ + EFI_STATUS Status; + LIST_ENTRY *Link; + PCI_IO_DEVICE *Device; + + for ( Link =3D RootBridge->ChildList.ForwardLink + ; Link !=3D &RootBridge->ChildList + ; Link =3D Link->ForwardLink + ) { + Device =3D PCI_IO_DEVICE_FROM_LINK (Link); + if (!DeviceExist (Device)) { + DEBUG (( + DEBUG_ERROR, "::Device [%02x|%02x|%02x] - does not exist!!!\n", + Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber + )); + continue; + } + if (IS_PCI_BRIDGE (&Device->Pci)) { + DEBUG (( + DEBUG_INFO, "::Bridge [%02x|%02x|%02x] -", + Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber + )); + if (Device->IsPciExp) { + DEBUG (( DEBUG_INFO, "ready to override!\n")); + + Status =3D ProgramDevicePciFeatures (Device); + } else { + DEBUG (( DEBUG_INFO, "skipped!\n")); + // + // PCI Bridge which does not have PCI Express Capability structure + // cannot process this kind of PCI Bridge device + // + } + + Status =3D ProgramPciFeatures (Device); + } else { + DEBUG (( + DEBUG_INFO, "::Device [%02x|%02x|%02x] -", + Device->BusNumber, Device->DeviceNumber, Device->FunctionNumber + )); + if (Device->IsPciExp) { + DEBUG (( DEBUG_INFO, "ready to override!\n")); + + Status =3D ProgramDevicePciFeatures (Device); + } else { + DEBUG (( DEBUG_INFO, "skipped!\n")); + // + // PCI Device which does not have PCI Express Capability structure + // cannot process this kind of PCI device + // + } + } + } + + return Status; +} + +/** + Create and add a node of type PRIMARY_ROOT_PORT_NODE in the list for the= primary + Root Port so that all its child PCI devices can be identified against th= e PCI + features configuration table group ID, of type OTHER_PCI_FEATURES_CONFIG= URATION_TABLE. + + @param BridgePort A pointer to the PCI_IO_DEVICE + @param PortNumber A UINTN value to identify the PCI feature configura= tion + table group + + @retval EFI_SUCCESS success in adding a node of PRIMARY_ROOT_P= ORT_NODE + to the list + EFI_OUT_OF_RESOURCES unable to get memory for creating the node +**/ +EFI_STATUS +AddPrimaryRootPortNode ( + IN PCI_IO_DEVICE *BridgePort, + IN UINTN PortNumber + ) +{ + PRIMARY_ROOT_PORT_NODE *RootPortNode =3D NULL; + OTHER_PCI_FEATURES_CONFIGURATION_TABLE *PciConfigTable =3D NULL; + + RootPortNode =3D AllocateZeroPool (sizeof (PRIMARY_ROOT_PORT_NODE)); + if (RootPortNode =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + RootPortNode->Signature =3D PCI_ROOT_PORT_SIGN= ATURE; + RootPortNode->RootPortDevicePath =3D BridgePort->Device= Path; + PciConfigTable =3D AllocateZeroPool ( + sizeof (OTHER_PCI_FEATURES_CONFIGURATION_TABLE) + ); + if (PciConfigTable) { + PciConfigTable->ID =3D PortNumber; + } + RootPortNode->OtherPciFeaturesConfigurationTable =3D PciConfigTable; + + if (mPrimaryRootPortList !=3D NULL) { + InsertTailList (&mPrimaryRootPortList->NeighborRootPort, &RootPortNode= ->NeighborRootPort); + } else { + InitializeListHead (&RootPortNode->NeighborRootPort); + mPrimaryRootPortList =3D RootPortNode; + } + + if (PciConfigTable =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + return EFI_SUCCESS; +} + +/** + Scan all the nodes of the RootBridge to identify and create a separate l= ist + of all primary physical PCI root ports and link each with its own instan= ce of + the PCI Feature Configuration Table. + + @param RootBridge A pointer to the PCI_IO_DEVICE of the PCI Root Bri= dge + + @retval EFI_OUT_OF_RESOURCES unable to allocate buffer to store PCI fea= ture + configuration table for all the physical P= CI root + ports given + EFI_NOT_FOUND No PCI Bridge device found + EFI_SUCCESS PCI Feature COnfiguration table created fo= r all + the PCI Rooot ports found + EFI_INVALID_PARAMETER invalid parameter passed to the routine wh= ich + creates the PCI controller node for the pr= imary + Root post list +**/ +EFI_STATUS +RecordPciRootPortBridges ( + IN PCI_IO_DEVICE *RootBridge + ) +{ + EFI_STATUS Status =3D EFI_NOT_FOUND; + LIST_ENTRY *Link; + PCI_IO_DEVICE *Device; + UINTN NumberOfRootPorts; + + DEBUG (( + DEBUG_INFO, "<<********** RecordPciRootPortBridges -start **********= ***>>\n" + )); + NumberOfRootPorts =3D 0; + for ( Link =3D RootBridge->ChildList.ForwardLink + ; Link !=3D &RootBridge->ChildList + ; Link =3D Link->ForwardLink + ) { + Device =3D PCI_IO_DEVICE_FROM_LINK (Link); + if (!DeviceExist (Device)) { + continue; + } + if (IS_PCI_BRIDGE (&Device->Pci)) { + NumberOfRootPorts++; + DEBUG (( + DEBUG_INFO, "#%d ::Bridge [%02x|%02x|%02x]", + NumberOfRootPorts, Device->BusNumber, Device->DeviceNumber, Devi= ce->FunctionNumber + )); + // + // create a primary root port list if that port is connected + // + if (!IsListEmpty (&Device->ChildList)) { + DEBUG (( + DEBUG_INFO, "- has downstream device!\n" + )); + Status =3D AddPrimaryRootPortNode (Device, NumberOfRootPorts); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, "PCI configuration table allocation failure for= #%d ::Bridge [%02x|%02x|%02x]\n", + NumberOfRootPorts, Device->BusNumber, Device->DeviceNumber, = Device->FunctionNumber + )); + } + } else { + DEBUG (( + DEBUG_INFO, "- no downstream device!\n" + )); + } + } + } + DEBUG (( + DEBUG_INFO, "<<********** RecordPciRootPortBridges - end **********>= >\n" + )); + return Status; +} + +/** + Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge, = to + configure the other PCI features. + + @param RootBridge A pointer to the PCI_IO_DEVICE. + + @retval EFI_SUCCESS The other PCI features configuration durin= g enumeration + of all the nodes of the PCI root bridge in= stance were + programmed in PCI-compliance pattern along= with the + device-specific policy, as applicable. + @retval EFI_UNSUPPORTED One of the override operation maong the no= des of + the PCI hierarchy resulted in a incompatib= le address + range. + @retval EFI_INVALID_PARAMETER The override operation is performed with i= nvalid input + parameters. +**/ +EFI_STATUS +EnumerateOtherPciFeatures ( + IN PCI_IO_DEVICE *RootBridge + ) +{ + EFI_STATUS Status; + CHAR16 *Str; + UINTN OtherPciFeatureConfigPhase; + + // + // check on PCI features configuration is complete and re-enumeration is= required + // + if (!CheckPciFeaturesConfigurationRequired (RootBridge)) { + return EFI_ALREADY_STARTED; + } + + Str =3D ConvertDevicePathToText ( + DevicePathFromHandle (RootBridge->Handle), + FALSE, + FALSE + ); + DEBUG ((DEBUG_INFO, "Enumerating PCI features for Root Bridge %s\n", Str= !=3D NULL ? Str : L"")); + + for ( OtherPciFeatureConfigPhase =3D PciFeatureRootBridgeScan + ; OtherPciFeatureConfigPhase <=3D PciFeatureConfigurationComplete + ; OtherPciFeatureConfigPhase++ + ) { + switch (OtherPciFeatureConfigPhase){ + case PciFeatureRootBridgeScan: + SetupPciFeaturesConfigurationDefaults (); + // + //first scan the entire root bridge heirarchy for the primary PCI = root ports + // + RecordPciRootPortBridges (RootBridge); + break; + + case PciFeatureGetDevicePolicy: + case PciFeatureSetupPhase: + DEBUG (( + DEBUG_INFO, "<<********** SetupPciFeatures - start **********>= >\n" + )); + // + // enumerate the other PCI features + // + Status =3D SetupPciFeatures (RootBridge, OtherPciFeatureConfigPhas= e); + + DEBUG (( + DEBUG_INFO, "<<********** SetupPciFeatures - end **********>>\= n" + )); + break; + + case PciFeatureConfigurationPhase: + // + // override the PCI features as per enumeration phase + // + DEBUG ((DEBUG_INFO, "PCI features override for Root Bridge %s\n", = Str !=3D NULL ? Str : L"")); + DEBUG (( + DEBUG_INFO, "<<********** ProgramPciFeatures - start *********= *>>\n" + )); + Status =3D ProgramPciFeatures (RootBridge); + DEBUG (( + DEBUG_INFO, "<<********** ProgramPciFeatures - end **********>= >\n" + )); + break; + + case PciFeatureConfigurationComplete: + // + // clean up the temporary resource nodes created for this root bri= dge + // + DestroyPrimaryRootPortNodes (); + } + } + + if (Str !=3D NULL) { + FreePool (Str); + } + // + // mark this root bridge as PCI features configuration complete, and no = new + // enumeration is required + // + AddRootBridgeInPciFeaturesConfigCompletionList (RootBridge, FALSE); + return Status; +} + +/** + This routine is invoked from the Stop () interface for the EFI handle of= the + RootBridge. Free up its node of type PCI_FEATURE_CONFIGURATION_COMPLETIO= N_LIST. + + @param RootBridge A pointer to the PCI_IO_DEVICE +**/ +VOID +DestroyRootBridgePciFeaturesConfigCompletionList ( + IN PCI_IO_DEVICE *RootBridge + ) +{ + LIST_ENTRY *Link; + PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *Temp; + + if (mPciFeaturesConfigurationCompletionList) { + Link =3D &mPciFeaturesConfigurationCompletionList->RootBridgeLink; + + do { + Temp =3D PCI_FEATURE_CONFIGURATION_COMPLETION_LIST_FROM_LINK (Link); + if (Temp->RootBridgeHandle =3D=3D RootBridge->Handle) { + RemoveEntryList (Link); + FreePool (Temp); + return; + } + Link =3D Link->ForwardLink; + } while (Link !=3D &mPciFeaturesConfigurationCompletionList->RootBridg= eLink); + } + // + // not found on the PCI feature configuration completion list, return + // + return; +} diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h index d06a5e8..b06c140 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -23,4 +23,150 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define PCI_FEATURE_SUPPORT_FLAG_CCC BIT13 #define PCI_FEATURE_SUPPORT_FLAG_ESYN BIT14 #define PCI_FEATURE_SUPPORT_FLAG_PTM BIT20 + +// +// defines the data structure to hold the details of the PCI Root port dev= ices +// +typedef struct _PRIMARY_ROOT_PORT_NODE PRIMARY_ROOT_PORT_NODE; + +// +// defines the data structure to hold the configuration data for the other= PCI +// features +// +typedef struct _OTHER_PCI_FEATURES_CONFIGURATION_TABLE OTHER_PCI_FEATURES= _CONFIGURATION_TABLE; + +// +// Defines for the PCI features configuration completion and re-enumeratio= n list +// +typedef struct _PCI_FEATURE_CONFIGURATION_COMPLETION_LIST PCI_FEATURE_CON= FIGURATION_COMPLETION_LIST; + +// +// Signature value for the PCI Root Port node +// +#define PCI_ROOT_PORT_SIGNATURE SIGNATURE_32 ('p', 'c', 'i',= 'p') + +// +// Definitions of the PCI Root Port data structure members +// +struct _PRIMARY_ROOT_PORT_NODE { + // + // Signature header + // + UINT32 Signature; + // + // linked list pointers to next node + // + LIST_ENTRY NeighborRootPort; + // + // pointer to PCI_IO_DEVICE of the primary PCI Controller device + // + EFI_DEVICE_PATH_PROTOCOL *RootPortDevicePath; + // + // pointer to the corresponding PCI feature configuration Table node + // all the child PCI devices of the controller are aligned based on this= table + // + OTHER_PCI_FEATURES_CONFIGURATION_TABLE *OtherPciFeaturesConfiguration= Table; +}; + +#define PRIMARY_ROOT_PORT_NODE_FROM_LINK(a) \ + CR (a, PRIMARY_ROOT_PORT_NODE, NeighborRootPort, PCI_ROOT_PORT_SIGNATURE) + +// +// Definition of the PCI Feature configuration Table members +// +struct _OTHER_PCI_FEATURES_CONFIGURATION_TABLE { + // + // Configuration Table ID + // + UINTN ID; +}; + + +// +// PCI feature configuration node signature value +// +#define PCI_FEATURE_CONFIGURATION_SIGNATURE SIGNATURE_32 ('p= ', 'c', 'i', 'f') + +struct _PCI_FEATURE_CONFIGURATION_COMPLETION_LIST { + // + // Signature header + // + UINT32 Signature; + // + // link to next Root Bridge whose PCI Feature configuration is complete + // + LIST_ENTRY RootBridgeLink; + // + // EFI handle of the Root Bridge whose PCI feature configuration is comp= lete + // + EFI_HANDLE RootBridgeHandle; + // + // indication for complete re-enumeration of the PCI feature configurati= on + // + BOOLEAN ReEnumeratePciFeatureConfigura= tion; +}; + +#define PCI_FEATURE_CONFIGURATION_COMPLETION_LIST_FROM_LINK(a) \ + CR (a, PCI_FEATURE_CONFIGURATION_COMPLETION_LIST, RootBridgeLink, PCI_FE= ATURE_CONFIGURATION_SIGNATURE) + +// +// Declaration of the internal sub-phases within the PCI Feature enumerati= on +// +typedef enum { + // + // initial phase in configuring the other PCI features to record the pri= mary + // root ports + // + PciFeatureRootBridgeScan, + // + // get the PCI device-specific platform policies and align with device c= apabilities + // + PciFeatureGetDevicePolicy, + // + // align all PCI nodes in the PCI heirarchical tree + // + PciFeatureSetupPhase, + // + // finally override to complete configuration of the PCI feature + // + PciFeatureConfigurationPhase, + // + // PCI feature configuration complete + // + PciFeatureConfigurationComplete + +}PCI_FEATURE_CONFIGURATION_PHASE; + + +/** + Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge, = to + configure the other PCI features. + + @param RootBridge A pointer to the PCI_IO_DEVICE. + + @retval EFI_SUCCESS The other PCI features configuration durin= g enumeration + of all the nodes of the PCI root bridge in= stance were + programmed in PCI-compliance pattern along= with the + device-specific policy, as applicable. + @retval EFI_UNSUPPORTED One of the override operation maong the no= des of + the PCI hierarchy resulted in a incompatib= le address + range. + @retval EFI_INVALID_PARAMETER The override operation is performed with i= nvalid input + parameters. +**/ +EFI_STATUS +EnumerateOtherPciFeatures ( + IN PCI_IO_DEVICE *RootBridge + ); + +/** + This routine is invoked from the Stop () interface for the EFI handle of= the + RootBridge. Free up its node of type PCI_FEATURE_CONFIGURATION_COMPLETIO= N_LIST. + + @param RootBridge A pointer to the PCI_IO_DEVICE +**/ +VOID +DestroyRootBridgePciFeaturesConfigCompletionList ( + IN PCI_IO_DEVICE *RootBridge + ); #endif --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49809): https://edk2.groups.io/g/devel/message/49809 Mute This Topic: https://groups.io/mt/40419696/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49810+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49810+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621019; cv=none; d=zoho.com; s=zohoarc; b=hli+GKBBS60sVYO+56zqBLXSFcvGGlBjADIsTTQ4fsDsZ45TbZwLs7YCuf1DXkEj4zzBrvAfpTImbpHHj4ukZFmIu3YOBELowKfC2o0cebUTJWrAX/2IRMES86F+vkrut0VxjIev28b5Owv77Dcp5i55fGMBmzoZWqMLIv5N3Uo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621019; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=BbzKLOQpiKsQpqDAKJLbUsKKyx2QX84b5ATnlHlie6g=; b=cM2AEhxlbgczp48Q5JCTEZ1oW0s6R08kjobLUImReTDG2Oz+mLQDFBSg3ErYER/PiCQiyasZPR6egDsQ8osuuvl6/bvi9+kiPesw5qfHZ34JFVPm3zcvN6VxTUim4TqS2eskzBqMVs58WuqE3vNN9lVnxPiJAPHoVmUQvpzzDZY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49810+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621019409127.4602168910601; Fri, 1 Nov 2019 08:10:19 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:18 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:18 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687119" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:15 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 06/12] PciBusDxe: Integration of setup for PCI feature enumeration Date: Fri, 1 Nov 2019 20:39:46 +0530 Message-Id: <20191101150952.3340-7-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621018; bh=4AcMQnZ6OhH/f1JVRzh4CpWdGGlb76vfuFlixyzPxnc=; h=Cc:Date:From:Reply-To:Subject:To; b=QVTNU+3COsAjwG8y9k0nKtNicQsOVwEHtPKmaREPqUqtrAxuUM+pqyDOgX41g1WbbtJ USIXmAlQ2c3zMRxaLlg+nRMl1BQlflyHBZF+GJ34FxSL/Cm2acSPnBpiw8GbHsWbHG/RC 4mjdUKlma8pMNY7YsOajyme4UUavF0QvuHo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The code changes are made to integrate the setup infrastructure for the PCI feature enumeration, in the last phase of the PCI Bus driver, after its registration and its option ROM loading phase is complete. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c | 11 +++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 15 ++++++++++++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 11 +++++++++++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c b/MdeModuleP= kg/Bus/Pci/PciBusDxe/PciDeviceSupport.c index 33a0e94..b839102 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciDeviceSupport.c @@ -8,6 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 #include "PciBus.h" +#include "PciFeatureSupport.h" =20 // // This device structure is serviced as a header. @@ -170,6 +171,8 @@ DestroyRootBridgeByHandle ( =20 if (Temp->Handle =3D=3D Controller) { =20 + DestroyRootBridgePciFeaturesConfigCompletionList (Temp); + RemoveEntryList (CurrentLink); =20 DestroyPciDeviceTree (Temp); @@ -818,6 +821,14 @@ StartPciDevicesOnBridge ( if (EFI_ERROR (Status) =3D=3D EFI_NOT_FOUND) { return Status; } else { + if (CheckOtherPciFeaturesPcd ()) { + // + // the late configuration of PCI features + // + Status =3D EnumerateOtherPciFeatures ( + RootBridge + ); + } // // finally start those PCI bridge port devices only // diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index ab0e096..9e6671d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -25,6 +25,19 @@ PRIMARY_ROOT_PORT_NODE *mPrimaryRoo= tPortList; **/ PCI_FEATURE_CONFIGURATION_COMPLETION_LIST *mPciFeaturesConfigurationComp= letionList =3D NULL; =20 +/** + Main routine to indicate platform selection of any of the other PCI feat= ures + to be configured by this driver + + @retval TRUE platform has selected the other PCI features to be confi= gured + FALSE platform has not selected any of the other PCI features +**/ +BOOLEAN +CheckOtherPciFeaturesPcd ( + ) +{ + return PcdGet32 (PcdOtherPciFeatures) ? TRUE : FALSE; +} =20 /** Main routine to indicate whether the platform has selected the Max_Paylo= ad_Size @@ -699,7 +712,7 @@ ProgramDevicePciFeatures ( IN PCI_IO_DEVICE *PciDevice ) { - EFI_STATUS Status; + EFI_STATUS Status =3D EFI_SUCCESS; =20 return Status; } diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h index b06c140..f92d008 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -138,6 +138,17 @@ typedef enum { }PCI_FEATURE_CONFIGURATION_PHASE; =20 =20 +/** + Main routine to indicate platform selection of any of the other PCI feat= ures + to be configured by this driver + + @retval TRUE platform has selected the other PCI features to be confi= gured + FALSE platform has not selected any of the other PCI features +**/ +BOOLEAN +CheckOtherPciFeaturesPcd ( + ); + /** Enumerate all the nodes of the specified root bridge or PCI-PCI Bridge, = to configure the other PCI features. --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49810): https://edk2.groups.io/g/devel/message/49810 Mute This Topic: https://groups.io/mt/40419700/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49811+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49811+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621021; cv=none; d=zoho.com; s=zohoarc; b=KNwiV/8PRExkCXpd9E3sc9sNOk3f6FUZqA1vgOSTs4rAJLqCdiexpLzOM4F8UOXFspyT84mZM7FUzxDjmB8noHaOgYKmuitYIvRF7iGaPThFTGcuBAfk3wxchiXX6NLepWoHVTfQYO4Vr0R1aXbN6fIZ1jqQDpiVpX1bEwNKjeA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621021; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OhhsxvNVeo+fewHMUDy5IT++bDZGqy0OmiKJM9zuid0=; b=cBL6NPwN/xW2niVo6J5+Om0nbJENr9C2v/Xvc+lyk5+9bqN6gzIgJRDFAzK7pgEuhP77AhCr6chJf5QwpbhnZY0QYzktIttrbcPEtJ6ndwqQ9rQJe88reKGBfS2FUHR3qmBxHiTaeMrRRsVvjuzg47SlMHK5aJ3XtfeZevBkNag= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49811+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621021183237.14150354237267; Fri, 1 Nov 2019 08:10:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:20 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:20 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687147" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:17 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/12] PciBusDxe: Record the PCI-Express Capability Structure Date: Fri, 1 Nov 2019 20:39:47 +0530 Message-Id: <20191101150952.3340-8-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621020; bh=nP7ZbRW7YXTPD1TCopJ4YMqPum5yJt8BOmVLULmhLFo=; h=Cc:Date:From:Reply-To:Subject:To; b=d5+tmJjEbhLKsxCfFpzLaExUhT+b5NtXjjgwkiWJEwaCmLqHqrFMGQyQgSpKvfNEA9D FR7soTEKHreXHWcFijm6d+GbN/VcfFeI0LyJv9cjsZkOKiZTr94rUSMjwt+tNJ7viNHp9 w5h5w8PTRVGtFrv8ECTSiaEn2jGt3E0rHWY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The code changes are made to record the PCI device's PCI-Express Capability Structure register set during early PCI enumeration phase. This data shall be used during PCI feature enumeration phase. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 6 +++++- MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 34 +++++++++++++++= +++++++------------ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 51 +++++++++++++++= ++++++++++++++++++++++++++++++++++++ 3 files changed, 78 insertions(+), 13 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 95a677b..dc29ef3 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -266,9 +266,13 @@ struct _PCI_IO_DEVICE { =20 BOOLEAN IsPciExp; // - // For SR-IOV + // For PCI Express Capability List Structure // UINT8 PciExpressCapabilityOffset; + PCI_CAPABILITY_PCIEXP PciExpStruct; + // + // For SR-IOV + // UINT32 AriCapabilityOffset; UINT32 SrIovCapabilityOffset; UINT32 MrIovCapabilityOffset; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index c7eafff..2343702 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -230,7 +230,7 @@ PciSearchDevice ( PciIoDevice =3D NULL; =20 DEBUG (( - EFI_D_INFO, + DEBUG_INFO, "PciBus: Discovered %s @ [%02x|%02x|%02x]\n", IS_PCI_BRIDGE (Pci) ? L"PPB" : IS_CARDBUS_BRIDGE (Pci) ? L"P2C" : @@ -397,7 +397,7 @@ DumpPpbPaddingResource ( =20 if ((Type !=3D PciBarTypeUnknown) && ((ResourceType =3D=3D PciBarTypeU= nknown) || (ResourceType =3D=3D Type))) { DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " Padding: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%lx\n= ", mBarTypeStr[Type], Descriptor->AddrRangeMax, Descriptor->AddrLen )); @@ -424,7 +424,7 @@ DumpPciBars ( } =20 DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " BAR[%d]: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%lx;\tO= ffset =3D 0x%02x\n", Index, mBarTypeStr[MIN (PciIoDevice->PciBar[Index].BarType, PciBarTy= peMaxType)], PciIoDevice->PciBar[Index].Alignment, PciIoDevice->PciBar[Index].Len= gth, PciIoDevice->PciBar[Index].Offset @@ -437,13 +437,13 @@ DumpPciBars ( } =20 DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " VFBAR[%d]: Type =3D %s; Alignment =3D 0x%lx;\tLength =3D 0x%lx;\tO= ffset =3D 0x%02x\n", Index, mBarTypeStr[MIN (PciIoDevice->VfPciBar[Index].BarType, PciBar= TypeMaxType)], PciIoDevice->VfPciBar[Index].Alignment, PciIoDevice->VfPciBar[Index]= .Length, PciIoDevice->VfPciBar[Index].Offset )); } - DEBUG ((EFI_D_INFO, "\n")); + DEBUG ((DEBUG_INFO, "\n")); } =20 /** @@ -1903,7 +1903,7 @@ PciParseBar ( // Fix the length to support some special 64 bit BAR // if (Value =3D=3D 0) { - DEBUG ((EFI_D_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 = BAR returns 0, change to 0xFFFFFFFF.\n")); + DEBUG ((DEBUG_INFO, "[PciBus]BAR probing for upper 32bit of MEM64 = BAR returns 0, change to 0xFFFFFFFF.\n")); Value =3D (UINT32) -1; } else { Value |=3D ((UINT32)(-1) << HighBitSet32 (Value)); @@ -2153,7 +2153,17 @@ CreatePciIoDevice ( NULL ); if (!EFI_ERROR (Status)) { - PciIoDevice->IsPciExp =3D TRUE; + PciIoDevice->IsPciExp =3D TRUE; + // + // read the PCI device's entire PCI Express Capability structure + // + PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint8, + PciIoDevice->PciExpressCapabilityOffset, + sizeof (PCI_CAPABILITY_PCIEXP) / sizeof (UINT8), + &PciIoDevice->PciExpStruct + ); } =20 if (PcdGetBool (PcdAriSupport)) { @@ -2206,7 +2216,7 @@ CreatePciIoDevice ( &Data32 ); DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " ARI: forwarding enabled for PPB[%02x:%02x:%02x]\n", Bridge->BusNumber, Bridge->DeviceNumber, @@ -2215,7 +2225,7 @@ CreatePciIoDevice ( } } =20 - DEBUG ((EFI_D_INFO, " ARI: CapOffset =3D 0x%x\n", PciIoDevice->AriCa= pabilityOffset)); + DEBUG ((DEBUG_INFO, " ARI: CapOffset =3D 0x%x\n", PciIoDevice->AriCa= pabilityOffset)); } } =20 @@ -2325,12 +2335,12 @@ CreatePciIoDevice ( PciIoDevice->ReservedBusNum =3D (UINT16)(EFI_PCI_BUS_OF_RID (LastVF)= - Bus + 1); =20 DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " SR-IOV: SupportedPageSize =3D 0x%x; SystemPageSize =3D 0x%x; Fir= stVFOffset =3D 0x%x;\n", SupportedPageSize, PciIoDevice->SystemPageSize >> 12, FirstVFOffset )); DEBUG (( - EFI_D_INFO, + DEBUG_INFO, " InitialVFs =3D 0x%x; ReservedBusNum =3D 0x%x; CapOffset = =3D 0x%x\n", PciIoDevice->InitialVFs, PciIoDevice->ReservedBusNum, PciIoDevice-= >SrIovCapabilityOffset )); @@ -2345,7 +2355,7 @@ CreatePciIoDevice ( NULL ); if (!EFI_ERROR (Status)) { - DEBUG ((EFI_D_INFO, " MR-IOV: CapOffset =3D 0x%x\n", PciIoDevice->Mr= IovCapabilityOffset)); + DEBUG ((DEBUG_INFO, " MR-IOV: CapOffset =3D 0x%x\n", PciIoDevice->Mr= IovCapabilityOffset)); } } =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index 9e6671d..df9e696 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -467,6 +467,14 @@ GetPciFeaturesConfigurationTable ( return EFI_SUCCESS; } =20 + // + // The PCI features configuration table is not built for RCiEP, return N= ULL + // + if (PciDevice->PciExpStruct.Capability.Bits.DevicePortType =3D=3D \ + PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) { + *PciFeaturesConfigTable =3D NULL; + return EFI_SUCCESS; + } =20 if (IsDevicePathEnd (PciDevice->DevicePath)){ // @@ -575,6 +583,45 @@ IsPciRootPortEmpty ( } =20 =20 +/** + helper routine to dump the PCIe Device Port Type +**/ +VOID +DumpDevicePortType ( + IN UINT8 DevicePortType + ) +{ + switch (DevicePortType){ + case PCIE_DEVICE_PORT_TYPE_PCIE_ENDPOINT: + DEBUG (( DEBUG_INFO, "PCIe endpoint found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_LEGACY_PCIE_ENDPOINT: + DEBUG (( DEBUG_INFO, "legacy PCI endpoint found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_ROOT_PORT: + DEBUG (( DEBUG_INFO, "PCIe Root Port found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT: + DEBUG (( DEBUG_INFO, "PCI switch upstream port found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT: + DEBUG (( DEBUG_INFO, "PCI switch downstream port found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_PCIE_TO_PCI_BRIDGE: + DEBUG (( DEBUG_INFO, "PCIe-PCI bridge found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_PCI_TO_PCIE_BRIDGE: + DEBUG (( DEBUG_INFO, "PCI-PCIe bridge found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT: + DEBUG (( DEBUG_INFO, "RCiEP found\n")); + break; + case PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_EVENT_COLLECTOR: + DEBUG (( DEBUG_INFO, "RC Event Collector found\n")); + break; + } +} + /** Process each PCI device as per the pltaform and device-specific policy. =20 @@ -590,8 +637,12 @@ SetupDevicePciFeatures ( ) { EFI_STATUS Status; + PCI_REG_PCIE_CAPABILITY PcieCap; OTHER_PCI_FEATURES_CONFIGURATION_TABLE *OtherPciFeaturesConfigTable; =20 + PcieCap.Uint16 =3D PciDevice->PciExpStruct.Capability.Uint16; + DumpDevicePortType ((UINT8)PcieCap.Bits.DevicePortType); + OtherPciFeaturesConfigTable =3D NULL; Status =3D GetPciFeaturesConfigurationTable (PciDevice, &OtherPciFeature= sConfigTable); if (EFI_ERROR( Status)) { --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49811): https://edk2.groups.io/g/devel/message/49811 Mute This Topic: https://groups.io/mt/40419704/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49812+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49812+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621024; cv=none; d=zoho.com; s=zohoarc; b=S/KaTDQDsX7T4zwDOx6trp5Ly/d4nI++6wSwBrdXY8RuShcHeymekSosNvk2cWPYVwifSeU1JbRqNHF1IuXKGE027DmTmhQGTKg+act/zRQNwObVF5UDCIqP1j6xSkspkb/8EUCFs+hLD3QQae5AHt+jN427Ggzr56WdskvcPRQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621024; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=pHfRBkZwkP6wfuwnnuSoG7m17c0ZiZgUudxRGznNQ7M=; b=Ir3htNga+OFQScaKmSZempHidpOkfVpC6vo+56RRsB4CSU4+2qWmvCq9Bbvk+9o1CKCAUdjI8+7ufxpwmorI2ETWFsyxnE5iFWtMKGwfm/qBcKPfQkdCRxQ8Bog6U3j29ZbCKuedD9Rw74wblWFR3fzfTPG+laucNzvh2HpqoJc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49812+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621024279492.69259584284725; Fri, 1 Nov 2019 08:10:24 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:23 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:23 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687185" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:20 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 08/12] PciBusDxe: New PCI feature Max_Payload_Size Date: Fri, 1 Nov 2019 20:39:48 +0530 Message-Id: <20191101150952.3340-9-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621023; bh=ArVpiFfxwfy/1KHtc4nd/hUrmdwl9aJmB46ho8e7X5c=; h=Cc:Date:From:Reply-To:Subject:To; b=R6WL2PD6U2QWCy8RhZRy/IzxqyxiCmntuXDNzxkWCWMV9G80rIb1m72uXZKRt89SEvH LYhvwRrXhoUXgz666MazQBsjtyTI77C/I7+lEqE3aMst0WPgLEQ5LCc+aSo9CSmjhCzNT 8zEnX0l23+yBkihjXPtXKcRS8AjqRXBicw0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The code changes are made to enable the configuration of new PCI feature Max_Payload_Size (MPS), which defines the data packet size for the PCI transactions, as per the PCI Base Specification 4 Revision 1. The code changes are made to calibrate highest common value that is appl- icable to all the child nodes originating from the primary parent root port of the root bridge instance. This programming of MPS is based on each PCI device's capability, and also its device-specific platform policy obtained using the new PCI Platform Protocol interface, defined in the below record:- https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 4 ++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 157 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 5 +++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 59 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 32 ++++++++++++++++= ++++++++++++++++ 5 files changed, 257 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index dc29ef3..065ae54 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -286,6 +286,10 @@ struct _PCI_IO_DEVICE { // This field is used to support this case. // UINT16 BridgeIoAlignment; + // + // Other PCI features setup flags + // + UINT8 SetupMPS; }; =20 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index df9e696..8fdaa05 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -582,6 +582,146 @@ IsPciRootPortEmpty ( return FALSE; } =20 +/** + The main routine which process the PCI feature Max_Payload_Size as per t= he + device-specific platform policy, as well as in complaince with the PCI B= ase + specification Revision 4, that aligns the value for the entire PCI heira= rchy + starting from its physical PCI Root port / Bridge device. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciConfigPhase for the PCI feature configuration = phases: + PciFeatureGetDevicePolicy & PciFea= tureSetupPhase + @param PciFeaturesConfigurationTable pointer to OTHER_PCI_FEATURES_CONF= IGURATION_TABLE + + @retval EFI_SUCCESS processing of PCI feature Max_Payl= oad_Size + is successful. +**/ +EFI_STATUS +ProcessMaxPayloadSize ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase, + IN OTHER_PCI_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTab= le + ) +{ + PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap; + UINT8 MpsValue; + + + PciDeviceCap.Uint32 =3D PciDevice->PciExpStruct.DeviceCapability.Uint32; + + if (PciConfigPhase =3D=3D PciFeatureGetDevicePolicy) { + if (SetupMpsAsPerDeviceCapability (PciDevice->SetupMPS)) { + MpsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize; + // + // no change to PCI Root ports without any endpoint device + // + if (IS_PCI_BRIDGE (&PciDevice->Pci) && PciDeviceCap.Bits.MaxPayloadS= ize) { + if (IsPciRootPortEmpty (PciDevice)) { + MpsValue =3D PCIE_MAX_PAYLOAD_SIZE_128B; + } + } + } else { + MpsValue =3D TranslateMpsSetupValueToPci (PciDevice->SetupMPS); + } + // + // discard device policy override request if greater than PCI device c= apability + // + PciDevice->SetupMPS =3D MIN ((UINT8)PciDeviceCap.Bits.MaxPayloadSize, = MpsValue); + } + + // + // align the MPS of the tree to the HCF with this device + // + if (PciFeaturesConfigurationTable) { + MpsValue =3D PciFeaturesConfigurationTable->Max_Payload_Size; + + MpsValue =3D MIN (PciDevice->SetupMPS, MpsValue); + PciDevice->SetupMPS =3D MIN (PciDevice->SetupMPS, MpsValue); + + if (MpsValue !=3D PciFeaturesConfigurationTable->Max_Payload_Size) { + PciFeaturesConfigurationTable->Max_Payload_Size =3D MpsValue; + } + } + + DEBUG (( DEBUG_INFO, + "MPS: %d [DevCap:%d],", + PciDevice->SetupMPS, PciDeviceCap.Bits.MaxPayloadSize + )); + return EFI_SUCCESS; +} + +/** + Overrides the PCI Device Control register MaxPayloadSize register field;= if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +OverrideMaxPayloadSize ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + PcieDev.Uint16 =3D 0; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + if (EFI_ERROR(Status)){ + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) read e= rror!", + Offset + )); + return Status; + } + if (PcieDev.Bits.MaxPayloadSize !=3D PciDevice->SetupMPS) { + PcieDev.Bits.MaxPayloadSize =3D PciDevice->SetupMPS; + DEBUG (( DEBUG_INFO, "MPS=3D%d,", PciDevice->SetupMPS)); + + // + // Raise TPL to high level to disable timer interrupt while the write = operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpStruct.DeviceControl.Uint16 =3D PcieDev.Uint16; + } else { + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) writ= e error!", + Offset + )); + } + } else { + DEBUG (( DEBUG_INFO, "No write of MPS=3D%d,", PciDevice->SetupMPS)); + } + + return Status; +} =20 /** helper routine to dump the PCIe Device Port Type @@ -669,6 +809,18 @@ SetupDevicePciFeatures ( } } =20 + DEBUG ((DEBUG_INFO, "[")); + // + // process the PCI device Max_Payload_Size feature + // + if (SetupMaxPayloadSize ()) { + Status =3D ProcessMaxPayloadSize ( + PciDevice, + PciConfigPhase, + OtherPciFeaturesConfigTable + ); + } + DEBUG ((DEBUG_INFO, "]\n")); return Status; } =20 @@ -765,6 +917,10 @@ ProgramDevicePciFeatures ( { EFI_STATUS Status =3D EFI_SUCCESS; =20 + if (SetupMaxPayloadSize ()) { + Status =3D OverrideMaxPayloadSize (PciDevice); + } + DEBUG (( DEBUG_INFO, "\n")); return Status; } =20 @@ -878,6 +1034,7 @@ AddPrimaryRootPortNode ( ); if (PciConfigTable) { PciConfigTable->ID =3D PortNumber; + PciConfigTable->Max_Payload_Size =3D PCIE_MAX_PAYLOAD_SIZE_= 4096B; } RootPortNode->OtherPciFeaturesConfigurationTable =3D PciConfigTable; =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h index f92d008..e5ac2a3 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -79,6 +79,11 @@ struct _OTHER_PCI_FEATURES_CONFIGURATION_TABLE { // Configuration Table ID // UINTN ID; + // + // to configure the PCI feature Maximum payload size to maintain the dat= a packet + // size among all the PCI devices in the PCI hierarchy + // + UINT8 Max_Payload_Size; }; =20 =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index 238959e..99badd6 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -356,6 +356,63 @@ GetPlatformPciOptionRom ( return Status; } =20 +/** + Helper routine to indicate whether the given PCI device specific policy = value + dictates to override the Max_Payload_Size to a particular value, or set = as per + device capability. + + @param MPS Input device-specific policy should be in terms of type + EFI_PCI_CONF_MAX_PAYLOAD_SIZE + + @retval TRUE Setup Max_Payload_Size as per device capability + FALSE override as per device-specific platform policy +**/ +BOOLEAN +SetupMpsAsPerDeviceCapability ( + IN UINT8 MPS +) +{ + if (MPS =3D=3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO) { + return TRUE; + } else { + return FALSE; + } +} + +/** + Routine to translate the given device-specific platform policy from type + EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base Spec= ification + Revision 4.0; for the PCI feature Max_Payload_Size. + + @param MPS Input device-specific policy should be in terms of type + EFI_PCI_CONF_MAX_PAYLOAD_SIZE + + @retval Range values for the Max_Payload_Size as defined in the = PCI + Base Specification 4.0 +**/ +UINT8 +TranslateMpsSetupValueToPci ( + IN UINT8 MPS +) +{ + switch (MPS) { + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_128B: + return PCIE_MAX_PAYLOAD_SIZE_128B; + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_256B: + return PCIE_MAX_PAYLOAD_SIZE_256B; + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_512B: + return PCIE_MAX_PAYLOAD_SIZE_512B; + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_1024B: + return PCIE_MAX_PAYLOAD_SIZE_1024B; + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_2048B: + return PCIE_MAX_PAYLOAD_SIZE_2048B; + case EFI_PCI_CONF_MAX_PAYLOAD_SIZE_4096B: + return PCIE_MAX_PAYLOAD_SIZE_4096B; + default: + return PCIE_MAX_PAYLOAD_SIZE_128B; + } +} + /** Generic routine to setup the PCI features as per its predetermined defau= lts. **/ @@ -364,6 +421,7 @@ SetupDefaultsDevicePlatformPolicy ( IN PCI_IO_DEVICE *PciDevice ) { + PciDevice->SetupMPS =3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO; } =20 /** @@ -399,6 +457,7 @@ GetPciDevicePlatformPolicyEx ( // // platform chipset policies are returned for this PCI device // + PciIoDevice->SetupMPS =3D PciPlatformExtendedPolicy.DeviceCtlMPS; =20 DEBUG (( DEBUG_INFO, "[device policy: platform]" diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h index a13131c..786c00d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h @@ -124,4 +124,36 @@ EFI_STATUS GetPciDevicePlatformPolicy ( IN PCI_IO_DEVICE *PciDevice ); + +/** + Helper routine to indicate whether the given PCI device specific policy = value + dictates to override the Max_Payload_Size to a particular value, or set = as per + device capability. + + @param MPS Input device-specific policy should be in terms of type + EFI_PCI_CONF_MAX_PAYLOAD_SIZE + + @retval TRUE Setup Max_Payload_Size as per device capability + FALSE override as per device-specific platform policy +**/ +BOOLEAN +SetupMpsAsPerDeviceCapability ( + IN UINT8 MPS +); + +/** + Routine to translate the given device-specific platform policy from type + EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base Spec= ification + Revision 4.0; for the PCI feature Max_Payload_Size. + + @param MPS Input device-specific policy should be in terms of type + EFI_PCI_CONF_MAX_PAYLOAD_SIZE + + @retval Range values for the Max_Payload_Size as defined in the = PCI + Base Specification 4.0 +**/ +UINT8 +TranslateMpsSetupValueToPci ( + IN UINT8 MPS +); #endif --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49812): https://edk2.groups.io/g/devel/message/49812 Mute This Topic: https://groups.io/mt/40419709/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49813+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49813+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621026; cv=none; d=zoho.com; s=zohoarc; b=mOENRg1A0lj8jmNsY99UxIe3AtBcJ6UIIaCjjqwcRWpBByssTo5LpnZFg/31URMtwCf2b0KP/i6YlVvJ29TVV4US7wnrLlEJf4yhomjQqs9PVJbKw71xGCDsTNEkzroR9K4R2N+XwFI7iwDE72lSmpFq+GuhQL3kcqgeB67qp1Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621026; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cyu9f70djuLprMSMZR2YJLFcAxjz8IJ2XfLjt2n0dn0=; b=MqlK9OitIih4Y69tK6xw9l7/aDaWfZHcfPU4lQWtS6IYPUKWHLDrOdyQlKwwCtQLM4TEzyg5oIzgjLyACGGbkdShoHDlmQtEqQRIwyVZqy0VCebxEet9cy0HCLBfGFuwuqVTwyQDlqdAsXhji76EHMtARY0jjkqFsl8FOOgiUSs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49813+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621026902271.9192608246933; Fri, 1 Nov 2019 08:10:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:26 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:25 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687213" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:22 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 09/12] PciBusDxe: New PCI feature Max_Read_Req_Size Date: Fri, 1 Nov 2019 20:39:49 +0530 Message-Id: <20191101150952.3340-10-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621026; bh=/isCMWBKui9ZJNEnYqSHOAMFcij3OvN+7iZ+r1Yk1bw=; h=Cc:Date:From:Reply-To:Subject:To; b=IyYdlbXygrr3ark8r1xeMNstYJU2Phddt4aT/9+Rjgk94RNHD6ZFelBNXUdGzNgL6us yWsfHm6yG9N/oiW/9IBWJzf/7bQFtIlRDR5f2GB/j3EF7myV4NcPyK2Cg/fSSjgaEHalb U+ipGvUBcMIc6eGSNPmckFDrs6puNk43AR4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2194 The code changes are made to enable the configuration of new PCI feature Max_Read_Req_Size (MRRS), which defines the memory read request size for the PCI transactions, as per the PCI Base Specification 4 Revision 1. The code changes are made to configure a common value that is applicable to all the child nodes originating from the primary parent root port of the root bridge instance, based on following 3 criteria:- (1) if platform defines MRRS device policy for any one PCI device in the tree than align all the devices in the PCI tree to that same value (2) if platform does not provide device policy for any of the devices in the PCI tree than setup the MRRS value equivalent to MPS value for all PCI devices to meet the criteria for the isochronous traffic (3) if platform does not provide device policy for any of the devices in the PCI tree and platform firmware policy has not selected the PCI bus driver to configure the MPS; than configuration of the MRRS is performed based on highest common value of the MPS advertized in the PCI device capability registers of the PCI devices This programming of MRRS gets the device-specific platform policy using the new PCI Platform Protocol interface, defined in the below record:- https://bugzilla.tianocore.org/show_bug.cgi?id=3D1954 Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 204 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 9 +++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 59 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h | 32 ++++++++++++++++= ++++++++++++++++ 5 files changed, 305 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 065ae54..38abd20 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -290,6 +290,7 @@ struct _PCI_IO_DEVICE { // Other PCI features setup flags // UINT8 SetupMPS; + UINT8 SetupMRRS; }; =20 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index 8fdaa05..614285f 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -650,6 +650,121 @@ ProcessMaxPayloadSize ( return EFI_SUCCESS; } =20 +/** + The main routine which process the PCI feature Max_Read_Req_Size as per = the + device-specific platform policy, as well as in complaince with the PCI B= ase + specification Revision 4, that aligns the value for the entire PCI heira= rchy + starting from its physical PCI Root port / Bridge device. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciConfigPhase for the PCI feature configuration = phases: + PciFeatureGetDevicePolicy & PciFea= tureSetupPhase + @param PciFeaturesConfigurationTable pointer to OTHER_PCI_FEATURES_CONF= IGURATION_TABLE + + @retval EFI_SUCCESS processing of PCI feature Max_Read= _Req_Size + is successful. +**/ +EFI_STATUS +ProcessMaxReadReqSize ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase, + IN OTHER_PCI_FEATURES_CONFIGURATION_TABLE *PciFeaturesConfigurationTab= le + ) +{ + PCI_REG_PCIE_DEVICE_CAPABILITY PciDeviceCap; + UINT8 MrrsValue; + + PciDeviceCap.Uint32 =3D PciDevice->PciExpStruct.DeviceCapability.Uint32; + + if (PciConfigPhase =3D=3D PciFeatureGetDevicePolicy) { + if (SetupMrrsAsPerDeviceCapability (PciDevice->SetupMRRS)) { + // + // The maximum read request size is not the data packet size of the = TLP, + // but the memory read request size, and set to the function as a re= questor + // to not exceed this limit. + // However, for the PCI device capable of isochronous traffic; this = memory read + // request size should not extend beyond the Max_Payload_Size. Thus,= in case if + // device policy return by platform indicates to set as per device c= apability + // than set as per Max_Payload_Size configuration value + // + if (SetupMaxPayloadSize ()) { + MrrsValue =3D PciDevice->SetupMPS; + } else { + // + // in case this driver is not required to configure the Max_Payloa= d_Size + // than consider programming HCF of the device capability's Max_Pa= yload_Size + // in this PCI hierarchy; thus making this an implementation speci= fic feature + // which the platform should avoid. For better results, the platfo= rm should + // make both the Max_Payload_Size & Max_Read_Request_Size to be co= nfigured + // by this driver + // + MrrsValue =3D (UINT8)PciDeviceCap.Bits.MaxPayloadSize; + } + } else { + // + // override as per platform based device policy + // + MrrsValue =3D TranslateMrrsSetupValueToPci (PciDevice->SetupMRRS); + // + // align this device's Max_Read_Request_Size value to the entire PCI= tree + // + if (PciFeaturesConfigurationTable) { + if (!PciFeaturesConfigurationTable->Lock_Max_Read_Request_Size) { + PciFeaturesConfigurationTable->Lock_Max_Read_Request_Size =3D TR= UE; + PciFeaturesConfigurationTable->Max_Read_Request_Size =3D MrrsVal= ue; + } else { + // + // in case of another user enforced value of MRRS within the sam= e tree, + // pick the smallest between the locked value and this value; to= set + // across entire PCI tree nodes + // + MrrsValue =3D MIN ( + MrrsValue, + PciFeaturesConfigurationTable->Max_Read_Request_Si= ze + ); + PciFeaturesConfigurationTable->Max_Read_Request_Size =3D MrrsVal= ue; + } + } + } + // + // align this device's Max_Read_Request_Size to derived configuration = value + // + PciDevice->SetupMRRS =3D MrrsValue; + + } + + // + // align the Max_Read_Request_Size of the PCI tree based on 3 conditions: + // first, if user defines MRRS for any one PCI device in the tree than a= lign + // all the devices in the PCI tree. + // second, if user override is not define for this PCI tree than setup t= he MRRS + // based on MPS value of the tree to meet the criteria for the isochrono= us + // traffic. + // third, if no user override, or platform firmware policy has not selec= ted + // this PCI bus driver to configure the MPS; than configure the MRRS to a + // highest common value of PCI device capability for the MPS found among= all + // the PCI devices in this tree + // + if (PciFeaturesConfigurationTable) { + if (PciFeaturesConfigurationTable->Lock_Max_Read_Request_Size) { + PciDevice->SetupMRRS =3D PciFeaturesConfigurationTable->Max_Read_Req= uest_Size; + } else { + if (SetupMaxPayloadSize ()) { + PciDevice->SetupMRRS =3D PciDevice->SetupMPS; + } else { + PciDevice->SetupMRRS =3D MIN ( + PciDevice->SetupMRRS, + PciFeaturesConfigurationTable->Max_Read_Re= quest_Size + ); + } + PciFeaturesConfigurationTable->Max_Read_Request_Size =3D PciDevice->= SetupMRRS; + } + } + DEBUG (( DEBUG_INFO, "MRRS: %d,", PciDevice->SetupMRRS)); + + return EFI_SUCCESS; +} + /** Overrides the PCI Device Control register MaxPayloadSize register field;= if the hardware value is different than the intended value. @@ -723,6 +838,79 @@ OverrideMaxPayloadSize ( return Status; } =20 +/** + Overrides the PCI Device Control register Max_Read_Req_Size register fie= ld; if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI controller. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +OverrideMaxReadReqSize ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + PcieDev.Uint16 =3D 0; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + if (EFI_ERROR(Status)){ + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) read e= rror!", + Offset + )); + return Status; + } + if (PcieDev.Bits.MaxReadRequestSize !=3D PciDevice->SetupMRRS) { + PcieDev.Bits.MaxReadRequestSize =3D PciDevice->SetupMRRS; + DEBUG (( DEBUG_INFO, "Max_Read_Request_Size: %d,", PciDevice->SetupMRR= S)); + + // + // Raise TPL to high level to disable timer interrupt while the write = operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpStruct.DeviceControl.Uint16 =3D PcieDev.Uint16; + } else { + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) writ= e error!", + Offset + )); + } + } else { + DEBUG (( DEBUG_INFO, "No write of MRRS=3D%d,", PciDevice->SetupMRRS)); + } + + return Status; +} + /** helper routine to dump the PCIe Device Port Type **/ @@ -820,6 +1008,17 @@ SetupDevicePciFeatures ( OtherPciFeaturesConfigTable ); } + // + // implementation specific rule:- the MRRS of any PCI device should be p= rocessed + // only after the MPS is processed for that device + // + if (SetupMaxReadReqSize ()) { + Status =3D ProcessMaxReadReqSize ( + PciDevice, + PciConfigPhase, + OtherPciFeaturesConfigTable + ); + } DEBUG ((DEBUG_INFO, "]\n")); return Status; } @@ -920,6 +1119,9 @@ ProgramDevicePciFeatures ( if (SetupMaxPayloadSize ()) { Status =3D OverrideMaxPayloadSize (PciDevice); } + if (SetupMaxReadReqSize ()) { + Status =3D OverrideMaxReadReqSize (PciDevice); + } DEBUG (( DEBUG_INFO, "\n")); return Status; } @@ -1035,6 +1237,8 @@ AddPrimaryRootPortNode ( if (PciConfigTable) { PciConfigTable->ID =3D PortNumber; PciConfigTable->Max_Payload_Size =3D PCIE_MAX_PAYLOAD_SIZE_= 4096B; + PciConfigTable->Max_Read_Request_Size =3D PCIE_MAX_READ_REQ_SIZE= _4096B; + PciConfigTable->Lock_Max_Read_Request_Size =3D FALSE; } RootPortNode->OtherPciFeaturesConfigurationTable =3D PciConfigTable; =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h index e5ac2a3..96ee6ff 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -84,6 +84,15 @@ struct _OTHER_PCI_FEATURES_CONFIGURATION_TABLE { // size among all the PCI devices in the PCI hierarchy // UINT8 Max_Payload_Size; + // + // to configure the PCI feature maximum read request size to maintain th= e memory + // requester size among all the PCI devices in the PCI hierarchy + // + UINT8 Max_Read_Request_Size; + // + // lock the Max_Read_Request_Size for the entire PCI tree of a root port + // + BOOLEAN Lock_Max_Read_Request_Size; }; =20 =20 diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index 99badd6..f032b5d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -379,6 +379,29 @@ SetupMpsAsPerDeviceCapability ( } } =20 +/** + Helper routine to indicate whether the given PCI device specific policy = value + dictates to override the Max_Read_Req_Size to a particular value, or set= as per + device capability. + + @param MRRS Input device-specific policy should be in terms of type + EFI_PCI_CONF_MAX_READ_REQ_SIZE + + @retval TRUE Setup Max_Read_Req_Size as per device capability + FALSE override as per device-specific platform policy +**/ +BOOLEAN +SetupMrrsAsPerDeviceCapability ( + IN UINT8 MRRS +) +{ + if (MRRS =3D=3D EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO) { + return TRUE; + } else { + return FALSE; + } +} + /** Routine to translate the given device-specific platform policy from type EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base Spec= ification @@ -413,6 +436,40 @@ TranslateMpsSetupValueToPci ( } } =20 +/** + Routine to translate the given device-specific platform policy from type + EFI_PCI_CONF_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Base Spe= cification + Revision 4.0; for the PCI feature Max_Read_Req_Size. + + @param MRRS Input device-specific policy should be in terms of type + EFI_PCI_CONF_MAX_READ_REQ_SIZE + + @retval Range values for the Max_Read_Req_Size as defined in the= PCI + Base Specification 4.0 +**/ +UINT8 +TranslateMrrsSetupValueToPci ( + IN UINT8 MRRS +) +{ + switch (MRRS) { + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_128B: + return PCIE_MAX_READ_REQ_SIZE_128B; + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_256B: + return PCIE_MAX_READ_REQ_SIZE_256B; + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_512B: + return PCIE_MAX_READ_REQ_SIZE_512B; + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_1024B: + return PCIE_MAX_READ_REQ_SIZE_1024B; + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_2048B: + return PCIE_MAX_READ_REQ_SIZE_2048B; + case EFI_PCI_CONF_MAX_READ_REQ_SIZE_4096B: + return PCIE_MAX_READ_REQ_SIZE_4096B; + default: + return PCIE_MAX_READ_REQ_SIZE_128B; + } +} + /** Generic routine to setup the PCI features as per its predetermined defau= lts. **/ @@ -422,6 +479,7 @@ SetupDefaultsDevicePlatformPolicy ( ) { PciDevice->SetupMPS =3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO; + PciDevice->SetupMRRS =3D EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO; } =20 /** @@ -458,6 +516,7 @@ GetPciDevicePlatformPolicyEx ( // platform chipset policies are returned for this PCI device // PciIoDevice->SetupMPS =3D PciPlatformExtendedPolicy.DeviceCtlMPS; + PciIoDevice->SetupMRRS =3D PciPlatformExtendedPolicy.DeviceCtlMRRS; =20 DEBUG (( DEBUG_INFO, "[device policy: platform]" diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h index 786c00d..8ed3836 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.h @@ -141,6 +141,22 @@ SetupMpsAsPerDeviceCapability ( IN UINT8 MPS ); =20 +/** + Helper routine to indicate whether the given PCI device specific policy = value + dictates to override the Max_Read_Req_Size to a particular value, or set= as per + device capability. + + @param MRRS Input device-specific policy should be in terms of type + EFI_PCI_CONF_MAX_READ_REQ_SIZE + + @retval TRUE Setup Max_Read_Req_Size as per device capability + FALSE override as per device-specific platform policy +**/ +BOOLEAN +SetupMrrsAsPerDeviceCapability ( + IN UINT8 MRRS +); + /** Routine to translate the given device-specific platform policy from type EFI_PCI_CONF_MAX_PAYLOAD_SIZE to HW-specific value, as per PCI Base Spec= ification @@ -156,4 +172,20 @@ UINT8 TranslateMpsSetupValueToPci ( IN UINT8 MPS ); + +/** + Routine to translate the given device-specific platform policy from type + EFI_PCI_CONF_MAX_READ_REQ_SIZE to HW-specific value, as per PCI Base Spe= cification + Revision 4.0; for the PCI feature Max_Read_Req_Size. + + @param MRRS Input device-specific policy should be in terms of type + EFI_PCI_CONF_MAX_READ_REQ_SIZE + + @retval Range values for the Max_Read_Req_Size as defined in the= PCI + Base Specification 4.0 +**/ +UINT8 +TranslateMrrsSetupValueToPci ( + IN UINT8 MRRS +); #endif --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49813): https://edk2.groups.io/g/devel/message/49813 Mute This Topic: https://groups.io/mt/40419712/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49814+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49814+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621029; cv=none; d=zoho.com; s=zohoarc; b=ALp2JQqE0NDgMSF2Y2Sc8Hl19+qsYq7ElliOQXzmZ8kZcgLGM0SygOmnd50/zEeF7M6nC33vZLG1M/K3KV51G4VdpE3rC6opb5YquheJmmRX2tlykcoseVB7VUfLEF9N9dJygWxvb53neXfoa3IbQcs67eT3vUt4IlXCd7lFZhQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621029; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=PKPWQ0f6NbuEJDip+UGbCtpMKtgXBEf5fpILjVwocps=; b=oRkHXUUeNQhKBcl3mHsLiq0hKAm3Gn6Wvi0RFJwgG2SRbqOq7lM1BZBd5GaUu6xynD/L65hN/At5aSPNTJM4mGp5RNSQ6/gQyLz/FssWeCQM7VG1dg593n32mAzqRXGX/OaL5tfr1cBtUNnHaAkot+AyJKtsozcP0h6oYKqhYM4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49814+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621029548746.1147330888481; Fri, 1 Nov 2019 08:10:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:28 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:28 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687246" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:25 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 10/12] PciBusDxe: New PCI feature Relax Ordering Date: Fri, 1 Nov 2019 20:39:50 +0530 Message-Id: <20191101150952.3340-11-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621028; bh=7RXN3kTDdsA+sUmOV7rS31AebUgnWWBERuDFCTbZHns=; h=Cc:Date:From:Reply-To:Subject:To; b=iyEgI3QUItKErjso2n/xi6h28NLJtx4QQQuaDSn7NNbp4I7tL1l9DaRfJ4/vn3tVY3l N5Xrcu/EChiSHsMRUZzOqEXJp1Iba6UuyrgkC0Wr9jdRXLn19XyWgmWxylf6qU/SWoSLQ qxmyP4fhskkOmNv6bTru6zzsycutplhxjJc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 The code changes are made to enable the configuration of new PCI feature Relax Ordering (OR), which enables the PCI function to initiate requests if it does not require strong write ordering for its transactions; as per the PCI Base Specification 4 Revision 1. The code changes are made to configure only those PCI devices which are requested to override by platform through the new PCI Platform protocol interface for device-specific policies. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 2 ++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 78 +++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h | 26 +++++++++++++++++= +++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 44 +++++++++++++++++= +++++++++++++++++++++++++++ 4 files changed, 150 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 38abd20..9f017b7 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -82,6 +82,7 @@ typedef enum { #include "PciHotPlugSupport.h" #include "PciLib.h" #include "PciPlatformSupport.h" +#include "PciFeatureSupport.h" =20 #define VGABASE1 0x3B0 #define VGALIMIT1 0x3BB @@ -291,6 +292,7 @@ struct _PCI_IO_DEVICE { // UINT8 SetupMPS; UINT8 SetupMRRS; + PCI_FEATURE_POLICY SetupRO; }; =20 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index 614285f..a60cb42 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -911,6 +911,81 @@ OverrideMaxReadReqSize ( return Status; } =20 +/** + Overrides the PCI Device Control register Relax Order register field; if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +OverrideRelaxOrder ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + PcieDev.Uint16 =3D 0; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + if (EFI_ERROR(Status)){ + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) read e= rror!", + Offset + )); + return Status; + } + if (PciDevice->SetupRO.Override + && PcieDev.Bits.RelaxedOrdering !=3D PciDevice->SetupRO.Act + ) { + PcieDev.Bits.RelaxedOrdering =3D PciDevice->SetupRO.Act; + DEBUG (( DEBUG_INFO, "RO=3D%d,", PciDevice->SetupRO.Act)); + + // + // Raise TPL to high level to disable timer interrupt while the write = operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpStruct.DeviceControl.Uint16 =3D PcieDev.Uint16; + } else { + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) writ= e error!", + Offset + )); + } + } else { + DEBUG (( DEBUG_INFO, "No write of RO,", PciDevice->SetupRO.Act)); + } + + return Status; +} + /** helper routine to dump the PCIe Device Port Type **/ @@ -1122,6 +1197,9 @@ ProgramDevicePciFeatures ( if (SetupMaxReadReqSize ()) { Status =3D OverrideMaxReadReqSize (PciDevice); } + if (SetupRelaxOrder ()) { + Status =3D OverrideRelaxOrder (PciDevice); + } DEBUG (( DEBUG_INFO, "\n")); return Status; } diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h index 96ee6ff..5044dc2 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.h @@ -40,6 +40,11 @@ typedef struct _OTHER_PCI_FEATURES_CONFIGURATION_TABLE = OTHER_PCI_FEATURES_CONFI // typedef struct _PCI_FEATURE_CONFIGURATION_COMPLETION_LIST PCI_FEATURE_CON= FIGURATION_COMPLETION_LIST; =20 +// +// define the data type for the PCI feature policy support +// +typedef struct _PCI_FEATURE_POLICY PCI_FEATURE_POLICY; + // // Signature value for the PCI Root Port node // @@ -151,6 +156,27 @@ typedef enum { =20 }PCI_FEATURE_CONFIGURATION_PHASE; =20 +// +// declaration for the data type to harbor the PCI feature policies +// +struct _PCI_FEATURE_POLICY { + // + // if set, it indicates the feature should be enabled + // if clear, it indicates the feature should be disabled + // + UINT8 Act : 1; + // + // this field will be specific to feature, it can be implementation spec= ific + // or it can be reserved and remain unused + // + UINT8 Support : 6; + // + // if set indicates override the feature policy defined by the members a= bove + // if clear it indicates that this feature policy should be ignored comp= letely + // this means the above two members should not be used + // + UINT8 Override : 1; +}; =20 /** Main routine to indicate platform selection of any of the other PCI feat= ures diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index f032b5d..f1e7039 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -470,6 +470,45 @@ TranslateMrrsSetupValueToPci ( } } =20 +/** + Routine to set the device-specific policy for the PCI feature Relax Orde= ring + + @param RelaxOrder value corresponding to data type EFI_PCI_CONF_RELA= X_ORDER + @param PciDevice A pointer to PCI_IO_DEVICE +**/ +VOID +SetDevicePolicyRelaxOrder ( + IN EFI_PCI_CONF_RELAX_ORDER RelaxOrder, + OUT PCI_IO_DEVICE *PciDevice + ) +{ + // + // implementation specific rules for the usage of PCI_FEATURE_POLICY mem= bers + // exclusively for the PCI Feature Relax Ordering (RO) + // + // .Override =3D 0 to skip this PCI feature RO for the PCI device + // .Override =3D 1 to program this RO PCI feature + // .Act =3D 1 to enable the RO in the PCI device + // .Act =3D 0 to disable the RO in the PCI device + // + switch (RelaxOrder) { + case EFI_PCI_CONF_RO_AUTO: + PciDevice->SetupRO.Override =3D 0; + break; + case EFI_PCI_CONF_RO_DISABLE: + PciDevice->SetupRO.Override =3D 1; + PciDevice->SetupRO.Act =3D 0; + break; + case EFI_PCI_CONF_RO_ENABLE: + PciDevice->SetupRO.Override =3D 1; + PciDevice->SetupRO.Act =3D 1; + break; + default: + PciDevice->SetupRO.Override =3D 0; + break; + } +} + /** Generic routine to setup the PCI features as per its predetermined defau= lts. **/ @@ -480,6 +519,7 @@ SetupDefaultsDevicePlatformPolicy ( { PciDevice->SetupMPS =3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO; PciDevice->SetupMRRS =3D EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO; + PciDevice->SetupRO.Override =3D 0; } =20 /** @@ -517,6 +557,10 @@ GetPciDevicePlatformPolicyEx ( // PciIoDevice->SetupMPS =3D PciPlatformExtendedPolicy.DeviceCtlMPS; PciIoDevice->SetupMRRS =3D PciPlatformExtendedPolicy.DeviceCtlMRRS; + // + // set device specific policy for Relax Ordering + // + SetDevicePolicyRelaxOrder (PciPlatformExtendedPolicy.DeviceCtlRelaxO= rder, PciIoDevice); =20 DEBUG (( DEBUG_INFO, "[device policy: platform]" --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49814): https://edk2.groups.io/g/devel/message/49814 Mute This Topic: https://groups.io/mt/40419720/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49815+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49815+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621031; cv=none; d=zoho.com; s=zohoarc; b=Ghmibrw5K1VpZTmi9xzCT3ypUEohHrCGGBJH7HMiLTMCaDww3NS7BnerVgPj5zwXZRcgK8HhiKx/9tsiP024R7WT7O0Q/SkjUjx+iq90/539A0xqM/bP6mS1rV98mvAegFIez91K2PZk0T1Uo7rcXcbVAZpOx4+iJWO/6wiAEdM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621031; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=HXtvL2MdqCG1SVmbPOrWjt2EwgAsUo0SEgSSv9oYPQ0=; b=DBoPxGuz+uo7ZqoUo3wNK6FV92u3ChzZRtGDKXenAUYFAWpuuhsXlXySzDk2Mtvd/IaCCKRb43bSXgwievXJAkRxaUmmw6dtTys+oQu2GtzkYkswn+79RYvAuiSO3uHm+67J93hRtX0ymAjn4cDNmsOSq23av4+h6/uKvYUxzp4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49815+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621031305968.6594205394357; Fri, 1 Nov 2019 08:10:31 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:30 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:30 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687281" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:27 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 11/12] PciBusDxe: New PCI feature No-Snoop Date: Fri, 1 Nov 2019 20:39:51 +0530 Message-Id: <20191101150952.3340-12-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621030; bh=m5pCxqmyhjGfHxRd/R18/XwUPbBiURZOcgcDwlkKS6g=; h=Cc:Date:From:Reply-To:Subject:To; b=EA9av8yuJCQRAuEiGc6q5ogrwdQlu3cdx3CL5U1nUsxWVeEP+iLnOU7sDKy067isKBr +D8acGesJv06U5Wae+RVLjpzb+xZGxC5bzoLffXcxTu8mN3qg/7Yd/Q+1+8RfvK0Qfpu8 6zbp9HMt/SuHeJdtkCE/4vYMX5DsOQBMbow= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 The code changes are made; as per the PCI Base Specification 4 Revision 1; to enable the configuration of new PCI feature No-Snoop (NS), which enables the PCI function to initiate requests if it does not require har- dware enforced cache-coherency for its transactions. The code changes are made to configure only those PCI devices which are requested to override by platform through the new PCI Platform protocol interface for device-specific policies. Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 78 +++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 45 +++++++++++++++++= ++++++++++++++++++++++++++++ 3 files changed, 124 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index 9f017b7..be1c341 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -293,6 +293,7 @@ struct _PCI_IO_DEVICE { UINT8 SetupMPS; UINT8 SetupMRRS; PCI_FEATURE_POLICY SetupRO; + PCI_FEATURE_POLICY SetupNS; }; =20 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index a60cb42..a7f0a2f 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -986,6 +986,81 @@ OverrideRelaxOrder ( return Status; } =20 +/** + Overrides the PCI Device Control register No-Snoop register field; if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +OverrideNoSnoop ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL PcieDev; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + PcieDev.Uint16 =3D 0; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + if (EFI_ERROR(Status)){ + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) read e= rror!", + Offset + )); + return Status; + } + if (PciDevice->SetupRO.Override + && PcieDev.Bits.NoSnoop !=3D PciDevice->SetupNS.Act + ) { + PcieDev.Bits.NoSnoop =3D PciDevice->SetupNS.Act; + DEBUG (( DEBUG_INFO, "NS=3D%d", PciDevice->SetupNS.Act)); + + // + // Raise TPL to high level to disable timer interrupt while the write = operation completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &PcieDev.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpStruct.DeviceControl.Uint16 =3D PcieDev.Uint16; + } else { + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl register (0x%x) writ= e error!", + Offset + )); + } + } else { + DEBUG (( DEBUG_INFO, "No write of NS,", PciDevice->SetupRO.Act)); + } + + return Status; +} + /** helper routine to dump the PCIe Device Port Type **/ @@ -1200,6 +1275,9 @@ ProgramDevicePciFeatures ( if (SetupRelaxOrder ()) { Status =3D OverrideRelaxOrder (PciDevice); } + if (SetupNoSnoop ()) { + Status =3D OverrideNoSnoop (PciDevice); + } DEBUG (( DEBUG_INFO, "\n")); return Status; } diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index f1e7039..47295cd 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -509,6 +509,46 @@ SetDevicePolicyRelaxOrder ( } } =20 +/** + Routine to set the device-specific policy for the PCI feature No-Snoop e= nable + or disable + + @param NoSnoop value corresponding to data type EFI_PCI_CONF_NO_S= NOOP + @param PciDevice A pointer to PCI_IO_DEVICE +**/ +VOID +SetDevicePolicyNoSnoop ( + IN EFI_PCI_CONF_NO_SNOOP NoSnoop, + OUT PCI_IO_DEVICE *PciDevice + ) +{ + // + // implementation specific rules for the usage of PCI_FEATURE_POLICY mem= bers + // exclusively for the PCI Feature No-Snoop + // + // .Override =3D 0 to skip this PCI feature No-Snoop for the PCI device + // .Override =3D 1 to program this No-Snoop PCI feature + // .Act =3D 1 to enable the No-Snoop in the PCI device + // .Act =3D 0 to disable the No-Snoop in the PCI device + // + switch (NoSnoop) { + case EFI_PCI_CONF_NS_AUTO: + PciDevice->SetupNS.Override =3D 0; + break; + case EFI_PCI_CONF_NS_DISABLE: + PciDevice->SetupNS.Override =3D 1; + PciDevice->SetupNS.Act =3D 0; + break; + case EFI_PCI_CONF_NS_ENABLE: + PciDevice->SetupNS.Override =3D 1; + PciDevice->SetupNS.Act =3D 1; + break; + default: + PciDevice->SetupNS.Override =3D 0; + break; + } +} + /** Generic routine to setup the PCI features as per its predetermined defau= lts. **/ @@ -520,6 +560,7 @@ SetupDefaultsDevicePlatformPolicy ( PciDevice->SetupMPS =3D EFI_PCI_CONF_MAX_PAYLOAD_SIZE_AUTO; PciDevice->SetupMRRS =3D EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO; PciDevice->SetupRO.Override =3D 0; + PciDevice->SetupNS.Override =3D 0; } =20 /** @@ -561,6 +602,10 @@ GetPciDevicePlatformPolicyEx ( // set device specific policy for Relax Ordering // SetDevicePolicyRelaxOrder (PciPlatformExtendedPolicy.DeviceCtlRelaxO= rder, PciIoDevice); + // + // set the device specific policy for No-Snoop + // + SetDevicePolicyNoSnoop (PciPlatformExtendedPolicy.DeviceCtlNoSnoop, = PciIoDevice); =20 DEBUG (( DEBUG_INFO, "[device policy: platform]" --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49815): https://edk2.groups.io/g/devel/message/49815 Mute This Topic: https://groups.io/mt/40419724/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 26 00:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49816+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49816+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572621034; cv=none; d=zoho.com; s=zohoarc; b=omd7e3TiU3/D6Ey2syVGl+JWXqfx5kLGiJwqWKh31DuEbw61bZ18VJ+d9Cq/AP3U2UsaWZclu3oSkSZBaKYRaGOJVWpKQ4UQqCi3IlYDafWxnr99h6iJoOatHFULqr6rWo+DfL5qaUIWcb7EYaG3mW8d4ZTYXv24WZ7QKiwMtmQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572621034; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=r/ix0hmBM0od4XEquMTC+o8/P/RSZ13DVAseU+PXBPQ=; b=L0rTqAgVxyCS2sEGirJbBCPxLWVGZRAq69Emfo/218Fh1hdS4bOyciHiC8ytuai7om8e2o/Ao3nDLD8BGyRb/6I+HSjEmY22QM49iKuty6OCTveO43cTqhrw1CaGAVOy/8ObHlbYbJp2iYxt3Bl6A+8lHf95hNOa0Q1Sqzg+Nsw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49816+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572621034087681.1535919091076; Fri, 1 Nov 2019 08:10:34 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id aaaaYY1788612xaaaaaaaaaa; Fri, 01 Nov 2019 08:10:33 -0700 X-Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5162.1572621016444543116 for ; Fri, 01 Nov 2019 08:10:32 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Nov 2019 08:10:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,256,1569308400"; d="scan'208";a="194687345" X-Received: from pidsbabios005.gar.corp.intel.com ([10.223.9.183]) by orsmga008.jf.intel.com with ESMTP; 01 Nov 2019 08:10:30 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Jian J Wang , Hao A Wu , Ray Ni Subject: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/12] PciBusDxe: New PCI feature Completion Timeout Date: Fri, 1 Nov 2019 20:39:52 +0530 Message-Id: <20191101150952.3340-13-ashraf.javeed@intel.com> In-Reply-To: <20191101150952.3340-1-ashraf.javeed@intel.com> References: <20191101150952.3340-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com X-Gm-Message-State: aaaaaaaaaaaaaaaaaaaaaaaax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572621033; bh=shmkZ7QqnbIEPYV8v5vAhKLpZTJYFwswTF7RpGOF5+k=; h=Cc:Date:From:Reply-To:Subject:To; b=p5nmhQGv/OOTToFUuB0BDchQxVnnreHQcyI1EIQOnQWNCHHcAiK2wsChOYVCrTpix0J CG1smSVHcIfzN+Z0tXNgDfuhF+c1pPs2Ja+4T7V4ci5kUPEbgBRnXNZ8/vNbgM9r+XR+C NQrbLMGqMa1gQOLj8uAE2Ad9Km1vAa9T15E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2313 The code changes are made; as per the PCI Base Specification 4 Revision 1; to enable the configuration of new PCI feature Completion Timeout (CTO), which enables the PCI function to wait on programmed duration for its transactions before timeout, or disable its detection mechanism. The code changes are made to configure only those PCI devices which are requested to override by platform through the new PCI Platform protocol interface for device-specific policies. The changes are made to also com- ply with the device-specific capability attributes. The code follows the below implementation specific rules in case the req- uested platform policy does not match with the device-specific capability attributes:- (1) if device is capable of Range A only and if platform ask for any of ranges B, C, D; than this implementation will only program the default range value for the duration of 50us to 50ms (2) if device is capable of Range B, or range B & C, or Ranges B, C & D only and if the platform ask for the Range A; than this implementation will only program the default range value for the duration of 50us to 50ms (3) if the device is capable of Range B only, or the ranges A & B; and if the platform ask for Range C, or Range D values, than this implement- ation will only program the Range B value for the duration of 65ms to 210ms (4) if the device is capable of Ranges B & C, or Ranges A, B, and C; and if the platform ask for Range D values; than this implementation will only program the Range C for the duration of 1s to 3.5s Signed-off-by: Ashraf Javeed Cc: Jian J Wang Cc: Hao A Wu Cc: Ray Ni --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c | 413 ++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c | 84 ++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 498 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index be1c341..b6ec14f 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -294,6 +294,7 @@ struct _PCI_IO_DEVICE { UINT8 SetupMRRS; PCI_FEATURE_POLICY SetupRO; PCI_FEATURE_POLICY SetupNS; + PCI_FEATURE_POLICY SetupCTO; }; =20 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c b/MdeModule= Pkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c index a7f0a2f..ba0de0d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciFeatureSupport.c @@ -765,6 +765,294 @@ ProcessMaxReadReqSize ( return EFI_SUCCESS; } =20 +/** + To determine the CTO Range A values + + @param CtoValue input CTO range value from 0 to 14 + @retval TRUE the given CTO value belongs to Range A + FALSE the given value does not belong to Range A +**/ +BOOLEAN +IsCtoRangeA ( + IN UINT8 CtoValue + ) +{ + switch (CtoValue) { + case PCIE_COMPLETION_TIMEOUT_50US_100US: + case PCIE_COMPLETION_TIMEOUT_1MS_10MS: + return TRUE; + } + return FALSE; +} + +/** + To determine the CTO Range B values + + @param CtoValue input CTO range value from 0 to 14 + @retval TRUE the given CTO value belongs to Range B + FALSE the given value does not belong to Range B +**/ +BOOLEAN +IsCtoRangeB ( + IN UINT8 CtoValue + ) +{ + switch (CtoValue) { + case PCIE_COMPLETION_TIMEOUT_16MS_55MS: + case PCIE_COMPLETION_TIMEOUT_65MS_210MS: + return TRUE; + } + return FALSE; +} + +/** + To determine the CTO Range C values + + @param CtoValue input CTO range value from 0 to 14 + @retval TRUE the given CTO value belongs to Range C + FALSE the given value does not belong to Range C +**/ +BOOLEAN +IsCtoRangeC ( + IN UINT8 CtoValue + ) +{ + switch (CtoValue) { + case PCIE_COMPLETION_TIMEOUT_260MS_900MS: + case PCIE_COMPLETION_TIMEOUT_1S_3_5S: + return TRUE; + } + return FALSE; +} + +/** + To determine the CTO Range D values + + @param CtoValue input CTO range value from 0 to 14 + @retval TRUE the given CTO value belongs to Range D + FALSE the given value does not belong to Range D +**/ +BOOLEAN +IsCtoRangeD ( + IN UINT8 CtoValue + ) +{ + switch (CtoValue) { + case PCIE_COMPLETION_TIMEOUT_4S_13S: + case PCIE_COMPLETION_TIMEOUT_17S_64S: + return TRUE; + } + return FALSE; +} + +/** + The main routine which process the PCI feature Completion Timeout as per= the + device-specific platform policy, as well as in complaince with the PCI B= ase + specification Revision 4. + + @param PciDevice A pointer to the PCI_IO_DEVICE. + @param PciConfigPhase for the PCI feature configuration = phases: + PciFeatureGetDevicePolicy & PciFea= tureSetupPhase + + @retval EFI_SUCCESS processing of PCI feature CTO is s= uccessful. +**/ +EFI_STATUS +ProcessCompletionTimeout ( + IN PCI_IO_DEVICE *PciDevice, + IN PCI_FEATURE_CONFIGURATION_PHASE PciConfigPhase + ) +{ + PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2; + UINT8 CtoRangeValue; + + if (PciConfigPhase !=3D PciFeatureGetDevicePolicy) { + // + // no reprocessing required for device CTO configuration + // + return EFI_SUCCESS; + } + + if (!PciDevice->SetupCTO.Override) { + // + // No override of CTO is required for this device + // + return EFI_SUCCESS; + } + + // + // determine the CTO range values as per its device capability register + // + DeviceCap2.Uint32 =3D PciDevice->PciExpStruct.DeviceCapability2.Uint32; + if (!DeviceCap2.Bits.CompletionTimeoutRanges + && !DeviceCap2.Bits.CompletionTimeoutDisable + ) { + // + // device does not support the CTO mechanism, hence no override is app= licable + // + return EFI_SUCCESS; + } + + // + // override the device CTO values if applicable + // + if (PciDevice->SetupCTO.Act) { + // + // program the CTO range values + // + if (DeviceCap2.Bits.CompletionTimeoutRanges) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; + // + // in case if the supported CTO range and the requirement from platf= orm + // policy does not match, than the CTO range setting would be based = on + // this driver's implementation specific, and its rules are as follo= ws:- + // + // if device is capable of Range A only and if platform ask for any = of + // ranges B, C, D; than this implementation will only program the de= fault + // range value for the duration of 50us to 50ms. + // + // if device is capable of Range B, or range B & C, or Ranges B, C &= D only + // and if the platform ask for the Range A; than this implementation= will + // only program the default range value for the duration of 50us to = 50ms. + // + // if the device is capable of Range B only, or the ranges A & B; an= d the + // platform ask for Range C, or Range D values, than this implementa= tion + // will only program the Range B value for the duration of 65ms to 2= 10ms. + // + // if the device is capable of Ranges B & C, or Ranges A, B, and C; = and + // if the platform ask for Range D values; than this implementation = will + // only program the Range C for the duration of 1s to 3.5s. + // + + switch (DeviceCap2.Bits.CompletionTimeoutRanges) { + case PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED: + if (IsCtoRangeA (PciDevice->SetupCTO.Support)) { + CtoRangeValue =3D PciDevice->SetupCTO.Support; + } + // + // if device is capable of Range A only and if platform ask for = any of + // ranges B, C, D; than this implementation will only program th= e default + // range value for the duration of 50us to 50ms. + // + if (IsCtoRangeB (PciDevice->SetupCTO.Support) + || IsCtoRangeC (PciDevice->SetupCTO.Support) + || IsCtoRangeD (PciDevice->SetupCTO.Support) + ) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; + } + break; + + case PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED: + // + // if device is capable of Range B, or range B & C, or Ranges B,= C & D only + // and if the platform ask for the Range A; than this implementa= tion will + // only program the default range value for the duration of 50us= to 50ms. + // + if (IsCtoRangeA (PciDevice->SetupCTO.Support)) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; + } + + if (IsCtoRangeB (PciDevice->SetupCTO.Support)) { + CtoRangeValue =3D PciDevice->SetupCTO.Support; + } + // + // if the device is capable of Range B only, or the ranges A & B= ; and the + // platform ask for Range C, or Range D values, than this implem= entation + // will only program the Range B value for the duration of 65ms = to 210ms. + // + if (IsCtoRangeC (PciDevice->SetupCTO.Support) + || IsCtoRangeD (PciDevice->SetupCTO.Support) + ) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS; + } + break; + + case PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED: + if (IsCtoRangeA (PciDevice->SetupCTO.Support)) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; + } + + if (IsCtoRangeB (PciDevice->SetupCTO.Support) + || IsCtoRangeC (PciDevice->SetupCTO.Support) + ) { + CtoRangeValue =3D PciDevice->SetupCTO.Support; + } + // + // if the device is capable of Ranges B & C, or Ranges A, B, and= C; and + // if the platform ask for Range D values; than this implementat= ion will + // only program the Range C for the duration of 1s to 3.5s. + // + if (IsCtoRangeD (PciDevice->SetupCTO.Support)) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S; + } + break; + + case PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED: + if (IsCtoRangeA (PciDevice->SetupCTO.Support)) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; + } + if (IsCtoRangeB (PciDevice->SetupCTO.Support) + || IsCtoRangeC (PciDevice->SetupCTO.Support) + || IsCtoRangeD (PciDevice->SetupCTO.Support) + ) { + CtoRangeValue =3D PciDevice->SetupCTO.Support; + } + break; + + case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED: + if (IsCtoRangeA (PciDevice->SetupCTO.Support) + || IsCtoRangeB (PciDevice->SetupCTO.Support) + ) { + CtoRangeValue =3D PciDevice->SetupCTO.Support; + } + if (IsCtoRangeC (PciDevice->SetupCTO.Support) + || IsCtoRangeD (PciDevice->SetupCTO.Support) + ) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS; + } + break; + + case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED: + if (IsCtoRangeA (PciDevice->SetupCTO.Support) + || IsCtoRangeB (PciDevice->SetupCTO.Support) + || IsCtoRangeC (PciDevice->SetupCTO.Support) + ) { + CtoRangeValue =3D PciDevice->SetupCTO.Support; + } + if (IsCtoRangeD (PciDevice->SetupCTO.Support)) { + CtoRangeValue =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S; + } + break; + + case PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED: + if (IsCtoRangeA (PciDevice->SetupCTO.Support) + || IsCtoRangeB (PciDevice->SetupCTO.Support) + || IsCtoRangeC (PciDevice->SetupCTO.Support) + || IsCtoRangeD (PciDevice->SetupCTO.Support) + ) { + CtoRangeValue =3D PciDevice->SetupCTO.Support; + } + break; + + default: + DEBUG (( + DEBUG_ERROR, "Invalid CTO range: %d\n", + DeviceCap2.Bits.CompletionTimeoutRanges + )); + return EFI_INVALID_PARAMETER; + } + + if (PciDevice->SetupCTO.Support !=3D CtoRangeValue) { + PciDevice->SetupCTO.Support =3D CtoRangeValue; + } + } + DEBUG (( DEBUG_INFO, "CTO enable: %d, CTO range: 0x%x,", + PciDevice->SetupCTO.Act, + PciDevice->SetupCTO.Support + )); + } + return EFI_SUCCESS; +} + /** Overrides the PCI Device Control register MaxPayloadSize register field;= if the hardware value is different than the intended value. @@ -1061,6 +1349,119 @@ OverrideNoSnoop ( return Status; } =20 +/** + Overrides the PCI Device Control2 register Completion Timeout range; if + the hardware value is different than the intended value. + + @param PciDevice A pointer to the PCI_IO_DEVICE instance. + + @retval EFI_SUCCESS The data was read from or written to the P= CI device. + @retval EFI_UNSUPPORTED The address range specified by Offset, Wid= th, and Count is not + valid for the PCI configuration header of = the PCI controller. + @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid. + +**/ +EFI_STATUS +OverrideCompletionTimeout ( + IN PCI_IO_DEVICE *PciDevice + ) +{ + PCI_REG_PCIE_DEVICE_CONTROL2 DeviceCtl2; + PCI_REG_PCIE_DEVICE_CAPABILITY2 DeviceCap2; + UINT32 Offset; + EFI_STATUS Status; + EFI_TPL OldTpl; + + if (!PciDevice->SetupCTO.Override) { + // + // No override of CTO is required for this device + // + DEBUG (( DEBUG_INFO, "CTO skipped,")); + return EFI_SUCCESS; + } + + // + // to program the CTO range values, determine in its device capability r= egister + // + DeviceCap2.Uint32 =3D PciDevice->PciExpStruct.DeviceCapability2.Uint32; + if (DeviceCap2.Bits.CompletionTimeoutRanges + || DeviceCap2.Bits.CompletionTimeoutDisable) { + // + // device supports the CTO mechanism + // + DeviceCtl2.Uint16 =3D 0; + Offset =3D PciDevice->PciExpressCapabilityOffset + + OFFSET_OF (PCI_CAPABILITY_PCIEXP, DeviceControl2); + Status =3D PciDevice->PciIo.Pci.Read ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &DeviceCtl2.Uint16 + ); + if (EFI_ERROR(Status)){ + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl2 register (0x%x) rea= d error!", + Offset + )); + return Status; + } + } else { + // + // device does not support the CTO mechanism, hence no override perfor= med + // + DEBUG (( DEBUG_INFO, "CTO n/a,")); + return EFI_SUCCESS; + } + + // + // override the device CTO values if applicable + // + if (PciDevice->SetupCTO.Act) { + // + // program the CTO range values + // + if (PciDevice->SetupCTO.Support !=3D DeviceCtl2.Bits.CompletionTimeout= Value) { + DeviceCtl2.Bits.CompletionTimeoutValue =3D PciDevice->SetupCTO.Suppo= rt; + } + } else { + // + // disable the CTO mechanism in device + // + DeviceCtl2.Bits.CompletionTimeoutValue =3D 0; + DeviceCtl2.Bits.CompletionTimeoutDisable =3D 1; + } + DEBUG (( DEBUG_INFO, "CTO disable: %d, CTO range: 0x%x,", + DeviceCtl2.Bits.CompletionTimeoutDisable, + DeviceCtl2.Bits.CompletionTimeoutValue + )); + + // + // Raise TPL to high level to disable timer interrupt while the write op= eration completes + // + OldTpl =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + + Status =3D PciDevice->PciIo.Pci.Write ( + &PciDevice->PciIo, + EfiPciIoWidthUint16, + Offset, + 1, + &DeviceCtl2.Uint16 + ); + // + // Restore TPL to its original level + // + gBS->RestoreTPL (OldTpl); + + if (!EFI_ERROR(Status)) { + PciDevice->PciExpStruct.DeviceControl2.Uint16 =3D DeviceCtl2.Uint16; + } else { + DEBUG (( DEBUG_ERROR, "Unexpected DeviceControl2 register (0x%x) write= error!", + Offset + )); + } + return Status; +} + /** helper routine to dump the PCIe Device Port Type **/ @@ -1169,6 +1570,15 @@ SetupDevicePciFeatures ( OtherPciFeaturesConfigTable ); } + // + // process the PCI device CTO range values to be configured + // + if (SetupCompletionTimeout ()) { + Status =3D ProcessCompletionTimeout ( + PciDevice, + PciConfigPhase + ); + } DEBUG ((DEBUG_INFO, "]\n")); return Status; } @@ -1278,6 +1688,9 @@ ProgramDevicePciFeatures ( if (SetupNoSnoop ()) { Status =3D OverrideNoSnoop (PciDevice); } + if (SetupCompletionTimeout()) { + Status =3D OverrideCompletionTimeout (PciDevice); + } DEBUG (( DEBUG_INFO, "\n")); return Status; } diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c index 47295cd..7ee0d7d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciPlatformSupport.c @@ -549,6 +549,85 @@ SetDevicePolicyNoSnoop ( } } =20 +/** + Routine to set the device-specific policy for the PCI feature CTO value = range + or disable + + @param CtoSupport value corresponding to data type EFI_PCI_CONF_CTO_= SUPPORT + @param PciDevice A pointer to PCI_IO_DEVICE +**/ +VOID +SetDevicePolicyCTO ( + IN EFI_PCI_CONF_CTO_SUPPORT CtoSupport, + OUT PCI_IO_DEVICE *PciDevice +) +{ + // + // implementation specific rules for the usage of PCI_FEATURE_POLICY mem= bers + // exclusively for the PCI Feature CTO + // + // .Override =3D 0 to skip this PCI feature CTO for the PCI device + // .Override =3D 1 to program this CTO PCI feature + // .Act =3D 1 to program the CTO range as per given device policy i= n .Support + // .Act =3D 0 to disable the CTO mechanism in the PCI device, CTO s= et to default range + // + switch (CtoSupport) { + case EFI_PCI_CONF_CTO_AUTO: + PciDevice->SetupCTO.Override =3D 0; + break; + case EFI_PCI_CONF_CTO_DEFAULT: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; + break; + case EFI_PCI_CONF_CTO_RANGE_A1: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_100US; + break; + case EFI_PCI_CONF_CTO_RANGE_A2: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_1MS_10MS; + break; + case EFI_PCI_CONF_CTO_RANGE_B1: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_16MS_55MS; + break; + case EFI_PCI_CONF_CTO_RANGE_B2: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_65MS_210MS; + break; + case EFI_PCI_CONF_CTO_RANGE_C1: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_260MS_900MS; + break; + case EFI_PCI_CONF_CTO_RANGE_C2: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_1S_3_5S; + break; + case EFI_PCI_CONF_CTO_RANGE_D1: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_4S_13S; + break; + case EFI_PCI_CONF_CTO_RANGE_D2: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 1; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_17S_64S; + break; + case EFI_PCI_CONF_CTO_DET_DISABLE: + PciDevice->SetupCTO.Override =3D 1; + PciDevice->SetupCTO.Act =3D 0; + PciDevice->SetupCTO.Support =3D PCIE_COMPLETION_TIMEOUT_50US_50MS; + break; + } +} + /** Generic routine to setup the PCI features as per its predetermined defau= lts. **/ @@ -561,6 +640,7 @@ SetupDefaultsDevicePlatformPolicy ( PciDevice->SetupMRRS =3D EFI_PCI_CONF_MAX_READ_REQ_SIZE_AUTO; PciDevice->SetupRO.Override =3D 0; PciDevice->SetupNS.Override =3D 0; + PciDevice->SetupCTO.Override =3D 0; } =20 /** @@ -606,6 +686,10 @@ GetPciDevicePlatformPolicyEx ( // set the device specific policy for No-Snoop // SetDevicePolicyNoSnoop (PciPlatformExtendedPolicy.DeviceCtlNoSnoop, = PciIoDevice); + // + // set the device specific policy for Completion Timeout (CTO) + // + SetDevicePolicyCTO (PciPlatformExtendedPolicy.CTOsupport, PciIoDevic= e); =20 DEBUG (( DEBUG_INFO, "[device policy: platform]" --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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