From nobody Mon Feb 9 17:23:39 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49753+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49753+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572517705; cv=none; d=zoho.com; s=zohoarc; b=INkLpGO1KtpntGNo4BJw7RQzvB/VD0RcAnAkeAWBvQ/vCelkRgkoG/lCZfdu9GzaLb6RqetRAsFROdcC0t+vDsSCP9HAcEYAX6AFqdLhVqN6x2ScD8IFePRvTdrBPvb9vyT9yKdoUI9P00SBoVFMWzxzFEMkRsTFWty7D+2xkgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572517705; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=clNvx3xtsREOOFsf9Msb0qjSqzCMlLFfsz13DTlaABQ=; b=fXXJO/x1DGQJEnoiG8v69H2JAghDLx83LsaKGYwRP8WO0+fGt2glZzq2NjxGsTgFTSs6UYAftEwqDVwPaB7ncevrlUKewTld/aMbS1mOrzY5M4FQMeFd4TBeRYlsRMk/gG+grTCq9zcxW9z7OnmhANooqhQkU2I1rrqxgO6pgmI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49753+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572517705780785.6441125285719; Thu, 31 Oct 2019 03:28:25 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id MQOHYY1788612xuPYkVfbP0B; Thu, 31 Oct 2019 03:28:24 -0700 X-Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web09.4149.1572517703065913333 for ; Thu, 31 Oct 2019 03:28:24 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 Oct 2019 03:28:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,250,1569308400"; d="scan'208";a="283848055" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.215.140]) by orsmga001.jf.intel.com with ESMTP; 31 Oct 2019 03:28:22 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Michael Kubacki , Nate DeSimone , Liming Gao Subject: [edk2-devel] [edk2-platforms: PATCH v3 1/6] MinPlatformPkg: Add SetCacheMtrrLib library class. Date: Thu, 31 Oct 2019 18:28:12 +0800 Message-Id: <20191031102817.17096-2-chasel.chiu@intel.com> In-Reply-To: <20191031102817.17096-1-chasel.chiu@intel.com> References: <20191031102817.17096-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: ItHsZFR9uynBXI1ccx0IAUqWx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572517704; bh=dvwhGwMT9SLAwn+ExyhWpQWFForLmVNJl4zBRiZMhLY=; h=Cc:Date:From:Reply-To:Subject:To; b=JWRcuXFAcnRj5qLHMgq6/C4qg7A2PYkgBnAH8CpPj4Cd63ayeaJVsqYCH59z2Vit47t cipdWI9uOK2f//61LA4CMbXuCkNdL8goSdW1vx+OFzSR2liVJKUSPuAxgbAzVulyntS4Z rZy/OtV1XrmM8tW2CVD4AeGtQWOC/q1PFsI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 MinPlatformPkg should contain the library class header (API) and the NULL library class instance. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu Reviewed-by: Michael Kubacki Reviewed-by: Nate DeSimone --- Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.c = | 327 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.= c | 37 +++++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h = | 34 ++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf = | 46 ++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLibNull.= inf | 29 +++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec = | 6 ++++-- 6 files changed, 477 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCache= MtrrLib.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheM= trrLib.c new file mode 100644 index 0000000000..26f06321f7 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib= .c @@ -0,0 +1,327 @@ +/** @file + +SetCacheMtrr library functions. +This implementation is for typical platforms and may not be +needed when cache MTRR will be initialized by FSP. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + MTRR_SETTINGS MtrrSetting; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 LowMemoryLength; + UINT64 HighMemoryLength; + EFI_BOOT_MODE BootMode; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + UINT64 CacheMemoryLength; + + /// + /// Reset all MTRR setting. + /// + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + /// + /// Cache the Flash area as WP to boost performance + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance + /// + MtrrSetAllMtrrs (&MtrrSetting); + + /// + /// Set low to 1 MB. Since 1MB cacheability will always be set + /// until override by CSM. + /// Initialize high memory to 0. + /// + LowMemoryLength =3D 0x100000; + HighMemoryLength =3D 0; + ResourceAttribute =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; + } + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || + ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) + ) { + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); + DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); + + /// + /// Assume size of main memory is multiple of 256MB + /// + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; + MemoryBase =3D 0; + + CacheMemoryLength =3D MemoryLength; + /// + /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB + /// + if (MemoryLength > 0xDC000000) { + CacheMemoryLength =3D 0xC0000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xC0000000; + CacheMemoryLength =3D MemoryLength - 0xC0000000; + if (MemoryLength > 0xE0000000) { + CacheMemoryLength =3D 0x20000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xE0000000; + CacheMemoryLength =3D MemoryLength - 0xE0000000; + } + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + if (LowMemoryLength !=3D MemoryLength) { + MemoryBase =3D LowMemoryLength; + MemoryLength -=3D LowMemoryLength; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + MemoryLength, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } + + /// + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer + /// + MtrrSetAllMtrrs (&MtrrSetting); + + return ; +} + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + MTRR_SETTINGS MtrrSetting; + EFI_PEI_HOB_POINTERS Hob; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 Power2Length; + EFI_BOOT_MODE BootMode; + UINTN Index; + UINT64 SmramSize; + UINT64 SmramBase; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + return EFI_SUCCESS; + } + // + // Clear the CAR Settings + // + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + // + // Default Cachable attribute will be set to WB to support large memory = size/hot plug memory + // + MtrrSetting.MtrrDefType &=3D ~((UINT64)(0xFF)); + MtrrSetting.MtrrDefType |=3D (UINT64) CacheWriteBack; + + // + // Set fixed cache for memory range below 1MB + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0x0, + 0xA0000, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xC0000, + 0x40000, + CacheWriteProtected + ); + ASSERT_EFI_ERROR ( Status); + + // + // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protoc= ol is not available. + // Set cacheability of SMRAM to WB here to improve SMRAM initialization = performance. + // + SmramSize =3D 0; + SmramBase =3D 0; + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { + if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { + SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Ho= b.Guid + 1); + for (Index =3D 0; Index < SmramHobDescriptorBlock->NumberOfSmmRese= rvedRegions; Index++) { + if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0= x100000) { + SmramSize +=3D SmramHobDescriptorBlock->Descriptor[Index].Phys= icalSize; + if (SmramBase =3D=3D 0 || SmramBase > SmramHobDescriptorBlock-= >Descriptor[Index].CpuStart) { + SmramBase =3D SmramHobDescriptorBlock->Descriptor[Index].Cpu= Start; + } + } + } + break; + } + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + // + // Set non system memory as UC + // + MemoryBase =3D 0x100000000; + + // + // Add IED size to set whole SMRAM as WB to save MTRR count + // + MemoryLength =3D MemoryBase - (SmramBase + SmramSize); + while (MemoryLength !=3D 0) { + Power2Length =3D GetPowerOfTwo64 (MemoryLength); + MemoryBase -=3D Power2Length; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + Power2Length, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + MemoryLength -=3D Power2Length; + } + + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64= (PcdPciReservedMemAbove4GBLimit))); + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 = (PcdPciReservedMemAbove4GBBase))); + if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReserved= MemAbove4GBBase)) { + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + PcdGet64 (PcdPciReservedMemAbove4GBBase), + PcdGet64 (PcdPciReservedMemAbove4GBLimit) - Pcd= Get64 (PcdPciReservedMemAbove4GBBase) + 1, + CacheUncacheable + ); + ASSERT_EFI_ERROR ( Status); + } + + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet6= 4 (PcdPciReservedPMemAbove4GBLimit))); + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64= (PcdPciReservedPMemAbove4GBBase))); + if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReserve= dPMemAbove4GBBase)) { + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + PcdGet64 (PcdPciReservedPMemAbove4GBBase), + PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - Pc= dGet64 (PcdPciReservedPMemAbove4GBBase) + 1, + CacheUncacheable + ); + ASSERT_EFI_ERROR ( Status); + } + + // + // Update MTRR setting from MTRR buffer + // + MtrrSetAllMtrrs (&MtrrSetting); + + return Status; +} diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCache= MtrrLibNull.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCa= cheMtrrLibNull.c new file mode 100644 index 0000000000..4f40de35f4 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib= Null.c @@ -0,0 +1,37 @@ +/** @file + +NULL instances of SetCacheMtrr library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + return; +} + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.= h b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h new file mode 100644 index 0000000000..0fb566dfcc --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheMtrrLib.h @@ -0,0 +1,34 @@ +/** @file + +Header for SetCacheMtrr library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SET_CACHE_MTRR_LIB_H_ +#define _SET_CACHE_MTRR_LIB_H_ + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ); + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ); + +#endif diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCache= MtrrLib.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCach= eMtrrLib.inf new file mode 100644 index 0000000000..0cfdda414b --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib= .inf @@ -0,0 +1,46 @@ +## @file +# Component information file for Platform SetCacheMtrr Library. +# This library implementation is for typical platforms and may not be +# needed when cache MTRR will be initialized by FSP. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSetCacheMtrrLib + FILE_GUID =3D 9F2A2899-3AD7-4176-9B89-33B3AC456A99 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheMtrrLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + HobLib + MtrrLib + PeiServicesLib + BaseMemoryLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Sources] + SetCacheMtrrLib.c + +[Guids] + gEfiSmmSmramMemoryGuid ## CONSUMES + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit ## CONSUMES diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCache= MtrrLibNull.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/Set= CacheMtrrLibNull.inf new file mode 100644 index 0000000000..433bd47331 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheMtrrLib/SetCacheMtrrLib= Null.inf @@ -0,0 +1,29 @@ +## @file +# Component information file for Platform SetCacheMtrr Library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseSetCacheMtrrLibNull + FILE_GUID =3D D1ED4CD7-AD20-4943-9192-3ABE766A9411 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheMtrrLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + +[Sources] + SetCacheMtrrLibNull.c + diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index d79f5ec1bd..a851021c0b 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -65,6 +65,8 @@ SecBoardInitLib|Include/Library/SecBoardInitLib.h TestPointLib|Include/Library/TestPointLib.h TestPointCheckLib|Include/Library/TestPointCheckLib.h =20 +SetCacheMtrrLib|Include/Library/SetCacheMtrrLib.h + [PcdsFixedAtBuild, PcdsPatchableInModule] =20 gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|FALSE|BOOLEAN|0x800000= 08 @@ -204,11 +206,11 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|U= INT32|0x90000019 gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase |0x90000000= |UINT32|0x40010043 gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x00000000= |UINT32|0x40010044 gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase |0xFFFFFFFF= FFFFFFFF |UINT64|0x40010045 - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x00000000= 00000000 |UINT64|0x40010046=20 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit |0x00000000= 00000000 |UINT64|0x40010046 gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemBase |0xFFFFFFFF= |UINT32|0x40010047 gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemLimit |0x00000000= |UINT32|0x40010048 gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase |0xFFFFFFFF= FFFFFFFF |UINT64|0x40010049 - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x00000000= 00000000 |UINT64|0x4001004A=20 + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit|0x00000000= 00000000 |UINT64|0x4001004A gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G |FALSE|BOOL= EAN|0x4001004B gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace |FALSE|BOOL= EAN|0x4001004C gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned |FALSE|BOOL= EAN|0x4001004D --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49753): https://edk2.groups.io/g/devel/message/49753 Mute This Topic: https://groups.io/mt/40108817/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-