From nobody Sun Feb 8 12:38:13 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49685+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49685+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572481840; cv=none; d=zoho.com; s=zohoarc; b=S5toiNQI7lbt9yw+ulStdB1ufg6DRgYlB0FePfD1JOuUu7JijWpYA43jVrJxRq5pQ5vyH1R5r/Z0u371tvcGcU1LhU8mtLAfbcb9SWYn+b0T8rMl//1XA17AfHpGsKS8ezyGTKYCRX8Tc9QJs7NiDJ3MSVuWuyS1mh8ZKQN1J5g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572481840; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=1r8Du08uJmrprWXXkeoo9KN9EThQ+64vRrXuKEAM2F4=; b=kHeWLE5WWth7yf9dips4L1/k3pHU0NqxqMeR/uxZ6SAQEkdPIWcGFVMJGPS15MALQk5uHKDhajd0LVzMP63KXTxpqtODT0GAWm7hZRTATzgGs0qwsZJipKfv7UK1s0aucEgJaYWDkrPyy+n5A/VGdUALoXM17ZwMadRlVED3S+E= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49685+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572481840333530.4584014962993; Wed, 30 Oct 2019 17:30:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1ruaYY1788612xUc5tTg6MsN; Wed, 30 Oct 2019 17:30:38 -0700 X-Received: from mga02.intel.com (mga02.intel.com []) by mx.groups.io with SMTP id smtpd.web11.718.1572481837056118480 for ; Wed, 30 Oct 2019 17:30:37 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 17:30:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,248,1569308400"; d="scan'208";a="203359797" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.240.37]) by orsmga003.jf.intel.com with ESMTP; 30 Oct 2019 17:30:29 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Michael Kubacki , Nate DeSimone , Liming Gao Subject: [edk2-devel] [edk2-platforms: PATCH v2 2/6] MinPlatformPkg: Add SetCacheLib library class. Date: Thu, 31 Oct 2019 08:29:48 +0800 Message-Id: <20191031002952.3860-3-chasel.chiu@intel.com> In-Reply-To: <20191031002952.3860-1-chasel.chiu@intel.com> References: <20191031002952.3860-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: OlUoHoKrw21avBGGXrf1xGK0x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572481838; bh=mHhkan0C+zSh6c9haQy33UggzFM92jkeq3x1u/N1haM=; h=Cc:Date:From:Reply-To:Subject:To; b=f/2owrhsBIIG7gbGOviQAnl+jgBug/qnoDDjr/MbcMSdeORrBvGKPqPgH959dSGcOFK HU0244CI0ak968M5VZ/aOF0JRuV9CnxKgS7FN2Z/ZuuY1Zj+dnk4kwkGibQie+I39m0ao lPT2eKu7dR9RE5kOFv/AltFHCyygRSYE6KM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 MinPlatformPkg PlatformInit modules to consume SetCacheLib. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu Reviewed-by: Michael Kubacki Reviewed-by: Nate DeSimone --- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPos= tMem.c | 149 +-----------------------------------------------------------= ---------------------------------------------------------------------------= -------------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPre= Mem.c | 164 ++----------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPos= tMem.inf | 11 +---------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPre= Mem.inf | 7 ++----- 4 files changed, 6 insertions(+), 325 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pla= tformInitPostMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformIni= tPei/PlatformInitPostMem.c index 70e6b9a495..df64d4fc0d 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPostMem.c +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPostMem.c @@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include -#include -#include =20 #include #include @@ -22,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 EFI_STATUS EFIAPI @@ -38,152 +37,6 @@ static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = =3D { }; =20 /** - Update MTRR setting and set write back as default memory attribute. - - @retval EFI_SUCCESS The function completes successfully. - @retval Others Some error occurs. -**/ -EFI_STATUS -EFIAPI -SetCacheMtrrAfterEndOfPei ( - VOID - ) -{ - EFI_STATUS Status; - MTRR_SETTINGS MtrrSetting; - EFI_PEI_HOB_POINTERS Hob; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 Power2Length; - EFI_BOOT_MODE BootMode; - UINTN Index; - UINT64 SmramSize; - UINT64 SmramBase; - EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode =3D=3D BOOT_ON_S3_RESUME) { - return EFI_SUCCESS; - } - // - // Clear the CAR Settings - // - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - // - // Default Cachable attribute will be set to WB to support large memory = size/hot plug memory - // - MtrrSetting.MtrrDefType &=3D ~((UINT64)(0xFF)); - MtrrSetting.MtrrDefType |=3D (UINT64) CacheWriteBack; - - // - // Set fixed cache for memory range below 1MB - // - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0x0, - 0xA0000, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xC0000, - 0x40000, - CacheWriteProtected - ); - ASSERT_EFI_ERROR ( Status); - - // - // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protoc= ol is not available. - // Set cacheability of SMRAM to WB here to improve SMRAM initialization = performance. - // - SmramSize =3D 0; - SmramBase =3D 0; - Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { - if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { - SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Ho= b.Guid + 1); - for (Index =3D 0; Index < SmramHobDescriptorBlock->NumberOfSmmRese= rvedRegions; Index++) { - if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0= x100000) { - SmramSize +=3D SmramHobDescriptorBlock->Descriptor[Index].Phys= icalSize; - if (SmramBase =3D=3D 0 || SmramBase > SmramHobDescriptorBlock-= >Descriptor[Index].CpuStart) { - SmramBase =3D SmramHobDescriptorBlock->Descriptor[Index].Cpu= Start; - } - } - } - break; - } - } - Hob.Raw =3D GET_NEXT_HOB (Hob); - } - - // - // Set non system memory as UC - // - MemoryBase =3D 0x100000000; - - // - // Add IED size to set whole SMRAM as WB to save MTRR count - // - MemoryLength =3D MemoryBase - (SmramBase + SmramSize); - while (MemoryLength !=3D 0) { - Power2Length =3D GetPowerOfTwo64 (MemoryLength); - MemoryBase -=3D Power2Length; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - Power2Length, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - MemoryLength -=3D Power2Length; - } - - DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64= (PcdPciReservedMemAbove4GBLimit))); - DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 = (PcdPciReservedMemAbove4GBBase))); - if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReserved= MemAbove4GBBase)) { - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - PcdGet64 (PcdPciReservedMemAbove4GBBase), - PcdGet64 (PcdPciReservedMemAbove4GBLimit) - Pcd= Get64 (PcdPciReservedMemAbove4GBBase) + 1, - CacheUncacheable - ); - ASSERT_EFI_ERROR ( Status); - } - - DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet6= 4 (PcdPciReservedPMemAbove4GBLimit))); - DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64= (PcdPciReservedPMemAbove4GBBase))); - if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReserve= dPMemAbove4GBBase)) { - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - PcdGet64 (PcdPciReservedPMemAbove4GBBase), - PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - Pc= dGet64 (PcdPciReservedPMemAbove4GBBase) + 1, - CacheUncacheable - ); - ASSERT_EFI_ERROR ( Status); - } - - // - // Update MTRR setting from MTRR buffer - // - MtrrSetAllMtrrs (&MtrrSetting); - - return Status; -} - -/** This function handles PlatformInit task at the end of PEI =20 @param[in] PeiServices Pointer to PEI Services Table. diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pla= tformInitPreMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInit= Pei/PlatformInitPreMem.c index 2690511abe..731bc234b0 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPreMem.c +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPreMem.c @@ -1,7 +1,7 @@ /** @file Source code file for Platform Init Pre-Memory PEI module =20 -Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -15,7 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include -#include #include #include #include @@ -26,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -319,166 +319,6 @@ Done: return EFI_SUCCESS; } =20 -/** - Set Cache Mtrr. -**/ -VOID -SetCacheMtrr ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_HOB_POINTERS Hob; - MTRR_SETTINGS MtrrSetting; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 LowMemoryLength; - UINT64 HighMemoryLength; - EFI_BOOT_MODE BootMode; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - UINT64 CacheMemoryLength; - - /// - /// Reset all MTRR setting. - /// - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - /// - /// Cache the Flash area as WP to boost performance - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), - (UINTN) PcdGet32 (PcdFlashAreaSize), - CacheWriteProtected - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance - /// - MtrrSetAllMtrrs (&MtrrSetting); - - /// - /// Set low to 1 MB. Since 1MB cacheability will always be set - /// until override by CSM. - /// Initialize high memory to 0. - /// - LowMemoryLength =3D 0x100000; - HighMemoryLength =3D 0; - ResourceAttribute =3D ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode !=3D BOOT_ON_S3_RESUME) { - ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; - } - - Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || - ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && - (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) - ) { - if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { - HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { - LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } - } - } - - Hob.Raw =3D GET_NEXT_HOB (Hob); - } - - DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); - DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); - - /// - /// Assume size of main memory is multiple of 256MB - /// - MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; - MemoryBase =3D 0; - - CacheMemoryLength =3D MemoryLength; - /// - /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB - /// - if (MemoryLength > 0xDC000000) { - CacheMemoryLength =3D 0xC0000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xC0000000; - CacheMemoryLength =3D MemoryLength - 0xC0000000; - if (MemoryLength > 0xE0000000) { - CacheMemoryLength =3D 0x20000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xE0000000; - CacheMemoryLength =3D MemoryLength - 0xE0000000; - } - } - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - if (LowMemoryLength !=3D MemoryLength) { - MemoryBase =3D LowMemoryLength; - MemoryLength -=3D LowMemoryLength; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - MemoryLength, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } - - /// - /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer - /// - MtrrSetAllMtrrs (&MtrrSetting); - - return ; -} - VOID ReportCpuHob ( VOID diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pla= tformInitPostMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPostMem.inf index 0736c8d494..a14f20f150 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPostMem.inf +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPostMem.inf @@ -23,15 +23,14 @@ BaseMemoryLib HobLib PeiServicesLib - MtrrLib BoardInitLib TestPointCheckLib + SetCacheLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec =20 [Sources] PlatformInitPostMem.c @@ -44,14 +43,6 @@ =20 [Protocols] =20 -[Guids] - gEfiSmmSmramMemoryGuid ## CONSUMES - [Depex] gEfiPeiMemoryDiscoveredPpiGuid =20 -[Pcd] - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pla= tformInitPreMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformIn= itPei/PlatformInitPreMem.inf index 2c3a13106e..de5f11f829 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPreMem.inf +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPreMem.inf @@ -1,7 +1,7 @@ ### @file # Component information file for the Platform Init Pre-Memory PEI module. # -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,23 +22,20 @@ HobLib IoLib MemoryAllocationLib - MtrrLib PeimEntryPoint PeiServicesLib ReportFvLib TestPointCheckLib TimerLib + SetCacheLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec =20 [Pcd] gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES =20 --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49685): https://edk2.groups.io/g/devel/message/49685 Mute This Topic: https://groups.io/mt/40049896/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-