From nobody Thu Apr 18 06:24:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49652+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49652+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572438630; cv=none; d=zoho.com; s=zohoarc; b=GO2MOXd66l4sY7MeoqaRi2Kj64USN26gQxNSDWY14hZ9Ylk/UJfoMhFwJukFT0i08O4NaWRGvK+SpvtFAV/0Z4jTHZhy0Pcioq1c6qYjxWm9NOEh1qcCnqObuiQRriFXs99+lxEHkGtg/3MbmvInT6hiBjW0qdVsRk1+bgm6kJY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572438630; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=Nv0khG24+J6PeWtjYFFI3KZ3bnh2OJaNhniJdeyvWTs=; b=eDDrdetII+J/6ykvzwaP0iCv+AJD4TH/yUOWapCdatx1Sr8YOymfKrVdBM/ugYsxyOxcBtY89fNZum8uWwR0wGeKjHuklB5JU8OK6yBVI0LsyAEwNUXVqmE0aHyYcC+coQht0u9iDDlO9AYTPkjH5QuFHA1F3gPHQlrt+Y3meVM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49652+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572438630214533.2610523510272; Wed, 30 Oct 2019 05:30:30 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jSCAYY1788612xdQKDd1T2vv; Wed, 30 Oct 2019 05:30:29 -0700 X-Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web09.4163.1572438626213879058 for ; Wed, 30 Oct 2019 05:30:28 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 05:30:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,247,1569308400"; d="scan'208";a="190262707" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.252.190.81]) by orsmga007.jf.intel.com with ESMTP; 30 Oct 2019 05:30:25 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Michael Kubacki , Nate DeSimone , Liming Gao Subject: [edk2-devel] [edk2-platforms: PATCH 1/5] MinPlatformPkg: Add SetCacheLib library class. Date: Wed, 30 Oct 2019 20:29:39 +0800 Message-Id: <20191030122943.14432-2-chasel.chiu@intel.com> In-Reply-To: <20191030122943.14432-1-chasel.chiu@intel.com> References: <20191030122943.14432-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: avIauZbSC089wjRHoObnM1tLx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572438629; bh=n3q72k1Mq2ZYiUSHb2v/nh9Sh6OPpt4RVVLFJ+Wp5vQ=; h=Cc:Date:From:Reply-To:Subject:To; b=qn4eNqxDbnxpVwBw5K0nIROOk16a2XG+0jb2X2WNNr0B2pXsEjh/O+bFJTgEx7rhTGY G7xzfd6LxfJFLQiACsJyPX9QzDLlR4pBCho+k1b3aGUgWCv28wVdu/mRO4T9vTevEm4XZ ZUg4CGCUj1UlPKxt4I8sWgTzXyBR6JwxiX8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 MinPlatformPkg should contain the library class header (API) and the NULL library class instance. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Chasel Chiu --- Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c = | 325 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c = | 37 +++++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPos= tMem.c | 149 +-----------------------------------------------------------= ---------------------------------------------------------------------------= -------------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPre= Mem.c | 164 ++----------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------------- Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h = | 34 ++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf = | 44 ++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf = | 30 ++++++++++++++++++++++++++++++ Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPos= tMem.inf | 11 +---------- Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPre= Mem.inf | 7 ++----- 9 files changed, 476 insertions(+), 325 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.= c b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c new file mode 100644 index 0000000000..b5c5041430 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.c @@ -0,0 +1,325 @@ +/** @file + +SetCache library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + MTRR_SETTINGS MtrrSetting; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 LowMemoryLength; + UINT64 HighMemoryLength; + EFI_BOOT_MODE BootMode; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + UINT64 CacheMemoryLength; + + /// + /// Reset all MTRR setting. + /// + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + /// + /// Cache the Flash area as WP to boost performance + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance + /// + MtrrSetAllMtrrs (&MtrrSetting); + + /// + /// Set low to 1 MB. Since 1MB cacheability will always be set + /// until override by CSM. + /// Initialize high memory to 0. + /// + LowMemoryLength =3D 0x100000; + HighMemoryLength =3D 0; + ResourceAttribute =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; + } + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || + ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) + ) { + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); + DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); + + /// + /// Assume size of main memory is multiple of 256MB + /// + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; + MemoryBase =3D 0; + + CacheMemoryLength =3D MemoryLength; + /// + /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB + /// + if (MemoryLength > 0xDC000000) { + CacheMemoryLength =3D 0xC0000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xC0000000; + CacheMemoryLength =3D MemoryLength - 0xC0000000; + if (MemoryLength > 0xE0000000) { + CacheMemoryLength =3D 0x20000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xE0000000; + CacheMemoryLength =3D MemoryLength - 0xE0000000; + } + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + if (LowMemoryLength !=3D MemoryLength) { + MemoryBase =3D LowMemoryLength; + MemoryLength -=3D LowMemoryLength; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + MemoryLength, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } + + /// + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer + /// + MtrrSetAllMtrrs (&MtrrSetting); + + return ; +} + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + MTRR_SETTINGS MtrrSetting; + EFI_PEI_HOB_POINTERS Hob; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 Power2Length; + EFI_BOOT_MODE BootMode; + UINTN Index; + UINT64 SmramSize; + UINT64 SmramBase; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + return EFI_SUCCESS; + } + // + // Clear the CAR Settings + // + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + // + // Default Cachable attribute will be set to WB to support large memory = size/hot plug memory + // + MtrrSetting.MtrrDefType &=3D ~((UINT64)(0xFF)); + MtrrSetting.MtrrDefType |=3D (UINT64) CacheWriteBack; + + // + // Set fixed cache for memory range below 1MB + // + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0x0, + 0xA0000, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xC0000, + 0x40000, + CacheWriteProtected + ); + ASSERT_EFI_ERROR ( Status); + + // + // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protoc= ol is not available. + // Set cacheability of SMRAM to WB here to improve SMRAM initialization = performance. + // + SmramSize =3D 0; + SmramBase =3D 0; + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { + if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { + SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Ho= b.Guid + 1); + for (Index =3D 0; Index < SmramHobDescriptorBlock->NumberOfSmmRese= rvedRegions; Index++) { + if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0= x100000) { + SmramSize +=3D SmramHobDescriptorBlock->Descriptor[Index].Phys= icalSize; + if (SmramBase =3D=3D 0 || SmramBase > SmramHobDescriptorBlock-= >Descriptor[Index].CpuStart) { + SmramBase =3D SmramHobDescriptorBlock->Descriptor[Index].Cpu= Start; + } + } + } + break; + } + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + // + // Set non system memory as UC + // + MemoryBase =3D 0x100000000; + + // + // Add IED size to set whole SMRAM as WB to save MTRR count + // + MemoryLength =3D MemoryBase - (SmramBase + SmramSize); + while (MemoryLength !=3D 0) { + Power2Length =3D GetPowerOfTwo64 (MemoryLength); + MemoryBase -=3D Power2Length; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + Power2Length, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + MemoryLength -=3D Power2Length; + } + + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64= (PcdPciReservedMemAbove4GBLimit))); + DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 = (PcdPciReservedMemAbove4GBBase))); + if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReserved= MemAbove4GBBase)) { + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + PcdGet64 (PcdPciReservedMemAbove4GBBase), + PcdGet64 (PcdPciReservedMemAbove4GBLimit) - Pcd= Get64 (PcdPciReservedMemAbove4GBBase) + 1, + CacheUncacheable + ); + ASSERT_EFI_ERROR ( Status); + } + + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet6= 4 (PcdPciReservedPMemAbove4GBLimit))); + DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64= (PcdPciReservedPMemAbove4GBBase))); + if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReserve= dPMemAbove4GBBase)) { + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + PcdGet64 (PcdPciReservedPMemAbove4GBBase), + PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - Pc= dGet64 (PcdPciReservedPMemAbove4GBBase) + 1, + CacheUncacheable + ); + ASSERT_EFI_ERROR ( Status); + } + + // + // Update MTRR setting from MTRR buffer + // + MtrrSetAllMtrrs (&MtrrSetting); + + return Status; +} diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibN= ull.c b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c new file mode 100644 index 0000000000..581bc7648b --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.c @@ -0,0 +1,37 @@ +/** @file + +NULL instances of SetCache library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ) +{ + return; +} + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pla= tformInitPostMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformIni= tPei/PlatformInitPostMem.c index 70e6b9a495..df64d4fc0d 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPostMem.c +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPostMem.c @@ -13,8 +13,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include -#include -#include =20 #include #include @@ -22,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 EFI_STATUS EFIAPI @@ -38,152 +37,6 @@ static EFI_PEI_NOTIFY_DESCRIPTOR mEndOfPeiNotifyList = =3D { }; =20 /** - Update MTRR setting and set write back as default memory attribute. - - @retval EFI_SUCCESS The function completes successfully. - @retval Others Some error occurs. -**/ -EFI_STATUS -EFIAPI -SetCacheMtrrAfterEndOfPei ( - VOID - ) -{ - EFI_STATUS Status; - MTRR_SETTINGS MtrrSetting; - EFI_PEI_HOB_POINTERS Hob; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 Power2Length; - EFI_BOOT_MODE BootMode; - UINTN Index; - UINT64 SmramSize; - UINT64 SmramBase; - EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *SmramHobDescriptorBlock; - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode =3D=3D BOOT_ON_S3_RESUME) { - return EFI_SUCCESS; - } - // - // Clear the CAR Settings - // - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - // - // Default Cachable attribute will be set to WB to support large memory = size/hot plug memory - // - MtrrSetting.MtrrDefType &=3D ~((UINT64)(0xFF)); - MtrrSetting.MtrrDefType |=3D (UINT64) CacheWriteBack; - - // - // Set fixed cache for memory range below 1MB - // - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0x0, - 0xA0000, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xC0000, - 0x40000, - CacheWriteProtected - ); - ASSERT_EFI_ERROR ( Status); - - // - // PI SMM IPL can't set SMRAM to WB because at that time CPU ARCH protoc= ol is not available. - // Set cacheability of SMRAM to WB here to improve SMRAM initialization = performance. - // - SmramSize =3D 0; - SmramBase =3D 0; - Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) { - if (CompareGuid (&Hob.Guid->Name, &gEfiSmmSmramMemoryGuid)) { - SmramHobDescriptorBlock =3D (EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *) (Ho= b.Guid + 1); - for (Index =3D 0; Index < SmramHobDescriptorBlock->NumberOfSmmRese= rvedRegions; Index++) { - if (SmramHobDescriptorBlock->Descriptor[Index].PhysicalStart > 0= x100000) { - SmramSize +=3D SmramHobDescriptorBlock->Descriptor[Index].Phys= icalSize; - if (SmramBase =3D=3D 0 || SmramBase > SmramHobDescriptorBlock-= >Descriptor[Index].CpuStart) { - SmramBase =3D SmramHobDescriptorBlock->Descriptor[Index].Cpu= Start; - } - } - } - break; - } - } - Hob.Raw =3D GET_NEXT_HOB (Hob); - } - - // - // Set non system memory as UC - // - MemoryBase =3D 0x100000000; - - // - // Add IED size to set whole SMRAM as WB to save MTRR count - // - MemoryLength =3D MemoryBase - (SmramBase + SmramSize); - while (MemoryLength !=3D 0) { - Power2Length =3D GetPowerOfTwo64 (MemoryLength); - MemoryBase -=3D Power2Length; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - Power2Length, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - MemoryLength -=3D Power2Length; - } - - DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBLimit - 0x%lx\n", PcdGet64= (PcdPciReservedMemAbove4GBLimit))); - DEBUG ((DEBUG_INFO, "PcdPciReservedMemAbove4GBBase - 0x%lx\n", PcdGet64 = (PcdPciReservedMemAbove4GBBase))); - if (PcdGet64 (PcdPciReservedMemAbove4GBLimit) > PcdGet64 (PcdPciReserved= MemAbove4GBBase)) { - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - PcdGet64 (PcdPciReservedMemAbove4GBBase), - PcdGet64 (PcdPciReservedMemAbove4GBLimit) - Pcd= Get64 (PcdPciReservedMemAbove4GBBase) + 1, - CacheUncacheable - ); - ASSERT_EFI_ERROR ( Status); - } - - DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBLimit - 0x%lx\n", PcdGet6= 4 (PcdPciReservedPMemAbove4GBLimit))); - DEBUG ((DEBUG_INFO, "PcdPciReservedPMemAbove4GBBase - 0x%lx\n", PcdGet64= (PcdPciReservedPMemAbove4GBBase))); - if (PcdGet64 (PcdPciReservedPMemAbove4GBLimit) > PcdGet64 (PcdPciReserve= dPMemAbove4GBBase)) { - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - PcdGet64 (PcdPciReservedPMemAbove4GBBase), - PcdGet64 (PcdPciReservedPMemAbove4GBLimit) - Pc= dGet64 (PcdPciReservedPMemAbove4GBBase) + 1, - CacheUncacheable - ); - ASSERT_EFI_ERROR ( Status); - } - - // - // Update MTRR setting from MTRR buffer - // - MtrrSetAllMtrrs (&MtrrSetting); - - return Status; -} - -/** This function handles PlatformInit task at the end of PEI =20 @param[in] PeiServices Pointer to PEI Services Table. diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pla= tformInitPreMem.c b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInit= Pei/PlatformInitPreMem.c index 2690511abe..731bc234b0 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPreMem.c +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPreMem.c @@ -1,7 +1,7 @@ /** @file Source code file for Platform Init Pre-Memory PEI module =20 -Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -15,7 +15,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include -#include #include #include #include @@ -26,6 +25,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -319,166 +319,6 @@ Done: return EFI_SUCCESS; } =20 -/** - Set Cache Mtrr. -**/ -VOID -SetCacheMtrr ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_HOB_POINTERS Hob; - MTRR_SETTINGS MtrrSetting; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 LowMemoryLength; - UINT64 HighMemoryLength; - EFI_BOOT_MODE BootMode; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - UINT64 CacheMemoryLength; - - /// - /// Reset all MTRR setting. - /// - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - /// - /// Cache the Flash area as WP to boost performance - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), - (UINTN) PcdGet32 (PcdFlashAreaSize), - CacheWriteProtected - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance - /// - MtrrSetAllMtrrs (&MtrrSetting); - - /// - /// Set low to 1 MB. Since 1MB cacheability will always be set - /// until override by CSM. - /// Initialize high memory to 0. - /// - LowMemoryLength =3D 0x100000; - HighMemoryLength =3D 0; - ResourceAttribute =3D ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode !=3D BOOT_ON_S3_RESUME) { - ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; - } - - Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || - ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && - (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) - ) { - if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { - HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { - LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } - } - } - - Hob.Raw =3D GET_NEXT_HOB (Hob); - } - - DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); - DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); - - /// - /// Assume size of main memory is multiple of 256MB - /// - MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; - MemoryBase =3D 0; - - CacheMemoryLength =3D MemoryLength; - /// - /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB - /// - if (MemoryLength > 0xDC000000) { - CacheMemoryLength =3D 0xC0000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xC0000000; - CacheMemoryLength =3D MemoryLength - 0xC0000000; - if (MemoryLength > 0xE0000000) { - CacheMemoryLength =3D 0x20000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xE0000000; - CacheMemoryLength =3D MemoryLength - 0xE0000000; - } - } - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - if (LowMemoryLength !=3D MemoryLength) { - MemoryBase =3D LowMemoryLength; - MemoryLength -=3D LowMemoryLength; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - MemoryLength, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } - - /// - /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer - /// - MtrrSetAllMtrrs (&MtrrSetting); - - return ; -} - VOID ReportCpuHob ( VOID diff --git a/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h b/= Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h new file mode 100644 index 0000000000..d67426cef7 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/Library/SetCacheLib.h @@ -0,0 +1,34 @@ +/** @file + +Header for SetCache library functions. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SET_CACHE_LIB_H_ +#define _SET_CACHE_LIB_H_ + +/** + Set Cache Mtrr. +**/ +VOID +EFIAPI +SetCacheMtrr ( + VOID + ); + +/** + Update MTRR setting and set write back as default memory attribute. + + @retval EFI_SUCCESS The function completes successfully. + @retval Others Some error occurs. +**/ +EFI_STATUS +EFIAPI +SetCacheMtrrAfterEndOfPei ( + VOID + ); + +#endif diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.= inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf new file mode 100644 index 0000000000..a53aed858f --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf @@ -0,0 +1,44 @@ +## @file +# Component information file for Platform SetCache Library +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SetCacheLib + FILE_GUID =3D 9F2A2899-3AD7-4176-9B89-33B3AC456A99 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + HobLib + MtrrLib + PeiServicesLib + BaseMemoryLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Sources] + SetCacheLib.c + +[Guids] + gEfiSmmSmramMemoryGuid ## CONSUMES + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit ## CONSUMES diff --git a/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibN= ull.inf b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull= .inf new file mode 100644 index 0000000000..50419b398b --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Library/SetCacheLib/SetCacheLibNull.inf @@ -0,0 +1,30 @@ +## @file +# Component information file for Platform SetCache Library +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SetCacheLibNull + FILE_GUID =3D D1ED4CD7-AD20-4943-9192-3ABE766A9411 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SetCacheLib + +[LibraryClasses] + BaseLib + PcdLib + DebugLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdePkg/MdePkg.dec + +[Sources] + SetCacheLibNull.c + +[Pcd] diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pla= tformInitPostMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPostMem.inf index 0736c8d494..a14f20f150 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPostMem.inf +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPostMem.inf @@ -23,15 +23,14 @@ BaseMemoryLib HobLib PeiServicesLib - MtrrLib BoardInitLib TestPointCheckLib + SetCacheLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec =20 [Sources] PlatformInitPostMem.c @@ -44,14 +43,6 @@ =20 [Protocols] =20 -[Guids] - gEfiSmmSmramMemoryGuid ## CONSUMES - [Depex] gEfiPeiMemoryDiscoveredPpiGuid =20 -[Pcd] - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBBase - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemAbove4GBLimit - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBBase - gMinPlatformPkgTokenSpaceGuid.PcdPciReservedPMemAbove4GBLimit diff --git a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/Pla= tformInitPreMem.inf b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformIn= itPei/PlatformInitPreMem.inf index 2c3a13106e..de5f11f829 100644 --- a/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPreMem.inf +++ b/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformIn= itPreMem.inf @@ -1,7 +1,7 @@ ### @file # Component information file for the Platform Init Pre-Memory PEI module. # -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,23 +22,20 @@ HobLib IoLib MemoryAllocationLib - MtrrLib PeimEntryPoint PeiServicesLib ReportFvLib TestPointCheckLib TimerLib + SetCacheLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec =20 [Pcd] gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES =20 --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49652): https://edk2.groups.io/g/devel/message/49652 Mute This Topic: https://groups.io/mt/39770821/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 06:24:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49653+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49653+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572438632; cv=none; d=zoho.com; s=zohoarc; b=UcK5iOBkzzd0cKLRT2+a122rc6TQuHywsGBIFn882ZcD8Gwc+9LzcBG6kSyiZ4Ukhp9RW7qJF2a3wVi0QNadBFXS1nLOm8CATN23sHRIMMUalRSy/pU3ThQEy32YKgkpHrDAh3BZSsOtuP4Q9dd4Kmv5Xr31kYFHNwHT/m7a03s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572438632; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=sPaw9h+XkWRrNVCXL1x9euMeED2gDn2rre1pIHLISYI=; b=jpylg67KWz4CPZCRNvEPsxc4buWKEJoC5lJo8sMtH5fjKzgosh5S78cSfAZSxLXCcG3d3+CBAyEkO5+lLGrWVEtHgMuUshwccdTtumDbJko5PHXNY0JnlHKSSKT1I5gIqmRCpuMxK/muen6vUSUPx8F7lXUBCAiZnUxIOyyTJYY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49653+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572438632549894.3914678983556; Wed, 30 Oct 2019 05:30:32 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id RoLqYY1788612xilm7G3fwoy; Wed, 30 Oct 2019 05:30:31 -0700 X-Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web09.4163.1572438626213879058 for ; Wed, 30 Oct 2019 05:30:30 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 05:30:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,247,1569308400"; d="scan'208";a="190262722" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.252.190.81]) by orsmga007.jf.intel.com with ESMTP; 30 Oct 2019 05:30:28 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Michael Kubacki , Nate DeSimone , Liming Gao , Jeremy Soller Subject: [edk2-devel] [edk2-platforms: PATCH 2/5] KabylakeOpenBoardPkg: Add SetCacheLib library class. Date: Wed, 30 Oct 2019 20:29:40 +0800 Message-Id: <20191030122943.14432-3-chasel.chiu@intel.com> In-Reply-To: <20191030122943.14432-1-chasel.chiu@intel.com> References: <20191030122943.14432-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: zOe81v4YJjIJ8SDhKabpr64Kx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572438631; bh=CsHsBkT2UOtysrvjdDyMiClnCtTCUAvpftsyp070G+g=; h=Cc:Date:From:Reply-To:Subject:To; b=B3Ja54mQwDlrtHB23MrwdrKB8YYJjkJhQqHFM1pJKuuh6ptS+1UljAIRcuqaOJ8Yj+s fShi/sLHQcXWCBs5Wuh/O9rE5pDlnvHfuiuFDdjSNV1Ymu41N5dZQ80oKTeELqnoLz4rq sxNOaMTR9Sn58ybNctY2ConzAZUklm9YOPs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 Kabylake boards are relying on FSP to configure MTRRs so they can include SetCacheLibNull. Test: internal platform can boot with FSP API and Dispatch modes. Cc: Michael Kubacki Cc: Nate DeSimone Cc: Liming Gao Cc: Jeremy Soller Signed-off-by: Chasel Chiu --- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/Min= PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c | 640 -----= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ----------------------------------- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc = | 3 ++- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf = | 2 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/Min= PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf | 67 -----= -------------------------------------------------------------- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc = | 1 + 5 files changed, 4 insertions(+), 709 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platfo= rm/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b= /Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/Min= PlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c deleted file mode 100644 index b784026c1b..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Inte= l/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c +++ /dev/null @@ -1,640 +0,0 @@ -/** @file - Source code file for Platform Init Pre-Memory PEI module - -Copyright (c) 2019, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -EFI_STATUS -EFIAPI -MemoryDiscoveredPpiNotifyCallback ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, - IN VOID *Ppi - ); - -EFI_STATUS -EFIAPI -GetPlatformMemorySize ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, - IN OUT UINT64 *MemorySize - ); - -/** - - This function checks the memory range in PEI. - - @param PeiServices Pointer to PEI Services. - @param This Pei memory test PPI pointer. - @param BeginAddress Beginning of the memory address to be checked. - @param MemoryLength Bytes of memory range to be checked. - @param Operation Type of memory check operation to be performed. - @param ErrorAddress Return the address of the error memory address. - - @retval EFI_SUCCESS The operation completed successfully. - @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use thi= s range of memory. - -**/ -EFI_STATUS -EFIAPI -BaseMemoryTest ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_BASE_MEMORY_TEST_PPI *This, - IN EFI_PHYSICAL_ADDRESS BeginAddress, - IN UINT64 MemoryLength, - IN PEI_MEMORY_TEST_OP Operation, - OUT EFI_PHYSICAL_ADDRESS *ErrorAddress - ); - -static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D { - (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), - &gEfiPeiMemoryDiscoveredPpiGuid, - (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootM= ode =3D { - (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), - &gEfiPeiBootInRecoveryModePpiGuid, - NULL -}; - -GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode =3D { - (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), - &gEfiPeiMasterBootModePpiGuid, - NULL -}; - -static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi =3D { BaseMemory= Test }; - -static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi =3D { GetPlatfor= mMemorySize }; - -static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] =3D { - { - EFI_PEI_PPI_DESCRIPTOR_PPI, - &gPeiBaseMemoryTestPpiGuid, - &mPeiBaseMemoryTestPpi - }, - { - (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), - &gPeiPlatformMemorySizePpiGuid, - &mMemoryMemorySizePpi - }, -}; - -/// -/// Memory Reserved should be between 125% to 150% of the Current required= memory -/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resum= e issues. -/// -GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTy= peInformation[] =3D { - { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory= Size) }, // ASL - { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize= ) }, // ACPI NVS (including S3 related) - { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz= e) }, // BIOS Reserved (including S3 related) - { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize)= }, // Runtime Service Data - { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize)= }, // Runtime Service Code - { EfiMaxMemoryType, 0 } -}; - -VOID -BuildMemoryTypeInformation ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; - UINTN DataSize; - EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; - - // - // Locate system configuration variable - // - Status =3D PeiServicesLocatePpi( - &gEfiPeiReadOnlyVariable2PpiGuid, // GUID - 0, // INSTANCE - NULL, // EFI_PEI_PPI_DESCRIPTOR - (VOID **) &VariableServices // PPI - ); - ASSERT_EFI_ERROR(Status); - - DataSize =3D sizeof (MemoryData); - Status =3D VariableServices->GetVariable ( - VariableServices, - EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, - &gEfiMemoryTypeInformationGuid, - NULL, - &DataSize, - &MemoryData - ); - if (EFI_ERROR(Status)) { - DataSize =3D sizeof (mDefaultMemoryTypeInformation); - CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize); - } - - /// - /// Build the GUID'd HOB for DXE - /// - BuildGuidDataHob ( - &gEfiMemoryTypeInformationGuid, - MemoryData, - DataSize - ); -} - -EFI_STATUS -EFIAPI -GetPlatformMemorySize ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, - IN OUT UINT64 *MemorySize - ) -{ - EFI_STATUS Status; - EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; - UINTN DataSize; - EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; - UINTN Index; - EFI_BOOT_MODE BootMode; - UINTN IndexNumber; - -#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x1= 00000)) - - *MemorySize =3D PEI_MIN_MEMORY_SIZE; - Status =3D PeiServicesLocatePpi ( - &gEfiPeiReadOnlyVariable2PpiGuid, - 0, - NULL, - (VOID **)&Variable - ); - - ASSERT_EFI_ERROR (Status); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - DataSize =3D sizeof (MemoryData); - - Status =3D Variable->GetVariable ( - Variable, - EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, - &gEfiMemoryTypeInformationGuid, - NULL, - &DataSize, - &MemoryData - ); - IndexNumber =3D sizeof (mDefaultMemoryTypeInformation) / sizeof (EFI_MEM= ORY_TYPE_INFORMATION); - - // - // Accumulate maximum amount of memory needed - // - - DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n", DivU64x32(*MemorySize= ,1024))); - DEBUG((DEBUG_ERROR, "IndexNumber:%d MemoryDataNumber%d \n", IndexNumber,= DataSize/ sizeof (EFI_MEMORY_TYPE_INFORMATION))); - if (EFI_ERROR (Status)) { - // - // Start with minimum memory - // - for (Index =3D 0; Index < IndexNumber; Index++) { - DEBUG((DEBUG_ERROR, "Index[%d].Type =3D %d .NumberOfPages=3D0x%x\n",= Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeInformat= ion[Index].NumberOfPages)); - *MemorySize +=3D mDefaultMemoryTypeInformation[Index].NumberOfPages = * EFI_PAGE_SIZE; - } - DEBUG((DEBUG_ERROR, "No memory type, Total platform memory:%dKB \n", = DivU64x32(*MemorySize,1024))); - } else { - // - // Start with at least 0x200 pages of memory for the DXE Core and the = DXE Stack - // - for (Index =3D 0; Index < IndexNumber; Index++) { - DEBUG((DEBUG_ERROR, "Index[%d].Type =3D %d .NumberOfPages=3D0x%x\n",= Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages)); - *MemorySize +=3D MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE; - - } - DEBUG((DEBUG_ERROR, "has memory type, Total platform memory:%dKB \n",= DivU64x32(*MemorySize,1024))); - } - - return EFI_SUCCESS; -} - -/** - - This function checks the memory range in PEI. - - @param PeiServices Pointer to PEI Services. - @param This Pei memory test PPI pointer. - @param BeginAddress Beginning of the memory address to be checked. - @param MemoryLength Bytes of memory range to be checked. - @param Operation Type of memory check operation to be performed. - @param ErrorAddress Return the address of the error memory address. - - @retval EFI_SUCCESS The operation completed successfully. - @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use thi= s range of memory. - -**/ -EFI_STATUS -EFIAPI -BaseMemoryTest ( - IN EFI_PEI_SERVICES **PeiServices, - IN PEI_BASE_MEMORY_TEST_PPI *This, - IN EFI_PHYSICAL_ADDRESS BeginAddress, - IN UINT64 MemoryLength, - IN PEI_MEMORY_TEST_OP Operation, - OUT EFI_PHYSICAL_ADDRESS *ErrorAddress - ) -{ - UINT32 TestPattern; - UINT32 SpanSize; - EFI_PHYSICAL_ADDRESS TempAddress; - -#define MEMORY_TEST_PATTERN 0x5A5A5A5A -#define MEMORY_TEST_COVER_SPAN 0x40000 - - TestPattern =3D MEMORY_TEST_PATTERN; - SpanSize =3D 0; - - // - // Make sure we don't try and test anything above the max physical addre= ss range - // - ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS); - - switch (Operation) { - case Extensive: - SpanSize =3D 0x4; - break; - - case Sparse: - case Quick: - SpanSize =3D MEMORY_TEST_COVER_SPAN; - break; - - case Ignore: - goto Done; - break; - } - // - // Write the test pattern into memory range - // - TempAddress =3D BeginAddress; - while (TempAddress < BeginAddress + MemoryLength) { - (*(UINT32 *) (UINTN) TempAddress) =3D TestPattern; - TempAddress +=3D SpanSize; - } - // - // Read pattern from memory and compare it - // - TempAddress =3D BeginAddress; - while (TempAddress < BeginAddress + MemoryLength) { - if ((*(UINT32 *) (UINTN) TempAddress) !=3D TestPattern) { - *ErrorAddress =3D TempAddress; - return EFI_DEVICE_ERROR; - } - - TempAddress +=3D SpanSize; - } - -Done: - - return EFI_SUCCESS; -} - -/** - Set Cache Mtrr. -**/ -VOID -SetCacheMtrr ( - VOID - ) -{ - EFI_STATUS Status; - EFI_PEI_HOB_POINTERS Hob; - MTRR_SETTINGS MtrrSetting; - UINT64 MemoryBase; - UINT64 MemoryLength; - UINT64 LowMemoryLength; - UINT64 HighMemoryLength; - EFI_BOOT_MODE BootMode; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - UINT64 CacheMemoryLength; - - /// - /// Reset all MTRR setting. - /// - ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); - - /// - /// Cache the Flash area as WP to boost performance - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), - (UINTN) PcdGet32 (PcdFlashAreaSize), - CacheWriteProtected - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance - /// - MtrrSetAllMtrrs (&MtrrSetting); - - /// - /// Set low to 1 MB. Since 1MB cacheability will always be set - /// until override by CSM. - /// Initialize high memory to 0. - /// - LowMemoryLength =3D 0x100000; - HighMemoryLength =3D 0; - ResourceAttribute =3D ( - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE - ); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - if (BootMode !=3D BOOT_ON_S3_RESUME) { - ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; - } - - Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); - while (!END_OF_HOB_LIST (Hob)) { - if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { - if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || - ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && - (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) - ) { - if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { - HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { - LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; - } - } - } - - Hob.Raw =3D GET_NEXT_HOB (Hob); - } - - DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); - DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); - - /// - /// Assume size of main memory is multiple of 256MB - /// - MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; - MemoryBase =3D 0; - - CacheMemoryLength =3D MemoryLength; - /// - /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB - /// - if (MemoryLength > 0xDC000000) { - CacheMemoryLength =3D 0xC0000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xC0000000; - CacheMemoryLength =3D MemoryLength - 0xC0000000; - if (MemoryLength > 0xE0000000) { - CacheMemoryLength =3D 0x20000000; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - MemoryBase =3D 0xE0000000; - CacheMemoryLength =3D MemoryLength - 0xE0000000; - } - } - - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - CacheMemoryLength, - CacheWriteBack - ); - ASSERT_EFI_ERROR (Status); - - if (LowMemoryLength !=3D MemoryLength) { - MemoryBase =3D LowMemoryLength; - MemoryLength -=3D LowMemoryLength; - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - MemoryBase, - MemoryLength, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } - - /// - /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC - /// - Status =3D MtrrSetMemoryAttributeInMtrrSettings ( - &MtrrSetting, - 0xA0000, - 0x20000, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - /// - /// Update MTRR setting from MTRR buffer - /// - MtrrSetAllMtrrs (&MtrrSetting); - - return ; -} - -VOID -ReportCpuHob ( - VOID - ) -{ - UINT8 PhysicalAddressBits; - UINT32 RegEax; - - AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); - if (RegEax >=3D 0x80000008) { - AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); - PhysicalAddressBits =3D (UINT8) RegEax; - } else { - PhysicalAddressBits =3D 36; - } - - /// - /// Create a CPU hand-off information - /// - BuildCpuHob (PhysicalAddressBits, 16); -} - -/** - Install Firmware Volume Hob's once there is main memory - - @param[in] PeiServices General purpose services available to ever= y PEIM. - @param[in] NotifyDescriptor Notify that this module published. - @param[in] Ppi PPI that was installed. - - @retval EFI_SUCCESS The function completed successfully. -**/ -EFI_STATUS -EFIAPI -MemoryDiscoveredPpiNotifyCallback ( - IN CONST EFI_PEI_SERVICES **PeiServices, - IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, - IN VOID *Ppi - ) -{ - EFI_STATUS Status; - EFI_BOOT_MODE BootMode; - - Status =3D BoardInitAfterMemoryInit (); - ASSERT_EFI_ERROR (Status); - - Status =3D PeiServicesGetBootMode (&BootMode); - ASSERT_EFI_ERROR (Status); - - - ReportCpuHob (); - - TestPointMemoryDiscoveredMtrrFunctional (); - - TestPointMemoryDiscoveredMemoryResourceFunctional (); - - /// - /// If S3 resume, then we are done - /// - if (BootMode =3D=3D BOOT_ON_S3_RESUME) { - return EFI_SUCCESS; - } - - TestPointMemoryDiscoveredDmaProtectionEnabled (); - - if (PcdGetBool (PcdStopAfterMemInit)) { - CpuDeadLoop (); - } - - return Status; -} - - -/** - This function handles PlatformInit task after PeiReadOnlyVariable2 PPI p= roduced - - @param[in] PeiServices Pointer to PEI Services Table. - - @retval EFI_SUCCESS The function completes successfully - @retval others -**/ -EFI_STATUS -EFIAPI -PlatformInitPreMem ( - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - EFI_BOOT_MODE BootMode; - - // - // Start board detection - // - BoardDetect (); - - BoardDebugInit (); - - TestPointDebugInitDone (); - - if (PcdGetBool (PcdStopAfterDebugInit)) { - CpuDeadLoop (); - } - - BootMode =3D BoardBootModeDetect (); - Status =3D PeiServicesSetBootMode (BootMode); - ASSERT_EFI_ERROR (Status); - if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { - Status =3D PeiServicesInstallPpi (&mPpiListRecoveryBootMode); - } - /// - /// Signal possible dependent modules that there has been a - /// final boot mode determination, it is used to build BIST - /// Hob for Dxe use. - /// - Status =3D PeiServicesInstallPpi (&mPpiBootMode); - ASSERT_EFI_ERROR (Status); - - BuildMemoryTypeInformation (); - - if (!PcdGetBool(PcdFspWrapperBootMode)) { - Status =3D PeiServicesInstallPpi (mMemPpiList); - ASSERT_EFI_ERROR (Status); - } - - Status =3D BoardInitBeforeMemoryInit (); - ASSERT_EFI_ERROR (Status); - - return Status; -} - - -/** - Platform Init before memory PEI module entry point - - @param[in] FileHandle Not used. - @param[in] PeiServices General purpose services available to e= very PEIM. - - @retval EFI_SUCCESS The function completes successfully - @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se -**/ -EFI_STATUS -EFIAPI -PlatformInitPreMemEntryPoint ( - IN EFI_PEI_FILE_HANDLE FileHandle, - IN CONST EFI_PEI_SERVICES **PeiServices - ) -{ - EFI_STATUS Status; - - Status =3D PlatformInitPreMem (PeiServices); - - /// - /// After code reorangized, memorycallback will run because the PPI is a= lready - /// installed when code run to here, it is supposed that the InstallEfiM= emory is - /// done before. - /// - Status =3D PeiServicesNotifyPpi (&mMemDiscoveredNotifyList); - - return Status; -} diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index f59248bba4..d1384d9773 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -159,6 +159,7 @@ ####################################### DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf + SetCacheLib|$(PLATFORM_PACKAGE)/Library/SetCacheLib/SetCacheLibNull.inf =20 ####################################### # Platform Package @@ -260,7 +261,7 @@ # Platform Package ####################################### $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf - $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPreMem.inf { + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib= .inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fd= f b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf index 80efab1aad..6827019c25 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf @@ -237,7 +237,7 @@ INF MdeModulePkg/Core/Pei/PeiMain.inf !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf =20 INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf -INF $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/Platfor= mInitPei/PlatformInitPreMem.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM= em.inf INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platfo= rm/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf= b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Intel/M= inPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf deleted file mode 100644 index 76dd67d1a8..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Override/Platform/Inte= l/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +++ /dev/null @@ -1,67 +0,0 @@ -### @file -# Component information file for the Platform Init Pre-Memory PEI module. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -### - -[Defines] - INF_VERSION =3D 0x00010017 - BASE_NAME =3D PlatformInitPreMem - FILE_GUID =3D EEEE611D-F78F-4FB9-B868-55907F169280 - VERSION_STRING =3D 1.0 - MODULE_TYPE =3D PEIM - ENTRY_POINT =3D PlatformInitPreMemEntryPoint - -[LibraryClasses] - BaseMemoryLib - BoardInitLib - DebugLib - HobLib - IoLib - MemoryAllocationLib - MtrrLib - PeimEntryPoint - PeiServicesLib - ReportFvLib - TestPointCheckLib - TimerLib - -[Packages] - MinPlatformPkg/MinPlatformPkg.dec - MdeModulePkg/MdeModulePkg.dec - MdePkg/MdePkg.dec - UefiCpuPkg/UefiCpuPkg.dec - -[Pcd] - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES - -[FixedPcd] - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CO= NSUMES - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CO= NSUMES - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CO= NSUMES - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CO= NSUMES - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CO= NSUMES - -[Sources] - PlatformInitPreMem.c - -[Ppis] - gEfiPeiMemoryDiscoveredPpiGuid - gEfiPeiMasterBootModePpiGuid ## PRODUCES - gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES - gEfiPeiReadOnlyVariable2PpiGuid - gPeiBaseMemoryTestPpiGuid - gPeiPlatformMemorySizePpiGuid - -[Guids] - gEfiMemoryTypeInformationGuid - -[Depex] - gEfiPeiReadOnlyVariable2PpiGuid diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 7e65eeda6f..6df8008215 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -208,6 +208,7 @@ !if $(TARGET) =3D=3D DEBUG TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf !endif + SetCacheLib|$(PLATFORM_PACKAGE)/Library/SetCacheLib/SetCacheLibNull.inf =20 ####################################### # Board Package --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49653): https://edk2.groups.io/g/devel/message/49653 Mute This Topic: https://groups.io/mt/39770822/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 06:24:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49654+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49654+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572438633; cv=none; d=zoho.com; s=zohoarc; b=mQctd9XJzKuPVGyz3Rw3H4RqSNWCC297xCTNIn0ud3Os44sPbCMwhVJYGrelHGV409TWuMhsyME5AggzQAvcm/jnxQKZv2f/PRMACWHeo8ukMyQioqG1Kd75+ScZ1462BnfMZp8HmeJd2Idl4N7w3Kk67jgHxy62wJcNWG1KkT4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572438633; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=L552LnDVZcDFNC3JDJY4fl1MncuTO47wbym+hJZ1enI=; b=YLmj29g8gayZo4/fPEK7Go8LiON9+RvCPvV6XpB7+e1jfndllaW+xWf2X7N2w+MtypZs81WBEL0gRV7qwo08JAPNBz+cKiFQwswDuYFKVbjyUbDvMsL89kgiMswXxBH/aPgu6Zsb7xKJCGmsOdGUeddex/EoSiDSvL3H8QUEgCI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49654+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572438633813891.7759145237446; Wed, 30 Oct 2019 05:30:33 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Urn8YY1788612xXlmoi1D4WX; Wed, 30 Oct 2019 05:30:33 -0700 X-Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web09.4163.1572438626213879058 for ; Wed, 30 Oct 2019 05:30:32 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 05:30:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,247,1569308400"; d="scan'208";a="190262738" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.252.190.81]) by orsmga007.jf.intel.com with ESMTP; 30 Oct 2019 05:30:30 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Michael Kubacki , Nate DeSimone Subject: [edk2-devel] [edk2-platforms: PATCH 3/5] WhiskeylakeOpenBoardPkg: Add SetCacheLib library class. Date: Wed, 30 Oct 2019 20:29:41 +0800 Message-Id: <20191030122943.14432-4-chasel.chiu@intel.com> In-Reply-To: <20191030122943.14432-1-chasel.chiu@intel.com> References: <20191030122943.14432-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: uBSspvrM4L3KaPjTzQvnNIurx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572438633; bh=i7f/1Q70WhsYxOHt8I5eVAzZHkz0jCZSPZTMCzu1aWU=; h=Cc:Date:From:Reply-To:Subject:To; b=mUM8okbN/DnRA1SQO0qOOyS+7KtrdSh+drlsubX30WD/Y/ST7Eq4NjAwAS+FWMgZrm1 eL6U5z7Q08LbDVi/f4a2ykb1RGJkNnlkE+2RFInC0VX0GRgOTo4VGOAiDiHql/EvSxZnM X/gEI5m1JhcmpztK9lfLGtNaCSEgfCVLF7s= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 Whiskeylake board relying on FSP to configure MTRRs so it can include SetCacheLibNull. Test: internal platform can boot with FSP API modes. Cc: Michael Kubacki Cc: Nate DeSimone Signed-off-by: Chasel Chiu --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | = 1 + 1 file changed, 1 insertion(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.dsc index 8e0ea2d5ce..ba06ba3c89 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc @@ -164,6 +164,7 @@ !if $(TARGET) =3D=3D DEBUG TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf !endif + SetCacheLib|$(PLATFORM_PACKAGE)/Library/SetCacheLib/SetCacheLibNull.inf =20 ####################################### # Board Package --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49654): https://edk2.groups.io/g/devel/message/49654 Mute This Topic: https://groups.io/mt/39770824/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 06:24:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49655+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49655+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572438634; cv=none; d=zoho.com; s=zohoarc; b=XzJavOKqmaNROlKqW77o5uWyVC/IJTtsFgOCsq6CReSFKLLEyehNkW0O8XaG7nIqg/DK3MbC+TGGYUbPkavPtgmoXBu4a0gfvvPB2cw4SE62hQjhdt2unXJz61hqrUQ2GuSCZGaHdUCqHfQcAjkieOJR0BOzIHh1s8WKufMjscE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572438634; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=EndtcIyIS1cLmQnsqA9qcWJSDh98qEyuDsOFKfFkKeM=; b=iW6MrEzIS4uwgd6vvajmzz31ocQc4A/6QSSNG2qURoHAh/p7dcwM1/4fC/PicZBwyYYc26xThLOzvF29dNHQLHrv7+renPBVCYoxJd8+nbALgo7ien3jnqFG8PlBmhIsNi86Bl1vSyeuS0k149iDUItsVP534wBR2XCmAVt9HRM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49655+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572438634667363.78808457029686; Wed, 30 Oct 2019 05:30:34 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 2S6BYY1788612xMRynrT1riT; Wed, 30 Oct 2019 05:30:34 -0700 X-Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web09.4163.1572438626213879058 for ; Wed, 30 Oct 2019 05:30:33 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 05:30:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,247,1569308400"; d="scan'208";a="190262757" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.252.190.81]) by orsmga007.jf.intel.com with ESMTP; 30 Oct 2019 05:30:32 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Shifei A Lu , Xiaohu Zhou , Isaac W Oram Subject: [edk2-devel] [edk2-platforms: PATCH 4/5] PurleyOpenBoardPkg/BoardMtOlympus: Add SetCacheLib library class. Date: Wed, 30 Oct 2019 20:29:42 +0800 Message-Id: <20191030122943.14432-5-chasel.chiu@intel.com> In-Reply-To: <20191030122943.14432-1-chasel.chiu@intel.com> References: <20191030122943.14432-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: cBIGMyECseGL0N1C6aqxwEe3x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572438634; bh=TsBRLAbal6OowljQNIUTwy0sXRchFhRpUiIGewudKYQ=; h=Cc:Date:From:Reply-To:Subject:To; b=Ak00PaPj3S2j05/3XRTC/xYmeWhDIwtm7LNxszhqVJUpeM3AW6dpHzXak+uGA3cweOJ C2WpbxgHVPQ+6UtiDCXyK5trEFu8WHVZrXfJWyEH3wHiDVB75xpFUesi+IvVvd0hNpl4/ gm6inD6P2Nnwn0MaT8557ZG8L91vOigW9F0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 Include SetCacheLib from MinPlatformPkg. Cc: Shifei A Lu Cc: Xiaohu Zhou Cc: Isaac W Oram Signed-off-by: Chasel Chiu --- Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.d= sc b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc index 595ffd4144..c7be68d979 100644 --- a/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc +++ b/Platform/Intel/PurleyOpenBoardPkg/BoardMtOlympus/PlatformPkg.dsc @@ -1,6 +1,6 @@ ### @file # -# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -135,6 +135,7 @@ !include $(RC_PKG)/RcDxeLib.dsc !include $(SKT_PKG)/SktDxeLib.dsc !include $(PCH_PKG)/PchDxeLib.dsc + SetCacheLib|MinPlatformPkg/Library/SetCacheLib/SetCacheLib.inf =20 [LibraryClasses.X64] BoardAcpiTableLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardAcpiLib/DxeBoa= rdAcpiTableLib.inf --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49655): https://edk2.groups.io/g/devel/message/49655 Mute This Topic: https://groups.io/mt/39770825/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 18 06:24:50 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49656+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49656+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1572438637; cv=none; d=zoho.com; s=zohoarc; b=GbVCIzGXL1XYsRhUWk5L1snJmHBV0bw4zqmYi5hDvN+K1yBaPbNzF1O5imhso1n7siZcqcQcs/AP0oAJy/HOZFruTTUkzGcLxX6Q36q+Hfb7wnIiQQ1bNvSrsyAR1FQwKs4v4hiHXpLIt8aVkLBLzCmnf//CzWnfH+nmfTyCGqg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1572438637; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=4asjUN5+69tPfnKc2Gjh0Dmbb7DS8AcYNKhhKhZGx+I=; b=bfMi3G8w2km7rggRxq16qqxj4bO1copINsB/zC4kU5u8EtsJNNhZRqwpA+hFYxP7n8oqG75yYiTRKuZLKm0OJZ1i/tkrEubaRqCadM2M9w006AuFqJ7GWpdh14XINS5rMon9b5mQJ6JG0R0r5Gp3m9qjd17NQ8G3YOrlRJyadPs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49656+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1572438637066235.2659504961465; Wed, 30 Oct 2019 05:30:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id c5lEYY1788612xBGCTgqD8UU; Wed, 30 Oct 2019 05:30:36 -0700 X-Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web09.4163.1572438626213879058 for ; Wed, 30 Oct 2019 05:30:35 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Oct 2019 05:30:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,247,1569308400"; d="scan'208";a="190262773" X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.252.190.81]) by orsmga007.jf.intel.com with ESMTP; 30 Oct 2019 05:30:33 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: Wei David Y , Agyeman Prince Subject: [edk2-devel] [edk2-platforms: PATCH 5/5] SimicsOpenBoardPkg/BoardX58Ich10: Add SetCacheLib library class. Date: Wed, 30 Oct 2019 20:29:43 +0800 Message-Id: <20191030122943.14432-6-chasel.chiu@intel.com> In-Reply-To: <20191030122943.14432-1-chasel.chiu@intel.com> References: <20191030122943.14432-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com X-Gm-Message-State: cW35jS7KgJUzdXznnkDH8CqPx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1572438636; bh=gNO5Etk3fbDU1LOAwkO23Dw1XJnbFI8yEzJRMl3XUJ8=; h=Cc:Date:From:Reply-To:Subject:To; b=C9ReDg/0BrPCSaoBYQnlxX/mkhJ6Ro3abb1yTJVibe8zoO/GSVti6KBsKuBmYCRfqG2 1Zb2M2mCJ9RmiJFsoCFR34UgWbRO+9P8m2yz4odtyP37NAKhm2E2AmHt7Hd9hw8jM5pik V08Je9rOwdh7hBduvw5An5AQCoADppELRDE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2314 Include SetCacheLib from MinPlatformPkg. Cc: Wei David Y Cc: Agyeman Prince Signed-off-by: Chasel Chiu --- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 1 + 1 file changed, 1 insertion(+) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.d= sc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc index 4f8ab4170d..85691c55dd 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc @@ -136,6 +136,7 @@ TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf !endif TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf + SetCacheLib|$(PLATFORM_PACKAGE)/Library/SetCacheLib/SetCacheLib.inf =20 [LibraryClasses.common.DXE_DRIVER] ####################################### --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49656): https://edk2.groups.io/g/devel/message/49656 Mute This Topic: https://groups.io/mt/39770827/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-