From nobody Tue May 7 11:22:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49244+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49244+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1571427357; cv=none; d=zoho.com; s=zohoarc; b=Lr/v/K3mGbIxpfEuyKjT9tjkB2/li+ms/NRbVKYp4LHkJsDIgI0GCdjodgv9euvGxNcqB+r048tgN21g0fND+8cAuic/zrkmvoZF7WsboInNKbMa8wV0FsVSlPkCisjQTXTdiNZFda5R9I3bFTjSSr3i2cVNIynwdio2WSKs/wU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571427357; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=NGvKSxZBieuN5I8qxdXKFzld8hTGs0+YTbmTM7ApE40=; b=ntTTRm/QYXHMMcabjvx15y/OKRfPyDHphpJSngyyRot3ESP8/ChsHmkK44fK6fGwAuwTGmAeVYlTeHwdWX+iFdWZ2j42FBl1pU7IWcSaGRBJIGeMRxcLQJxTLi64wBHbecRQLv2Tpzjexxch7fO/QxFd3ZctARvcYnW6m8QfZq0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49244+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15714273575821001.7440052825251; Fri, 18 Oct 2019 12:35:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id SG2RYY1788612xxx0iL7KMKf; Fri, 18 Oct 2019 12:35:56 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web12.946.1571427280671928858 for ; Fri, 18 Oct 2019 12:34:41 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Oct 2019 12:34:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,312,1566889200"; d="scan'208";a="398041802" X-Received: from unknown (HELO mdkinney-MOBL2.amr.corp.intel.com) ([10.241.111.156]) by fmsmga006.fm.intel.com with ESMTP; 18 Oct 2019 12:34:40 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Sean Brogan , Ray Ni Subject: [edk2-devel] [Patch] PcAtChipsetPkg: Fix spelling errors Date: Fri, 18 Oct 2019 12:34:37 -0700 Message-Id: <20191018193437.3100-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com X-Gm-Message-State: TvLjCNjx8ybFrKtBT8oYyElIx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1571427356; bh=V4+goFqFcB9SwWkHv0rMOenwt13xD44oMi5ANM93tmM=; h=Cc:Date:From:Reply-To:Subject:To; b=Pn3fzPlWV1vvhNqCXn44Ez6Qcbvx0TCBmtY/sXyRERdxhydQg7FoSoAZUkGa+a0SlfS Sz9Vu/J5qW7ZTkqAozKwLtmLPtaGiCU2TiQo5BV5GC8BgmSyuFwWcr68XA375duBvlqym s6WK0Vqa6CDeqiOtclf4ZJUw/6xu3YoTnew= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Sean Brogan https://bugzilla.tianocore.org/show_bug.cgi?id=3D2263 Cc: Ray Ni Signed-off-by: Michael D Kinney Reviewed-by: Ray Ni --- PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c | 12 ++++++------ PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf | 2 +- PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni | 2 +- PcAtChipsetPkg/Include/Library/IoApicLib.h | 2 +- PcAtChipsetPkg/Include/Register/Hpet.h | 6 +++--- PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c | 2 +- PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c | 8 ++++---- PcAtChipsetPkg/PcAtChipsetPkg.dec | 2 +- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c | 4 ++-- PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h | 8 ++++---- .../PcatRealTimeClockRuntimeDxe/PcRtcEntry.c | 2 +- 11 files changed, 25 insertions(+), 25 deletions(-) diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c b/PcAtChipsetPkg/HpetT= imerDxe/HpetTimer.c index ded3b53619..cbe986ebfd 100644 --- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c @@ -1,5 +1,5 @@ /** @file - Timer Architectural Protocol module using High Precesion Event Timer (HP= ET) + Timer Architectural Protocol module using High Precision Event Timer (HP= ET) =20 Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -246,7 +246,7 @@ HpetRead ( /** Write a 64-bit HPET register. =20 - @param Offset Specifies the ofsfert of the HPET register to write. + @param Offset Specifies the offset of the HPET register to write. @param Value Specifies the value to write to the HPET register specif= ied by Offset. =20 @return The 64-bit value written to HPET register specified by Offset. @@ -530,7 +530,7 @@ TimerDriverSetTimerPeriod ( // If TimerPeriod is 0, then mask HPET Timer interrupts // =20 - if (mTimerConfiguration.Bits.MsiInterruptCapablity !=3D 0 && FeaturePc= dGet (PcdHpetMsiEnable)) { + if (mTimerConfiguration.Bits.MsiInterruptCapability !=3D 0 && FeatureP= cdGet (PcdHpetMsiEnable)) { // // Disable HPET MSI interrupt generation // @@ -576,7 +576,7 @@ TimerDriverSetTimerPeriod ( // // Enable HPET Timer interrupt generation // - if (mTimerConfiguration.Bits.MsiInterruptCapablity !=3D 0 && FeaturePc= dGet (PcdHpetMsiEnable)) { + if (mTimerConfiguration.Bits.MsiInterruptCapability !=3D 0 && FeatureP= cdGet (PcdHpetMsiEnable)) { // // Program MSI Address and MSI Data values in the selected HPET Timer // Program HPET register with APIC ID of current BSP in case BSP has= been switched @@ -834,7 +834,7 @@ TimerDriverInitialize ( // // Check to see if this HPET Timer supports MSI // - if (mTimerConfiguration.Bits.MsiInterruptCapablity !=3D 0) { + if (mTimerConfiguration.Bits.MsiInterruptCapability !=3D 0) { // // Save the index of the first HPET Timer that supports MSI interrup= ts // @@ -959,7 +959,7 @@ TimerDriverInitialize ( // Show state of enabled HPET timer // DEBUG_CODE ( - if (mTimerConfiguration.Bits.MsiInterruptCapablity !=3D 0 && FeaturePc= dGet (PcdHpetMsiEnable)) { + if (mTimerConfiguration.Bits.MsiInterruptCapability !=3D 0 && FeatureP= cdGet (PcdHpetMsiEnable)) { DEBUG ((DEBUG_INFO, "HPET Interrupt Mode MSI\n")); } else { DEBUG ((DEBUG_INFO, "HPET Interrupt Mode I/O APIC\n")); diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf b/PcAtChipsetPkg/= HpetTimerDxe/HpetTimerDxe.inf index ba2e075118..125eea0aab 100644 --- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf @@ -1,5 +1,5 @@ ## @file -# Timer Architectural Protocol module using High Precesion Event Timer (HP= ET). +# Timer Architectural Protocol module using High Precision Event Timer (HP= ET). # # Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni b/PcAtChipsetPkg/= HpetTimerDxe/HpetTimerDxe.uni index e2320653b6..7d1797b1df 100644 --- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni +++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni @@ -1,5 +1,5 @@ // /** @file -// Timer Architectural Protocol module using High Precesion Event Timer (H= PET). +// Timer Architectural Protocol module using High Precision Event Timer (H= PET). // // Timer Architectural Protocol module using High Precision Event Timer (H= PET). // diff --git a/PcAtChipsetPkg/Include/Library/IoApicLib.h b/PcAtChipsetPkg/In= clude/Library/IoApicLib.h index 200ef731fb..4ee092c0f2 100644 --- a/PcAtChipsetPkg/Include/Library/IoApicLib.h +++ b/PcAtChipsetPkg/Include/Library/IoApicLib.h @@ -63,7 +63,7 @@ IoApicEnableInterrupt ( Configures an I/O APIC interrupt. =20 Configure an I/O APIC Redirection Table Entry to deliver an interrupt in= physical - mode to the Local APIC of the currntly executing CPU. The default state= of the + mode to the Local APIC of the currently executing CPU. The default stat= e of the entry is for the interrupt to be disabled (masked). IoApicEnableInterru= pts() must be used to enable(unmask) the I/O APIC Interrupt. =20 diff --git a/PcAtChipsetPkg/Include/Register/Hpet.h b/PcAtChipsetPkg/Includ= e/Register/Hpet.h index f7c0174e14..8437ec1f2d 100644 --- a/PcAtChipsetPkg/Include/Register/Hpet.h +++ b/PcAtChipsetPkg/Include/Register/Hpet.h @@ -70,14 +70,14 @@ typedef union { UINT32 LevelTriggeredInterrupt:1; UINT32 InterruptEnable:1; UINT32 PeriodicInterruptEnable:1; - UINT32 PeriodicInterruptCapablity:1; - UINT32 CounterSizeCapablity:1; + UINT32 PeriodicInterruptCapability:1; + UINT32 CounterSizeCapability:1; UINT32 ValueSetEnable:1; UINT32 Reserved1:1; UINT32 CounterSizeEnable:1; UINT32 InterruptRoute:5; UINT32 MsiInterruptEnable:1; - UINT32 MsiInterruptCapablity:1; + UINT32 MsiInterruptCapability:1; UINT32 Reserved2:16; UINT32 InterruptRouteCapability; } Bits; diff --git a/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c b/PcAtChipset= Pkg/Library/BaseIoApicLib/IoApicLib.c index 7a3c9aca8d..9e4a58049e 100644 --- a/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c +++ b/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c @@ -94,7 +94,7 @@ IoApicEnableInterrupt ( Configures an I/O APIC interrupt. =20 Configure an I/O APIC Redirection Table Entry to deliver an interrupt in= physical - mode to the Local APIC of the currntly executing CPU. The default state= of the + mode to the Local APIC of the currently executing CPU. The default stat= e of the entry is for the interrupt to be disabled (masked). IoApicEnableInterru= pts() must be used to enable(unmask) the I/O APIC Interrupt. =20 diff --git a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c b/PcAtChips= etPkg/Library/SerialIoLib/SerialPortLib.c index 93affe151e..25c4cefc13 100644 --- a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c +++ b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c @@ -195,7 +195,7 @@ SerialPortRead ( /** Polls a serial device to see if there is any data waiting to be read. =20 - Polls aserial device to see if there is any data waiting to be read. + Polls a serial device to see if there is any data waiting to be read. If there is data waiting to be read from the serial device, then TRUE is= returned. If there is no data waiting to be read from the serial device, then FALS= E is returned. =20 @@ -339,13 +339,13 @@ SerialPortGetControl ( } =20 /** - Sets the baud rate, receive FIFO depth, transmit/receice time out, parit= y, + Sets the baud rate, receive FIFO depth, transmit/receive time out, parit= y, data bits, and stop bits on a serial device. =20 @param BaudRate The requested baud rate. A BaudRate value of 0= will use the device's default interface speed. On output, the value actually set. - @param ReveiveFifoDepth The requested depth of the FIFO on the receive= side of the + @param ReceiveFifoDepth The requested depth of the FIFO on the receive= side of the serial interface. A ReceiveFifoDepth value of = 0 will use the device's default FIFO depth. On output, the value actually set. @@ -358,7 +358,7 @@ SerialPortGetControl ( DefaultParity will use the device's default pa= rity value. On output, the value actually set. @param DataBits The number of data bits to use on the serial d= evice. A DataBits - vaule of 0 will use the device's default data = bit setting. + value of 0 will use the device's default data = bit setting. On output, the value actually set. @param StopBits The number of stop bits to use on this serial = device. A StopBits value of DefaultStopBits will use the device's= default number of diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec b/PcAtChipsetPkg/PcAtChipset= Pkg.dec index aad53b07c8..88de5cceea 100644 --- a/PcAtChipsetPkg/PcAtChipsetPkg.dec +++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec @@ -50,7 +50,7 @@ [PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatcha= bleInModule] # @Prompt HPET local APIC vector. gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x000000= 0A =20 - ## This PCD specifies the defaut period of the HPET Timer in 100 ns unit= s. + ## This PCD specifies the default period of the HPET Timer in 100 ns uni= ts. # The default value of 100000 100 ns units is the same as 10 ms. # @Prompt Default period of HPET timer. gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x= 0000000B diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChips= etPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c index 8b68b0f192..52af179417 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c @@ -1051,9 +1051,9 @@ IsLeapYear ( } =20 /** - Converts time from EFI_TIME format defined by UEFI spec to RTC's. + Converts time from EFI_TIME format defined by UEFI spec to RTC format. =20 - This function converts time from EFI_TIME format defined by UEFI spec to= RTC's. + This function converts time from EFI_TIME format defined by UEFI spec to= RTC format. If data mode of RTC is BCD, then converts EFI_TIME to it. If RTC is in 12-hour format, then converts EFI_TIME to it. =20 diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChips= etPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h index 038482d04d..47293ce44c 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h @@ -110,7 +110,7 @@ typedef struct { UINT8 Uf : 1; // Update End Interrupt Flag UINT8 Af : 1; // Alarm Interrupt Flag UINT8 Pf : 1; // Periodic Interrupt Flag - UINT8 Irqf : 1; // Iterrupt Request Flag =3D PF & PIE | AF & AIE | U= F & UIE + UINT8 Irqf : 1; // Interrupt Request Flag =3D PF & PIE | AF & AIE | = UF & UIE } RTC_REGISTER_C_BITS; =20 typedef union { @@ -234,7 +234,7 @@ PcRtcGetWakeupTime ( /** The user Entry Point for PcRTC module. =20 - This is the entrhy point for PcRTC module. It installs the UEFI runtime = service + This is the entry point for PcRTC module. It installs the UEFI runtime s= ervice including GetTime(),SetTime(),GetWakeupTime(),and SetWakeupTime(). =20 @param ImageHandle The firmware allocated handle for the EFI image. @@ -266,9 +266,9 @@ RtcTimeFieldsValid ( ); =20 /** - Converts time from EFI_TIME format defined by UEFI spec to RTC's. + Converts time from EFI_TIME format defined by UEFI spec to RTC format. =20 - This function converts time from EFI_TIME format defined by UEFI spec to= RTC's. + This function converts time from EFI_TIME format defined by UEFI spec to= RTC format. If data mode of RTC is BCD, then converts EFI_TIME to it. If RTC is in 12-hour format, then converts EFI_TIME to it. =20 diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c b/PcAt= ChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c index dca3b8d9ff..ccda633137 100644 --- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c +++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c @@ -108,7 +108,7 @@ PcRtcEfiSetWakeupTime ( /** The user Entry Point for PcRTC module. =20 - This is the entrhy point for PcRTC module. It installs the UEFI runtime = service + This is the entry point for PcRTC module. It installs the UEFI runtime s= ervice including GetTime(),SetTime(),GetWakeupTime(),and SetWakeupTime(). =20 @param ImageHandle The firmware allocated handle for the EFI image. --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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