From nobody Sun May 5 09:46:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+49123+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49123+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1571267920; cv=none; d=zoho.com; s=zohoarc; b=Jk+JzK2/wnuoJ4tDo7qNzfCE0/HoCMOkTnFYQht1A//kcGFsFH5VEot1LUTdXGPpv2kb2GO2wsKLg1oP1xmOYZfXpADpMq4EypBMaprLClpwlCH2AcAkPuCkpsYQL87U3pR4Vmff0ZPb74QG9oZPghRWsW9jz+ACmCGfCe7u4ew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1571267920; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To; bh=1pun85B9oll3Ay5cICkjcN3qtuy8vv0naq/nTkw280A=; b=Ya/mo+QSjn8kBVBi5YUBSx9MmmENIP9U6wGoKD6o0Uy8nGvFG9AxFJn5XStaSsMxqMp/xN++FMlKfnRkO2Tq37oNgObAsWoi2qt1aqcTSnv4pJqk0dNc+O7HUEG48Q+eOhyu7OIfVIMu2nopR7pWOtGrCS9FghxjFVcCRr5jWFQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+49123+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1571267920199479.2326776054232; Wed, 16 Oct 2019 16:18:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id MqbRYY1788612x1yLNBw2zzG; Wed, 16 Oct 2019 16:18:39 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.2630.1571266926473050295 for ; Wed, 16 Oct 2019 16:02:06 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Oct 2019 16:02:05 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,305,1566889200"; d="scan'208";a="279685785" X-Received: from iwenevel-dev01.amr.corp.intel.com ([10.9.70.66]) by orsmga001.jf.intel.com with ESMTP; 16 Oct 2019 16:02:05 -0700 From: Evelyn Wang To: devel@edk2.groups.io Cc: Jenny Huang , More Shih , Ray Ni , Rangasai V Chaganty , Jiewen Yao Subject: [edk2-devel] [PATCH] IntelSiliconPkg-Vtd: Code Optimization Date: Wed, 16 Oct 2019 16:01:53 -0700 Message-Id: <20191016230153.2392-1-iwen.evelyn.wang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,iwen.evelyn.wang@intel.com X-Gm-Message-State: t0xIB0tYZbbmiWuVGUOkMuAgx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1571267919; bh=XdiCCU6GsYFb7nvRerl8OSIeb4aOQWUq1ULhnxX/MLQ=; h=Cc:Date:From:Reply-To:Subject:To; b=e5EmqyDFsVeKAS/72avchjfAxcEbq/sQxUHZuGpmCq38D05/AXvaPJM+xbUkzhciYE4 a/pUDgR/rqgHNPwxl+01eQeHUfxduD1MeHFYMcVON8w+68HQwVlbQb2cV76OZBRyxtwnu 0ECRkxpAoCFEYK+8JwVFe33GMy2hJnplc38= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1770 1) DisableDMAr Function Code Optimization Optimize the flow to follow the VT-d spec requirements. 2) Renamed InitDmar() to InitGlobalVtd() The oringal function name is misleading Signed-off-by: Evelyn Wang Cc: Jenny Huang Cc: More Shih Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Jiewen Yao Reviewed-by: Ray Ni --- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c = | 30 +++++++++++++++++++++++++++--- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c = | 29 ++++++++++++++++++++++++++--- Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Platfor= mVTdInfoSamplePei.c | 9 +++++---- 3 files changed, 58 insertions(+), 10 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 22bf821d2b..699639ba88 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -309,6 +309,8 @@ DisableDmar ( UINTN Index; UINTN SubIndex; UINT32 Reg32; + UINT32 Status; + UINT32 Command; =20 for (Index =3D 0; Index < mVtdUnitNumber; Index++) { DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index)); @@ -319,9 +321,31 @@ DisableDmar ( FlushWriteBuffer (Index); =20 // - // Disable VTd + // Disable Dmar // - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, B_GMCD_REG_SRTP); + // + // Set TE (Translation Enable: BIT31) of Global command register to ze= ro + // + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & ~B_GMCD_REG_TE); + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); + + // + // Poll on TE Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + + // + // Set SRTP (Set Root Table Pointer: BIT30) of Global command register= in order to update the root table pointerDisable VTd + // + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | B_GMCD_REG_SRTP); + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); + do { Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdRe= g.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c index 4774a2ae5b..c9669426aa 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -197,6 +197,8 @@ DisableDmar ( ) { UINT32 Reg32; + UINT32 Status; + UINT32 Command; =20 DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBase= Address)); =20 @@ -206,9 +208,30 @@ DisableDmar ( FlushWriteBuffer (VtdUnitBaseAddress); =20 // - // Disable VTd + // Disable Dmar // - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP); + // + // Set TE (Translation Enable: BIT31) of Global command register to zero + // + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & ~B_GMCD_REG_TE); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + // + // Poll on TE Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + + // + // Set SRTP (Set Root Table Pointer: BIT30) of Global command register i= n order to update the root table pointerDisable VTd + // + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | B_GMCD_REG_SRTP); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); do { Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSampl= ePei/PlatformVTdInfoSamplePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd= /PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c index 3698c3d3f1..6f6c14f7a9 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePei.c @@ -1,7 +1,7 @@ /** @file Platform VTd Info Sample PEI driver. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -166,15 +166,16 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDes= c =3D { =20 /** Initialize VTd register. + Initialize the VTd hardware unit which has INCLUDE_PCI_ALL set **/ VOID -InitDmar ( +InitGlobalVtd ( VOID ) { UINT32 MchBar; =20 - DEBUG ((DEBUG_INFO, "InitDmar\n")); + DEBUG ((DEBUG_INFO, "InitGlobalVtd\n")); =20 MchBar =3D PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0; PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 | BIT0); @@ -346,7 +347,7 @@ PlatformVTdInfoSampleInitialize ( DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized)); if (!SiliconInitialized) { Status =3D PeiServicesNotifyPpi (&mSiliconInitializedNotifyList); - InitDmar (); + InitGlobalVtd (); =20 Status =3D PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc); ASSERT_EFI_ERROR (Status); --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#49123): https://edk2.groups.io/g/devel/message/49123 Mute This Topic: https://groups.io/mt/34656317/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-