From nobody Mon Feb 9 17:24:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48537+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48537+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511836; cv=none; d=zoho.com; s=zohoarc; b=Ac95nv3uMUU8h5Aed1svBJPd5Ukv7YItChy2y9E0qWia+R+FvzeqspB/d+lqH8IOYj3RUFu0J2sOyF6ZbbL/V9BTZl7K6DKf1TC9puHgIB58nVH3Wz5RAf8pPpbQjcdL1tZWElMLw3GuOXIY1wKMwg5P7c67ivUwMc9cmt2YE40= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511836; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=Bmt1ZKtCcvbHuIKQhIjw9nz2LG2/CyrNDox65TBhex8=; b=JEN6JQMm1QK0HCs2QSy2cb+T4ZbaG/okSlLw1s+zw/sPpE6nUMxRD42f2/4fa8IIdq5zEu7bht9n/1mrcp/2WR+PWhWg+PngUV0/Y7KyD19CpK48DszhqMjQmikm3DXIT9vgJjdesFG7UrzHdNPwyc1i4hAsza6ywjd1kFQU9n4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48537+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511836876753.2813547179325; Mon, 7 Oct 2019 22:17:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8t49YY1788612xYTiNVwbOw5; Mon, 07 Oct 2019 22:17:16 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:15 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297296" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:15 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH V1 09/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Remove OpenBoardPkgConfig.dsc Date: Mon, 7 Oct 2019 22:16:37 -0700 Message-Id: <20191008051645.22052-10-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: FJA7lfQY2oZqztfOAw6f9EWNx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511836; bh=Py9EhqZuazyjoMcoFIL38gW/yXRxPvAFjSQTarK39gk=; h=Cc:Date:From:Reply-To:Subject:To; b=MXCIZ+yviJvXKLh7vBM4viQBnFJQI3b4oL9bHbXf5sqZ7ZthYZtlhq/dCPJM4gDiJpe vjW78Gqz5PWcyS+t1AdiR/mKwfrHnJYR0UnbHEYIQxhrQzRANPdqegHipsexsZG7FGQ6U f++W/RKl7fWIgg2Noz4um73JWRNQH1g/HIY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2243 The location for PCD configuration is currently inconsistent in WhiskeylakeOpenBoardPkg. A large set of FeaturePCD definitions are in OpenBoardPkgConfig.dsc while other PCD definitions (including FeaturePCD) are located in OpenBoardPkgPcd.dsc. This change consolidates PCD configuration for the WhiskeylakeURvp board to OpenBoardPkgPcd.dsc and removes OpenBoardPkgConfig.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc = | 1 - Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgConfig.= dsc | 128 -------------------- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc= | 116 ++++++++++++++++++ 3 files changed, 116 insertions(+), 129 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.dsc index 9a516cad60..1d07fdea84 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc @@ -26,7 +26,6 @@ # # Platform On/Off features are defined here # - !include OpenBoardPkgConfig.dsc !include OpenBoardPkgPcd.dsc =20 ##########################################################################= ###### diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgConfig.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Op= enBoardPkgConfig.dsc deleted file mode 100644 index c68fecf50e..0000000000 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgCo= nfig.dsc +++ /dev/null @@ -1,128 +0,0 @@ -## @file -# Platform configuration file. -# -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[PcdsFixedAtBuild] - # - # Please select BootStage here. - # Stage 1 - enable debug (system deadloop after debug init) - # Stage 2 - mem init (system deadloop after mem init) - # Stage 3 - boot to shell only - # Stage 4 - boot to OS - # Stage 5 - boot to OS with security boot enabled - # - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 - -[PcdsFeatureFlag] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE -!endif - - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - -# -# TRUE is ENABLE. FALSE is DISABLE. -# -# -# BIOS build switches configuration -# - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - -# CPU - gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE - -# SA - gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE - gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE - -# ME - gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE - gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE - - gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE - gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE - gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE - gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE - gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE -= HPET / FALSE - 8254 timer is used. - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE - - gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE - gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE - -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # - - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE - - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif - - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif - - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE - diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenB= oardPkgPcd.dsc index 96d65133ae..24e3da6686 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc @@ -14,7 +14,123 @@ # Pcd Section - list of all EDK II PCD Entries defined by this Platform # ##########################################################################= ###### +[PcdsFixedAtBuild] + # + # Please select BootStage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + [PcdsFeatureFlag.common] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + # + # More fine granularity control below: + # + + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + +# +# TRUE is ENABLE. FALSE is DISABLE. +# +# +# BIOS build switches configuration +# + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + +# CPU + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + +# SA + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE + +# ME + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE + + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE + gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE -= HPET / FALSE - 8254 timer is used. + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE + gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE + +# +# Override some PCDs for specific build requirements. +# + # + # Disable USB debug message when Source Level Debug is enabled + # because they cannot be enabled at the same time. + # + + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE + + !if $(TARGET) =3D=3D DEBUG + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !else + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !endif + + !if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + #gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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