From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48529+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48529+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511821; cv=none; d=zoho.com; s=zohoarc; b=WVsd1W1o3od+xTytYy46LUkoYiqxpn2HM2io7U8Rhc2FdXf8I7+SvlOq4H4hTn4GiKb3lCYAsg5pzVOZOijRDyebF020J5jMu2Djjn6cTAd+//OKbMzF0O+7oB3ZZWhMGdinViODBD2zbm0exlXSpLTocwpVK8aZB10vSDx8WdU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511821; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=6MMQqXD0PsZ727RFzfur3jGYoo7nm4CkZT40GetByBY=; b=f0a3K5v8q2Ps7snr9pUsH3Rzb+wbyMFsS1+CTNl4XlQzKfEEmlMm7IDDA19mXBrE2iBvOvVj89/gUEpRl26k1p8j5HMrOTtfV64WWV7mvjhVZQOxueK/gic12W82NYnVzLcBIi1lYdfwjF2Jp3Qz4vxxDa1Ypt6hOaAAsgo2xeg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48529+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511821376497.57812374924356; Mon, 7 Oct 2019 22:17:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id V0mSYY1788612xJ4TFGUL2MU; Mon, 07 Oct 2019 22:17:00 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by groups.io with SMTP; Mon, 07 Oct 2019 22:16:59 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:16:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297208" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:16:58 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH V1 01/17] KabylakeOpenBoardPkg/KabylakeRvp3: Remove OpenBoardPkgConfig.dsc Date: Mon, 7 Oct 2019 22:16:29 -0700 Message-Id: <20191008051645.22052-2-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: 954CexlrBH4kU1meCJ2d3jx7x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511820; bh=L5f125foYd2vpTnw8aWa4VsxM7JxT/DhIyWGx700rEY=; h=Cc:Date:From:Reply-To:Subject:To; b=fGDj2qsCbx7PjWxG23oj6Y9AAtjR+bUP42m58YHgc0VmBCPrFrt5NSNk1AHeME0DPRa bp24T5EeaZwZx79QOymcw3DSAuFZn1y22k3uDAg1UA9Tlgm/PZrpqWdTIFNlvK1+7oWKd dwiZ5rHFlhVi0Ac49vuW0fHZE1jkh9fUowM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2242 The location for PCD configuration is currently inconsistent in KabylakeOpenBoardPkg. A large set of FeaturePCD definitions are in OpenBoardPkgConfig.dsc while other PCD definitions (including FeaturePCD) are located in OpenBoardPkgPcd.dsc. This change consolidates PCD configuration for the KabylakeRvp3 board to OpenBoardPkgPcd.dsc and removes OpenBoardPkgConfig.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | = 1 - Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.dsc | = 138 -------------------- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | = 132 ++++++++++++++++++- 3 files changed, 130 insertions(+), 141 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 7090852192..a3378d3c5d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -22,7 +22,6 @@ # # Platform On/Off features are defined here # - !include OpenBoardPkgConfig.dsc !include OpenBoardPkgPcd.dsc =20 [Defines] diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgC= onfig.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgCo= nfig.dsc deleted file mode 100644 index 15468494dd..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgConfig.d= sc +++ /dev/null @@ -1,138 +0,0 @@ -## @file -# Platform configuration file. -# -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[PcdsFixedAtBuild] - # - # Please select BootStage here. - # Stage 1 - enable debug (system deadloop after debug init) - # Stage 2 - mem init (system deadloop after mem init) - # Stage 3 - boot to shell only - # Stage 4 - boot to OS - # Stage 5 - boot to OS with security boot enabled - # - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 - =20 -[PcdsFeatureFlag] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE -!endif - =20 - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - =20 - =20 - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - - - -# -# TRUE is ENABLE. FALSE is DISABLE. -# - -# -# BIOS build switches configuration -# - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - -# CPU - gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build @tod= o Convert TXT ASM to NASM - gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE - -# SA - gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE - gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE - gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE - -# ME - gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE - gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE - - gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE - gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE - gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE - gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE - gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE - gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE - -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # - - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - - - - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif - - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif - - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index 2009bb225a..edb4013cc0 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -12,7 +12,135 @@ # Pcd Section - list of all EDK II PCD Entries defined by this Platform # ##########################################################################= ###### +[PcdsFixedAtBuild] + # + # Please select BootStage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + [PcdsFeatureFlag.common] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + # + # More fine granularity control below: + # + + + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + + + +# +# TRUE is ENABLE. FALSE is DISABLE. +# + +# +# BIOS build switches configuration +# + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + +# CPU + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build @tod= o Convert TXT ASM to NASM + gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE + +# SA + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE + gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE + +# ME + gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE + + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE + gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + +# +# Override some PCDs for specific build requirements. +# + # + # Disable USB debug message when Source Level Debug is enabled + # because they cannot be enabled at the same time. + # + + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE + + + + !if $(TARGET) =3D=3D DEBUG + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !else + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !endif + + !if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE !if $(TARGET) =3D=3D RELEASE @@ -274,7 +402,7 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 - =20 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 =20 [PcdsDynamicDefault.common.DEFAULT] @@ -283,7 +411,7 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0 gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 - =20 + # Tbt gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn | 0x1 gBoardModuleTokenSpaceGuid.PcdDTbtControllerType | 0x1 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48529): https://edk2.groups.io/g/devel/message/48529 Mute This Topic: https://groups.io/mt/34439436/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48530+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48530+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511821; cv=none; d=zoho.com; s=zohoarc; b=IR9BPsrgGtlQfJdrFC5pa61hc3WAfppuLdy04OiHiajjaoc9kLmuWLZJFK1am/2RfeyccQL2Cr8QAfBQYXkDHu1EN0WboBHFLl0stgixbTj4UPietLcD1JhM42bB/Yj2jWt8Sj6iy2xRbLYH8yaqHb0lsKpWoADQWwoCkxY4Czo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511821; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=C/0SSo+OrtFdmBBWPcWvSGM90bXXMjmU0hI27sxWwe0=; b=miVDT4rXtzuTfWBdXoMa6wK/KfYx3eeoPSecWsGHuxWCgnW0I/6J+6Z6M3EVrZutycEB+qEmC1wYq/+F0CuP44vOiMayFbv42rJ1VCgPBR5SNREwLBmsgfFy75ptb8Wf1BQxJau7TFKjSKQxIBscgI4u0IgoFndhgyuPkjnJ3aQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48530+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511821515703.7899119788591; Mon, 7 Oct 2019 22:17:01 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5JRzYY1788612xzAiBezaobW; Mon, 07 Oct 2019 22:17:01 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:00 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297212" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:00 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu Subject: [edk2-devel] [edk2-platforms][PATCH V1 02/17] KabylakeSiliconPkg: Add DSC include file section tags Date: Mon, 7 Oct 2019 22:16:30 -0700 Message-Id: <20191008051645.22052-3-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: yXtJuAFu5D7bNfB4MporOxSXx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511821; bh=LsNXEGGeXSm7BBFj5/1yXYsQu5CkvwMQCvlPrRQeOf8=; h=Cc:Date:From:Reply-To:Subject:To; b=CUl8KAY/TsJxoGcPfMTOuxf2Ajx6lqlaTMQONdSNtrGKrlzTXrtAHxKVqdRhGWJBeT7 W1qdYamFefJKrX4rNn8QLeg49uiISw7h1WdkHpFg6Ewx9D+Dwfx+5pIIbvAHCULELw2K7 9yJFozilQOSD0SfgZBz3/zPFfUGqlzjVTPY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2245 The DSC LibraryClass files in KabylakeSiliconPkg that are intended to be included elsewhere such as SiPkgPeiLib.dsc, SiPkgDxeLib.dsc, and SiPkgCommonLib.dsc should have section tags so that they are not dependent on the top-level DSC file to place the include file in the correct location in the DSC file and better define the applicability of their library content. This change adds section tags for the library class related files. The component files may be built differently in the consuming package depending on their architecture requirements so those are not modified. Cc: Sai Chaganty Cc: Chasel Chiu Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Silicon/Intel/KabylakeSiliconPkg/SiPkgCommonLib.dsc | 6 ++++-- Silicon/Intel/KabylakeSiliconPkg/SiPkgDxeLib.dsc | 5 +++-- Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc | 3 ++- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkgCommonLib.dsc b/Silicon/= Intel/KabylakeSiliconPkg/SiPkgCommonLib.dsc index 920b02e410..fa9dd4a32d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkgCommonLib.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkgCommonLib.dsc @@ -1,11 +1,13 @@ ## @file -# Component description file for the SkyLake SiPkg both Pei and Dxe libra= ries DSC file. +# Build description file for Kaby Lake silicon PEI and DXE libraries. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[LibraryClasses.common] # # Silicon Init Common Library # diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkgDxeLib.dsc b/Silicon/Int= el/KabylakeSiliconPkg/SiPkgDxeLib.dsc index 8c194d8e7c..bc497c3531 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkgDxeLib.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkgDxeLib.dsc @@ -1,12 +1,13 @@ # @file -# Component description file for the SkyLake SiPkg DXE libraries. +# Build description file for Kaby Lake silicon DXE libraries. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 +[LibraryClasses.common.DXE_CORE,LibraryClasses.common.DXE_SMM_DRIVER,Libra= ryClasses.common.SMM_CORE,LibraryClasses.common.DXE_DRIVER,LibraryClasses.c= ommon.DXE_RUNTIME_DRIVER,LibraryClasses.common.UEFI_DRIVER] # # Silicon Init Dxe Library # diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc b/Silicon/Int= el/KabylakeSiliconPkg/SiPkgPeiLib.dsc index 86e34ff359..5334598544 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkgPeiLib.dsc @@ -1,5 +1,5 @@ ## @file -# Component description file for the SkyLake SiPkg PEI libraries. +# Build description file for Kaby Lake silicon PEI libraries. # # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# @@ -7,6 +7,7 @@ # ## =20 +[LibraryClasses] # # Silicon Init Pei Library # --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48530): https://edk2.groups.io/g/devel/message/48530 Mute This Topic: https://groups.io/mt/34439437/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48531+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48531+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511823; cv=none; d=zoho.com; s=zohoarc; b=HCN6S8OymHQO/LGLbuTYvRP2DOASTBfwo0BRHXWYrNcKqpgmDj7QGURv0y+qb8XUXK4gGGi3gva2+wkE+tvxs97kwnB75E6yh9q6IlW3dHSpr6UrqyfK5DfIQOuABjrBT8CyC2TRfUIWSwnlbJaJJpyWsf0KTe/OOnvl8CBmvZc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511823; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=Y56mM8tDLLz9gVZgrAS/3jI6cTMGgRnH7oAOvoyj73Q=; b=V6ADxMviiH+EURngWmJEY5SvXwJY04VxLXsxez177q4leS6LyQPXcH0VO4vytAWv6cOcqqtmU7FOic47ujn7S2n+dD2kxJuM85AbCk85Oj61rpwS6LeVEiACL+ZH024ginys3svzJIgTsg+DpFQZNlAmDpJ21P3PUd9JOBxhLzo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48531+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511823088580.5835334696189; Mon, 7 Oct 2019 22:17:03 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ICHUYY1788612x3k6mFCWXM8; Mon, 07 Oct 2019 22:17:02 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:02 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297223" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:01 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH V1 03/17] KabylakeOpenBoardPkg/KabylakeRvp3: DSC cleanup Date: Mon, 7 Oct 2019 22:16:31 -0700 Message-Id: <20191008051645.22052-4-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: BOmibU89DhTH38JNAJ60HIA7x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511822; bh=/oLyX0Kaj/rjV+/2wQ5iwsLgreeZbB/BysQ5Lxvd0aY=; h=Cc:Date:From:Reply-To:Subject:To; b=b89DWnwbFHEcX6icabBbhHQdPV4SlpSKHQOFNYYgteQlvuHgyWn0wJK+fn6HtKCOKsB pNZF1/vrFWXBvWhqg/bzHESQFTT4ZFgxUY90ZOY/7tE8q5ZKsCVNsa2+apUk1Uldbm/SU lst9DVSe2uSpgY6uFFuNonxqx4szMrnv+3U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2242 This change refactors OpenBoardPkg.dsc and OpenBoardPkgPcd.dsc to consolidate redundant sections and better group file content to improve maintainability and readability. The same pattern made in this change for KabylakeRvp3 is being applied to all existing board packages in Platform/Intel to improve overall consistency. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 521= ++++++++++--------- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 547= ++++++++++---------- 2 files changed, 539 insertions(+), 529 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index a3378d3c5d..efc4c2dca8 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -1,5 +1,5 @@ ## @file -# Platform description. +# The main build description file for the KabylakeRvp3 board. # # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# @@ -7,11 +7,6 @@ # ## [Defines] - # - # Set platform specific package/folder name, same as passed from PREBUIL= D script. - # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package= build folder - # DEFINE only takes effect at R9 DSC and FDF. - # DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg @@ -20,7 +15,7 @@ DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE= )/$(BOARD) =20 # - # Platform On/Off features are defined here + # Include PCD configuration for this board. # !include OpenBoardPkgPcd.dsc =20 @@ -68,8 +63,6 @@ SUPPORTED_ARCHITECTURES =3D IA32|X64 BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D ALL - - FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf =20 FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 @@ -82,172 +75,205 @@ =20 ##########################################################################= ###### # -# SKU Identification section - list of all SKU IDs supported by this -# Platform. +# SKU Identification section - list of all SKU IDs supported by this board. # ##########################################################################= ###### [SkuIds] - 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. - 4|KabylakeRvp3 + 0x00|DEFAULT # 0|DEFAULT is reserved and always required. + 0x04|KabylakeRvp3 0x60|KabyLakeYLpddr3Rvp3 =20 ##########################################################################= ###### # -# Library Class section - list of all Library Classes needed by this Platf= orm. +# Includes section - other DSC file contents included for this board build. # ##########################################################################= ###### =20 +####################################### +# Library Includes +####################################### !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +####################################### +# Component Includes +####################################### +[Components.IA32] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +[Components.X64] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + +####################################### +# Build Option Includes +####################################### +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc +!include OpenBoardPkgBuildOption.dsc + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this board. +# +##########################################################################= ###### =20 [LibraryClasses.common] - - PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf - - PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf - PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf - PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf - I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf - GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf - - PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf - - FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf - PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf - + ####################################### + # Edk2 Packages + ####################################### FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf =20 - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf - -!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 - # - # Below library are used by FSP API mode - # - SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf -!else - # - # Below library are used by FSP Dispatch mode and non-FSP build (EDK2 bu= ild) - # - SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiSiliconPolicyUpdateLib.inf - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFspAml.inf -!endif - + ####################################### + # Silicon Initialization Package + ####################################### ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseCon= figBlockLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInit= Lib.inf =20 +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # FSP API mode + # + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf +!else + # + # FSP Dispatch mode and non-FSP build (EDK2 build) + # + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFspAml.inf +!endif + + ##################################### + # Platform Package + ##################################### BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf =20 -# Tbt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf - DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf -!endif + ####################################### + # Board Package + ####################################### EcLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseEcLib/BaseEcLib.inf + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf + PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf =20 -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc - -[LibraryClasses.IA32] - # - # PEI phase common - # - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf -!if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf -!endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf - BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf - -# Tbt + # Thunderbolt !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf - PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf + DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf +!endif + + ####################################### + # Board-specific + ####################################### + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # FSP API mode + # + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +!else + # + # FSP Dispatch mode and non-FSP build (EDK2 build) + # + SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiSiliconPolicyUpdateLib.inf !endif -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc =20 [LibraryClasses.IA32.SEC] + ####################################### + # Platform Package + ####################################### TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf =20 -[LibraryClasses.X64] - # - # DXE phase common - # - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf +[LibraryClasses.common.PEIM] + ####################################### + # Platform Package + ####################################### + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf !if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf !endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf + + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf +!endif + +[LibraryClasses.common.DXE_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInit= Lib/DxeSiliconPolicyInitLib.inf + + ####################################### + # Platform Package + ####################################### + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/DxeMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/DxeMultiBoardAcpiSupportLib.inf - BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf =20 - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInit= Lib/DxeSiliconPolicyInitLib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf +!endif + + ####################################### + # Board-specific + ####################################### SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateL= ib/DxeSiliconPolicyUpdateLib.inf =20 -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf =20 [LibraryClasses.X64.DXE_SMM_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf -!if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf -!endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf - MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf + + ####################################### + # Platform Package + ####################################### BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/SmmMultiBoardAcpiSupportLib.inf - -[LibraryClasses.X64.DXE_RUNTIME_DRIVER] - ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf +!endif =20 [Components.IA32] - -# -# Common -# -!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc - - # - # FSP wrapper SEC Core - # + ####################################### + # Edk2 Packages + ####################################### UefiCpuPkg/SecCore/SecCore.inf { - #PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf } =20 -# -# Silicon -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc - -# -# Platform -# - $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.i= nf -!else - NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf -!endif - } - !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 # # In FSP API mode the policy has to be installed before FSP Wrapper upda= ting UPD. @@ -257,16 +283,13 @@ SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf } - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { - # - # Hook a library constructor to update some policy fields when policy = installed. - # - NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyNoti= fyLib/PeiPreMemSiliconPolicyNotifyLib.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf } !else # - # In FSP Dispatch mode the policy will be installed after FSP-M dispatch= ed. (only PrePolicy silicon-init executed) + # In FSP Dispatch mode the policy will be installed after FSP-M dispatch= ed (only PrePolicy silicon-init executed). # Do not add policy dependency and let FspmWrapper report FSP-M FV to di= spatcher. # IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { @@ -274,89 +297,98 @@ SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf } # - # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP t= o install a default policy PPI. - # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch mode= can generate different policy structure - # for different FSP revisions, but they must maintain backward compatibi= lity. + # In FSP Dispatch mode the policy will be installed after FSP-S dispatch= ed (only PrePolicy silicon-init executed). + # Do not add policy dependency and let FspsWrapper report FSP-S FV to di= spatcher. # - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLib/PeiPreMemSiliconPolicyInitLib.inf + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf } !endif =20 + ####################################### + # Silicon Initialization Package + ####################################### + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf + + ####################################### + # Platform Package + ####################################### + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib= .inf + !else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf + !endif + } + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.= inf -!else - NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf -!endif + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLi= b.inf + !else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i= nf + !endif } =20 !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 - # - # In FSP API mode the policy has to be installed before FSP Wrapper upda= ting UPD. - # Add policy as dependency for FSP Wrapper - # - IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf + # + # Hook a library constructor to update some policy fields when policy = is installed. + # + NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiliconPolicyNoti= fyLib/PeiPreMemSiliconPolicyNotifyLib.inf } $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf !else - # - # In FSP Dispatch mode the policy will be installed after FSP-S dispatch= ed. (only PrePolicy silicon-init executed) - # Do not add policy dependency and let FspsWrapper report FSP-S FV to di= spatcher. - # - IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { - - SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf - } # # FSP Dispatch mode will consume DefaultPolicyInit PPI produced by FSP t= o install a default policy PPI. # Similar as UPD in FSP API mode, DefaultPolicyInit PPI in Dispatch mode= can generate different policy structure # for different FSP revisions, but they must maintain backward compatibi= lity. # + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { + + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLib/PeiPreMemSiliconPolicyInitLib.inf + } $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf { SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLib/PeiPostMemSiliconPolicyInitLib.inf } !endif =20 -# -# Security -# - !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf !endif =20 - IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf - IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf - -# Tbt + ####################################### + # Board Package + ####################################### + # Thunderbolt !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf !endif =20 [Components.X64] - -# -# Common -# -!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc - - UefiCpuPkg/CpuDxe/CpuDxe.inf + ####################################### + # Edk2 Packages + ####################################### + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + UefiCpuPkg/CpuDxe/CpuDxe.inf =20 +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 # - # Shell + # FSP API mode # + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf +!endif + ShellPkg/Application/Shell/Shell.inf { gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE @@ -376,92 +408,79 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf } =20 -# -# Silicon -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc - -# Tbt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf - $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf -!endif - -# -# Platform -# - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf -!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 - # - # Below module is used by FSP API mode - # - IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf -!endif - $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf - - $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf - $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf - -# -# OS Boot -# !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableL= ib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf -!endif - } - $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableL= ib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf -!endif - } - $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnabl= eLib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf -!endif - } - - $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf - UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 -!if $(TARGET) =3D=3D DEBUG - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf -!endif + !if $(TARGET) =3D=3D DEBUG + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialP= ort.inf + !endif } - -!endif - -# -# Security -# - $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf - -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf !endif =20 + ####################################### + # Silicon Initialization Package + ####################################### IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf - -# -# Other -# $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf =20 -!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc -!include OpenBoardPkgBuildOption.dsc + ####################################### + # Platform Package + ####################################### + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf + !endif + } + + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf + !endif + } + +!endif + + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf + !endif + } +!endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index edb4013cc0..15d05bea43 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -1,5 +1,5 @@ ## @file -# Platform description. +# PCD configuration build description file for the KabylakeRvp3 board. # # Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# @@ -9,12 +9,16 @@ =20 ##########################################################################= ###### # -# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# Pcd Section - list of all PCD Entries used by this board. # ##########################################################################= ###### -[PcdsFixedAtBuild] + +[PcdsFixedAtBuild.common] + ###################################### + # Key Boot Stage and FSP configuration + ###################################### # - # Please select BootStage here. + # Please select the Boot Stage here. # Stage 1 - enable debug (system deadloop after debug init) # Stage 2 - mem init (system deadloop after mem init) # Stage 3 - boot to shell only @@ -23,61 +27,87 @@ # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 =20 + # + # 0: FSP Wrapper is running in Dispatch mode. + # 1: FSP Wrapper is running in API mode. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 + + # + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 + + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # FSP API mode does not share stack with the boot loader, + # so FSP needs more temporary memory for FSP heap + stack size. + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 + # + # FSP API mode does not need to enlarge the boot loader stack size + # since the stacks are separate. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 +!else + # + # In FSP Dispatch mode boot loader stack size must be large + # enough for executing both boot loader and FSP. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 +!endif + +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1) + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid= .PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength +!else + # + # FSP Dispatch mode requires more platform memory as boot loader and FSP= sharing the same + # platform memory. + # + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 +!endif + [PcdsFeatureFlag.common] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE +!if $(TARGET) =3D=3D RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE !endif - - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - - - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - - - -# -# TRUE is ENABLE. FALSE is DISABLE. -# - -# -# BIOS build switches configuration -# + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + ###################################### + # Silicon Configuration + ###################################### + # Build switches gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE =20 -# CPU - gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build @tod= o Convert TXT ASM to NASM + # CPU gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE =20 -# SA + # SA gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE @@ -88,207 +118,133 @@ gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE =20 -# ME + # ME gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE =20 + # Others gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE - -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # - - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - - - - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif - - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif - + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE =20 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE -!if $(TARGET) =3D=3D RELEASE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + +!if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE !else - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE !endif - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE =20 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE - - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + ###################################### + # Board Configuration + ###################################### + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE =20 [PcdsFixedAtBuild.common] - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE - # - # 0: FSP Wrapper is running in Dispatch mode. - # 1: FSP Wrapper is running in API mode. - # - gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 - + ###################################### + # Edk2 Configuration + ###################################### +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS) + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 !endif - + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 + gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE !if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 !endif - - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 - - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - -!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 - # - # FSP API mode is backward compatible with earlier FSP which - # does not share stack with boot loader, so FSP needs more - # temporary memory for FSP heap + stack size. - # - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 - - # - # In FSP API mode, FSP and boot loader runnig on different stack - # so no need to enlarge boot loader stack size. - # - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 -!else - # - # FSP Dispatch mode will share the same stack and heap with boot loader, - # no separate temporary ram required by FSP. - # - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0 - - # - # In FSP Dispatch mode boot loader stack size must be big enough for exe= cuting - # both boot loader and FSP. - # - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 -!endif - - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 -!if $(TARGET) =3D=3D RELEASE - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 -!else - gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!if $(TARGET) =3D=3D DEBUG gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif - gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS) - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 - - - - -gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE - -# -# 8MB Default -# -gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 - -# -# 16MB TSEG in Debug build only. -# -!if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 -!endif - - =20 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 =20 - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B - !endif - - - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 - !endif - - # - # FSP Base address PCD will be updated in FDF basing on flash map. - # - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 - - ## Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. + # Specifies timeout value in microseconds for the BSP to detect all APs = for the first time. gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 !if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1) # # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBui= ld # (They will be DynamicEx in FSP Dispatch mode) # ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss + # @Prompt Configure max supported number of Logical Processors gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 =20 ## Specifies the size of the microcode Region. @@ -302,17 +258,24 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # 3: Place AP in the Run-Loop state. # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 - - gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid= .PcdPciExpressBaseAddress - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength -!else - # - # FSP Dispatch mode requires more platform memory as boot loader and FSP= sharing the same - # platform memory. - # - gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 !endif =20 + ###################################### + # Silicon Configuration + ###################################### + + # Refer to HstiFeatureBit.h for bit definitions + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags # @@ -324,11 +287,18 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 =20 - # - # See HstiFeatureBit.h for the definition - # - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 +!if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b +!if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 +!endif =20 !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} @@ -355,90 +325,111 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 !endif =20 [PcdsFixedAtBuild.IA32] + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 + [PcdsFixedAtBuild.X64] + ###################################### + # Edk2 Configuration + ###################################### + # Default platform supported RFC 4646 languages: (American) English gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" =20 - [PcdsPatchableInModule.common] + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 =20 + ###################################### + # Silicon Configuration + ###################################### !if $(TARGET) =3D=3D DEBUG gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 !endif =20 -[PcdsDynamicHii.X64.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" - gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout" -!endif - [PcdsDynamicDefault] - # - # FSP Base address PCD will be updated in FDF basing on flash map. - # - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 - # Platform will pre-allocate UPD buffer and pass it to FspWrapper - # Those dummy address will be patched before FspWrapper executing - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF - -[PcdsDynamicDefault.common.DEFAULT] - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + # # Set video to native resolution as Windows 8 WHCK requirement. # gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 =20 - gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 - -[PcdsDynamicDefault.common.DEFAULT] - # gEfiTpmDeviceInstanceTpm20DtpmGuid - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0 gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} =20 -# Tbt -gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn | 0x1 -gBoardModuleTokenSpaceGuid.PcdDTbtControllerType | 0x1 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber | 0x1 -gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType | 0x2 -gBoardModuleTokenSpaceGuid.PcdExpander | 0x0 -gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1 -gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13 -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011 -gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature | 0 -gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting | 0 -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode | 0x1 -#gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter | 0x0 -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0 -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1 -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1 -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1 -gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0 -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0 -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1 -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support | 0x0 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay | 0x0 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay | 5000 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd | 56 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd | 100 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 -gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 + # Platform will pre-allocate UPD buffer and pass it to FspWrapper + # Those dummy address will be patched before FspWrapper executing + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF + + ###################################### + # Board Configuration + ###################################### + + # Thunderbolt Configuration + gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0 + gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0 + gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 + gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtControllerType|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 + gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType|0x2 + gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd|100 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support|0x0 + gBoardModuleTokenSpaceGuid.PcdExpander|0x0 + gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001 + gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay|5000 + +[PcdsDynamicHii.X64.DEFAULT] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout" +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" +!endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48531): https://edk2.groups.io/g/devel/message/48531 Mute This Topic: https://groups.io/mt/34439438/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48532+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48532+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511830; cv=none; d=zoho.com; s=zohoarc; b=SolZvpyMhx/uOs0rsYGr2s3R7U9txPDJVcDGk4Fy9p+tRhSPJeDPNPqG1E1kvB/19Z48LrMW4CAuqOLW09LKfEOjW0qgEF30ujYXiLhPgeGhmmol0ndP3w1qdy094v4HvCpaZxDOsJLTDxjfZoap1407x91CDrIOslfV4tZ/fjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511830; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=0AjyPlijWtVRRdm8GPL3jyCQYvCSVPOsFQIvfG4uGrI=; b=Qs5hrE05+oOlHNclpVWxUF8u7y/bC8B9dvqfwKVh5xvzsBelvUxfq+YJQ030dYGfdnguTYg0huqhihrgxNTECwhZhYvNoXN7xhwUY/zHu9vbV0am5TLd5Tw9yavr/Zh8NFBpZQdDQxDLKUpLW1lFTTJV6MkAWJJrWHhWhhg4IJY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48532+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511830477723.5271009115525; Mon, 7 Oct 2019 22:17:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pHNZYY1788612x7xBOMvvLfa; Mon, 07 Oct 2019 22:17:10 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:09 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297231" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:07 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Jeremy Soller Subject: [edk2-devel] [edk2-platforms][PATCH V1 04/17] KabylakeOpenBoardPkg/GalagoPro3: Relocate PCD DSC include Date: Mon, 7 Oct 2019 22:16:32 -0700 Message-Id: <20191008051645.22052-5-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: nD8wbSjU97AA37zAOLanyFkYx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511830; bh=ht6+I3twdqARRR1tydH1v2bDVgfF7mJJI8eHdTqzPcw=; h=Cc:Date:From:Reply-To:Subject:To; b=gJJHt9uTlzLXqnT8Q6E0iU94z4wvkEn0H0xKydBJZupA153ckW8CrXumTiOs5+foylx pss20Kfpycx/6yVZ1BpXeVYN6tuWDHratVH0wa+I1cco2XOKdgeMilFzY7tNrnTZLsp+p Iy2YRGWONbh+/We5k+UE83eZ/m7F4J7RDgI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This change moves the include of OpenBoardPkgPcd.dsc to the top of OpenBoardPkg.dsc to improve visibility and align the include location with other board DSC files. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Jeremy Soller Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index f3dd2b0c91..90ee5dfc53 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -24,6 +24,7 @@ # Platform On/Off features are defined here # !include OpenBoardPkgConfig.dsc + !include OpenBoardPkgPcd.dsc =20 ##########################################################################= ###### # @@ -174,8 +175,6 @@ [LibraryClasses.X64.DXE_RUNTIME_DRIVER] ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf =20 -!include OpenBoardPkgPcd.dsc - [Components.IA32] =20 # --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48532): https://edk2.groups.io/g/devel/message/48532 Mute This Topic: https://groups.io/mt/34439439/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48533+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48533+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511830; cv=none; d=zoho.com; s=zohoarc; b=h8kur1hwQOjlN8y1f+m3bKqghwuEc+YsQef8MEJ6YC2hc6W1PJdAcGBIDDu0qRWtGXJ2muJRH5PKAe1YyTzV5bFRGySJoVSAdc6l/xjNH/W+JAow1auvnd0xQ213V15t3qlLxmpolioIkonX6roEZfFu0bLz4hmYqUqaEYXCZZ4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511830; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=Xcds/u26hKXVdTmXR7x/OhN+M+WSVHTLYWNSN+P4Hn4=; b=g1ANAVoipaD9ZYc+lIqwxxpA0+RRbyNN9VsZxZVODPICh+gS3ReQBhG3OkdLnyOBnk6WkCvJbh+iUPNkdnqsqRiVXholGPepgyiH5rM0qErT8wUu4YnGVgp8k03Kva8LBEbjS79nDeDFyDOvrfBfDgpmv35mc6tFsQAimqgvNno= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48533+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511830922531.2749433976243; Mon, 7 Oct 2019 22:17:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XuWUYY1788612xa9l6gtPpKp; Mon, 07 Oct 2019 22:17:10 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:09 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297249" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:09 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Jeremy Soller Subject: [edk2-devel] [edk2-platforms][PATCH V1 05/17] KabylakeOpenBoardPkg/GalagoPro3: Remove OpenBoardPkgConfig.dsc Date: Mon, 7 Oct 2019 22:16:33 -0700 Message-Id: <20191008051645.22052-6-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: jCBLNCTfHurnorwO4AWMoLckx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511830; bh=5jWpdpujBTx4NhbS7zuvQOP6CLtSCyjfYDRWHlGyYM0=; h=Cc:Date:From:Reply-To:Subject:To; b=dzxR0qgRSxDBGWg4bbd38ZC4tQgtpaPJ3BgreDwxIsEdiG4N4mFcWQLXYcj/LK1hn5e wpYJwJqKxPhUHaR6Ih1JfU+MHpY4fW0gRz7h/fkLzbNGEXAYdudjBwaLN+kF/9jzd+nbR IEvnB9ijvq5bInueUPwgZTHU6UfwnU+j/Wc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2242 The location for PCD configuration is currently inconsistent in KabylakeOpenBoardPkg. A large set of FeaturePCD definitions are in OpenBoardPkgConfig.dsc while other PCD definitions (including FeaturePCD) are located in OpenBoardPkgPcd.dsc. This change consolidates PCD configuration for the GalagoPro3 board to OpenBoardPkgPcd.dsc and removes OpenBoardPkgConfig.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Jeremy Soller Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | = 1 - Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgConfig.dsc | 13= 2 -------------------- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc | 12= 2 ++++++++++++++++++ 3 files changed, 122 insertions(+), 133 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index 90ee5dfc53..75f774d26b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -23,7 +23,6 @@ # # Platform On/Off features are defined here # - !include OpenBoardPkgConfig.dsc !include OpenBoardPkgPcd.dsc =20 ##########################################################################= ###### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgCon= fig.dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgConfig= .dsc deleted file mode 100644 index 3de3f8942c..0000000000 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgConfig.dsc +++ /dev/null @@ -1,132 +0,0 @@ -## @file -# System 76 GalagoPro3 board configuration. -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -[PcdsFixedAtBuild] - # - # Please select BootStage here. - # Stage 1 - enable debug (system deadloop after debug init) - # Stage 2 - mem init (system deadloop after mem init) - # Stage 3 - boot to shell only - # Stage 4 - boot to OS - # Stage 5 - boot to OS with security boot enabled - # - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 - -[PcdsFeatureFlag] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE -!endif - - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - -# -# TRUE is ENABLE. FALSE is DISABLE. -# - -# -# BIOS build switches configuration -# - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - -# CPU - gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build @tod= o Convert TXT ASM to NASM - gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE - -# SA - gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE - gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE - gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE - -# ME - gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE - gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE - - gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE - gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE - gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE - gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE - gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE - gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE - -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # - - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif - - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif - - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE - diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd= .dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc index 2dfdd3b30e..d564f0a9ee 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc @@ -12,7 +12,129 @@ # Pcd Section - list of all EDK II PCD Entries defined by this Platform # ##########################################################################= ###### +[PcdsFixedAtBuild] + # + # Please select BootStage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + [PcdsFeatureFlag.common] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + # + # More fine granularity control below: + # + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + +# +# TRUE is ENABLE. FALSE is DISABLE. +# + +# +# BIOS build switches configuration +# + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + +# CPU + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build @tod= o Convert TXT ASM to NASM + gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE + +# SA + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSkycamEnable|TRUE + gSiPkgTokenSpaceGuid.PcdGmmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE + +# ME + gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE + + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE + gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + +# +# Override some PCDs for specific build requirements. +# + # + # Disable USB debug message when Source Level Debug is enabled + # because they cannot be enabled at the same time. + # + + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE + + !if $(TARGET) =3D=3D DEBUG + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !else + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !endif + + !if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE !if $(TARGET) =3D=3D RELEASE --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48533): https://edk2.groups.io/g/devel/message/48533 Mute This Topic: https://groups.io/mt/34439440/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48534+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48534+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511832; cv=none; d=zoho.com; s=zohoarc; b=kZc79kSFjba8N8necyFc65hsOSI2bxV8apY3ddaFwCpfQFbRjQIIRnSNCMxsqcWH1r7O3FStkvfmcBEhNmecb2VxnSa3llC8Q79e+NRlS1dq3S3xE9oUFsFZX6G78V5soBbKlyBYMd6oF1dWxZt+S5fdnybmXLMA7XShv/uUn10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511832; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=+jJV4DhXq/72qDfNuGsUmCQ4LyQqDr5FthIblaEIRl4=; b=fSAzEOTRgMeSykxT3E/6SBni8ou4C4JvPI7EzmlpCWgMMpVzXsuo8cVf+f4Sq2lJc03/tCy5LHRdxx5KLoeeglusu/wXer+hMIpJjLXdMAQjpCujEQoJjcyW7BTuxYGiy2ERD6Ze4dCiWqGFTf03Qhnu0h3QnBNgXfFV3d3TyJU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48534+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511832721887.2004716880092; Mon, 7 Oct 2019 22:17:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id yl5CYY1788612xSTeynt8t4v; Mon, 07 Oct 2019 22:17:12 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:11 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:11 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297255" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:10 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Jeremy Soller Subject: [edk2-devel] [edk2-platforms][PATCH V1 06/17] KabylakeOpenBoardPkg/GalagoPro3: DSC cleanup Date: Mon, 7 Oct 2019 22:16:34 -0700 Message-Id: <20191008051645.22052-7-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: UUppiZL8qEinsLUFRfrXJEAqx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511832; bh=YPCZx/awXeMR+uZotFH6dPi2f+FqzjIflFu5NwQgxzU=; h=Cc:Date:From:Reply-To:Subject:To; b=Uvz/CLOQn8J8lAe1TZLFEpS4FkEu4T1weZCcjgOmjmEW0rJAwNi73gqwCcc3aReSp0u h+xxSDlTcuk/SZQEKLaxPPRY1icKpo3L00yzrsM8D05Pf3JODpu7kPwan+ovxQldv9OlZ nwy5z+s4NOk6BXnh+sVGsLR5wxvZzxlxEZw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2242 This change refactors OpenBoardPkg.dsc and OpenBoardPkgPcd.dsc to consolidate redundant sections and better group file content to improve maintainability and readability. The same pattern made in this change for GalagoPro3 is being applied to all existing board packages in Platform/Intel to improve overall consistency. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Jeremy Soller Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc | 478 += ++++++++++--------- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc | 476 += +++++++++--------- 2 files changed, 506 insertions(+), 448 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index 75f774d26b..5f77c8db0a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -1,5 +1,5 @@ ## @file -# System 76 GalagoPro3 board description file. +# The main build description file for the GalagoPro3 board. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
# @@ -7,11 +7,6 @@ # ## [Defines] - # - # Set platform specific package/folder name, same as passed from PREBUIL= D script. - # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package= build folder - # DEFINE only takes effect at R9 DSC and FDF. - # DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg @@ -21,7 +16,7 @@ DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE= )/$(BOARD) =20 # - # Platform On/Off features are defined here + # Include PCD configuration for this board. # !include OpenBoardPkgPcd.dsc =20 @@ -53,8 +48,7 @@ =20 ##########################################################################= ###### # -# SKU Identification section - list of all SKU IDs supported by this -# Platform. +# SKU Identification section - list of all SKU IDs supported by this board. # ##########################################################################= ###### [SkuIds] @@ -63,220 +57,261 @@ =20 ##########################################################################= ###### # -# Library Class section - list of all Library Classes needed by this Platf= orm. +# Includes section - other DSC file contents included for this board build. # ##########################################################################= ###### =20 +####################################### +# Library Includes +####################################### !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +####################################### +# Component Includes +####################################### +[Components.IA32] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +[Components.X64] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + +####################################### +# Build Option Includes +####################################### +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc +!include OpenBoardPkgBuildOption.dsc + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this board. +# +##########################################################################= ###### =20 [LibraryClasses.common] - - PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf - - PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf - PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf - PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf - I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf - GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf - - PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf - - FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf - PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf - + ####################################### + # Edk2 Packages + ####################################### FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf =20 - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf - SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf - + ####################################### + # Silicon Initialization Package + ####################################### ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseCon= figBlockLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInit= Lib.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf =20 + ##################################### + # Platform Package + ##################################### BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf =20 -# Tbt + ####################################### + # Board Package + ####################################### + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf + PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf + + # Thunderbolt !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf !endif -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc + + ####################################### + # Board-specific + ####################################### + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf + SiliconPolicyUpdateLib|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyUpd= ateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf =20 [LibraryClasses.IA32.SEC] - SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf + ####################################### + # Edk2 Packages + ####################################### DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf + + ####################################### + # Platform Package + ####################################### SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf =20 -[LibraryClasses.IA32] - # - # PEI phase common - # - SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf +[LibraryClasses.common.PEIM] + ####################################### + # Edk2 Packages + ####################################### DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf -!if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf -!endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf + + ####################################### + # Platform Package + ####################################### BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf +!endif =20 -# Tbt + ####################################### + # Board Package + ####################################### + # Thunderbolt !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf !endif -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc =20 -[LibraryClasses.X64] - # - # DXE phase common - # - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf -!if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf -!endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf +[LibraryClasses.common.DXE_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInit= Lib/DxeSiliconPolicyInitLib.inf + + ####################################### + # Platform Package + ####################################### + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/DxeMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/DxeMultiBoardAcpiSupportLib.inf - BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf =20 - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/DxeSiliconPolicyInit= Lib/DxeSiliconPolicyInitLib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf +!endif + + ####################################### + # Board-specific + ####################################### SiliconPolicyUpdateLib|$(PROJECT)/Policy/Library/DxeSiliconPolicyUpdateL= ib/DxeSiliconPolicyUpdateLib.inf =20 -# -# Silicon Init Package -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf =20 [LibraryClasses.X64.DXE_SMM_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf -!if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf -!endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf - MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf + + ####################################### + # Platform Package + ####################################### BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/SmmMultiBoardAcpiSupportLib.inf - -[LibraryClasses.X64.DXE_RUNTIME_DRIVER] - ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf +!endif =20 [Components.IA32] - -# -# Common -# -!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc - - # - # Core - # - MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { - - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf - } - - # - # FSP wrapper SEC Core - # + ####################################### + # Edk2 Packages + ####################################### UefiCpuPkg/SecCore/SecCore.inf { - #PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf } =20 -# -# Silicon -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc - -# -# Platform -# - $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf - $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPreMem.inf { + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf { -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.i= nf -!else - NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf -!endif + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf } + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf { SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf } - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf{ - - # # - # Hook a library constructor to update some policy fields when policy = installed. - # - NULL|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMem= SiliconPolicyNotifyLib.inf - } - - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLib.= inf -!else - NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf -!endif - } - IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf { SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPostMemSiliconPolicyInitLibDependency.inf } - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf - -# -# Security -# - -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf -!endif =20 + ####################################### + # Silicon Initialization Package + ####################################### IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf =20 -# Tbt + ####################################### + # Platform Package + ####################################### + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf + $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPreMem.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib= .inf + !else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf + !endif + } + + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLi= b.inf + !else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i= nf + !endif + } + + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { + + # + # Hook a library constructor to update some policy fields when policy = is installed. + # + NULL|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMem= SiliconPolicyNotifyLib.inf + } + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif + + ####################################### + # Board Package + ####################################### + # Thunderbolt !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf !endif =20 [Components.X64] - -# -# Common -# -!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc - - UefiCpuPkg/CpuDxe/CpuDxe.inf + ####################################### + # Edk2 Packages + ####################################### + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + UefiCpuPkg/CpuDxe/CpuDxe.inf =20 - # - # Shell - # ShellPkg/Application/Shell/Shell.inf { gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE @@ -296,88 +331,79 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf } =20 -# -# Silicon -# -!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc - -# Tbt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf - $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf -!endif - -# -# Platform -# - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf - IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf - - $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf - - $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf - $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf - -# -# OS Boot -# !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableL= ib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf -!endif - } - $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTableL= ib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf -!endif - } - $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { - -!if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEnabl= eLib.inf -!else - NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf -!endif - } - - $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf - UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 -!if $(TARGET) =3D=3D DEBUG - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf -!endif + !if $(TARGET) =3D=3D DEBUG + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialP= ort.inf + !endif } - -!endif - -# -# Security -# - $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf - -!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf !endif =20 + ####################################### + # Silicon Initialization Package + ####################################### IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf - -# -# Other -# $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf =20 -!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc -!include OpenBoardPkgBuildOption.dsc + ####################################### + # Platform Package + ####################################### + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf + !endif + } + + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf + !endif + } + +!endif + + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf + !endif + } +!endif diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd= .dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc index d564f0a9ee..d13761e077 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc @@ -1,5 +1,5 @@ ## @file -# System 76 GalagoPro3 board PCD configuration. +# PCD configuration build description file for the GalagoPro3 board. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
# @@ -9,12 +9,16 @@ =20 ##########################################################################= ###### # -# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# Pcd Section - list of all PCD Entries used by this board. # ##########################################################################= ###### -[PcdsFixedAtBuild] + +[PcdsFixedAtBuild.common] + ###################################### + # Key Boot Stage and FSP configuration + ###################################### # - # Please select BootStage here. + # Please select the Boot Stage here. # Stage 1 - enable debug (system deadloop after debug init) # Stage 2 - mem init (system deadloop after mem init) # Stage 3 - boot to shell only @@ -23,57 +27,69 @@ # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 =20 + # + # 0: FSP Wrapper is running in Dispatch mode. + # 1: FSP Wrapper is running in API mode. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 + + # + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 + + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 + + # + # FSP API mode does not share stack with the boot loader, + # so FSP needs more temporary memory for FSP heap + stack size. + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 + + # + # FSP API mode does not need to enlarge the boot loader stack size + # since the stacks are separate. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 + [PcdsFeatureFlag.common] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE +!if $(TARGET) =3D=3D RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE !endif - - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - -# -# TRUE is ENABLE. FALSE is DISABLE. -# - -# -# BIOS build switches configuration -# + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + ###################################### + # Silicon Configuration + ###################################### + # Build switches gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE =20 -# CPU - gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|TRUE #Set to FALSE for GCC Build @tod= o Convert TXT ASM to NASM + # CPU gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE =20 -# SA + # SA gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE @@ -84,171 +100,139 @@ gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE =20 -# ME + # ME gSiPkgTokenSpaceGuid.PcdAmtEnable|TRUE gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE =20 + # Others gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE gSiPkgTokenSpaceGuid.PcdBootGuardEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE gSiPkgTokenSpaceGuid.PcdEvLoaderEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE gSiPkgTokenSpaceGuid.PcdSerialGpioEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable|TRUE gSiPkgTokenSpaceGuid.PcdSsaFlagEnable|FALSE - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE =20 -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE =20 - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTxtEnable|FALSE +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif =20 - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif =20 - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif =20 - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif =20 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE -!if $(TARGET) =3D=3D RELEASE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + +!if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE !else - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE !endif - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE =20 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE - - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + ###################################### + # Board Configuration + ###################################### + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE =20 [PcdsFixedAtBuild.common] - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 -!endif - - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 - - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 - - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 - - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + ###################################### + # Edk2 Configuration + ###################################### !if $(TARGET) =3D=3D RELEASE gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 !else gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif - gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS) - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 - + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS) + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE +!if $(TARGET) =3D=3D DEBUG + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE +!endif =20 - # - # 8MB Default - # - gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 - - # - # 16MB TSEG in Debug build only. - # - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 - !endif - + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x40 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 =20 - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B - !endif - - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 - !endif + # Specifies timeout value in microseconds for the BSP to detect all APs = for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 =20 # - # FSP Base address PCD will be updated in FDF basing on flash map. + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBui= ld + # (They will be DynamicEx in FSP Dispatch mode) # - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss + # @Prompt Configure max supported number of Logical Processors gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 =20 ## Specifies the size of the microcode Region. # @Prompt Microcode Region size. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 =20 - ## Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - ## Specifies the AP wait loop state during POST phase. # The value is defined as below. # 1: Place AP in the Hlt-Loop state. @@ -257,6 +241,25 @@ # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 =20 + ###################################### + # Silicon Configuration + ###################################### + + # Refer to HstiFeatureBit.h for bit definitions + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 + gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 + + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid= .PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags # @@ -268,11 +271,18 @@ # gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 =20 - # - # See HstiFeatureBit.h for the definition - # - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature1|0xF2 - gSiPkgTokenSpaceGuid.PcdHstiIhvFeature2|0x07 +!if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b +!if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 +!endif =20 !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} @@ -299,89 +309,111 @@ !endif =20 [PcdsFixedAtBuild.IA32] + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 + [PcdsFixedAtBuild.X64] + ###################################### + # Edk2 Configuration + ###################################### + # Default platform supported RFC 4646 languages: (American) English gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" =20 [PcdsPatchableInModule.common] + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 - gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 =20 + ###################################### + # Silicon Configuration + ###################################### !if $(TARGET) =3D=3D DEBUG gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 !endif =20 -[PcdsDynamicHii.X64.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" - gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout" -!endif - [PcdsDynamicDefault] - # - # FSP Base address PCD will be updated in FDF basing on flash map. - # - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 - # Platform will pre-allocate UPD buffer and pass it to FspWrapper - # Those dummy address will be patched before FspWrapper executing - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF - -[PcdsDynamicDefault.common.DEFAULT] - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + # # Set video to native resolution as Windows 8 WHCK requirement. # gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 =20 - gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 - -[PcdsDynamicDefault.common.DEFAULT] - # gEfiTpmDeviceInstanceTpm20DtpmGuid - gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} gEfiSecurityPkgTokenSpaceGuid.PcdTcg2HashAlgorithmBitmap|0 gEfiSecurityPkgTokenSpaceGuid.PcdTpm2HashMask|0x0000001F gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|1 + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28= , 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17} =20 - # Tbt - gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtControllerType | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType | 0x2 - gBoardModuleTokenSpaceGuid.PcdExpander | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13 - gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011 - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature | 0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting | 0 - gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode | 0x1 - #gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support | 0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay | 0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay | 5000 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd | 56 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd | 100 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 - gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 + # Platform will pre-allocate UPD buffer and pass it to FspWrapper + # Those dummy address will be patched before FspWrapper executing + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0xFFFFFFFF + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0xFFFFFFFF + + ###################################### + # Board Configuration + ###################################### + + # Thunderbolt Configuration + gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0 + gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0 + gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 + gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtControllerType|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 + gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType|0x2 + gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd|100 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support|0x0 + gBoardModuleTokenSpaceGuid.PcdExpander|0x0 + gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001 + gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay|5000 + +[PcdsDynamicHii.X64.DEFAULT] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout" +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" +!endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48534): https://edk2.groups.io/g/devel/message/48534 Mute This Topic: https://groups.io/mt/34439441/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48535+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48535+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511834; cv=none; d=zoho.com; s=zohoarc; b=Isf+i06nhRXj+LiVuiIpUGPx0wjZDVj0lcNqmA4xGhO4UF3yhhEWtmzTKSX4Dbq09kCEKxWEAVYI/Ty68Pmx5byKLOnoRPSp9mHLLzgsIQUQf5t+D5MTD812IFtmbxVUYIUMapRGibtU8OSPrjgf8x61gv5NirdU0r4YwNyN8VE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511834; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=zpSWLO97lVBfWv6kV/tOz0Is1luBCGqm19zJa1UWZdY=; b=WrQLtH0Xtjhy9SEySQaNa4eWgF7+lNtTLoIMc7Zi7ibi/qKszGGWK4UcFd/wH4dk4ouDxSE9Gstbhp40xDXeoEJmukBHSIwpeWSTRZ5bdFNtJVZmo8bOFNqcRqLlm2FfrFsyvghlENaDJxDFYtW0o0i/iXFNqCbjil696F5LVEo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48535+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511834572127.03138144407194; Mon, 7 Oct 2019 22:17:14 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id oFITYY1788612xYvKLDDGI7x; Mon, 07 Oct 2019 22:17:13 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:13 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297272" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:12 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Jeremy Soller Subject: [edk2-devel] [edk2-platforms][PATCH V1 07/17] KabylakeOpenBoardPkg: Assign unique token namespace Date: Mon, 7 Oct 2019 22:16:35 -0700 Message-Id: <20191008051645.22052-8-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: UUTZPyq3PDBsCpVMOuaDNmIlx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511833; bh=PkP0apIC/UUlli6zmw5npcx1RdoG2OJZblP8PrZdS/Q=; h=Cc:Date:From:Reply-To:Subject:To; b=gjE5dpblt0g5T+su0jqGw+7SpiUiAjNtwCjpR2DieBX0j230QqIt5uzqfh1JMAvyRYh m5klk36vq8AMzQs/ryuaRPTurDQhPVeh504E/0yHu0LiWMMC5Y2kGSRgbaIQ/oAsyG9QD xxHVfCrhc3yJy/Qj2b0CIAPOBSUxFL6uT+Q= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2247 PCDs declared in the KabylakeOpenBoardPkg currently use the GUID gBoardModuleTokenSpaceGuid. The same name is used in other board packages and a package has been added called BoardModulePkg so this name is now misleading. This change assigns a unique GUID value and a name specific to the package to provide differentiation from PCDs in other board packages. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Jeremy Soller Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec = | 408 ++++++++++---= ------- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc = | 18 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc = | 60 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc = | 18 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc = | 60 +-- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapInclude= .fdf | 4 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf = | 8 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf = | 4 +- Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf = | 16 +- Platform/Intel/KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf = | 4 +- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLib/D= xeTbtPolicyLib.inf | 40 +- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCommo= nLib/TbtCommonLib.inf | 40 +- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLib/P= eiTbtPolicyLib.inf | 18 +- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf = | 4 +- Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNot= ifyLib/PeiPreMemSiliconPolicyNotifyLib.inf | 8 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSilic= onPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf | 8 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSilic= onPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 70 ++-- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHookLib= /BasePlatformHookLib.inf | 18 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeBoa= rdAcpiTableLib.inf | 4 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/DxeMul= tiBoardAcpiSupportLib.inf | 10 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmBoa= rdAcpiEnableLib.inf | 2 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/SmmMul= tiBoardAcpiSupportLib.inf | 2 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoa= rdInitPostMemLib.inf | 16 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiBoa= rdInitPreMemLib.inf | 134 +++---- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMul= tiBoardInitPostMemLib.inf | 16 +- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/PeiMul= tiBoardInitPreMemLib.inf | 132 +++---- Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPo= licyUpdateLib/DxeSiliconPolicyUpdateLib.inf | 4 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSil= iconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 74 ++-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatformHookL= ib/BasePlatformHookLib.inf | 18 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeB= oardAcpiTableLib.inf | 12 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/DxeM= ultiBoardAcpiSupportLib.inf | 14 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmB= oardAcpiEnableLib.inf | 6 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib/SmmM= ultiBoardAcpiSupportLib.inf | 6 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiB= oardInitPostMemLib.inf | 18 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiB= oardInitPreMemLib.inf | 134 +++---- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiM= ultiBoardInitPostMemLib.inf | 18 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib/PeiM= ultiBoardInitPreMemLib.inf | 136 +++---- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf | 6 +- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSilicon= PolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf | 54 +-- Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/PeiSe= rialPortLibSpiFlash.inf | 4 +- 40 files changed, 813 insertions(+), 813 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec b/Platfor= m/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec index bdaf728af1..9680e63bad 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec +++ b/Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec @@ -26,7 +26,7 @@ Features/Tbt/Include =20 [Guids] =20 -gBoardModuleTokenSpaceGuid =3D {0x72d1fff7, 0xa42a, 0x4219, {0= xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} +gKabylakeOpenBoardPkgTokenSpaceGuid =3D {0x7cdc8563, 0xe40d, 0x446b, {0= x9f, 0x0d, 0xf3, 0x67, 0xfb, 0x01, 0xae, 0xc9}} =20 gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0= x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} =20 @@ -51,260 +51,260 @@ gPeiTbtPolicyBoardInitDonePpiGuid =3D {0x970f9c6= 0, 0x8547, 0x49d7, { 0xa4, 0x =20 [PcdsFixedAtBuild] =20 -gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004 -gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10= 001004 +gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0= x10001005 =20 -gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018 -gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000= 018 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x900000= 1F =20 -gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000= 001C -gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT= 16|0x9000001C +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000= 001D =20 -gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000= 021 -gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x900000= 22 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT1= 6|0x90000021 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16= |0x90000022 =20 ## Tbt SW_SMI_DTBT_ENUMERATEgSetupVariableGuid -gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UINT8|0x000000110 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate|0xF7|UINT8|0x000= 000110 =20 -gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x9= 0000015 =20 -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|0x00000000|UINT32|0x= 90000030 -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize|0x00000000|UINT32|0x= 90000031 -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|0x00000000|UINT32|= 0x90000032 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageBase|0x00000000|= UINT32|0x90000030 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize|0x00000000|= UINT32|0x90000031 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset|0x0000000= 0|UINT32|0x90000032 =20 [PcdsDynamic] =20 # Board GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000114 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000= 041 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x0000= 0043 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000= 000113 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0= x000000114 =20 # Board Expander GPIO Table -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x000000= 44 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00= 000045 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000= 046 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x0= 0000047 =20 # TouchPanel & SDHC CD GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0= x00000048 =20 # PCH-LP HSIO PTSS Table -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x000000= 4C -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x000000= 4D -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x0000= 0050 -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x0000= 0051 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0= 000004A +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0= 000004B +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16= |0x0000004C +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16= |0x0000004D +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0= x0000004E +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0= x0000004F +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT= 16|0x00000050 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT= 16|0x00000051 =20 # PCH-H HSIO PTSS Table -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x00000054 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x00000055 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000= 058 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000= 059 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00= 000052 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00= 000053 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|= 0x00000054 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|= 0x00000055 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x= 00000056 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x= 00000057 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT1= 6|0x00000058 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT1= 6|0x00000059 =20 # HDA Verb Table -gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A -gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B -gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F -gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000= 005D +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000= 005E +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000= 005F +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0= x00000060 =20 # SA Misc Configuration -gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 -gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067 -gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0= x00000067 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101 =20 # DRAM Configuration -gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068 -gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069 -gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A -gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B -gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C -gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D -gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x= 0000006E -gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006F -gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070 -gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x000000= 6C +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x00= 00006D +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|B= OOLEAN|0x0000006E +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|= 0x0000006F +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071 =20 # PEG RESET GPIO -gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072 -gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073 -gBoardModuleTokenSpaceGuid.PcdPegResetGpioPad|0|UINT32|0x00000074 -gBoardModuleTokenSpaceGuid.PcdPegResetGpioActive|FALSE|BOOLEAN|0x00000075 -gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079 -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007F +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0= x00000072 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0= x00000073 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPegResetGpioPad|0|UINT32|0x00000074 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPegResetGpioActive|FALSE|BOOLEAN|0x= 00000075 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x00= 00007A +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x00000= 07B +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x= 0000007C +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x= 0000007D +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x000= 0007E +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|= 0x0000007F =20 # SPD Address Table -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099 -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000= 099 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x00000= 09A +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x00000= 09B +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x00000= 09C =20 # CA Vref Configuration -gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D =20 # Root Port Clock Info -gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo|0|UINT64|0x0000009E -gBoardModuleTokenSpaceGuid.PcdRootPort1ClkInfo|0|UINT64|0x0000009F -gBoardModuleTokenSpaceGuid.PcdRootPort2ClkInfo|0|UINT64|0x000000A0 -gBoardModuleTokenSpaceGuid.PcdRootPort3ClkInfo|0|UINT64|0x000000A1 -gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo|0|UINT64|0x000000A2 -gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo|0|UINT64|0x000000A3 -gBoardModuleTokenSpaceGuid.PcdRootPort6ClkInfo|0|UINT64|0x000000A4 -gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo|0|UINT64|0x000000A5 -gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo|0|UINT64|0x000000A6 -gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo|0|UINT64|0x000000A7 -gBoardModuleTokenSpaceGuid.PcdRootPort10ClkInfo|0|UINT64|0x000000A8 -gBoardModuleTokenSpaceGuid.PcdRootPort11ClkInfo|0|UINT64|0x000000A9 -gBoardModuleTokenSpaceGuid.PcdRootPort12ClkInfo|0|UINT64|0x000000AA -gBoardModuleTokenSpaceGuid.PcdRootPort13ClkInfo|0|UINT64|0x000000AB -gBoardModuleTokenSpaceGuid.PcdRootPort14ClkInfo|0|UINT64|0x000000AC -gBoardModuleTokenSpaceGuid.PcdRootPort15ClkInfo|0|UINT64|0x000000AD -gBoardModuleTokenSpaceGuid.PcdRootPort16ClkInfo|0|UINT64|0x000000AE -gBoardModuleTokenSpaceGuid.PcdRootPort17ClkInfo|0|UINT64|0x000000AF -gBoardModuleTokenSpaceGuid.PcdRootPort18ClkInfo|0|UINT64|0x000000B0 -gBoardModuleTokenSpaceGuid.PcdRootPort19ClkInfo|0|UINT64|0x000000B1 -gBoardModuleTokenSpaceGuid.PcdRootPort20ClkInfo|0|UINT64|0x000000B2 -gBoardModuleTokenSpaceGuid.PcdRootPort21ClkInfo|0|UINT64|0x000000B3 -gBoardModuleTokenSpaceGuid.PcdRootPort22ClkInfo|0|UINT64|0x000000B4 -gBoardModuleTokenSpaceGuid.PcdRootPort23ClkInfo|0|UINT64|0x000000B5 -gBoardModuleTokenSpaceGuid.PcdRootPort24ClkInfo|0|UINT64|0x000000B6 -gBoardModuleTokenSpaceGuid.PcdRootPort25ClkInfo|0|UINT64|0x000000B7 -gBoardModuleTokenSpaceGuid.PcdRootPort26ClkInfo|0|UINT64|0x000000B8 -gBoardModuleTokenSpaceGuid.PcdRootPort27ClkInfo|0|UINT64|0x000000B9 -gBoardModuleTokenSpaceGuid.PcdRootPort28ClkInfo|0|UINT64|0x000000BA -gBoardModuleTokenSpaceGuid.PcdRootPort29ClkInfo|0|UINT64|0x000000BB -gBoardModuleTokenSpaceGuid.PcdRootPort30ClkInfo|0|UINT64|0x000000BC -gBoardModuleTokenSpaceGuid.PcdRootPort31ClkInfo|0|UINT64|0x000000BD -gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo|0|UINT64|0x000000BE +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo|0|UINT64|0x0000009E +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort1ClkInfo|0|UINT64|0x0000009F +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort2ClkInfo|0|UINT64|0x000000A0 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort3ClkInfo|0|UINT64|0x000000A1 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo|0|UINT64|0x000000A2 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo|0|UINT64|0x000000A3 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort6ClkInfo|0|UINT64|0x000000A4 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo|0|UINT64|0x000000A5 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo|0|UINT64|0x000000A6 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo|0|UINT64|0x000000A7 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort10ClkInfo|0|UINT64|0x000000= A8 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort11ClkInfo|0|UINT64|0x000000= A9 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort12ClkInfo|0|UINT64|0x000000= AA +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort13ClkInfo|0|UINT64|0x000000= AB +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort14ClkInfo|0|UINT64|0x000000= AC +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort15ClkInfo|0|UINT64|0x000000= AD +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort16ClkInfo|0|UINT64|0x000000= AE +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort17ClkInfo|0|UINT64|0x000000= AF +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort18ClkInfo|0|UINT64|0x000000= B0 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort19ClkInfo|0|UINT64|0x000000= B1 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort20ClkInfo|0|UINT64|0x000000= B2 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort21ClkInfo|0|UINT64|0x000000= B3 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort22ClkInfo|0|UINT64|0x000000= B4 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort23ClkInfo|0|UINT64|0x000000= B5 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort24ClkInfo|0|UINT64|0x000000= B6 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort25ClkInfo|0|UINT64|0x000000= B7 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort26ClkInfo|0|UINT64|0x000000= B8 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort27ClkInfo|0|UINT64|0x000000= B9 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort28ClkInfo|0|UINT64|0x000000= BA +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort29ClkInfo|0|UINT64|0x000000= BB +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort30ClkInfo|0|UINT64|0x000000= BC +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort31ClkInfo|0|UINT64|0x000000= BD +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo|0|UINT64|0x00000= 0BE =20 # USB 2.0 Port AFE -gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF -gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0 -gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1 -gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2 -gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3 -gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4 -gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5 -gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6 -gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7 -gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8 -gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9 -gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA -gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB -gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC -gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD -gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE =20 # USB 2.0 Port Over Current Pin -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x= 000000CF +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x= 000000D0 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x= 000000D1 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x= 000000D2 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x= 000000D3 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x= 000000D4 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x= 000000D5 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x= 000000D6 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x= 000000D7 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x= 000000D8 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0= x000000D9 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0= x000000DA +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0= x000000DB +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0= x000000DC +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0= x000000DD +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0= x000000DE =20 # USB 3.0 Port Over Current Pin -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x= 000000DF +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x= 000000E0 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x= 000000E1 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x= 000000E2 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x= 000000E3 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x= 000000E4 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x= 000000E5 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x= 000000E6 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x= 000000E7 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x= 000000E8 =20 # TBT -gBoardModuleTokenSpaceGuid.PcdDTbtBootOn |0|UINT8|0x000000E9 -gBoardModuleTokenSpaceGuid.PcdDTbtUsbOn |0|UINT8|0x000000EA -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwr |0|UINT8|0x000000EB -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly |0|UINT16|0x000000ED -gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn |0|UINT8|0x000000EE -gBoardModuleTokenSpaceGuid.PcdDTbtControllerType |0|UINT8|0x000000EF -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber |0|UINT8|0x000000F0 -gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType |0|UINT8|0x000000F1 -gBoardModuleTokenSpaceGuid.PcdExpander |0|UINT8|0x000000F2 -gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3 -gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4 -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5 -gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature |0|UINT32|0x000000F6 -gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting |0|BOOLEAN|0x000= 000F7 -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode |0|UINT8|0x000000F8 -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter |0|UINT8|0x000000F9 -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD -gBoardModuleTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE -gBoardModuleTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116 -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support |0|UINT8|0x000000102 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay |0|UINT16|0x00000103 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay |0|UINT16|0x00000104 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd |0|UINT8|0x00000105 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd |0|UINT16|0x00000106 -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107 -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108 -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109 -gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe|0|UINT32|0x00000117 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtBootOn |0|UINT8|0x000000E9 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtUsbOn |0|UINT8|0x000000EA +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpio3ForcePwr |0|UINT8|0x000000= EB +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly |0|UINT16|0x00= 0000ED +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerEn |0|UINT8|0x000000EE +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerType |0|UINT8|0x00000= 0EF +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber |0|UINT8|0x000000F0 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioAccessType |0|UINT8|0x00000= 0F1 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExpander |0|UINT8|0x000000F2 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x0= 00000F4 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0= x000000F5 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature |0|UINT32|0x00= 0000F6 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting |0|BOOL= EAN|0x000000F7 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode |0|UINT8|0x000000F8 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpio5Filter |0|UINT8|0x000000F9 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000= FA +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support |0|UINT8|0x0000001= 02 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay |0|UINT16|0x0000= 0103 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay |0|UINT16|0x00000104 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd |0|UINT8|0x000= 00105 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd |0|UINT16|0x00000106 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00= 000107 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x000001= 08 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x0= 0000109 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPchPcieRootPortHpe|0|UINT32|0x00000= 117 =20 =20 =20 =20 # UCMC GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111 -gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x00000= 0111 +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x0= 00000112 =20 # Misc -gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x0= 00000EC =20 - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|1|UINT8|0x40000009 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPs2KbMsEnable|1|UINT8|0x40000009 =20 - gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002 - gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003 - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004 - gBoardModuleTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005 - gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006 - gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A - gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B - gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x400000= 0C + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x400000= 06 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0= x4000000A + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|= 0x4000000B + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8= |0x4000000C # 0: Type-C # 1: Stacked-Jack - gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012 =20 - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x400000= 13 =20 - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0= xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID= *|0x40000014 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4= , 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0= xb0}|VOID*|0x40000014 =20 [PcdsDynamicEx] =20 @@ -313,8 +313,8 @@ gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|B= OOLEAN|0x000000EC [PcdsPatchableInModule] =20 [PcdsFeatureFlag] - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|0xF00000= 62 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN= |0xF0000062 =20 - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN|0xF00000= 00 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN= |0xF0000000 =20 - gBoardModuleTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEAN|0x00000= 0115 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEA= N|0x000000115 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index 5f77c8db0a..b6f9807e7e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -129,7 +129,7 @@ PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf =20 # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf !endif @@ -175,7 +175,7 @@ # Board Package ####################################### # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf !endif @@ -262,7 +262,7 @@ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPreMem.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib= .inf !else NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf @@ -271,7 +271,7 @@ =20 $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLi= b.inf !else NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i= nf @@ -295,7 +295,7 @@ # Board Package ####################################### # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf !endif =20 @@ -369,7 +369,7 @@ =20 $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf !else NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf @@ -378,7 +378,7 @@ =20 $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf !else NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf @@ -391,7 +391,7 @@ # Board Package ####################################### # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf @@ -400,7 +400,7 @@ !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf !else NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd= .dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc index d13761e077..c68b8a49cf 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc @@ -168,8 +168,8 @@ ###################################### # Board Configuration ###################################### - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE =20 [PcdsFixedAtBuild.common] ###################################### @@ -378,34 +378,34 @@ ###################################### =20 # Thunderbolt Configuration - gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0 - gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 - gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtControllerType|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType|0x2 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd|100 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support|0x0 - gBoardModuleTokenSpaceGuid.PcdExpander|0x0 - gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001 - gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay|5000 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerEn|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerType|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioAccessType|0x2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd|100 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExpander|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay|5000 =20 [PcdsDynamicHii.X64.DEFAULT] ###################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index efc4c2dca8..b412dc9eec 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -169,7 +169,7 @@ PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf =20 # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf !endif @@ -213,7 +213,7 @@ # Board Package ####################################### # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf !endif @@ -318,7 +318,7 @@ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib= .inf !else NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf @@ -327,7 +327,7 @@ =20 $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLi= b.inf !else NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i= nf @@ -367,7 +367,7 @@ # Board Package ####################################### # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf !endif =20 @@ -446,7 +446,7 @@ =20 $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf !else NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf @@ -455,7 +455,7 @@ =20 $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf !else NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf @@ -468,7 +468,7 @@ # Board Package ####################################### # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf @@ -477,7 +477,7 @@ !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D=3D = FALSE BoardAcpiTableLib|$(PROJECT)/Library/BoardAcpiLib/DxeBoardAcpiTabl= eLib.inf !else NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index 15d05bea43..34cc731313 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -186,8 +186,8 @@ ###################################### # Board Configuration ###################################### - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE =20 [PcdsFixedAtBuild.common] ###################################### @@ -394,34 +394,34 @@ ###################################### =20 # Thunderbolt Configuration - gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0 - gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 - gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtControllerType|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioAccessType|0x2 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd|100 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support|0x0 - gBoardModuleTokenSpaceGuid.PcdExpander|0x0 - gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001 - gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay|5000 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignature|0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcpiGpeSignaturePorting|0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerEn|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerType|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioAccessType|0x2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd|56 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd|100 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExpander|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPchPcieRootPortHpe|0x00000001 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay|0x0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay|5000 =20 [PcdsDynamicHii.X64.DEFAULT] ###################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/Fla= shMapInclude.fdf b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/F= df/FlashMapInclude.fdf index e024dd127c..c7f314ffe4 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIn= clude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Include/Fdf/FlashMapIn= clude.fdf @@ -24,8 +24,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWor= kingOffset =3D 0x0001E000 SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D 0x= 00002000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFFA40000) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x= 00020000 # -SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset =3D 0x= 00040000 # Flash addr (0xFFA60000) -SET gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize =3D 0x= 00010000 # +SET gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset =3D 0= x00040000 # Flash addr (0xFFA60000) +SET gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize =3D 0= x00010000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00050000 # Flash addr (0xFFA70000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x= 00060000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 000B0000 # Flash addr (0xFFAD0000) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fd= f b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf index 56bb0edaad..c46f7a71e5 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.fdf @@ -133,8 +133,8 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpare= Offset|gEfiMdeModulePkgTo gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize #NV_FTW_SPARE =20 -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gBoardModuleTokenS= paceGuid.PcdFlashNvDebugMessageSize -gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase|gBoardModuleTokenSpa= ceGuid.PcdFlashNvDebugMessageSize +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageOffset|gKabylake= OpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageBase|gKabylakeOp= enBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize #DEBUG_MESSAGE_AREA =20 gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvAdvancedSize @@ -621,7 +621,7 @@ READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 =20 -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf !endif =20 @@ -663,7 +663,7 @@ READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE FvNameGuid =3D 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D =20 -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= fdf b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf index 2b8eab36a1..c61b93db84 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.fdf @@ -627,7 +627,7 @@ READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 =20 -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf !endif =20 @@ -669,7 +669,7 @@ READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE FvNameGuid =3D 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D =20 -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcp= iDxe.inf b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiD= xe.inf index 0eaf2fab49..7d2e105e54 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf @@ -1,7 +1,7 @@ ### @file # Component information file for AcpiPlatform module # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -50,14 +50,14 @@ gEfiGlobalNvsAreaProtocolGuid =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress =20 - gBoardModuleTokenSpaceGuid.PcdAcpiSleepState - gBoardModuleTokenSpaceGuid.PcdAcpiHibernate - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints - gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints - gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints =20 [Depex] gEfiAcpiTableProtocolGuid AND diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/PciHotPlug/PciHot= Plug.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPl= ug.inf index 4139721e5e..92e1425a3a 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf @@ -2,7 +2,7 @@ # This module will perform specific PCI-Express devices # resource configuration. # -# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -54,7 +54,7 @@ gPcieRpConfigGuid ## CONSUMES =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPchPcieRootPortHpe =20 [Depex] gDxeTbtPolicyProtocolGuid diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/DxeTb= tPolicyLib/DxeTbtPolicyLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Featur= es/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf index 931b1a3203..74bc98228e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicy= Lib/DxeTbtPolicyLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicy= Lib/DxeTbtPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for Tbt functionality # -# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -33,25 +33,25 @@ HobLib KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpio5Filter ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber ## CONSUMES =20 =20 [Sources] diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiDx= eSmmTbtCommonLib/TbtCommonLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Fea= tures/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf index ff1f7777ce..1f8bf1be2b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf @@ -1,7 +1,7 @@ ### @file # Component information file for Tbt common library # -# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -38,25 +38,25 @@ =20 =20 [Pcd] -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtGpio5Filter ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWin10Support ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReqDelay ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtOffDelay ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpio5Filter ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWin10Support ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReqDelay ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtOffDelay ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieExtraBusRsvd ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemRsvd ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber =20 [Sources] TbtCommonLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiTb= tPolicyLib/PeiTbtPolicyLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Featur= es/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf index 91cae945b8..58ccedf935 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicy= Lib/PeiTbtPolicyLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicy= Lib/PeiTbtPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for Tbt policy # -# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -36,14 +36,14 @@ GpioLib IntelSiliconPkg/IntelSiliconPkg.dec =20 [Pcd] -gBoardModuleTokenSpaceGuid.PcdDTbtControllerEn ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtControllerType ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtBootOn ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtUsbOn ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwr ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CONSUMES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerEn ## CONSU= MES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtControllerType ## CONSU= MES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber ## CONSU= MES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtBootOn ## CONSU= MES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtUsbOn ## CONSU= MES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpio3ForcePwr ## CONSU= MES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpio3ForcePwrDly ## CONSU= MES +gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CONSU= MES =20 [Sources] PeiTbtPolicyLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/T= btSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tb= tSmm.inf index 8bc2f8729f..e6c185a4bd 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.i= nf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.i= nf @@ -43,11 +43,11 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES =20 [FixedPcd] gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES - =20 + [Sources] TbtSmiHandler.h TbtSmiHandler.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSili= conPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf b/Platform/Intel/Kab= ylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMemSil= iconPolicyNotifyLib.inf index 13c12655f6..d2929118e5 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPoli= cyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPoli= cyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf @@ -37,7 +37,7 @@ =20 [Pcd] # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr= ary/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf b/Platfor= m/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicy= NotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf index 13c12655f6..d2929118e5 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf @@ -37,7 +37,7 @@ =20 [Pcd] # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platfor= m/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf index 41deee1c97..eb7fb82361 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -90,51 +90,51 @@ PeiLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved =20 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size =20 - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 - gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 - gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable =20 - gBoardModuleTokenSpaceGuid.PcdAudioConnector + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector =20 - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid =20 [Guids] gFspNonVolatileStorageHobGuid ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePla= tformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/= GalagoPro3/Library/BasePlatformHookLib/BasePlatformHookLib.inf index b985d23f80..1de10aa008 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHo= okLib/BasePlatformHookLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BasePlatformHo= okLib/BasePlatformHookLib.inf @@ -35,17 +35,17 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSUMES + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSU= MES =20 [FixedPcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES - gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSU= MES =20 [Sources] BasePlatformHookLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAc= piLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Galago= Pro3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf index c527f3fc0e..a79bdcdbc6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/D= xeBoardAcpiTableLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/D= xeBoardAcpiTableLib.inf @@ -35,11 +35,11 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPs2KbMsEnable gMinPlatformPkgTokenSpaceGuid.PcdPciExpNative gMinPlatformPkgTokenSpaceGuid.PcdNativeAspmEnable gMinPlatformPkgTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress =20 [Sources] DxeGalagoPro3AcpiTableLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAc= piLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg= /GalagoPro3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf index fba5053d47..db8ba7a822 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/D= xeMultiBoardAcpiSupportLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/D= xeMultiBoardAcpiSupportLib.inf @@ -36,11 +36,11 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable - gBoardModuleTokenSpaceGuid.PcdPciExpNative - gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPs2KbMsEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress =20 [Sources] DxeGalagoPro3AcpiTableLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAc= piLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Galag= oPro3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf index 36c4219bf8..8360d35e01 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/S= mmBoardAcpiEnableLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/S= mmBoardAcpiEnableLib.inf @@ -36,7 +36,7 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES =20 [Protocols] =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAc= piLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardPkg= /GalagoPro3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf index ea15c7ffc2..7f8ad556e7 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/S= mmMultiBoardAcpiSupportLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardAcpiLib/S= mmMultiBoardAcpiSupportLib.inf @@ -37,7 +37,7 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES =20 [Protocols] =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Gala= goPro3/Library/BoardInitLib/PeiBoardInitPostMemLib.inf index 8a57f1f6d0..0e7249bb13 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPostMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPostMemLib.inf @@ -40,14 +40,14 @@ [FixedPcd] =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel =20 - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize =20 - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable =20 - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Galag= oPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index 53e70310e4..cad057b416 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf @@ -37,95 +37,95 @@ PeiBoardInitPreMemLib.c =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort =20 # PCH-LP HSIO PTSS Table - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 # PCH-H HSIO PTSS Table - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive =20 =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 =20 # CA Vref Configuration =20 # Root Port Clock Info - gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 =20 # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent =20 =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg= /GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf index 19e8e0144c..2ea8b2fdb3 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPostMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPostMemLib.inf @@ -42,14 +42,14 @@ [FixedPcd] =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel =20 - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize =20 - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable =20 - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/= GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index cba590b3e3..ccd385b354 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf @@ -39,92 +39,92 @@ PeiGalagoPro3Detect.c =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort =20 # PCH-LP HSIO PTSS Table - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive =20 =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 =20 # CA Vref Configuration =20 # Root Port Clock Info - gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 =20 # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent =20 =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/= DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/Ka= bylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSiliconPolicyUpdateLib/DxeS= iliconPolicyUpdateLib.inf index c9b73fc2bb..d53641ceb7 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSili= conPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Policy/Library/DxeSili= conPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf @@ -32,8 +32,8 @@ DxeSaPolicyUpdate.c =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid =20 [Protocols] gEfiFirmwareVolume2ProtocolGuid ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li= brary/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platf= orm/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPo= licyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf index 7ce6fd8470..5391bbfde0 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -90,55 +90,55 @@ PeiLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize =20 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES - =20 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 - gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 - gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size =20 - gBoardModuleTokenSpaceGuid.PcdAudioConnector + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable =20 - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector + + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid =20 [Guids] gFspNonVolatileStorageHobGuid ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BaseP= latformHookLib/BasePlatformHookLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/KabylakeRvp3/Library/BasePlatformHookLib/BasePlatformHookLib.inf index e65c7a25c2..fde7083399 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatform= HookLib/BasePlatformHookLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BasePlatform= HookLib/BasePlatformHookLib.inf @@ -1,7 +1,7 @@ ### @file # Platform Hook Library instance for SandyBridge Mobile/Desktop CRB. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -36,16 +36,16 @@ =20 [Pcd] gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort ## CONSU= MES =20 [FixedPcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES - gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSU= MES =20 [Sources] BasePlatformHookLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= AcpiLib/DxeBoardAcpiTableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Kaby= lakeRvp3/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf index dd971ef97a..7295b2d063 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib= /DxeBoardAcpiTableLib.inf @@ -35,12 +35,12 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable - gBoardModuleTokenSpaceGuid.PcdPciExpNative - gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress - =20 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPs2KbMsEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress + [Sources] DxeKabylakeRvp3AcpiTableLib.c DxeBoardAcpiTableLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= AcpiLib/DxeMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardP= kg/KabylakeRvp3/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.inf index e0394214ee..e41e9b3b91 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib= /DxeMultiBoardAcpiSupportLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib= /DxeMultiBoardAcpiSupportLib.inf @@ -1,7 +1,7 @@ ### @file # Platform Hook Library instance for SandyBridge Mobile/Desktop CRB. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -36,12 +36,12 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable - gBoardModuleTokenSpaceGuid.PcdPciExpNative - gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress - =20 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPs2KbMsEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress + [Sources] DxeKabylakeRvp3AcpiTableLib.c DxeMultiBoardAcpiSupportLib.c diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= AcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Kab= ylakeRvp3/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf index 32068b59d7..ecf3882270 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib= /SmmBoardAcpiEnableLib.inf @@ -1,7 +1,7 @@ ### @file # Platform Hook Library instance for SandyBridge Mobile/Desktop CRB. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -36,8 +36,8 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES - =20 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + [Protocols] =20 [Sources] diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= AcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/KabylakeOpenBoardP= kg/KabylakeRvp3/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf index fad4230c85..cd19b3f605 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib= /SmmMultiBoardAcpiSupportLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardAcpiLib= /SmmMultiBoardAcpiSupportLib.inf @@ -1,7 +1,7 @@ ### @file # Platform Hook Library instance for SandyBridge Mobile/Desktop CRB. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -37,8 +37,8 @@ KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES - =20 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + [Protocols] =20 [Sources] diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Ka= bylakeRvp3/Library/BoardInitLib/PeiBoardInitPostMemLib.inf index 108ee8f541..165ed97c7b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPostMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPostMemLib.inf @@ -1,7 +1,7 @@ ## @file # Component information file for KabylakeRvp3InitLib in PEI post memory ph= ase. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -40,14 +40,14 @@ [FixedPcd] =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel =20 - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize =20 - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable =20 - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Kab= ylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index 7be1c180de..dd7f3c4fbb 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf @@ -39,95 +39,95 @@ PeiBoardInitPreMemLib.c =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort =20 # PCH-LP HSIO PTSS Table - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 # PCH-H HSIO PTSS Table - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive =20 =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 =20 # CA Vref Configuration =20 # Root Port Clock Info - gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 =20 # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent =20 =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/KabylakeOpenBoardP= kg/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf index b118f9030a..43336d237f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPostMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPostMemLib.inf @@ -1,7 +1,7 @@ ## @file # Component information file for KabylakeRvp3InitLib in PEI post memory ph= ase. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -42,14 +42,14 @@ [FixedPcd] =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel =20 - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize =20 - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable =20 - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index 2d8d26d7a1..eee617e138 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf @@ -37,99 +37,99 @@ PeiKabylakeRvp3InitPreMemLib.c KabylakeRvp3HsioPtssTables.c KabylakeRvp3SpdTable.c - PeiMultiBoardInitPreMemLib.c =20 + PeiMultiBoardInitPreMemLib.c PeiKabylakeRvp3Detect.c =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort =20 # PCH-LP HSIO PTSS Table - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 # PCH-H HSIO PTSS Table - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive =20 =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 =20 # CA Vref Configuration =20 # Root Port Clock Info - gBoardModuleTokenSpaceGuid.PcdRootPort0ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort4ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort5ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort7ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort8ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPort9ClkInfo - gBoardModuleTokenSpaceGuid.PcdRootPortLanClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort0ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort4ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort5ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort7ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort8ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPort9ClkInfo + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortLanClkInfo =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 =20 # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent =20 =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/= KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/DxeSiliconPolicyUpdateLib/= DxeSiliconPolicyUpdateLib.inf index ad12b027a5..4b4f4c4288 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/DxeSi= liconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf @@ -1,7 +1,7 @@ ## @file # Component information file for Silicon Update Library # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,8 +32,8 @@ DxeSaPolicyUpdate.c =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid =20 [Protocols] gEfiFirmwareVolume2ProtocolGuid ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/= KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/= PeiSiliconPolicyUpdateLib.inf index aa163ebf08..a9d01c46bb 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -53,34 +53,34 @@ gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize =20 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSp= iFlash/PeiSerialPortLibSpiFlash.inf b/Platform/Intel/KabylakeOpenBoardPkg/L= ibrary/PeiSerialPortLibSpiFlash/PeiSerialPortLibSpiFlash.inf index ed93d0785f..31518fb40b 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/= PeiSerialPortLibSpiFlash.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Library/PeiSerialPortLibSpiFlash/= PeiSerialPortLibSpiFlash.inf @@ -46,5 +46,5 @@ =20 [Pcd] gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageBase ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdFlashNvDebugMessageSize ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageBase ## CONSU= MES + gKabylakeOpenBoardPkgTokenSpaceGuid.PcdFlashNvDebugMessageSize ## CONSU= MES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48535): https://edk2.groups.io/g/devel/message/48535 Mute This Topic: https://groups.io/mt/34439443/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48536+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48536+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511835; cv=none; d=zoho.com; s=zohoarc; b=IpBtzYpYSG/AkG2JFuzg+ncLm1wqDbhiNmwihKVSG/QYEnYnMUID5sYxGGGJnt5XqXiknIRDovpHdODVLOe3GxC8x8w+cyef/AFNK6NJYI39tP9qabjupBPn1i2RbljoXrH+JJNR858TdFQxh2+Y66GUbjgFrY1veel6RawCgbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511835; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=PbQEHrDVfEFrgJr6iKySPGZXoAcDODmEeKiJkSz0UdY=; b=KQ8ZjGJMGrwOv5OkHIYDhnHcf/XF7IvJiAwoY90RfXWwQ4htzZK7VIxp2PPOa1UKXjtXg1FRaDUmhvP7iwzrYNt4CH6fLiY58wiGsXkLRuYkUmtkifHf1SkOV9/o1S3fRT5BBd+IXtZnHa14/qVVi6SqOFZrpR2wZXu3ZDMo768= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48536+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511835843291.14084448854464; Mon, 7 Oct 2019 22:17:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id TAfKYY1788612xtyMaeNGM6L; Mon, 07 Oct 2019 22:17:14 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:14 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297290" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:14 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH V1 08/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Relocate PCD DSC include Date: Mon, 7 Oct 2019 22:16:36 -0700 Message-Id: <20191008051645.22052-9-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: dA1R0fdyXQWYKSyQvbx3tHw9x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511834; bh=N79SGrqMc+Spo9wtLB80ifUi1eneaZ1yIT6p7DnpAek=; h=Cc:Date:From:Reply-To:Subject:To; b=kYgclCMeyzXxTD+ETaUoQXKWQ8Nnq2+nY687jOU8pXprVioE7goFUZ7sJpzFdPscqZ2 AfaFQ0saf8kSrpG45okLzzIYNes42Lf+ohwnEK9Xb8qd01MzyzX+FQFqXr3AvYDPgB1Op vhedR9Me2hRvurWTRYVZioR+c09zWhHnhK0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This change moves the include of OpenBoardPkgPcd.dsc to the top of OpenBoardPkg.dsc to improve visibility and align the placement with other board DSC files. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc | = 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.dsc index eea809140c..9a516cad60 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc @@ -27,6 +27,7 @@ # Platform On/Off features are defined here # !include OpenBoardPkgConfig.dsc + !include OpenBoardPkgPcd.dsc =20 ##########################################################################= ###### # @@ -190,7 +191,6 @@ [LibraryClasses.X64.DXE_RUNTIME_DRIVER] ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - !include OpenBoardPkgPcd.dsc =20 [Components.IA32] # --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48536): https://edk2.groups.io/g/devel/message/48536 Mute This Topic: https://groups.io/mt/34439444/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48537+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48537+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511836; cv=none; d=zoho.com; s=zohoarc; b=Ac95nv3uMUU8h5Aed1svBJPd5Ukv7YItChy2y9E0qWia+R+FvzeqspB/d+lqH8IOYj3RUFu0J2sOyF6ZbbL/V9BTZl7K6DKf1TC9puHgIB58nVH3Wz5RAf8pPpbQjcdL1tZWElMLw3GuOXIY1wKMwg5P7c67ivUwMc9cmt2YE40= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511836; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=Bmt1ZKtCcvbHuIKQhIjw9nz2LG2/CyrNDox65TBhex8=; b=JEN6JQMm1QK0HCs2QSy2cb+T4ZbaG/okSlLw1s+zw/sPpE6nUMxRD42f2/4fa8IIdq5zEu7bht9n/1mrcp/2WR+PWhWg+PngUV0/Y7KyD19CpK48DszhqMjQmikm3DXIT9vgJjdesFG7UrzHdNPwyc1i4hAsza6ywjd1kFQU9n4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48537+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511836876753.2813547179325; Mon, 7 Oct 2019 22:17:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8t49YY1788612xYTiNVwbOw5; Mon, 07 Oct 2019 22:17:16 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:15 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297296" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:15 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH V1 09/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Remove OpenBoardPkgConfig.dsc Date: Mon, 7 Oct 2019 22:16:37 -0700 Message-Id: <20191008051645.22052-10-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: FJA7lfQY2oZqztfOAw6f9EWNx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511836; bh=Py9EhqZuazyjoMcoFIL38gW/yXRxPvAFjSQTarK39gk=; h=Cc:Date:From:Reply-To:Subject:To; b=MXCIZ+yviJvXKLh7vBM4viQBnFJQI3b4oL9bHbXf5sqZ7ZthYZtlhq/dCPJM4gDiJpe vjW78Gqz5PWcyS+t1AdiR/mKwfrHnJYR0UnbHEYIQxhrQzRANPdqegHipsexsZG7FGQ6U f++W/RKl7fWIgg2Noz4um73JWRNQH1g/HIY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2243 The location for PCD configuration is currently inconsistent in WhiskeylakeOpenBoardPkg. A large set of FeaturePCD definitions are in OpenBoardPkgConfig.dsc while other PCD definitions (including FeaturePCD) are located in OpenBoardPkgPcd.dsc. This change consolidates PCD configuration for the WhiskeylakeURvp board to OpenBoardPkgPcd.dsc and removes OpenBoardPkgConfig.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc = | 1 - Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgConfig.= dsc | 128 -------------------- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc= | 116 ++++++++++++++++++ 3 files changed, 116 insertions(+), 129 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.dsc index 9a516cad60..1d07fdea84 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc @@ -26,7 +26,6 @@ # # Platform On/Off features are defined here # - !include OpenBoardPkgConfig.dsc !include OpenBoardPkgPcd.dsc =20 ##########################################################################= ###### diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgConfig.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Op= enBoardPkgConfig.dsc deleted file mode 100644 index c68fecf50e..0000000000 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgCo= nfig.dsc +++ /dev/null @@ -1,128 +0,0 @@ -## @file -# Platform configuration file. -# -# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -# -## - -[PcdsFixedAtBuild] - # - # Please select BootStage here. - # Stage 1 - enable debug (system deadloop after debug init) - # Stage 2 - mem init (system deadloop after mem init) - # Stage 3 - boot to shell only - # Stage 4 - boot to OS - # Stage 5 - boot to OS with security boot enabled - # - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 - -[PcdsFeatureFlag] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE -!endif - - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - -# -# TRUE is ENABLE. FALSE is DISABLE. -# -# -# BIOS build switches configuration -# - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - -# CPU - gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE - -# SA - gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE - gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE - -# ME - gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE - gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE - - gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE - gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE - gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE - gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE - gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE - gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE -= HPET / FALSE - 8254 timer is used. - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE - - gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE - gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE - -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # - - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE - - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif - - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif - - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE - diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenB= oardPkgPcd.dsc index 96d65133ae..24e3da6686 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc @@ -14,7 +14,123 @@ # Pcd Section - list of all EDK II PCD Entries defined by this Platform # ##########################################################################= ###### +[PcdsFixedAtBuild] + # + # Please select BootStage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + [PcdsFeatureFlag.common] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + # + # More fine granularity control below: + # + + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + +# +# TRUE is ENABLE. FALSE is DISABLE. +# +# +# BIOS build switches configuration +# + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + +# CPU + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + +# SA + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE + +# ME + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE + + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE + gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE -= HPET / FALSE - 8254 timer is used. + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE + gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE + +# +# Override some PCDs for specific build requirements. +# + # + # Disable USB debug message when Source Level Debug is enabled + # because they cannot be enabled at the same time. + # + + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE + + !if $(TARGET) =3D=3D DEBUG + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !else + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !endif + + !if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + #gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48537): https://edk2.groups.io/g/devel/message/48537 Mute This Topic: https://groups.io/mt/34439445/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48538+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48538+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511838; cv=none; d=zoho.com; s=zohoarc; b=CkYpm5aQtJfQNNKs/xzaXzWWIW5obC5EOxgICNoHjHfTiroDwDZzExKxhVayfK8GwWw0IMjcwkE4AGB+ak8eGSf1j8g/OtG23clKcoyJDNwk/jz5WGlLlQ9upBSS2cuLUWL4V+gUhJsvk95SLrCCt0x3Q+mYibbOBy59tkNCwIA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511838; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=x4ThHOMVqoRKxwoWkRMVDP/gT+v+oQlLwhcyC5tFY24=; b=Q16BOmdFAOPiVJBY4FdM/MYL0rsjkdlTO7QVo6elN+YAef35rb7ZRyHSQgIpS2momt9g9JAYYOyl8/qG35JVnHqWCyKuhx32sk3cO4cYac82CaJxorl6SPWKuccv4LY5GYcHCj9gSyTFvfRu/8MK+EsFpIZPjYjg0P9P/zPlHuI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48538+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511838121737.1269253072644; Mon, 7 Oct 2019 22:17:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id J5LeYY1788612x0b9sVIYxjT; Mon, 07 Oct 2019 22:17:17 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:16 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297315" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:16 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu Subject: [edk2-devel] [edk2-platforms][PATCH V1 10/17] CoffeelakeSiliconPkg: Add DSC include file section tags Date: Mon, 7 Oct 2019 22:16:38 -0700 Message-Id: <20191008051645.22052-11-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: 8E0qjPlQ5fRxrcOxxRAau0jkx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511837; bh=zW0uRd0oRciUgLHySTMKhVTlX202CHhZy5nLgH7j1uQ=; h=Cc:Date:From:Reply-To:Subject:To; b=QpvMQp0aAFD35n2T0SGOl8RrxGWPLHF+2igjoQ6rKNiQUf0MJNGVf/bsoSIi4YjrjDq H31oa9DdMcKbwtM+RXfQVVWpuLyozZjX/2MQ9IJGWgOTkQ0jXtojaq5R0zhwYLF2oeOYg fuTfVInUES43XmIR+xEk+DG5bahkg8MnT70= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2246 The DSC LibraryClass files in CoffeelakeSiliconPkg that are intended to be included elsewhere such as SiPkgPeiLib.dsc, SiPkgDxeLib.dsc, and SiPkgCommonLib.dsc should have section tags so that they are not dependent on the top-level DSC file to place the include file in the correct location in the DSC file and better define the applicability of their library content. This change adds section tags for the library class related files. The component files may be built differently in the consuming package depending on their architecture requirements so those are not modified. Cc: Sai Chaganty Cc: Chasel Chiu Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc | 1 + Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc | 1 + Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc | 1 + 3 files changed, 3 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc b/Silico= n/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc index 2df08c6d01..7a9911e825 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc @@ -13,6 +13,7 @@ # DEFINE PCH =3D Cnl =20 +[LibraryClasses.common] # # Cpu # diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc b/Silicon/I= ntel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc index 214de06d58..e21004c993 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc @@ -7,6 +7,7 @@ # ## =20 +[LibraryClasses.common.DXE_CORE,LibraryClasses.common.DXE_SMM_DRIVER,Libra= ryClasses.common.SMM_CORE,LibraryClasses.common.DXE_DRIVER,LibraryClasses.c= ommon.DXE_RUNTIME_DRIVER,LibraryClasses.common.UEFI_DRIVER] # # Silicon Init Dxe Library # diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc b/Silicon/I= ntel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc index 6e244a6ded..bc3fcabd4d 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc @@ -7,6 +7,7 @@ # ## =20 +[LibraryClasses] # # Silicon Init Pei Library # --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48538): https://edk2.groups.io/g/devel/message/48538 Mute This Topic: https://groups.io/mt/34439446/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48539+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48539+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511838; cv=none; d=zoho.com; s=zohoarc; b=VqyW45dFb0omuQCLoSSPTFRwLW2afO+pOCUHA9fsLJTXHh6i7LFlEPyc8k28HuqBKvv7loof+jK25PqExY5C25+B2Di3D6rxsOAzwfZOzBhnpaoXLRBWzR7btXDeAGnEpTX65kyDHOsOQ9TdLVwvjUoyAq3euYihdLIVJWMJoh4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511838; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=n8iP/83sjuHq3QwrelvOJFZEtcdG+AIMdKB0b8YjRr0=; b=HmOaMMwnfF1+xOC45XmvEfVJ9bxfTRlq3V/z/fa5f5n4iqlB8oGEM7U4exwNo3waN3TYFcmr+BOVXSM0SCdDcOsMU1uPxG9rV7x2cu2vnqRJ5KXafUp6wNV1wAChegr40MoKmkXUHdNEIPW3TxiKOLHrYO3SP9VIB/BrJaSKu9M= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48539+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511838653102.55618632553194; Mon, 7 Oct 2019 22:17:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id IoJtYY1788612xn9OfNkxl01; Mon, 07 Oct 2019 22:17:17 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:17 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:17 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297320" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:17 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH V1 11/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Update FSP base PCDs Date: Mon, 7 Oct 2019 22:16:39 -0700 Message-Id: <20191008051645.22052-12-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: CVwlXzaLPLmiYZ4lsIBF6Ytpx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511837; bh=QPmGiBhsLhp1jkEsvgGb73vzJMw1Eq3I3LrA9tDofn0=; h=Cc:Date:From:Reply-To:Subject:To; b=qXg16gHIXcDkPjcVwxk21d6BUGIqbH+ezBEtU74yQ0dDVf7W2vUMTkMuIsmlUBp5qo6 Jrph1SOw27iow6uX4CO/LDKQRC5OxRRmIO8f8epumtYyD+r9VDRcWKKFx2/87/JtBG0JA AkM62dxXP0BWtL04iz4CzpyMu7RoRjeJNcY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Sets the FSP-T, FSP-M, and FSP-S base address PCDs based on the flash map. Previously these were hardcoded in the DSC file. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf | = 3 +++ 1 file changed, 3 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.fdf index 611078e4b4..30ce0b9b79 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df @@ -55,6 +55,9 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize= =3D gSiPkgTokenSpaceG SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok= enSpaceGuid.PcdBiosAreaBaseAddress SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok= enSpaceGuid.PcdBiosSize +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pcd= FlashFvFspTOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pcd= FlashFvFspMOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgT= okenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.Pcd= FlashFvFspSOffset) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok= enSpaceGuid.PcdBiosAreaBaseAddress SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok= enSpaceGuid.PcdBiosSize ##########################################################################= ###### --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48539): https://edk2.groups.io/g/devel/message/48539 Mute This Topic: https://groups.io/mt/34439447/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48540+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48540+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511839; cv=none; d=zoho.com; s=zohoarc; b=PkSZJMoJY/BfgfCHXOptu/eUOsZKPIGBL/yj7Z0JxeZP9RR4hl/n8DwJLc0xD9xdltuvbtl4qna3XV1hKx3SvM3XUg/RhFZxqVX+6y26IrA3XMZbRFlFnkADvmpjbU+t331j5nc7v/0HHwoqKmzx8BWlyzszFDPzytJHTiOD/sM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511839; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=S3Ach7ZB/0sBDRPpgCLD2R2Y5lLMVhoE5Qeo96acsyg=; b=QwnGah9IQbWFhHwPmj1DLhBDDB33w4CRoMMbHr89/bSnPM1OuKjYqjKyXwmJGFiEHbZ5Ydjb//WeCvct1EW5qmk8Vl+ea/e9YrRchUM8pzoBfgUUlBT4kATeyIbqwDEsm1QpoSTvOewkSyhCzo5wk8t9jqvmRPpYKo0eo6vXRhQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48540+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 157051183967471.1967390355295; Mon, 7 Oct 2019 22:17:19 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Wm9gYY1788612xaeG1YrL3hg; Mon, 07 Oct 2019 22:17:19 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:18 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297354" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:18 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH V1 12/17] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: DSC cleanup Date: Mon, 7 Oct 2019 22:16:40 -0700 Message-Id: <20191008051645.22052-13-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: 1PnluBFhy58RIXNA0guKePShx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511839; bh=ReYfjXx/CDdWvFJ/FF6jslT27thFO+ePTnjDvPeGC1k=; h=Cc:Date:From:Reply-To:Subject:To; b=WObqFkg2mPuI7TKgMSEgalXNUf0DjBOhHNeYCiZ/FPELEXafKtq/QA75q/pnPKW2h+j 2lo4ZbHLK2vS0ifidPT7mM/i0W8BlHWSwdqP0UoIcQLzFw0/bw4Ml4K5rxWwUDjjL5KTm h+hl4jRHsX/XxIRI8Q+pk0isCWf5vBoka1E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2243 This change refactors OpenBoardPkg.dsc and OpenBoardPkgPcd.dsc to consolidate redundant sections and better group file content to improve maintainability and readability. The same pattern made in this change for WhiskeylakeURvp is being applied to all existing board packages in Platform/Intel to improve overall consistency. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc = | 502 +++++++++++--------- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc= | 441 +++++++++-------- 2 files changed, 510 insertions(+), 433 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.dsc index 1d07fdea84..d6eb66a880 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc @@ -1,20 +1,13 @@ ## @file -# Platform description. -# +# The main build description file for the WhiskeylakeURvp board. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # -# ## =20 [Defines] - # - # Set platform specific package/folder name, same as passed from PREBUIL= D script. - # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package= build folder - # DEFINE only takes effect at R9 DSC and FDF. - # DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE =3D CoffeelakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE =3D CoffeelakeSiliconBinPkg @@ -24,7 +17,7 @@ DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE)/$(BO= ARD) =20 # - # Platform On/Off features are defined here + # Include PCD configuration for this board. # !include OpenBoardPkgPcd.dsc =20 @@ -42,8 +35,6 @@ SUPPORTED_ARCHITECTURES =3D IA32|X64 BUILD_TARGETS =3D DEBUG|RELEASE SKUID_IDENTIFIER =3D ALL - - FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf =20 FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 @@ -56,163 +47,238 @@ =20 ##########################################################################= ###### # -# SKU Identification section - list of all SKU IDs supported by this -# Platform. +# SKU Identification section - list of all SKU IDs supported by this board. # ##########################################################################= ###### [SkuIds] - 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. + 0|DEFAULT # 0|DEFAULT is reserved and always required. 0x60|WhiskeylakeURvp =20 ##########################################################################= ###### # -# Library Class section - list of all Library Classes needed by this Platf= orm. +# Includes section - other DSC file contents included for this board build. # ##########################################################################= ###### =20 - !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc - !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc - !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +####################################### +# Library Includes +####################################### +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +####################################### +# Component Includes +####################################### +[Components.IA32] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +[Components.X64] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + +####################################### +# Build Option Includes +####################################### +!include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc +!include OpenBoardPkgBuildOption.dsc + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this board. +# +##########################################################################= ###### =20 [LibraryClasses.common] - - PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf - ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf - - PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf - PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf - PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf - I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf - GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf - - PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf - - FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf - PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf - + ####################################### + # Edk2 Packages + ####################################### FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf =20 - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf - SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf - + ####################################### + # Silicon Initialization Package + ####################################### ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseCon= figBlockLib.inf - BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf - - # Tbt - !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmT= btCommonLib/TbtCommonLib.inf - !endif - DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf - # - # Silicon Init Package - # - !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc - PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDxe= SmmPchHsioLib.inf MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPci= Lib.inf + PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDxe= SmmPchHsioLib.inf PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSm= mPchPmcLib.inf =20 - TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf - -[LibraryClasses.IA32] - # - # PEI phase common - # - SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf + ##################################### + # Platform Package + ##################################### + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf - !if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/P= eiTestPointCheckLib.inf - !endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf - BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf - TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf + + ####################################### + # Board Package + ####################################### + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.inf + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf + PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf +!endif =20 - # Tbt - !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtP= olicyLib/PeiTbtPolicyLib.inf - PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/= PeiDTbtInitLib/PeiDTbtInitLib.inf - !endif - - # - # Silicon Init Package - # - !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc - PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyIni= tLib/PeiPolicyInitLib.inf - PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/Pei= PolicyBoardConfigLib.inf - PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyU= pdateLib/PeiPolicyUpdateLib.inf - PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHo= oklib.inf - !if $(TARGET) =3D=3D DEBUG - GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseG= pioCheckConflictLib.inf - !else - GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/B= aseGpioCheckConflictLibNull.inf - !endif + ####################################### + # Board-specific + ####################################### + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf =20 [LibraryClasses.IA32.SEC] + ####################################### + # Platform Package + ####################################### TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf + + ####################################### + # Board Package + ####################################### + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf + +[LibraryClasses.common.PEIM] + ####################################### + # Platform Package + ####################################### + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf +!endif + + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf +!endif + PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyInitL= ib/PeiPolicyInitLib.inf + PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyUpd= ateLib/PeiPolicyUpdateLib.inf + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf =20 -[LibraryClasses.X64] - # - # DXE phase common - # - FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf - !if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/D= xeTestPointCheckLib.inf - !endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf - MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf + ####################################### + # Board-specific + ####################################### + PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHook= lib.inf + PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/PeiPo= licyBoardConfigLib.inf + +!if $(TARGET) =3D=3D DEBUG + GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseGpi= oCheckConflictLib.inf +!else + GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/Bas= eGpioCheckConflictLibNull.inf +!endif + +[LibraryClasses.common.DXE_DRIVER] + ####################################### + # Edk2 Packages + ####################################### + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + + ####################################### + # Platform Package + ####################################### + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/DxeMultiBoardInitSupportLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/DxeMultiBoardAcpiSupportLib.inf - BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf =20 - DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxePo= licyBoardConfigLib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf +!endif + + ####################################### + # Board Package + ####################################### DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolicyUpd= ateLib/DxePolicyUpdateLib.inf - # - # Silicon Init Package - # - !include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf + + ####################################### + # Board-specific + ####################################### + DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxePo= licyBoardConfigLib.inf + +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] + ####################################### + # Edk2 Packages + ####################################### DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf =20 + ####################################### + # Silicon Initialization Package + ####################################### + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf + [LibraryClasses.X64.DXE_SMM_DRIVER] + ####################################### + # Edk2 Packages + ####################################### + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + + ####################################### + # Silicon Initialization Package + ####################################### SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf - !if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S= mmTestPointCheckLib.inf - !endif - TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf - MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf + + ####################################### + # Platform Package + ####################################### BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/SmmMultiBoardAcpiSupportLib.inf - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf - -[LibraryClasses.X64.DXE_RUNTIME_DRIVER] - ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf - DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf +!if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf +!endif =20 [Components.IA32] - # - # Common - # - !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc - - # - # FSP wrapper SEC Core - # + ####################################### + # Edk2 Packages + ####################################### UefiCpuPkg/SecCore/SecCore.inf { PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf } =20 # - # Silicon + # In FSP API mode the policy has to be installed before FSP Wrapper upda= ting UPD. + # Add policy as dependency for FSP Wrapper # - !include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf =20 - # - # Platform - # + ####################################### + # Silicon Initialization Package + ####################################### + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf + + ####################################### + # Platform Package + ####################################### $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { @@ -223,12 +289,7 @@ !endif NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf } - IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { - - SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf - SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPo= licyUpdateLibNull/SiliconPolicyUpdateLibNull.inf - } + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE @@ -237,51 +298,43 @@ NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i= nf !endif } - IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf -#to do $(PLATFORM_PACKAGE)/FspWrapper/FspWrapperPeim/FspWrapperPeim.inf + + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { + + SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Silico= nPolicyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Sili= conPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + } $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf { - SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf - SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPo= licyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Silico= nPolicyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Sili= conPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf } =20 - # - # Security - # +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif =20 - !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf - !endif - - IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf - IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf - - # Tbt - !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf - !endif + ####################################### + # Board Package + ####################################### + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf +!endif =20 [Components.X64] - - # - # Common - # - !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc - - $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf - - UefiCpuPkg/CpuDxe/CpuDxe.inf + ####################################### + # Edk2 Packages + ####################################### + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf - MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf - MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + UefiCpuPkg/CpuDxe/CpuDxe.inf =20 - # - # Shell - # ShellPkg/Application/Shell/Shell.inf { gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE @@ -301,57 +354,7 @@ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf } =20 - # - # Silicon - # - !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc - - # Tbt - !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf - $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf - $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf - !endif - - # - # Platform - # - $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{ - - NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf - } - - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf { - - SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf - SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolic= yUpdateLibNull/SiliconPolicyUpdateLibNull.inf - } - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf - IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf - - $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf - - $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf - $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf - - # - # OS Boot - # - !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf - $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf - $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { - - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE - BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf - !else - NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf - !endif - } - - $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf - +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 @@ -360,25 +363,66 @@ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialP= ort.inf !endif } +!endif =20 - !endif - - # - # Security - # - $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf - - !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE - $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf - !endif - + ####################################### + # Silicon Initialization Package + ####################################### IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf - - # - # Other - # + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf =20 - !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc - !include OpenBoardPkgBuildOption.dsc + ####################################### + # Platform Package + ####################################### + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf { + + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPo= licyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + } + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf =20 +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf + !endif + } + + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf + +!endif + + ####################################### + # Board Package + ####################################### + $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{ + + NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf + } + + # Thunderbolt +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf +!endif diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenB= oardPkgPcd.dsc index 24e3da6686..5cf0aa9d86 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc @@ -1,22 +1,24 @@ ## @file -# Platform description. +# PCD configuration build description file for the WhiskeylakeURvp board. # +# Copyright (c) 2019, Intel Corporation. All rights reserved.
# -# Copyright (c) 2019, Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# +# SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 ##########################################################################= ###### # -# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# Pcd Section - list of all PCD Entries used by this board. # ##########################################################################= ###### -[PcdsFixedAtBuild] + +[PcdsFixedAtBuild.common] + ###################################### + # Key Boot Stage and FSP configuration + ###################################### # - # Please select BootStage here. + # Please select the Boot Stage here. # Stage 1 - enable debug (system deadloop after debug init) # Stage 2 - mem init (system deadloop after mem init) # Stage 3 - boot to shell only @@ -25,56 +27,74 @@ # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 =20 + # + # 0: FSP Wrapper is running in Dispatch mode. + # 1: FSP Wrapper is running in API mode. + # Note: Dispatch mode is currently NOT supported for this board. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 + + # + # FALSE: The board is not a FSP wrapper (FSP binary not used) + # TRUE: The board is a FSP wrapper (FSP binary is used) + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 + + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 + + # + # FSP API mode does not share stack with the boot loader, + # so FSP needs more temporary memory for FSP heap + stack size. + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x26000 + # + # FSP API mode does not need to enlarge the boot loader stack size + # since the stacks are separate. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + [PcdsFeatureFlag.common] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE +!if $(TARGET) =3D=3D RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE !endif - - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE - # - # More fine granularity control below: - # - - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - -# -# TRUE is ENABLE. FALSE is DISABLE. -# -# -# BIOS build switches configuration -# + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + ###################################### + # Silicon Configuration + ###################################### + # Build switches gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE =20 -# CPU + # CPU + gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE =20 -# SA + # SA + gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE @@ -82,166 +102,132 @@ gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE =20 -# ME + # ME gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE - gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE =20 + # Others gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE - gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE - gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE -= HPET / FALSE - 8254 timer is used. - gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE - gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE - HPET / FALSE - 8254= timer is used. =20 - gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE - gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE - gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE - gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE =20 -# -# Override some PCDs for specific build requirements. -# - # - # Disable USB debug message when Source Level Debug is enabled - # because they cannot be enabled at the same time. - # +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif =20 - gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif =20 - !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !else - gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE - !endif +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif =20 - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif =20 - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif =20 - #gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE -!if $(TARGET) =3D=3D RELEASE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE !else - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE !endif - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE - - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE =20 + ###################################### + # Board Configuration + ###################################### gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE =20 [PcdsFixedAtBuild.common] - gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 -!endif - - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 - - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 - gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 - - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 - - gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 - - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + ###################################### + # Edk2 Configuration + ###################################### !if $(TARGET) =3D=3D RELEASE gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 !else gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F - gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 !endif - gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS) - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif + + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS) + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE - -# -# 8MB Default -# -gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 - -# -# 16MB TSEG in Debug build only. -# +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE !if $(TARGET) =3D=3D DEBUG - gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE !endif =20 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 =20 - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B - !endif + # Specifies timeout value in microseconds for the BSP to detect all APs = for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 =20 - - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b - !if $(TARGET) =3D=3D RELEASE - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 - !else - gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 - !endif - - gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEAC000 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFDC0000 + # + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBui= ld + # (They will be DynamicEx in FSP Dispatch mode) + # =20 ## Specifies the size of the microcode Region. # @Prompt Microcode Region size. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 =20 - ## Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - ## Specifies the AP wait loop state during POST phase. # The value is defined as below. # 1: Place AP in the Hlt-Loop state. @@ -250,6 +236,17 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 =20 + ###################################### + # Silicon Configuration + ###################################### + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpace= Guid.PcdPciExpressRegionLength + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -262,6 +259,19 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 =20 +!if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b +!if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 +!else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 +!endif + !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} !endif @@ -287,75 +297,98 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 !endif =20 [PcdsFixedAtBuild.IA32] + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 + [PcdsFixedAtBuild.X64] + ###################################### + # Edk2 Configuration + ###################################### + # Default platform supported RFC 4646 languages: (American) English gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" =20 - [PcdsPatchableInModule.common] + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 =20 + ###################################### + # Silicon Configuration + ###################################### !if $(TARGET) =3D=3D DEBUG gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 !endif =20 -[PcdsDynamicHii.X64.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" - gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" - -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout" -!endif - [PcdsDynamicDefault] - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFD50000 - # Platform will pre-allocate UPD buffer and pass it to FspWrapper - # Those dummy address will be patched before FspWrapper executing - gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0 - gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0 - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processors - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 - -[PcdsDynamicDefault.common.DEFAULT] - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + # # Set video to native resolution as Windows 8 WHCK requirement. # gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 =20 - gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 - gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00 =20 -[PcdsDynamicDefault.common.DEFAULT] + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0 =20 - # Tbt - gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13 - gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011 - gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0 + # Platform will pre-allocate UPD buffer and pass it to FspWrapper + # Those dummy address will be patched before FspWrapper executing + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0 =20 - gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 =20 + ###################################### + # Board Configuration + ###################################### + + # Thunderbolt Configuration + gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 + gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 + gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 + gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 + gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 + +[PcdsDynamicHii.X64.DEFAULT] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout" +!else + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" +!endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48540): https://edk2.groups.io/g/devel/message/48540 Mute This Topic: https://groups.io/mt/34439448/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48541+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48541+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511841; cv=none; d=zoho.com; s=zohoarc; b=mjOiYtO0kGBKrho0/TMUI1e2XJ2Lyl25/Jkm9sCKPUUG1MZZURMneTORvyB/0PjCHGcvtbolgr6FuXn90C13dISzn67FibGMkaSVa8lr9MuFrhShyU4a2B9FagphdQjiMZHNwdrtElkZdnYZWCPEzgDKVgGqTRmDQNGpcempSx8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511841; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=SOjAVe3zieU9Y7jGlgjbfzuPzqZ4YSTZwU17QlqM7IQ=; b=F1Az1liJ7s5DsmcwrBB+WUWeP+tnZwMcEjfvly4b3y+ecCPANzw3gGaRs+OxWwSfjPTQFxjOTx4j3/p6HViVBTFVKSnqwwLA1K3QmlTt5SWUtVmw1F6zq4HoUj3U25QmQuSAAToIAVV/X//7kBh00rGCTmuOvmFAghcPHfMhUDk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48541+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511841548786.0588676604837; Mon, 7 Oct 2019 22:17:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id yfscYY1788612xV6hKPN066y; Mon, 07 Oct 2019 22:17:20 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:19 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297375" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:18 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone Subject: [edk2-devel] [edk2-platforms][PATCH V1 13/17] WhiskeylakeOpenBoardPkg: Assign unique token namespace Date: Mon, 7 Oct 2019 22:16:41 -0700 Message-Id: <20191008051645.22052-14-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: 1JI0PFIXTf1XXu3kDncra1K5x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511840; bh=6HaEZaD3kZlB9ndprqRid/rGwIediUh2rT/+zvCgOls=; h=Cc:Date:From:Reply-To:Subject:To; b=oQY4ADLKA6ieV4M3O8O1sbc/VuK1BIP2tXyxydqaLQlwrKWa+ry/MirydmMkoqbFwRH yrrwwn8UeT7FEIeNGMIuRCKIZaCX/+D0PzN1D0CPaQcniJjG7UDlricuTC30B+CPoTxss uhgfc7MVa729yPXjVAqTdH+6fb1NkmEH3CA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2248 PCDs declared in the WhiskeylakeOpenBoardPkg currently use the GUID gBoardModuleTokenSpaceGuid. The same name is used in other board packages and a package has been added called BoardModulePkg so this name is now misleading. This change assigns a unique GUID value and a name specific to the package to provide differentiation from PCDs in other board packages. Cc: Chasel Chiu Cc: Nate DeSimone Signed-off-by: Michael Kubacki --- Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec = | 684 ++++++++++---------- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc = | 14 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc= | 34 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf = | 4 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf = | 14 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCo= mmonLib/TbtCommonLib.inf | 26 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLi= b/PeiTbtPolicyLib.inf | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf= | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPolicyInitLib.inf | 22 +- Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 64 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVe= rbTableLib.inf | 14 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPolicyUpdateLib.inf | 280 ++++---- Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.= inf | 164 ++--- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatfor= mHookLib/BasePlatformHookLib.inf | 12 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmBoardAcpiEnableLib.inf | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmMultiBoardAcpiSupportLib.inf | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiBoardInitPostMemLib.inf | 14 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiBoardInitPreMemLib.inf | 112 ++-- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPostMemLib.inf | 214 +++--- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPreMemLib.inf | 316 ++++----- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatform= HookLib/PeiPlatformHooklib.inf | 66 +- 21 files changed, 1031 insertions(+), 1031 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec b/Plat= form/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec index 8de48077f0..34494d0168 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec @@ -26,7 +26,7 @@ WhiskeylakeURvp/Include =20 [Guids] =20 -gBoardModuleTokenSpaceGuid =3D {0x72d1fff7, 0xa42a, 0x4219, {0= xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} +gWhiskeylakeOpenBoardPkgTokenSpaceGuid =3D {0xec265230, 0x3a23, 0x4650, {0= xb7, 0xb6, 0x52, 0x1d, 0x33, 0xd6, 0x6f, 0x78}} =20 gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0= x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} =20 @@ -72,8 +72,8 @@ gPeiTbtPolicyBoardInitDonePpiGuid =3D {0x970f9c60, 0= x8547, 0x49d7, { 0xa4, 0x =20 [PcdsFixedAtBuild] =20 -gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004 -gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0= x10001004 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT1= 6|0x10001005 =20 gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT64|0x900000= 03 gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x90000004 @@ -102,455 +102,455 @@ gPlatformModuleTokenSpaceGuid.PcdRuntimeUpdateFvHea= derLength|0x48|UINT8|0x900000 gPlatformModuleTokenSpaceGuid.PcdEcExtraIoBase|0x6A0|UINT16|0x20000505 gPlatformModuleTokenSpaceGuid.PcdFspTemporaryRamSize|0x1000|UINT32|0x10001= 003 =20 -gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 -gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018 -gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000= 001C -gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D -gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F -gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000= 021 -gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x900000= 22 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|= 0x90000015 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90= 000018 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|U= INT16|0x9000001C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9= 000001D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x900= 0001F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UI= NT16|0x90000021 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UIN= T16|0x90000022 =20 [PcdsDynamic] # Board GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000114 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x000000= 40 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00= 000041 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000= 042 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x0= 0000043 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x= 000000113 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT1= 6|0x000000114 =20 # Board Expander GPIO Table -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046 -gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x000= 00044 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0= x00000045 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00= 000046 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|= 0x00000047 =20 # TouchPanel & SDHC CD GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT3= 2|0x00000048 =20 # PCH-LP HSIO PTSS Table -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x000000= 4C -gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x000000= 4D -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x0000= 0050 -gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x0000= 0051 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|= 0x0000004A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|= 0x0000004B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UIN= T16|0x0000004C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UIN= T16|0x0000004D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT3= 2|0x0000004E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT3= 2|0x0000004F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|U= INT16|0x00000050 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|U= INT16|0x00000051 =20 # PCH-H HSIO PTSS Table -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x00000054 -gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x00000055 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000= 058 -gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000= 059 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0= x00000052 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0= x00000053 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT= 16|0x00000054 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT= 16|0x00000055 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32= |0x00000056 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32= |0x00000057 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UI= NT16|0x00000058 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UI= NT16|0x00000059 =20 # HDA Verb Table -gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A -gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B -gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E -gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F -gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x00000= 05C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0= 000005D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0= 000005E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0= 000005F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT3= 2|0x00000060 =20 # SA Misc Configuration -gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 -gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067 -gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT1= 6|0x00000067 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x000001= 01 =20 # DRAM Configuration -gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068 -gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069 -gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A -gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B -gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C -gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D -gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x= 0000006E -gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006F -gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070 -gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x0000= 0068 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x000000= 69 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000= 006B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x000= 0006C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0= x0000006D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALS= E|BOOLEAN|0x0000006E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLE= AN|0x0000006F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x000000= 71 =20 # PEG RESET GPIO -gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072 -gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073 -gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079 -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B -gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E -gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEA= N|0x00000072 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEA= N|0x00000073 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000= 079 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0= x0000007A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x00= 00007B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN= |0x0000007C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8= |0x0000007D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x= 0000007E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLE= AN|0x0000007F =20 # SPD Address Table -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099 -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B -gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00= 000099 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x00= 00009A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x00= 00009B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x00= 00009C =20 # CA Vref Configuration -gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x000000= 9D =20 # USB 2.0 Port AFE -gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF -gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0 -gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1 -gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2 -gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3 -gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4 -gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5 -gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6 -gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7 -gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8 -gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9 -gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA -gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB -gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC -gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD -gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000= C9 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000= CA +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000= CB +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000= CC +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000= CD +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000= CE =20 # USB 2.0 Port Over Current Pin -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9 -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD -gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8= |0x000000CF +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8= |0x000000D0 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8= |0x000000D1 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8= |0x000000D2 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8= |0x000000D3 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8= |0x000000D4 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8= |0x000000D5 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8= |0x000000D6 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8= |0x000000D7 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8= |0x000000D8 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT= 8|0x000000D9 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT= 8|0x000000DA +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT= 8|0x000000DB +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT= 8|0x000000DC +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT= 8|0x000000DD +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT= 8|0x000000DE =20 # USB 3.0 Port Over Current Pin -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7 -gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8= |0x000000DF +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8= |0x000000E0 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8= |0x000000E1 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8= |0x000000E2 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8= |0x000000E3 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8= |0x000000E4 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8= |0x000000E5 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8= |0x000000E6 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8= |0x000000E7 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8= |0x000000E8 =20 # Misc -gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|= 0x000000EC =20 # TBT -gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3 -gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4 -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5 -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD -gBoardModuleTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE -gBoardModuleTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116 -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100 -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107 -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108 -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x00000= 0F3 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|= 0x000000F4 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT3= 2|0x000000F5 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000= 000FA +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000= FF +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0= x00000107 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x000= 00108 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|= 0x00000109 =20 # UCMC GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111 -gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x00= 0000111 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|= 0x000000112 =20 -gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002 -gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003 -gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004 -gBoardModuleTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005 -gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006 -gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|0|UINT8|0x40000009 -gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A -gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B -gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000= 006 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPs2KbMsEnable|0|UINT8|0x40000009 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|= 0x4000000A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8= |0x4000000B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT= 8|0x4000000C =20 # 0: Type-C # 1: Stacked-Jack -gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012 =20 -gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000= 013 =20 # gIntelPeiGraphicsVbtGuid =3D {0x4ad46122, 0xffeb, 0x4a52, {0xbf, 0xb0, = 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}} -gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xe= b, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|= 0x40000014 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd= 4, 0x4a, 0xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, = 0xb0}|VOID*|0x40000014 #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D # # The PCD which indicates the Memory Slot Population. # -gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType|FALSE|BOOLEAN|0x= 00101027 -gBoardModuleTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate|0|UINT64|0x0000= 0010 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType|FALS= E|BOOLEAN|0x00101027 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate|0|U= INT64|0x00000010 =20 # Board GPIO Table -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem|0|UINT32|0x0= 01000115 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize|0|UINT16= |0x001000116 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem|0|UINT32|0x= 001000117 -gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize|0|UINT1= 6|0x001000118 -gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio|0x0|UINT32|0x001002= 0C -gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|UINT8|0x0010022E -gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32|0x0010022F -gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32|0x00100230 -gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BOOLEAN|0x00100231 -gBoardModuleTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32|0x00100234 -gBoardModuleTokenSpaceGuid.PcdWlanRootPortNumber|0x0|UINT8|0x00100235 -gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround|FALSE|BOOLEAN|0x00100236 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem|= 0|UINT32|0x001000115 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemS= ize|0|UINT16|0x001000116 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem= |0|UINT32|0x001000117 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem= Size|0|UINT16|0x001000118 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio|0x0|UIN= T32|0x0010020C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|UINT8|= 0x0010022E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32|0x00100= 22F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32|0x00100= 230 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BOOLEAN|0x0= 0100231 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32|0x001002= 34 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWlanRootPortNumber|0x0|UINT8|0x0= 0100235 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround|FALSE|BOOLEA= N|0x00100236 =20 # UCMC GPIO Table -gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033 -gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x= 00100033 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT1= 6|0x00100034 =20 # PEG RESET GPIO -gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT32|0x00000074 -gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|BOOLEAN|0x00000075 -gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT32|0x00000105 -gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|BOOLEAN|0x00000106 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT32|0x0000= 0074 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|BOOLEA= N|0x00000075 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT32|0x0000= 0105 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|BOOLEA= N|0x00000106 =20 # PCIE RTD3 GPIO -gBoardModuleTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x00000076 -gBoardModuleTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0x00000077 -gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000104 -gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|0x00000078 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x00000076 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0x000000= 77 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000= 104 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|0x00000= 078 =20 -gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|0x00000080 -gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32|0x00000081 -gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|UINT8|0x00000082 -gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT32|0x00000083 -gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|BOOLEAN|0x00000084 -gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo|0|UINT8|0x00000085 -gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UINT32|0x00000086 -gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE|BOOLEAN|0x00000087 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|0x00000= 080 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32|0x00000= 081 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|UINT8|0= x00000082 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT32|0x00= 000083 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|BOOLEAN= |0x00000084 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo|0|UINT8= |0x00000085 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UINT32|0x= 00000086 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE|BOOLE= AN|0x00000087 =20 -gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|0x00000088 -gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32|0x00000089 -gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|UINT8|0x0000008A -gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT32|0x0000008B -gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|BOOLEAN|0x0000008C -gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo|0|UINT8|0x0000008D -gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UINT32|0x0000008E -gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE|BOOLEAN|0x0000008F -gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|0x00000130 -gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32|0x00000131 -gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|UINT8|0x00000132 -gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT32|0x00000133 -gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|BOOLEAN|0x00000134 -gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo|0|UINT8|0x00000135 -gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UINT32|0x00000136 -gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE|BOOLEAN|0x00000137 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|0x00000= 088 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32|0x00000= 089 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|UINT8|0= x0000008A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT32|0x00= 00008B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|BOOLEAN= |0x0000008C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo|0|UINT8= |0x0000008D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UINT32|0x= 0000008E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE|BOOLE= AN|0x0000008F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|0x00000= 130 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32|0x00000= 131 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|UINT8|0= x00000132 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT32|0x00= 000133 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|BOOLEAN= |0x00000134 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo|0|UINT8= |0x00000135 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UINT32|0x= 00000136 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE|BOOLE= AN|0x00000137 =20 # Root Port Clock Info -gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E -gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F -gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0 -gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1 -gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2 -gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3 -gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4 -gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5 -gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6 -gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7 -gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8 -gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9 -gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA -gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB -gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC -gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD =20 # GPIO Group Tier -gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9 -gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA -gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000= 000E9 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000= 000EA +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000= 000EB =20 # Board related PCH PmConfig -gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FALSE|BOOLEAN|0x000000= F6 -gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE|BOOLEAN|0x000000F7 -gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE|BOOLEAN|0x000000F8 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FALSE|BOOL= EAN|0x000000F6 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE|BOOLEAN= |0x000000F7 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE|BOOLEAN= |0x000000F8 =20 # Misc -gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|0x000000ED -gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0x000000EE -gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BOOLEAN|0x000000EF -gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT64|0x000000F0 -gBoardModuleTokenSpaceGuid.PcdMobileDramPresent|FALSE|BOOLEAN|0x000000F1 -gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BOOLEAN|0x000000F2 -gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|0x000000F9 -#gBoardModuleTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLEAN|0x000000FC +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEA= N|0x000000ED +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN= |0x000000EE +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BOOLEAN|0= x000000EF +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT64|0x0000= 00F0 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent|FALSE|BOOLEAN|= 0x000000F1 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BOOLEAN|0x= 000000F2 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEA= N|0x000000F9 +#gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLEAN|0x000= 000FC =20 #PlatformInfoPcd -gBoardModuleTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLEAN|0x00101= 000 -gBoardModuleTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLEAN|0x00101001 -gBoardModuleTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BOOLEAN|0x00101002 -gBoardModuleTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0x00101003 -gBoardModuleTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004 -gBoardModuleTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|0x00101005 -gBoardModuleTokenSpaceGuid.PcdBoardName|L"0123456789ABCDEF0123456789ABCDEF= "|VOID*|0x00101007 -gBoardModuleTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8|0x00101008 -gBoardModuleTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8|0x00101009 -gBoardModuleTokenSpaceGuid.PcdBiosVersion|L"012345678901234567890123456789= 0123456789"|VOID*|0x0010100E -gBoardModuleTokenSpaceGuid.PcdReleaseDate|L"01234567890123456789"|VOID*|0x= 0010100F -gBoardModuleTokenSpaceGuid.PcdReleaseTime|L"01234567890123456789"|VOID*|0x= 00101010 -gBoardModuleTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x00101011 -gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012 -gBoardModuleTokenSpaceGuid.PcdDockAttached|FALSE|BOOLEAN|0x00101013 -gBoardModuleTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014 -gBoardModuleTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015 -gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x00101016 -gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x00101017 -gBoardModuleTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101018 -gBoardModuleTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019 -gBoardModuleTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|0x0010101A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOO= LEAN|0x00101000 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLEAN|0x001= 01001 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BOOLEAN|0= x00101002 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0x001010= 03 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|0x00101005 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardName|L"0123456789ABCDEF0123= 456789ABCDEF"|VOID*|0x00101007 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8|0x0010= 1008 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8|0x0010= 1009 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBiosVersion|L"012345678901234567= 8901234567890123456789"|VOID*|0x0010100E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdReleaseDate|L"012345678901234567= 89"|VOID*|0x0010100F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdReleaseTime|L"012345678901234567= 89"|VOID*|0x00101010 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x0= 0101011 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101= 012 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDockAttached|FALSE|BOOLEAN|0x001= 01013 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101= 015 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x00101016 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x00101017 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101018 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|0x001010= 1A =20 # PCH Misc Configuration -gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE|BOOLEAN|0x00000061 -gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x00000065 -gBoardModuleTokenSpaceGuid.PcdSmbiosFabBoardName|0|UINT64|0x00000102 -gBoardModuleTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UINT64|0x00000103 -gBoardModuleTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|0x00000110 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE|BOOLEAN= |0x00000061 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|= 0x00000065 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosFabBoardName|0|UINT64|0x00= 000102 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UINT64|0x0= 0000103 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEA= N|0x00000110 =20 # Control PCD to dump default silicon policy gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy|FALSE|BOOLEAN|0x= 00010064 =20 # Pch SerialIo I2c Pads Termination -gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x0= 0000020 -gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x0= 0000021 -gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x0= 0000022 -gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x0= 0000023 -gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x0= 0000030 -gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x0= 0000031 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0= x1|UINT8|0x00000020 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0= x1|UINT8|0x00000021 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0= x1|UINT8|0x00000022 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0= x1|UINT8|0x00000023 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0= x1|UINT8|0x00000030 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0= x1|UINT8|0x00000031 # # The PCD which holds the pointer of Smbios Platform Info table # -gBoardModuleTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT64|0x0010101B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT64|0x00= 10101B # # The PCD which used to enable / disable the code to use RVP Smbios Board = Info # -gBoardModuleTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FALSE|BOOLEAN|0x001010= 1C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FALSE|BOOL= EAN|0x0010101C # # The PCD which holds the pointer of RVP Smbios Board Info # -gBoardModuleTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|0x0010101D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|0x00101= 01D # # CoEngineering Custom Defaults PCD # -gBoardModuleTokenSpaceGuid.PcdCoEngEnableCustomDefaults|0x0|UINT8|0x001002= 27 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCoEngEnableCustomDefaults|0x0|UI= NT8|0x00100227 # # The PCD which is defined to enable/disable the SMBus Alert function. # -gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0010101E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0= x0010101E # # The PCD which is defined to enable/disable the SATA LED function. # -gBoardModuleTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010101F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x00= 10101F # # The PCD which is defined to enable/disable the VR Alert function. # -gBoardModuleTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00101020 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00= 101020 # # The PCD which is defined to enable/disable the PCH thermal hot threshold= function. # -gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable|FALSE|BOOLEAN|0x00101021 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable|FALSE|BOOLEA= N|0x00101021 # # The PCD which is defined to enable/disable the memory thermal sensor GPI= O C/D function. # -gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable|TRUE|BO= OLEAN|0x00101022 -gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable|TRUE|BO= OLEAN|0x00101023 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEn= able|TRUE|BOOLEAN|0x00101022 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEn= able|TRUE|BOOLEAN|0x00101023 # # The PCD defines the I2C bus number to which PSS chip connected. # -gBoardModuleTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101024 -gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UINT8|0x00101025 -gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00101026 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x001010= 24 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UINT8|0x001= 01025 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x= 00101026 # # The PCD defines the USB port number to which BLE connected. # -gBoardModuleTokenSpaceGuid.PcdBleUsbPortNumber |0x0|UI= NT8|0x00101028 -gBoardModuleTokenSpaceGuid.PcdEcHotKeyF3Support |0x00|U= INT8|0x00100113 -gBoardModuleTokenSpaceGuid.PcdEcHotKeyF4Support |0x00|U= INT8|0x00100114 -gBoardModuleTokenSpaceGuid.PcdEcHotKeyF5Support |0x00|U= INT8|0x00100115 -gBoardModuleTokenSpaceGuid.PcdEcHotKeyF6Support |0x00|U= INT8|0x00100116 -gBoardModuleTokenSpaceGuid.PcdEcHotKeyF7Support |0x00|U= INT8|0x00100117 -gBoardModuleTokenSpaceGuid.PcdEcHotKeyF8Support |0x00|U= INT8|0x00100118 -gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport |FALSE|= BOOLEAN|0x00100119 -gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport |FALSE|= BOOLEAN|0x0010011A -gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport |FALSE|= BOOLEAN|0x0010011B -gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport |FALSE|= BOOLEAN|0x0010011C -gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport |FALSE|= BOOLEAN|0x0010011D -gBoardModuleTokenSpaceGuid.PcdAcDcAutoSwitchSupport |FALSE|= BOOLEAN|0x0010011F -gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin |0x00|U= INT32|0x00100120 -gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport |FALSE|= BOOLEAN|0x00100121 -gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport |FALSE|= BOOLEAN|0x00100122 -gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature |FALSE|= BOOLEAN|0x00100123 -gBoardModuleTokenSpaceGuid.PcdBatteryPresent |0x0|UI= NT8|0x00100124 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BOOLEAN|0x00100212 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOOLEAN|0x00100213 -gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|0x00100204 -gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x00100205 -gBoardModuleTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UINT32|0x00100209 -gBoardModuleTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT32|0x0010020A -gBoardModuleTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|0x0010020B -gBoardModuleTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT32|0x0010020F -gBoardModuleTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UINT32|0x00100210 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber = |0x0|UINT8|0x00101028 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support = |0x00|UINT8|0x00100113 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support = |0x00|UINT8|0x00100114 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support = |0x00|UINT8|0x00100115 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support = |0x00|UINT8|0x00100116 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support = |0x00|UINT8|0x00100117 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support = |0x00|UINT8|0x00100118 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport = |FALSE|BOOLEAN|0x00100119 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport = |FALSE|BOOLEAN|0x0010011A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport = |FALSE|BOOLEAN|0x0010011B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSupport= |FALSE|BOOLEAN|0x0010011C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport = |FALSE|BOOLEAN|0x0010011D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport = |FALSE|BOOLEAN|0x0010011F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin = |0x00|UINT32|0x00100120 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport = |FALSE|BOOLEAN|0x00100121 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport = |FALSE|BOOLEAN|0x00100122 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature = |FALSE|BOOLEAN|0x00100123 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent = |0x0|UINT8|0x00100124 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BOOLEAN|0x= 00100212 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOOLEAN|0x0= 0100213 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT6= 4|0x00100204 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x0= 0100205 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UINT32|= 0x00100209 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT32|0x= 0010020A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|0x00100= 20B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT32|0x001= 0020F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UINT32|0x0= 0100210 =20 -gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecIrqGpio |0x0|UI= NT32|0x00100126 -gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber |0x0|UI= NT8|0x00100127 -gBoardModuleTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x00100200 -gBoardModuleTokenSpaceGuid.PcdEcLowPowerExitGpio |0x0|UI= NT32|0x00100125 -gBoardModuleTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x00100201 -gBoardModuleTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALSE|BOOLEAN|0x00100202 -gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0x00100203 -gBoardModuleTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x00100215 -gBoardModuleTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT64|0x00100217 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8|0x00100039 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UINT8|0x0010003A -gBoardModuleTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|UINT8|0x0010003B -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8|0x0010003C -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UINT8|0x0010003D -gBoardModuleTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|UINT8|0x0010003E -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8|0x0010003F -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UINT8|0x00100040 -gBoardModuleTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|UINT8|0x00100041 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8|0x00100042 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UINT8|0x00100043 -gBoardModuleTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|UINT8|0x00100044 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8|0x00100045 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UINT8|0x00100046 -gBoardModuleTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|UINT8|0x00100047 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8|0x00100048 -gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UINT8|0x00100049 -gBoardModuleTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|UINT8|0x0010004A -gBoardModuleTokenSpaceGuid.PcdMipiCam0LinkUsed |0x0|UI= NT8|0x00100128 -gBoardModuleTokenSpaceGuid.PcdMipiCam1LinkUsed |0x0|UI= NT8|0x00100129 -gBoardModuleTokenSpaceGuid.PcdMipiCam2LinkUsed |0x0|UI= NT8|0x0010012A -gBoardModuleTokenSpaceGuid.PcdMipiCam3LinkUsed |0x0|UI= NT8|0x0010012B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio = |0x0|UINT32|0x00100126 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber = |0x0|UINT8|0x00100127 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x00100200 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio = |0x0|UINT32|0x00100125 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x001002= 01 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALSE|BOOLEA= N|0x00100202 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN= |0x00100203 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x00100215 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT64|0x00= 100217 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8|0x00100= 039 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UINT8|0x00= 10003A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|UINT8|0= x0010003B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8|0x00100= 03C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UINT8|0x00= 10003D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|UINT8|0= x0010003E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8|0x00100= 03F +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UINT8|0x00= 100040 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|UINT8|0= x00100041 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8|0x00100= 042 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UINT8|0x00= 100043 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|UINT8|0= x00100044 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8|0x00100= 045 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UINT8|0x00= 100046 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|UINT8|0= x00100047 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8|0x00100= 048 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UINT8|0x00= 100049 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|UINT8|0= x0010004A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed = |0x0|UINT8|0x00100128 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed = |0x0|UINT8|0x00100129 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed = |0x0|UINT8|0x0010012A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed = |0x0|UINT8|0x0010012B =20 # Super IO Pcd gPlatformModuleTokenSpaceGuid.PcdH8S2113Present|TRUE|BOOLEAN|0xF0000100 gPlatformModuleTokenSpaceGuid.PcdNat87393Present|TRUE|BOOLEAN|0xF0000104 gPlatformModuleTokenSpaceGuid.PcdNct677FPresent|TRUE|BOOLEAN|0xF0000105 -gBoardModuleTokenSpaceGuid.PcdConvertableDockSupport |FALSE|= BOOLEAN|0x00100112 -gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin |0x00|U= INT32|0x00100111 -gBoardModuleTokenSpaceGuid.PcdRealBattery1Control |0x00|U= INT8|0x00100103 -gBoardModuleTokenSpaceGuid.PcdRealBattery2Control |0x00|U= INT8|0x00100104 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport = |FALSE|BOOLEAN|0x00100112 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin = |0x00|UINT32|0x00100111 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control = |0x00|UINT8|0x00100103 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control = |0x00|UINT8|0x00100104 =20 -gBoardModuleTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|0x00100221 -gBoardModuleTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x0010020E -gBoardModuleTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x0010020D -gBoardModuleTokenSpaceGuid.PcdWhlErbRtd3TableEnable|FALSE|BOOLEAN|0x001002= 2C -gBoardModuleTokenSpaceGuid.PcdTypeCPortsSupported|0x00|UINT8|0x0010004B -gBoardModuleTokenSpaceGuid.PcdMipiCamSensor |FALSE|= BOOLEAN|0x00100105 -gBoardModuleTokenSpaceGuid.PcdH8S2113SIO |FALSE|= BOOLEAN|0x0010010A -gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM |FALSE|= BOOLEAN|0x00100107 -gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO |FALSE|= BOOLEAN|0x00100108 -gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON |FALSE|= BOOLEAN|0x00100109 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEA= N|0x00100221 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x0010020E +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x001002= 0D +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWhlErbRtd3TableEnable|FALSE|BOOL= EAN|0x0010022C +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported|0x00|UINT8|0= x0010004B +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor = |FALSE|BOOLEAN|0x00100105 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO = |FALSE|BOOLEAN|0x0010010A +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM = |FALSE|BOOLEAN|0x00100107 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO = |FALSE|BOOLEAN|0x00100108 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON = |FALSE|BOOLEAN|0x00100109 =20 [PcdsDynamicEx] =20 @@ -559,7 +559,7 @@ gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON = |FALSE|BOOLEA [PcdsPatchableInModule] =20 [PcdsFeatureFlag] -gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|0xF0000062 -gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN|0xF0000000 -gBoardModuleTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEAN|0x0000001= 15 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEA= N|0xF0000062 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEA= N|0xF0000000 +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLE= AN|0x000000115 =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.dsc index d6eb66a880..423fa88c12 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc @@ -130,7 +130,7 @@ PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmTbt= CommonLib/TbtCommonLib.inf !endif =20 @@ -169,7 +169,7 @@ # Board Package ####################################### # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/Pe= iDTbtInitLib/PeiDTbtInitLib.inf PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf !endif @@ -282,7 +282,7 @@ $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D= =3D FALSE BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib= .inf !else NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf @@ -292,7 +292,7 @@ =20 $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D= =3D FALSE BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLi= b.inf !else NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i= nf @@ -318,7 +318,7 @@ # Board Package ####################################### # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf !endif =20 @@ -397,7 +397,7 @@ =20 $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { - !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport =3D= =3D FALSE BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf !else NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf @@ -417,7 +417,7 @@ } =20 # Thunderbolt -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenB= oardPkgPcd.dsc index 5cf0aa9d86..adbd48f6d7 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc @@ -166,9 +166,9 @@ ###################################### # Board Configuration ###################################### - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE - gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE - gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable|TRUE + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMultiBoardSupport|TRUE + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable|FALSE =20 [PcdsFixedAtBuild.common] ###################################### @@ -367,20 +367,20 @@ ###################################### =20 # Thunderbolt Configuration - gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtAspm|0x0 - gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x02010011 - gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 - gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 - gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 - gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0x1 - gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 - gBoardModuleTokenSpaceGuid.PcdRtd3Tbt|0x1 - gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch|0x0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm|0x0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad|0x0201= 0011 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtForcepowerGpioPad|13 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtGpioLevel|0x1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify|0x1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI|0x1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax|26 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax|28 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd|100 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq|0x1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport|0x0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt|0x1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq|0x1 =20 [PcdsDynamicHii.X64.DEFAULT] ###################################### diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.fdf index 30ce0b9b79..320e444aae 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df @@ -613,7 +613,7 @@ READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 =20 -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf !endif =20 @@ -655,7 +655,7 @@ READ_LOCK_CAP =3D TRUE READ_LOCK_STATUS =3D TRUE FvNameGuid =3D 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D =20 -!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +!if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Board= AcpiDxe.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Boar= dAcpiDxe.inf index 2bbc3cb9e2..af5c8f1c06 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe= .inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe= .inf @@ -51,14 +51,14 @@ gEfiGlobalNvsAreaProtocolGuid =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiGnvsAddress =20 - gBoardModuleTokenSpaceGuid.PcdAcpiSleepState - gBoardModuleTokenSpaceGuid.PcdAcpiHibernate - gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle - gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints - gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints - gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiSleepState + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHibernate + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLowPowerS0Idle + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisableActiveTripPoints + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisablePassiveTripPoints + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisableCriticalTripPoints =20 [Depex] gEfiAcpiTableProtocolGuid AND diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iDxeSmmTbtCommonLib/TbtCommonLib.inf b/Platform/Intel/WhiskeylakeOpenBoardP= kg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf index f2330b5b71..75c4f8118d 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmm= TbtCommonLib/TbtCommonLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmm= TbtCommonLib/TbtCommonLib.inf @@ -40,19 +40,19 @@ =20 =20 [Pcd] -gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES -gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSecurityMode ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotSMI ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtHotNotify ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtSetClkReq ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAspm ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3Tbt ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSU= MES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtPcieRpNumber =20 [Sources] TbtCommonLib.c diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iTbtPolicyLib/PeiTbtPolicyLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf index b74e641e16..7ede75d14e 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf @@ -37,7 +37,7 @@ GpioLib IntelSiliconPkg/IntelSiliconPkg.dec =20 [Pcd] -gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CONSUMES +gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CO= NSUMES =20 [Sources] PeiTbtPolicyLib.c diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Sm= m/TbtSmm.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/= Smm/TbtSmm.inf index 3d4e6ceea0..bfe299d733 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm= m.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm= m.inf @@ -45,7 +45,7 @@ CoffeelakeSiliconPkg/SiPkg.dec =20 [Pcd] -# gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES +# gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES =20 [FixedPcd] diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf index bd39cd60b7..8146d0fa03 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPolicyInitLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPolicyInitLib.inf @@ -75,17 +75,17 @@ [Pcd] gSiPkgTokenSpaceGuid.PcdTsegSize gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES - gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CON= SUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CON= SUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CON= SUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize ## CON= SUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CON= SUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CON= SUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CON= SUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CON= SUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CON= SUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CON= SUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CON= SUMES =20 [Ppis] gSiPolicyPpiGuid ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/= WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/Pei= SiliconPolicyUpdateLibFsp.inf index 994cf93e33..c6dea37402 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -90,45 +90,45 @@ PeiLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor ## CONS= UMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget ## CONS= UMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap ## CONS= UMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONS= UMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize =20 =20 - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES - gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size =20 - gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGraphicsVbtGuid =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 =20 [Guids] gFspNonVolatileStorageHobGuid ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PeiHdaVerbTableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library= /PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf index b09dc6b139..31b42bf4ab 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.inf @@ -59,10 +59,10 @@ PcdLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable ##= CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaVerbTable2 ##= CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdExtHdaVerbTable ##= CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable1 ##= CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable2 ##= CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCommonHdaVerbTable3 ##= CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDisplayAudioHdaVerbTable ##= CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf index 3095a7333e..ad3146dc7b 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPolicyUpdateLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPolicyUpdateLib.inf @@ -71,174 +71,174 @@ gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdBoardBomId ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId ## CONSUM= ES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUM= ES =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize = ## CONSUMES =20 # Display DDI - gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize = ## CONSUMES =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive = ## CONSUMES =20 # PCIE RTD3 GPIO - gBoardModuleTokenSpaceGuid.PcdRootPortDev ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdRootPortFunc ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex = ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive = ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive = ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive = ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive = ## CONSUMES =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 = ## CONSUMES =20 # CA Vref Configuration - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMobileDramPresent ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent = ## CONSUMES =20 # PCIe Clock Info - gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15 = ## CONSUMES =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe = ## CONSUMES =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 = ## CONSUMES =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 = ## CONSUMES =20 # Pch SerialIo I2c Pads Termination - gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm= ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm= ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm= ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm= ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm= ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm= ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdEcPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent =20 - gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSataLedEnable ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdVrAlertEnable ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable ## C= ONSUMES - gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable ## C= ONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmbusAlertEnable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSataLedEnable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVrAlertEnable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPchThermalHotEnable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsync= Enable ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsync= Enable ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid ## C= ONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## C= ONSUMES =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Po= licyInitDxe.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitD= xe/PolicyInitDxe.inf index 65c531a532..3233375d65 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.inf @@ -49,105 +49,105 @@ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ##= CONSUMES gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ##= CONSUMES gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ##= CONSUMES - gBoardModuleTokenSpaceGuid.PcdIntelGopEnable - gBoardModuleTokenSpaceGuid.PcdPlatformFlavor - gBoardModuleTokenSpaceGuid.PcdPlatformType - gBoardModuleTokenSpaceGuid.PcdEcPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIntelGopEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformFlavor + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcPresent gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid - gBoardModuleTokenSpaceGuid.PcdTbtEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable gSiPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable ##= CONSUMES gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable ##= CONSUMES gSiPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication ##= CONSUMES gSiPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication ##= CONSUMES gSiPkgTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication ##= CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport - gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport - gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport - gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport - gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport - gBoardModuleTokenSpaceGuid.PcdAcDcAutoSwitchSupport - gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin - gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport - gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport - gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature - gBoardModuleTokenSpaceGuid.PcdBatteryPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdVirtualButtonRotationLockSuppo= rt + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlateModeSwitchSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcDcAutoSwitchSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPmPowerButtonGpioPin + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiEnableAllButtonSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdAcpiHidDriverButtonSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTsOnDimmTemperature + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBatteryPresent =20 - gBoardModuleTokenSpaceGuid.PcdUsbTypeCSupport - gBoardModuleTokenSpaceGuid.PcdUsbTypeCEcLess - gBoardModuleTokenSpaceGuid.PcdEcHotKeyF3Support - gBoardModuleTokenSpaceGuid.PcdEcHotKeyF4Support - gBoardModuleTokenSpaceGuid.PcdEcHotKeyF5Support - gBoardModuleTokenSpaceGuid.PcdEcHotKeyF6Support - gBoardModuleTokenSpaceGuid.PcdEcHotKeyF7Support - gBoardModuleTokenSpaceGuid.PcdEcHotKeyF8Support + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCEcLess + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF3Support + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF4Support + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF5Support + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF6Support + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF7Support + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcHotKeyF8Support =20 # # PSS Board Configuration. # - gBoardModuleTokenSpaceGuid.PcdPssReadSN - gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber - gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssReadSN + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cBusNumber + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPssI2cSlaveAddress =20 - gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature - gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile - gBoardModuleTokenSpaceGuid.PcdFingerPrintSleepGpio - gBoardModuleTokenSpaceGuid.PcdFingerPrintIrqGpio - gBoardModuleTokenSpaceGuid.PcdGnssResetGpio - gBoardModuleTokenSpaceGuid.PcdTouchpadIrqGpio - gBoardModuleTokenSpaceGuid.PcdTouchpanelIrqGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdXhciAcpiTableSignature + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPreferredPmProfile + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintSleepGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFingerPrintIrqGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGnssResetGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTouchpadIrqGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTouchpanelIrqGpio =20 - gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecIrqGpio - gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber - gBoardModuleTokenSpaceGuid.PcdBleUsbPortNumber - gBoardModuleTokenSpaceGuid.PcdEcSmiGpio - gBoardModuleTokenSpaceGuid.PcdEcLowPowerExitGpio - gBoardModuleTokenSpaceGuid.PcdHidI2cIntPad - gBoardModuleTokenSpaceGuid.PcdDetectPs2KbOnCmdAck - gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride - gBoardModuleTokenSpaceGuid.PcdDDISelection - gBoardModuleTokenSpaceGuid.PcdGfxCrbDetectGpio - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1 - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1Pch - gBoardModuleTokenSpaceGuid.PcdUsbCPort1Proterties - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2 - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2Pch - gBoardModuleTokenSpaceGuid.PcdUsbCPort2Proterties - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3 - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3Pch - gBoardModuleTokenSpaceGuid.PcdUsbCPort3Proterties - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4 - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4Pch - gBoardModuleTokenSpaceGuid.PcdUsbCPort4Proterties - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5 - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5Pch - gBoardModuleTokenSpaceGuid.PcdUsbCPort5Proterties - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6 - gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6Pch - gBoardModuleTokenSpaceGuid.PcdUsbCPort6Proterties - gBoardModuleTokenSpaceGuid.PcdMipiCam0LinkUsed - gBoardModuleTokenSpaceGuid.PcdMipiCam1LinkUsed - gBoardModuleTokenSpaceGuid.PcdMipiCam2LinkUsed - gBoardModuleTokenSpaceGuid.PcdMipiCam3LinkUsed + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecIrqGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBleUsbPortNumber + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcSmiGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdEcLowPowerExitGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdHidI2cIntPad + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDetectPs2KbOnCmdAck + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdAddressOverride + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDDISelection + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGfxCrbDetectGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort1Pch + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort1Proterties + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort2Pch + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort2Proterties + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort3Pch + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort3Proterties + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort4Pch + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort4Proterties + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort5Pch + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort5Proterties + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbTypeCPort6Pch + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsbCPort6Proterties + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam0LinkUsed + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam1LinkUsed + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam2LinkUsed + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCam3LinkUsed gPlatformModuleTokenSpaceGuid.PcdH8S2113Present gPlatformModuleTokenSpaceGuid.PcdNat87393Present gPlatformModuleTokenSpaceGuid.PcdNct677FPresent - gBoardModuleTokenSpaceGuid.PcdConvertableDockSupport - gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin - gBoardModuleTokenSpaceGuid.PcdRealBattery1Control - gBoardModuleTokenSpaceGuid.PcdRealBattery2Control - gBoardModuleTokenSpaceGuid.PcdDimmPopulationError - gBoardModuleTokenSpaceGuid.PcdBtIrqGpio - gBoardModuleTokenSpaceGuid.PcdBtRfKillGpio - gBoardModuleTokenSpaceGuid.PcdWhlErbRtd3TableEnable - gBoardModuleTokenSpaceGuid.PcdTypeCPortsSupported - gBoardModuleTokenSpaceGuid.PcdMipiCamSensor - gBoardModuleTokenSpaceGuid.PcdH8S2113SIO - gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM - gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO - gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON - gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable - gBoardModuleTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdConvertableDockSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcRuntimeSciPin + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery1Control + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRealBattery2Control + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDimmPopulationError + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBtIrqGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBtRfKillGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWhlErbRtd3TableEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTypeCPortsSupported + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamSensor + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdH8S2113SIO + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FCOM + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FSIO + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdNCT6776FHWMON + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioTier2WakeEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate =20 [Sources] PolicyInitDxe.c diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/WhiskeylakeOp= enBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.= inf index 143bb89c63..9f45d6ca4b 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePl= atformHookLib/BasePlatformHookLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePl= atformHookLib/BasePlatformHookLib.inf @@ -37,16 +37,16 @@ =20 [Pcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioIndexPort ## CONSU= MES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioDataPort ## CONSU= MES gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSU= MES gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSU= MES =20 [FixedPcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES - gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcIoDecodeRange = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PchLpcIoEnableDecoding = ## CONSUMES =20 [Sources] BasePlatformHookLib.c diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf index 8ad32a55dc..c3fd60007a 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmBoardAcpiEnableLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmBoardAcpiEnableLib.inf @@ -38,7 +38,7 @@ CoffeelakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONS= UMES =20 [Protocols] =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/WhiskeylakeO= penBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLi= b.inf index 27001c3b7f..eaf46ad4ef 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmMultiBoardAcpiSupportLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmMultiBoardAcpiSupportLib.inf @@ -38,7 +38,7 @@ CoffeelakeSiliconPkg/SiPkg.dec =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONS= UMES =20 [Protocols] =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf index 91cc569388..9bf4d127c5 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPostMemLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPostMemLib.inf @@ -42,14 +42,14 @@ GpioTableWhiskeylakeUDdr4Rvp.c =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel =20 - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize =20 - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize =20 gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index 9361c3df3e..4ab80f9eb3 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPreMemLib.inf @@ -38,79 +38,79 @@ PeiBoardInitPreMemLib.c =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort =20 # PCH-LP HSIO PTSS Table - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive =20 =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 =20 # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent =20 =20 =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeO= penBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLi= b.inf index c7330439fb..c043e32638 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPostMemLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPostMemLib.inf @@ -50,152 +50,152 @@ [FixedPcd] =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel =20 - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize =20 - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable - gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardUcmcGpioTableSize =20 #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase # Board Init Table List =20 - gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMe= mSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreM= em + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreM= emSize =20 # WWAN Full Card Power Off and reset pins - gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio - gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio - gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio - gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit =20 # Display DDI - gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES - gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable = ## PRODUCES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize = ## PRODUCES =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl - gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort - gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad - gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive - gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad - gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive =20 # PCIE RTD3 GPIO - gBoardModuleTokenSpaceGuid.PcdRootPortDev - gBoardModuleTokenSpaceGuid.PcdRootPortFunc - gBoardModuleTokenSpaceGuid.PcdRootPortIndex + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex =20 - gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport - gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport - gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive =20 - gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport - gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive =20 - gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport - gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive =20 # CA Vref Configuration - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig =20 # PCIe Clock Info - gBoardModuleTokenSpaceGuid.PcdPcieClock0 - gBoardModuleTokenSpaceGuid.PcdPcieClock1 - gBoardModuleTokenSpaceGuid.PcdPcieClock2 - gBoardModuleTokenSpaceGuid.PcdPcieClock3 - gBoardModuleTokenSpaceGuid.PcdPcieClock4 - gBoardModuleTokenSpaceGuid.PcdPcieClock5 - gBoardModuleTokenSpaceGuid.PcdPcieClock6 - gBoardModuleTokenSpaceGuid.PcdPcieClock7 - gBoardModuleTokenSpaceGuid.PcdPcieClock8 - gBoardModuleTokenSpaceGuid.PcdPcieClock9 - gBoardModuleTokenSpaceGuid.PcdPcieClock10 - gBoardModuleTokenSpaceGuid.PcdPcieClock11 - gBoardModuleTokenSpaceGuid.PcdPcieClock12 - gBoardModuleTokenSpaceGuid.PcdPcieClock13 - gBoardModuleTokenSpaceGuid.PcdPcieClock14 - gBoardModuleTokenSpaceGuid.PcdPcieClock15 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15 =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 =20 # GPIO Group Tier - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 =20 # Pch PmConfig Policy - gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl - gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport - gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport =20 # Misc - gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent - gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable - gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent - gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio - gBoardModuleTokenSpaceGuid.PcdMobileDramPresent - gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable =20 =20 - gBoardModuleTokenSpaceGuid.PcdSpdPresent - gBoardModuleTokenSpaceGuid.PcdBoardRev - gBoardModuleTokenSpaceGuid.PcdBoardBomId - gBoardModuleTokenSpaceGuid.PcdPlatformType - gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType =20 - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2 ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable - gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable # TPM interrupt gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOp= enBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.= inf index 927a89d401..cd0315377a 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPreMemLib.inf @@ -60,225 +60,225 @@ gTcoWdtHobGuid ## CONSUMES =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort =20 # PCH-LP HSIO PTSS Table - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size - gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size =20 # PCH-H HSIO PTSS Table - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size - #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd - gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor - gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap - gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram - gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize - gBoardModuleTokenSpaceGuid.PcdMrcSpdData - gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscUserBd + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompResistor + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcRcompTarget + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMap + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqByteMapSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdData + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdDataSize =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0WakeGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0HoldRstActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0PwrEnableActive =20 =20 # SPD Address Table - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 - gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcSpdAddressTable3 =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port0Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port1Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port2Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port3Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port4Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port5Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port6Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port7Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port8Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port9Afe =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 =20 # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent =20 #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D # Board Init Table List =20 - gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMe= mSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreM= em + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreM= emSize =20 # WWAN Full Card Power Off and reset pins - gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio - gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio - gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio - gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanFullCardPowerOffGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanPerstGpioPolarity =20 # SA Misc Config - gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl - gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved - gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcDqPinsInterleaved + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDdrFreqLimit =20 # Display DDI - gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES - gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTable = ## PRODUCES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSaDisplayConfigTableSize = ## PRODUCES =20 # PEG Reset By GPIO - gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl - gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort - gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad - gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive - gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad - gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetControl + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPegGpioResetSupoort + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioPad + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg0ResetGpioActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioPad + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPeg3ResetGpioActive =20 # PCIE RTD3 GPIO - gBoardModuleTokenSpaceGuid.PcdRootPortDev - gBoardModuleTokenSpaceGuid.PcdRootPortFunc - gBoardModuleTokenSpaceGuid.PcdRootPortIndex + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortDev + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortFunc + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRootPortIndex =20 - gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie0GpioSupport =20 - gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport - gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1GpioSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1WakeGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1HoldRstActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie1PwrEnableActive =20 - gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport - gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2GpioSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2WakeGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2HoldRstActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie2PwrEnableActive =20 - gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport - gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo - gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3GpioSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3WakeGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3HoldRstActive + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableGpioNo + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcie3PwrEnableActive =20 # CA Vref Configuration - gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMrcCaVrefConfig =20 # PCIe Clock Info - gBoardModuleTokenSpaceGuid.PcdPcieClock0 - gBoardModuleTokenSpaceGuid.PcdPcieClock1 - gBoardModuleTokenSpaceGuid.PcdPcieClock2 - gBoardModuleTokenSpaceGuid.PcdPcieClock3 - gBoardModuleTokenSpaceGuid.PcdPcieClock4 - gBoardModuleTokenSpaceGuid.PcdPcieClock5 - gBoardModuleTokenSpaceGuid.PcdPcieClock6 - gBoardModuleTokenSpaceGuid.PcdPcieClock7 - gBoardModuleTokenSpaceGuid.PcdPcieClock8 - gBoardModuleTokenSpaceGuid.PcdPcieClock9 - gBoardModuleTokenSpaceGuid.PcdPcieClock10 - gBoardModuleTokenSpaceGuid.PcdPcieClock11 - gBoardModuleTokenSpaceGuid.PcdPcieClock12 - gBoardModuleTokenSpaceGuid.PcdPcieClock13 - gBoardModuleTokenSpaceGuid.PcdPcieClock14 - gBoardModuleTokenSpaceGuid.PcdPcieClock15 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock3 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock4 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock5 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock6 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock7 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock8 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock9 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock10 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock11 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock12 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock13 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock14 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieClock15 =20 # USB 2.0 Port AFE - gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe - gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port10Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port11Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port12Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port13Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port14Afe + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20Port15Afe =20 # USB 2.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 - gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 =20 # USB 3.0 Port Over Current Pin - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 - gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 =20 # GPIO Group Tier - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 =20 # Pch PmConfig Policy - gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl - gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport - gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0VmRuntimeControl + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm070VSupport + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSlpS0Vm075VSupport =20 # Misc - gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent - gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable - gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent - gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio - gBoardModuleTokenSpaceGuid.PcdMobileDramPresent - gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMobileDramPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable =20 =20 - gBoardModuleTokenSpaceGuid.PcdSpdPresent - gBoardModuleTokenSpaceGuid.PcdBoardRev - gBoardModuleTokenSpaceGuid.PcdBoardBomId - gBoardModuleTokenSpaceGuid.PcdPlatformType - gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSpdPresent + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardRev + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardBomId + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPlatformType + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDualDimmPerChannelBoardType =20 gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable - gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround ## PRODUCES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround ## PROD= UCES gSiPkgTokenSpaceGuid.PcdTcoBaseAddress =20 =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhiskeylakeOpen= BoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf index 079fb70ecb..d66290e79b 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPla= tformHookLib/PeiPlatformHooklib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPla= tformHookLib/PeiPlatformHooklib.inf @@ -40,45 +40,45 @@ CoffeelakeSiliconPkg/SiPkg.dec =20 [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2 ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2 ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size ## CONSU= MES - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel ## CONSU= MES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdLpcSioConfigDefaultPort = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdSioBaseAddress = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdDebugUsbUartEnable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdMipiCamGpioEnable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableSize = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTable2Size = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTableSize = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioExpanderTable2Size = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableTouchPanel = ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem - gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMem + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMe= mSize + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreM= em + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreM= emSize =20 # GPIO Group Tier - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw0 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw1 = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdGpioGroupToGpeDw2 = ## CONSUMES =20 # Misc - gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIoExpanderPresent = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPc8374SioKbcPresent = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdOddPowerInitEnable = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdIvCamInitPresent = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdRecoveryModeGpio = ## CONSUMES + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdCpuVboostEnable = ## CONSUMES =20 - gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio - gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable - gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanBbrstGpio + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdPcieWwanEnable + gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdWwanResetWorkaround =20 [Sources] PeiPlatformHooklib.c --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48541): https://edk2.groups.io/g/devel/message/48541 Mute This Topic: https://groups.io/mt/34439449/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48542+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48542+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511841; cv=none; d=zoho.com; s=zohoarc; b=n+XrCUYsaWA+z/dBmq12alMe7BD3+TkvJD0/RGk5fINBO7o2MjvJhPn1HQbPGRO9+S//jyb/Fxb152ZTKRXXyqOirgPxmhn6x5C1xu9qaCvWo0EipEr7h04rBG8+tqeS5luHawg4HnvoJsJps6DssuFgP0IFSWypyH/p2E3Cock= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511841; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=+VTi4l8ZPbaIG+ZGE4az4/62ikXgedpp7/Eq3vbiJ48=; b=NQagrs6b/vKwyhiPuAlAJZyxvhETBkghe/MnOyIV+lpc0/zEKuoXaXjfIPpHo/lcP3b1eIUMzEE5CtVvo/Z2ImYAHNFRhXSFPGu/hRv71ki7GBHm6rEA/J5+ARv57CEsaaTvOzr2apGLGyUGQUO2gaYiQdeW8LQgCkLZp2f2IZA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48542+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511841061941.4586591927971; Mon, 7 Oct 2019 22:17:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id OWJRYY1788612xYzw2aZuLmB; Mon, 07 Oct 2019 22:17:20 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:19 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297382" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:19 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Agyeman Prince , Wei David Y Subject: [edk2-devel] [edk2-platforms][PATCH V1 14/17] SimicsOpenBoardPkg/BoardX58Ich10: Relocate DSC includes Date: Mon, 7 Oct 2019 22:16:42 -0700 Message-Id: <20191008051645.22052-15-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: jxvxYGLDHHoURlLxpntp6102x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511840; bh=Ykmn5PqpH3GzZr2V/NtXeuTWHAUh4yS0TLE95e4RZGE=; h=Cc:Date:From:Reply-To:Subject:To; b=oxxRovBoVNtJYVsax8YlICWM2UNsnO4OH0Z6IY4V/CdDardfke5sD2on1fI4SqVK3dT 4vaxFGAz+lsw1aCH3J+n3wj+dik7CQPfcKU+kVatkf8WowzYTZQKiSxWIOAUXwMRpysfT Df3AKfdo3/CEEivsWxrCmje5apMRjaM7DZk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This change moves the following DSC file includes to the top of the OpenBoardPkg.dsc file. This is to improve visibility and align placement of the include with other board DSC files. * OpenBoardPkgConfig.dsc * OpenBoardPkgPcd.dsc * CorePeiLib.dsc * CoreDxeLib.dsc Cc: Agyeman Prince Cc: Wei David Y Signed-off-by: Michael Kubacki --- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 21 ++++= +++------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.d= sc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc index 59e13154a7..be29737c16 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc @@ -39,7 +39,11 @@ DEFINE NETWORK_TLS_ENABLE =3D FALSE DEFINE NETWORK_ISCSI_ENABLE =3D FALSE DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE + + !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgConfig.dsc + !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgPcd.dsc !include NetworkPkg/NetworkDefines.dsc.inc + ##########################################################################= ###### # # SKU Identification section - list of all SKU IDs supported by this Platf= orm. @@ -54,12 +58,9 @@ # ##########################################################################= ###### =20 -[PcdsFeatureFlag] - # - # Platform On/Off features are defined here - # - !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgConfig.dsc !include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc + !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc + !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc !include $(PCH_PKG)/IchCommonLib.dsc =20 [LibraryClasses] @@ -76,17 +77,13 @@ SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/Si= liconPolicyInitLib.inf SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLi= b/SiliconPolicyUpdateLib.inf PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/Pci= SegmentInfoLibSimple.inf - - !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc - S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib= .inf LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf + [LibraryClasses.common.SEC] ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf =20 -[LibraryClasses.common.PEI_CORE] - [LibraryClasses.common.PEIM] PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -97,16 +94,12 @@ !endif TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf =20 - !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc - [LibraryClasses.common.DXE_DRIVER] PlatformBootManagerLib|$(BOARD_PKG)/Library/PlatformBootManagerLib/Platf= ormBootManagerLib.inf =20 [LibraryClasses.common.DXE_SMM_DRIVER] SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCom= monLib.inf =20 - !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgPcd.dsc - [Components.IA32] $(BOARD_PKG)/SecCore/SecMain.inf { --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48542): https://edk2.groups.io/g/devel/message/48542 Mute This Topic: https://groups.io/mt/34439450/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48543+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48543+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511841; cv=none; d=zoho.com; s=zohoarc; b=oiOkXEWpHvJr/RW/ZuhqwF0boUJQIfs56OKgyCWDK3ncak5Abru5VJPzzTmFhZi0AbqqkOLgVTFJjlCuhmaNo/GHf2wZzFqEgElnP0mJF5Eh1Z7xgSbVjtrUIar4ofY6lswSTIwiV/3mvwuhEtzc+gPOpKoraZCSyo6PreQULYE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511841; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=vMuzdzAKIgh61rHoBQkWl1Zt7NRbFvCuIO/jH15mD0I=; b=dsrdhtnx68ABnNn7VZIDgSFvxgWX/j3iZDAJVc6TX6H357mChok0y08GgqAmQDjNVaUrqEJGZ/be8L8g4IrVZXxVzrA01uqcVa3Op/u9zgtg33QwkK27tWajooFDVt2uMLjD7t1MkSy8UCqQyNOIf88lgKuO1ww8EFkl1RDMbUc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48543+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511841888241.84955146615187; Mon, 7 Oct 2019 22:17:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id J452YY1788612xa82uL7htZW; Mon, 07 Oct 2019 22:17:21 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:20 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:20 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297386" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:20 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Agyeman Prince , Wei David Y Subject: [edk2-devel] [edk2-platforms][PATCH V1 15/17] SimicsOpenBoardPkg/BoardX58Ich10: Remove OpenBoardPkgConfig.dsc Date: Mon, 7 Oct 2019 22:16:43 -0700 Message-Id: <20191008051645.22052-16-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: LtLgxlRV5yHMntveWDsoOp0Hx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511841; bh=/JE7Huz7QKvIG6z1dHa82jB0ODKxjuRu7xFxRxox3Tc=; h=Cc:Date:From:Reply-To:Subject:To; b=tUdgQyYNrnRZ3YgPH/knTprPgZ9F96Poqp6zzOpbnTSy0uI8PIyvQVWQ1d+I9yTTzuW O9paNuZrGLPwM3dj2M4d65FAXH/ajbd5x/oktc0DU+Io4MrTLsXlzvM94ArWQf6E4Lvu4 e8NEt9t6G8VkVwdESDbqp0LgDrE7c1T4zsM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2244 The location for PCD configuration is currently inconsistent in SimicsOpenBoardPkg. A large set of FeaturePCD definitions are in OpenBoardPkgConfig.dsc while other PCD definitions (including FeaturePCD) are located in OpenBoardPkgPcd.dsc. This change consolidates PCD configuration for the BoardX58Ich10 board to OpenBoardPkgPcd.dsc and removes OpenBoardPkgConfig.dsc. Cc: Agyeman Prince Cc: Wei David Y Signed-off-by: Michael Kubacki --- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | = 1 - Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.dsc | 5= 6 -------------------- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc | 4= 3 +++++++++++++++ 3 files changed, 43 insertions(+), 57 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.d= sc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc index be29737c16..40f864ae17 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc @@ -40,7 +40,6 @@ DEFINE NETWORK_ISCSI_ENABLE =3D FALSE DEFINE NETWORK_ALLOW_HTTP_CONNECTIONS =3D TRUE =20 - !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgConfig.dsc !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgPcd.dsc !include NetworkPkg/NetworkDefines.dsc.inc =20 diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgCo= nfig.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConf= ig.dsc deleted file mode 100644 index 75de60e5bc..0000000000 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.dsc +++ /dev/null @@ -1,56 +0,0 @@ -## @file -# -# Copyright (c) 2019 Intel Corporation. All rights reserved.
-# -# SPDX-License-Identifier: BSD-2-Clause-Patent -# -## - -# -# TRUE is ENABLE. FALSE is DISABLE. -# - -[PcdsFixedAtBuild] - gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 - -[PcdsFeatureFlag] - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 - gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE -!endif - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE - gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE -!endif - - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif - - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE - - gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE - gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE - diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPc= d.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc index 3bf10ee524..ad5e0c5a38 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc @@ -11,7 +11,50 @@ # Pcd Section - list of all EDK II PCD Entries defined by this Platform # ##########################################################################= ###### +[PcdsFixedAtBuild] + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + [PcdsFeatureFlag.common] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + !if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + + gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + !if $(TARGET) =3D=3D RELEASE gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE !else --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48543): https://edk2.groups.io/g/devel/message/48543 Mute This Topic: https://groups.io/mt/34439451/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48544+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48544+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511842; cv=none; d=zoho.com; s=zohoarc; b=Qk8H336IF/CALLCIp3lAsvWpsAWEzVhkxuBBf3Oqjyh5we/80u7iIvhWM+tSQGd2PFwCB+PVxGbMzUISYosiknUvWkk07X6kxaImAYu9zLvI42p9K5zzdqbN3ShaJhW1jLgnOYdnMIhsFFJCJ9DMze4eFxpFIdaaOpU3dHK1F/E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511842; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=+1pjn4fx6TWsCZtRiqvKg3fevakUjnZ6N/qTNkKZtrU=; b=PJVupM+ndYdMX9YP/hPbbw4PT7PqFseN27KCmCilVtMgFY35D+ocVS9dCxxdKnz/qO2Uan/Lys6+072DMrmHxCPCKDUPmVQqVBDgyi+/zPRJtRluJGylqD+zYCR7M6NyyyctFBi25dd2HAdZYryHQuSerro4wWc8RInpnMqEn8Y= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48544+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511842850870.3447731448451; Mon, 7 Oct 2019 22:17:22 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id IaHmYY1788612xuFJ63WwR8p; Mon, 07 Oct 2019 22:17:22 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:21 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297390" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:21 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Agyeman Prince , Wei David Y Subject: [edk2-devel] [edk2-platforms][PATCH V1 16/17] SimicsOpenBoardPkg/BoardX58Ich10: DSC cleanup Date: Mon, 7 Oct 2019 22:16:44 -0700 Message-Id: <20191008051645.22052-17-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: tKIPbMs0HJrNvyhE0G56v9Nnx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511842; bh=nX3qOQie3oWVn9zhawPKOWJElNKykMMg0qNpObj+xrA=; h=Cc:Date:From:Reply-To:Subject:To; b=Sk0I3cY983B1pq2Q9qUuL4TnKqzJZCrJrznSUO+Itd5xApzT53xDl91RlEVh9Ivaaen 1wxT5QunaFtVqms5lE7sK02959nB6fFjbjJ+cHvfhWLgMOLiu37FRaJ7hoLi5m2+haRyX lc9MY5mgTDCN+n50180gN7vUVqmgMQV/jNc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2244 This change refactors OpenBoardPkg.dsc and OpenBoardPkgPcd.dsc to consolidate redundant sections and better group file content to improve maintainability and readability. The same pattern made in this change for BoardX58Ich10 is being applied to all existing board packages in Platform/Intel to improve overall consistency. Cc: Agyeman Prince Cc: Wei David Y Signed-off-by: Michael Kubacki --- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc | 282 = +++++++------ Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc | 418 = +++++++++----------- 2 files changed, 361 insertions(+), 339 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.d= sc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc index 40f864ae17..4f8ab4170d 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc @@ -1,6 +1,7 @@ ## @file +# The main build description file for the X58Ich10 board. # -# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# Copyright (c) 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -33,7 +34,7 @@ DEFINE SMM_REQUIRE =3D TRUE =20 # - #PLATFORMX64_ENABLE is set to TRUE when PEI is IA32 and DXE is X64 platf= orm + # PLATFORMX64_ENABLE is set to TRUE when PEI is IA32 and DXE is X64 plat= form # DEFINE PLATFORMX64_ENABLE =3D TRUE DEFINE NETWORK_TLS_ENABLE =3D FALSE @@ -45,7 +46,7 @@ =20 ##########################################################################= ###### # -# SKU Identification section - list of all SKU IDs supported by this Platf= orm. +# SKU Identification section - list of all SKU IDs supported by this board. # ##########################################################################= ###### [SkuIds] @@ -53,173 +54,232 @@ =20 ##########################################################################= ###### # -# Library Class section - list of all Library Classes needed by this Platf= orm. +# Includes section - other DSC file contents included for this board build. # ##########################################################################= ###### =20 - !include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc - !include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc - !include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc - !include $(PCH_PKG)/IchCommonLib.dsc +####################################### +# Library Includes +####################################### +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc +!include $(PCH_PKG)/IchCommonLib.dsc + +####################################### +# Component Includes +####################################### +[Components.IA32] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc +!include $(SKT_PKG)/SktPkgPei.dsc + +[Components.X64] +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc +!include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc + +####################################### +# Build Option Includes +####################################### +!include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgBuildOption.dsc + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this board. +# +##########################################################################= ###### =20 [LibraryClasses] - ReportFvLib|$(BOARD_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf + ####################################### + # Edk2 Packages + ####################################### BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf + CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/C= puExceptionHandlerLibNull.inf + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf + + ##################################### + # Platform Package + ##################################### + AslUpdateLib|$(PLATFORM_PACKAGE)/Acpi/Library/DxeAslUpdateLib/DxeAslUpda= teLib.inf + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf + + ####################################### + # Board Package + ####################################### + DxeLoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/DxeLoadLinuxLib.inf + LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf NvVarsFileLib|$(BOARD_PKG)/Library/NvVarsFileLib/NvVarsFileLib.inf + ReportFvLib|$(BOARD_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf SerializeVariablesLib|$(BOARD_PKG)/Library/SerializeVariablesLib/Seriali= zeVariablesLib.inf - DxeLoadLinuxLib|$(BOARD_PKG)/Library/LoadLinuxLib/DxeLoadLinuxLib.inf - CpuExceptionHandlerLib|MdeModulePkg/Library/CpuExceptionHandlerLibNull/C= puExceptionHandlerLibNull.inf - - TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/Test= PointCheckLibNull.inf - BoardInitLib|MinPlatformPkg/PlatformInit/Library/BoardInitLibNull/BoardI= nitLibNull.inf SiliconPolicyInitLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyInitLib/Si= liconPolicyInitLib.inf SiliconPolicyUpdateLib|$(BOARD_PKG)/Policy/Library/SiliconPolicyUpdateLi= b/SiliconPolicyUpdateLib.inf - PciSegmentInfoLib|MinPlatformPkg/Pci/Library/PciSegmentInfoLibSimple/Pci= SegmentInfoLibSimple.inf - S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf - AslUpdateLib|MinPlatformPkg/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib= .inf - LogoLib|$(BOARD_PKG)/Library/DxeLogoLib/DxeLogoLib.inf =20 [LibraryClasses.common.SEC] + ####################################### + # Edk2 Packages + ####################################### ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf =20 [LibraryClasses.common.PEIM] + ####################################### + # Edk2 Packages + ####################################### PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf =20 -[LibraryClasses.IA32] + ##################################### + # Platform Package + ##################################### !if $(TARGET) =3D=3D DEBUG - TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestP= ointCheckLib.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf !endif - TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf =20 [LibraryClasses.common.DXE_DRIVER] + ####################################### + # Board Package + ####################################### PlatformBootManagerLib|$(BOARD_PKG)/Library/PlatformBootManagerLib/Platf= ormBootManagerLib.inf =20 [LibraryClasses.common.DXE_SMM_DRIVER] + ####################################### + # Silicon Initialization Package + ####################################### SpiFlashCommonLib|$(PCH_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCom= monLib.inf =20 [Components.IA32] - $(BOARD_PKG)/SecCore/SecMain.inf { - - NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf - } - !include $(SKT_PKG)/SktPkgPei.dsc - !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc - - $(BOARD_PKG)/SimicsPei/SimicsPei.inf { - - PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf - } -# S3 SMM driver -# UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + ####################################### + # Edk2 Packages + ####################################### + # S3 SMM driver + # @todo: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf { LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf } =20 + ####################################### + # Silicon Initialization Package + ####################################### !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE $(SKT_PKG)/Smm/Access/SmmAccessPei.inf { PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf } !endif - $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf =20 - MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + ##################################### + # Platform Package + ##################################### + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoar= dInitPreMemLib.inf } - MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf { + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { BoardInitLib|$(BOARD_PKG)/$(BOARD_NAME)/Library/BoardInitLib/PeiBoar= dInitPostMemLib.inf } - MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf - MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf + + ####################################### + # Board Package + ####################################### + $(BOARD_PKG)/SecCore/SecMain.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompre= ssLib.inf + } + + $(BOARD_PKG)/SimicsPei/SimicsPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } =20 [Components.X64] - !include MinPlatformPkg/Include/Dsc/CoreDxeInclude.dsc - !include AdvancedFeaturePkg/Include/Dsc/CoreAdvancedDxeInclude.dsc - - MdeModulePkg/Universal/EbcDxe/EbcDxe.inf - - MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf - # - # ISA Support - # - $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf - MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf - - $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf - $(BOARD_PKG)/AcpiTables/AcpiTables.inf - # - # Video support - # - $(BOARD_PKG)/SimicsVideoDxe/SimicsVideoDxe.inf - - MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf - MinPlatformPkg/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf - $(BOARD_PKG)/SimicsDxe/SimicsDxe.inf - MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf - MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf - - SimicsIch10BinPkg/UndiBinary/UndiDxe.inf - - # - # Shell - # - ShellPkg/Application/Shell/Shell.inf { - - gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE - - NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma= ndsLib.inf - NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma= ndsLib.inf - NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma= ndsLib.inf - NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com= mandsLib.inf - NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1C= ommandsLib.inf - NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma= ndsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C= ommandsLib.inf - NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C= ommandsLib.inf - ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand= Lib.inf - HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePars= ingLib.inf - BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg= CommandLib.inf - ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib= .inf - ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf - } - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf - $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf - UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf - $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf - MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf - UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf - MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf { - - LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf - } -!endif - MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + ####################################### + # Edk2 Packages + ####################################### MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf { PciHostBridgeLib|$(BOARD_PKG)/Library/PciHostBridgeLib/PciHostBridge= Lib.inf } - MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf - - UefiCpuPkg/CpuDxe/CpuDxe.inf - MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - MdeModulePkg/Universal/PrintDxe/PrintDxe.inf MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf - # - # ACPI Support - # MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf - $(BOARD_PKG)/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf { + + LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf + } + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +!endif + UefiCpuPkg/CpuDxe/CpuDxe.inf =20 + ShellPkg/Application/Shell/Shell.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2= CommandsLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLi= b.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + } + + ####################################### + # Silicon Initialization Package + ####################################### + SimicsIch10BinPkg/UndiBinary/UndiDxe.inf +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(PCH_PKG)/SmmControl/RuntimeDxe/SmmControl2Dxe.inf + $(PCH_PKG)/Spi/Smm/PchSpiSmm.inf + $(SKT_PKG)/Smm/Access/SmmAccess2Dxe.inf +!endif + + ##################################### + # Platform Package + ##################################### + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf +!endif + + ####################################### + # Advanced Feature Package + ####################################### !if gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable =3D=3D TRUE AdvancedFeaturePkg/Smbios/SmbiosBasicDxe/SmbiosBasicDxe.inf !endif =20 - !include $(BOARD_PKG)/$(BOARD_NAME)/OpenBoardPkgBuildOption.dsc + ####################################### + # Board Package + ####################################### + $(BOARD_PKG)/AcpiTables/AcpiTables.inf + $(BOARD_PKG)/AcpiTables/MinPlatformAcpiTables/AcpiPlatform.inf + $(BOARD_PKG)/LegacySioDxe/LegacySioDxe.inf + $(BOARD_PKG)/SimicsDxe/SimicsDxe.inf + $(BOARD_PKG)/SimicsVideoDxe/SimicsVideoDxe.inf + $(BOARD_PKG)/SmbiosPlatformDxe/SmbiosPlatformDxe.inf diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPc= d.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc index ad5e0c5a38..29cd2455f6 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc @@ -1,4 +1,5 @@ ## @file +# PCD configuration build description file for the X58Ich10 board. # # Copyright (c) 2019 Intel Corporation. All rights reserved.
# @@ -8,18 +9,53 @@ =20 ##########################################################################= ###### # -# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# Pcd Section - list of all PCD Entries used by this board. # ##########################################################################= ###### -[PcdsFixedAtBuild] +[PcdsFixedAtBuild.common] + ###################################### + # Key Boot Stage and FSP configuration + ###################################### + # + # Please select the Boot Stage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 =20 [PcdsFeatureFlag.common] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE +!if $(TARGET) =3D=3D RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE - gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE =20 !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE @@ -44,231 +80,54 @@ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE !endif =20 - !if $(TARGET) =3D=3D DEBUG - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE - !else - gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE - !endif +!if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE +!else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE +!endif =20 - gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + ###################################### + # Silicon Configuration + ###################################### +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire|TRUE +!endif =20 + ###################################### + # Advanced Feature Configuration + ###################################### gAdvancedFeaturePkgTokenSpaceGuid.PcdNetworkEnable|TRUE gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosEnable|TRUE =20 -!if $(TARGET) =3D=3D RELEASE - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE -!else - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE -!endif - # Server doesn't support capsle update on Reset. - gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE - gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE - - -#S3 add - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE -#S3 add - - ## This PCD specified whether ACPI SDT protocol is installed. - gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE - [PcdsFeatureFlag.X64] + ###################################### + # Edk2 Configuration + ###################################### gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard|FALSE =20 -[PcdsFeatureFlag] - gEfiMdeModulePkgTokenSpaceGuid.PcdBrowerGrayOutReadOnlyMenu|TRUE - -[PcdsDynamicExDefault] - [PcdsFixedAtBuild.common] - gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|TRUE -!if $(TARGET) =3D=3D "RELEASE" - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 -!else - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 -!endif - gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 - gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 -#S3 modified - gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE -#S3 modified - - gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 - gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333 - gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000 - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000 - - ## Specifies delay value in microseconds after sending out an INIT IPI. - # @Prompt Configure delay value after send an INIT IPI - gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 - - ## Specifies max supported number of Logical Processors. - # @Prompt Configure max supported number of Logical Processorss - gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 - gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 -!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE - gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 -!endif - - ## Defines the ACPI register set base address. - # The invalid 0xFFFF is as its default value. It must be configured to = the real value. - # @Prompt ACPI Timer IO Port Address - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0400 - - ## Defines the PCI Bus Number of the PCI device that contains the BAR an= d Enable for ACPI hardware registers. - # @Prompt ACPI Hardware PCI Bus Number - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00 - - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002 + ###################################### + # Edk2 Configuration + ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x20091013 - - ## Defines the PCI Device Number of the PCI device that contains the BAR= and Enable for ACPI hardware registers. - # The invalid 0xFF is as its default value. It must be configured to th= e real value. - # @Prompt ACPI Hardware PCI Device Number - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F - - ## Defines the PCI Function Number of the PCI device that contains the B= AR and Enable for ACPI hardware registers. - # The invalid 0xFF is as its default value. It must be configured to th= e real value. - # @Prompt ACPI Hardware PCI Function Number - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x00 - - ## Defines the PCI Register Offset of the PCI device that contains the E= nable for ACPI hardware registers. - # The invalid 0xFFFF is as its default value. It must be configured to = the real value. - # @Prompt ACPI Hardware PCI Register Offset - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044 - - ## Defines the bit mask that must be set to enable the APIC hardware reg= ister BAR. - # @Prompt ACPI Hardware PCI Bar Enable BitMask - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80 - - ## Defines the PCI Register Offset of the PCI device that contains the B= AR for ACPI hardware registers. - # The invalid 0xFFFF is as its default value. It must be configured to = the real value. - # @Prompt ACPI Hardware PCI Bar Register Offset - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040 - - ## Defines the offset to the 32-bit Timer Value register that resides wi= thin the ACPI BAR. - # @Prompt Offset to 32-bit Timer register in ACPI BAR - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008 - - ## Defines the bit mask to retrieve ACPI IO Port Base Address - # @Prompt ACPI IO Port Base Address Mask - gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask |0xFFFC - + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002 + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x10000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0xc000 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x1700000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400 + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000 gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE - - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|4 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128 - gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4 - gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 - gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 - gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x0 - gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0003 - gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x400 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x404 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x450 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x408 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x420 - gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 - -[PcdsFixedAtBuild.X64] - gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8 - gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015 - gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099 - # Change PcdBootManagerMenuFile to UiApp -## - - gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } - - gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE - - [PcdsPatchableInModule.common] - -!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 -!endif - - gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 - - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 - gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 - - gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE - - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x0 - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x0 - -[PcdsDynamicExDefault.common.DEFAULT] - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000 - gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0 - -[PcdsDynamicExHii.common.DEFAULT] - gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|50 # Variable: L"Timeout" - gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" - - -[PcdsDynamicExDefault] - - gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F - - gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36 - - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54, 0x= 45, 0x4C, 0x20} - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20465730303632= 53 - -[PcdsDynamicExDefault.X64] - - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 - gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 - - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 - - gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800 - gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 - - gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 - -[PcdsFeatureFlag] - gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE - gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE - #gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE - #gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE - -!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE - gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire|TRUE -!endif - -[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 - gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400 - gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xc000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0xc000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x2000 - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x10000 - gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 - # DEBUG_INIT 0x00000001 // Initialization # DEBUG_WARN 0x00000002 // Warnings # DEBUG_LOAD 0x00000004 // Load events @@ -291,34 +150,137 @@ # DEBUG_ERROR 0x80000000 // Error gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdePkgTokenSpaceGuid.PcdFSBClock|133333333 + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0 +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 +!endif +!if $(TARGET) =3D=3D "RELEASE" + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03 +!else + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask| 0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x0040 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber| 0x00 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber| 0x1F + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x0044 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber| 0x00 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x0400 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x0008 + gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10 + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x4000 =20 - # - # PCI feature overrides. - # - gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE - -##########################################################################= ###### -# -# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Pla= tform -# -##########################################################################= ###### + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x420 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x404 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x400 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x450 + gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x408 + gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5 + gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0003 + gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x0 + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|128 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|4 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|4 + gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000 + +[PcdsFixedAtBuild.X64] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0x0eB8 + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2015 + gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|2099 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE + + [PcdsPatchableInModule.common] + ###################################### + # Edk2 Configuration + ###################################### +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + gPcAtChipsetPkgTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000 + + ###################################### + # Platform Configuration + ###################################### + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x0 + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x0 =20 [PcdsDynamicDefault] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 =20 - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0 + ###################################### + # Board Configuration + ###################################### gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0 gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0 gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0 gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0 gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0 gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x800000000 + gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0 =20 + ###################################### + # Advanced Feature Configuration + ###################################### + gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"2= 019-08-09" gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosVersion|"Ver.1= .0.0" gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType1StringProductName|"QSP U= EFI BIOS" gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType2StringProductName|"QSP U= EFI BIOS" - gAdvancedFeaturePkgTokenSpaceGuid.PcdSmbiosType0StringBiosReleaseDate|"2= 019-08-09" =20 - gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE +[PcdsDynamicExDefault] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|{0x49, 0x4E, 0x54, 0x= 45, 0x4C, 0x20} + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20465730303632= 53 + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L""|VOID*|36 + gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1F + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|30000 + gUefiCpuPkgTokenSpaceGuid.PcdCpuS3DataAddress|0 + +[PcdsDynamicExDefault.X64] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|100 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|31 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|600 + gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1 + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1 + gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugDataAddress|0 + +[PcdsDynamicExHii.common.DEFAULT] + ###################################### + # Edk2 Configuration + ###################################### + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|50 # Variable: L"Timeout" + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#48544): https://edk2.groups.io/g/devel/message/48544 Mute This Topic: https://groups.io/mt/34439453/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Mar 29 13:52:07 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+48545+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48545+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1570511843; cv=none; d=zoho.com; s=zohoarc; b=OTn+p/oHouoK3U2gytU8iNNF4WgmtdHdvvDCpMMDHEMh++c8cwB8tG/7MDOsZm1tqR+gIdl211D7JyfiI7nT5Hmw7OfMeqPsa2KIL0abp/KhW0DCbwgkCp2dMS4tPw2+43pziVtmKNSL/xP/lygIQMw/qITnlcShgU/4Y7EXgAw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1570511843; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=y0bf/qp9rWsiIhcxJ03+LiwlSHnSrG+xXv9BcTsy/tk=; b=O/enrD2AsfnhMwxCZkBB84hi+XyPhwbkCvOZSgixoWDnit3n3qs3BZ0GyWtvVNS5Y44BcxwvFsWzO1R5vH5reKaluosswa2ZxL1DuAGJCloNXNThbgvmHH7HvtMNiE+AF6Ep+XVu/2A3BNgoI2ETQKFfo+IP+ObaF8EM5verwOY= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+48545+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1570511843681838.4107795560689; Mon, 7 Oct 2019 22:17:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4JaeYY1788612xPv9jJwOCSd; Mon, 07 Oct 2019 22:17:23 -0700 X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 07 Oct 2019 22:17:22 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Oct 2019 22:17:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,269,1566889200"; d="scan'208";a="205297397" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga002.jf.intel.com with ESMTP; 07 Oct 2019 22:17:22 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Agyeman Prince , Wei David Y Subject: [edk2-devel] [edk2-platforms][PATCH V1 17/17] SimicsOpenBoardPkg: Assign unique token namespace Date: Mon, 7 Oct 2019 22:16:45 -0700 Message-Id: <20191008051645.22052-18-michael.a.kubacki@intel.com> In-Reply-To: <20191008051645.22052-1-michael.a.kubacki@intel.com> References: <20191008051645.22052-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com X-Gm-Message-State: NWDk11u1GeayjHTykvH4qCiyx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1570511843; bh=ivbfmvXfjvO1Lsj02celMU2PUvEfVdt4Hcvw9RoHENw=; h=Cc:Date:From:Reply-To:Subject:To; b=GdQfqpYiCzmlRt31x8yRO370cN1GPf6jdzeNowT62GdGavXjB7hhqnzXzSU33aiuDx5 4wEl0SF329PHp5rrJdwOgHIf68DARYjLIWBkRLpmzg6eFxPfd4X3UFhzibx2XghF7ZKk8 R3EvbIlCYHQ21Qtw8R4ifZuUA4JHAU3/ylw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2249 PCDs declared in the SimicsOpenBoardPkg currently use the GUID gBoardModuleTokenSpaceGuid. The same name is used in other board packages and a package has been added called BoardModulePkg so this name is now misleading. This change assigns a unique GUID value and a name specific to the package to provide differentiation from PCDs in other board packages. Cc: Agyeman Prince Cc: Wei David Y Signed-off-by: Michael Kubacki --- Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec = | 72 ++++++++++---------- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc = | 14 ++-- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf = | 12 ++-- Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBridgeLi= b.inf | 14 ++-- Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvLib.in= f | 10 +-- Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/PlatformB= ootManagerLib.inf | 10 +-- Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf = | 18 ++--- Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf = | 36 +++++----- Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf = | 2 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.inc = | 6 +- Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc = | 16 ++--- 11 files changed, 105 insertions(+), 105 deletions(-) diff --git a/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec b/Platform/= Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec index 40487820fa..421c464023 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec +++ b/Platform/Intel/SimicsOpenBoardPkg/OpenBoardPkg.dec @@ -17,57 +17,57 @@ Include =20 [Guids] - gBoardModuleTokenSpaceGuid =3D {0xeed35f57, 0x4ff2, 0x4244, {0xb8, 0x3a= , 0xea, 0x71, 0x5f, 0xd3, 0x59, 0xa5}} + gSimicsOpenBoardPkgTokenSpaceGuid =3D {0x75fd61da, 0x3931, 0x49aa, {0x8= f, 0x11, 0x18, 0x25, 0xf6, 0x31, 0x21, 0xd2}} gSimicsBoardConfigGuid =3D {0xeed35f57, 0x4ff2, 0x4244, {0xb8, 0x3a, 0x= ea, 0x71, 0x5f, 0xd3, 0x59, 0xa5}} =20 [PcdsFixedAtBuild] - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase|0x0|UINT32|0 - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize|0x0|UINT32|1 - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase|0x0|UINT32|0x15 - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize|0x0|UINT32|0x16 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase|0x0|UINT32|0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize|0x0|UINT32|1 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase|0x0|UINT32|0x15 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize|0x0|UINT32|0x16 =20 #TODO: Remove these two when we integrate new PlatformPei - gBoardModuleTokenSpaceGuid.PcdSimicsMemFvBase|0x00800000|UINT32|2 - gBoardModuleTokenSpaceGuid.PcdSimicsMemFvSize|0x00500000|UINT32|3 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsMemFvBase|0x00800000|UINT32|2 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsMemFvSize|0x00500000|UINT32|3 =20 - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase|0x0|UINT3= 2|0x8 - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize|0x0|UINT3= 2|0x9 - gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareFdSize|0x0|UINT32|0xa - gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareBlockSize|0|UINT32|0xb - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase|0x0|UINT3= 2|0xc - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase|0x0|UINT3= 2|0xd - gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase|0x0|UIN= T32|0xe - gBoardModuleTokenSpaceGuid.PcdSimicsFdBaseAddress|0x0|UINT32|0xf - gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase|0x0|UINT32|0x11 - gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesSize|0x0|UINT32|0x12 - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|0x0|UINT32|0x13 - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize|0x0|UINT32|0x14 - gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase|0x0|UINT32|0x18 - gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageSize|0x0|UINT32|0x19 - gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0= x1a - gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd|0x0|UINT32|0= x1f + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase|0x= 0|UINT32|0x8 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize|0x= 0|UINT32|0x9 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareFdSize|0x0|UINT32|0xa + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareBlockSize|0|UINT32|0xb + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase|0x= 0|UINT32|0xc + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase|0x= 0|UINT32|0xd + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase|= 0x0|UINT32|0xe + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFdBaseAddress|0x0|UINT32|0xf + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase|0x0|UINT32|= 0x11 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesSize|0x0|UINT32|= 0x12 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|0x0|UINT32|= 0x13 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize|0x0|UINT32|= 0x14 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase|0x0|UINT32= |0x18 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize|0x0|UINT32= |0x19 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|U= INT32|0x1a + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd|0x0|U= INT32|0x1f =20 [PcdsDynamic, PcdsDynamicEx] =20 # TODO: investigate whether next two Pcds are needed - gBoardModuleTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|0x28 - gBoardModuleTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0|UINT16|0x1b + gSimicsOpenBoardPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|0x28 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOL= EAN|0x10 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0|UINT1= 6|0x1b =20 ## The IO port aperture shared by all PCI root bridges. # - gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22 - gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23 =20 ## The 32-bit MMIO aperture shared by all PCI root bridges. # - gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24 - gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25 =20 ## The 64-bit MMIO aperture shared by all PCI root bridges. # - gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26 - gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27 =20 [PcdsFixedAtBuild, PcdsDynamic, PcdsDynamicEx, PcdsPatchableInModule] ## Pcd8259LegacyModeMask defines the default mask value for platform. Th= is value is determined

@@ -131,7 +131,7 @@ [PcdsFixedAtBuild, PcdsPatchableInModule] ## FFS filename to find the shell application. # @Prompt FFS Name of Shell Application - gBoardModuleTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, = 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|VOID*|0x= 40000004 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C,= 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|V= OID*|0x40000004 =20 ## ISA Bus features to support DMA, SlaveDMA and ISA Memory.

# BIT0 indicates if DMA is supported
@@ -140,10 +140,10 @@ # Other BITs are reseved and must be zero. # If more than one features are supported, the different BIT will be en= abled at the same time. # @Prompt ISA Bus Features - # @Expression 0x80000002 | (gBoardModuleTokenSpaceGuid.PcdIsaBusSupporte= dFeatures & 0xF8) =3D=3D 0 - gBoardModuleTokenSpaceGuid.PcdIsaBusSupportedFeatures|0x05|UINT8|0x00010= 040 + # @Expression 0x80000002 | (gSimicsOpenBoardPkgTokenSpaceGuid.PcdIsaBusS= upportedFeatures & 0xF8) =3D=3D 0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdIsaBusSupportedFeatures|0x05|UINT8|= 0x00010040 =20 - gBoardModuleTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xB2, 0x7B, 0xBB, = 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }|VOID*|0x= 00010037 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdLogoFile |{ 0x99, 0x8b, 0xB2, 0x7B,= 0xBB, 0x61, 0xD5, 0x11, 0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }|V= OID*|0x00010037 =20 [Protocols] ## diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPc= d.dsc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc index 29cd2455f6..0298e4b12d 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc @@ -235,13 +235,13 @@ ###################################### # Board Configuration ###################################### - gBoardModuleTokenSpaceGuid.PcdPciIoBase|0x0 - gBoardModuleTokenSpaceGuid.PcdPciIoSize|0x0 - gBoardModuleTokenSpaceGuid.PcdPciMmio32Base|0x0 - gBoardModuleTokenSpaceGuid.PcdPciMmio32Size|0x0 - gBoardModuleTokenSpaceGuid.PcdPciMmio64Base|0x0 - gBoardModuleTokenSpaceGuid.PcdPciMmio64Size|0x800000000 - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base|0x0 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size|0x800000000 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId|0 =20 ###################################### # Advanced Feature Configuration diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.f= df b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf index 6c1579bef7..75a99a5270 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf @@ -80,23 +80,23 @@ BlockSize =3D 0x10000 NumBlocks =3D 0xB0 =20 0x000000|0x006000 -gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase|gBoardModuleTokenSpa= ceGuid.PcdSimicsSecPageTablesSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase|gSimicsOpenBo= ardPkgTokenSpaceGuid.PcdSimicsSecPageTablesSize =20 0x006000|0x001000 -gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gBoardModuleTokenSp= aceGuid.PcdSimicsLockBoxStorageSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase|gSimicsOpenB= oardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize =20 0x007000|0x001000 -gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gBoardModuleT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize +gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gSimicsOpenBo= ardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize =20 0x010000|0x008000 -gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gBoardModuleTokenSpa= ceGuid.PcdSimicsSecPeiTempRamSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase|gSimicsOpenBo= ardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize =20 0x020000|0x0E0000 -gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase|gBoardModuleTokenSpaceGui= d.PcdSimicsPeiMemFvSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase|gSimicsOpenBoardPk= gTokenSpaceGuid.PcdSimicsPeiMemFvSize FV =3D FvPreMemory =20 0x100000|0xA00000 -gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase|gBoardModuleTokenSpaceGui= d.PcdSimicsDxeMemFvSize +gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase|gSimicsOpenBoardPk= gTokenSpaceGuid.PcdSimicsDxeMemFvSize FV =3D DXEFV =20 ##########################################################################= ###### diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/Pci= HostBridgeLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridge= Lib/PciHostBridgeLib.inf index e1920bd2ff..372e0c9651 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBri= dgeLib.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PciHostBridgeLib/PciHostBri= dgeLib.inf @@ -41,11 +41,11 @@ PciLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdPciIoBase - gBoardModuleTokenSpaceGuid.PcdPciIoSize - gBoardModuleTokenSpaceGuid.PcdPciMmio32Base - gBoardModuleTokenSpaceGuid.PcdPciMmio32Size - gBoardModuleTokenSpaceGuid.PcdPciMmio64Base - gBoardModuleTokenSpaceGuid.PcdPciMmio64Size - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiRe= portFvLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/Pe= iReportFvLib.inf index bc85420f97..5d2e39532c 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvL= ib.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PeiReportFvLib/PeiReportFvL= ib.inf @@ -48,9 +48,9 @@ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase ## CONSUMES gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize ## CONSUMES - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerL= ib/PlatformBootManagerLib.inf b/Platform/Intel/SimicsOpenBoardPkg/Library/P= latformBootManagerLib/PlatformBootManagerLib.inf index cdb6e242e8..3fb76c3564 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/Plat= formBootManagerLib.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/Library/PlatformBootManagerLib/Plat= formBootManagerLib.inf @@ -50,12 +50,12 @@ LogoLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdEmuVariableEvent - gBoardModuleTokenSpaceGuid.PcdOvmfFlashVariablesEnable - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId + gSimicsOpenBoardPkgTokenSpaceGuid.PcdEmuVariableEvent + gSimicsOpenBoardPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut - gBoardModuleTokenSpaceGuid.PcdShellFile - gBoardModuleTokenSpaceGuid.PcdLogoFile + gSimicsOpenBoardPkgTokenSpaceGuid.PcdShellFile + gSimicsOpenBoardPkgTokenSpaceGuid.PcdLogoFile =20 [Pcd.IA32, Pcd.X64] gEfiMdePkgTokenSpaceGuid.PcdFSBClock diff --git a/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf b/Platfo= rm/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf index b1d319c5ea..61ca2c0613 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SecCore/SecMain.inf @@ -58,16 +58,16 @@ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress - gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize - gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd + gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =20 [FeaturePcd] gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf b/Pl= atform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf index e466d57e4e..9499d2aad5 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsPei/SimicsPei.inf @@ -55,25 +55,25 @@ PcdLib =20 [Pcd] - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvBase - gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize - gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageBase - gBoardModuleTokenSpaceGuid.PcdSimicsLockBoxStorageSize - gBoardModuleTokenSpaceGuid.PcdSimicsSecPageTablesBase - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamBase - gBoardModuleTokenSpaceGuid.PcdSimicsSecPeiTempRamSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsPeiMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsLockBoxStorageSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPageTablesBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsSecPeiTempRamSize gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress - gBoardModuleTokenSpaceGuid.PcdGuidedExtractHandlerTableSize - gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId - gBoardModuleTokenSpaceGuid.PcdPciIoBase - gBoardModuleTokenSpaceGuid.PcdPciIoSize - gBoardModuleTokenSpaceGuid.PcdPciMmio32Base - gBoardModuleTokenSpaceGuid.PcdPciMmio32Size - gBoardModuleTokenSpaceGuid.PcdPciMmio64Base - gBoardModuleTokenSpaceGuid.PcdPciMmio64Size + gSimicsOpenBoardPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoBase + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciIoSize + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Base + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio32Size + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Base + gSimicsOpenBoardPkgTokenSpaceGuid.PcdPciMmio64Size gSimicsX58PkgTokenSpaceGuid.PcdX58TsegMbytes gSimicsX58PkgTokenSpaceGuid.PcdSmmSmramRequire gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize diff --git a/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDx= e.inf b/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf index 002cb56826..e0eee30985 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf +++ b/Platform/Intel/SimicsOpenBoardPkg/SimicsVideoDxe/SimicsVideoDxe.inf @@ -70,5 +70,5 @@ =20 [Pcd] gOptionRomPkgTokenSpaceGuid.PcdDriverSupportedEfiVersion - gBoardModuleTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsX58HostBridgePciDevId gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratch= End.fdf.inc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratc= hEnd.fdf.inc index ae9a625da9..af583ecde6 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf= .inc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf= .inc @@ -45,7 +45,7 @@ # The total size after decompression is (128 + PcdSimicsPeiMemFvSize + 16 + # PcdSimicsDxeMemFvSize). =20 -DEFINE OUTPUT_SIZE =3D (128 + gBoardModuleTokenSpaceGuid.PcdSimicsPeiMemFv= Size + 16 + gBoardModuleTokenSpaceGuid.PcdSimicsDxeMemFvSize) +DEFINE OUTPUT_SIZE =3D (128 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsP= eiMemFvSize + 16 + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvSize) =20 # LzmaCustomDecompressLib uses a constant scratch buffer size of 64KB; see # SCRATCH_BUFFER_REQUEST_SIZE in @@ -58,10 +58,10 @@ DEFINE DECOMP_SCRATCH_SIZE =3D 0x00010000 # # The calculation below mirrors DecompressMemFvs() [SimicsX58Pkg/Sec/SecMa= in.c]. =20 -DEFINE OUTPUT_BASE =3D ($(MEMFD_BASE_ADDRESS) + gBoardMo= duleTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000) +DEFINE OUTPUT_BASE =3D ($(MEMFD_BASE_ADDRESS) + gSimicsO= penBoardPkgTokenSpaceGuid.PcdSimicsDxeMemFvBase + 0x00100000) DEFINE DECOMP_SCRATCH_BASE_UNALIGNED =3D ($(OUTPUT_BASE) + $(OUTPUT_SIZE)) DEFINE DECOMP_SCRATCH_BASE_ALIGNMENT =3D 0x000FFFFF DEFINE DECOMP_SCRATCH_BASE_MASK =3D 0xFFF00000 DEFINE DECOMP_SCRATCH_BASE =3D (($(DECOMP_SCRATCH_BASE_UNALIGNED= ) + $(DECOMP_SCRATCH_BASE_ALIGNMENT)) & $(DECOMP_SCRATCH_BASE_MASK)) =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =3D $(DECO= MP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsDecompressionScratchEnd =3D= $(DECOMP_SCRATCH_BASE) + $(DECOMP_SCRATCH_SIZE) diff --git a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.f= df.inc b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.i= nc index 044129c941..9c2436c3ad 100644 --- a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc +++ b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc @@ -29,20 +29,20 @@ DEFINE SECFV_OFFSET =3D 0x001EC000 DEFINE SECFV_SIZE =3D 0x14000 =20 =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFdBaseAddress =3D $(FW_BASE_AD= DRESS) -SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareFdSize =3D $(FW_SIZE) -SET gBoardModuleTokenSpaceGuid.PcdSimicsFirmwareBlockSize =3D $(BLOCK_SIZE) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFdBaseAddress =3D $(FW_= BASE_ADDRESS) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareFdSize =3D $(FW_= SIZE) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFirmwareBlockSize =3D $(BLO= CK_SIZE) =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase =3D $(F= W_BASE_ADDRESS) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase = =3D $(FW_BASE_ADDRESS) SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0xE000 =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase =3D gBo= ardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase + gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize =3D $(B= LOCK_SIZE) +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase = =3D gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageVariableBase += gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize = =3D $(BLOCK_SIZE) =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase =3D g= BoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase + gBoardModul= eTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBas= e =3D gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogBase= + gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageEventLogSize SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D $(B= LOCK_SIZE) =20 -SET gBoardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase =3D gBo= ardModuleTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase + gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +SET gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwSpareBase = =3D gSimicsOpenBoardPkgTokenSpaceGuid.PcdSimicsFlashNvStorageFtwWorkingBase= + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x100= 00 =20 SET gEfiPchTokenSpaceGuid.PcdFlashAreaBaseAddress =3D 0xFFE00000 --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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