From nobody Mon Feb 9 13:22:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47927+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47927+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1569324921; cv=none; d=zoho.com; s=zohoarc; b=lUs3HhjgQmJm2GOPN6Eyty1q2IWOjV+CK62RVxSX4Cqecv0eddYqg7A6AuQ606k3NokwRFIVeEuNNFoSVBZEH5A2j7+XgUD3YHXXXYe2kKafExpT5Of9EfUbpbKdzDxsJ2CcKjhBb19Icy7fuP7akXl1pwmznF8HSoaZiUKfcHM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1569324921; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=N329VGJwAoeXHJJcnABRbZlwcF/geo4Nv1EQbXgOqmY=; b=XAibyhhd4bKVFRWg/d1PTq0WDd8g9O+K033QVwHosHqbtaWKIhE4nrGG600rh0Op1QldzEm+BgUdAIw44ZoJDyW0AphsyuysE8LGtUtSA60jJSQEjXOzc56D0kAzHVXXLtmw52G/fr7cgRX2AtsFiBHb4egzt5cV0/PF8czgRYM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47927+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1569324921663535.8100127976985; Tue, 24 Sep 2019 04:35:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 8IrYYY1788612xWsJqPZzGTs; Tue, 24 Sep 2019 04:35:21 -0700 X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Tue, 24 Sep 2019 04:35:20 -0700 X-Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.phx2.redhat.com [10.5.11.11]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 2CEB7307D923; Tue, 24 Sep 2019 11:35:20 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-118.rdu2.redhat.com [10.10.120.118]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7C722600CC; Tue, 24 Sep 2019 11:35:17 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Boris Ostrovsky , Brijesh Singh , Igor Mammedov , Jiewen Yao , Joao M Martins , Jordan Justen , Jun Nakajima , Michael Kinney , Paolo Bonzini , Phillip Goerl , Yingwen Chen Subject: [edk2-devel] [PATCH wave 1 03/10] OvmfPkg/IndustryStandard: add MCH_DEFAULT_SMBASE* register macros Date: Tue, 24 Sep 2019 13:34:58 +0200 Message-Id: <20190924113505.27272-4-lersek@redhat.com> In-Reply-To: <20190924113505.27272-1-lersek@redhat.com> References: <20190924113505.27272-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Tue, 24 Sep 2019 11:35:20 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com X-Gm-Message-State: Ip4WqAzzOeucomFGhaxpkOKvx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1569324921; bh=BEgO33/P8i++Cb4v9jR3ARIcC6wwI+2zXZqlLKKS1Qc=; h=Cc:Date:From:Reply-To:Subject:To; b=p0/3ir/1CYmBwlRvPsEQwjS2eo9oiFFvXWckkhbR22jOUT989g1cOOU2ZygKr9fJkZn PECuCMWQl4O8DanuFwhy7BsHXGm1ykeOG3fxi6SLNvZXS7sLthZiqEyTZE2269063HX3A t9/EKNCU6CVlYc+FkNMSoyiOdftPA9CYV78= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" In Intel datasheet 316966-002 (the "q35 spec"), Table 5-1 "DRAM Controller Register Address Map (D0:F0)" leaves the byte register at config space offset 0x9C unused. On QEMU's Q35 board, for detecting the "SMRAM at default SMBASE" feature, firmware is expected to write MCH_DEFAULT_SMBASE_QUERY (0xFF) to offset MCH_DEFAULT_SMBASE_CTL (0x9C), and read back the register. If the value is MCH_DEFAULT_SMBASE_IN_RAM (0x01), then the feature is available, and the range mentioned below is open (accessible to code running outside of SMM). Then, once firmware writes MCH_DEFAULT_SMBASE_LCK (0x02) to the register, the MCH_DEFAULT_SMBASE_SIZE (128KB) range at 0x3_0000 (SMM_DEFAULT_SMBASE) gets closed and locked down, and the register becomes read-only. The area is reopened, and the register becomes read/write, at platform reset. Add the above-listed macros to "Q35MchIch9.h". (There are some other unused offsets in Table 5-1; for example we had scavenged 0x50 for implementing the extended TSEG feature. 0x9C is the first byte-wide register standing in isolation after 0x50.) Cc: Ard Biesheuvel Cc: Boris Ostrovsky Cc: Brijesh Singh Cc: Igor Mammedov Cc: Jiewen Yao Cc: Joao M Martins Cc: Jordan Justen Cc: Jun Nakajima Cc: Michael Kinney Cc: Paolo Bonzini Cc: Phillip Goerl Cc: Yingwen Chen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1512 Signed-off-by: Laszlo Ersek --- OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Includ= e/IndustryStandard/Q35MchIch9.h index 614699ab38f1..eac57b10d77e 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -49,6 +49,12 @@ #define MCH_PAM5 0x95 #define MCH_PAM6 0x96 =20 +#define MCH_DEFAULT_SMBASE_CTL 0x9C +#define MCH_DEFAULT_SMBASE_QUERY 0xFF +#define MCH_DEFAULT_SMBASE_IN_RAM 0x01 +#define MCH_DEFAULT_SMBASE_LCK 0x02 +#define MCH_DEFAULT_SMBASE_SIZE SIZE_128KB + #define MCH_SMRAM 0x9D #define MCH_SMRAM_D_LCK BIT4 #define MCH_SMRAM_G_SMRAME BIT3 --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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