From nobody Sun Feb 8 14:35:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47540+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47540+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865105; cv=none; d=zoho.com; s=zohoarc; b=BJA+bpko325X/anYI4RDdiNZTo2+BuAtfXquTphNbeqtBDjeeD3LhW8rG8VUylhg8uet8ddLTWRO31g/JoHrU+DtyN2oijkpKS/QMlmTe5AZgO5W0tpbxY8+C9H1A+rhrKVxZEIczGMtWLnDP3wAeXj7F4gZ/x94sdeWFZxJiVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865105; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=HbkjHqJKuE1ieMNk1mNJ03mItESCqS47wyCFNQElppU=; b=lqiar8HNf6+xH2oDYGfDZgVvRV5X0huWOm9HvYAomp6pzWTCnJQlIc8wcWutcs8FKstoitI9simpJ5oWr01mFXNlcJMpvJIHfxAqhNKzcfQipl+4SjxznCkPVoxP9Hpxse+yPVN1ATKPA3U03Svz8kfbX3F8v4/P+e0t8o9Hqbg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47540+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865105796998.0343989410969; Wed, 18 Sep 2019 20:51:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id F5HrYY1788612xnWxoBvl5Vi; Wed, 18 Sep 2019 20:51:45 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:44 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pMkj013263 for ; Thu, 19 Sep 2019 03:51:44 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v3vapdarv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:43 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id ED9D14E for ; Thu, 19 Sep 2019 03:51:42 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 2C94E45 for ; Thu, 19 Sep 2019 03:51:41 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 07/14] RiscV/SiFive: Initial version of SiFive U500 platform package Date: Thu, 19 Sep 2019 11:51:24 +0800 Message-Id: <20190919035131.4700-8-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: WhuOu63tKIfuy6jD7xEHJaWux1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865105; bh=Nm1dFVeEqU4Uj0UwM3sZypeUcXgH4LShZWSrk0xT5Mw=; h=Date:From:Reply-To:Subject:To; b=lAKT3RM0wRrfHcGB1YLribIPVtVLzFMsgHkujEKx7lrdaa+iSRk4tedxCaX9jontHXZ r94PKWm1TRSdRsyQCfQewSztpQUDQ9zAmKzX/4xfVIREwZhD7lUBNbbh14Jupynpml6dg dTHZNs23wu7OvqNhfFCToGwU9fxGjdCqX1E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The initial version of SiFive U500 platform package. Signed-off-by: Gilbert Chen --- Platform/RiscV/SiFive/U500Pkg/Readme.md | 62 +++ Platform/RiscV/SiFive/U500Pkg/U500.dec | 34 ++ Platform/RiscV/SiFive/U500Pkg/U500.dsc | 549 +++++++++++++++++++++= ++++ Platform/RiscV/SiFive/U500Pkg/U500.fdf | 335 +++++++++++++++ Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc | 52 +++ Platform/RiscV/SiFive/U500Pkg/U500.uni | 13 + Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni | 12 + Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc | 78 ++++ 8 files changed, 1135 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Readme.md create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dec create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dsc create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.uni create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni create mode 100644 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc diff --git a/Platform/RiscV/SiFive/U500Pkg/Readme.md b/Platform/RiscV/SiFiv= e/U500Pkg/Readme.md new file mode 100644 index 00000000..71fa62a1 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Readme.md @@ -0,0 +1,62 @@ +# Introduction + +## U500 Platform Package +This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U= 500 VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Get= ting Started Guide" on https://www.sifive.com/documentation. This package i= s built with below common packages,
+- **RiscVPlatformPkg**, edk2-platform/Platform/RiscV +- **RiscVPkg**, edk2 master branch (Currently is in edk2-staging/RISC-V br= anch) +
+This package provides librareis and modules which are SiFive U500 platform= implementation-specific and incorporate with common RISC-V packages mentio= ned above. + +## Download the sources +``` +git clone https://github.com/tianocore/edk2-staging.git +# Checkout RISC-V-V2 branch +git clone https://github.com/tianocore/edk2-platforms.git +# Checkout devel-riscv-v2 branch +git clone https://github.com/tianocore/edk2-non-osi.git +``` + +## Platform Owners +Chang, Abner
+Chen, Gilbert + +## Platform Status +Currently the binary built from U500Pkg can boot SiFive Freedom U500 VC707= FPGA to EFI shell with console in/out enabled. + +## Linux Build Instructions +You can build the RISC-V platform using below script,
+`build -a RISCV64 -p Platform/RiscV/SiFive/U500Pkg/U500.dsc -t GCCRISCV` + +## Supported Operating Systems +Only support to boot to EFI Shell so far + +## Known Issues and Limitations +Only RISC-V RV64 is verified on this platform. + +## Related Materials +- [RISC-V OpenSbi](https://github.com/riscv/opensbi)
+- [SiFive U500 VC707 FPGA Getting Started Guide](https://sifive.cdn.prismi= c.io/sifive%2Fc248fabc-5e44-4412-b1c3-6bb6aac73a2c_sifive-u500-vc707-gettin= gstarted-v0.2.pdf)
+- [SiFive RISC-V Core Document](https://www.sifive.com/documentation) + +## U500 Platform Libraries and Drivers +### OpneSbiPlatformLib +In order to reduce the dependencies with RISC-V OpenSBI project (https://g= ithub.com/riscv/opensbi) and less burdens to EDK2 build process, the implem= entation of RISC-V EDK2 platform is leverage platform source code from Open= SBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from RI= SC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build env= ironment. + +### PeiCoreInfoHobLib +This is the library to create RISC-V core characteristics for building up = RISC-V related SMBIOS records to support the unified boot loader and OS ima= ge. This library leverage the silicon libraries provided in Silicon/SiFive. + +### RiscVPlatformTimerLib +This is U500 platform timer library which has the platform-specific timer = implementation. + +### PlatformPei +This is the platform-implementation specific library which is executed in = early PEI phase for platform initialization. + +### TimerDxe +This is U500 platform timer DXE driver whcih has the platform-specific tim= er implementation. + +## U500 Platform PCD settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdNumberofU5Cores| Number of U5 core enabled on U500 platform| +|PcdE5MCSupported| Indicates whether or not the Monitor Core (E5) is suppo= rted on U500 platform| diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dec b/Platform/RiscV/SiFive= /U500Pkg/U500.dec new file mode 100644 index 00000000..4ecca89b --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.dec @@ -0,0 +1,34 @@ +## @file U500.dec +# This Package provides SiFive U500 modules and libraries. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D U500 + PACKAGE_UNI_FILE =3D U500.uni + PACKAGE_GUID =3D D11E9DB9-5940-4642-979D-2114342140D2 + PACKAGE_VERSION =3D 1.0 + +[Includes] + Include + +[LibraryClasses] + + +[Guids] + gUefiRiscVPlatformU500PkgTokenSpaceGuid =3D {0xDFD87009, 0x27A1, 0x41DD= , { 0x84, 0xB1, 0x35, 0xB4, 0xB9, 0x0D, 0x17, 0x63 }} + +[PcdsFixedAtBuild] + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores|0x8|UINT32|0x= 00001000 + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported|TRUE|BOOLEAN|0x= 00001001 + +[PcdsPatchableInModule] + + +[UserExtensions.TianoCore."ExtraFiles"] + U500PkgExtra.uni diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dsc b/Platform/RiscV/SiFive= /U500Pkg/U500.dsc new file mode 100644 index 00000000..edcd951a --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.dsc @@ -0,0 +1,549 @@ +## @file +# RISC-V EFI on SiFive VC707 (U500) RISC-V platform +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D U500 + PLATFORM_GUID =3D 0955581C-2A6A-48F7-8690-9D275AE884F8 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/U500Pkg + SUPPORTED_ARCHITECTURES =3D RISCV64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/RiscV/SiFive/U500Pkg/U500.fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE DEBUG_ON_SERIAL_PORT =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_SNP_ENABLE =3D FALSE + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this Platf= orm. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### +[LibraryClasses] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + SerialPortLib|Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIo= Lib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + +# RISC-V Platform Library + RealTimeClockLib|Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClo= ckLibNull.inf + +# RISC-V Core Library + RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf +!endif + + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + +# ACPI not supported yet. + #S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScri= ptLib.inf + SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common] +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +!endif + RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf + RiscVPlatformTimerLib|Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatfor= mTimerLib/RiscVPlatformTimerLib.inf + CpuExceptionHandlerLib|RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHa= ndlerDxeLib.inf + +[LibraryClasses.common.SEC] +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf +!endif + + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + +# +# OpenSBi Platform Library +# + OpenSbiPlatformLib|Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatform= Lib/OpenSbiPlatformLib.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOp= enSbi/PeiServicesTablePointerLibOpenSbi.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOp= enSbi/PeiServicesTablePointerLibOpenSbi.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf +!endif + FirmwareContextProcessorSpecificLib|Platform/RiscV/Library/FirmwareConte= xtProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf + RiscVPlatformDxeIplLib|RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/Ris= cVDxeIplHandoffOpenSbiLib.inf + +# +# RISC-V core libraries +# + SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf + SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf + SiliconSiFiveU5MCCoreplexInfoLib|Platform/RiscV/SiFive/U500Pkg/Library/P= eiCoreInfoHobLib/PeiCoreInfoHobLib.inf + +[LibraryClasses.common.DXE_CORE] + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + #CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpu= ExceptionHandlerLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + PlatformBootManagerLib|Platform/RiscV/SiFive/U500Pkg/Library/PlatformBoo= tManagerLib/PlatformBootManagerLib.inf + #PlatformBootManagerLib|MdeModulePkg/Library/PlatformBootManagerLibNull/= PlatformBootManagerLibNull.inf + #CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpu= ExceptionHandlerLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + +[LibraryClasses.common.SMM_CORE] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +##########################################################################= ###### +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 +!endif + + #gUefiPayloadPkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x= 3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + # + # F2 for UI APP + # + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + +##########################################################################= ###### +# +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Pla= tform +# +##########################################################################= ###### + +[PcdsDynamicDefault] + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0 + + # Set video resolution for text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + Platform/RiscV/Universal/Sec/SecMain.inf + + # + # PEI Phase modules + # + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouter= Pei.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompress= Lib.inf + } + + Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } + + # + # DXE Phase modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompr= essLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + + # + # EBC not supported on RISC-V yet + # + #MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf { + + ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseReset= SystemLibNull.inf + } + + # + # RISC-V Platform module + # + Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf + Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/Fvb= ServicesRuntimeDxe.inf + + # + # RISC-V Core module + # + RiscVPkg/Universal/CpuDxe/CpuDxe.inf + RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + +# No graphic console supported yet. +# MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.in= f { +# +# PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf +# } + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # SMBIOS Support + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # ACPI Support + # Not support on RISC-V yet + # + #MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + #MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + + # + # Network Support + # + !include NetworkPkg/Network.dsc.inc + + # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!endif + + MdeModulePkg/Application/UiApp/UiApp.inf diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.fdf b/Platform/RiscV/SiFive= /U500Pkg/U500.fdf new file mode 100644 index 00000000..5ca84be3 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.fdf @@ -0,0 +1,335 @@ +# @file +# Flash definition file on SiFive VC707 (U500) RISC-V platform +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + +!include U500.fdf.inc + +# +# Build the variable store and the firmware code as one unified flash devi= ce +# image. +# +[FD.U500] +BaseAddress =3D $(FW_BASE_ADDRESS) +Size =3D $(FW_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(FW_BLOCKS) + +$(SECFV_OFFSET)|$(SECFV_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVSecFvSize +FV =3D SECFV + +$(PEIFV_OFFSET)|$(PEIFV_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVPeiFvSize +FV =3D PEIFV + +$(FVMAIN_OFFSET)|$(FVMAIN_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVDxeFvSize +FV =3D FVMAIN_COMPACT + +!include VarStore.fdf.inc + +##########################################################################= ###### + +[FV.SECFV] +BlockSize =3D 0x1000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +# +# SEC Phase modules +# +# The code in this FV handles the initial firmware startup, and +# decompresses the PEI and DXE FVs which handles the rest of the boot sequ= ence. +# +INF Platform/RiscV/Universal/Sec/SecMain.inf + +##########################################################################= ###### +[FV.PEIFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +APRIORI PEI { + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeR= outerPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.i= nf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +} + +# +# PEI Phase modules +# +INF MdeModulePkg/Core/Pei/PeiMain.inf +INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRou= terPei.inf +INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +# RISC-V Platform PEI Driver +INF Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.i= nf + +##########################################################################= ###### + +[FV.DXEFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +APRIORI DXE { + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDx= e/FvbServicesRuntimeDxe.inf +} + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf + +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF MdeModulePkg/Universal/Metronome/Metronome.inf + +# RISC-V Platform Drivers +INF Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= FvbServicesRuntimeDxe.inf + +# RISC-V Core Drivers +INF RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf +INF Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf +INF RiscVPkg/Universal/CpuDxe/CpuDxe.inf +INF RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf + +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf +!endif + +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +#INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe= .inf + +!ifndef $(SOURCE_DEBUG_ENABLE) +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf +!endif + +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + +# +# ACPI is not supported yet on RISC-V package. +# +#INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +#INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf +#INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf + +#INF RuleOverride =3D BINARY FatBinPkg/EnhancedFatDxe/Fat.inf + +INF ShellPkg/Application/Shell/Shell.inf + +# +# Network modules +# +!if $(E1000_ENABLE) + FILE DRIVER =3D 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 { + SECTION PE32 =3D Intel3.5/EFIX64/E3507X2.EFI + } +!endif + +!include NetworkPkg/Network.fdf.inc + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +INF MdeModulePkg/Application/UiApp/UiApp.inf + +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE { + # + # These firmware volumes will have files placed in them uncompressed, + # and then both firmware volumes will be compressed in a single + # compression operation in order to achieve better overall compressio= n. + # + SECTION FV_IMAGE =3D DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align =3D 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc b/Platform/RiscV/Si= Five/U500Pkg/U500.fdf.inc new file mode 100644 index 00000000..ac24b5b0 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc @@ -0,0 +1,52 @@ +## @file +# Definitions of Flash definition file on SiFive VC707 (U500) RISC-V plat= form +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +DEFINE BLOCK_SIZE =3D 0x1000 + +DEFINE FW_BASE_ADDRESS =3D 0x80000000 +DEFINE FW_SIZE =3D 0x00800000 +DEFINE FW_BLOCKS =3D 0x800 + +# +# 0x000000-0x7DFFFF code +# 0x7E0000-0x800000 variables +# +DEFINE CODE_BASE_ADDRESS =3D 0x80000000 +DEFINE CODE_SIZE =3D 0x007E0000 +DEFINE CODE_BLOCKS =3D 0x7E0 +DEFINE VARS_BLOCKS =3D 0x20 + +DEFINE SECFV_OFFSET =3D 0x00000000 +DEFINE SECFV_SIZE =3D 0x00020000 +DEFINE PEIFV_OFFSET =3D 0x00020000 +DEFINE PEIFV_SIZE =3D 0x00060000 +DEFINE SCRATCH_OFFSET =3D 0x00080000 +DEFINE SCRATCH_SIZE =3D 0x00010000 +DEFINE FVMAIN_OFFSET =3D 0x00100000 # Must be power of 2 for PMP setti= ng +DEFINE FVMAIN_SIZE =3D 0x0018C000 +DEFINE VARS_OFFSET =3D 0x007E0000 +DEFINE VARS_SIZE =3D 0x00020000 + +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =3D $(FW_= BASE_ADDRESS) + $(VARS_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize =3D $(BLO= CK_SIZE) + +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress =3D $(CODE_BASE_= ADDRESS) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress =3D $(CODE_BASE_AD= DRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =3D 8192 +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase =3D $(CODE_BASE_= ADDRESS) + $(SCRATCH_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize =3D $(SCRATCH_SI= ZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase =3D $(CODE_BAS= E_ADDRESS) + $(FW_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize =3D 0x10000 + + +SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz =3D 10= 00000 +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount =3D 4 #= Total cores on U500 platform +SET gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores =3D 4 #= Total U5 cores enabled on U500 platform +SET gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported =3D False #= Enable optional E51 MC core? +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId =3D 0 #= Boot hart ID diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.uni b/Platform/RiscV/SiFive= /U500Pkg/U500.uni new file mode 100644 index 00000000..7ac1096f --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.uni @@ -0,0 +1,13 @@ +// /** @file +// SiFive U500 Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_PACKAGE_ABSTRACT #language en-US "Provides SiFIve R= ISC-V U500 platform modules and libraries" + +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package SiFI= ve RISC-V U500 platform modules and libraries." diff --git a/Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni b/Platform/Risc= V/SiFive/U500Pkg/U500PkgExtra.uni new file mode 100644 index 00000000..6b68fb43 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// SiFive U500 Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_PACKAGE_NAME +#language en-US +"SiFive U500 package" diff --git a/Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc b/Platform/Risc= V/SiFive/U500Pkg/VarStore.fdf.inc new file mode 100644 index 00000000..c287bb43 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc @@ -0,0 +1,78 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|0x00007000 +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block + 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + # Size: 0x7000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x6fb8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0x6F, 0x00, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x007e7000|0x00001000 +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBas= e|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +#NV_FTW_WROK +# +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x007e8000|0x00018000 +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +#NV_FTW_SPARE --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47540): https://edk2.groups.io/g/devel/message/47540 Mute This Topic: https://groups.io/mt/34196355/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-