From nobody Sun Feb 8 18:30:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47536+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47536+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865100; cv=none; d=zoho.com; s=zohoarc; b=MpB6NNl6WR7TFHOwLjrhPu2wfwGPwm/Cl+jzaxiYRPTXk7NFStY4VGhs0eSie7Uf7ZcLzwH9xCMBbZq+gaBjXf0Fy/K6hL2eoLhzb7itS1FUB17uY6c0DRZ6gselLc43DO2haV+G3c79zrIK2xxzTFbYSeCSFKOcLl+z9jKq5MY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865100; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=KlSrpfDL1RMuM2OhQGI/Sx1ljuZij+yJUA7mf9JmGXA=; b=K/EDpmIqT42n1cL+Zeba1wQKXSKVlk6ZB979QZf99QzM16WZLT47oc2XYE5ONXJgCzpTg0bYJRCnZRnF4NvQoYzv1kpMCbrjrbgsp1T1L8Q8zVB1JMSAJL8CYm5dRVy78PZjq1ZJq8VeR2EDlzyMnXH1aIipNYrUpyujv76LT0U= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47536+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865100200348.78809628953513; Wed, 18 Sep 2019 20:51:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id V7K4YY1788612x0kkYLgk4oD; Wed, 18 Sep 2019 20:51:39 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:39 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pKqn017013 for ; Thu, 19 Sep 2019 03:51:38 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v3vatnf2v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:38 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id B8DE457 for ; Thu, 19 Sep 2019 03:51:37 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id EC79345 for ; Thu, 19 Sep 2019 03:51:36 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 03/14] platforms/RiscV: Initial version of RISC-V platform package Date: Thu, 19 Sep 2019 11:51:20 +0800 Message-Id: <20190919035131.4700-4-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: mQKlddHOD1PCUqQJsUmC8qnRx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865099; bh=xmvWON3bUKJIHxPZUJ1w/vkDCpUrWiTEjXhalGdq93g=; h=Date:From:Reply-To:Subject:To; b=jcXBaM+i5+PmM3VvBC+LrS/pvLT1dtAznTqbiCKyt08HNLsbbEQmr70JHKWuk9xpUb0 6U9hPzwqVzrtT/Czm9CgoaUmzAc1jI7VO4DY/rC0IAT+tZ95GQkBFA1GUbX6wI8pH2KQs RgmuZsJGe1pgla4MGTfGkSdoqH7ZhRvAS1Y= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Initial version of RISC-V platform package which provides the common libraries, drivers, PCD and etc. for RISC-V platform development. Signed-off-by: Gilbert Chen --- Platform/RiscV/Readme.md | 89 ++++++++++++++++++++++++++++= ++++ Platform/RiscV/RiscVPlatformPkg.dec | 72 ++++++++++++++++++++++++++ Platform/RiscV/RiscVPlatformPkg.uni | 15 ++++++ Platform/RiscV/RiscVPlatformPkgExtra.uni | 12 +++++ 4 files changed, 188 insertions(+) create mode 100644 Platform/RiscV/Readme.md create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni diff --git a/Platform/RiscV/Readme.md b/Platform/RiscV/Readme.md new file mode 100644 index 00000000..277782e3 --- /dev/null +++ b/Platform/RiscV/Readme.md @@ -0,0 +1,89 @@ +# Introduction + +## EDK2 RISC-V Platform Package +RISC-V platform package provides the generic and common modules for RISC-V= platforms. RISC-V platform package could include RiscPlatformPkg.dec to us= e the common drivers, libraries, definitions, PCDs and etc. for the platfor= m development. + +## EDK2 RISC-V Platforms +RISC-V platform is created and maintained by RISC-V platform vendors. The = directory of RISC-V platform should be created under Platform/RiscV. Vendor= should create the folder under Platform/RiscV and name it using vendor nam= e, under the vendor folder is the platform folder named by platform model n= ame, code name or etc. (e.g. Platform/RiscV/SiFive/U500Pkg) + +## Build EDK2 RISC-V Platforms +RISC-V platform package should provide EDK2 metafiles under RISC-V platfor= m package folder (Platform/RiscV/{Vendor}/{Platform}). Build RISC-V platfor= m package against edk2 and follow the build guidence mentioned in Readme.md= under below link.
+https://github.com/tianocore/edk2-platforms
+ +### Download the sources ### +``` +git clone https://github.com/tianocore/edk2-staging.git +# Checkout RISC-V-V2 branch +git clone https://github.com/tianocore/edk2-platforms.git +# Checkout devel-riscv-v2 branch +git clone https://github.com/tianocore/edk2-non-osi.git +``` + +### Requirements +Build EDK2 RISC-V platform requires GCC RISC-V toolchain. Refer to https:/= /github.com/riscv/riscv-gnu-toolchain for the details. +The commit ID 64879b24 is verified to build RISC-V EDK2 platform and boot = to EFI SHELL successfully. + +### EDK2 project +Currently, the EDK2 RISC-V platform can only build with edk2 project in **= edk2-staging/RISC-V-V2** branch. The build architecture whcih is supported = and verified so far is "RISCV64". The verified RISC-V toolchain is https://= github.com/riscv/riscv-gnu-toolchain @64879b24, toolchain tag is "GCCRISCV"= declared in tools_def.txt
+ +### Linux Build Instructions +You can build the RISC-V platform using below script,
+`build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCCRIS= CV` + +Or modify target.txt to set up your build parameters. + +## RISC-V Platform PCD settings +### EDK2 Firmware Volume Settings +EDK2 Firmware volume related PCDs which declared in platform FDF file. + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdRiscVSecFvBase| The base address of SEC Firmware Volume| +|PcdRiscVSecFvSize| The size of SEC Firmware Volume| +|PcdRiscVPeiFvBase| The base address of SEC Firmware Volume| +|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| +|PcdRiscVDxeFvBase| The base address of SEC Firmware Volume| +|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| + +### EDK2 EFI Variable Region Settings +The PCD settings regard to EFI Variable + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdVariableFdBaseAddress| The EFI variable firmware device base address| +|PcdVariableFdSize| The EFI variable firmware device size| +|PcdVariableFdBlockSize| The block size of EFI variable firmware device| +|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within f= irmware device| +|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable= fault tolerance worksapce (FTW) within firmware device| +|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable s= pare FTW within firmware device| + +### RISC-V Physical Memory Protection (PMP) Region Settings +Below PCDs could be set in platform FDF file. + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdFwStartAddress| The starting address of firmware region to protected b= y PMP| +|PcdFwEndAddress| The ending address of firmware region to protected by PM= P| + +### RISC-V Processor HART Settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific| +|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS| + +### RISC-V OpenSBI Settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RIS= C-V HARTs| +|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-= V HARTs| +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use OpenSBI| +|PcdTemporaryRamBase| The base address of temporary memory for PEI phase| +|PcdTemporaryRamSize| The temporary memory size for PEI phase| + +## Supported Operating Systems +Only support to boot to EFI Shell so far + +## Known Issues and Limitations +Only RISC-V RV64 is verified diff --git a/Platform/RiscV/RiscVPlatformPkg.dec b/Platform/RiscV/RiscVPlat= formPkg.dec new file mode 100644 index 00000000..3ce16bfc --- /dev/null +++ b/Platform/RiscV/RiscVPlatformPkg.dec @@ -0,0 +1,72 @@ +## @file RiscVPlatformPkg.dec +# This Package provides UEFI RISC-V platform modules and libraries. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D RiscPlatformPkg + PACKAGE_UNI_FILE =3D RiscPlatformPkg.uni + PACKAGE_GUID =3D 6A67AF99-4592-40F8-B6BE-62BCA10DA1EC + PACKAGE_VERSION =3D 1.0 + +[Includes] + Include + +[LibraryClasses] + +[LibraryClasses.RISCV32, LibraryClasses.RISCV64] + +[Guids] + gUefiRiscVPlatformPkgTokenSpaceGuid =3D {0x6A67AF99, 0x4592, 0x40F8, { = 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}} + +[PcdsFixedAtBuild] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|0x0|UINT32|0x00001= 000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize|0x0|UINT32|0x00001= 001 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001= 002 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001= 003 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001= 004 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001= 005 + +# +# Definition of EFI Variable region +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001010 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001012 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001013 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001014 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001015 +# +# Firmware region which is protected by PMP. +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022 +# +# Definition of RISC-V Hart +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024 +# +# Definitions for OpenSbi +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001025 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize|0|UINT32|0x00001026 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize|0|UINT32|0x00001= 027 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00001= 028 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001= 029 + +[PcdsPatchableInModule] + +[PcdsFeatureFlag] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001006 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVPlatformPkgExtra.uni diff --git a/Platform/RiscV/RiscVPlatformPkg.uni b/Platform/RiscV/RiscVPlat= formPkg.uni new file mode 100644 index 00000000..deb91fa1 --- /dev/null +++ b/Platform/RiscV/RiscVPlatformPkg.uni @@ -0,0 +1,15 @@ +// /** @file +// RISC-V Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI com= patible RISC-V platform modules and libraries" + +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package prov= ides UEFI compatible RISC-V platform modules and libraries." + + diff --git a/Platform/RiscV/RiscVPlatformPkgExtra.uni b/Platform/RiscV/Risc= VPlatformPkgExtra.uni new file mode 100644 index 00000000..98d81aed --- /dev/null +++ b/Platform/RiscV/RiscVPlatformPkgExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// RISC-V Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_PACKAGE_NAME +#language en-US +"RiscV platform package" --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47536): https://edk2.groups.io/g/devel/message/47536 Mute This Topic: https://groups.io/mt/34196350/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-