From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47534+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47534+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865098; cv=none; d=zoho.com; s=zohoarc; b=DCFnItnBC29lQWitawSOrMdEC3fCYR9MoDbuHH9R72CaIAefEmfrptEWYpy71bIu47l63cIKu/gLEDdiRmik6PfoDFagWPE1XG+jOndDH62B0/M+BsiTpmClwEnQ6miVDLW0himwyfoQ8j3G+3bkALQqP/bl9pzHDVmR6t6/qzM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865098; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=9O55kC76sJI+F/Wo96zQkzL+0Ap4BTrdUyOctvpL7hY=; b=dWFBXDdYsAVmWYSwqggGZgKihFdJyxn4SNNy+KIvuId9FQ/yMdlnv1c/tkyOMqbtK+fHOLn+4lOMagV+B38K8c+cRVx6h9PyOXbZvCWP86b0Cf9qkNX221tQF3uZFJb5LNwofo7BQOFndObIB2e0Z8mR1mPYXk7YUxz9dwJJmlo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47534+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865098285782.9570484993232; Wed, 18 Sep 2019 20:51:38 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id AWLWYY1788612xGI8jpDWEp7; Wed, 18 Sep 2019 20:51:37 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:37 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pLO8017060 for ; Thu, 19 Sep 2019 03:51:36 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com with ESMTP id 2v3vatnf2g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:36 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 250848D for ; Thu, 19 Sep 2019 03:51:35 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 56FED45 for ; Thu, 19 Sep 2019 03:51:34 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 01/14] Silicon/SiFive: Initial version of SiFive silicon package Date: Thu, 19 Sep 2019 11:51:18 +0800 Message-Id: <20190919035131.4700-2-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: Q4pC0yHOvyf0I9oS6uOyaP6Ox1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865097; bh=hRrXbX2cD9SEXpR9jXXmJIyetSZmJIFYYQGgkQRPorE=; h=Date:From:Reply-To:Subject:To; b=For8YCnU3YgU1m2AfB3vgrVeD3seR9g8gnTtbMpFNPgtFziY3GCbQlvXtUrDrwtxeIy D4sB1p3yvYQbL1Q1zdNeMJ2OQTlRnex+E2pLnDPBxNZY88WO1+o9/nfaBLsZFRvfM1f+C BUlNJZCSL2fIVW9cNrLwGDPYQBJIbey5jbI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add SiFive silicon EDK2 metafile and header files of SiFive RISC-V cores. Signed-off-by: Gilbert Chen --- Silicon/SiFive/Include/Library/SiFiveE51.h | 60 ++++++++++++++++++= ++++ Silicon/SiFive/Include/Library/SiFiveU54.h | 60 ++++++++++++++++++= ++++ .../SiFive/Include/Library/SiFiveU54MCCoreplex.h | 55 ++++++++++++++++++= ++ Silicon/SiFive/SiFive.dec | 39 ++++++++++++++ 4 files changed, 214 insertions(+) create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h create mode 100644 Silicon/SiFive/SiFive.dec diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h b/Silicon/SiFive/In= clude/Library/SiFiveE51.h new file mode 100644 index 00000000..5faea5c7 --- /dev/null +++ b/Silicon/SiFive/Include/Library/SiFiveE51.h @@ -0,0 +1,60 @@ +/** @file + SiFive E51 Core library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SIFIVE_E51_CORE_H_ +#define _SIFIVE_E51_CORE_H_ + +#include + +#include +#include + +/** + Function to build core specific information HOB. + + @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + could be the same as CoreGuid if one proc= essor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns= this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobData Pointer to receive RISC_V_PROCESSOR_SPECI= FIC_DATA_HOB. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData + ); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ); + +#endif diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h b/Silicon/SiFive/In= clude/Library/SiFiveU54.h new file mode 100644 index 00000000..2e3a1c75 --- /dev/null +++ b/Silicon/SiFive/Include/Library/SiFiveU54.h @@ -0,0 +1,60 @@ +/** @file + SiFive U54 Core library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SIFIVE_U54_CORE_H_ +#define _SIFIVE_U54_CORE_H_ + +#include + +#include +#include + +/** + Function to build core specific information HOB. + + @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + could be the same as CoreGuid if one proc= essor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns= this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA= _HOB. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobdata + ); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + IN RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ); + +#endif diff --git a/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h b/Silicon= /SiFive/Include/Library/SiFiveU54MCCoreplex.h new file mode 100644 index 00000000..3d23b34c --- /dev/null +++ b/Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h @@ -0,0 +1,55 @@ +/** @file + SiFive U54 Coreplex library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SIFIVE_U54MC_COREPLEX_CORE_H_ +#define _SIFIVE_U54MC_COREPLEX_CORE_H_ + +#include + +#include +#include + +#define SIFIVE_U54MC_COREPLEX_E51_HART_ID 0 +#define SIFIVE_U54MC_COREPLEX_U54_0_HART_ID 1 +#define SIFIVE_U54MC_COREPLEX_U54_1_HART_ID 2 +#define SIFIVE_U54MC_COREPLEX_U54_2_HART_ID 3 +#define SIFIVE_U54MC_COREPLEX_U54_3_HART_ID 4 + +/** + Build up U54MC coreplex processor core-specific information. + + @param UniqueId U54MC unique ID. + + @return EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +CreateU54MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + IN RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ); +#endif diff --git a/Silicon/SiFive/SiFive.dec b/Silicon/SiFive/SiFive.dec new file mode 100644 index 00000000..7aca3e75 --- /dev/null +++ b/Silicon/SiFive/SiFive.dec @@ -0,0 +1,39 @@ +## @file +# SiFive silicon package definitions +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D SiFiveSiliconPkg + PACKAGE_GUID =3D 576912B2-7077-4B78-A934-4C133FEB20BB + PACKAGE_VERSION =3D 1.0 + +[Includes] + Include # Root include for the package + +[LibraryClasses] + +[Guids] + gEfiSiFiveSiliconSpaceGuid =3D {0x5F3E9E15, 0x8FFC, 0x4F53, { 0x8E, 0x6= 4, 0x92, 0x0B, 0xA5, 0x39, 0x81, 0xB0 }} + +[Protocols] + +[PcdsFixedAtBuild] + # E51 Core GUID + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveE51CoreGuid |{0xD4, 0x69, 0x54, 0x87= , 0x96, 0x96, 0x48, 0x7F, 0x9F, 0x57, 0xB6, 0xF1, 0xDE, 0x7D, 0x97, 0x42}|V= OID*|0x00001000 + # U54 Core GUID + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54CoreGuid |{0x64, 0x70, 0xF6, 0x90= , 0x11, 0x59, 0x47, 0xF1, 0xB8, 0xD5, 0xCF, 0x89, 0x10, 0xC5, 0x30, 0x20}|V= OID*|0x00001001 + # U54 MC Coreplex GUID + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54MCCoreplexGuid |{0x67, 0xBF, 0x15= , 0xD9, 0x7E, 0x4F, 0x48, 0x27, 0x87, 0x19, 0x79, 0x0B, 0xA6, 0x22, 0x7C, 0= xBE}|VOID*|0x00001002 + # U5 MC Coreplex GUID + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU5MCCoreplexGuid |{0x06, 0x38, 0x9F,= 0x33, 0xF9, 0xDB, 0x43, 0x13, 0x9A, 0x9B, 0x1C, 0x68, 0xD6, 0x04, 0xEA, 0x= FF}|VOID*|0x00001003 + +[PcdsDynamic, PcdsDynamicEx] + +[PcdsFeatureFlag] + --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47534): https://edk2.groups.io/g/devel/message/47534 Mute This Topic: https://groups.io/mt/34196347/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47535+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47535+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865100; cv=none; d=zoho.com; s=zohoarc; b=E7AdgbqzPz7iIh7AzEzSQEVG459B/H5jsI2i5yAGxVqiaOoBfEKIOFxrd3L25crJBOL0i40zH+U3DC6E1Yv62I4n9XWp8lTS19PDvgK4BBkEi09K8C9zyeOyztRmwdbC2NHkpO/R60pqbysOO5Z4l9uV4BqDKGC25xRXrVGGKsw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865100; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=l1pZadZG6APHwWtdqogXF36CRTXOxsCqVoq3ReecJ28=; b=leZudklo7gRTsadbEoxsiFKp+2agzXeYWb+GG6ozWIbl0hkpB2E1BJxm6FchxXuWcm4hB+zbVp4Jwx3jPK7og36dJ6c0i6thT8ur+Zv5B8wHQloDmgWr1qJLdz9Xr3zirAON+scsW32HjE+yTw8NF5aICzuXENShnXfJ/zJs3S8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47535+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865100201221.7025875012888; Wed, 18 Sep 2019 20:51:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Iu0sYY1788612xXq5op0U64P; Wed, 18 Sep 2019 20:51:38 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:38 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pJw3021123 for ; Thu, 19 Sep 2019 03:51:37 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vaqnkax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:37 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 6F74492 for ; Thu, 19 Sep 2019 03:51:36 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id A148047 for ; Thu, 19 Sep 2019 03:51:35 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 02/14] Silicon/SiFive: Add library module of SiFive RISC-V cores Date: Thu, 19 Sep 2019 11:51:19 +0800 Message-Id: <20190919035131.4700-3-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: pJmEcU2Fd3dBHQ1nbunZiVfwx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865098; bh=UoKK04z3BviIw1uuCVaVJIGcRr6Y8KuJHOY96bqRPZ8=; h=Date:From:Reply-To:Subject:To; b=NHGkvYrfwCKv+9N19Z0LZ0l9266taO8pfktm+qmkubF3xVAlexU9FtjJtBPPfVgnSdr gXF0bmpRXrYWlOYFkpK/oZr43dgnf0vZx5FMaCwB/iLRrkYAUl0R35XYTkpwKz9orggVr EAcXJspBFNXbRn1IwlX6TAYpM5KHbuWL02o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Initial version of SiFive RISC-V core libraries. Library of each core creates processor core SMBIOS data hob for building SMBIOS records in DXE phase. Signed-off-by: Gilbert Chen --- .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 242 +++++++++++++++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++ .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c | 294 +++++++++++++++++= ++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 51 ++++ .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 185 +++++++++++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 50 ++++ 6 files changed, 873 insertions(+) create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHo= b.c create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInf= oHobLib.inf create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHo= b.c create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInf= oHobLib.inf create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= CoreInfoHob.c create mode 100644 Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/= PeiCoreInfoHobLib.inf diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c new file mode 100644 index 00000000..b7140b53 --- /dev/null +++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,242 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Function to build core specific information HOB. RISC-V SMBIOS DXE drive= r collect + this information and build SMBIOS Type44. + + @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + could be the same as CoreGuid if one proc= essor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns= this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobData Pointer to receive EFI_HOB_GUID_TYPE. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData + ) +{ + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob; + EFI_GUID *ProcessorSpecDataHobGuid; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob; + struct sbi_scratch *ThisHartSbiScratch; + struct sbi_platform *ThisHartSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); + + if (GuidHobData =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ThisHartSbiScratch =3D sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(= ), (UINT32)HartId); + DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch)= ); + ThisHartSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(ThisHart= SbiScratch); + DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatfor= m)); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPla= tform->firmware_context; + DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContex= t)); + FirmwareContextHartSpecific =3D FirmwareContext->HartSpecific[HartId]; + DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", = FirmwareContextHartSpecific)); + + // + // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB. + // + CommonFirmwareContextHartSpecificInfo ( + FirmwareContextHartSpecific, + ParentProcessorGuid, + ParentProcessorUid, + (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid), + HartId, + IsBootHart, + &ProcessorSpecDataHob + ); + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported; + ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64; + + DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L)); + DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId)); + DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported)); + DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen )); + DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen)); + DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen)); + DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen)); + DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported)); + DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L)); + + // + // Build GUID HOB for E51 core, this is for SMBIOS type 44 + // + ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid); + CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_DATA_HOB)); + if (CoreGuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n")); + ASSERT (FALSE); + } + *GuidHobData =3D CoreGuidHob; + return EFI_SUCCESS; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateE51ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L1InstCacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Build up SMBIOS type 7 L1 instruction cache record. + // + ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA= _HOB)); + CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveE51CoreGuid)); + L1InstCacheDataHob.ProcessorUid =3D ProcessorUid; + L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; + L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; + L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion; + L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _DATA_HOB)); + if (L1InstCacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_H= OB)); + CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veE51CoreGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DAT= A_HOB)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr; + SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L2Cache =3D NULL; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HO= B)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core RISC_= V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + return EFI_SUCCESS; +} + + diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf new file mode 100644 index 00000000..003ad5ae --- /dev/null +++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -0,0 +1,51 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconSiFiveE51CoreInfoLib + FILE_GUID =3D 80A59B85-1245-4309-AC58-2CFA4199B46C + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveE51CoreInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Silicon/SiFive/SiFive.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + FirmwareContextProcessorSpecificLib + +[Guids] + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveE51CoreGuid + diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c b/S= ilicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c new file mode 100644 index 00000000..295e020a --- /dev/null +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,294 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Function to build core specific information HOB. + + @param ParentProcessorGuid Parent processor od this core. ParentProc= essorGuid + could be the same as CoreGuid if one proc= essor has + only one core. + @param ParentProcessorUid Unique ID of pysical processor which owns= this core. + @param HartId Hart ID of this core. + @param IsBootHart TRUE means this is the boot HART. + @param GuidHobdata Pointer to RISC_V_PROCESSOR_SPECIFIC_DATA= _HOB. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54CoreProcessorSpecificDataHob ( + IN EFI_GUID *ParentProcessorGuid, + IN UINTN ParentProcessorUid, + IN UINTN HartId, + IN BOOLEAN IsBootHart, + OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobdata + ) +{ + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob; + EFI_GUID *ProcessorSpecDataHobGuid; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob; + struct sbi_scratch *ThisHartSbiScratch; + struct sbi_platform *ThisHartSbiPlatform; + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext; + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); + + if (GuidHobdata =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ThisHartSbiScratch =3D sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(= ), (UINT32)HartId); + DEBUG ((DEBUG_INFO, " SBI Scratch is at 0x%x.\n", ThisHartSbiScratch)= ); + ThisHartSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(ThisHart= SbiScratch); + DEBUG ((DEBUG_INFO, " SBI platform is at 0x%x.\n", ThisHartSbiPlatfor= m)); + FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisHartSbiPla= tform->firmware_context; + DEBUG ((DEBUG_INFO, " Firmware Context is at 0x%x.\n", FirmwareContex= t)); + FirmwareContextHartSpecific =3D FirmwareContext->HartSpecific[HartId]; + DEBUG ((DEBUG_INFO, " Firmware Context Hart specific is at 0x%x.\n", = FirmwareContextHartSpecific)); + + // + // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB. + // + CommonFirmwareContextHartSpecificInfo ( + FirmwareContextHartSpecific, + ParentProcessorGuid, + ParentProcessorUid, + (EFI_GUID *)PcdGetPtr (PcdSiFiveU54CoreGuid), + HartId, + IsBootHart, + &ProcessorSpecDataHob + ); + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_= H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_L =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Valu= e64_H =3D TO_BE_FILLED; + ProcessorSpecDataHob.ProcessorSpecificData.HartXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.MachineModeXlen =3D = RegisterLen64; + ProcessorSpecDataHob.ProcessorSpecificData.SupervisorModeXlen =3D = RegisterUnsupported; + ProcessorSpecDataHob.ProcessorSpecificData.UserModeXlen =3D = RegisterLen64; + + DEBUG ((DEBUG_INFO, " *HartId =3D 0x%x\n", ProcessorSpecDataHob.P= rocessorSpecificData.HartId.Value64_L)); + DEBUG ((DEBUG_INFO, " *Is Boot Hart? =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.BootHartId)); + DEBUG ((DEBUG_INFO, " *PrivilegeModeSupported =3D 0x%x\n", Proces= sorSpecDataHob.ProcessorSpecificData.PrivilegeModeSupported)); + DEBUG ((DEBUG_INFO, " *MModeExcepDelegation =3D 0x%x\n", Processo= rSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *MModeInterruptDelegation =3D 0x%x\n", Proc= essorSpecDataHob.ProcessorSpecificData.MModeInterruptDelegation.Value64_L)); + DEBUG ((DEBUG_INFO, " *HartXlen =3D 0x%x\n", ProcessorSpecDataHob= .ProcessorSpecificData.HartXlen )); + DEBUG ((DEBUG_INFO, " *MachineModeXlen =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineModeXlen)); + DEBUG ((DEBUG_INFO, " *SupervisorModeXlen =3D 0x%x\n", ProcessorS= pecDataHob.ProcessorSpecificData.SupervisorModeXlen)); + DEBUG ((DEBUG_INFO, " *UserModeXlen =3D 0x%x\n", ProcessorSpecDat= aHob.ProcessorSpecificData.UserModeXlen)); + DEBUG ((DEBUG_INFO, " *InstSetSupported =3D 0x%x\n", ProcessorSpe= cDataHob.ProcessorSpecificData.InstSetSupported)); + DEBUG ((DEBUG_INFO, " *MachineVendorId =3D 0x%x\n", ProcessorSpec= DataHob.ProcessorSpecificData.MachineVendorId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineArchId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineArchId.Value64_L)); + DEBUG ((DEBUG_INFO, " *MachineImplId =3D 0x%x\n", ProcessorSpecDa= taHob.ProcessorSpecificData.MachineImplId.Value64_L)); + + // + // Build GUID HOB for U54 core. + // + ProcessorSpecDataHobGuid =3D PcdGetPtr (PcdProcessorSpecificDataGuidHobG= uid); + CoreGuidHob =3D (RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *)BuildGuidDataHob (= ProcessorSpecDataHobGuid, (VOID *)&ProcessorSpecDataHob, sizeof (RISC_V_PRO= CESSOR_SPECIFIC_DATA_HOB)); + if (CoreGuidHob =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive E51 core.\n")); + ASSERT (FALSE); + } + *GuidHobdata =3D CoreGuidHob; + return EFI_SUCCESS; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54ProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + IN RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L1InstCacheDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L1DataCacheDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1InstCacheDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L1DataCacheDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + // + // Build up SMBIOS type 7 L1 instruction cache record. + // + ZeroMem((VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA= _HOB)); + CopyGuid (&L1InstCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveU54CoreGuid)); + L1InstCacheDataHob.ProcessorUid =3D ProcessorUid; + L1InstCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L1InstCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; + L1InstCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L1InstCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; + L1InstCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; + L1InstCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeInstruc= tion; + L1InstCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L1InstCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1InstCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _DATA_HOB)); + if (L1InstCacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 in= struction cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 7 L1 data cache record. + // + ZeroMem((VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA= _HOB)); + CopyGuid (&L1DataCacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSi= FiveU54CoreGuid)); + L1DataCacheDataHob.ProcessorUid =3D ProcessorUid; + L1DataCacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_B= Y_VENDOR; + L1DataCacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_= CONFIGURATION_CACHE_LEVEL_1 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_INTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L1DataCacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY= _VENDOR; + L1DataCacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VE= NDOR; + L1DataCacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L1DataCacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L1DataCacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDO= R; + L1DataCacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED= _BY_VENDOR; + L1DataCacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeData; + L1DataCacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VE= NDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L1DataCacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDa= taHob (GuidPtr, (VOID *)&L1DataCacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7= _DATA_HOB)); + if (L1DataCacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L1 da= ta cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 7 L2 cache record. + // + ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB= )); + CopyGuid (&L2CacheDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFive= U54CoreGuid)); + L2CacheDataHob.ProcessorUid =3D ProcessorUid; + L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; + L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; + L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; + L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; + L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HO= B)); + if (L2CacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core L2 ca= che RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_H= OB)); + CopyGuid (&ProcessorDataHob.PrcessorGuid, (EFI_GUID *)PcdGetPtr (PcdSiFi= veU54CoreGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 1; + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DAT= A_HOB)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_= V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D L1InstCacheDataHobPtr; + SmbiosDataHob.L1DataCache =3D L1DataCacheDataHobPtr; + SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HO= B)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 core RISC_= V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + return EFI_SUCCESS; +} + diff --git a/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib= .inf b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf new file mode 100644 index 00000000..8efee93b --- /dev/null +++ b/Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf @@ -0,0 +1,51 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconSiFiveU54CoreInfoLib + FILE_GUID =3D 483DE090-267E-4278-A0A1-15D9836780EA + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveU54CoreInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + Silicon/SiFive/SiFive.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + FirmwareContextProcessorSpecificLib + +[Guids] + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSpecificDataGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54CoreGuid + diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInf= oHob.c b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob= .c new file mode 100644 index 00000000..e14b5977 --- /dev/null +++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,185 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include + +#include +#include +#include + +/** + Build up processor-specific HOB for U54MC Coreplex + + @param UniqueId Unique ID of this U54MC Coreplex processor + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ) +{ + EFI_STATUS Status; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ThisGuidHobData; + EFI_GUID *ParentProcessorGuid; + + DEBUG ((DEBUG_INFO, "%a: Entry.\n", __FUNCTION__)); + + ParentProcessorGuid =3D PcdGetPtr (PcdSiFiveU54MCCoreplexGuid); + Status =3D CreateE51CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54MC_COREPLEX_E51_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build E51 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_0_HART_ID, TRUE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_1_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_2_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentProcessorGuid, U= niqueId, SIFIVE_U54_COREPLEX_U54MC_3_HART_ID, FALSE, &ThisGuidHobData); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, "%a: Faile to build U54 core information HOB for = U54 Coreplex.\n", __FUNCTION__)); + return Status; + } + return Status; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU54MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + IN RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Build up SMBIOS type 7 L2 cache record. + // + ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB= )); + L2CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54MCC= oreplexGuid)); + L2CacheDataHob.ProcessorUid =3D ProcessorUid; + L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; + L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; + L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; + L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; + L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HO= B)); + if (L2CacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x L2 cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_H= OB)); + ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU54M= CCoreplexGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D 5; + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DAT= A_HOB)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54 MC Coreple= x RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D NULL; + SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HO= B)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U54MC Coreplex= RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + return EFI_SUCCESS; +} diff --git a/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCore= InfoHobLib.inf b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/Pei= CoreInfoHobLib.inf new file mode 100644 index 00000000..a5714a20 --- /dev/null +++ b/Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHob= Lib.inf @@ -0,0 +1,50 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconSiFiveU54MCCoreplexInfoLib + FILE_GUID =3D 483DE090-267E-4278-A0A1-15D9836780EA + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveU54MCCoreplexInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Silicon/SiFive/SiFive.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + SiliconSiFiveE51CoreInfoLib + SiliconSiFiveU54CoreInfoLib + +[Guids] + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54MCCoreplexGuid + --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47535): https://edk2.groups.io/g/devel/message/47535 Mute This Topic: https://groups.io/mt/34196349/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47536+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47536+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865100; cv=none; d=zoho.com; s=zohoarc; b=MpB6NNl6WR7TFHOwLjrhPu2wfwGPwm/Cl+jzaxiYRPTXk7NFStY4VGhs0eSie7Uf7ZcLzwH9xCMBbZq+gaBjXf0Fy/K6hL2eoLhzb7itS1FUB17uY6c0DRZ6gselLc43DO2haV+G3c79zrIK2xxzTFbYSeCSFKOcLl+z9jKq5MY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865100; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=KlSrpfDL1RMuM2OhQGI/Sx1ljuZij+yJUA7mf9JmGXA=; b=K/EDpmIqT42n1cL+Zeba1wQKXSKVlk6ZB979QZf99QzM16WZLT47oc2XYE5ONXJgCzpTg0bYJRCnZRnF4NvQoYzv1kpMCbrjrbgsp1T1L8Q8zVB1JMSAJL8CYm5dRVy78PZjq1ZJq8VeR2EDlzyMnXH1aIipNYrUpyujv76LT0U= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47536+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865100200348.78809628953513; Wed, 18 Sep 2019 20:51:40 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id V7K4YY1788612x0kkYLgk4oD; Wed, 18 Sep 2019 20:51:39 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:39 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pKqn017013 for ; Thu, 19 Sep 2019 03:51:38 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v3vatnf2v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:38 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id B8DE457 for ; Thu, 19 Sep 2019 03:51:37 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id EC79345 for ; Thu, 19 Sep 2019 03:51:36 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 03/14] platforms/RiscV: Initial version of RISC-V platform package Date: Thu, 19 Sep 2019 11:51:20 +0800 Message-Id: <20190919035131.4700-4-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: mQKlddHOD1PCUqQJsUmC8qnRx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865099; bh=xmvWON3bUKJIHxPZUJ1w/vkDCpUrWiTEjXhalGdq93g=; h=Date:From:Reply-To:Subject:To; b=jcXBaM+i5+PmM3VvBC+LrS/pvLT1dtAznTqbiCKyt08HNLsbbEQmr70JHKWuk9xpUb0 6U9hPzwqVzrtT/Czm9CgoaUmzAc1jI7VO4DY/rC0IAT+tZ95GQkBFA1GUbX6wI8pH2KQs RgmuZsJGe1pgla4MGTfGkSdoqH7ZhRvAS1Y= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Initial version of RISC-V platform package which provides the common libraries, drivers, PCD and etc. for RISC-V platform development. Signed-off-by: Gilbert Chen --- Platform/RiscV/Readme.md | 89 ++++++++++++++++++++++++++++= ++++ Platform/RiscV/RiscVPlatformPkg.dec | 72 ++++++++++++++++++++++++++ Platform/RiscV/RiscVPlatformPkg.uni | 15 ++++++ Platform/RiscV/RiscVPlatformPkgExtra.uni | 12 +++++ 4 files changed, 188 insertions(+) create mode 100644 Platform/RiscV/Readme.md create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni diff --git a/Platform/RiscV/Readme.md b/Platform/RiscV/Readme.md new file mode 100644 index 00000000..277782e3 --- /dev/null +++ b/Platform/RiscV/Readme.md @@ -0,0 +1,89 @@ +# Introduction + +## EDK2 RISC-V Platform Package +RISC-V platform package provides the generic and common modules for RISC-V= platforms. RISC-V platform package could include RiscPlatformPkg.dec to us= e the common drivers, libraries, definitions, PCDs and etc. for the platfor= m development. + +## EDK2 RISC-V Platforms +RISC-V platform is created and maintained by RISC-V platform vendors. The = directory of RISC-V platform should be created under Platform/RiscV. Vendor= should create the folder under Platform/RiscV and name it using vendor nam= e, under the vendor folder is the platform folder named by platform model n= ame, code name or etc. (e.g. Platform/RiscV/SiFive/U500Pkg) + +## Build EDK2 RISC-V Platforms +RISC-V platform package should provide EDK2 metafiles under RISC-V platfor= m package folder (Platform/RiscV/{Vendor}/{Platform}). Build RISC-V platfor= m package against edk2 and follow the build guidence mentioned in Readme.md= under below link.
+https://github.com/tianocore/edk2-platforms
+ +### Download the sources ### +``` +git clone https://github.com/tianocore/edk2-staging.git +# Checkout RISC-V-V2 branch +git clone https://github.com/tianocore/edk2-platforms.git +# Checkout devel-riscv-v2 branch +git clone https://github.com/tianocore/edk2-non-osi.git +``` + +### Requirements +Build EDK2 RISC-V platform requires GCC RISC-V toolchain. Refer to https:/= /github.com/riscv/riscv-gnu-toolchain for the details. +The commit ID 64879b24 is verified to build RISC-V EDK2 platform and boot = to EFI SHELL successfully. + +### EDK2 project +Currently, the EDK2 RISC-V platform can only build with edk2 project in **= edk2-staging/RISC-V-V2** branch. The build architecture whcih is supported = and verified so far is "RISCV64". The verified RISC-V toolchain is https://= github.com/riscv/riscv-gnu-toolchain @64879b24, toolchain tag is "GCCRISCV"= declared in tools_def.txt
+ +### Linux Build Instructions +You can build the RISC-V platform using below script,
+`build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t GCCRIS= CV` + +Or modify target.txt to set up your build parameters. + +## RISC-V Platform PCD settings +### EDK2 Firmware Volume Settings +EDK2 Firmware volume related PCDs which declared in platform FDF file. + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdRiscVSecFvBase| The base address of SEC Firmware Volume| +|PcdRiscVSecFvSize| The size of SEC Firmware Volume| +|PcdRiscVPeiFvBase| The base address of SEC Firmware Volume| +|PcdRiscVPeiFvSize| The size of SEC Firmware Volume| +|PcdRiscVDxeFvBase| The base address of SEC Firmware Volume| +|PcdRiscVDxeFvSize| The size of SEC Firmware Volume| + +### EDK2 EFI Variable Region Settings +The PCD settings regard to EFI Variable + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdVariableFdBaseAddress| The EFI variable firmware device base address| +|PcdVariableFdSize| The EFI variable firmware device size| +|PcdVariableFdBlockSize| The block size of EFI variable firmware device| +|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within f= irmware device| +|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable= fault tolerance worksapce (FTW) within firmware device| +|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable s= pare FTW within firmware device| + +### RISC-V Physical Memory Protection (PMP) Region Settings +Below PCDs could be set in platform FDF file. + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdFwStartAddress| The starting address of firmware region to protected b= y PMP| +|PcdFwEndAddress| The ending address of firmware region to protected by PM= P| + +### RISC-V Processor HART Settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementati= on specific| +|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and bo= ot system to OS| + +### RISC-V OpenSBI Settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RIS= C-V HARTs| +|PcdScratchRamSize| The total size of OpenSBI scratch buffer for all RISC-= V HARTs| +|PcdOpenSbiStackSize| The size of initial stack of each RISC-V HART for bo= oting system use OpenSBI| +|PcdTemporaryRamBase| The base address of temporary memory for PEI phase| +|PcdTemporaryRamSize| The temporary memory size for PEI phase| + +## Supported Operating Systems +Only support to boot to EFI Shell so far + +## Known Issues and Limitations +Only RISC-V RV64 is verified diff --git a/Platform/RiscV/RiscVPlatformPkg.dec b/Platform/RiscV/RiscVPlat= formPkg.dec new file mode 100644 index 00000000..3ce16bfc --- /dev/null +++ b/Platform/RiscV/RiscVPlatformPkg.dec @@ -0,0 +1,72 @@ +## @file RiscVPlatformPkg.dec +# This Package provides UEFI RISC-V platform modules and libraries. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D RiscPlatformPkg + PACKAGE_UNI_FILE =3D RiscPlatformPkg.uni + PACKAGE_GUID =3D 6A67AF99-4592-40F8-B6BE-62BCA10DA1EC + PACKAGE_VERSION =3D 1.0 + +[Includes] + Include + +[LibraryClasses] + +[LibraryClasses.RISCV32, LibraryClasses.RISCV64] + +[Guids] + gUefiRiscVPlatformPkgTokenSpaceGuid =3D {0x6A67AF99, 0x4592, 0x40F8, { = 0xB6, 0xBE, 0x62, 0xBC, 0xA1, 0x0D, 0xA1, 0xEC}} + +[PcdsFixedAtBuild] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|0x0|UINT32|0x00001= 000 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvSize|0x0|UINT32|0x00001= 001 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|0x0|UINT32|0x00001= 002 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize|0x0|UINT32|0x00001= 003 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|0x0|UINT32|0x00001= 004 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize|0x0|UINT32|0x00001= 005 + +# +# Definition of EFI Variable region +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress|0|UINT32|0x= 00001010 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize|0|UINT32|0x00001011 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize|0|UINT32|0x00= 001012 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBas= e|0|UINT32|0x00001013 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase|0|UINT32|0x00001014 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBas= e|0|UINT32|0x00001015 +# +# Firmware region which is protected by PMP. +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwBlockSize|0|UINT32|0x00001020 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress|0|UINT32|0x00001021 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress|0|UINT32|0x00001022 +# +# Definition of RISC-V Hart +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount|0|UINT32|0x00001023 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId|0|UINT32|0x00001024 +# +# Definitions for OpenSbi +# + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase|0|UINT32|0x00001025 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize|0|UINT32|0x00001026 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize|0|UINT32|0x00001= 027 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase|0|UINT32|0x00001= 028 + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize|0|UINT32|0x00001= 029 + +[PcdsPatchableInModule] + +[PcdsFeatureFlag] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable|FALSE|BOOLEAN|= 0x00001006 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + +[UserExtensions.TianoCore."ExtraFiles"] + RiscVPlatformPkgExtra.uni diff --git a/Platform/RiscV/RiscVPlatformPkg.uni b/Platform/RiscV/RiscVPlat= formPkg.uni new file mode 100644 index 00000000..deb91fa1 --- /dev/null +++ b/Platform/RiscV/RiscVPlatformPkg.uni @@ -0,0 +1,15 @@ +// /** @file +// RISC-V Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_PACKAGE_ABSTRACT #language en-US "Provides UEFI com= patible RISC-V platform modules and libraries" + +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package prov= ides UEFI compatible RISC-V platform modules and libraries." + + diff --git a/Platform/RiscV/RiscVPlatformPkgExtra.uni b/Platform/RiscV/Risc= VPlatformPkgExtra.uni new file mode 100644 index 00000000..98d81aed --- /dev/null +++ b/Platform/RiscV/RiscVPlatformPkgExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// RISC-V Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_PACKAGE_NAME +#language en-US +"RiscV platform package" --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47536): https://edk2.groups.io/g/devel/message/47536 Mute This Topic: https://groups.io/mt/34196350/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47537+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47537+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865101; cv=none; d=zoho.com; s=zohoarc; b=hCSlXhd4mo7k6R0lpHQBPmuEhSM+tvlSzsjbVMbiuK35Mzj2SdRtTqMl6S6ZOZeTCc+P8uFxl88Bovc3SuqaOPdPk25OWFr2JZRn668Lfhsei8PgrhtECf3jBSCTUYp5VuZU1SnEYX7zW2MSvNt4HlfyNCacu8vH2Wp7cn4a5YY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865101; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=R79Rb2srgC350/e4pcSU84ryDb48xLT2e7YqXTSV83s=; b=JzsYAM6+Hnxlxt81P8zbFiRIvYwELBtdg0zBEol1Io4LcmCcaM0ug0NlZ3Wa3DXjSVe9FjbqvZZy9idxWObYH01TA6jPvw59eU7VnVYThHwM6umzvFXTnVm14tZchAVNQYR5NPBGS7t++hsuj/MxdD3fEf4E2gwl2BJVFokuO2c= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47537+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865101311693.1894561649889; Wed, 18 Sep 2019 20:51:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5oCTYY1788612xVtAby0RzZU; Wed, 18 Sep 2019 20:51:40 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:40 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pdLs030784 for ; Thu, 19 Sep 2019 03:51:39 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vapnb6q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:39 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id 1066F4E for ; Thu, 19 Sep 2019 03:51:39 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 41EB145 for ; Thu, 19 Sep 2019 03:51:38 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 04/14] RiscV/Include: Initial version of header files in RISC-V platform package Date: Thu, 19 Sep 2019 11:51:21 +0800 Message-Id: <20190919035131.4700-5-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: 3USMkio0TtE4P0X9BeeM0NT2x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865100; bh=C8I+kU+vYJ4T3diFOTdY465p1xCyK80zBCpPXdC0gWE=; h=Date:From:Reply-To:Subject:To; b=CbdY8wrnk6mJRBTzSo13DyA0YT66UNFFAQfny5HHFjmxn0htKQvPBo5P4vyqaLBaPiP zL7rpsHuHM/tv1YcRDrPie/BXl9wL/YIXAV9Cif13sblksdJIuqtff+WP26CXd7nc8wfd jy2OIyNSPhuDeNxN9TRRI3SyX9kFfrJ0NLY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" FirmwareContextProcessorSpecificLib.h - The difinitions of Firmware Context EDK2 implementaion based on RISC-V OpenSBI. Signed-off-by: Gilbert Chen --- .../Library/FirmwareContextProcessorSpecificLib.h | 40 ++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) create mode 100644 Platform/RiscV/Include/Library/FirmwareContextProcessor= SpecificLib.h diff --git a/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecifi= cLib.h b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib= .h new file mode 100644 index 00000000..772a0783 --- /dev/null +++ b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h @@ -0,0 +1,40 @@ +/** @file + Firmware Context Processor-specific common library + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H_ +#define _FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H_ + +#include + +/** + Build up common firmware context processor-specific information + + @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTE= XT_HART_SPECIFIC + @param ParentProcessorGuid Pointer to GUID of Processor which = contains this core + @param ParentProcessorUid Unique ID of pysical processor whic= h owns this core. + @param CoreGuid Pointer to GUID of core + @param HartId Hart ID of this core. + @param IsBootHart This is boot hart or not + @param ProcessorSpecDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB + + @return EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +CommonFirmwareContextHartSpecificInfo ( + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific, + EFI_GUID *ParentProcessorGuid, + UINTN ParentProcessorUid, + EFI_GUID *CoreGuid, + UINTN HartId, + BOOLEAN IsBootHart, + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob + ); + +#endif --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47537): https://edk2.groups.io/g/devel/message/47537 Mute This Topic: https://groups.io/mt/34196351/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47538+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47538+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865102; cv=none; d=zoho.com; s=zohoarc; b=H4fnRT3BULjfY83FO9MliGdrCFUzyicqxMEiMCSzjqJWiSwrYC+jCTZpyW9GfGIeXFqP3B3U+aU3Y6b5+fhley7+QpApvBfu6i3KtWFjQO4vte+0MyAwCLX/+C8wlC263TT9efBbcka8WlDpGm43JfhQ4SUfBY8FejeWSsmnPsg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865102; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=fE8D24At+VYsxEoKG/CAVMswUsmL/XB+Di8QK6SlLKg=; b=ZD+6I67fTyT8RvXupybqw/izPQoNTKBcLrbPZV500tlAxXpgwgViowO1h+2ZwoJIpWfKIuco43ZquFJpPG5/pdpylW/1MOg+WankmA256wsskiqsKWHw9F7ky0eSf/twet1P6miBMbFO51xAOdBLiVMIqYpQSZ6jZoHofEVgLy8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47538+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865102809268.3263009508232; Wed, 18 Sep 2019 20:51:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id u1PJYY1788612xvZmsZjhMJN; Wed, 18 Sep 2019 20:51:42 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:42 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pf7v013413 for ; Thu, 19 Sep 2019 03:51:41 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0b-002e3701.pphosted.com with ESMTP id 2v3vapdarg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:41 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id 5918F8D for ; Thu, 19 Sep 2019 03:51:40 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 8C4E445 for ; Thu, 19 Sep 2019 03:51:39 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 05/14] RiscV/Library: Initial version of libraries introduced in RISC-V platform package Date: Thu, 19 Sep 2019 11:51:22 +0800 Message-Id: <20190919035131.4700-6-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: XaoW7k8Gb0MqgCDYEirN7zChx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865102; bh=H5/sPcYytLu66EclnbSISxSUqKPIm15QOudV+A20Ego=; h=Date:From:Reply-To:Subject:To; b=iP+0HM/s8j5YNecLMe7z9eyFwJy9YMKRPzONZrL8EK/XyQMzGTIapCcGMt7Z6YixBue TypPe86U0dVnnobudPW8XGVuraGHynmjL2xinOml29VwGBYJI1TPqlDyaQZzmY+cx1qoO JKJUPXlJc+erjAKmjOWFoRYQVvnXFypFio0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" FirmwareContextProcessorSpecificLib - Common library to consume EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC and build up processor specific data HOB. RealTimClockLibNull - NULL instance of Real Time Clock library. Signed-off-by: Gilbert Chen --- .../FirmwareContextProcessorSpecificLib.c | 82 +++++++++ .../FirmwareContextProcessorSpecificLib.inf | 33 ++++ .../RealTimeClockLibNull/RealTimeClockLibNull.c | 204 +++++++++++++++++= ++++ .../RealTimeClockLibNull/RealTimeClockLibNull.inf | 30 +++ 4 files changed, 349 insertions(+) create mode 100644 Platform/RiscV/Library/FirmwareContextProcessorSpecific= Lib/FirmwareContextProcessorSpecificLib.c create mode 100644 Platform/RiscV/Library/FirmwareContextProcessorSpecific= Lib/FirmwareContextProcessorSpecificLib.inf create mode 100644 Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClo= ckLibNull.c create mode 100644 Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClo= ckLibNull.inf diff --git a/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/Fir= mwareContextProcessorSpecificLib.c b/Platform/RiscV/Library/FirmwareContext= ProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c new file mode 100644 index 00000000..4d4c51dc --- /dev/null +++ b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareCo= ntextProcessorSpecificLib.c @@ -0,0 +1,82 @@ +/**@file + Common library to build upfirmware context processor-specific information + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +/** + Build up common firmware context processor-specific information + + @param FirmwareContextHartSpecific Pointer to EFI_RISCV_FIRMWARE_CONTE= XT_HART_SPECIFIC + @param ParentProcessorGuid Pointer to GUID of Processor which = contains this core + @param ParentProcessorUid Unique ID of pysical processor whic= h owns this core. + @param CoreGuid Pointer to GUID of core + @param HartId Hart ID of this core. + @param IsBootHart This is boot hart or not + @param ProcessorSpecDataHob Pointer to RISC_V_PROCESSOR_SPECIFI= C_DATA_HOB + + @return EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +CommonFirmwareContextHartSpecificInfo ( + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific, + EFI_GUID *ParentProcessorGuid, + UINTN ParentProcessorUid, + EFI_GUID *CoreGuid, + UINTN HartId, + BOOLEAN IsBootHart, + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob + ) +{ + // + // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB. + // + CopyGuid (&ProcessorSpecDataHob->ParentPrcessorGuid, ParentProcessorGuid= ); + ProcessorSpecDataHob->ParentProcessorUid =3D ParentProcessorUid; + CopyGuid (&ProcessorSpecDataHob->CoreGuid, CoreGuid); + ProcessorSpecDataHob->Context =3D NULL; + ProcessorSpecDataHob->ProcessorSpecificData.Revision =3D SMBIOS_= RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION; + ProcessorSpecDataHob->ProcessorSpecificData.Length =3D sizeof = (SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA); + ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_L =3D (UINT64= )HartId; + ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_H =3D 0; + ProcessorSpecDataHob->ProcessorSpecificData.BootHartId =3D (UINT8)= IsBootHart; + ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported =3D Firmwar= eContextHartSpecific->IsaExtensionSupported; + ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported =3D= SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED; + if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported & RISC= _V_ISA_SUPERVISOR_MODE_IMPLEMENTED) !=3D 0) { + ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |= =3D SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED; + } + if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported & RISC= _V_ISA_USER_MODE_IMPLEMENTED) !=3D 0) { + ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |= =3D SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED; + } + ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_L = =3D FirmwareContextHartSpecific->MachineVendorId.Value64_L; + ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_H = =3D FirmwareContextHartSpecific->MachineVendorId.Value64_H; + ProcessorSpecDataHob->ProcessorSpecificData.MachineArchId.Value64_L =3D = FirmwareContextHartSpecific->MachineArchId.Value64_L; + ProcessorSpecDataHob->ProcessorSpecificData.MachineArchId.Value64_H =3D = FirmwareContextHartSpecific->MachineArchId.Value64_H; + ProcessorSpecDataHob->ProcessorSpecificData.MachineImplId.Value64_L =3D = FirmwareContextHartSpecific->MachineImplId.Value64_L; + ProcessorSpecDataHob->ProcessorSpecificData.MachineImplId.Value64_H =3D = FirmwareContextHartSpecific->MachineImplId.Value64_H; + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/Fir= mwareContextProcessorSpecificLib.inf b/Platform/RiscV/Library/FirmwareConte= xtProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf new file mode 100644 index 00000000..ff841c3e --- /dev/null +++ b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareCo= ntextProcessorSpecificLib.inf @@ -0,0 +1,33 @@ +#/** @file +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D FirmwareContextProcessorSpecificLib + FILE_GUID =3D 8BEC9FD7-C554-403A-94F1-0EBBFD81A242 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FirmwareContextProcessorSpecificLib + +[Sources.common] + FirmwareContextProcessorSpecificLib.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Silicon/SiFive/SiFive.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + +[Pcd] + diff --git a/Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNu= ll.c b/Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.c new file mode 100644 index 00000000..904e7e7b --- /dev/null +++ b/Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.c @@ -0,0 +1,204 @@ +/** @file + EFI RealTimeClock NULL library + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +// Use EfiAtRuntime to check stage +#include +#include +#include +#include + + +/** + Returns the current time and date information, and the time-keeping capa= bilities + of the hardware platform. + + @param Time A pointer to storage to receive a snapsho= t of the current time. + @param Capabilities An optional pointer to a buffer to receiv= e the real time clock + device's capabilities. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER Time is NULL. + @retval EFI_DEVICE_ERROR The time could not be retrieved due to ha= rdware error. + @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an= authentication failure. +**/ +EFI_STATUS +EFIAPI +LibGetTime ( + OUT EFI_TIME *Time, + OUT EFI_TIME_CAPABILITIES *Capabilities + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + + return Status; + +} + + +/** + Sets the current local time and date information. + + @param Time A pointer to the current time. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The time could not be set due due to hardw= are error. + +**/ +EFI_STATUS +EFIAPI +LibSetTime ( + IN EFI_TIME *Time + ) +{ + + EFI_STATUS Status =3D EFI_SUCCESS; + + + return Status; +} + + +/** + Returns the current wakeup alarm clock setting. + + @param Enabled Indicates if the alarm is currently enable= d or disabled. + @param Pending Indicates if the alarm signal is pending a= nd requires acknowledgement. + @param Time The current alarm setting. + + @retval EFI_SUCCESS The alarm settings were returned. + @retval EFI_INVALID_PARAMETER Any parameter is NULL. + @retval EFI_DEVICE_ERROR The wakeup time could not be retrieved due= to a hardware error. + +**/ +EFI_STATUS +EFIAPI +LibGetWakeupTime ( + OUT BOOLEAN *Enabled, + OUT BOOLEAN *Pending, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + + +/** + Sets the system wakeup alarm clock time. + + @param Enabled Enable or disable the wakeup alarm. + @param Time If Enable is TRUE, the time to set the wak= eup alarm for. + + @retval EFI_SUCCESS If Enable is TRUE, then the wakeup alarm w= as enabled. If + Enable is FALSE, then the wakeup alarm was= disabled. + @retval EFI_INVALID_PARAMETER A time field is out of range. + @retval EFI_DEVICE_ERROR The wakeup time could not be set due to a = hardware error. + @retval EFI_UNSUPPORTED A wakeup timer is not supported on this pl= atform. + +**/ +EFI_STATUS +EFIAPI +LibSetWakeupTime ( + IN BOOLEAN Enabled, + OUT EFI_TIME *Time + ) +{ + // Not a required feature + return EFI_UNSUPPORTED; +} + + + +/** + This is the declaration of an EFI image entry point. This can be the ent= ry point to an application + written to this specification, an EFI boot service driver, or an EFI run= time driver. + + @param ImageHandle Handle that identifies the loaded image. + @param SystemTable System Table for this image. + + @retval EFI_SUCCESS The operation completed successfully. + +**/ +EFI_STATUS +EFIAPI +LibRtcInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + + EFI_TIME EfiTime; + + // Setup the setters and getters + gRT->GetTime =3D LibGetTime; + gRT->SetTime =3D LibSetTime; + gRT->GetWakeupTime =3D LibGetWakeupTime; + gRT->SetWakeupTime =3D LibSetWakeupTime; + + + (VOID)gRT->GetTime (&EfiTime, NULL); + if((EfiTime.Year < 2015) || (EfiTime.Year > 2099)){ + EfiTime.Year =3D 2015; + EfiTime.Month =3D 1; + EfiTime.Day =3D 1; + EfiTime.Hour =3D 0; + EfiTime.Minute =3D 0; + EfiTime.Second =3D 0; + EfiTime.Nanosecond =3D 0; + Status =3D gRT->SetTime(&EfiTime); + if (EFI_ERROR(Status)) + { + DEBUG((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n", __FUNCTION__, __LI= NE__, Status)); + } + } + + // Install the protocol + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiRealTimeClockArchProtocolGuid, NULL, + NULL + ); + + return Status; +} + + +/** + Fixup internal data so that EFI can be call in virtual mode. + Call the passed in Child Notify event and convert any pointers in + lib to virtual mode. + + @param[in] Event The Event that is being processed + @param[in] Context Event Context +**/ +VOID +EFIAPI +LibRtcVirtualNotifyEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + // + // Only needed if you are going to support the OS calling RTC functions = in virtual mode. + // You will need to call EfiConvertPointer (). To convert any stored phy= sical addresses + // to virtual address. After the OS transitions to calling in virtual mo= de, all future + // runtime calls will be made in virtual mode. + // + return; +} diff --git a/Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNu= ll.inf b/Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.i= nf new file mode 100644 index 00000000..21b2e435 --- /dev/null +++ b/Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf @@ -0,0 +1,30 @@ +#/** @file +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RealTimeClockLibNull + FILE_GUID =3D BFC3E25A-8AD0-4201-8A75-F00DE7964370 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RealTimeClockLib + +[Sources.common] + RealTimeClockLibNull.c + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiLib + DebugLib +# Use EFiAtRuntime to check stage + UefiRuntimeLib + +[Pcd] + --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47538): https://edk2.groups.io/g/devel/message/47538 Mute This Topic: https://groups.io/mt/34196352/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47539+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47539+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865105; cv=none; d=zoho.com; s=zohoarc; b=XlKNAeLX+sVCwcv7M4GvgAWA1fWdpU3vaqil1E5rur7fixipdO8ghBFMAzb05mSfBaLCTPXwUAnrEnzZ1Q77N8ZwBmSOsE7n4LT/8WBITf2NB+pQv9lz4668qGoDHscBPzvnUlw2Y3JTte93eynI3eA487h1FIb9RVUq2l1wA9s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865105; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=EVX+fvAAIeH6ZNAK8Lj/kGQUceu/qyI0f48a8Nseqlk=; b=eKMMznZbDWe6wiBuOzxxc8kecyt4LM2scfsBhlWJZmDIIjit/5eqIJVwo0Zvxl+xHcKb+KgSCGAN6R/JX+aQx4+9nYbGanZmJ15rC8k1hPjZsLvXiLo9zX2DJzy0yRD3C/nD1O8Kb5qHB9Mhi++lpaz1YxlaAhSUXQT5XAsd87c= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47539+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865105122348.6197735035686; Wed, 18 Sep 2019 20:51:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id goQWYY1788612xi9Vsafo2uv; Wed, 18 Sep 2019 20:51:44 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:43 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pK3C021143 for ; Thu, 19 Sep 2019 03:51:42 GMT X-Received: from g4t3425.houston.hpe.com (g4t3425.houston.hpe.com [15.241.140.78]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vaqnkbw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:42 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3425.houston.hpe.com (Postfix) with ESMTP id A37038D for ; Thu, 19 Sep 2019 03:51:41 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id D655B45 for ; Thu, 19 Sep 2019 03:51:40 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 06/14] RiscV/Universal: Initial version of common RISC-V SEC module Date: Thu, 19 Sep 2019 11:51:23 +0800 Message-Id: <20190919035131.4700-7-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: h7smEJWa0ipamlmb96XIcqNsx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865104; bh=T0rVngsJrHk6FZtuWrBnoeyQt0xCjVQVEsuuVefEfho=; h=Date:From:Reply-To:Subject:To; b=aR7UTF2yz+LJVbkhK5qIG5UqioJAGgaWxagEMcWSYDTu3H37qUI12bTozUGwErrydd1 0VwKjTO5ePwkYPBytjaW2Sv4l4m6juLFUHUso5l3d76u7DxsxNHjpRK5m0ginjGld6EM1 chRbhDxDEtly9fAj4QSzd1H3jEX686kJt9s= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Common RISC-V SEC module for RISC-V platforms. Signed-off-by: Gilbert Chen --- Platform/RiscV/Universal/Sec/Riscv64/SecEntry.S | 438 ++++++++++++++++++++ Platform/RiscV/Universal/Sec/SecMain.c | 524 ++++++++++++++++++++= ++++ Platform/RiscV/Universal/Sec/SecMain.h | 57 +++ Platform/RiscV/Universal/Sec/SecMain.inf | 75 ++++ 4 files changed, 1094 insertions(+) create mode 100644 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.S create mode 100644 Platform/RiscV/Universal/Sec/SecMain.c create mode 100644 Platform/RiscV/Universal/Sec/SecMain.h create mode 100644 Platform/RiscV/Universal/Sec/SecMain.inf diff --git a/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.S b/Platform/Ris= cV/Universal/Sec/Riscv64/SecEntry.S new file mode 100644 index 00000000..18b54b84 --- /dev/null +++ b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.S @@ -0,0 +1,438 @@ +/* + * Copyright (c) 2019 , Hewlett Packard Enterprise Development LP. All rig= hts reserved. + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Anup Patel + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +.text +.align 3 +.global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + /* + * Jump to warm-boot if this is not the selected core booting, + */ + csrr a6, CSR_MHARTID + li a5, FixedPcdGet32 (PcdBootHartId) + bne a6, a5, _wait_for_boot_hart + + // light LED on + li a5, 0x54002000 + li a4, 0xff + sw a4, 0x08(a5) + li a4, 0x11 + sw a4, 0x0c(a5) + + li ra, 0 + call _reset_regs + + /* Preload HART details + * s7 -> HART Count + * s8 -> HART Stack Size + */ + li s7, FixedPcdGet32 (PcdHartCount) + li s8, FixedPcdGet32 (PcdOpenSbiStackSize) + + /* Setup scratch space for all the HARTs*/ + li tp, FixedPcdGet32 (PcdScratchRamBase) + mul a5, s7, s8 + add tp, tp, a5 + /* Keep a copy of tp */ + add t3, tp, zero + /* Counter */ + li t2, 1 + /* hartid 0 is mandated by ISA */ + li t1, 0 +_scratch_init: + add tp, t3, zero + mul a5, s8, t1 + sub tp, tp, a5 + li a5, SBI_SCRATCH_SIZE + sub tp, tp, a5 + + /* Initialize scratch space */ + li a4, FixedPcdGet32 (PcdFwStartAddress) + li a5, FixedPcdGet32 (PcdFwEndAddress) + sub a5, a5, a4 + sd a4, SBI_SCRATCH_FW_START_OFFSET(tp) + sd a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp) + /* Note: fw_next_arg1() uses a0, a1, and ra */ + call fw_next_arg1 + sd a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp) + /* Note: fw_next_addr() uses a0, a1, and ra */ + call fw_next_addr + sd a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp) + li a4, PRV_S + sd a4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp) + la a4, _start_warm + sd a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp) + la a4, platform + sd a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp) + la a4, _hartid_to_scratch + sd a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp) + sd zero, SBI_SCRATCH_TMP0_OFFSET(tp) +#ifdef FW_OPTIONS + li a4, FW_OPTIONS + sd a4, SBI_SCRATCH_OPTIONS_OFFSET(tp) +#else + sd zero, SBI_SCRATCH_OPTIONS_OFFSET(tp) +#endif + add t1, t1, t2 + blt t1, s7, _scratch_init + + /* Fill-out temporary memory with 55aa*/ + li a4, FixedPcdGet32 (PcdTemporaryRamBase) + li a5, FixedPcdGet32 (PcdTemporaryRamSize) + add a5, a4, a5 +1: + li a3, 0x5AA55AA55AA55AA5 + sd a3, (a4) + add a4, a4, __SIZEOF_POINTER__ + blt a4, a5, 1b + + /* Update boot hart flag */ + la a4, _boot_hart_done + li a5, 1 + sd a5, (a4) + + /* Wait for boot hart */ +_wait_for_boot_hart: + la a4, _boot_hart_done + ld a5, (a4) + /* Reduce the bus traffic so that boot hart may proceed faster */ + nop + nop + nop + beqz a5, _wait_for_boot_hart + +_start_warm: + li ra, 0 + call _reset_regs + + /* Disable and clear all interrupts */ + csrw CSR_MIE, zero + csrw CSR_MIP, zero + + li s7, FixedPcdGet32 (PcdHartCount) + li s8, FixedPcdGet32 (PcdOpenSbiStackSize) + + /* HART ID should be within expected limit */ + csrr s6, CSR_MHARTID + bge s6, s7, _start_hang + + /* find the scratch space for this hart */ + li tp, FixedPcdGet32 (PcdScratchRamBase) + mul a5, s7, s8 + add tp, tp, a5 + mul a5, s8, s6 + sub tp, tp, a5 + li a5, SBI_SCRATCH_SIZE + sub tp, tp, a5 + + /* update the mscratch */ + csrw CSR_MSCRATCH, tp + + /*make room for Hart specific Firmware Context*/ + li a5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE + sub tp, tp, a5 + + /* Setup stack */ + add sp, tp, zero + + /* Setup stack for the Hart executing EFI to top of temporary ram*/ + csrr a6, CSR_MHARTID + li a5, FixedPcdGet32 (PcdBootHartId) + bne a6, a5, 1f + + li a4, FixedPcdGet32(PcdTemporaryRamBase) + li a5, FixedPcdGet32(PcdTemporaryRamSize) + add sp, a4, a5 + 1: + + /* Setup trap handler */ + la a4, _trap_handler + csrw CSR_MTVEC, a4 + /* Make sure that mtvec is updated */ + 1: + csrr a5, CSR_MTVEC + bne a4, a5, 1b + + /* Call library constructors before jup to SEC core */ + call ProcessLibraryConstructorList + + /* jump to SEC Core C */ + csrr a0, CSR_MHARTID + csrr a1, CSR_MSCRATCH + call SecCoreStartUpWithStack + + /* We do not expect to reach here hence just hang */ + j _start_hang + + .align 3 + .section .data, "aw" +_boot_hart_done: + RISCV_PTR 0 + + .align 3 + .section .entry, "ax", %progbits + .globl _hartid_to_scratch +_hartid_to_scratch: + add sp, sp, -(3 * __SIZEOF_POINTER__) + sd s0, (sp) + sd s1, (__SIZEOF_POINTER__)(sp) + sd s2, (__SIZEOF_POINTER__ * 2)(sp) + /* + * a0 -> HART ID (passed by caller) + * s0 -> HART Stack Size + * s1 -> HART Stack End + * s2 -> Temporary + */ + la s2, platform +#if __riscv_xlen =3D=3D 64 + lwu s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) + lwu s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2) +#else + lw s0, SBI_PLATFORM_HART_STACK_SIZE_OFFSET(s2) + lw s2, SBI_PLATFORM_HART_COUNT_OFFSET(s2) +#endif + mul s2, s2, s0 + li s1, FixedPcdGet32 (PcdScratchRamBase) + add s1, s1, s2 + mul s2, s0, a0 + sub s1, s1, s2 + li s2, SBI_SCRATCH_SIZE + sub a0, s1, s2 + ld s0, (sp) + ld s1, (__SIZEOF_POINTER__)(sp) + ld s2, (__SIZEOF_POINTER__ * 2)(sp) + add sp, sp, (3 * __SIZEOF_POINTER__) + ret + + .align 3 + .section .entry, "ax", %progbits + .globl _start_hang +_start_hang: + wfi + j _start_hang + + .align 3 + .section .entry, "ax", %progbits + .globl _trap_handler +_trap_handler: + /* Swap TP and MSCRATCH */ + csrrw tp, CSR_MSCRATCH, tp + + /* Save T0 in scratch space */ + sd t0, SBI_SCRATCH_TMP0_OFFSET(tp) + + /* Check which mode we came from */ + csrr t0, CSR_MSTATUS + srl t0, t0, MSTATUS_MPP_SHIFT + and t0, t0, PRV_M + xori t0, t0, PRV_M + beq t0, zero, _trap_handler_m_mode + + /* We came from S-mode or U-mode */ +_trap_handler_s_mode: + /* Set T0 to original SP */ + add t0, sp, zero + + /* Setup exception stack */ + add sp, tp, -(SBI_TRAP_REGS_SIZE) + + /* Jump to code common for all modes */ + j _trap_handler_all_mode + + /* We came from M-mode */ +_trap_handler_m_mode: + /* Set T0 to original SP */ + add t0, sp, zero + + /* Re-use current SP as exception stack */ + add sp, sp, -(SBI_TRAP_REGS_SIZE) + +_trap_handler_all_mode: + /* Save original SP (from T0) on stack */ + sd t0, SBI_TRAP_REGS_OFFSET(sp)(sp) + + /* Restore T0 from scratch space */ + ld t0, SBI_SCRATCH_TMP0_OFFSET(tp) + + /* Save T0 on stack */ + sd t0, SBI_TRAP_REGS_OFFSET(t0)(sp) + + /* Swap TP and MSCRATCH */ + csrrw tp, CSR_MSCRATCH, tp + + /* Save MEPC and MSTATUS CSRs */ + csrr t0, CSR_MEPC + sd t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) + csrr t0, CSR_MSTATUS + sd t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) + + /* Save all general regisers except SP and T0 */ + sd zero, SBI_TRAP_REGS_OFFSET(zero)(sp) + sd ra, SBI_TRAP_REGS_OFFSET(ra)(sp) + sd gp, SBI_TRAP_REGS_OFFSET(gp)(sp) + sd tp, SBI_TRAP_REGS_OFFSET(tp)(sp) + sd t1, SBI_TRAP_REGS_OFFSET(t1)(sp) + sd t2, SBI_TRAP_REGS_OFFSET(t2)(sp) + sd s0, SBI_TRAP_REGS_OFFSET(s0)(sp) + sd s1, SBI_TRAP_REGS_OFFSET(s1)(sp) + sd a0, SBI_TRAP_REGS_OFFSET(a0)(sp) + sd a1, SBI_TRAP_REGS_OFFSET(a1)(sp) + sd a2, SBI_TRAP_REGS_OFFSET(a2)(sp) + sd a3, SBI_TRAP_REGS_OFFSET(a3)(sp) + sd a4, SBI_TRAP_REGS_OFFSET(a4)(sp) + sd a5, SBI_TRAP_REGS_OFFSET(a5)(sp) + sd a6, SBI_TRAP_REGS_OFFSET(a6)(sp) + sd a7, SBI_TRAP_REGS_OFFSET(a7)(sp) + sd s2, SBI_TRAP_REGS_OFFSET(s2)(sp) + sd s3, SBI_TRAP_REGS_OFFSET(s3)(sp) + sd s4, SBI_TRAP_REGS_OFFSET(s4)(sp) + sd s5, SBI_TRAP_REGS_OFFSET(s5)(sp) + sd s6, SBI_TRAP_REGS_OFFSET(s6)(sp) + sd s7, SBI_TRAP_REGS_OFFSET(s7)(sp) + sd s8, SBI_TRAP_REGS_OFFSET(s8)(sp) + sd s9, SBI_TRAP_REGS_OFFSET(s9)(sp) + sd s10, SBI_TRAP_REGS_OFFSET(s10)(sp) + sd s11, SBI_TRAP_REGS_OFFSET(s11)(sp) + sd t3, SBI_TRAP_REGS_OFFSET(t3)(sp) + sd t4, SBI_TRAP_REGS_OFFSET(t4)(sp) + sd t5, SBI_TRAP_REGS_OFFSET(t5)(sp) + sd t6, SBI_TRAP_REGS_OFFSET(t6)(sp) + + /* Call C routine */ + add a0, sp, zero + csrr a1, CSR_MSCRATCH + call sbi_trap_handler + + /* Restore all general regisers except SP and T0 */ + ld ra, SBI_TRAP_REGS_OFFSET(ra)(sp) + ld gp, SBI_TRAP_REGS_OFFSET(gp)(sp) + ld tp, SBI_TRAP_REGS_OFFSET(tp)(sp) + ld t1, SBI_TRAP_REGS_OFFSET(t1)(sp) + ld t2, SBI_TRAP_REGS_OFFSET(t2)(sp) + ld s0, SBI_TRAP_REGS_OFFSET(s0)(sp) + ld s1, SBI_TRAP_REGS_OFFSET(s1)(sp) + ld a0, SBI_TRAP_REGS_OFFSET(a0)(sp) + ld a1, SBI_TRAP_REGS_OFFSET(a1)(sp) + ld a2, SBI_TRAP_REGS_OFFSET(a2)(sp) + ld a3, SBI_TRAP_REGS_OFFSET(a3)(sp) + ld a4, SBI_TRAP_REGS_OFFSET(a4)(sp) + ld a5, SBI_TRAP_REGS_OFFSET(a5)(sp) + ld a6, SBI_TRAP_REGS_OFFSET(a6)(sp) + ld a7, SBI_TRAP_REGS_OFFSET(a7)(sp) + ld s2, SBI_TRAP_REGS_OFFSET(s2)(sp) + ld s3, SBI_TRAP_REGS_OFFSET(s3)(sp) + ld s4, SBI_TRAP_REGS_OFFSET(s4)(sp) + ld s5, SBI_TRAP_REGS_OFFSET(s5)(sp) + ld s6, SBI_TRAP_REGS_OFFSET(s6)(sp) + ld s7, SBI_TRAP_REGS_OFFSET(s7)(sp) + ld s8, SBI_TRAP_REGS_OFFSET(s8)(sp) + ld s9, SBI_TRAP_REGS_OFFSET(s9)(sp) + ld s10, SBI_TRAP_REGS_OFFSET(s10)(sp) + ld s11, SBI_TRAP_REGS_OFFSET(s11)(sp) + ld t3, SBI_TRAP_REGS_OFFSET(t3)(sp) + ld t4, SBI_TRAP_REGS_OFFSET(t4)(sp) + ld t5, SBI_TRAP_REGS_OFFSET(t5)(sp) + ld t6, SBI_TRAP_REGS_OFFSET(t6)(sp) + + /* Restore MEPC and MSTATUS CSRs */ + ld t0, SBI_TRAP_REGS_OFFSET(mepc)(sp) + csrw CSR_MEPC, t0 + ld t0, SBI_TRAP_REGS_OFFSET(mstatus)(sp) + csrw CSR_MSTATUS, t0 + + /* Restore T0 */ + ld t0, SBI_TRAP_REGS_OFFSET(t0)(sp) + + /* Restore SP */ + ld sp, SBI_TRAP_REGS_OFFSET(sp)(sp) + + mret + + .align 3 + .section .entry, "ax", %progbits + .globl _reset_regs +_reset_regs: + + /* flush the instruction cache */ + fence.i + /* Reset all registers except ra, a0,a1 */ + li sp, 0 + li gp, 0 + li tp, 0 + li t0, 0 + li t1, 0 + li t2, 0 + li s0, 0 + li s1, 0 + li a2, 0 + li a3, 0 + li a4, 0 + li a5, 0 + li a6, 0 + li a7, 0 + li s2, 0 + li s3, 0 + li s4, 0 + li s5, 0 + li s6, 0 + li s7, 0 + li s8, 0 + li s9, 0 + li s10, 0 + li s11, 0 + li t3, 0 + li t4, 0 + li t5, 0 + li t6, 0 + csrw CSR_MSCRATCH, 0 + ret + + .align 3 + .section .entry, "ax", %progbits + .global fw_prev_arg1 +fw_prev_arg1: + /* We return previous arg1 in 'a0' */ + add a0, zero, zero + ret + + .align 3 + .section .entry, "ax", %progbits + .global fw_next_arg1 +fw_next_arg1: + /* We return next arg1 in 'a0' */ + li a0, FixedPcdGet32(PcdRiscVPeiFvBase) + ret + + .align 3 + .section .entry, "ax", %progbits + .global fw_next_addr +fw_next_addr: + /* We return next address in 'a0' */ + la a0, _jump_addr + ld a0, (a0) + ret + + .align 3 + .section .entry, "ax", %progbits +_jump_addr: + RISCV_PTR SecCoreStartUpWithStack diff --git a/Platform/RiscV/Universal/Sec/SecMain.c b/Platform/RiscV/Univer= sal/Sec/SecMain.c new file mode 100644 index 00000000..40b351ca --- /dev/null +++ b/Platform/RiscV/Universal/Sec/SecMain.c @@ -0,0 +1,524 @@ +/** @file + RISC-V SEC phase module. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +int HartsIn =3D 0; + +EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi =3D { + TemporaryRamMigration +}; + +EFI_PEI_TEMPORARY_RAM_DONE_PPI mTemporaryRamDonePpi =3D { + TemporaryRamDone +}; + +EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiTemporaryRamSupportPpiGuid, + &mTemporaryRamSupportPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiTemporaryRamDonePpiGuid, + &mTemporaryRamDonePpi + }, +}; + +/** + Locates a section within a series of sections + with the specified section type. + + The Instance parameter indicates which instance of the section + type to return. (0 is first instance, 1 is second...) + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[in] Instance The section instance number + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInstance ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + IN UINTN Instance, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_PHYSICAL_ADDRESS CurrentAddress; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfSections; + EFI_COMMON_SECTION_HEADER *Section; + EFI_PHYSICAL_ADDRESS EndOfSection; + + // + // Loop through the FFS file sections within the PEI Core FFS file + // + EndOfSection =3D (EFI_PHYSICAL_ADDRESS)(UINTN) Sections; + EndOfSections =3D EndOfSection + SizeOfSections; + for (;;) { + if (EndOfSection =3D=3D EndOfSections) { + break; + } + CurrentAddress =3D (EndOfSection + 3) & ~(3ULL); + if (CurrentAddress >=3D EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + Section =3D (EFI_COMMON_SECTION_HEADER*)(UINTN) CurrentAddress; + + Size =3D SECTION_SIZE (Section); + if (Size < sizeof (*Section)) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfSection =3D CurrentAddress + Size; + if (EndOfSection > EndOfSections) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the requested section type + // + if (Section->Type =3D=3D SectionType) { + if (Instance =3D=3D 0) { + *FoundSection =3D Section; + return EFI_SUCCESS; + } else { + Instance--; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Locates a section within a series of sections + with the specified section type. + + @param[in] Sections The sections to search + @param[in] SizeOfSections Total size of all sections + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsSectionInSections ( + IN VOID *Sections, + IN UINTN SizeOfSections, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + return FindFfsSectionInstance ( + Sections, + SizeOfSections, + SectionType, + 0, + FoundSection + ); +} + +/** + Locates a FFS file with the specified file type and a section + within that file with the specified section type. + + @param[in] Fv The firmware volume to search + @param[in] FileType The file type to locate + @param[in] SectionType The section type to locate + @param[out] FoundSection The FFS section if found + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindFfsFileAndSection ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + IN EFI_FV_FILETYPE FileType, + IN EFI_SECTION_TYPE SectionType, + OUT EFI_COMMON_SECTION_HEADER **FoundSection + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS CurrentAddress; + EFI_PHYSICAL_ADDRESS EndOfFirmwareVolume; + EFI_FFS_FILE_HEADER *File; + UINT32 Size; + EFI_PHYSICAL_ADDRESS EndOfFile; + + if (Fv->Signature !=3D EFI_FVH_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "FV at %p does not have FV header signature\n", F= v)); + return EFI_VOLUME_CORRUPTED; + } + + CurrentAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN) Fv; + EndOfFirmwareVolume =3D CurrentAddress + Fv->FvLength; + + // + // Loop through the FFS files in the Boot Firmware Volume + // + for (EndOfFile =3D CurrentAddress + Fv->HeaderLength; ; ) { + + CurrentAddress =3D (EndOfFile + 7) & ~(7ULL); + if (CurrentAddress > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + File =3D (EFI_FFS_FILE_HEADER*)(UINTN) CurrentAddress; + Size =3D *(UINT32*) File->Size & 0xffffff; + if (Size < (sizeof (*File) + sizeof (EFI_COMMON_SECTION_HEADER))) { + return EFI_VOLUME_CORRUPTED; + } + + EndOfFile =3D CurrentAddress + Size; + if (EndOfFile > EndOfFirmwareVolume) { + return EFI_VOLUME_CORRUPTED; + } + + // + // Look for the request file type + // + if (File->Type !=3D FileType) { + continue; + } + + Status =3D FindFfsSectionInSections ( + (VOID*) (File + 1), + (UINTN) EndOfFile - (UINTN) (File + 1), + SectionType, + FoundSection + ); + if (!EFI_ERROR (Status) || (Status =3D=3D EFI_VOLUME_CORRUPTED)) { + return Status; + } + } +} + +/** + Locates the PEI Core entry point address + + @param[in] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +EFI_STATUS +FindPeiCoreImageBaseInFv ( + IN EFI_FIRMWARE_VOLUME_HEADER *Fv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + EFI_STATUS Status; + EFI_COMMON_SECTION_HEADER *Section; + + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_PE32, + &Section + ); + if (EFI_ERROR (Status)) { + Status =3D FindFfsFileAndSection ( + Fv, + EFI_FV_FILETYPE_PEI_CORE, + EFI_SECTION_TE, + &Section + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Unable to find PEI Core image\n")); + return Status; + } + } + DEBUG ((DEBUG_ERROR, "PeiCoreImageBase found\n")); + *PeiCoreImageBase =3D (EFI_PHYSICAL_ADDRESS)(UINTN)(Section + 1); + return EFI_SUCCESS; +} + +/** + Locates the PEI Core entry point address + + @param[in,out] Fv The firmware volume to search + @param[out] PeiCoreEntryPoint The entry point of the PEI Core image + + @retval EFI_SUCCESS The file and section was found + @retval EFI_NOT_FOUND The file and section was not found + @retval EFI_VOLUME_CORRUPTED The firmware volume was corrupted + +**/ +VOID +FindPeiCoreImageBase ( + IN OUT EFI_FIRMWARE_VOLUME_HEADER **BootFv, + OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase + ) +{ + *PeiCoreImageBase =3D 0; + + DEBUG ((DEBUG_INFO, "FindPeiCoreImageBaseInFv\n")); + FindPeiCoreImageBaseInFv (*BootFv, PeiCoreImageBase); +} + +/* + Find and return Pei Core entry point. + + It also find SEC and PEI Core file debug inforamtion. It will report the= m if + remote debug is enabled. + +**/ +VOID +FindAndReportEntryPoints ( + IN EFI_FIRMWARE_VOLUME_HEADER **BootFirmwareVolumePtr, + OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PeiCoreImageBase; + + DEBUG ((DEBUG_INFO, "FindAndReportEntryPoints\n")); + + FindPeiCoreImageBase (BootFirmwareVolumePtr, &PeiCoreImageBase); + // + // Find PEI Core entry point + // + Status =3D PeCoffLoaderGetEntryPoint ((VOID *) (UINTN) PeiCoreImageBase,= (VOID**) PeiCoreEntryPoint); + if (EFI_ERROR(Status)) { + *PeiCoreEntryPoint =3D 0; + } + DEBUG ((DEBUG_INFO, "PeCoffLoaderGetEntryPoint success: %x\n", *PeiCoreE= ntryPoint)); + + return; +} +/* + Print out the content of firmware context. + +**/ +VOID +DebutPrintFirmwareContext ( + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext + ) +{ + DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI Firmware Context at 0x%x\n", Fir= mwareContext)); + DEBUG ((DEBUG_INFO, " PEI Service at 0x%x\n\n", FirmwareContex= t->PeiServiceTable)); +} + +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ) +{ + VOID *OldHeap; + VOID *NewHeap; + VOID *OldStack; + VOID *NewStack; + struct sbi_platform *ThisSbiPlatform; + + DEBUG ((DEBUG_INFO, + "TemporaryRamMigration(0x%Lx, 0x%Lx, 0x%Lx)\n", + TemporaryMemoryBase, + PermanentMemoryBase, + (UINT64)CopySize + )); + + OldHeap =3D (VOID*)(UINTN)TemporaryMemoryBase; + NewHeap =3D (VOID*)((UINTN)PermanentMemoryBase + (CopySize >> 1)); + + OldStack =3D (VOID*)((UINTN)TemporaryMemoryBase + (CopySize >> 1)); + NewStack =3D (VOID*)(UINTN)PermanentMemoryBase; + + CopyMem (NewHeap, OldHeap, CopySize >> 1); // Migrate Heap + CopyMem (NewStack, OldStack, CopySize >> 1); // Migrate Stack + + // + // Reset firmware context pointer + // + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_= thishart_ptr()); + ThisSbiPlatform->firmware_context +=3D (unsigned long)((UINTN)NewStack -= (UINTN)OldStack); + // + // Relocate PEI Service ** + // + ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbiPlatform->firmware_context= )->PeiServiceTable +=3D (unsigned long)((UINTN)NewStack - (UINTN)OldStack); + DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI Firmware Context is relocated to= 0x%x\n", ThisSbiPlatform->firmware_context)); + DebutPrintFirmwareContext ((EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)ThisSbi= Platform->firmware_context); + + register uintptr_t a0 asm ("a0") =3D (uintptr_t)((UINTN)NewStack - (UINT= N)OldStack); + asm volatile ("add sp, sp, a0"::"r"(a0):); + return EFI_SUCCESS; +} + +EFI_STATUS EFIAPI TemporaryRamDone (VOID) +{ + DEBUG ((DEBUG_INFO, "2nd time PEI core, temporary ram done.\n")); + return EFI_SUCCESS; +} + +#if 1 +#define GPIO_CTRL_ADDR 0x54002000 +#define GPIO_OUTPUT_VAL 0x0C +static volatile UINT32 * const gpio =3D (void *)GPIO_CTRL_ADDR; +#define REG32(p, i) ((p)[(i)>>2]) +#endif + +static VOID EFIAPI PeiCore(VOID) +{ + EFI_SEC_PEI_HAND_OFF SecCoreData; + EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint; + EFI_FIRMWARE_VOLUME_HEADER *BootFv =3D (EFI_FIRMWARE_VOLUME_HEADER *)Fix= edPcdGet32(PcdRiscVPeiFvBase); + EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT FirmwareContext; + struct sbi_platform *ThisSbiPlatform; + UINT32 HartId; + + REG32(gpio, GPIO_OUTPUT_VAL) =3D 0x88; + FindAndReportEntryPoints (&BootFv, &PeiCoreEntryPoint); + + SecCoreData.DataSize =3D sizeof(EFI_SEC_PEI_HAND_OFF); + SecCoreData.BootFirmwareVolumeBase =3D BootFv; + SecCoreData.BootFirmwareVolumeSize =3D (UINTN) BootFv->FvLength; + SecCoreData.TemporaryRamBase =3D (VOID*)(UINT64) FixedPcdGet32(Pcd= TemporaryRamBase); + SecCoreData.TemporaryRamSize =3D (UINTN) FixedPcdGet32(PcdTempora= ryRamSize); + SecCoreData.PeiTemporaryRamBase =3D SecCoreData.TemporaryRamBase; + SecCoreData.PeiTemporaryRamSize =3D SecCoreData.TemporaryRamSize >> 1; + SecCoreData.StackBase =3D (UINT8 *)SecCoreData.TemporaryRam= Base + (SecCoreData.TemporaryRamSize >> 1); + SecCoreData.StackSize =3D SecCoreData.TemporaryRamSize >> 1; + + // + // Print out scratch address of each hart + // + DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI scratch address for each hart:\n= ")); + for (HartId =3D 0; HartId < FixedPcdGet32 (PcdHartCount); HartId ++) { + DEBUG ((DEBUG_INFO, " Hart %d: 0x%x\n", HartId, sbi_hart_id_t= o_scratch(sbi_scratch_thishart_ptr(), HartId))); + } + + // + // Set up OpepSBI firmware context poitner on boot hart OpenSbi scratch.= Firmware context residents in stack and will be + // switched to memory when temporary ram migration. + // + ZeroMem ((VOID *)&FirmwareContext, sizeof (EFI_RISCV_OPENSBI_FIRMWARE_CO= NTEXT)); + ThisSbiPlatform =3D (struct sbi_platform *)sbi_platform_ptr(sbi_scratch_= thishart_ptr()); + if (ThisSbiPlatform->opensbi_version > OPENSBI_VERSION) { + DEBUG ((DEBUG_ERROR, "[OpenSBI]: OpenSBI platform table version 0x%x= is newer than OpenSBI version 0x%x.\n" + "There maybe be some backward compatable issues= .\n", + ThisSbiPlatform->opensbi_version, + OPENSBI_VERSION + )); + ASSERT(FALSE); + } + DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI platform table at address: 0x%x\= nFirmware Context is located at 0x%x\n", + ThisSbiPlatform, + &FirmwareContext + )); + ThisSbiPlatform->firmware_context =3D (unsigned long)&FirmwareContext; + // + // Set firmware context Hart-specific pointer + // + for (HartId =3D 0; HartId < FixedPcdGet32 (PcdHartCount); HartId ++) { + FirmwareContext.HartSpecific [HartId] =3D \ + (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UINT8 *)sbi_hart_id_to= _scratch(sbi_scratch_thishart_ptr(), HartId) - FIRMWARE_CONTEXT_HART_SPECIF= IC_SIZE); + DEBUG ((DEBUG_INFO, "[OpenSBI]: OpenSBI Hart %d Firmware Context Hart-= specific at address: 0x%x\n", + HartId, + FirmwareContext.HartSpecific [HartId] + )); + } + + // + // Transfer the control to the PEI core + // + (*PeiCoreEntryPoint) (&SecCoreData, (EFI_PEI_PPI_DESCRIPTOR *)&mPrivateD= ispatchTable); +} +/** + This function initilizes hart specific information and SBI. + For the boot hart, it boots system through PEI core and initial SBI in t= he DXE IPL. + For others, it goes to initial SBI and halt. + + the lay out of memory region for each hart is as below delineates, + + _ = ____ + |----Scratch ends | = | + | | sizeof (sbi_scratch) = | + | _| = | + |----Scratch buffer start s <----- *scratch = | + |----Firmware Context Hart-specific ends _ = | + | | = | + | | FIRMWARE_CONTEXT_HART_SP= ECIFIC_SIZE | + | | = | PcdOpenSbiStackSize + | _| = | + |----Firmware Context Hart-specific starts <----- **HartFirmwareContex= t | + |----Hart stack top _ = | + | | = | + | | = | + | | Stack = | + | | = | + | _| = ____| + |----Hart stack bottom + +**/ +VOID EFIAPI SecCoreStartUpWithStack(unsigned long hartid, struct sbi_scrat= ch *scratch) +{ + EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *HartFirmwareContext; + + // + // Setup EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC for each hart. + // + HartFirmwareContext =3D (EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *)((UI= NT8 *)scratch - FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE); + HartFirmwareContext->IsaExtensionSupported =3D RiscVReadMisa (); + HartFirmwareContext->MachineVendorId.Value64_L =3D RiscVReadMVendorId (); + HartFirmwareContext->MachineVendorId.Value64_H =3D 0; + HartFirmwareContext->MachineArchId.Value64_L =3D RiscVReadMArchId (); + HartFirmwareContext->MachineArchId.Value64_H =3D 0; + HartFirmwareContext->MachineImplId.Value64_L =3D RiscVReadMImplId (); + HartFirmwareContext->MachineImplId.Value64_H =3D 0; + +#if 0 + while (HartsIn !=3D hartid); + DEBUG ((DEBUG_INFO, "[OpenSBI]: Initial Firmware Context Hart-specific f= or HART ID:%d\n", hartid)); + DEBUG ((DEBUG_INFO, " Scratch at address: 0x%x\n", scratch)); + DEBUG ((DEBUG_INFO, " Firmware Context Hart-specific at addres= s: 0x%x\n", HartFirmwareContext)); + DEBUG ((DEBUG_INFO, " stack pointer at address: 0x%x\n", stack= _point)); + DEBUG ((DEBUG_INFO, " MISA: 0x%x\n", HartFirmwareCont= ext->IsaExtensionSupported)); + DEBUG ((DEBUG_INFO, " MVENDORID: 0x%x\n", HartFirmwar= eContext->MachineVendorId.Value64_L)); + DEBUG ((DEBUG_INFO, " MARCHID: 0x%x\n", HartFirmwareC= ontext->MachineArchId.Value64_L)); + DEBUG ((DEBUG_INFO, " MIMPID: 0x%x\n\n", HartFirmware= Context->MachineImplId.Value64_L)); + HartsIn ++; + for (;;); +#endif + + if (hartid =3D=3D FixedPcdGet32(PcdBootHartId)) { + PeiCore(); + } + sbi_init(scratch); +} diff --git a/Platform/RiscV/Universal/Sec/SecMain.h b/Platform/RiscV/Univer= sal/Sec/SecMain.h new file mode 100644 index 00000000..e7565f5e --- /dev/null +++ b/Platform/RiscV/Universal/Sec/SecMain.h @@ -0,0 +1,57 @@ +/** @file + RISC-V SEC phase module definitions.. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _SECMAIN_H_ +#define _SECMAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +SecMachineModeTrapHandler ( + IN VOID + ); + +VOID +EFIAPI +SecStartupPhase2 ( + IN VOID *Context + ); + +EFI_STATUS +EFIAPI +TemporaryRamMigration ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase, + IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase, + IN UINTN CopySize + ); + +EFI_STATUS +EFIAPI +TemporaryRamDone ( + VOID + ); + +#endif // _SECMAIN_H_ diff --git a/Platform/RiscV/Universal/Sec/SecMain.inf b/Platform/RiscV/Univ= ersal/Sec/SecMain.inf new file mode 100644 index 00000000..c408fc8d --- /dev/null +++ b/Platform/RiscV/Universal/Sec/SecMain.inf @@ -0,0 +1,75 @@ +## @file +# RISC-V SEC module. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SecMain + FILE_GUID =3D df1ccef6-f301-4a63-9661-fc6030dcc880 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SecMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 EBC +# + +[Sources] + SecMain.c + +[Sources.RISCV64] + Riscv64/SecEntry.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + PcdLib + DebugAgentLib + IoLib + PeCoffLib + PeCoffGetEntryPointLib + PeCoffExtraActionLib + ExtractGuidedSectionLib + RiscVCpuLib + PrintLib + SerialPortLib + RiscVOpensbiLib + OpenSbiPlatformLib # This is required library which + # provides platform level opensbi + # functions. + +[Ppis] + gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED + gEfiTemporaryRamDonePpiGuid # PPI ALWAYS_PRODUCED + +[Guids] + gUefiRiscVMachineContextGuid + +[FixedPcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvSize + +[Pcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47539): https://edk2.groups.io/g/devel/message/47539 Mute This Topic: https://groups.io/mt/34196353/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47540+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47540+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865105; cv=none; d=zoho.com; s=zohoarc; b=BJA+bpko325X/anYI4RDdiNZTo2+BuAtfXquTphNbeqtBDjeeD3LhW8rG8VUylhg8uet8ddLTWRO31g/JoHrU+DtyN2oijkpKS/QMlmTe5AZgO5W0tpbxY8+C9H1A+rhrKVxZEIczGMtWLnDP3wAeXj7F4gZ/x94sdeWFZxJiVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865105; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=HbkjHqJKuE1ieMNk1mNJ03mItESCqS47wyCFNQElppU=; b=lqiar8HNf6+xH2oDYGfDZgVvRV5X0huWOm9HvYAomp6pzWTCnJQlIc8wcWutcs8FKstoitI9simpJ5oWr01mFXNlcJMpvJIHfxAqhNKzcfQipl+4SjxznCkPVoxP9Hpxse+yPVN1ATKPA3U03Svz8kfbX3F8v4/P+e0t8o9Hqbg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47540+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865105796998.0343989410969; Wed, 18 Sep 2019 20:51:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id F5HrYY1788612xnWxoBvl5Vi; Wed, 18 Sep 2019 20:51:45 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:44 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pMkj013263 for ; Thu, 19 Sep 2019 03:51:44 GMT X-Received: from g4t3426.houston.hpe.com (g4t3426.houston.hpe.com [15.241.140.75]) by mx0b-002e3701.pphosted.com with ESMTP id 2v3vapdarv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:43 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3426.houston.hpe.com (Postfix) with ESMTP id ED9D14E for ; Thu, 19 Sep 2019 03:51:42 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 2C94E45 for ; Thu, 19 Sep 2019 03:51:41 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 07/14] RiscV/SiFive: Initial version of SiFive U500 platform package Date: Thu, 19 Sep 2019 11:51:24 +0800 Message-Id: <20190919035131.4700-8-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: WhuOu63tKIfuy6jD7xEHJaWux1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865105; bh=Nm1dFVeEqU4Uj0UwM3sZypeUcXgH4LShZWSrk0xT5Mw=; h=Date:From:Reply-To:Subject:To; b=lAKT3RM0wRrfHcGB1YLribIPVtVLzFMsgHkujEKx7lrdaa+iSRk4tedxCaX9jontHXZ r94PKWm1TRSdRsyQCfQewSztpQUDQ9zAmKzX/4xfVIREwZhD7lUBNbbh14Jupynpml6dg dTHZNs23wu7OvqNhfFCToGwU9fxGjdCqX1E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The initial version of SiFive U500 platform package. Signed-off-by: Gilbert Chen --- Platform/RiscV/SiFive/U500Pkg/Readme.md | 62 +++ Platform/RiscV/SiFive/U500Pkg/U500.dec | 34 ++ Platform/RiscV/SiFive/U500Pkg/U500.dsc | 549 +++++++++++++++++++++= ++++ Platform/RiscV/SiFive/U500Pkg/U500.fdf | 335 +++++++++++++++ Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc | 52 +++ Platform/RiscV/SiFive/U500Pkg/U500.uni | 13 + Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni | 12 + Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc | 78 ++++ 8 files changed, 1135 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Readme.md create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dec create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dsc create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.uni create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni create mode 100644 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc diff --git a/Platform/RiscV/SiFive/U500Pkg/Readme.md b/Platform/RiscV/SiFiv= e/U500Pkg/Readme.md new file mode 100644 index 00000000..71fa62a1 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Readme.md @@ -0,0 +1,62 @@ +# Introduction + +## U500 Platform Package +This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U= 500 VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Get= ting Started Guide" on https://www.sifive.com/documentation. This package i= s built with below common packages,
+- **RiscVPlatformPkg**, edk2-platform/Platform/RiscV +- **RiscVPkg**, edk2 master branch (Currently is in edk2-staging/RISC-V br= anch) +
+This package provides librareis and modules which are SiFive U500 platform= implementation-specific and incorporate with common RISC-V packages mentio= ned above. + +## Download the sources +``` +git clone https://github.com/tianocore/edk2-staging.git +# Checkout RISC-V-V2 branch +git clone https://github.com/tianocore/edk2-platforms.git +# Checkout devel-riscv-v2 branch +git clone https://github.com/tianocore/edk2-non-osi.git +``` + +## Platform Owners +Chang, Abner
+Chen, Gilbert + +## Platform Status +Currently the binary built from U500Pkg can boot SiFive Freedom U500 VC707= FPGA to EFI shell with console in/out enabled. + +## Linux Build Instructions +You can build the RISC-V platform using below script,
+`build -a RISCV64 -p Platform/RiscV/SiFive/U500Pkg/U500.dsc -t GCCRISCV` + +## Supported Operating Systems +Only support to boot to EFI Shell so far + +## Known Issues and Limitations +Only RISC-V RV64 is verified on this platform. + +## Related Materials +- [RISC-V OpenSbi](https://github.com/riscv/opensbi)
+- [SiFive U500 VC707 FPGA Getting Started Guide](https://sifive.cdn.prismi= c.io/sifive%2Fc248fabc-5e44-4412-b1c3-6bb6aac73a2c_sifive-u500-vc707-gettin= gstarted-v0.2.pdf)
+- [SiFive RISC-V Core Document](https://www.sifive.com/documentation) + +## U500 Platform Libraries and Drivers +### OpneSbiPlatformLib +In order to reduce the dependencies with RISC-V OpenSBI project (https://g= ithub.com/riscv/opensbi) and less burdens to EDK2 build process, the implem= entation of RISC-V EDK2 platform is leverage platform source code from Open= SBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from RI= SC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build env= ironment. + +### PeiCoreInfoHobLib +This is the library to create RISC-V core characteristics for building up = RISC-V related SMBIOS records to support the unified boot loader and OS ima= ge. This library leverage the silicon libraries provided in Silicon/SiFive. + +### RiscVPlatformTimerLib +This is U500 platform timer library which has the platform-specific timer = implementation. + +### PlatformPei +This is the platform-implementation specific library which is executed in = early PEI phase for platform initialization. + +### TimerDxe +This is U500 platform timer DXE driver whcih has the platform-specific tim= er implementation. + +## U500 Platform PCD settings + +| **PCD name** |**Usage**| +|----------------|----------| +|PcdNumberofU5Cores| Number of U5 core enabled on U500 platform| +|PcdE5MCSupported| Indicates whether or not the Monitor Core (E5) is suppo= rted on U500 platform| diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dec b/Platform/RiscV/SiFive= /U500Pkg/U500.dec new file mode 100644 index 00000000..4ecca89b --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.dec @@ -0,0 +1,34 @@ +## @file U500.dec +# This Package provides SiFive U500 modules and libraries. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D U500 + PACKAGE_UNI_FILE =3D U500.uni + PACKAGE_GUID =3D D11E9DB9-5940-4642-979D-2114342140D2 + PACKAGE_VERSION =3D 1.0 + +[Includes] + Include + +[LibraryClasses] + + +[Guids] + gUefiRiscVPlatformU500PkgTokenSpaceGuid =3D {0xDFD87009, 0x27A1, 0x41DD= , { 0x84, 0xB1, 0x35, 0xB4, 0xB9, 0x0D, 0x17, 0x63 }} + +[PcdsFixedAtBuild] + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores|0x8|UINT32|0x= 00001000 + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported|TRUE|BOOLEAN|0x= 00001001 + +[PcdsPatchableInModule] + + +[UserExtensions.TianoCore."ExtraFiles"] + U500PkgExtra.uni diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dsc b/Platform/RiscV/SiFive= /U500Pkg/U500.dsc new file mode 100644 index 00000000..edcd951a --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.dsc @@ -0,0 +1,549 @@ +## @file +# RISC-V EFI on SiFive VC707 (U500) RISC-V platform +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D U500 + PLATFORM_GUID =3D 0955581C-2A6A-48F7-8690-9D275AE884F8 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/U500Pkg + SUPPORTED_ARCHITECTURES =3D RISCV64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + FLASH_DEFINITION =3D Platform/RiscV/SiFive/U500Pkg/U500.fdf + + # + # Enable below options may cause build error or may not work on + # the initial version of RISC-V package + # Defines for default states. These can be changed on the command line. + # -D FLAG=3DVALUE + # + DEFINE SECURE_BOOT_ENABLE =3D FALSE + DEFINE DEBUG_ON_SERIAL_PORT =3D TRUE + + # + # Network definition + # + DEFINE NETWORK_SNP_ENABLE =3D FALSE + DEFINE NETWORK_IP6_ENABLE =3D FALSE + DEFINE NETWORK_TLS_ENABLE =3D FALSE + DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE + DEFINE NETWORK_ISCSI_ENABLE =3D FALSE + +[BuildOptions] + GCC:RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG +!ifdef $(SOURCE_DEBUG_ENABLE) + GCC:*_*_RISCV64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this Platf= orm. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### +[LibraryClasses] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServic= esLib.inf + HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf + CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + SerialPortLib|Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIo= Lib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLibDevicePathProtocol/UefiDev= icePathLibDevicePathProtocol.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeS= ecurityManagementLib.inf + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/Customize= dDisplayLib.inf + SortLib|MdeModulePkg/Library/BaseSortLib/BaseSortLib.inf + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + +# RISC-V Platform Library + RealTimeClockLib|Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClo= ckLibNull.inf + +# RISC-V Core Library + RiscVOpensbiLib|RiscVPkg/Library/RiscVOpensbiLib/RiscVOpensbiLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDeb= ug/PeCoffExtraActionLibDebug.inf + DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibS= erialPort/DebugCommunicationLibSerialPort.inf +!else + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.i= nf +!endif + + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf + TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure= mentLib.inf + AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf +!else + TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLib= Null.inf +!endif + VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf + +!if $(HTTP_BOOT_ENABLE) =3D=3D TRUE + HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf +!endif + +# ACPI not supported yet. + #S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScri= ptLib.inf + SmbusLib|MdePkg/Library/BaseSmbusLibNull/BaseSmbusLibNull.inf + OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib= /BaseOrderedCollectionRedBlackTreeLib.inf + +[LibraryClasses.common] +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf +!endif + RiscVCpuLib|RiscVPkg/Library/RiscVCpuLib/RiscVCpuLib.inf + RiscVPlatformTimerLib|Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatfor= mTimerLib/RiscVPlatformTimerLib.inf + CpuExceptionHandlerLib|RiscVPkg/Library/RiscVExceptionLib/CpuExceptionHa= ndlerDxeLib.inf + +[LibraryClasses.common.SEC] +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + ExtractGuidedSectionLib|MdePkg/Library/BaseExtractGuidedSectionLib/BaseE= xtractGuidedSectionLib.inf + +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf +!endif + + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + +# +# OpenSBi Platform Library +# + OpenSbiPlatformLib|Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatform= Lib/OpenSbiPlatformLib.inf + +[LibraryClasses.common.PEI_CORE] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOp= enSbi/PeiServicesTablePointerLibOpenSbi.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + +[LibraryClasses.common.PEIM] + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + PeiServicesTablePointerLib|RiscVPkg/Library/PeiServicesTablePointerLibOp= enSbi/PeiServicesTablePointerLibOpenSbi.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiRepor= tStatusCodeLib.inf + OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHo= okStatusCodeLibNull.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiRe= sourcePublicationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib= .inf +!endif + FirmwareContextProcessorSpecificLib|Platform/RiscV/Library/FirmwareConte= xtProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf + RiscVPlatformDxeIplLib|RiscVPkg/Library/RiscVDxeIplHandoffOpenSbiLib/Ris= cVDxeIplHandoffOpenSbiLib.inf + +# +# RISC-V core libraries +# + SiliconSiFiveE51CoreInfoLib|Silicon/SiFive/E51/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf + SiliconSiFiveU54CoreInfoLib|Silicon/SiFive/U54/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf + SiliconSiFiveU5MCCoreplexInfoLib|Platform/RiscV/SiFive/U500Pkg/Library/P= eiCoreInfoHobLib/PeiCoreInfoHobLib.inf + +[LibraryClasses.common.DXE_CORE] + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeC= oreMemoryAllocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + #CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpu= ExceptionHandlerLib.inf + +[LibraryClasses.common.DXE_RUNTIME_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/R= untimeDxeReportStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + +[LibraryClasses.common.UEFI_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + +[LibraryClasses.common.DXE_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif +!ifdef $(SOURCE_DEBUG_ENABLE) + DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf +!endif + UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManag= erLib.inf + PlatformBootManagerLib|Platform/RiscV/SiFive/U500Pkg/Library/PlatformBoo= tManagerLib/PlatformBootManagerLib.inf + #PlatformBootManagerLib|MdeModulePkg/Library/PlatformBootManagerLibNull/= PlatformBootManagerLibNull.inf + #CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpu= ExceptionHandlerLib.inf + +[LibraryClasses.common.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf +!ifdef $(DEBUG_ON_SERIAL_PORT) + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +!else + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +!endif + ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeRepor= tStatusCodeLib.inf + +[LibraryClasses.common.DXE_SMM_DRIVER] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + +[LibraryClasses.common.SMM_CORE] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + TimerLib|RiscVPkg/Library/RiscVTimerLib/BaseRiscVTimerLib.inf + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform. +# +##########################################################################= ###### +[PcdsFeatureFlag] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE + +[PcdsFixedAtBuild] + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1 + gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FAL= SE + gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000 + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0xe000 + + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x17 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F +!endif + +!ifdef $(SOURCE_DEBUG_ENABLE) + gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 +!endif + + #gUefiPayloadPkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x= 3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # override the default values from SecurityPkg to ensure images from all= sources are verified in secure boot + gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04 + gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0= x04 +!endif + + # + # F2 for UI APP + # + gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c= , 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0= x31 } + +##########################################################################= ###### +# +# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Pla= tform +# +##########################################################################= ###### + +[PcdsDynamicDefault] + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 + + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|0 + + # Set video resolution for text setup. + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution|640 + gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution|480 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosDocRev|0x0 + +##########################################################################= ###### +# +# Components Section - list of all EDK II Modules needed by this Platform. +# +##########################################################################= ###### +[Components] + + # + # SEC Phase modules + # + Platform/RiscV/Universal/Sec/SecMain.inf + + # + # PEI Phase modules + # + MdeModulePkg/Core/Pei/PeiMain.inf + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouter= Pei.inf + MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { + + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompress= Lib.inf + } + + Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } + + # + # DXE Phase modules + # + MdeModulePkg/Core/Dxe/DxeMain.inf { + + NULL|MdeModulePkg//Library/LzmaCustomDecompressLib/LzmaCustomDecompr= essLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + } + + MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf + MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRun= timeDxe.inf + + MdeModulePkg/Universal/PCD/Dxe/Pcd.inf { + + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + + MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf { + + NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificatio= nLib.inf + } +!else + MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +!endif + + # + # EBC not supported on RISC-V yet + # + #MdeModulePkg/Universal/EbcDxe/EbcDxe.inf + + UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf { + + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + } + MdeModulePkg/Universal/Metronome/Metronome.inf + MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf { + + ResetSystemLib|MdeModulePkg/Library/BaseResetSystemLibNull/BaseReset= SystemLibNull.inf + } + + # + # RISC-V Platform module + # + Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf + Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/Fvb= ServicesRuntimeDxe.inf + + # + # RISC-V Core module + # + RiscVPkg/Universal/CpuDxe/CpuDxe.inf + RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf + RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf + + MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf { + + NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf + } + MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf + MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + +# No graphic console supported yet. +# MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.in= f { +# +# PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf +# } + MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf { + + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + } + MdeModulePkg/Universal/PrintDxe/PrintDxe.inf + MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf + MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf + MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf + MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf + MdeModulePkg/Universal/SerialDxe/SerialDxe.inf + + # + # SMBIOS Support + # + MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + + # + # ACPI Support + # Not support on RISC-V yet + # + #MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + #MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + + # + # Network Support + # + !include NetworkPkg/Network.dsc.inc + + # + # Usb Support + # + MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + + + ShellPkg/Application/Shell/Shell.inf { + + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellComman= dLib.inf + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePar= singLib.inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf + SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcf= gCommandLib.inf + + + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000 + } + +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDx= e.inf +!endif + + MdeModulePkg/Application/UiApp/UiApp.inf diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.fdf b/Platform/RiscV/SiFive= /U500Pkg/U500.fdf new file mode 100644 index 00000000..5ca84be3 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.fdf @@ -0,0 +1,335 @@ +# @file +# Flash definition file on SiFive VC707 (U500) RISC-V platform +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +[Defines] + +!include U500.fdf.inc + +# +# Build the variable store and the firmware code as one unified flash devi= ce +# image. +# +[FD.U500] +BaseAddress =3D $(FW_BASE_ADDRESS) +Size =3D $(FW_SIZE) +ErasePolarity =3D 1 +BlockSize =3D $(BLOCK_SIZE) +NumBlocks =3D $(FW_BLOCKS) + +$(SECFV_OFFSET)|$(SECFV_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVSecFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVSecFvSize +FV =3D SECFV + +$(PEIFV_OFFSET)|$(PEIFV_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVPeiFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVPeiFvSize +FV =3D PEIFV + +$(FVMAIN_OFFSET)|$(FVMAIN_SIZE) +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase|gUefiRiscVPlatformPk= gTokenSpaceGuid.PcdRiscVDxeFvSize +FV =3D FVMAIN_COMPACT + +!include VarStore.fdf.inc + +##########################################################################= ###### + +[FV.SECFV] +BlockSize =3D 0x1000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +# +# SEC Phase modules +# +# The code in this FV handles the initial firmware startup, and +# decompresses the PEI and DXE FVs which handles the rest of the boot sequ= ence. +# +INF Platform/RiscV/Universal/Sec/SecMain.inf + +##########################################################################= ###### +[FV.PEIFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +APRIORI PEI { + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeR= outerPei.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.i= nf + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +} + +# +# PEI Phase modules +# +INF MdeModulePkg/Core/Pei/PeiMain.inf +INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf +INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRou= terPei.inf +INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf +INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + +# RISC-V Platform PEI Driver +INF Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.i= nf + +##########################################################################= ###### + +[FV.DXEFV] +BlockSize =3D 0x10000 +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +APRIORI DXE { + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDx= e/FvbServicesRuntimeDxe.inf +} + +# +# DXE Phase modules +# +INF MdeModulePkg/Core/Dxe/DxeMain.inf + +INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatus= CodeRouterRuntimeDxe.inf +INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandler= RuntimeDxe.inf +INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + +INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf +INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf +INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf +INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +INF MdeModulePkg/Universal/Metronome/Metronome.inf + +# RISC-V Platform Drivers +INF Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= FvbServicesRuntimeDxe.inf + +# RISC-V Core Drivers +INF RiscVPkg/Universal/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf +INF Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf +INF RiscVPkg/Universal/CpuDxe/CpuDxe.inf +INF RiscVPkg/Universal/SmbiosDxe/RiscVSmbiosDxe.inf + +INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf + +INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootCon= figDxe.inf +!endif + +INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf +INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf +INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRun= timeDxe.inf +INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf +INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf +#INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe= .inf +INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf +INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf +INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf +INF MdeModulePkg/Universal/PrintDxe/PrintDxe.inf +INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf +INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf +INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf +INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf +INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf +INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf +INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf +INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe= .inf + +!ifndef $(SOURCE_DEBUG_ENABLE) +INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf +!endif + +INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + +# +# ACPI is not supported yet on RISC-V package. +# +#INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf +#INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf +#INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf + +#INF RuleOverride =3D BINARY FatBinPkg/EnhancedFatDxe/Fat.inf + +INF ShellPkg/Application/Shell/Shell.inf + +# +# Network modules +# +!if $(E1000_ENABLE) + FILE DRIVER =3D 5D695E11-9B3F-4b83-B25F-4A8D5D69BE07 { + SECTION PE32 =3D Intel3.5/EFIX64/E3507X2.EFI + } +!endif + +!include NetworkPkg/Network.fdf.inc + +# +# Usb Support +# +INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf +INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf +INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf +INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf +INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf +INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + +INF MdeModulePkg/Application/UiApp/UiApp.inf + +##########################################################################= ###### + +[FV.FVMAIN_COMPACT] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 27A72E80-3118-4c0c-8673-AA5B4EFA9613 + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED= =3D TRUE { + # + # These firmware volumes will have files placed in them uncompressed, + # and then both firmware volumes will be compressed in a single + # compression operation in order to achieve better overall compressio= n. + # + SECTION FV_IMAGE =3D DXEFV + } + } + +[Rule.Common.SEC] + FILE SEC =3D $(NAMED_GUID) RELOCS_STRIPPED { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEI_CORE] + FILE PEI_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING =3D"$(MODULE_NAME)" Optional + VERSION STRING =3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.PEIM] + FILE PEIM =3D $(NAMED_GUID) { + PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.DXE_CORE] + FILE DXE_CORE =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.DXE_RUNTIME_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align =3D 4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_DRIVER.BINARY] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional |.depex + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.UEFI_APPLICATION] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K $(INF_OUTPUT)/$(MODULE_NAME).efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBER) + } + +[Rule.Common.UEFI_APPLICATION.BINARY] + FILE APPLICATION =3D $(NAMED_GUID) { + PE32 PE32 Align=3D4K |.efi + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI |.acpi + RAW ASL |.aml + } diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc b/Platform/RiscV/Si= Five/U500Pkg/U500.fdf.inc new file mode 100644 index 00000000..ac24b5b0 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc @@ -0,0 +1,52 @@ +## @file +# Definitions of Flash definition file on SiFive VC707 (U500) RISC-V plat= form +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## +DEFINE BLOCK_SIZE =3D 0x1000 + +DEFINE FW_BASE_ADDRESS =3D 0x80000000 +DEFINE FW_SIZE =3D 0x00800000 +DEFINE FW_BLOCKS =3D 0x800 + +# +# 0x000000-0x7DFFFF code +# 0x7E0000-0x800000 variables +# +DEFINE CODE_BASE_ADDRESS =3D 0x80000000 +DEFINE CODE_SIZE =3D 0x007E0000 +DEFINE CODE_BLOCKS =3D 0x7E0 +DEFINE VARS_BLOCKS =3D 0x20 + +DEFINE SECFV_OFFSET =3D 0x00000000 +DEFINE SECFV_SIZE =3D 0x00020000 +DEFINE PEIFV_OFFSET =3D 0x00020000 +DEFINE PEIFV_SIZE =3D 0x00060000 +DEFINE SCRATCH_OFFSET =3D 0x00080000 +DEFINE SCRATCH_SIZE =3D 0x00010000 +DEFINE FVMAIN_OFFSET =3D 0x00100000 # Must be power of 2 for PMP setti= ng +DEFINE FVMAIN_SIZE =3D 0x0018C000 +DEFINE VARS_OFFSET =3D 0x007E0000 +DEFINE VARS_SIZE =3D 0x00020000 + +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress =3D $(FW_= BASE_ADDRESS) + $(VARS_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize =3D $(VAR= S_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize =3D $(BLO= CK_SIZE) + +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwStartAddress =3D $(CODE_BASE_= ADDRESS) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdFwEndAddress =3D $(CODE_BASE_AD= DRESS) + $(SECFV_SIZE) + $(PEIFV_SIZE) + $(SCRATCH_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize =3D 8192 +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamBase =3D $(CODE_BASE_= ADDRESS) + $(SCRATCH_OFFSET) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdScratchRamSize =3D $(SCRATCH_SI= ZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase =3D $(CODE_BAS= E_ADDRESS) + $(FW_SIZE) +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize =3D 0x10000 + + +SET gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz =3D 10= 00000 +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount =3D 4 #= Total cores on U500 platform +SET gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores =3D 4 #= Total U5 cores enabled on U500 platform +SET gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported =3D False #= Enable optional E51 MC core? +SET gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId =3D 0 #= Boot hart ID diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.uni b/Platform/RiscV/SiFive= /U500Pkg/U500.uni new file mode 100644 index 00000000..7ac1096f --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500.uni @@ -0,0 +1,13 @@ +// /** @file +// SiFive U500 Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_PACKAGE_ABSTRACT #language en-US "Provides SiFIve R= ISC-V U500 platform modules and libraries" + +#string STR_PACKAGE_DESCRIPTION #language en-US "This Package SiFI= ve RISC-V U500 platform modules and libraries." diff --git a/Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni b/Platform/Risc= V/SiFive/U500Pkg/U500PkgExtra.uni new file mode 100644 index 00000000..6b68fb43 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// SiFive U500 Package Localized Strings and Content. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_PACKAGE_NAME +#language en-US +"SiFive U500 package" diff --git a/Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc b/Platform/Risc= V/SiFive/U500Pkg/VarStore.fdf.inc new file mode 100644 index 00000000..c287bb43 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc @@ -0,0 +1,78 @@ +## @file +# FDF include file with Layout Regions that define an empty variable stor= e. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (C) 2014, Red Hat, Inc. +# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +$(VARS_OFFSET)|0x00007000 +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase|= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +# +# NV_VARIABLE_STORE +# +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid: gEfiSystemNvDataFvGuid =3D + # { 0xFFF12B8D, 0x7696, 0x4C8B, + # { 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50 }} + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x20000 + 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, + # Signature "_FVH" # Attributes + 0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00, + # HeaderLength # CheckSum # ExtHeaderOffset #Reserved #Revision + 0x48, 0x00, 0x39, 0xF1, 0x00, 0x00, 0x00, 0x02, + # Blockmap[0]: 0x20 Blocks * 0x1000 Bytes / Block + 0x00, 0x08, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, + # Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if $(SECURE_BOOT_ENABLE) =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D + # { 0xaaf32c78, 0x947b, 0x439a, + # { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid =3D + # { 0xddcf3616, 0x3275, 0x4164, + # { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + # Size: 0x7000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - + # 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x6fb8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0x6F, 0x00, 0x00, + # FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x007e7000|0x00001000 +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingBas= e|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +# +#NV_FTW_WROK +# +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0x2c, 0xaf, 0x2c, 0x64, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +0x007e8000|0x00018000 +gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase|= gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +# +#NV_FTW_SPARE --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47540): https://edk2.groups.io/g/devel/message/47540 Mute This Topic: https://groups.io/mt/34196355/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47541+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47541+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865107; cv=none; d=zoho.com; s=zohoarc; b=Lfq/CKIoQkE/eIOJvlPNcoCcqhOsuMhqnS6q6kNiumT/8ThZ2kWuyOvh/+BD8wEq180SVV5qRE9+icnU1EZpUr97KRJbFKzTY+4vt2ppMu6zX092RqTKkgQT0+EKAgJHRjLYjIDNgDJvzceykvVd5KVb7Mn/+duvgRb/KqWlNPU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865107; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=dtJ15lNh08o0q5OsktE3QuHKo0NYc8hn/39qdds2Tq0=; b=CuNXJyUss7bRr+ONY8FWE/86/MtUq5EymmFJEeh59nlvcqq8eM3+dt7JF8mVr+kIqfFWttqXWKsWfi66oONaWaykL+bUyMY/CXBHtRVzjSXfMhqJUk6uIrCpIN8tXQt4LT1mkSMfNGFrCATzScQ3EdRV4dcsnwL3E1K+MGsJNU0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47541+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865107465915.0451977433352; Wed, 18 Sep 2019 20:51:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Jw58YY1788612x8Ui670PKEG; Wed, 18 Sep 2019 20:51:46 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:45 -0700 X-Received: from pps.filterd (m0150241.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pKup021201 for ; Thu, 19 Sep 2019 03:51:44 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vaqnkcx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:44 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 4690951 for ; Thu, 19 Sep 2019 03:51:44 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 767C545 for ; Thu, 19 Sep 2019 03:51:43 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 08/14] U500Pkg/Include: Header files of SiFive U500 platform Date: Thu, 19 Sep 2019 11:51:25 +0800 Message-Id: <20190919035131.4700-9-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: 62s18M7GhYPBm4NwVpxMw68Ux1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865106; bh=l9aDmqfJMpA2V1Y/N/mr+hhEkDs/cALY9sjCmDslhIY=; h=Date:From:Reply-To:Subject:To; b=TLwfUL2o6nyD5AHMWyqbmtRFBzusXUU1MO9WfH7w4/7KDWYHMxSXoqc19z6DZ2XkC6y n7+vMs3NeZS0phcI1Q5XXVVgPBqCny1vWNHcqUOIXkZHXPpAzu1DT/o3802wSQJsMdj0k QFhOwiVYAeQP8c7c2XTn5rAO+K/mIX9WKR4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The initial header file commit for SiFive U5-MC Coreplex and U500 Core Local interrupt definitions. Signed-off-by: Gilbert Chen --- .../SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h | 51 ++++++++++++++++++= ++++ Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h | 19 ++++++++ 2 files changed, 70 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreple= x.h create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h b/P= latform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h new file mode 100644 index 00000000..9968159c --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h @@ -0,0 +1,51 @@ +/** @file + SiFive U54 Coreplex library definitions. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SIFIVE_U5MC_COREPLEX_H_ +#define _SIFIVE_U5MC_COREPLEX_H_ + +#include + +#include +#include + +#define SIFIVE_U5MC_COREPLEX_MC_HART_ID 0 + +/** + Build up U5MC coreplex processor core-specific information. + + @param UniqueId U5MC unique ID. + + @return EFI_STATUS + +**/ +EFI_STATUS +EFIAPI +CreateU5MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ); + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns th= is core. + @param SmbiosDataHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_D= ATA_HOB. The pointers + maintained in this structure is only valid b= efore memory is discovered. + Access to those pointers after memory is ins= talled will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU5MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosDataHobPtr + ); +#endif diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h b/Platform/R= iscV/SiFive/U500Pkg/Include/U500Clint.h new file mode 100644 index 00000000..a8c9ae15 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h @@ -0,0 +1,19 @@ +/** @file + RISC-V Timer Architectural definition for U500 platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _U500_H_ +#define _U500_H_ + +#define CLINT_REG_MTIME 0x0200BFF8 +#define CLINT_REG_MTIMECMP0 0x02004000 +#define CLINT_REG_MTIMECMP1 0x02004008 +#define CLINT_REG_MTIMECMP2 0x02004010 +#define CLINT_REG_MTIMECMP3 0x02004018 +#define CLINT_REG_MTIMECMP4 0x02004020 + +#endif --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47541): https://edk2.groups.io/g/devel/message/47541 Mute This Topic: https://groups.io/mt/34196356/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47542+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47542+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865109; cv=none; d=zoho.com; s=zohoarc; b=mFsCjuQgXOxhbZjI4/twwBWt/SBdthTEJinHkfNWr3bAOHvVt6K41SKA51GNLabMZ3gTcqOGCPfEf+lwvvUPgqiey1FBdOrmxTbKn5kfMgGxVxT0QAVnhsekYilcHqi81R9qGudDMbQSwo0yOvq28NAIzbALnQPLOS4fHzMcku8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865109; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=/7nOHaAHku95TRp9eVfhaqXkItUrrd6szy8WOWlyyqw=; b=JsW3/LmnYr/Bvk5UtmSKpaJpb4KTFYU1lfj6I43D/YGeSCEWcR8asGJ9dRvPcYMx+y9hTIIeaVMjPyyIgSwRNHiTogRePkG3EhiMb2mRl2Dn8WD/t9SI7YHefhSp9tQYRWLEQyQeROoyMgt9utbXerFIdmxybx0bQhAaHvE9OG4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47542+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865109259264.98635486269313; Wed, 18 Sep 2019 20:51:49 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id GacPYY1788612xL7r7zhLpCT; Wed, 18 Sep 2019 20:51:48 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:47 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pdLt030784 for ; Thu, 19 Sep 2019 03:51:46 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vapnb9d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:46 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 9066A51 for ; Thu, 19 Sep 2019 03:51:45 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id C10DF45 for ; Thu, 19 Sep 2019 03:51:44 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 09/14] U500Pkg/Library: Initial version of PlatformBootManagerLib Date: Thu, 19 Sep 2019 11:51:26 +0800 Message-Id: <20190919035131.4700-10-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> MIME-Version: 1.0 X-HPE-SCL: -1 X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-002e3701.pphosted.com id x8J3pdLt030784 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: 9oOwk86RqAI9CsGwoGDKOMZix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865108; bh=jlde/RD3YOHXi9eQZa3zEyFXQVWlWbEn0Gmj1WZDDOA=; h=Content-Type:Date:From:Reply-To:Subject:To; b=wV10aa2qLF12FkWxr7XYDnU9IQDHxH22qnextBgNjQmzMLLsCO49ir3D2rdZSnGMDQk AcraBUJ7ri9oWExyVmdAimpsc59qZ+MRveMag2smaHS1SpweAmDPEWbOMCmdonp2GD9jX F7Mus1SY/Mh7w6cCLaNUg41X3OzwGtpgztI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" SiFive RISC-V U500 Platform Boot Manager library. Signed-off-by: Gilbert Chen --- .../Library/PlatformBootManagerLib/MemoryTest.c | 682 +++++++++++++++++= ++++ .../PlatformBootManagerLib/PlatformBootManager.c | 274 +++++++++ .../PlatformBootManagerLib/PlatformBootManager.h | 135 ++++ .../PlatformBootManagerLib.inf | 63 ++ .../Library/PlatformBootManagerLib/PlatformData.c | 49 ++ .../Library/PlatformBootManagerLib/Strings.uni | 28 + 6 files changed, 1231 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManag= erLib/MemoryTest.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManag= erLib/PlatformBootManager.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManag= erLib/PlatformBootManager.h create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManag= erLib/PlatformBootManagerLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManag= erLib/PlatformData.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManag= erLib/Strings.uni diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/M= emoryTest.c b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/= MemoryTest.c new file mode 100644 index 00000000..8c6d89e9 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTe= st.c @@ -0,0 +1,682 @@ +/** @file + Perform the RISC-V platform memory test + +Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights = reserved.
+Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PlatformBootManager.h" + +EFI_HII_HANDLE gStringPackHandle =3D NULL; +EFI_GUID mPlatformBootManagerStringPackGuid =3D { + 0x154dd51, 0x9079, 0x4a10, { 0x89, 0x5c, 0x9c, 0x7, 0x72, 0x81, 0x57, 0x= 88 } + }; +// extern UINT8 BdsDxeStrings[]; + +// +// BDS Platform Functions +// +/** + + Show progress bar with title above it. It only works in Graphics mode. + + @param TitleForeground Foreground color for Title. + @param TitleBackground Background color for Title. + @param Title Title above progress bar. + @param ProgressColor Progress bar color. + @param Progress Progress (0-100) + @param PreviousValue The previous value of the progress. + + @retval EFI_STATUS Success update the progress bar + +**/ +EFI_STATUS +PlatformBootManagerShowProgress ( + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground, + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground, + IN CHAR16 *Title, + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor, + IN UINTN Progress, + IN UINTN PreviousValue + ) +{ + EFI_STATUS Status; + EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput; + EFI_UGA_DRAW_PROTOCOL *UgaDraw; + UINT32 SizeOfX; + UINT32 SizeOfY; + UINT32 ColorDepth; + UINT32 RefreshRate; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color; + UINTN BlockHeight; + UINTN BlockWidth; + UINTN BlockNum; + UINTN PosX; + UINTN PosY; + UINTN Index; + + if (Progress > 100) { + return EFI_INVALID_PARAMETER; + } + + UgaDraw =3D NULL; + Status =3D gBS->HandleProtocol ( + gST->ConsoleOutHandle, + &gEfiGraphicsOutputProtocolGuid, + (VOID **) &GraphicsOutput + ); + if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) { + GraphicsOutput =3D NULL; + + Status =3D gBS->HandleProtocol ( + gST->ConsoleOutHandle, + &gEfiUgaDrawProtocolGuid, + (VOID **) &UgaDraw + ); + } + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + + SizeOfX =3D 0; + SizeOfY =3D 0; + if (GraphicsOutput !=3D NULL) { + SizeOfX =3D GraphicsOutput->Mode->Info->HorizontalResolution; + SizeOfY =3D GraphicsOutput->Mode->Info->VerticalResolution; + } else if (UgaDraw !=3D NULL) { + Status =3D UgaDraw->GetMode ( + UgaDraw, + &SizeOfX, + &SizeOfY, + &ColorDepth, + &RefreshRate + ); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } else { + return EFI_UNSUPPORTED; + } + + BlockWidth =3D SizeOfX / 100; + BlockHeight =3D SizeOfY / 50; + + BlockNum =3D Progress; + + PosX =3D 0; + PosY =3D SizeOfY * 48 / 50; + + if (BlockNum =3D=3D 0) { + // + // Clear progress area + // + SetMem (&Color, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0); + + if (GraphicsOutput !=3D NULL) { + Status =3D GraphicsOutput->Blt ( + GraphicsOutput, + &Color, + EfiBltVideoFill, + 0, + 0, + 0, + PosY - EFI_GLYPH_HEIGHT - 1, + SizeOfX, + SizeOfY - (PosY - EFI_GLYPH_HEIGHT - 1), + SizeOfX * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) + ); + } else if (FeaturePcdGet (PcdUgaConsumeSupport)) { + Status =3D UgaDraw->Blt ( + UgaDraw, + (EFI_UGA_PIXEL *) &Color, + EfiUgaVideoFill, + 0, + 0, + 0, + PosY - EFI_GLYPH_HEIGHT - 1, + SizeOfX, + SizeOfY - (PosY - EFI_GLYPH_HEIGHT - 1), + SizeOfX * sizeof (EFI_UGA_PIXEL) + ); + } else { + return EFI_UNSUPPORTED; + } + } + // + // Show progress by drawing blocks + // + for (Index =3D PreviousValue; Index < BlockNum; Index++) { + PosX =3D Index * BlockWidth; + if (GraphicsOutput !=3D NULL) { + Status =3D GraphicsOutput->Blt ( + GraphicsOutput, + &ProgressColor, + EfiBltVideoFill, + 0, + 0, + PosX, + PosY, + BlockWidth - 1, + BlockHeight, + (BlockWidth) * sizeof (EFI_GRAPHICS_OUTPUT_BLT_P= IXEL) + ); + } else if (FeaturePcdGet (PcdUgaConsumeSupport)) { + Status =3D UgaDraw->Blt ( + UgaDraw, + (EFI_UGA_PIXEL *) &ProgressColor, + EfiUgaVideoFill, + 0, + 0, + PosX, + PosY, + BlockWidth - 1, + BlockHeight, + (BlockWidth) * sizeof (EFI_UGA_PIXEL) + ); + } else { + return EFI_UNSUPPORTED; + } + } + + PrintXY ( + (SizeOfX - StrLen (Title) * EFI_GLYPH_WIDTH) / 2, + PosY - EFI_GLYPH_HEIGHT - 1, + &TitleForeground, + &TitleBackground, + Title + ); + + return EFI_SUCCESS; +} + +/** + Perform the memory test base on the memory test intensive level, + and update the memory resource. + + @param Level The memory test intensive level. + + @retval EFI_STATUS Success test all the system memory and update + the memory resource + +**/ +EFI_STATUS +PlatformBootManagerMemoryTest ( + IN EXTENDMEM_COVERAGE_LEVEL Level + ) +{ + EFI_STATUS Status; + EFI_STATUS KeyStatus; + EFI_STATUS InitStatus; + EFI_STATUS ReturnStatus; + BOOLEAN RequireSoftECCInit; + EFI_GENERIC_MEMORY_TEST_PROTOCOL *GenMemoryTest; + UINT64 TestedMemorySize; + UINT64 TotalMemorySize; + UINTN TestPercent; + UINT64 PreviousValue; + BOOLEAN ErrorOut; + BOOLEAN TestAbort; + EFI_INPUT_KEY Key; + CHAR16 StrPercent[80]; + CHAR16 *StrTotalMemory; + CHAR16 *Pos; + CHAR16 *TmpStr; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Foreground; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Background; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Color; + UINT32 TempData; + UINTN StrTotalMemorySize; + + ReturnStatus =3D EFI_SUCCESS; + ZeroMem (&Key, sizeof (EFI_INPUT_KEY)); + + StrTotalMemorySize =3D 128; + Pos =3D AllocateZeroPool (StrTotalMemorySize); + ASSERT (Pos !=3D NULL); + + if (gStringPackHandle =3D=3D NULL) { + gStringPackHandle =3D HiiAddPackages ( + &mPlatformBootManagerStringPackGuid, + gImageHandle, + PlatformBootManagerLibStrings, + NULL + ); + ASSERT (gStringPackHandle !=3D NULL); + } + + StrTotalMemory =3D Pos; + + TestedMemorySize =3D 0; + TotalMemorySize =3D 0; + PreviousValue =3D 0; + ErrorOut =3D FALSE; + TestAbort =3D FALSE; + + SetMem (&Foreground, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff); + SetMem (&Background, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0x0); + SetMem (&Color, sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL), 0xff); + + RequireSoftECCInit =3D FALSE; + + Status =3D gBS->LocateProtocol ( + &gEfiGenericMemTestProtocolGuid, + NULL, + (VOID **) &GenMemoryTest + ); + if (EFI_ERROR (Status)) { + FreePool (Pos); + return EFI_SUCCESS; + } + + InitStatus =3D GenMemoryTest->MemoryTestInit ( + GenMemoryTest, + Level, + &RequireSoftECCInit + ); + if (InitStatus =3D=3D EFI_NO_MEDIA) { + // + // The PEI codes also have the relevant memory test code to check the = memory, + // it can select to test some range of the memory or all of them. If P= EI code + // checks all the memory, this BDS memory test will has no not-test me= mory to + // do the test, and then the status of EFI_NO_MEDIA will be returned by + // "MemoryTestInit". So it does not need to test memory again, just re= turn. + // + FreePool (Pos); + return EFI_SUCCESS; + } + + if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) { + TmpStr =3D HiiGetString (gStringPackHandle, STRING_TOKEN (STR_ESC_TO_S= KIP_MEM_TEST), NULL); + + if (TmpStr !=3D NULL) { + PrintXY (10, 10, NULL, NULL, TmpStr); + FreePool (TmpStr); + } + } else { + DEBUG ((DEBUG_INFO, "Enter memory test.\n")); + } + do { + Status =3D GenMemoryTest->PerformMemoryTest ( + GenMemoryTest, + &TestedMemorySize, + &TotalMemorySize, + &ErrorOut, + TestAbort + ); + if (ErrorOut && (Status =3D=3D EFI_DEVICE_ERROR)) { + TmpStr =3D HiiGetString (gStringPackHandle, STRING_TOKEN (STR_SYSTEM= _MEM_ERROR), NULL); + if (TmpStr !=3D NULL) { + PrintXY (10, 10, NULL, NULL, TmpStr); + FreePool (TmpStr); + } + + ASSERT (0); + } + + if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) { + TempData =3D (UINT32) DivU64x32 (TotalMemorySize, 16); + TestPercent =3D (UINTN) DivU64x32 ( + DivU64x32 (MultU64x32 (TestedMemorySize, 100= ), 16), + TempData + ); + if (TestPercent !=3D PreviousValue) { + UnicodeValueToString (StrPercent, 0, TestPercent, 0); + TmpStr =3D HiiGetString (gStringPackHandle, STRING_TOKEN (STR_MEMO= RY_TEST_PERCENT), NULL); + if (TmpStr !=3D NULL) { + // + // TmpStr size is 64, StrPercent is reserved to 16. + // + StrnCatS ( + StrPercent, + sizeof (StrPercent) / sizeof (CHAR16), + TmpStr, + sizeof (StrPercent) / sizeof (CHAR16) - StrLen (StrPercent) - 1 + ); + PrintXY (10, 10, NULL, NULL, StrPercent); + FreePool (TmpStr); + } + + TmpStr =3D HiiGetString (gStringPackHandle, STRING_TOKEN (STR_PERF= ORM_MEM_TEST), NULL); + if (TmpStr !=3D NULL) { + PlatformBootManagerShowProgress ( + Foreground, + Background, + TmpStr, + Color, + TestPercent, + (UINTN) PreviousValue + ); + FreePool (TmpStr); + } + } + + PreviousValue =3D TestPercent; + } else { + DEBUG ((DEBUG_INFO, "Perform memory test (ESC to skip).\n")); + } + + if (!PcdGetBool (PcdConInConnectOnDemand)) { + KeyStatus =3D gST->ConIn->ReadKeyStroke (gST->ConIn, &Key); + if (!EFI_ERROR (KeyStatus) && (Key.ScanCode =3D=3D SCAN_ESC)) { + if (!RequireSoftECCInit) { + if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) { + TmpStr =3D HiiGetString (gStringPackHandle, STRING_TOKEN (STR_= PERFORM_MEM_TEST), NULL); + if (TmpStr !=3D NULL) { + PlatformBootManagerShowProgress ( + Foreground, + Background, + TmpStr, + Color, + 100, + (UINTN) PreviousValue + ); + FreePool (TmpStr); + } + + PrintXY (10, 10, NULL, NULL, L"100"); + } + Status =3D GenMemoryTest->Finished (GenMemoryTest); + goto Done; + } + + TestAbort =3D TRUE; + } + } + } while (Status !=3D EFI_NOT_FOUND); + + Status =3D GenMemoryTest->Finished (GenMemoryTest); + +Done: + if (!FeaturePcdGet(PcdBootlogoOnlyEnable)) { + UnicodeValueToString (StrTotalMemory, COMMA_TYPE, TotalMemorySize, 0); + if (StrTotalMemory[0] =3D=3D L',') { + StrTotalMemory++; + StrTotalMemorySize -=3D sizeof (CHAR16); + } + + TmpStr =3D HiiGetString (gStringPackHandle, STRING_TOKEN (STR_MEM_TEST= _COMPLETED), NULL); + if (TmpStr !=3D NULL) { + StrnCatS ( + StrTotalMemory, + StrTotalMemorySize / sizeof (CHAR16), + TmpStr, + StrTotalMemorySize / sizeof (CHAR16) - StrLen (StrTotalMemory) - 1 + ); + FreePool (TmpStr); + } + + PrintXY (10, 10, NULL, NULL, StrTotalMemory); + PlatformBootManagerShowProgress ( + Foreground, + Background, + StrTotalMemory, + Color, + 100, + (UINTN) PreviousValue + ); + + } else { + DEBUG ((DEBUG_INFO, "%d bytes of system memory tested OK\r\n", TotalMe= morySize)); + } + + FreePool (Pos); + return ReturnStatus; +} + +/** + Convert a *.BMP graphics image to a GOP blt buffer. If a NULL Blt buffer + is passed in a GopBlt buffer will be allocated by this routine. If a Gop= Blt + buffer is passed in it will be used if it is big enough. + + @param BmpImage Pointer to BMP file + @param BmpImageSize Number of bytes in BmpImage + @param GopBlt Buffer containing GOP version of BmpImage. + @param GopBltSize Size of GopBlt in bytes. + @param PixelHeight Height of GopBlt/BmpImage in pixels + @param PixelWidth Width of GopBlt/BmpImage in pixels + + @retval EFI_SUCCESS GopBlt and GopBltSize are returned. + @retval EFI_UNSUPPORTED BmpImage is not a valid *.BMP image + @retval EFI_BUFFER_TOO_SMALL The passed in GopBlt buffer is not big eno= ugh. + GopBltSize will contain the required size. + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate. + +**/ +EFI_STATUS +PlatformBootManagerConvertBmpToGopBlt ( + IN VOID *BmpImage, + IN UINTN BmpImageSize, + IN OUT VOID **GopBlt, + IN OUT UINTN *GopBltSize, + OUT UINTN *PixelHeight, + OUT UINTN *PixelWidth + ) +{ + UINT8 *Image; + UINT8 *ImageHeader; + BMP_IMAGE_HEADER *BmpHeader; + BMP_COLOR_MAP *BmpColorMap; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *BltBuffer; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt; + UINT64 BltBufferSize; + UINTN Index; + UINTN Height; + UINTN Width; + UINTN ImageIndex; + UINT32 DataSizePerLine; + BOOLEAN IsAllocated; + UINT32 ColorMapNum; + + if (sizeof (BMP_IMAGE_HEADER) > BmpImageSize) { + DEBUG ((DEBUG_INFO, "BMP_IMAGE_HEADER) > BmpImageSize.\n")); + return EFI_INVALID_PARAMETER; + } + + BmpHeader =3D (BMP_IMAGE_HEADER *) BmpImage; + + if (BmpHeader->CharB !=3D 'B' || BmpHeader->CharM !=3D 'M') { + DEBUG ((DEBUG_INFO, "(BmpHeader->CharB !=3D 'B' || BmpHeader->CharM != =3D 'M').\n")); + return EFI_UNSUPPORTED; + } + + // + // Doesn't support compress. + // + if (BmpHeader->CompressionType !=3D 0) { + DEBUG ((DEBUG_INFO, "It's compressed! We dont support.\n")); + return EFI_UNSUPPORTED; + } + + // + // Only support BITMAPINFOHEADER format. + // BITMAPFILEHEADER + BITMAPINFOHEADER =3D BMP_IMAGE_HEADER + // + if (BmpHeader->HeaderSize !=3D sizeof (BMP_IMAGE_HEADER) - OFFSET_OF(BMP= _IMAGE_HEADER, HeaderSize)) { + DEBUG ((DEBUG_INFO, "Only support BITMAPINFOHEADER.\n")); + return EFI_UNSUPPORTED; + } + + // + // The data size in each line must be 4 byte alignment. + // + DataSizePerLine =3D ((BmpHeader->PixelWidth * BmpHeader->BitPerPixel + 3= 1) >> 3) & (~0x3); + BltBufferSize =3D MultU64x32 (DataSizePerLine, BmpHeader->PixelHeight); + if (BltBufferSize > (UINT32) ~0) { + DEBUG ((DEBUG_INFO, "The data size in each line must be 4 byte alignme= nt.\n")); + return EFI_INVALID_PARAMETER; + } + + if ((BmpHeader->Size !=3D BmpImageSize) || + (BmpHeader->Size < BmpHeader->ImageOffset) || + (BmpHeader->Size - BmpHeader->ImageOffset !=3D BmpHeader->PixelHeig= ht * DataSizePerLine)) { + DEBUG ((DEBUG_INFO, "BmpHeader->Size problem.\n")); + return EFI_INVALID_PARAMETER; + } + + // + // Calculate Color Map offset in the image. + // + Image =3D BmpImage; + BmpColorMap =3D (BMP_COLOR_MAP *) (Image + sizeof (BMP_IMAGE_HEADER)); + if (BmpHeader->ImageOffset < sizeof (BMP_IMAGE_HEADER)) { + DEBUG ((DEBUG_INFO, "BmpHeader->ImageOffset < sizeof (BMP_IMAGE_HEADER= )\n")); + return EFI_INVALID_PARAMETER; + } + + if (BmpHeader->ImageOffset > sizeof (BMP_IMAGE_HEADER)) { + switch (BmpHeader->BitPerPixel) { + case 1: + ColorMapNum =3D 2; + break; + case 4: + ColorMapNum =3D 16; + break; + case 8: + ColorMapNum =3D 256; + break; + default: + ColorMapNum =3D 0; + break; + } + // + // BMP file may has padding data between the bmp header section and th= e bmp data section. + // + if (BmpHeader->ImageOffset - sizeof (BMP_IMAGE_HEADER) < sizeof (BMP_C= OLOR_MAP) * ColorMapNum) { + DEBUG ((DEBUG_INFO, "(BmpHeader->ImageOffset - sizeof (BMP_IMAGE_HEA= DER) < sizeof (BMP_COLOR_MAP) * ColorMapNum)\n")); + return EFI_INVALID_PARAMETER; + } + } + + // + // Calculate graphics image data address in the image + // + Image =3D ((UINT8 *) BmpImage) + BmpHeader->ImageOffset; + ImageHeader =3D Image; + + // + // Calculate the BltBuffer needed size. + // + BltBufferSize =3D MultU64x32 ((UINT64) BmpHeader->PixelWidth, BmpHeader-= >PixelHeight); + // + // Ensure the BltBufferSize * sizeof (EFI_GRAPHICS_OUTPUT_BLT_PIXEL) doe= sn't overflow + // + if (BltBufferSize > DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OUTPUT_B= LT_PIXEL))) { + return EFI_UNSUPPORTED; + } + BltBufferSize =3D MultU64x32 (BltBufferSize, sizeof (EFI_GRAPHICS_OUTPUT= _BLT_PIXEL)); + + IsAllocated =3D FALSE; + if (*GopBlt =3D=3D NULL) { + // + // GopBlt is not allocated by caller. + // + *GopBltSize =3D (UINTN) BltBufferSize; + *GopBlt =3D AllocatePool (*GopBltSize); + IsAllocated =3D TRUE; + if (*GopBlt =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "EFI_OUT_OF_RESOURCES\n")); + return EFI_OUT_OF_RESOURCES; + } + } else { + // + // GopBlt has been allocated by caller. + // + if (*GopBltSize < (UINTN) BltBufferSize) { + *GopBltSize =3D (UINTN) BltBufferSize; + DEBUG ((DEBUG_INFO, "EEFI_BUFFER_TOO_SMALL\n")); + return EFI_BUFFER_TOO_SMALL; + } + } + + *PixelWidth =3D BmpHeader->PixelWidth; + *PixelHeight =3D BmpHeader->PixelHeight; + + // + // Convert image from BMP to Blt buffer format + // + BltBuffer =3D *GopBlt; + for (Height =3D 0; Height < BmpHeader->PixelHeight; Height++) { + Blt =3D &BltBuffer[(BmpHeader->PixelHeight - Height - 1) * BmpHeader->= PixelWidth]; + for (Width =3D 0; Width < BmpHeader->PixelWidth; Width++, Image++, Blt= ++) { + switch (BmpHeader->BitPerPixel) { + case 1: + // + // Convert 1-bit (2 colors) BMP to 24-bit color + // + for (Index =3D 0; Index < 8 && Width < BmpHeader->PixelWidth; Inde= x++) { + Blt->Red =3D BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Red; + Blt->Green =3D BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Gre= en; + Blt->Blue =3D BmpColorMap[((*Image) >> (7 - Index)) & 0x1].Blu= e; + Blt++; + Width++; + } + + Blt--; + Width--; + break; + + case 4: + // + // Convert 4-bit (16 colors) BMP Palette to 24-bit color + // + Index =3D (*Image) >> 4; + Blt->Red =3D BmpColorMap[Index].Red; + Blt->Green =3D BmpColorMap[Index].Green; + Blt->Blue =3D BmpColorMap[Index].Blue; + if (Width < (BmpHeader->PixelWidth - 1)) { + Blt++; + Width++; + Index =3D (*Image) & 0x0f; + Blt->Red =3D BmpColorMap[Index].Red; + Blt->Green =3D BmpColorMap[Index].Green; + Blt->Blue =3D BmpColorMap[Index].Blue; + } + break; + + case 8: + // + // Convert 8-bit (256 colors) BMP Palette to 24-bit color + // + Blt->Red =3D BmpColorMap[*Image].Red; + Blt->Green =3D BmpColorMap[*Image].Green; + Blt->Blue =3D BmpColorMap[*Image].Blue; + break; + + case 24: + // + // It is 24-bit BMP. + // + Blt->Blue =3D *Image++; + Blt->Green =3D *Image++; + Blt->Red =3D *Image; + break; + + default: + // + // Other bit format BMP is not supported. + // + if (IsAllocated) { + FreePool (*GopBlt); + *GopBlt =3D NULL; + } + DEBUG ((DEBUG_INFO, "Other bit format BMP is not supported.\n")); + return EFI_UNSUPPORTED; + break; + }; + + } + + ImageIndex =3D (UINTN) (Image - ImageHeader); + if ((ImageIndex % 4) !=3D 0) { + // + // Bmp Image starts each row on a 32-bit boundary! + // + Image =3D Image + (4 - (ImageIndex % 4)); + } + } + + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/P= latformBootManager.c b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootMa= nagerLib/PlatformBootManager.c new file mode 100644 index 00000000..9ef85089 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Platform= BootManager.c @@ -0,0 +1,274 @@ +/** @file + This file include all platform action which can be customized + by IBV/OEM. + +Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights = reserved.
+Copyright (c) 2015, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PlatformBootManager.h" + + +EFI_GUID mUefiShellFileGuid =3D { 0x7C04A583, 0x9E3E, 0x4f1c, {0xAD, 0x65,= 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1}}; + +/** + Perform the platform diagnostic, such like test memory. OEM/IBV also + can customize this function to support specific platform diagnostic. + + @param MemoryTestLevel The memory test intensive level + @param QuietBoot Indicate if need to enable the quiet boot + +**/ +VOID +PlatformBootManagerDiagnostics ( + IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel, + IN BOOLEAN QuietBoot + ) +{ + EFI_STATUS Status; + + // + // Here we can decide if we need to show + // the diagnostics screen + // Notes: this quiet boot code should be remove + // from the graphic lib + // + if (QuietBoot) { + + // + // Perform system diagnostic + // + Status =3D PlatformBootManagerMemoryTest (MemoryTestLevel); + return; + } + + // + // Perform system diagnostic + // + Status =3D PlatformBootManagerMemoryTest (MemoryTestLevel); +} + +/** + Return the index of the load option in the load option array. + + The function consider two load options are equal when the + OptionType, Attributes, Description, FilePath and OptionalData are equal. + + @param Key Pointer to the load option to be found. + @param Array Pointer to the array of load options to be found. + @param Count Number of entries in the Array. + + @retval -1 Key wasn't found in the Array. + @retval 0 ~ Count-1 The index of the Key in the Array. +**/ +INTN +PlatformFindLoadOption ( + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key, + IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array, + IN UINTN Count + ) +{ + UINTN Index; + + for (Index =3D 0; Index < Count; Index++) { + if ((Key->OptionType =3D=3D Array[Index].OptionType) && + (Key->Attributes =3D=3D Array[Index].Attributes) && + (StrCmp (Key->Description, Array[Index].Description) =3D=3D 0) && + (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSi= ze (Key->FilePath)) =3D=3D 0) && + (Key->OptionalDataSize =3D=3D Array[Index].OptionalDataSize) && + (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->Op= tionalDataSize) =3D=3D 0)) { + return (INTN) Index; + } + } + + return -1; +} + +VOID +PlatformRegisterFvBootOption ( + EFI_GUID *FileGuid, + CHAR16 *Description, + UINT32 Attributes + ) +{ + EFI_STATUS Status; + UINTN OptionIndex; + EFI_BOOT_MANAGER_LOAD_OPTION NewOption; + EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions; + UINTN BootOptionCount; + MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode; + EFI_LOADED_IMAGE_PROTOCOL *LoadedImage; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + + Status =3D gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGu= id, (VOID **) &LoadedImage); + ASSERT_EFI_ERROR (Status); + + EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid); + DevicePath =3D AppendDevicePathNode ( + DevicePathFromHandle (LoadedImage->DeviceHandle), + (EFI_DEVICE_PATH_PROTOCOL *) &FileNode + ); + + Status =3D EfiBootManagerInitializeLoadOption ( + &NewOption, + LoadOptionNumberUnassigned, + LoadOptionTypeBoot, + Attributes, + Description, + DevicePath, + NULL, + 0 + ); + if (!EFI_ERROR (Status)) { + BootOptions =3D EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOp= tionTypeBoot); + + OptionIndex =3D PlatformFindLoadOption (&NewOption, BootOptions, BootO= ptionCount); + + if (OptionIndex =3D=3D -1) { + Status =3D EfiBootManagerAddLoadOptionVariable (&NewOption, (UINTN) = -1); + ASSERT_EFI_ERROR (Status); + } + EfiBootManagerFreeLoadOption (&NewOption); + EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount); + } +} + +/** + Do the platform specific action before the console is connected. + + Such as: + Update console variable; + Register new Driver#### or Boot####; + Signal ReadyToLock event. +**/ +VOID +EFIAPI +PlatformBootManagerBeforeConsole ( + VOID + ) +{ + UINTN Index; + EFI_STATUS Status; + EFI_INPUT_KEY Enter; + EFI_INPUT_KEY F2; + EFI_BOOT_MANAGER_LOAD_OPTION BootOption; + + // + // Update the console variables. + // + for (Index =3D 0; gPlatformConsole[Index].DevicePath !=3D NULL; Index++)= { + DEBUG ((DEBUG_INFO, "Check gPlatformConsole %d\n", Index)); + if ((gPlatformConsole[Index].ConnectType & CONSOLE_IN) =3D=3D CONSOLE_= IN) { + Status =3D EfiBootManagerUpdateConsoleVariable (ConIn, gPlatformCons= ole[Index].DevicePath, NULL); + DEBUG ((DEBUG_INFO, "CONSOLE_IN variable set %s : %r\n", ConvertDevi= cePathToText (gPlatformConsole[Index].DevicePath, FALSE, FALSE), Status)); + } + + if ((gPlatformConsole[Index].ConnectType & CONSOLE_OUT) =3D=3D CONSOLE= _OUT) { + Status =3D EfiBootManagerUpdateConsoleVariable (ConOut, gPlatformCon= sole[Index].DevicePath, NULL); + DEBUG ((DEBUG_INFO, "CONSOLE_OUT variable set %s : %r\n", ConvertDev= icePathToText (gPlatformConsole[Index].DevicePath, FALSE, FALSE), Status)); + } + + if ((gPlatformConsole[Index].ConnectType & STD_ERROR) =3D=3D STD_ERROR= ) { + Status =3D EfiBootManagerUpdateConsoleVariable (ErrOut, gPlatformCon= sole[Index].DevicePath, NULL); + DEBUG ((DEBUG_INFO, "STD_ERROR variable set %r", Status)); + } + } + + // + // Register ENTER as CONTINUE key + // + Enter.ScanCode =3D SCAN_NULL; + Enter.UnicodeChar =3D CHAR_CARRIAGE_RETURN; + EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL); + // + // Map F2 to Boot Manager Menu + // + F2.ScanCode =3D SCAN_F2; + F2.UnicodeChar =3D CHAR_NULL; + EfiBootManagerGetBootManagerMenu (&BootOption); + EfiBootManagerAddKeyOptionVariable (NULL, (UINT16) BootOption.OptionNumb= er, 0, &F2, NULL); + // + // Register UEFI Shell + // + PlatformRegisterFvBootOption (&mUefiShellFileGuid, L"UEFI Shell", LOAD_O= PTION_ACTIVE); +} + +/** + Do the platform specific action after the console is connected. + + Such as: + Dynamically switch output mode; + Signal console ready platform customized event; + Run diagnostics like memory testing; + Connect certain devices; + Dispatch aditional option roms. +**/ +VOID +EFIAPI +PlatformBootManagerAfterConsole ( + VOID + ) +{ + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL White; + + Black.Blue =3D Black.Green =3D Black.Red =3D Black.Reserved =3D 0; + White.Blue =3D White.Green =3D White.Red =3D White.Reserved =3D 0xFF; + + EfiBootManagerConnectAll (); + EfiBootManagerRefreshAllBootOption (); + + PlatformBootManagerDiagnostics (QUICK, TRUE); + + PrintXY (10, 10, &White, &Black, L"F2 to enter Boot Manager Menu. = "); + PrintXY (10, 30, &White, &Black, L"Enter to boot directly."); +} + +/** + This function is called each second during the boot manager waits the ti= meout. + + @param TimeoutRemain The remaining timeout. +**/ +VOID +EFIAPI +PlatformBootManagerWaitCallback ( + UINT16 TimeoutRemain + ) +{ + EFI_GRAPHICS_OUTPUT_BLT_PIXEL Black; + EFI_GRAPHICS_OUTPUT_BLT_PIXEL White; + UINT16 Timeout; + + Timeout =3D PcdGet16 (PcdPlatformBootTimeOut); + + Black.Blue =3D Black.Green =3D Black.Red =3D Black.Reserved =3D 0; + White.Blue =3D White.Green =3D White.Red =3D White.Reserved =3D 0xFF; + + PlatformBootManagerShowProgress ( + White, + Black, + L"Start boot option", + White, + (Timeout - TimeoutRemain) * 100 / Timeout, + 0 + ); +} + +/** + The function is called when no boot option could be launched, + including platform recovery options and options pointing to applications + built into firmware volumes. + + If this function returns, BDS attempts to enter an infinite loop. +**/ +VOID +EFIAPI +PlatformBootManagerUnableToBoot ( + VOID + ) +{ + return; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/P= latformBootManager.h b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootMa= nagerLib/PlatformBootManager.h new file mode 100644 index 00000000..20d66758 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Platform= BootManager.h @@ -0,0 +1,135 @@ +/**@file + Head file for BDS Platform specific code + +Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All rights = reserved.
+Copyright (c) 2015, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_BOOT_MANAGER_H_ +#define _PLATFORM_BOOT_MANAGER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + UINTN ConnectType; +} PLATFORM_CONSOLE_CONNECT_ENTRY; + +extern PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[]; + +#define gEndEntire \ + { \ + END_DEVICE_PATH_TYPE,\ + END_ENTIRE_DEVICE_PATH_SUBTYPE,\ + END_DEVICE_PATH_LENGTH,\ + 0\ + } + +#define CONSOLE_OUT BIT0 +#define CONSOLE_IN BIT1 +#define STD_ERROR BIT2 + +//D3987D4B-971A-435F-8CAF-4967EB627241 +#define EFI_SERIAL_DXE_GUID \ + { 0xD3987D4B, 0x971A, 0x435F, { 0x8C, 0xAF, 0x49, 0x67, 0xEB, 0x62, 0x72= , 0x41 } } + +typedef struct { + VENDOR_DEVICE_PATH Guid; + UART_DEVICE_PATH Uart; + VENDOR_DEVICE_PATH TerminalType; + EFI_DEVICE_PATH_PROTOCOL End; +} SERIAL_CONSOLE_DEVICE_PATH; + +/** + Use SystemTable Conout to stop video based Simple Text Out consoles from= going + to the video device. Put up LogoFile on every video device that is a con= sole. + + @param[in] LogoFile File name of logo to display on the center of the= screen. + + @retval EFI_SUCCESS ConsoleControl has been flipped to graphics and = logo displayed. + @retval EFI_UNSUPPORTED Logo not found + +**/ +EFI_STATUS +PlatformBootManagerEnableQuietBoot ( + IN EFI_GUID *LogoFile + ); + +/** + Use SystemTable Conout to turn on video based Simple Text Out consoles. = The + Simple Text Out screens will now be synced up with all non video output = devices + + @retval EFI_SUCCESS UGA devices are back in text mode and synced up. + +**/ +EFI_STATUS +PlatformBootManagerDisableQuietBoot ( + VOID + ); + +/** + Perform the memory test base on the memory test intensive level, + and update the memory resource. + + @param Level The memory test intensive level. + + @retval EFI_STATUS Success test all the system memory and update + the memory resource + +**/ +EFI_STATUS +PlatformBootManagerMemoryTest ( + IN EXTENDMEM_COVERAGE_LEVEL Level + ); + +/** + + Show progress bar with title above it. It only works in Graphics mode. + + + @param TitleForeground Foreground color for Title. + @param TitleBackground Background color for Title. + @param Title Title above progress bar. + @param ProgressColor Progress bar color. + @param Progress Progress (0-100) + @param PreviousValue The previous value of the progress. + + @retval EFI_STATUS Success update the progress bar + +**/ +EFI_STATUS +PlatformBootManagerShowProgress ( + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground, + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground, + IN CHAR16 *Title, + IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor, + IN UINTN Progress, + IN UINTN PreviousValue + ); + +#endif // _PLATFORM_BOOT_MANAGER_H diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/P= latformBootManagerLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformB= ootManagerLib/PlatformBootManagerLib.inf new file mode 100644 index 00000000..92c31db4 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Platform= BootManagerLib.inf @@ -0,0 +1,63 @@ +## @file +# Include all platform action which can be customized by IBV/OEM. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformBootManagerLib + FILE_GUID =3D 7DDA7916-6139-4D46-A415-30E854AF3BC7 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformBootManagerLib|DXE_DRIVER + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + PlatformData.c + PlatformBootManager.c + PlatformBootManager.h + MemoryTest.c + Strings.uni + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiLib + UefiBootManagerLib + PcdLib + DxeServicesLib + MemoryAllocationLib + DevicePathLib + HiiLib + PrintLib + +[Guids] + +[Protocols] + gEfiGenericMemTestProtocolGuid ## CONSUMES + gEfiGraphicsOutputProtocolGuid ## CONSUMES + gEfiUgaDrawProtocolGuid ## CONSUMES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn + gEfiMdePkgTokenSpaceGuid.PcdUgaConsumeSupport + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootlogoOnlyEnable diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/P= latformData.c b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLi= b/PlatformData.c new file mode 100644 index 00000000..3208051e --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Platform= Data.c @@ -0,0 +1,49 @@ +/**@file + Defined the platform specific device path which will be filled to + ConIn/ConOut variables. + +Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights = reserved.
+Copyright (c) 2015, Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PlatformBootManager.h" + +// +// Platform specific serial device path +// +SERIAL_CONSOLE_DEVICE_PATH gSerialConsoleDevicePath0 =3D { + { + { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH), 0= } }, + EFI_SERIAL_DXE_GUID // Use the driver's GUID + }, + { + { MESSAGING_DEVICE_PATH, MSG_UART_DP, { sizeof (UART_DEVICE_PATH), 0} = }, + 0, // Reserved + 115200, // BaudRate + 8, // DataBits + 1, // Parity + 1 // StopBits + }, + { + { MESSAGING_DEVICE_PATH, MSG_VENDOR_DP, { sizeof (VENDOR_DEVICE_PATH),= 0} }, + DEVICE_PATH_MESSAGING_PC_ANSI + }, + { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DE= VICE_PATH_PROTOCOL), 0 } } +}; + +// +// Predefined platform default console device path +// +PLATFORM_CONSOLE_CONNECT_ENTRY gPlatformConsole[] =3D { + { + (EFI_DEVICE_PATH_PROTOCOL *) &gSerialConsoleDevicePath0, + CONSOLE_OUT | CONSOLE_IN + }, + { + NULL, + 0 + } +}; diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/S= trings.uni b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/S= trings.uni new file mode 100644 index 00000000..73bf5d51 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Strings.= uni @@ -0,0 +1,28 @@ +///** @file +// +// String definitions for PlatformBootManagerLib. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rig= hts reserved.
+// Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//**/ + +/=3D# + +#langdef en-US "English" +#langdef fr-FR "Fran=C3=A7ais" + +#string STR_PERFORM_MEM_TEST #language en-US "Perform memory te= st (ESC to skip)" + #language fr-FR "Ex=C3=A9cute l'ex= amen de m=C3=A9moire (ESC pour sauter)" +#string STR_MEMORY_TEST_PERCENT #language en-US "% of the system m= emory tested OK" + #language fr-FR "% de la m=C3=A9mo= ire de syst=C3=A8me essay=C3=A9e D'ACCORD" +#string STR_ESC_TO_SKIP_MEM_TEST #language en-US "Press ESC key to = skip memory test" + #language fr-FR "Appuie sur ESC sa= uter examen de m=C3=A9moire" +#string STR_MEM_TEST_COMPLETED #language en-US " bytes of system = memory tested OK\r\n" + #language fr-FR "octets dela m=C3= =A9moire de syst=C3=A8me essay=C3=A9e D'ACCORD\r\n" +#string STR_SYSTEM_MEM_ERROR #language en-US "System encounters= memory errors" + #language fr-FR "le Syst=C3=A8me r= encontre les erreurs de m=C3=A9moire" +#string STR_START_BOOT_OPTION #language en-US "Start boot option" + #language fr-FR "l'option de botte= de D=C3=A9but" --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47542): https://edk2.groups.io/g/devel/message/47542 Mute This Topic: https://groups.io/mt/34196357/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47543+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47543+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865110; cv=none; d=zoho.com; s=zohoarc; b=UVortyml0BC+rbr/APEgzKnvykb+f1akz6rtfiqGoMkroJBR8yIA/qPDxRhw/WLCWP1tHtdvToHI+25DmE3Y9+nPgnxc5fWehbU7F53iT61Fhz10u202LrKUhjUIID66KClYQIJm4FtzeS/+mWRvrWPSaFQcoQGPbUwlFVSfp+0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865110; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=IwhgJTq+qdpuckmo09aK/kYFfov/I2bxiVwk210lYQg=; b=fkw2idvtMjOfG7SXJTPKTI3hOLEnZqmTWHX0HqBMuhVPRLX21bq7iZis6Rrj1hB6GzBe1+rnpx02Nn7qe53g8KFIOeS8ONMw6dVn0QCRxJjnOhx6p9ja+e/PI4imN1IiL86PPKj575SrQ+qR84vrfuQ7zYI2oS3DA34dfejriek= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47543+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156886511021467.62391653977613; Wed, 18 Sep 2019 20:51:50 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id w2n3YY1788612xhH1SDScUhf; Wed, 18 Sep 2019 20:51:49 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:48 -0700 X-Received: from pps.filterd (m0134421.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pKqo017013 for ; Thu, 19 Sep 2019 03:51:47 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v3vatnf60-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:47 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id DA1D055 for ; Thu, 19 Sep 2019 03:51:46 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 177CE45 for ; Thu, 19 Sep 2019 03:51:45 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 10/14] U500Pkg/Library: Library instances of U500 platform library Date: Thu, 19 Sep 2019 11:51:27 +0800 Message-Id: <20190919035131.4700-11-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: 4jafPVaLBrop6oZYv9j3fOjrx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865109; bh=v0MH/Uyfi35fBwXCaQMrnFuyE819/V1sX77svx5Gd0I=; h=Date:From:Reply-To:Subject:To; b=dyK9/K/HmhYry17WSKc8UNxDtN8D2HP+5F3JplNcrJFqr4jTz84LBSRUpCDD/yGDmoP dBbLcdO6miPEFfP1l5+9yeoxylbbJX2fo1OnE9p32mpEJ8y+INbQyoB7mCURExxiZBIoF f+WMgEGqBsm6sLhpyDNgdKEwPyG76MYOyuI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" OpneSbiPlatformLib - In order to reduce the dependencies with RISC-V OpenSBI project (https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the implementation of RISC-V EDK2 platform is leverage platform source code from OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build environment. PeiCoreInfoHobLib - This is the library to create RISC-V core characteristics for building up RISC-V related SMBIOS records to support the unified boot loader and OS image. - RiscVPlatformTimerLib This is U500 platform timer library which has the platform-specific timer implementation. - SerialPortLib U500 serial port platform library Signed-off-by: Gilbert Chen --- .../OpenSbiPlatformLib/OpenSbiPlatformLib.inf | 47 ++++ .../U500Pkg/Library/OpenSbiPlatformLib/platform.c | 214 ++++++++++++++++++ .../Library/PeiCoreInfoHobLib/CoreInfoHob.c | 195 +++++++++++++++++ .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf | 58 +++++ .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.S | 48 ++++ .../RiscVPlatformTimerLib.inf | 39 ++++ .../U500Pkg/Library/SerialIoLib/SerialIoLib.inf | 31 +++ .../U500Pkg/Library/SerialIoLib/SerialPortLib.c | 241 +++++++++++++++++= ++++ .../Library/SerialIoLib/U500SerialPortLib.uni | 16 ++ 9 files changed, 889 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLi= b/OpenSbiPlatformLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLi= b/platform.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib= /CoreInfoHob.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib= /PeiCoreInfoHobLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTime= rLib/RiscVPlatformTimerLib.S create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTime= rLib/RiscVPlatformTimerLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/Seria= lIoLib.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/Seria= lPortLib.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500S= erialPortLib.uni diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenS= biPlatformLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLi= b/OpenSbiPlatformLib.inf new file mode 100644 index 00000000..473386d2 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatf= ormLib.inf @@ -0,0 +1,47 @@ +## @file +# RISC-V OpenSbi Platform Library +# This is the the required library which provides platform +# level opensbi functions follow RISC-V opensbi implementation. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D OpenSbiPlatformLib + FILE_GUID =3D 9424ED54-EBDA-4FB5-8FF6-8291B07BB151 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D OpenSbiPlatformLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 EBC +# + +[Sources] + platform.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + PcdLib + DebugAgentLib + RiscVCpuLib + PrintLib + +[FixedPcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platf= orm.c b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c new file mode 100644 index 00000000..4dca75f2 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c @@ -0,0 +1,214 @@ +/* + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates. + * + * Authors: + * Atish Patra + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define U500_HART_COUNT FixedPcdGet32(PcdHartCount) +#define U500_HART_STACK_SIZE FixedPcdGet32(PcdOpenSbiStackSize) +#define U500_BOOT_HART_ID FixedPcdGet32(PcdBootHartId) + +#define U500_SYS_CLK 100000000 + +#define U500_CLINT_ADDR 0x2000000 + +#define U500_PLIC_ADDR 0xc000000 +#define U500_PLIC_NUM_SOURCES 0x35 +#define U500_PLIC_NUM_PRIORITIES 7 + +#define U500_UART_ADDR 0x54000000 + +#define U500_UART_BAUDRATE 115200 + +/** + * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode. + * HARTs 1 is selected as boot HART + */ +#ifndef U500_ENABLED_HART_MASK +#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID) +#endif + +#define U500_HARTID_DISABLED ~(U500_ENABLED_HART_MASK) + +/* PRCI clock related macros */ +//TODO: Do we need a separate driver for this ? +#define U500_PRCI_BASE_ADDR 0x10000000 +#define U500_PRCI_CLKMUXSTATUSREG 0x002C +#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL (0x1 << 1) + +static void U500_modify_dt(void *fdt) +{ + u32 i, size; + int chosen_offset, err; + int cpu_offset; + char cpu_node[32] =3D ""; + const char *mmu_type; + + for (i =3D 0; i < U500_HART_COUNT; i++) { + sbi_sprintf(cpu_node, "/cpus/cpu@%d", i); + cpu_offset =3D fdt_path_offset(fdt, cpu_node); + mmu_type =3D fdt_getprop(fdt, cpu_offset, "mmu-type", NULL); + if (mmu_type && (!strcmp(mmu_type, "riscv,sv39") || + !strcmp(mmu_type,"riscv,sv48"))) + continue; + else + fdt_setprop_string(fdt, cpu_offset, "status", "masked"); + memset(cpu_node, 0, sizeof(cpu_node)); + } + size =3D fdt_totalsize(fdt); + err =3D fdt_open_into(fdt, fdt, size + 256); + if (err < 0) + sbi_printf("Device Tree can't be expanded to accmodate new node"); + + chosen_offset =3D fdt_path_offset(fdt, "/chosen"); + fdt_setprop_string(fdt, chosen_offset, "stdout-path", + "/soc/serial@10010000:115200"); + + plic_fdt_fixup(fdt, "riscv,plic0"); +} + +static int U500_final_init(bool cold_boot) +{ + void *fdt; + + if (!cold_boot) + return 0; + + fdt =3D sbi_scratch_thishart_arg1_ptr(); + U500_modify_dt(fdt); + + return 0; +} + +static u32 U500_pmp_region_count(u32 hartid) +{ + return 1; +} + +static int U500_pmp_region_info(u32 hartid, u32 index, + ulong *prot, ulong *addr, ulong *log2size) +{ + int ret =3D 0; + + switch (index) { + case 0: + *prot =3D PMP_R | PMP_W | PMP_X; + *addr =3D 0; + *log2size =3D __riscv_xlen; + break; + default: + ret =3D -1; + break; + }; + + return ret; +} + +static int U500_console_init(void) +{ + unsigned long peri_in_freq; + + peri_in_freq =3D U500_SYS_CLK/2; + return sifive_uart_init(U500_UART_ADDR, peri_in_freq, U500_UART_BAUDRAT= E); +} + +static int U500_irqchip_init(bool cold_boot) +{ + int rc; + u32 hartid =3D sbi_current_hartid(); + + if (cold_boot) { + rc =3D plic_cold_irqchip_init(U500_PLIC_ADDR, + U500_PLIC_NUM_SOURCES, + U500_HART_COUNT); + if (rc) + return rc; + } + + return plic_warm_irqchip_init(hartid, + (hartid) ? (2 * hartid - 1) : 0, + (hartid) ? (2 * hartid) : -1); +} + +static int U500_ipi_init(bool cold_boot) +{ + int rc; + + if (cold_boot) { + rc =3D clint_cold_ipi_init(U500_CLINT_ADDR, + U500_HART_COUNT); + if (rc) + return rc; + + } + + return clint_warm_ipi_init(); +} + +static int U500_timer_init(bool cold_boot) +{ + int rc; + + if (cold_boot) { + rc =3D clint_cold_timer_init(U500_CLINT_ADDR, + U500_HART_COUNT); + if (rc) + return rc; + } + + return clint_warm_timer_init(); +} + +static int U500_system_down(u32 type) +{ + /* For now nothing to do. */ + return 0; +} + +const struct sbi_platform_operations platform_ops =3D { + .pmp_region_count =3D U500_pmp_region_count, + .pmp_region_info =3D U500_pmp_region_info, + .final_init =3D U500_final_init, + .console_putc =3D sifive_uart_putc, + .console_getc =3D sifive_uart_getc, + .console_init =3D U500_console_init, + .irqchip_init =3D U500_irqchip_init, + .ipi_send =3D clint_ipi_send, + .ipi_sync =3D clint_ipi_sync, + .ipi_clear =3D clint_ipi_clear, + .ipi_init =3D U500_ipi_init, + .timer_value =3D clint_timer_value, + .timer_event_stop =3D clint_timer_event_stop, + .timer_event_start =3D clint_timer_event_start, + .timer_init =3D U500_timer_init, + .system_reboot =3D U500_system_down, + .system_shutdown =3D U500_system_down +}; + +const struct sbi_platform platform =3D { + .opensbi_version =3D OPENSBI_VERSION, // The OpenSBI= version this platform table is built bassed on. + .platform_version =3D SBI_PLATFORM_VERSION(0x0001, 0x0000), // SBI = Platform version 1.0 + .name =3D "SiFive Freedom U500", + .features =3D SBI_PLATFORM_DEFAULT_FEATURES, + .hart_count =3D U500_HART_COUNT, + .hart_stack_size =3D U500_HART_STACK_SIZE, + .disabled_hart_mask =3D U500_HARTID_DISABLED, + .platform_ops_addr =3D (unsigned long)&platform_ops +}; diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreIn= foHob.c b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoH= ob.c new file mode 100644 index 00000000..bfb97351 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c @@ -0,0 +1,195 @@ +/**@file + Build up platform processor information. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include + +#include +#include +#include +#include +#include + +/** + Build up processor-specific HOB for U5MC Coreplex + + @param UniqueId Unique ID of this U5MC Coreplex processor + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU5MCCoreplexProcessorSpecificDataHob ( + IN UINTN UniqueId + ) +{ + EFI_STATUS Status; + UINT32 HartIdNumber; + RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *GuidHobData; + EFI_GUID *ParentCoreGuid; + BOOLEAN MCSupport; + + DEBUG ((DEBUG_INFO, "Building U5 Coreplex processor information HOB\n")); + + HartIdNumber =3D 0; + ParentCoreGuid =3D PcdGetPtr(PcdSiFiveU5MCCoreplexGuid); + MCSupport =3D PcdGetBool (PcdE5MCSupported); + if (MCSupport =3D=3D TRUE) { + Status =3D CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, Uniq= ueId, HartIdNumber, FALSE, &GuidHobData); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\= n")); + ASSERT (FALSE); + } + HartIdNumber ++; + DEBUG ((DEBUG_INFO, "Support E5 Monitor core on U500 platform, HOB at = address 0x%x\n", GuidHobData)); + } + for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSu= pport); HartIdNumber ++) { + Status =3D CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, Uniq= ueId, HartIdNumber, (HartIdNumber =3D=3D FixedPcdGet32 (PcdBootHartId))? TR= UE: FALSE, &GuidHobData); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\= n")); + ASSERT (FALSE); + } + DEBUG ((DEBUG_INFO, "Support U5 application core on U500 platform, HOB= Data at address 0x%x\n", GuidHobData)); + } + DEBUG ((DEBUG_INFO, "Support %d U5 application cores on U500 platform\n"= , HartIdNumber - (UINT32)MCSupport)); + + if (HartIdNumber !=3D FixedPcdGet32 (PcdHartCount)) { + DEBUG ((DEBUG_ERROR, "Improper core settings...\n")); + DEBUG ((DEBUG_ERROR, " PcdHartCount\n")); + DEBUG ((DEBUG_ERROR, " PcdNumberofU5Cores\n")); + DEBUG ((DEBUG_ERROR, " PcdE5MCSupported\n\n")); + ASSERT (FALSE); + } + return Status; +} + +/** + Function to build processor related SMBIOS information. RISC-V SMBIOS DX= E driver collect + this information and build SMBIOS Type4 and Type7 record. + + @param ProcessorUid Unique ID of pysical processor which owns this c= ore. + @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_= HOB. The pointers + maintained in this structure is only valid befor= e memory is discovered. + Access to those pointers after memory is install= ed will cause unexpected issues. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +CreateU5MCProcessorSmbiosDataHob ( + IN UINTN ProcessorUid, + OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr + ) +{ + EFI_GUID *GuidPtr; + RISC_V_PROCESSOR_TYPE4_DATA_HOB ProcessorDataHob; + RISC_V_PROCESSOR_TYPE7_DATA_HOB L2CacheDataHob; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB SmbiosDataHob; + RISC_V_PROCESSOR_TYPE4_DATA_HOB *ProcessorDataHobPtr; + RISC_V_PROCESSOR_TYPE7_DATA_HOB *L2CacheDataHobPtr; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosDataHobPtr; + + DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__)); + + if (SmbiosHobPtr =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Build up SMBIOS type 7 L2 cache record. + // + ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HOB= )); + L2CacheDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCo= replexGuid)); + L2CacheDataHob.ProcessorUid =3D ProcessorUid; + L2CacheDataHob.SmbiosType7Cache.SocketDesignation =3D TO_BE_FILLED_BY_VE= NDOR; + L2CacheDataHob.SmbiosType7Cache.CacheConfiguration =3D RISC_V_CACHE_CONF= IGURATION_CACHE_LEVEL_2 | \ + RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \ + RISC_V_CACHE_CONFIGURATION_ENABLED | \ + RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN; + L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize =3D TO_BE_FILLED_BY_VEN= DOR; + L2CacheDataHob.SmbiosType7Cache.InstalledSize =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown =3D 1; + L2CacheDataHob.SmbiosType7Cache.CacheSpeed =3D TO_BE_FILLED_BY_VENDOR; + L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType =3D TO_BE_FILLED_BY_= VENDOR; + L2CacheDataHob.SmbiosType7Cache.SystemCacheType =3D CacheTypeUnified; + L2CacheDataHob.SmbiosType7Cache.Associativity =3D TO_BE_FILLED_BY_VENDOR; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid); + L2CacheDataHobPtr =3D (RISC_V_PROCESSOR_TYPE7_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_DATA_HO= B)); + if (L2CacheDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex= L2 cache RISC_V_PROCESSOR_TYPE7_DATA_HOB.\n")); + ASSERT (FALSE); + } + + // + // Build up SMBIOS type 4 record. + // + ZeroMem((VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DATA_H= OB)); + ProcessorDataHob.PrcessorGuid =3D *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MC= CoreplexGuid)); + ProcessorDataHob.ProcessorUid =3D ProcessorUid; + ProcessorDataHob.SmbiosType4Processor.Socket =3D TO_BE_FILLED_BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.ProcessorType =3D CentralProcessor; + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily =3D ProcessorFamil= yIndicatorFamily2; + ProcessorDataHob.SmbiosType4Processor.ProcessorManufacture =3D TO_BE_FIL= LED_BY_VENDOR; + SetMem ((VOID *)&ProcessorDataHob.SmbiosType4Processor.ProcessorId, size= of (PROCESSOR_ID_DATA), TO_BE_FILLED_BY_CODE); + ProcessorDataHob.SmbiosType4Processor.ProcessorVersion =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.Voltage.ProcessorVoltageCapability= 3_3V =3D 1; + ProcessorDataHob.SmbiosType4Processor.ExternalClock =3D TO_BE_FILLED_BY_= VENDOR; + ProcessorDataHob.SmbiosType4Processor.MaxSpeed =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.CurrentSpeed =3D TO_BE_FILLED_BY_V= ENDOR; + ProcessorDataHob.SmbiosType4Processor.Status =3D TO_BE_FILLED_BY_CODE; + ProcessorDataHob.SmbiosType4Processor.ProcessorUpgrade =3D TO_BE_FILLED_= BY_VENDOR; + ProcessorDataHob.SmbiosType4Processor.L1CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L2CacheHandle =3D TO_BE_FILLED_BY_= RISC_V_SMBIOS_DXE_DRIVER; + ProcessorDataHob.SmbiosType4Processor.L3CacheHandle =3D 0xffff; + ProcessorDataHob.SmbiosType4Processor.SerialNumber =3D TO_BE_FILLED_BY_C= ODE; + ProcessorDataHob.SmbiosType4Processor.AssetTag =3D TO_BE_FILLED_BY_VENDO= R; + ProcessorDataHob.SmbiosType4Processor.PartNumber =3D TO_BE_FILLED_BY_VEN= DOR; + ProcessorDataHob.SmbiosType4Processor.CoreCount =3D (UINT8)FixedPcdGet32= (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount =3D (UINT8)FixedP= cdGet32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.ThreadCount =3D (UINT8)FixedPcdGet= 32 (PcdNumberofU5Cores) + (UINT8)PcdGetBool (PcdE5MCSupported); + ProcessorDataHob.SmbiosType4Processor.ProcessorCharacteristics =3D (UINT= 16)(1 << 2); // 64-bit capable + ProcessorDataHob.SmbiosType4Processor.ProcessorFamily2 =3D ProcessorFami= lyRiscVRV64; + ProcessorDataHob.SmbiosType4Processor.CoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.EnabledCoreCount2 =3D 0; + ProcessorDataHob.SmbiosType4Processor.ThreadCount2 =3D 0; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType4GuidHobGuid); + ProcessorDataHobPtr =3D (RISC_V_PROCESSOR_TYPE4_DATA_HOB *)BuildGuidData= Hob (GuidPtr, (VOID *)&ProcessorDataHob, sizeof (RISC_V_PROCESSOR_TYPE4_DAT= A_HOB)); + if (ProcessorDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex = RISC_V_PROCESSOR_TYPE4_DATA_HOB.\n")); + ASSERT (FALSE); + } + + ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HOB= )); + SmbiosDataHob.Processor =3D ProcessorDataHobPtr; + SmbiosDataHob.L1InstCache =3D NULL; + SmbiosDataHob.L1DataCache =3D NULL; + SmbiosDataHob.L2Cache =3D L2CacheDataHobPtr; + SmbiosDataHob.L3Cache =3D NULL; + GuidPtr =3D (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid); + SmbiosDataHobPtr =3D (RISC_V_PROCESSOR_SMBIOS_DATA_HOB *)BuildGuidDataHo= b (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_DATA_HO= B)); + if (SmbiosDataHobPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex = RISC_V_PROCESSOR_SMBIOS_DATA_HOB.\n")); + ASSERT (FALSE); + } + *SmbiosHobPtr =3D SmbiosDataHobPtr; + DEBUG ((DEBUG_INFO, "%a: Exit\n", __FUNCTION__)); + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCor= eInfoHobLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/P= eiCoreInfoHobLib.inf new file mode 100644 index 00000000..915021f9 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHo= bLib.inf @@ -0,0 +1,58 @@ +## @file +# Library instance to create core information HOB +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconSiFiveU5MCCoreplexInfoLib + FILE_GUID =3D 4E397A71-5164-4E69-9884-70CBE2740AAB + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconSiFiveU5MCCoreplexInfoLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV +# + +[Sources] + CoreInfoHob.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + Platform/RiscV/SiFive/U500Pkg/U500.dec + Silicon/SiFive/SiFive.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + PrintLib + SiliconSiFiveE51CoreInfoLib + SiliconSiFiveU54CoreInfoLib + +[Guids] + gUefiRiscVPlatformU500PkgTokenSpaceGuid + +[Ppis] + +[FixedPcd] + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosGuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType4GuidHobGuid + gUefiRiscVPkgTokenSpaceGuid.PcdProcessorSmbiosType7GuidHobGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU54CoreGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveE51CoreGuid + gEfiSiFiveSiliconSpaceGuid.PcdSiFiveU5MCCoreplexGuid + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/Ri= scVPlatformTimerLib.S b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatform= TimerLib/RiscVPlatformTimerLib.S new file mode 100644 index 00000000..bb4aafb9 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlat= formTimerLib.S @@ -0,0 +1,48 @@ +//------------------------------------------------------------------------= ------ +// +// SiFive U500 Timer CSR functions. +// +// Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +//------------------------------------------------------------------------= ------ +#include +#include +#include + +.data + +.text +.align 3 + +.global ASM_PFX(RiscVReadMachineTimer) +.global ASM_PFX(RiscVSetMachineTimerCmp) +.global ASM_PFX(RiscVReadMachineTimerCmp) + +// +// Read machine timer CSR. +// @retval a0 : 64-bit machine timer. +// +ASM_PFX (RiscVReadMachineTimer): + li t1, CLINT_REG_MTIME + ld a0, (t1) + ret + +// +// Set machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVSetMachineTimerCmp): + li t1, CLINT_REG_MTIMECMP0 + sd a0, (t1) + ret + +// +// Read machine timer compare CSR. +// @param a0 : UINT64 +// +ASM_PFX (RiscVReadMachineTimerCmp): + li t1, CLINT_REG_MTIMECMP0 + ld a0, (t1) + ret diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/Ri= scVPlatformTimerLib.inf b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatfo= rmTimerLib/RiscVPlatformTimerLib.inf new file mode 100644 index 00000000..62771b68 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlat= formTimerLib.inf @@ -0,0 +1,39 @@ +## @file +# RISC-V CPU lib to override timer mechanism for U500 platform. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D RiscVPlatformTimerLib + FILE_GUID =3D AFA75BBD-DE9D-4E77-BD88-1EA401BE931D + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D RiscVPlatformTimerLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV32 RISCV64 +# + +[Sources] + +[Sources.RISCV32] + RiscVPlatformTimerLib.s + +[Sources.RISCV64] + RiscVPlatformTimerLib.s + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/SiFive/U500Pkg/U500.dec + + diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.= inf b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf new file mode 100644 index 00000000..85af1fbd --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf @@ -0,0 +1,31 @@ +## @file +# Library instance for SerialIo library class +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D U500SerialPortLib + MODULE_UNI_FILE =3D U500SerialPortLib.uni + FILE_GUID =3D FCC4FD2B-2FF6-4FFA-B363-7C1111E5DCE9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SerialPortLib + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + IoLib + RiscVOpensbiLib + +[Sources] + SerialPortLib.c diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLi= b.c b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c new file mode 100644 index 00000000..e51bf9c1 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c @@ -0,0 +1,241 @@ +/** @file + UART Serial Port library functions + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +#define REG32(p, i) ((p)[(i) >> 2]) + +//--------------------------------------------- +// UART Register Offsets +//--------------------------------------------- + +#define UART_REG_IP 0x14 + #define UART_IP_RXWM 0x02 + +//--------------------------------------------- +// UART Settings +//--------------------------------------------- + +#define U500_UART_ADDR 0x54000000 +#define U500_UART_BAUDRATE 115200 +#define U500_SYS_CLK 100000000 + +/** + Initialize the serial device hardware. + + If no initialization is required, then return RETURN_SUCCESS. + If the serial device was successfuly initialized, then return RETURN_SUC= CESS. + If the serial device could not be initialized, then return RETURN_DEVICE= _ERROR. + + @retval RETURN_SUCCESS The serial device was initialized. + @retval RETURN_DEVICE_ERROR The serail device could not be initialized. + +**/ +RETURN_STATUS +EFIAPI +SerialPortInitialize ( + VOID + ) +{ + if (sifive_uart_init (U500_UART_ADDR, U500_SYS_CLK/2, U500_UART_BAUDRATE= ) !=3D 0) { + return EFI_DEVICE_ERROR; + } + return RETURN_SUCCESS; +} + +/** + Write data from buffer to serial device. + + Writes NumberOfBytes data bytes from Buffer to the serial device. + The number of bytes actually written to the serial device is returned. + If the return value is less than NumberOfBytes, then the write operation= failed. + + If Buffer is NULL, then ASSERT(). + + If NumberOfBytes is zero, then return 0. + + @param Buffer Pointer to the data buffer to be written. + @param NumberOfBytes Number of bytes to written to the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes written to the serial devic= e. + If this value is less than NumberOfBytes, then = the write operation failed. + +**/ +UINTN +EFIAPI +SerialPortWrite ( + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN i; + + if (Buffer =3D=3D NULL) { + return 0; + } + + for(i=3D0; i < NumberOfBytes; i++) { + sifive_uart_putc (Buffer[i]); + } + + return i; +} + + +/** + Reads data from a serial device into a buffer. + + @param Buffer Pointer to the data buffer to store the data re= ad from the serial device. + @param NumberOfBytes Number of bytes to read from the serial device. + + @retval 0 NumberOfBytes is 0. + @retval >0 The number of bytes read from the serial device. + If this value is less than NumberOfBytes, then = the read operation failed. + +**/ +UINTN +EFIAPI +SerialPortRead ( + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN i; + + if (NULL =3D=3D Buffer) { + return 0; + } + + for(i=3D0; i < NumberOfBytes; i++) { + Buffer[i] =3D (UINT8)sifive_uart_getc (); + } + + return i; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls aserial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is= returned. + If there is no data waiting to be read from the serial device, then FALS= E is returned. + + @retval TRUE Data is waiting to be read from the serial devi= ce. + @retval FALSE There is no data waiting to be read from the se= rial device. + +**/ +BOOLEAN +EFIAPI +SerialPortPoll ( + VOID + ) +{ + static volatile UINT32 * const uart =3D (void *)(U500_UART_ADDR); + UINT32 ip; + + ip =3D REG32(uart, UART_REG_IP); + if(ip & UART_IP_RXWM) { + return TRUE; + } + else { + return FALSE; + } +} + +/** + Sets the control bits on a serial device. + + @param Control Sets the bits of Control that are settable. + + @retval RETURN_SUCCESS The new control bits were set on the seria= l device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetControl ( + IN UINT32 Control + ) +{ + + return RETURN_SUCCESS; +} + +/** + Retrieve the status of the control bits on a serial device. + + @param Control A pointer to return the current control si= gnals from the serial device. + + @retval RETURN_SUCCESS The control bits were read from the serial= device. + @retval RETURN_UNSUPPORTED The serial device does not support this op= eration. + @retval RETURN_DEVICE_ERROR The serial device is not functioning corre= ctly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortGetControl ( + OUT UINT32 *Control + ) +{ + *Control =3D 0; + return RETURN_SUCCESS; +} + +/** + Sets the baud rate, receive FIFO depth, transmit/receice time out, parit= y, + data bits, and stop bits on a serial device. + + @param BaudRate The requested baud rate. A BaudRate value of 0= will use the + device's default interface speed. + On output, the value actually set. + @param ReveiveFifoDepth The requested depth of the FIFO on the receive= side of the + serial interface. A ReceiveFifoDepth value of = 0 will use + the device's default FIFO depth. + On output, the value actually set. + @param Timeout The requested time out for a single character = in microseconds. + This timeout applies to both the transmit and = receive side of the + interface. A Timeout value of 0 will use the d= evice's default time + out value. + On output, the value actually set. + @param Parity The type of parity to use on this serial devic= e. A Parity value of + DefaultParity will use the device's default pa= rity value. + On output, the value actually set. + @param DataBits The number of data bits to use on the serial d= evice. A DataBits + vaule of 0 will use the device's default data = bit setting. + On output, the value actually set. + @param StopBits The number of stop bits to use on this serial = device. A StopBits + value of DefaultStopBits will use the device's= default number of + stop bits. + On output, the value actually set. + + @retval RETURN_SUCCESS The new attributes were set on the ser= ial device. + @retval RETURN_UNSUPPORTED The serial device does not support thi= s operation. + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an u= nsupported value. + @retval RETURN_DEVICE_ERROR The serial device is not functioning c= orrectly. + +**/ +RETURN_STATUS +EFIAPI +SerialPortSetAttributes ( + IN OUT UINT64 *BaudRate, + IN OUT UINT32 *ReceiveFifoDepth, + IN OUT UINT32 *Timeout, + IN OUT EFI_PARITY_TYPE *Parity, + IN OUT UINT8 *DataBits, + IN OUT EFI_STOP_BITS_TYPE *StopBits + ) +{ + return RETURN_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPo= rtLib.uni b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPor= tLib.uni new file mode 100644 index 00000000..49163bd8 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.u= ni @@ -0,0 +1,16 @@ +// /** @file +// Library instance for SerialIo library class +// +// Library instance for SerialIO library class. +// +// Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Library instance = for SerialIO library class" + +#string STR_MODULE_DESCRIPTION #language en-US "Library instance = for SerialIO library class." + --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47543): https://edk2.groups.io/g/devel/message/47543 Mute This Topic: https://groups.io/mt/34196358/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47544+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47544+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865111; cv=none; d=zoho.com; s=zohoarc; b=aoa4aJqaorp7ePygIKKjEaoDOhjtkHa8CaDtS4yXxFj9oH0NvXjwfuaeGWDhJc9C4+/Eqg7T7GTcgjvvcp2RwcfrMv+mYKP4yMaPoGh83hNCKGUuZ/BH7lQQz+dwOvh1gk/MkMh8zu4oxHkJEOGtnOVlT8lhr6PiPNvNm0GSuDE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865111; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=fuMK0ADpXYVNFfrFvOgccbKheVMIkna73l6SUgWEQ7g=; b=cbfIoNGZMYqZMi3nIaesnGFxpqLOm8AMyMOIzgGqkYlEGrJDMo+sKoQLJQewLE9iPvXO1eqdoeUR/NmHPoCtxXJr2Osf7p3F7G5fwMXmSzEgh/HGHAJ17rvHiITCilfFQEFKNnYbeS42ylObvqjVP1wMqaerqmvWnVR1b3zP90w= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47544+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156886511123283.00382983532029; Wed, 18 Sep 2019 20:51:51 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id er4XYY1788612x62Uel7COi2; Wed, 18 Sep 2019 20:51:50 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:50 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3peYC030791 for ; Thu, 19 Sep 2019 03:51:49 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vapnbap-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:48 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 2E45057 for ; Thu, 19 Sep 2019 03:51:48 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 61E6B45 for ; Thu, 19 Sep 2019 03:51:47 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 11/14] U500Pkg/RamFvbServiceruntimeDxe: FVB driver for EFI variable. Date: Thu, 19 Sep 2019 11:51:28 +0800 Message-Id: <20190919035131.4700-12-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: Ti4AVRb8iXTN8rIOpccMWJ3Cx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865110; bh=A/MHkkoXuLLwUkRBKV1BCeVqSSJ1yfEVfcMxkPF8dUg=; h=Date:From:Reply-To:Subject:To; b=WaFWmeourIs8Pbb4rXIsEwOvwnyIg987psKGUvA8H5cG1d/6hQO1If+ru6mxaw9/Soy WnJKCxcab4t+BkYXzCZ+69fgP6lL9UFq38ws9bJc7ayJxBq90Ge9l70ncLMpmZwFrVtZb k7Q9DuxcPk+eT64C8TMQUMJSMVJOqZchNMQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Firmware Volume Block driver instance for ram based EFI variable on U500 platform. Signed-off-by: Gilbert Chen --- .../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c | 127 +++ .../FvbServicesRuntimeDxe.inf | 81 ++ .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c | 1123 ++++++++++++++++= ++++ .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h | 187 ++++ .../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c | 151 +++ .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c | 144 +++ .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h | 85 ++ .../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c | 20 + 8 files changed, 1918 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/FvbInfo.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/FvbServicesRuntimeDxe.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/FwBlockService.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/FwBlockService.h create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/FwBlockServiceDxe.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/RamFlash.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/RamFlash.h create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/RamFlashDxe.c diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRunt= imeDxe/FvbInfo.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServic= esRuntimeDxe/FvbInfo.c new file mode 100644 index 00000000..1ade0d14 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= FvbInfo.c @@ -0,0 +1,127 @@ +/**@file + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + Module Name: + + FvbInfo.c + + Abstract: + + Defines data structure that is the volume header found.These data is i= ntent + to decouple FVB driver with FV header. + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The protocols, PPI and GUID defintions for this module +// +#include +// +// The Library classes this module consumes +// +#include +#include + +typedef struct { + UINT64 FvLength; + EFI_FIRMWARE_VOLUME_HEADER FvbInfo; + // + // EFI_FV_BLOCK_MAP_ENTRY ExtraBlockMap[n];//n=3D0 + // + EFI_FV_BLOCK_MAP_ENTRY End[1]; +} EFI_FVB_MEDIA_INFO; + +EFI_FVB_MEDIA_INFO mPlatformFvbMediaInfo[] =3D { + // + // Systen NvStorage FVB + // + { + FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize), + { + { + 0, + }, // ZeroVector[16] + EFI_SYSTEM_NV_DATA_FV_GUID, + FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize), + EFI_FVH_SIGNATURE, + EFI_FVB2_MEMORY_MAPPED | + EFI_FVB2_READ_ENABLED_CAP | + EFI_FVB2_READ_STATUS | + EFI_FVB2_WRITE_ENABLED_CAP | + EFI_FVB2_WRITE_STATUS | + EFI_FVB2_ERASE_POLARITY | + EFI_FVB2_ALIGNMENT_16, + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY= ), + 0, // CheckSum + 0, // ExtHeaderOffset + { + 0, + }, // Reserved[1] + 2, // Revision + { + { + (FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) / + FixedPcdGet32 (PcdVariableFdBlockSize), + FixedPcdGet32 (PcdVariableFdBlockSize), + } + } // BlockMap[1] + }, + { + { + 0, + 0 + } + } // End[1] + } +}; + +EFI_STATUS +GetFvbInfo ( + IN UINT64 FvLength, + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo + ) +{ + STATIC BOOLEAN Checksummed =3D FALSE; + UINTN Index; + + if (!Checksummed) { + for (Index =3D 0; + Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_IN= FO); + Index +=3D 1) { + UINT16 Checksum; + mPlatformFvbMediaInfo[Index].FvbInfo.Checksum =3D 0; + Checksum =3D CalculateCheckSum16 ( + (UINT16*) &mPlatformFvbMediaInfo[Index].FvbInfo, + mPlatformFvbMediaInfo[Index].FvbInfo.HeaderLength + ); + mPlatformFvbMediaInfo[Index].FvbInfo.Checksum =3D Checksum; + } + Checksummed =3D TRUE; + } + + for (Index =3D 0; + Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO= ); + Index +=3D 1) { + if (mPlatformFvbMediaInfo[Index].FvLength =3D=3D FvLength) { + *FvbInfo =3D &mPlatformFvbMediaInfo[Index].FvbInfo; + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRunt= imeDxe/FvbServicesRuntimeDxe.inf b/Platform/RiscV/SiFive/U500Pkg/Universal/= Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf new file mode 100644 index 00000000..1e8aa592 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= FvbServicesRuntimeDxe.inf @@ -0,0 +1,81 @@ +## @file +# Component description file for RAM Flash Fimware Volume Block DXE driver +# module. +# +# This DXE runtime driver implements and produces the Fimware Volue Block +# Protocol for a RAM flash device. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D FvbServicesRuntimeDxe + FILE_GUID =3D B04036D3-4C60-43D6-9850-0FCC090FF054 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D FvbInitialize + +# +# The following information is for reference only and not required by the = build +# tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + FvbInfo.c + FwBlockService.c + FwBlockServiceDxe.c + RamFlash.c + RamFlashDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + DevicePathLib + DxeServicesTableLib + MemoryAllocationLib + PcdLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeLib + +[Guids] + gEfiEventVirtualAddressChangeGuid # ALWAYS_CONSUMED + # gEfiEventVirtualAddressChangeGuid # Create Event: EVENT_GROUP_GUID + +[Protocols] + gEfiFirmwareVolumeBlockProtocolGuid # PROTOCOL SOMETIMES_PRODU= CED + gEfiDevicePathProtocolGuid # PROTOCOL SOMETIMES_PRODU= CED + +[FixedPcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageVariableBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwWorkingB= ase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdPlatformFlashNvStorageFtwSpareBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBaseAddress + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdSize + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFdBlockSize + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 + +[Depex] + TRUE diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRunt= imeDxe/FwBlockService.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFv= bServicesRuntimeDxe/FwBlockService.c new file mode 100644 index 00000000..8b89d2e0 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= FwBlockService.c @@ -0,0 +1,1123 @@ +/**@file + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + Module Name: + + FWBlockService.c + + Abstract: + + Revision History + +**/ + +// +// The protocols, PPI and GUID defintions for this module +// +#include +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include + +#include "FwBlockService.h" +#include "RamFlash.h" + +#define EFI_FVB2_STATUS \ + (EFI_FVB2_READ_STATUS | EFI_FVB2_WRITE_STATUS | EFI_FVB2_LOCK_ST= ATUS) + +ESAL_FWB_GLOBAL *mFvbModuleGlobal; + +FV_MEMMAP_DEVICE_PATH mFvMemmapDevicePathTemplate =3D { + { + { + HARDWARE_DEVICE_PATH, + HW_MEMMAP_DP, + { + (UINT8)(sizeof (MEMMAP_DEVICE_PATH)), + (UINT8)(sizeof (MEMMAP_DEVICE_PATH) >> 8) + } + }, + EfiMemoryMappedIO, + (EFI_PHYSICAL_ADDRESS) 0, + (EFI_PHYSICAL_ADDRESS) 0, + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +FV_PIWG_DEVICE_PATH mFvPIWGDevicePathTemplate =3D { + { + { + MEDIA_DEVICE_PATH, + MEDIA_PIWG_FW_VOL_DP, + { + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH)), + (UINT8)(sizeof (MEDIA_FW_VOL_DEVICE_PATH) >> 8) + } + }, + { 0 } + }, + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } +}; + +EFI_FW_VOL_BLOCK_DEVICE mFvbDeviceTemplate =3D { + FVB_DEVICE_SIGNATURE, + NULL, + 0, + { + FvbProtocolGetAttributes, + FvbProtocolSetAttributes, + FvbProtocolGetPhysicalAddress, + FvbProtocolGetBlockSize, + FvbProtocolRead, + FvbProtocolWrite, + FvbProtocolEraseBlocks, + NULL + } +}; + + +EFI_STATUS +GetFvbInstance ( + IN UINTN Instance, + IN ESAL_FWB_GLOBAL *Global, + OUT EFI_FW_VOL_INSTANCE **FwhInstance + ) +/*++ + + Routine Description: + Retrieves the physical address of a memory mapped FV + + Arguments: + Instance - The FV instance whose base address is going to= be + returned + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + FwhInstance - The EFI_FW_VOL_INSTANCE fimrware instance stru= cture + + Returns: + EFI_SUCCESS - Successfully returns + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhRecord; + + *FwhInstance =3D NULL; + if (Instance >=3D Global->NumFv) { + return EFI_INVALID_PARAMETER; + } + // + // Find the right instance of the FVB private data + // + FwhRecord =3D Global->FvInstance; + while (Instance > 0) { + FwhRecord =3D (EFI_FW_VOL_INSTANCE *) + ( + (UINTN) ((UINT8 *) FwhRecord) + FwhRecord->VolumeHeader.HeaderLeng= th + + (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEAD= ER)) + ); + Instance--; + } + + *FwhInstance =3D FwhRecord; + + return EFI_SUCCESS; +} + +EFI_STATUS +FvbGetPhysicalAddress ( + IN UINTN Instance, + OUT EFI_PHYSICAL_ADDRESS *Address, + IN ESAL_FWB_GLOBAL *Global + ) +/*++ + + Routine Description: + Retrieves the physical address of a memory mapped FV + + Arguments: + Instance - The FV instance whose base address is going to= be + returned + Address - Pointer to a caller allocated EFI_PHYSICAL_ADD= RESS + that on successful return, contains the base + address of the firmware volume. + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + + Returns: + EFI_SUCCESS - Successfully returns + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_STATUS Status; + + // + // Find the right instance of the FVB private data + // + Status =3D GetFvbInstance (Instance, Global, &FwhInstance); + ASSERT_EFI_ERROR (Status); + *Address =3D FwhInstance->FvBase; + + return EFI_SUCCESS; +} + +EFI_STATUS +FvbGetVolumeAttributes ( + IN UINTN Instance, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes, + IN ESAL_FWB_GLOBAL *Global + ) +/*++ + + Routine Description: + Retrieves attributes, insures positive polarity of attribute bits, ret= urns + resulting attributes in output parameter + + Arguments: + Instance - The FV instance whose attributes is going to be + returned + Attributes - Output buffer which contains attributes + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + + Returns: + EFI_SUCCESS - Successfully returns + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_STATUS Status; + + // + // Find the right instance of the FVB private data + // + Status =3D GetFvbInstance (Instance, Global, &FwhInstance); + ASSERT_EFI_ERROR (Status); + *Attributes =3D FwhInstance->VolumeHeader.Attributes; + + return EFI_SUCCESS; +} + +EFI_STATUS +FvbGetLbaAddress ( + IN UINTN Instance, + IN EFI_LBA Lba, + OUT UINTN *LbaAddress, + OUT UINTN *LbaLength, + OUT UINTN *NumOfBlocks, + IN ESAL_FWB_GLOBAL *Global + ) +/*++ + + Routine Description: + Retrieves the starting address of an LBA in an FV + + Arguments: + Instance - The FV instance which the Lba belongs to + Lba - The logical block address + LbaAddress - On output, contains the physical starting addr= ess + of the Lba + LbaLength - On output, contains the length of the block + NumOfBlocks - A pointer to a caller allocated UINTN in which= the + number of consecutive blocks starting with Lba= is + returned. All blocks in this range have a size= of + BlockSize + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + + Returns: + EFI_SUCCESS - Successfully returns + EFI_INVALID_PARAMETER - Instance not found + +--*/ +{ + UINT32 NumBlocks; + UINT32 BlockLength; + UINTN Offset; + EFI_LBA StartLba; + EFI_LBA NextLba; + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_FV_BLOCK_MAP_ENTRY *BlockMap; + EFI_STATUS Status; + + // + // Find the right instance of the FVB private data + // + Status =3D GetFvbInstance (Instance, Global, &FwhInstance); + ASSERT_EFI_ERROR (Status); + + StartLba =3D 0; + Offset =3D 0; + BlockMap =3D &(FwhInstance->VolumeHeader.BlockMap[0]); + + // + // Parse the blockmap of the FV to find which map entry the Lba belongs = to + // + while (TRUE) { + NumBlocks =3D BlockMap->NumBlocks; + BlockLength =3D BlockMap->Length; + + if (NumBlocks =3D=3D 0 || BlockLength =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + NextLba =3D StartLba + NumBlocks; + + // + // The map entry found + // + if (Lba >=3D StartLba && Lba < NextLba) { + Offset =3D Offset + (UINTN) MultU64x32 ((Lba - StartLba), BlockLengt= h); + if (LbaAddress !=3D NULL) { + *LbaAddress =3D FwhInstance->FvBase + Offset; + } + + if (LbaLength !=3D NULL) { + *LbaLength =3D BlockLength; + } + + if (NumOfBlocks !=3D NULL) { + *NumOfBlocks =3D (UINTN) (NextLba - Lba); + } + + return EFI_SUCCESS; + } + + StartLba =3D NextLba; + Offset =3D Offset + NumBlocks * BlockLength; + BlockMap++; + } +} + +EFI_STATUS +FvbSetVolumeAttributes ( + IN UINTN Instance, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes, + IN ESAL_FWB_GLOBAL *Global + ) +/*++ + + Routine Description: + Modifies the current settings of the firmware volume according to the + input parameter, and returns the new setting of the volume + + Arguments: + Instance - The FV instance whose attributes is going to be + modified + Attributes - On input, it is a pointer to EFI_FVB_ATTRIBUTE= S_2 + containing the desired firmware volume setting= s. + On successful return, it contains the new sett= ings + of the firmware volume + Global - Pointer to ESAL_FWB_GLOBAL that contains all + instance data + + Returns: + EFI_SUCCESS - Successfully returns + EFI_ACCESS_DENIED - The volume setting is locked and cannot be mod= ified + EFI_INVALID_PARAMETER - Instance not found, or The attributes requeste= d are + in conflict with the capabilities as declared = in + the firmware volume header + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_FVB_ATTRIBUTES_2 OldAttributes; + EFI_FVB_ATTRIBUTES_2 *AttribPtr; + UINT32 Capabilities; + UINT32 OldStatus; + UINT32 NewStatus; + EFI_STATUS Status; + EFI_FVB_ATTRIBUTES_2 UnchangedAttributes; + + // + // Find the right instance of the FVB private data + // + Status =3D GetFvbInstance (Instance, Global, &FwhInstance); + ASSERT_EFI_ERROR (Status); + + AttribPtr =3D + (EFI_FVB_ATTRIBUTES_2 *) &(FwhInstance->VolumeHeader.Attributes); + OldAttributes =3D *AttribPtr; + Capabilities =3D OldAttributes & (EFI_FVB2_READ_DISABLED_CAP | \ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP \ + ); + OldStatus =3D OldAttributes & EFI_FVB2_STATUS; + NewStatus =3D *Attributes & EFI_FVB2_STATUS; + + UnchangedAttributes =3D EFI_FVB2_READ_DISABLED_CAP | \ + EFI_FVB2_READ_ENABLED_CAP | \ + EFI_FVB2_WRITE_DISABLED_CAP | \ + EFI_FVB2_WRITE_ENABLED_CAP | \ + EFI_FVB2_LOCK_CAP | \ + EFI_FVB2_STICKY_WRITE | \ + EFI_FVB2_MEMORY_MAPPED | \ + EFI_FVB2_ERASE_POLARITY | \ + EFI_FVB2_READ_LOCK_CAP | \ + EFI_FVB2_WRITE_LOCK_CAP | \ + EFI_FVB2_ALIGNMENT; + + // + // Some attributes of FV is read only can *not* be set + // + if ((OldAttributes & UnchangedAttributes) ^ + (*Attributes & UnchangedAttributes)) { + return EFI_INVALID_PARAMETER; + } + // + // If firmware volume is locked, no status bit can be updated + // + if (OldAttributes & EFI_FVB2_LOCK_STATUS) { + if (OldStatus ^ NewStatus) { + return EFI_ACCESS_DENIED; + } + } + // + // Test read disable + // + if ((Capabilities & EFI_FVB2_READ_DISABLED_CAP) =3D=3D 0) { + if ((NewStatus & EFI_FVB2_READ_STATUS) =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test read enable + // + if ((Capabilities & EFI_FVB2_READ_ENABLED_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_READ_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test write disable + // + if ((Capabilities & EFI_FVB2_WRITE_DISABLED_CAP) =3D=3D 0) { + if ((NewStatus & EFI_FVB2_WRITE_STATUS) =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test write enable + // + if ((Capabilities & EFI_FVB2_WRITE_ENABLED_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_WRITE_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + // + // Test lock + // + if ((Capabilities & EFI_FVB2_LOCK_CAP) =3D=3D 0) { + if (NewStatus & EFI_FVB2_LOCK_STATUS) { + return EFI_INVALID_PARAMETER; + } + } + + *AttribPtr =3D (*AttribPtr) & (0xFFFFFFFF & (~EFI_FVB2_STATUS)); + *AttribPtr =3D (*AttribPtr) | NewStatus; + *Attributes =3D *AttribPtr; + + return EFI_SUCCESS; +} + +// +// FVB protocol APIs +// +EFI_STATUS +EFIAPI +FvbProtocolGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ) +/*++ + + Routine Description: + + Retrieves the physical address of the device. + + Arguments: + + This - Calling context + Address - Output buffer containing the address. + + Returns: + EFI_SUCCESS - Successfully returns + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice =3D FVB_DEVICE_FROM_THIS (This); + + return FvbGetPhysicalAddress (FvbDevice->Instance, Address, + mFvbModuleGlobal); +} + +EFI_STATUS +EFIAPI +FvbProtocolGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN CONST EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumOfBlocks + ) +/*++ + + Routine Description: + Retrieve the size of a logical block + + Arguments: + This - Calling context + Lba - Indicates which block to return the size for. + BlockSize - A pointer to a caller allocated UINTN in which + the size of the block is returned + NumOfBlocks - a pointer to a caller allocated UINTN in which= the + number of consecutive blocks starting with Lba= is + returned. All blocks in this range have a size= of + BlockSize + + Returns: + EFI_SUCCESS - The firmware volume was read successfully and + contents are in Buffer + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice =3D FVB_DEVICE_FROM_THIS (This); + + return FvbGetLbaAddress ( + FvbDevice->Instance, + Lba, + NULL, + BlockSize, + NumOfBlocks, + mFvbModuleGlobal + ); +} + +EFI_STATUS +EFIAPI +FvbProtocolGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +/*++ + + Routine Description: + Retrieves Volume attributes. No polarity translations are done. + + Arguments: + This - Calling context + Attributes - output buffer which contains attributes + + Returns: + EFI_SUCCESS - Successfully returns + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice =3D FVB_DEVICE_FROM_THIS (This); + + return FvbGetVolumeAttributes (FvbDevice->Instance, Attributes, + mFvbModuleGlobal); +} + +EFI_STATUS +EFIAPI +FvbProtocolSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ) +/*++ + + Routine Description: + Sets Volume attributes. No polarity translations are done. + + Arguments: + This - Calling context + Attributes - output buffer which contains attributes + + Returns: + EFI_SUCCESS - Successfully returns + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + + FvbDevice =3D FVB_DEVICE_FROM_THIS (This); + + return FvbSetVolumeAttributes (FvbDevice->Instance, Attributes, + mFvbModuleGlobal); +} + +EFI_STATUS +EFIAPI +FvbProtocolEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + ... + ) +/*++ + + Routine Description: + + The EraseBlock() function erases one or more blocks as denoted by the + variable argument list. The entire parameter list of blocks must be + verified prior to erasing any blocks. If a block is requested that do= es + not exist within the associated firmware volume (it has a larger index= than + the last block of the firmware volume), the EraseBlock() function must + return EFI_INVALID_PARAMETER without modifying the contents of the fir= mware + volume. + + Arguments: + This - Calling context + ... - Starting LBA followed by Number of Lba to eras= e. + a -1 to terminate the list. + + Returns: + EFI_SUCCESS - The erase request was successfully completed + EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled st= ate + EFI_DEVICE_ERROR - The block device is not functioning correctly = and + could not be written. Firmware device may have= been + partially erased + +--*/ +{ + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + EFI_FW_VOL_INSTANCE *FwhInstance; + UINTN NumOfBlocks; + VA_LIST args; + EFI_LBA StartingLba; + UINTN NumOfLba; + EFI_STATUS Status; + + FvbDevice =3D FVB_DEVICE_FROM_THIS (This); + + Status =3D GetFvbInstance (FvbDevice->Instance, mFvbModuleGlobal, + &FwhInstance); + ASSERT_EFI_ERROR (Status); + + NumOfBlocks =3D FwhInstance->NumOfBlocks; + + VA_START (args, This); + + do { + StartingLba =3D VA_ARG (args, EFI_LBA); + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + break; + } + + NumOfLba =3D VA_ARG (args, UINT32); + + // + // Check input parameters + // + if ((NumOfLba =3D=3D 0) || ((StartingLba + NumOfLba) > NumOfBlocks)) { + VA_END (args); + return EFI_INVALID_PARAMETER; + } + } while (1); + + VA_END (args); + + VA_START (args, This); + do { + StartingLba =3D VA_ARG (args, EFI_LBA); + if (StartingLba =3D=3D EFI_LBA_LIST_TERMINATOR) { + break; + } + + NumOfLba =3D VA_ARG (args, UINT32); + + while (NumOfLba > 0) { + Status =3D RamFlashEraseBlock (StartingLba); + if (EFI_ERROR (Status)) { + VA_END (args); + return Status; + } + + StartingLba++; + NumOfLba--; + } + + } while (1); + + VA_END (args); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +FvbProtocolWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +/*++ + + Routine Description: + + Writes data beginning at Lba:Offset from FV. The write terminates eith= er + when *NumBytes of data have been written, or when a block boundary is + reached. *NumBytes is updated to reflect the actual number of bytes + written. The write opertion does not include erase. This routine will + attempt to write only the specified bytes. If the writes do not stick, + it will return an error. + + Arguments: + This - Calling context + Lba - Block in which to begin write + Offset - Offset in the block at which to begin write + NumBytes - On input, indicates the requested write size. = On + output, indicates the actual number of bytes + written + Buffer - Buffer containing source data for the write. + + Returns: + EFI_SUCCESS - The firmware volume was written successfully + EFI_BAD_BUFFER_SIZE - Write attempted across a LBA boundary. On outp= ut, + NumBytes contains the total number of bytes + actually written + EFI_ACCESS_DENIED - The firmware volume is in the WriteDisabled st= ate + EFI_DEVICE_ERROR - The block device is not functioning correctly = and + could not be written + EFI_INVALID_PARAMETER - NumBytes or Buffer are NULL + +--*/ +{ + return RamFlashWrite ((EFI_LBA)Lba, (UINTN)Offset, NumBytes, + (UINT8 *)Buffer); +} + +EFI_STATUS +EFIAPI +FvbProtocolRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN CONST EFI_LBA Lba, + IN CONST UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ) +/*++ + + Routine Description: + + Reads data beginning at Lba:Offset from FV. The Read terminates either + when *NumBytes of data have been read, or when a block boundary is + reached. *NumBytes is updated to reflect the actual number of bytes + written. The write opertion does not include erase. This routine will + attempt to write only the specified bytes. If the writes do not stick, + it will return an error. + + Arguments: + This - Calling context + Lba - Block in which to begin Read + Offset - Offset in the block at which to begin Read + NumBytes - On input, indicates the requested write size. = On + output, indicates the actual number of bytes R= ead + Buffer - Buffer containing source data for the Read. + + Returns: + EFI_SUCCESS - The firmware volume was read successfully and + contents are in Buffer + EFI_BAD_BUFFER_SIZE - Read attempted across a LBA boundary. On outpu= t, + NumBytes contains the total number of bytes + returned in Buffer + EFI_ACCESS_DENIED - The firmware volume is in the ReadDisabled sta= te + EFI_DEVICE_ERROR - The block device is not functioning correctly = and + could not be read + EFI_INVALID_PARAMETER - NumBytes or Buffer are NULL + +--*/ +{ + return RamFlashRead ((EFI_LBA)Lba, (UINTN)Offset, NumBytes, + (UINT8 *)Buffer); +} + +EFI_STATUS +ValidateFvHeader ( + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader + ) +/*++ + + Routine Description: + Check the integrity of firmware volume header + + Arguments: + FwVolHeader - A pointer to a firmware volume header + + Returns: + EFI_SUCCESS - The firmware volume is consistent + EFI_NOT_FOUND - The firmware volume has corrupted. So it is no= t an + FV + +--*/ +{ + UINT16 Checksum; + + // + // Verify the header revision, header signature, length + // Length of FvBlock cannot be 2**64-1 + // HeaderLength cannot be an odd number + // + if ((FwVolHeader->Revision !=3D EFI_FVH_REVISION) || + (FwVolHeader->Signature !=3D EFI_FVH_SIGNATURE) || + (FwVolHeader->FvLength =3D=3D ((UINTN) -1)) || + ((FwVolHeader->HeaderLength & 0x01) !=3D 0) + ) { + return EFI_NOT_FOUND; + } + + // + // Verify the header checksum + // + + Checksum =3D CalculateSum16 ((UINT16 *) FwVolHeader, + FwVolHeader->HeaderLength); + if (Checksum !=3D 0) { + UINT16 Expected; + + Expected =3D + (UINT16) (((UINTN) FwVolHeader->Checksum + 0x10000 - Checksum) & 0xf= fff); + + DEBUG ((DEBUG_INFO, "FV@%p Checksum is 0x%x, expected 0x%x\n", + FwVolHeader, FwVolHeader->Checksum, Expected)); + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +STATIC +EFI_STATUS +MarkMemoryRangeForRuntimeAccess ( + EFI_PHYSICAL_ADDRESS BaseAddress, + UINTN Length + ) +{ + EFI_STATUS Status; + + // + // Mark flash region as runtime memory + // + Status =3D gDS->RemoveMemorySpace ( + BaseAddress, + Length + ); + + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeSystemMemory, + BaseAddress, + Length, + EFI_MEMORY_UC | EFI_MEMORY_RUNTIME + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->AllocatePages ( + AllocateAddress, + EfiRuntimeServicesData, + EFI_SIZE_TO_PAGES (Length), + &BaseAddress + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +STATIC +EFI_STATUS +InitializeVariableFvHeader ( + VOID + ) +{ + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME_HEADER *GoodFwVolHeader; + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + UINTN Length; + UINTN WriteLength; + UINTN BlockSize; + + FwVolHeader =3D + (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) + PcdGet32 (PcdPlatformFlashNvStorageVariableBase); + + Length =3D + (FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)); + + BlockSize =3D PcdGet32 (PcdVariableFdBlockSize); + + Status =3D ValidateFvHeader (FwVolHeader); + if (!EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "ValidateFvHeader() return ok\n")); + if (FwVolHeader->FvLength !=3D Length || + FwVolHeader->BlockMap[0].Length !=3D BlockSize) { + Status =3D EFI_VOLUME_CORRUPTED; + DEBUG ((DEBUG_INFO, "FwVolHeader->FvLength(%x) !=3D Length(%x) || FwV= olHeader->BlockMap[0].Length(%x) !=3D BlockSize(%x)\n", FwVolHeader->FvLeng= th, Length, FwVolHeader->BlockMap[0].Length, BlockSize)); + } + } + else { + DEBUG ((DEBUG_INFO, "ValidateFvHeader() return failed\n")); + } + if (EFI_ERROR (Status)) { + UINTN Offset; + UINTN Start; + + DEBUG ((DEBUG_INFO, + "Variable FV header is not valid. It will be reinitialized.\n")); + + // + // Get FvbInfo to provide in FwhInstance. + // + Status =3D GetFvbInfo (Length, &GoodFwVolHeader); + ASSERT (!EFI_ERROR (Status)); + + Start =3D (UINTN)(UINT8*) FwVolHeader - PcdGet32 (PcdVariableFdBaseAdd= ress); + ASSERT (Start % BlockSize =3D=3D 0 && Length % BlockSize =3D=3D 0); + ASSERT (GoodFwVolHeader->HeaderLength <=3D BlockSize); + + // + // Erase all the blocks + // + for (Offset =3D Start; Offset < Start + Length; Offset +=3D BlockSize)= { + Status =3D RamFlashEraseBlock (Offset / BlockSize); + ASSERT_EFI_ERROR (Status); + } + + // + // Write good FV header + // + WriteLength =3D GoodFwVolHeader->HeaderLength; + Status =3D RamFlashWrite ( + Start / BlockSize, + 0, + &WriteLength, + (UINT8 *) GoodFwVolHeader); + ASSERT_EFI_ERROR (Status); + ASSERT (WriteLength =3D=3D GoodFwVolHeader->HeaderLength); + } + + return Status; +} + +EFI_STATUS +EFIAPI +FvbInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +/*++ + + Routine Description: + This function does common initialization for FVB services + + Arguments: + + Returns: + +--*/ +{ + EFI_STATUS Status; + EFI_FW_VOL_INSTANCE *FwhInstance; + EFI_FIRMWARE_VOLUME_HEADER *FwVolHeader; + UINT32 BufferSize; + EFI_FV_BLOCK_MAP_ENTRY *PtrBlockMapEntry; + EFI_FW_VOL_BLOCK_DEVICE *FvbDevice; + UINT32 MaxLbaSize; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINTN Length; + UINTN NumOfBlocks; + + if (EFI_ERROR (RamFlashInitialize ())) { + // + // Return an error so image will be unloaded + // + DEBUG ((DEBUG_INFO, + "RAM flash was not detected. Writable FVB is not being installed.\n"= )); + return EFI_WRITE_PROTECTED; + } + + // + // Allocate runtime services data for global variable, which contains + // the private data of all firmware volume block instances + // + mFvbModuleGlobal =3D AllocateRuntimePool (sizeof (ESAL_FWB_GLOBAL)); + ASSERT (mFvbModuleGlobal !=3D NULL); + + BaseAddress =3D (UINTN) PcdGet32 (PcdVariableFdBaseAddress); + Length =3D PcdGet32 (PcdVariableFdSize); + DEBUG ((DEBUG_INFO, "FvbInitialize(): BaseAddress: 0x%lx Length:0x%x\n",= BaseAddress, Length)); + Status =3D InitializeVariableFvHeader (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, + "RAM Flash: Unable to initialize variable FV header\n")); + return EFI_WRITE_PROTECTED; + } + + FwVolHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) BaseAddress; + Status =3D ValidateFvHeader (FwVolHeader); + if (EFI_ERROR (Status)) { + // + // Get FvbInfo + // + DEBUG ((DEBUG_INFO, "FvbInitialize(): ValidateFvHeader() return error(= %r)\n", Status)); + + Status =3D GetFvbInfo (Length, &FwVolHeader); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_INFO, "FvbInitialize(): GetFvbInfo (Length, &FwVolHead= er) return error(%r)\n", Status)); + return EFI_WRITE_PROTECTED; + } + } + + BufferSize =3D (sizeof (EFI_FW_VOL_INSTANCE) + + FwVolHeader->HeaderLength - + sizeof (EFI_FIRMWARE_VOLUME_HEADER) + ); + mFvbModuleGlobal->FvInstance =3D AllocateRuntimePool (BufferSize); + ASSERT (mFvbModuleGlobal->FvInstance !=3D NULL); + + FwhInstance =3D mFvbModuleGlobal->FvInstance; + + mFvbModuleGlobal->NumFv =3D 0; + MaxLbaSize =3D 0; + + FwVolHeader =3D + (EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) + PcdGet32 (PcdPlatformFlashNvStorageVariableBase); + + FwhInstance->FvBase =3D (UINTN) BaseAddress; + + CopyMem ((UINTN *) &(FwhInstance->VolumeHeader), (UINTN *) FwVolHeader, + FwVolHeader->HeaderLength); + FwVolHeader =3D &(FwhInstance->VolumeHeader); + + NumOfBlocks =3D 0; + + for (PtrBlockMapEntry =3D FwVolHeader->BlockMap; + PtrBlockMapEntry->NumBlocks !=3D 0; + PtrBlockMapEntry++) { + // + // Get the maximum size of a block. + // + if (MaxLbaSize < PtrBlockMapEntry->Length) { + MaxLbaSize =3D PtrBlockMapEntry->Length; + } + + NumOfBlocks =3D NumOfBlocks + PtrBlockMapEntry->NumBlocks; + } + + // + // The total number of blocks in the FV. + // + FwhInstance->NumOfBlocks =3D NumOfBlocks; + + // + // Add a FVB Protocol Instance + // + FvbDevice =3D AllocateRuntimePool (sizeof (EFI_FW_VOL_BLOCK_DEVICE)); + ASSERT (FvbDevice !=3D NULL); + + CopyMem (FvbDevice, &mFvbDeviceTemplate, sizeof (EFI_FW_VOL_BLOCK_DEVICE= )); + + FvbDevice->Instance =3D mFvbModuleGlobal->NumFv; + mFvbModuleGlobal->NumFv++; + + // + // Set up the devicepath + // + if (FwVolHeader->ExtHeaderOffset =3D=3D 0) { + FV_MEMMAP_DEVICE_PATH *FvMemmapDevicePath; + + // + // FV does not contains extension header, then produce MEMMAP_DEVICE_P= ATH + // + FvMemmapDevicePath =3D AllocateCopyPool (sizeof (FV_MEMMAP_DEVICE_PATH= ), + &mFvMemmapDevicePathTemplate); + FvMemmapDevicePath->MemMapDevPath.StartingAddress =3D BaseAddress; + FvMemmapDevicePath->MemMapDevPath.EndingAddress =3D + BaseAddress + FwVolHeader->FvLength - 1; + FvbDevice->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)FvMemmapDevicePa= th; + } else { + FV_PIWG_DEVICE_PATH *FvPiwgDevicePath; + + FvPiwgDevicePath =3D AllocateCopyPool (sizeof (FV_PIWG_DEVICE_PATH), + &mFvPIWGDevicePathTemplate); + CopyGuid ( + &FvPiwgDevicePath->FvDevPath.FvName, + (GUID *)(UINTN)(BaseAddress + FwVolHeader->ExtHeaderOffset) + ); + FvbDevice->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)FvPiwgDevicePath; + } + + // + // Module type specific hook. + // + InstallProtocolInterfaces (FvbDevice); + + MarkMemoryRangeForRuntimeAccess (BaseAddress, Length); + + // + // Set several PCD values to point to flash + // + PcdSet64 ( + PcdFlashNvStorageVariableBase64, + (UINTN) PcdGet32 (PcdPlatformFlashNvStorageVariableBase) + ); + PcdSet32 ( + PcdFlashNvStorageFtwWorkingBase, + PcdGet32 (PcdPlatformFlashNvStorageFtwWorkingBase) + ); + PcdSet32 ( + PcdFlashNvStorageFtwSpareBase, + PcdGet32 (PcdPlatformFlashNvStorageFtwSpareBase) + ); + + FwhInstance =3D (EFI_FW_VOL_INSTANCE *) + ( + (UINTN) ((UINT8 *) FwhInstance) + FwVolHeader->HeaderLength + + (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER)) + ); + + // + // Module type specific hook. + // + InstallVirtualAddressChangeHandler (); + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRunt= imeDxe/FwBlockService.h b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFv= bServicesRuntimeDxe/FwBlockService.h new file mode 100644 index 00000000..a1aeb2c3 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= FwBlockService.h @@ -0,0 +1,187 @@ +/**@file + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + Module Name: + + FwBlockService.h + + Abstract: + + Firmware volume block driver for Intel Firmware Hub (FWH) device + +**/ + +#ifndef _FW_BLOCK_SERVICE_H_ +#define _FW_BLOCK_SERVICE_H_ + +typedef struct { + UINTN FvBase; + UINTN NumOfBlocks; + EFI_FIRMWARE_VOLUME_HEADER VolumeHeader; +} EFI_FW_VOL_INSTANCE; + +typedef struct { + UINT32 NumFv; + EFI_FW_VOL_INSTANCE *FvInstance; +} ESAL_FWB_GLOBAL; + +extern ESAL_FWB_GLOBAL *mFvbModuleGlobal; + +// +// Fvb Protocol instance data +// +#define FVB_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, \ + FwVolBlockInstance, FVB_DEVICE_SIGNATURE) + +#define FVB_EXTEND_DEVICE_FROM_THIS(a) CR (a, EFI_FW_VOL_BLOCK_DEVICE, \ + FvbExtension, FVB_DEVICE_SIGNATUR= E) + +#define FVB_DEVICE_SIGNATURE SIGNATURE_32 ('F', 'V', 'B', 'N') + +typedef struct { + MEDIA_FW_VOL_DEVICE_PATH FvDevPath; + EFI_DEVICE_PATH_PROTOCOL EndDevPath; +} FV_PIWG_DEVICE_PATH; + +typedef struct { + MEMMAP_DEVICE_PATH MemMapDevPath; + EFI_DEVICE_PATH_PROTOCOL EndDevPath; +} FV_MEMMAP_DEVICE_PATH; + +typedef struct { + UINTN Signature; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + UINTN Instance; + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL FwVolBlockInstance; +} EFI_FW_VOL_BLOCK_DEVICE; + +EFI_STATUS +GetFvbInfo ( + IN UINT64 FvLength, + OUT EFI_FIRMWARE_VOLUME_HEADER **FvbInfo + ); + +EFI_STATUS +FvbSetVolumeAttributes ( + IN UINTN Instance, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes, + IN ESAL_FWB_GLOBAL *Global + ); + +EFI_STATUS +FvbGetVolumeAttributes ( + IN UINTN Instance, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes, + IN ESAL_FWB_GLOBAL *Global + ); + +EFI_STATUS +FvbGetPhysicalAddress ( + IN UINTN Instance, + OUT EFI_PHYSICAL_ADDRESS *Address, + IN ESAL_FWB_GLOBAL *Global + ); + +EFI_STATUS +EFIAPI +FvbInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + + +VOID +EFIAPI +FvbClassAddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +EFI_STATUS +FvbGetLbaAddress ( + IN UINTN Instance, + IN EFI_LBA Lba, + OUT UINTN *LbaAddress, + OUT UINTN *LbaLength, + OUT UINTN *NumOfBlocks, + IN ESAL_FWB_GLOBAL *Global + ); + +// +// Protocol APIs +// +EFI_STATUS +EFIAPI +FvbProtocolGetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbProtocolSetAttributes ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes + ); + +EFI_STATUS +EFIAPI +FvbProtocolGetPhysicalAddress ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + OUT EFI_PHYSICAL_ADDRESS *Address + ); + +EFI_STATUS +EFIAPI +FvbProtocolGetBlockSize ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN CONST EFI_LBA Lba, + OUT UINTN *BlockSize, + OUT UINTN *NumOfBlocks + ); + +EFI_STATUS +EFIAPI +FvbProtocolRead ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN CONST EFI_LBA Lba, + IN CONST UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbProtocolWrite ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + IN EFI_LBA Lba, + IN UINTN Offset, + IN OUT UINTN *NumBytes, + IN UINT8 *Buffer + ); + +EFI_STATUS +EFIAPI +FvbProtocolEraseBlocks ( + IN CONST EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *This, + ... + ); + +// +// The following functions have different implementations dependent on the +// module type chosen for building this driver. +// +VOID +InstallProtocolInterfaces ( + IN EFI_FW_VOL_BLOCK_DEVICE *FvbDevice + ); + +VOID +InstallVirtualAddressChangeHandler ( + VOID + ); +#endif diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRunt= imeDxe/FwBlockServiceDxe.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/Ra= mFvbServicesRuntimeDxe/FwBlockServiceDxe.c new file mode 100644 index 00000000..46112365 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= FwBlockServiceDxe.c @@ -0,0 +1,151 @@ +/**@file + Functions related to the Firmware Volume Block service whose + implementation is specific to the runtime DXE driver build. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (C) 2015, Red Hat, Inc. + Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "FwBlockService.h" +#include "RamFlash.h" + +VOID +InstallProtocolInterfaces ( + IN EFI_FW_VOL_BLOCK_DEVICE *FvbDevice + ) +{ + EFI_STATUS Status; + EFI_HANDLE FwbHandle; + EFI_FIRMWARE_VOLUME_BLOCK_PROTOCOL *OldFwbInterface; + + // + // Find a handle with a matching device path that has supports FW Block + // protocol + // + Status =3D gBS->LocateDevicePath (&gEfiFirmwareVolumeBlockProtocolGuid, + &FvbDevice->DevicePath, &FwbHandle); + if (EFI_ERROR (Status)) { + // + // LocateDevicePath fails so install a new interface and device path + // + FwbHandle =3D NULL; + DEBUG ((DEBUG_INFO, "Installing RAM FVB\n")); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &FwbHandle, + &gEfiFirmwareVolumeBlockProtocolGuid, + &FvbDevice->FwVolBlockInstance, + &gEfiDevicePathProtocolGuid, + FvbDevice->DevicePath, + NULL + ); + ASSERT_EFI_ERROR (Status); + } else if (IsDevicePathEnd (FvbDevice->DevicePath)) { + // + // Device already exists, so reinstall the FVB protocol + // + Status =3D gBS->HandleProtocol ( + FwbHandle, + &gEfiFirmwareVolumeBlockProtocolGuid, + (VOID**)&OldFwbInterface + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Reinstalling FVB for Ram flash region\n")); + Status =3D gBS->ReinstallProtocolInterface ( + FwbHandle, + &gEfiFirmwareVolumeBlockProtocolGuid, + OldFwbInterface, + &FvbDevice->FwVolBlockInstance + ); + ASSERT_EFI_ERROR (Status); + } else { + // + // There was a FVB protocol on an End Device Path node + // + ASSERT (FALSE); + } +} + + +STATIC +VOID +EFIAPI +FvbVirtualAddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +/*++ + + Routine Description: + + Fixup internal data so that EFI and SAL can be call in virtual mode. + Call the passed in Child Notify event and convert the mFvbModuleGlobal + date items to there virtual address. + + Arguments: + + (Standard EFI notify event - EFI_EVENT_NOTIFY) + + Returns: + + None + +--*/ +{ + EFI_FW_VOL_INSTANCE *FwhInstance; + UINTN Index; + + FwhInstance =3D mFvbModuleGlobal->FvInstance; + EfiConvertPointer (0x0, (VOID **) &mFvbModuleGlobal->FvInstance); + + // + // Convert the base address of all the instances + // + Index =3D 0; + while (Index < mFvbModuleGlobal->NumFv) { + EfiConvertPointer (0x0, (VOID **) &FwhInstance->FvBase); + FwhInstance =3D (EFI_FW_VOL_INSTANCE *) + ( + (UINTN) ((UINT8 *) FwhInstance) + + FwhInstance->VolumeHeader.HeaderLength + + (sizeof (EFI_FW_VOL_INSTANCE) - sizeof (EFI_FIRMWARE_VOLUME_HEADER= )) + ); + Index++; + } + + EfiConvertPointer (0x0, (VOID **) &mFvbModuleGlobal); + RamFlashConvertPointers (); +} + + +VOID +InstallVirtualAddressChangeHandler ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT VirtualAddressChangeEvent; + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + FvbVirtualAddressChangeEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &VirtualAddressChangeEvent + ); + ASSERT_EFI_ERROR (Status); +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRunt= imeDxe/RamFlash.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/RamFlash.c new file mode 100644 index 00000000..6c3e613a --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= RamFlash.c @@ -0,0 +1,144 @@ +/** @file + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +#include "RamFlash.h" + +UINT8 *mFlashBase; + +STATIC UINTN mFdBlockSize =3D 0; +STATIC UINTN mFdBlockCount =3D 0; + +STATIC +volatile UINT8* +RamFlashPtr ( + IN EFI_LBA Lba, + IN UINTN Offset + ) +{ + return mFlashBase + ((UINTN)Lba * mFdBlockSize) + Offset; +} + +/** + Read from Ram Flash + + @param[in] Lba The starting logical block index to read from. + @param[in] Offset Offset into the block at which to begin reading. + @param[in] NumBytes On input, indicates the requested read size. On + output, indicates the actual number of bytes read + @param[in] Buffer Pointer to the buffer to read into. + +**/ +EFI_STATUS +RamFlashRead ( + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + UINT8 *Ptr; + + // + // Only write to the first 64k. We don't bother saving the FTW Spare + // block into the flash memory. + // + if (Lba >=3D mFdBlockCount) { + return EFI_INVALID_PARAMETER; + } + + // + // Get flash address + // + Ptr =3D (UINT8*) RamFlashPtr (Lba, Offset); + + CopyMem (Buffer, Ptr, *NumBytes); + + return EFI_SUCCESS; +} + + +/** + Write to Ram Flash + + @param[in] Lba The starting logical block index to write to. + @param[in] Offset Offset into the block at which to begin writing. + @param[in] NumBytes On input, indicates the requested write size. On + output, indicates the actual number of bytes written + @param[in] Buffer Pointer to the data to write. + +**/ +EFI_STATUS +RamFlashWrite ( + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN *NumBytes, + IN UINT8 *Buffer + ) +{ + volatile UINT8 *Ptr; + UINTN Loop; + + // + // Only write to the first 64k. We don't bother saving the FTW Spare + // block into the flash memory. + // + if (Lba >=3D mFdBlockCount) { + return EFI_INVALID_PARAMETER; + } + + // + // Program flash + // + Ptr =3D RamFlashPtr (Lba, Offset); + for (Loop =3D 0; Loop < *NumBytes; Loop++) { + *Ptr =3D Buffer[Loop]; + Ptr++; + } + + return EFI_SUCCESS; +} + + +/** + Erase a Ram Flash block + + @param Lba The logical block index to erase. + +**/ +EFI_STATUS +RamFlashEraseBlock ( + IN EFI_LBA Lba + ) +{ + + return EFI_SUCCESS; +} + + +/** + Initializes Ram flash memory support + + @retval EFI_WRITE_PROTECTED The Ram flash device is not present. + @retval EFI_SUCCESS The Ram flash device is supported. + +**/ +EFI_STATUS +RamFlashInitialize ( + VOID + ) +{ + mFlashBase =3D (UINT8*)(UINTN) PcdGet32 (PcdVariableFdBaseAddress); + mFdBlockSize =3D PcdGet32 (PcdVariableFdBlockSize); + ASSERT(PcdGet32 (PcdVariableFdSize) % mFdBlockSize =3D=3D 0); + mFdBlockCount =3D PcdGet32 (PcdVariableFdSize) / mFdBlockSize; + + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRunt= imeDxe/RamFlash.h b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServi= cesRuntimeDxe/RamFlash.h new file mode 100644 index 00000000..008c795e --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= RamFlash.h @@ -0,0 +1,85 @@ +/** @file + Ram flash device for EFI variable + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _RAM_FLASH_H_ +#define _RAM_FLASH_H_ + +#include + +extern UINT8 *mFlashBase; + +/** + Read from Ram Flash + + @param[in] Lba The starting logical block index to read from. + @param[in] Offset Offset into the block at which to begin reading. + @param[in] NumBytes On input, indicates the requested read size. On + output, indicates the actual number of bytes read + @param[in] Buffer Pointer to the buffer to read into. + +**/ +EFI_STATUS +RamFlashRead ( + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN *NumBytes, + IN UINT8 *Buffer + ); + + +/** + Write to Ram Flash + + @param[in] Lba The starting logical block index to write to. + @param[in] Offset Offset into the block at which to begin writing. + @param[in] NumBytes On input, indicates the requested write size. On + output, indicates the actual number of bytes written + @param[in] Buffer Pointer to the data to write. + +**/ +EFI_STATUS +RamFlashWrite ( + IN EFI_LBA Lba, + IN UINTN Offset, + IN UINTN *NumBytes, + IN UINT8 *Buffer + ); + + +/** + Erase a Ram Flash block + + @param Lba The logical block index to erase. + +**/ +EFI_STATUS +RamFlashEraseBlock ( + IN EFI_LBA Lba + ); + + +/** + Initializes Ram flash memory support + + @retval EFI_WRITE_PROTECTED The Ram flash device is not present. + @retval EFI_SUCCESS The Ram flash device is supported. + +**/ +EFI_STATUS +RamFlashInitialize ( + VOID + ); + + +VOID +RamFlashConvertPointers ( + VOID + ); + +#endif diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRunt= imeDxe/RamFlashDxe.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbSe= rvicesRuntimeDxe/RamFlashDxe.c new file mode 100644 index 00000000..a9d48637 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/= RamFlashDxe.c @@ -0,0 +1,20 @@ +/** @file + Ram flash device for EFI variable + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include "RamFlash.h" + +VOID +RamFlashConvertPointers ( + VOID + ) +{ + EfiConvertPointer (0x0, (VOID **) &mFlashBase); +} --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47544): https://edk2.groups.io/g/devel/message/47544 Mute This Topic: https://groups.io/mt/34196360/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47545+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47545+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865112; cv=none; d=zoho.com; s=zohoarc; b=l3gP4XsSNV5xr7I+QVkcTdxEEsSCsLwL7FVr2Z/4alfzBWwYzitrSYdKa2EkINKu1qVm8PACas5AjfsiYisVwWJCACBJlSTd/OyWl6iprxNQ0grGXc2kt7VV4GAJYYmSlb028MnamJeWYcqittbDz8NvS+rRznqYgpir8A/Lz94= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865112; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=yaTONbaf5MmDLBVr0iLQ55yT1BhOKynUt1LpkHMhcY0=; b=HNn6w7pglWy8utUv9OXi4Y873DIlywSsn01Yr4o4vJKt4RyvPWk4b9F1Q8vrzxxDuJV6Og2+O/umv6Bi2P8jSI0ctah0tzK/kCDGgABXlInpp5c6OyRODg+rcEr4l1hk12tKKXKt/gmuxnqVYYMF18cV8oIZf2khvd2W69pY6Mk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47545+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865112087781.7377690973109; Wed, 18 Sep 2019 20:51:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZDYNYY1788612xD2uFCIYSbZ; Wed, 18 Sep 2019 20:51:51 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:51 -0700 X-Received: from pps.filterd (m0150242.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pLVR030211 for ; Thu, 19 Sep 2019 03:51:50 GMT X-Received: from g4t3427.houston.hpe.com (g4t3427.houston.hpe.com [15.241.140.73]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vapnbau-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:50 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g4t3427.houston.hpe.com (Postfix) with ESMTP id 78F635E for ; Thu, 19 Sep 2019 03:51:49 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id AC3B145 for ; Thu, 19 Sep 2019 03:51:48 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 12/14] U500Pkg/TimerDxe: Platform Timer DXE driver Date: Thu, 19 Sep 2019 11:51:29 +0800 Message-Id: <20190919035131.4700-13-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: rk1IxzNfO3CzAXFGrmIsaKtVx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865111; bh=9RWTEH8Y3lP/2nTVOk93MmTjh0yCGOd5RePLcLYWpRc=; h=Date:From:Reply-To:Subject:To; b=PuTQABNjjV/bmPql5qdWX8j4rY5lMeE0N6w7dlWLlCStTzV618BnztBJcxKI43NjsWF zlp1NmpU5OSLxmiPbvVErcE1HLfJnZ88lAMmWAzMzbIvAEfBXPrrmXwNnw8Bq0vSWXD6P PTSrKimypjXJ/MFWwfI8hooWWDYWgpHEctY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Timer DXE driver for U500 platform based U500 platform implementation specifc timer registers. Signed-off-by: Gilbert Chen --- .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c | 311 +++++++++++++++++= ++++ .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h | 174 ++++++++++++ .../U500Pkg/Universal/Dxe/TimerDxe/Timer.uni | 14 + .../U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf | 48 ++++ .../U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni | 12 + 5 files changed, 559 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Ti= mer.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Ti= mer.h create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Ti= mer.uni create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Ti= merDxe.inf create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Ti= merExtra.uni diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c b= /Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c new file mode 100644 index 00000000..5cb42943 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c @@ -0,0 +1,311 @@ +/** @file + RISC-V Timer Architectural Protocol for U500 platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "Timer.h" +#include +#include +#include +#include +#include + +#define CLINT_REG_MTIME 0x0200BFF8 +#define CLINT_REG_MTIMECMP0 0x02004000 +#define CLINT_REG_MTIMECMP1 0x02004008 +#define CLINT_REG_MTIMECMP2 0x02004010 +#define CLINT_REG_MTIMECMP3 0x02004018 +#define CLINT_REG_MTIMECMP4 0x02004020 + +static volatile void * const p_mtime =3D (void *)CLINT_REG_MTIME; +#define MTIME (*p_mtime) +#define MTIMECMP(i) (p_mtimecmp[i]) + +// +// The handle onto which the Timer Architectural Protocol will be installed +// +EFI_HANDLE mTimerHandle =3D NULL; + +// +// The Timer Architectural Protocol that this driver produces +// +EFI_TIMER_ARCH_PROTOCOL mTimer =3D { + TimerDriverRegisterHandler, + TimerDriverSetTimerPeriod, + TimerDriverGetTimerPeriod, + TimerDriverGenerateSoftInterrupt +}; + +// +// Pointer to the CPU Architectural Protocol instance +// +EFI_CPU_ARCH_PROTOCOL *mCpu; + +// +// The notification function to call on every timer interrupt. +// A bug in the compiler prevents us from initializing this here. +// +EFI_TIMER_NOTIFY mTimerNotifyFunction; + +// +// The current period of the timer interrupt +// +volatile UINT64 mTimerPeriod =3D 0; + + +/** + 8254 Timer #0 Interrupt Handler. + + @param InterruptType The type of interrupt that occured + @param SystemContext A pointer to the system context when the interru= pt occured +**/ + +VOID +EFIAPI +TimerInterruptHandler ( + IN EFI_EXCEPTION_TYPE InterruptType, + IN EFI_SYSTEM_CONTEXT SystemContext + ) +{ + EFI_TPL OriginalTPL; + UINT64 RiscvTimer; + + csr_clear(CSR_SIE, MIP_STIP); // enable timer int + OriginalTPL =3D gBS->RaiseTPL (TPL_HIGH_LEVEL); + if (mTimerPeriod =3D=3D 0) { + gBS->RestoreTPL (OriginalTPL); + mCpu->DisableInterrupt(mCpu); + return; + } + if (mTimerNotifyFunction !=3D NULL) { + mTimerNotifyFunction (mTimerPeriod); + } + gBS->RestoreTPL (OriginalTPL); + + + RiscvTimer =3D readq_relaxed(p_mtime); + sbi_set_timer(RiscvTimer +=3D mTimerPeriod); + csr_set(CSR_SIE, MIP_STIP); // enable timer int + +} + +/** + + This function registers the handler NotifyFunction so it is called every= time + the timer interrupt fires. It also passes the amount of time since the = last + handler call to the NotifyFunction. If NotifyFunction is NULL, then the + handler is unregistered. If the handler is registered, then EFI_SUCCESS= is + returned. If the CPU does not support registering a timer interrupt han= dler, + then EFI_UNSUPPORTED is returned. If an attempt is made to register a h= andler + when a handler is already registered, then EFI_ALREADY_STARTED is return= ed. + If an attempt is made to unregister a handler when a handler is not regi= stered, + then EFI_INVALID_PARAMETER is returned. If an error occurs attempting to + register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ER= ROR + is returned. + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The function to call when a timer interrupt fire= s. This + function executes at TPL_HIGH_LEVEL. The DXE Co= re will + register a handler for the timer interrupt, so i= t can know + how much time has passed. This information is u= sed to + signal timer based events. NULL will unregister= the handler. + + @retval EFI_SUCCESS The timer handler was registered. + @retval EFI_UNSUPPORTED The platform does not support time= r interrupts. + @retval EFI_ALREADY_STARTED NotifyFunction is not NULL, and a = handler is already + registered. + @retval EFI_INVALID_PARAMETER NotifyFunction is NULL, and a hand= ler was not + previously registered. + @retval EFI_DEVICE_ERROR The timer handler could not be reg= istered. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +{ + DEBUG ((DEBUG_INFO, "TimerDriverRegisterHandler(0x%lx) called\n", Notify= Function)); + mTimerNotifyFunction =3D NotifyFunction; + return EFI_SUCCESS; +} + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +{ + UINT64 RiscvTimer; + + DEBUG ((DEBUG_INFO, "TimerDriverSetTimerPeriod(0x%lx)\n", TimerPeriod)); + + if (TimerPeriod =3D=3D 0) { + mTimerPeriod =3D 0; + mCpu->DisableInterrupt(mCpu); + csr_clear(CSR_SIE, MIP_STIP); // disable timer int + return EFI_SUCCESS; + } + + mTimerPeriod =3D TimerPeriod / 10; // convert unit from 100ns to 1us + + mCpu->EnableInterrupt(mCpu); + csr_set(CSR_SIE, MIP_STIP); // enable timer int + + RiscvTimer =3D readq_relaxed(p_mtime); + sbi_set_timer(RiscvTimer + mTimerPeriod); + return EFI_SUCCESS; +} + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +{ + *TimerPeriod =3D mTimerPeriod; + return EFI_SUCCESS; +} + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +{ + return EFI_SUCCESS; +} + +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Initialize the pointer to our notify function. + // + mTimerNotifyFunction =3D NULL; + + // + // Make sure the Timer Architectural Protocol is not already installed i= n the system + // + ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiTimerArchProtocolGuid); + + // + // Find the CPU architectural protocol. + // + Status =3D gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **= ) &mCpu); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be disabled + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, 0); + ASSERT_EFI_ERROR (Status); + + // + // Install interrupt handler for RISC-V Timer. + // + Status =3D mCpu->RegisterInterruptHandler (mCpu, EXCEPT_RISCV_TIMER_INT,= TimerInterruptHandler); + ASSERT_EFI_ERROR (Status); + + // + // Force the timer to be enabled at its default period + // + Status =3D TimerDriverSetTimerPeriod (&mTimer, DEFAULT_TIMER_TICK_DURATI= ON); + ASSERT_EFI_ERROR (Status); + + // + // Install the Timer Architectural Protocol onto a new handle + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mTimerHandle, + &gEfiTimerArchProtocolGuid, &mTimer, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h b= /Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h new file mode 100644 index 00000000..3bfc415d --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h @@ -0,0 +1,174 @@ +/** @file + RISC-V Timer Architectural Protocol definitions for U500 platform, + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _TIMER_H_ +#define _TIMER_H_ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +// +// RISC-V use 100us timer. +// The default timer tick duration is set to 10 ms =3D 10 * 1000 * 10 100 = ns units +// +#define DEFAULT_TIMER_TICK_DURATION 100000 + +extern VOID RiscvSetTimerPeriod (UINT32 TimerPeriod); + +// +// Function Prototypes +// +/** + Initialize the Timer Architectural Protocol driver + + @param ImageHandle ImageHandle of the loaded driver + @param SystemTable Pointer to the System Table + + @retval EFI_SUCCESS Timer Architectural Protocol created + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occured attempting to init= ialize the driver. + +**/ +EFI_STATUS +EFIAPI +TimerDriverInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param NotifyFunction The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverRegisterHandler ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN EFI_TIMER_NOTIFY NotifyFunction + ) +; + +/** + + This function adjusts the period of timer interrupts to the value specif= ied + by TimerPeriod. If the timer period is updated, then the selected timer + period is stored in EFI_TIMER.TimerPeriod, and EFI_SUCCESS is returned. = If + the timer hardware is not programmable, then EFI_UNSUPPORTED is returned. + If an error occurs while attempting to update the timer period, then the + timer hardware will be put back in its state prior to this call, and + EFI_DEVICE_ERROR is returned. If TimerPeriod is 0, then the timer inter= rupt + is disabled. This is not the same as disabling the CPU's interrupts. + Instead, it must either turn off the timer hardware, or it must adjust t= he + interrupt controller so that a CPU interrupt is not generated when the t= imer + interrupt fires. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod The rate to program the timer interrupt in 100 nS= units. If + the timer hardware is not programmable, then EFI_= UNSUPPORTED is + returned. If the timer is programmable, then the= timer period + will be rounded up to the nearest timer period th= at is supported + by the timer hardware. If TimerPeriod is set to = 0, then the + timer interrupts will be disabled. + + @retval EFI_SUCCESS The timer period was changed. + @retval EFI_UNSUPPORTED The platform cannot change the period o= f the timer interrupt. + @retval EFI_DEVICE_ERROR The timer period could not be changed d= ue to a device error. + +**/ +EFI_STATUS +EFIAPI +TimerDriverSetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + IN UINT64 TimerPeriod + ) +; + +/** + + This function retrieves the period of timer interrupts in 100 ns units, + returns that value in TimerPeriod, and returns EFI_SUCCESS. If TimerPer= iod + is NULL, then EFI_INVALID_PARAMETER is returned. If a TimerPeriod of 0 = is + returned, then the timer is currently disabled. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + @param TimerPeriod A pointer to the timer period to retrieve in 100 = ns units. If + 0 is returned, then the timer is currently disabl= ed. + + @retval EFI_SUCCESS The timer period was returned in TimerPer= iod. + @retval EFI_INVALID_PARAMETER TimerPeriod is NULL. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGetTimerPeriod ( + IN EFI_TIMER_ARCH_PROTOCOL *This, + OUT UINT64 *TimerPeriod + ) +; + +/** + + This function generates a soft timer interrupt. If the platform does not= support soft + timer interrupts, then EFI_UNSUPPORTED is returned. Otherwise, EFI_SUCCE= SS is returned. + If a handler has been registered through the EFI_TIMER_ARCH_PROTOCOL.Reg= isterHandler() + service, then a soft timer interrupt will be generated. If the timer int= errupt is + enabled when this service is called, then the registered handler will be= invoked. The + registered handler should not be able to distinguish a hardware-generate= d timer + interrupt from a software-generated timer interrupt. + + + @param This The EFI_TIMER_ARCH_PROTOCOL instance. + + @retval EFI_SUCCESS The soft timer interrupt was generated. + @retval EFI_UNSUPPORTEDT The platform does not support the generation o= f soft timer interrupts. + +**/ +EFI_STATUS +EFIAPI +TimerDriverGenerateSoftInterrupt ( + IN EFI_TIMER_ARCH_PROTOCOL *This + ) +; + +#endif diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni= b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni new file mode 100644 index 00000000..38302244 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni @@ -0,0 +1,14 @@ +// /** @file +// +// RISC-V Timer Arch protocol strings. +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "RISC-V timer driv= er that provides Timer Arch protocol" + +#string STR_MODULE_DESCRIPTION #language en-US "RISC-V timer driv= er that provides Timer Arch protocol." diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.= inf b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf new file mode 100644 index 00000000..f8af6889 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf @@ -0,0 +1,48 @@ +## @file +# RISC-V Timer Arch protocol module for U500 platform +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D Timer + MODULE_UNI_FILE =3D Timer.uni + FILE_GUID =3D 3F75D495-23FF-46B6-9D19-0DECC8A4EA91 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D TimerDriverInitialize + +[Packages] + MdePkg/MdePkg.dec + RiscVPkg/RiscVPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + BaseLib + DebugLib + UefiDriverEntryPoint + IoLib + RiscVCpuLib + RiscVOpensbiLib + +[Sources] + Timer.h + Timer.c + +[Protocols] + gEfiCpuArchProtocolGuid ## CONSUMES + gEfiTimerArchProtocolGuid ## PRODUCES + +[Pcd] + gUefiRiscVPkgTokenSpaceGuid.PcdRiscVMachineTimerFrequencyInHerz + +[Depex] + gEfiCpuArchProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + TimerExtra.uni diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtr= a.uni b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni new file mode 100644 index 00000000..cf25ff14 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni @@ -0,0 +1,12 @@ +// /** @file +// Timer Localized Strings and Content +// +// Copyright (c) 2016, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"RISC-V Timer DXE Driver" --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47545): https://edk2.groups.io/g/devel/message/47545 Mute This Topic: https://groups.io/mt/34196361/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47546+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47546+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865113; cv=none; d=zoho.com; s=zohoarc; b=Atc+04/Bnu9A7EPgNSZ2dJiKu+1L3VWk+Y0v3JU1/sDYKj6Mw9kOc5hg11qgVFx6uDhm56y8Vl3DU1T43LF8/WAfm3ioDsSJytSoILp3HPdXeIK+LeZXcpMfIkDrLJAPMRoSV+EiuFM/qwNPUCYiBbUqIlmgrjOHl7+2jn+rrls= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865113; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=u89aYhmKBpeJ5Sag7Pjl2CDXxpAsbbE2xGU6XA4iTIs=; b=Yp3bCSPbET74c0dkdeqDkQ/MDebB7TdSKmiGkbmarN6C5ip3QBdN3iiR3g3e8j9QH+t32ER4m/ZvWznt27pShE2VfzVGwrPBLwvkKYRZ5yYAKvnpmAGpZYhz9ng8Dr6IHEA3+yRTIf1sbFbrZM2xtXGF+P5zc5BpCFkh2+zx2oM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47546+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865113374348.14313282151693; Wed, 18 Sep 2019 20:51:53 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jZvCYY1788612x3ZVcAOKEYm; Wed, 18 Sep 2019 20:51:53 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:52 -0700 X-Received: from pps.filterd (m0148663.ppops.net [127.0.0.1]) by mx0a-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pKBl006025 for ; Thu, 19 Sep 2019 03:51:51 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0a-002e3701.pphosted.com with ESMTP id 2v3vanwqga-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:51 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id C522151 for ; Thu, 19 Sep 2019 03:51:50 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 020DD45 for ; Thu, 19 Sep 2019 03:51:49 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 13/14] U500Pkg/PlatformPei: Platform initialization PEIM Date: Thu, 19 Sep 2019 11:51:30 +0800 Message-Id: <20190919035131.4700-14-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: UmuPKsl93I34km15VFJrRutcx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865113; bh=M0JtNGz/zVlQGqdVdUbeQvQ3q1mH7V1LC469UKGsHvI=; h=Date:From:Reply-To:Subject:To; b=g8Y9R5HVjoVseqMWxssV7rdCqjnzqNuMHHhdz5le3x/tmY1MM053ROepd14e11nJEmt CcDcYRjtgfO18BffwCv/zQSX2Mcf+BVZbJUg6Xyhu4K3occPQqsq+WzY2ZkMOKaXnHDXG GmNNPozPUDPtsPaiF/rDE3F338TEtCYvjIE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is the platform-implementation specific library which is executed in early PEI phase for platform initialization. Signed-off-by: Gilbert Chen --- .../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c | 49 ++++ .../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c | 74 +++++ .../U500Pkg/Universal/Pei/PlatformPei/Platform.c | 313 +++++++++++++++++= ++++ .../U500Pkg/Universal/Pei/PlatformPei/Platform.h | 92 ++++++ .../Universal/Pei/PlatformPei/PlatformPei.inf | 75 +++++ 5 files changed, 603 insertions(+) create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /Fv.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /MemDetect.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /Platform.c create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /Platform.h create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei= /PlatformPei.inf diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c b= /Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c new file mode 100644 index 00000000..74e4d433 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c @@ -0,0 +1,49 @@ +/** @file + Build FV related hobs for platform. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PiPei.h" +#include "Platform.h" +#include +#include +#include +#include + +/** + Publish PEI & DXE (Decompressed) Memory based FVs to let PEI + and DXE know about them. + + @retval EFI_SUCCESS Platform PEI FVs were initialized successfully. + +**/ +EFI_STATUS +PeiFvInitialization ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "Platform PEI Firmware Volume Initialization\n")); + // + // Let DXE know about the DXE FV + // + BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)); + DEBUG ((DEBUG_INFO, "Platform builds DXE FV at %x, size %x.\n", PcdGet32= (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize))); + + // + // Let PEI know about the DXE FV so it can find the DXE Core + // + PeiServicesInstallFvInfoPpi ( + NULL, + (VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase), + PcdGet32 (PcdRiscVDxeFvSize), + NULL, + NULL + ); + + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDet= ect.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c new file mode 100644 index 00000000..dc99f2e0 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c @@ -0,0 +1,74 @@ +/**@file + Memory Detection for Virtual Machines. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include + +#include "Platform.h" + + +/** + Publish PEI core memory + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +PublishPeiMemory ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS MemoryBase; + UINT64 MemorySize; + + MemoryBase =3D 0x80000000UL + 0x1000000UL; + MemorySize =3D 0x40000000UL - 0x1000000UL; //1GB - 16MB + + DEBUG((DEBUG_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__, = MemoryBase, MemorySize)); + + // + // Publish this memory to the PEI Core + // + Status =3D PublishSystemMemory(MemoryBase, MemorySize); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Publish system RAM and reserve memory regions + +**/ +VOID +InitializeRamRegions ( + VOID + ) +{ + AddMemoryRangeHob(0x81000000UL, 0x81000000UL + 0x3F000000UL); + +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platfo= rm.c b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c new file mode 100644 index 00000000..45356399 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c @@ -0,0 +1,313 @@ +/**@file + Platform PEI driver + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "Platform.h" + +EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] =3D { + { EfiACPIMemoryNVS, 0x004 }, + { EfiACPIReclaimMemory, 0x008 }, + { EfiReservedMemoryType, 0x004 }, + { EfiRuntimeServicesData, 0x024 }, + { EfiRuntimeServicesCode, 0x030 }, + { EfiBootServicesCode, 0x180 }, + { EfiBootServicesData, 0xF00 }, + { EfiMaxMemoryType, 0x000 } +}; + + +EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEfiPeiMasterBootModePpiGuid, + NULL + } +}; + +EFI_BOOT_MODE mBootMode =3D BOOT_WITH_FULL_CONFIGURATION; + +BOOLEAN mS3Supported =3D FALSE; + + +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + + +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + + +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + + +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE, + MemoryBase, + MemorySize + ); +} + +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddUntestedMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); +} + +VOID +AddPciResource ( + VOID + ) +{ + // + // Platform-specific + // +} + +VOID +MemMapInitialization ( + VOID + ) +{ + // + // Create Memory Type Information HOB + // + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + mDefaultMemoryTypeInformation, + sizeof(mDefaultMemoryTypeInformation) + ); + + // + // Add PCI IO Port space available for PCI resource allocations. + // + AddPciResource (); +} + +VOID +MiscInitialization ( + VOID + ) +{ + // + // Build the CPU HOB with guest RAM size dependent address width and 16-= bits + // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed dur= ing + // S3 resume as well, so we build it unconditionally.) + // + BuildCpuHob (32, 32); +} + +/** + Check if system retunrs from S3. + + @return BOOLEAN TRUE, system returned from S3 + FALSE, system is not returned from S3 + +**/ +BOOLEAN +CheckResumeFromS3 ( + VOID + ) +{ + // + //Platform implementation-specific + // + return FALSE; +} + + +VOID +BootModeInitialization ( + VOID + ) +{ + EFI_STATUS Status; + + if (CheckResumeFromS3 () =3D=3D TRUE) { + DEBUG ((DEBUG_INFO, "This is wake from S3\n")); + } else { + DEBUG ((DEBUG_INFO, "This is normal boot\n")); + } + Status =3D PeiServicesSetBootMode (mBootMode); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesInstallPpi (mPpiBootMode); + ASSERT_EFI_ERROR (Status); +} + +/** + Build processor information for U54 Coreplex processor. + + @return EFI_SUCCESS Status. + +**/ +EFI_STATUS +BuildCoreInformationHob ( + VOID +) +{ + EFI_STATUS Status; + RISC_V_PROCESSOR_SMBIOS_DATA_HOB *SmbiosHobPtr; + + Status =3D CreateU5MCCoreplexProcessorSpecificDataHob (0); + if (EFI_ERROR (Status)) { + ASSERT(FALSE); + } + Status =3D CreateU5MCProcessorSmbiosDataHob(0, &SmbiosHobPtr); + if (EFI_ERROR (Status)) { + ASSERT(FALSE); + } + + DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", = SmbiosHobPtr)); + + return EFI_SUCCESS; +} + +/** + Perform Platform PEI initialization. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS The PEIM initialized successfully. + +**/ +EFI_STATUS +EFIAPI +InitializePlatform ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); + + BootModeInitialization (); + DEBUG ((DEBUG_INFO, "Platform BOOT mode initiated.\n")); + PublishPeiMemory (); + DEBUG ((DEBUG_INFO, "PEI memory published.\n")); + InitializeRamRegions (); + DEBUG ((DEBUG_INFO, "Platform RAM regions initiated.\n")); + + if (mBootMode !=3D BOOT_ON_S3_RESUME) { + PeiFvInitialization (); + MemMapInitialization (); + } + + MiscInitialization (); + Status =3D BuildCoreInformationHob (); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to build processor informstion HOB.\n")); + ASSERT(FALSE); + } + return EFI_SUCCESS; +} diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platfo= rm.h b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h new file mode 100644 index 00000000..23600203 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h @@ -0,0 +1,92 @@ +/** @file + Platform PEI module include file. + + Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PLATFORM_PEI_H_INCLUDED_ +#define _PLATFORM_PEI_H_INCLUDED_ + +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddIoMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddUntestedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddReservedMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ); + +VOID +AddUntestedMemoryRangeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +AddressWidthInitialization ( + VOID + ); + +EFI_STATUS +PublishPeiMemory ( + VOID + ); + +UINT32 +GetSystemMemorySizeBelow4gb ( + VOID + ); + +VOID +InitializeRamRegions ( + VOID + ); + +EFI_STATUS +PeiFvInitialization ( + VOID + ); + +EFI_STATUS +InitializeXen ( + VOID + ); + +extern EFI_BOOT_MODE mBootMode; + +extern BOOLEAN mS3Supported; + +extern UINT8 mPhysMemAddressWidth; + +#endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platfo= rmPei.inf b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platfor= mPei.inf new file mode 100644 index 00000000..420b0702 --- /dev/null +++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.i= nf @@ -0,0 +1,75 @@ +## @file +# Platform PEI driver +# +# This module provides platform specific function to detect boot mode. +# +# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All righ= ts reserved.
+# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformPei + FILE_GUID =3D 222c386d-5abc-4fb4-b124-fbb82488acf4 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializePlatform + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC RISCV64 +# + +[Sources] + Fv.c + MemDetect.c + Platform.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + RiscVPkg/RiscVPkg.dec + Platform/RiscV/RiscVPlatformPkg.dec + Silicon/SiFive/SiFive.dec + Platform/RiscV/SiFive/U500Pkg/U500.dec + +[Guids] + gEfiMemoryTypeInformationGuid + gUefiRiscVPlatformU500PkgTokenSpaceGuid + +[LibraryClasses] + DebugLib + HobLib + IoLib + PciLib + PeiResourcePublicationLib + PeiServicesLib + PeiServicesTablePointerLib + PeimEntryPoint + PcdLib + SiliconSiFiveU5MCCoreplexInfoLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress + gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved + gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize + + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores + gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported + + +[Ppis] + gEfiPeiMasterBootModePpiGuid + +[Depex] + TRUE --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47546): https://edk2.groups.io/g/devel/message/47546 Mute This Topic: https://groups.io/mt/34196362/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 17:01:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47547+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47547+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=hpe.com ARC-Seal: i=1; a=rsa-sha256; t=1568865114; cv=none; d=zoho.com; s=zohoarc; b=er/P84rUdcrALg87umx2CtlnADQmOab/z9NRIhHtgJCPiQ71b/IonAzqjOZv/CPW66FOJIQMi6Eu48cqdQvAvL5gtopMZ+tvOyob7vrDpRtRqW0ne51+oGzq/qmEep1L9bhNnyIGbxvgkTMVLZ2y1TyNDjUD+NmWlOxpbGoZ/Gc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568865114; h=Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=/JTJzWLCEdOOJdzzzMmDe1hBVTTsD6c/0Hbc2KCbuGM=; b=DPb7mAJCNjZFqCc3z51TuyfAOjS5ghX6D2RdglVucoomiApWJYsk+Mk+aW7A5cfWwpW1rHNlo7l/0ZBIbTaF87Wsip2nEEBY/Mp39oLlVu7gJF2LLcrVTe6NB6tWyeqerRaYp7mFuEyJ4ANqR629Q/e0Sh07h3KiQWKH+G8vFkQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47547+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568865114942367.1132339475298; Wed, 18 Sep 2019 20:51:54 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id DiQPYY1788612xuiUIbIOHO8; Wed, 18 Sep 2019 20:51:54 -0700 X-Received: from mx0a-002e3701.pphosted.com (mx0a-002e3701.pphosted.com [148.163.147.86]) by groups.io with SMTP; Wed, 18 Sep 2019 20:51:53 -0700 X-Received: from pps.filterd (m0134420.ppops.net [127.0.0.1]) by mx0b-002e3701.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x8J3pmef013474 for ; Thu, 19 Sep 2019 03:51:52 GMT X-Received: from g9t5009.houston.hpe.com (g9t5009.houston.hpe.com [15.241.48.73]) by mx0b-002e3701.pphosted.com with ESMTP id 2v3vapdauj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 19 Sep 2019 03:51:52 +0000 X-Received: from g4t3433.houston.hpecorp.net (g4t3433.houston.hpecorp.net [16.208.49.245]) by g9t5009.houston.hpe.com (Postfix) with ESMTP id 1ADD251 for ; Thu, 19 Sep 2019 03:51:52 +0000 (UTC) X-Received: from ARBDN0VRAE.asiapacific.hpqcorp.net (arbdn0vrae.asiapacific.hpqcorp.net [10.43.41.0]) by g4t3433.houston.hpecorp.net (Postfix) with ESMTP id 4C91745 for ; Thu, 19 Sep 2019 03:51:51 +0000 (UTC) From: "Gilbert Chen" To: devel@edk2.groups.io Subject: [edk2-devel] [plaforms/devel-riscv-v2 PATCHv2 14/14] Platforms: Readme file updates Date: Thu, 19 Sep 2019 11:51:31 +0800 Message-Id: <20190919035131.4700-15-gilbert.chen@hpe.com> In-Reply-To: <20190919035131.4700-1-gilbert.chen@hpe.com> References: <20190919035131.4700-1-gilbert.chen@hpe.com> X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-HPE-SCL: -1 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,gilbert.chen@hpe.com X-Gm-Message-State: ciEIkwioedp4bJfVYOl5iojKx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568865114; bh=uvbD/JxnvH4c4iStNM7TEAeeml1UxyOCd+2hDAreD90=; h=Date:From:Reply-To:Subject:To; b=F35aTQOlIFB5ImESLKasSC2MNRotdSULu5mk2/wBakT0BSoHAas1Sk1/fnScsSHXkLu uq/oHcYq+NLUJA/Gef/UpXpBJB9ov0NyHS2lkJ322qfFvssy0UZDJQTXcD4BSV8ru0xFs OvzWu+COT+KO+D3tR1/Ons1xdUzPa+U/e0A= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update Readme.md and Maintainers.txt for RISV-V platforms. Signed-off-by: Gilbert Chen --- Maintainers.txt | 9 +++++++++ Readme.md | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 876ae561..c494c9d5 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -108,6 +108,11 @@ R: Marcin Wojtas Platform/SolidRun/Armada80x0McBin R: Marcin Wojtas =20 +Platform/RiscV +Platform/RiscV/SiFive/U500Pkg +R: Abner Chang +R: Gilbert Chen + Silicon M: Ard Biesheuvel M: Leif Lindholm @@ -151,3 +156,7 @@ M: Liming Gao =20 Silicon/Marvell R: Marcin Wojtas + +Silicon/SiFive +R: Abner Chang +R: Gilbert Chen diff --git a/Readme.md b/Readme.md index 63e59f60..0395e20a 100644 --- a/Readme.md +++ b/Readme.md @@ -52,6 +52,7 @@ ARM | arm-linux-gnueabihf- IA32 | i?86-linux-gnu-* _or_ x86_64-linux-gnu- IPF | ia64-linux-gnu X64 | x86_64-linux-gnu- +RISCV64 | riscv64-unknown-elf- =20 \* i386, i486, i586 or i686 =20 @@ -62,6 +63,12 @@ and [arm-linux-gnueabihf](https://releases.linaro.org/co= mponents/toolchain/binar compiled to run on x86_64/i686 Linux and i686 Windows. Some Linux distribu= tions provide their own packaged cross-toolchains. =20 +### GCC for RISC-V +RISC-V open source community provides GCC toolchains for +[riscv64-unknown-elf](https://github.com/riscv/riscv-gnu-toolchain) +compiled to run on x86 Linux. The commit ID 64879b24 is verified to build = RISC-V EDK2 platform and boot to EFI +SHELL successfully. + ### clang Clang does not require separate cross compilers, but it does need a target-specific binutils. These are included with any prepackaged GCC tool= chain @@ -243,6 +250,10 @@ For more information, see the ## Raspberry Pi * [Pi 3](Platform/RaspberryPi/RPi3) =20 +## RISC-V +### SiFive +* [Freedom U500 VC707 FPGA](Platform/RiscV/SiFive/U500Pkg) + ## Socionext * [SynQuacer](Platform/Socionext/DeveloperBox) =20 --=20 2.12.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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