From nobody Sun Apr 28 20:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47438+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47438+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1568760557; cv=none; d=zoho.com; s=zohoarc; b=CnG7DHxgQZsOaiHd4Vif46kIWoWeiaLZXsdHT7HqBNFBlztiQ50Jmo1d9NPp9oHfhRNK58kwBFpWwWrQDBbGc8CJ+TZPd+gJAUMDKT+O9+k8r8yiZGmbiRPK4vcMAJKcIXsofU9b2xIuUBcSrXwZBVGiQN2R7lDt/ykmtrezhzo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568760557; h=Content-Type:Content-Transfer-Encoding:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=oCTs85dAWjj8rWuscQlUe6TaiZR4efftIVJt2ZWUBcg=; b=NrmkEyMUTpnjfC+G2TfgKKUYl9szqcMvDNpoDAVyxQqep8jKvxQtt0F8n/1SCRtAqpgFwABJfLMRY5K3EdSCTcoVk6inY0LtdVYkEQRHsfHgFgtzUQPCHmMIgo8i9YAfSKX5xwxh8PYA58kBDBh9PELhtbYjIBMA+fpPbUF9a+E= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47438+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568760557629214.13548688216508; Tue, 17 Sep 2019 15:49:17 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id NS4dYY1788612xmfvn267t82; Tue, 17 Sep 2019 15:49:17 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Tue, 17 Sep 2019 15:49:16 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Sep 2019 15:49:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,518,1559545200"; d="scan'208";a="189072271" X-Received: from jelofgre-desk.amr.corp.intel.com ([10.78.26.249]) by orsmga003.jf.intel.com with ESMTP; 17 Sep 2019 15:49:15 -0700 From: "John E Lofgren" To: devel@edk2.groups.io Subject: [edk2-devel] [Patch V3] UefiCpuPkg/CpuExceptionHandlerLib: Fix split lock Date: Tue, 17 Sep 2019 15:49:10 -0700 Message-Id: <20190917224910.28040-1-john.e.lofgren@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,john.e.lofgren@intel.com X-Gm-Message-State: nEgd8GfW32Mv2FAVH0Plik8rx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568760557; bh=INJs9t92ONL8Ga+PTL2MrWviC784olSr8g3Br5TG/00=; h=Content-Type:Date:From:Reply-To:Subject:To; b=jyQjj/iH+oEOtRCqmp32xKvOFTyRnAmtbzEoZFVAYdTjzx/6A+C6Ko5pWNW21RjAdOS cWNcBtfyw0AaprpNgPDkY9jGNG5UADcp2s6Rpg0Xn1kqPp7tga5uZzR1RvgTWpgXf7fj0 ULkbEkYOiyT4I+L5si+FrKKF3Gyf55eMQGY= X-ZohoMail-DKIM: pass (identity @groups.io) REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2150 V3 changes: change to mov instruction (non locking instuction) instead of xchg to simplify design. V2 changes: Add xchg 16 bit instructions to handle sgdt and sidt base 63:48 bits and 47:32 bits. Add comment to explain why xchg 64bit isnt being used Split lock happens when a locking instruction is used on mis-aligned data that crosses two cachelines. If close source platform enables Alignment Che= ck Exception(#AC), They can hit a double fault due to split lock being in CpuExceptionHandlerLib. sigt and sgdt saves 10 bytes to memory, 8 bytes is base and 2 bytes is limi= t. The data is mis-aligned, can cross two cacheline, and a xchg instruction(locking instuction) is being utilize. Signed-off-by: John E Lofgren --- UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm | 2= 0 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandler= Asm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAs= m.nasm index 4db1a09f28..7b7642b290 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -180,21 +180,29 @@ HasErrorCode: push qword [rbp + 24] =20 ;; UINT64 Gdtr[2], Idtr[2]; + ; sidt and sgdt saves 10 bytes to memory, 8 bytes =3D base and 2 bytes= =3D limit. + ; To avoid #AC split lock when separating base and limit into their + ; own separate 64 bit memory, we can=E2=80=99t use 64 bit xchg since b= ase [63:48] bits + ; may cross the cache line. xor rax, rax push rax push rax sidt [rsp] - xchg rax, [rsp + 2] - xchg rax, [rsp] - xchg rax, [rsp + 8] + xchg eax, [rsp + 2] + xchg eax, [rsp] + xchg eax, [rsp + 8] + xchg ax, [rsp + 6] + xchg ax, [rsp + 4] =20 xor rax, rax push rax push rax sgdt [rsp] - xchg rax, [rsp + 2] - xchg rax, [rsp] - xchg rax, [rsp + 8] + xchg eax, [rsp + 2] + xchg eax, [rsp] + xchg eax, [rsp + 8] + xchg ax, [rsp + 6] + xchg ax, [rsp + 4] =20 ;; UINT64 Ldtr, Tr; xor rax, rax --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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