From nobody Fri May 3 18:48:45 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47168+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47168+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1568265743; cv=none; d=zoho.com; s=zohoarc; b=BB79sGSyZwtGMHCB8Qtw6/TzIZNaQqie3RLkTHV1JDNTLdUuecpgGaOWxCzayRoM1XjjgMWbVt06aFUB7JhGTGaacZsHX6JHrqB3+4vrdauKET15iuCLHzu5n59vXf9usvgwx12yIr47CO5TVzzMDDJeVzFmpdJjOHRhfurJuZg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568265743; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=CT07/iw9N+lTQHeRsMqW0p4NuTxBITYh1vTfVYN0HK8=; b=gST3BohHS9hVh79h5hPoHN9Jn4KUmPa5Es2bUalt4jaWq3D7o1ZyF5iAP4/MUaUFXxDLwlrzuuq3pIAASbUnuQ/fsFS/k+a2Ikln2EAF73eMxVI/R3fO1SMkCB+83mt+YCMJ3nHOmjatzimUPqFbml/rEs4Wie8M2RZLd2GQp9I= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47168+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568265743500249.28229919372836; Wed, 11 Sep 2019 22:22:23 -0700 (PDT) Return-Path: X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Wed, 11 Sep 2019 22:22:22 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Sep 2019 22:22:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,492,1559545200"; d="scan'208";a="189881454" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga006.jf.intel.com with ESMTP; 11 Sep 2019 22:22:20 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v2] UefiCpuPkg/CpuDxe: clean up PAGE_TABLE_LIB_PAGING_CONTEXT usage. Date: Thu, 12 Sep 2019 13:22:18 +0800 Message-Id: <20190912052218.20500-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568265742; bh=hWXobqR8z/yQ5Fmc4Yyjbjr6jRyMxPzgFNiHNeHjDeU=; h=Cc:Date:From:Reply-To:Subject:To; b=b1cUro38K5ae/KAOLex5wELtT2UCk40l/+1YYbAml3Jj0b8gSbfe0yRgDxUXFdmz872 qFd+st55LBIxumYzpC2B8uS870nk5tJr1xEmY/4jI595dbnTobbOC0ftzJQkM9dWilDZf XeOvnlSDgQtxjXYmEn66R8AbEpxDDx2cZKQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" V2 changes: Avoid use type case, use different file implementation. V1 changes: REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1039 Current implementation not checks system mode before using PAGE_TABLE_LIB_PAGING_CONTEXT.ContextData.X64 or PAGE_TABLE_LIB_PAGING_CONTEXT.ContextData.Ia32. This patch check the mode before using the correct one. Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Eric Dong Reviewed-by: Laszlo Ersek --- UefiCpuPkg/CpuDxe/CpuDxe.inf | 4 ++- UefiCpuPkg/CpuDxe/CpuPageTable.c | 41 +++++++++++++++--------- UefiCpuPkg/CpuDxe/CpuPageTable.h | 15 +++++++++ UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c | 34 ++++++++++++++++++++ UefiCpuPkg/CpuDxe/X64/PagingAttribute.c | 34 ++++++++++++++++++++ 5 files changed, 112 insertions(+), 16 deletions(-) create mode 100644 UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c create mode 100644 UefiCpuPkg/CpuDxe/X64/PagingAttribute.c diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf index 57381dbc85..d87fe503d1 100644 --- a/UefiCpuPkg/CpuDxe/CpuDxe.inf +++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf @@ -1,7 +1,7 @@ ## @file # CPU driver installs CPU Architecture Protocol and CPU MP protocol. # -# Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2008 - 2019, Intel Corporation. All rights reserved.
# Copyright (c) 2017, AMD Incorporated. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -54,9 +54,11 @@ =20 [Sources.IA32] Ia32/CpuAsm.nasm + Ia32/PagingAttribute.c =20 [Sources.X64] X64/CpuAsm.nasm + X64/PagingAttribute.c =20 [Protocols] gEfiCpuArchProtocolGuid ## PRODUCES diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.c index ec5cd424fc..cb12177142 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -155,6 +155,8 @@ GetCurrentPagingContext ( MSR_IA32_EFER_REGISTER MsrEfer; IA32_CR4 Cr4; IA32_CR0 Cr0; + UINT32 *Attributes; + UINTN *PageTableBase; =20 // // Don't retrieve current paging context from processor if in SMM mode. @@ -167,25 +169,27 @@ GetCurrentPagingContext ( mPagingContext.MachineType =3D IMAGE_FILE_MACHINE_I386; } =20 + GetPagingDetails (&mPagingContext.ContextData, &PageTableBase, &Attrib= utes); + Cr0.UintN =3D AsmReadCr0 (); Cr4.UintN =3D AsmReadCr4 (); =20 if (Cr0.Bits.PG !=3D 0) { - mPagingContext.ContextData.X64.PageTableBase =3D (AsmReadCr3 () & PA= GING_4K_ADDRESS_MASK_64); + *PageTableBase =3D (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); } else { - mPagingContext.ContextData.X64.PageTableBase =3D 0; + *PageTableBase =3D 0; } if (Cr0.Bits.WP !=3D 0) { - mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_WP_ENABLE; + *Attributes |=3D PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_W= P_ENABLE; } if (Cr4.Bits.PSE !=3D 0) { - mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_PSE; + *Attributes |=3D PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_P= SE; } if (Cr4.Bits.PAE !=3D 0) { - mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_PAE; + *Attributes |=3D PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_P= AE; } if (Cr4.Bits.LA57 !=3D 0) { - mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAGIN= G_CONTEXT_IA32_X64_ATTRIBUTES_5_LEVEL; + *Attributes |=3D PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_5= _LEVEL; } =20 AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL); @@ -197,12 +201,12 @@ GetCurrentPagingContext ( MsrEfer.Uint64 =3D AsmReadMsr64(MSR_CORE_IA32_EFER); if (MsrEfer.Bits.NXE !=3D 0) { // XD activated - mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_P= AGING_CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED; + *Attributes |=3D PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUT= ES_XD_ACTIVATED; } } =20 if (RegEdx.Bits.Page1GB !=3D 0) { - mPagingContext.ContextData.Ia32.Attributes |=3D PAGE_TABLE_LIB_PAG= ING_CONTEXT_IA32_X64_ATTRIBUTES_PAGE_1G_SUPPORT; + *Attributes |=3D PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES= _PAGE_1G_SUPPORT; } } } @@ -395,6 +399,7 @@ ConvertPageEntryAttribute ( { UINT64 CurrentPageEntry; UINT64 NewPageEntry; + UINT32 *PageAttributes; =20 CurrentPageEntry =3D *PageEntry; NewPageEntry =3D CurrentPageEntry; @@ -438,7 +443,10 @@ ConvertPageEntryAttribute ( break; } } - if ((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_= CONTEXT_IA32_X64_ATTRIBUTES_XD_ACTIVATED) !=3D 0) { + + GetPagingDetails (&PagingContext->ContextData, NULL, &PageAttributes); + + if ((*PageAttributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES= _XD_ACTIVATED) !=3D 0) { if ((Attributes & EFI_MEMORY_XP) !=3D 0) { switch (PageAction) { case PageActionAssign: @@ -1338,15 +1346,18 @@ InitializePageTableLib ( ) { PAGE_TABLE_LIB_PAGING_CONTEXT CurrentPagingContext; + UINT32 *Attributes; + UINTN *PageTableBase; =20 GetCurrentPagingContext (&CurrentPagingContext); =20 + GetPagingDetails (&CurrentPagingContext.ContextData, &PageTableBase, &At= tributes); + // // Reserve memory of page tables for future uses, if paging is enabled. // - if (CurrentPagingContext.ContextData.X64.PageTableBase !=3D 0 && - (CurrentPagingContext.ContextData.Ia32.Attributes & - PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) !=3D 0) { + if ((*PageTableBase !=3D 0) && + (*Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE= ) !=3D 0) { DisableReadOnlyPageWriteProtect (); InitializePageTablePool (1); EnableReadOnlyPageWriteProtect (); @@ -1361,10 +1372,10 @@ InitializePageTableLib ( ASSERT (mLastPFEntryPointer !=3D NULL); } =20 - DEBUG ((DEBUG_INFO, "CurrentPagingContext:\n", CurrentPagingContext.Mach= ineType)); + DEBUG ((DEBUG_INFO, "CurrentPagingContext:\n")); DEBUG ((DEBUG_INFO, " MachineType - 0x%x\n", CurrentPagingContext.Mac= hineType)); - DEBUG ((DEBUG_INFO, " PageTableBase - 0x%x\n", CurrentPagingContext.Con= textData.X64.PageTableBase)); - DEBUG ((DEBUG_INFO, " Attributes - 0x%x\n", CurrentPagingContext.Con= textData.X64.Attributes)); + DEBUG ((DEBUG_INFO, " PageTableBase - 0x%Lx\n", (UINT64)*PageTableBase)= ); + DEBUG ((DEBUG_INFO, " Attributes - 0x%x\n", *Attributes)); =20 return ; } diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.h b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.h index f845956f73..0234d1f96a 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.h +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.h @@ -139,4 +139,19 @@ AllocatePageTableMemory ( IN UINTN Pages ); =20 +/** + Get paging details. + + @param PagingContextData The paging context. NULL means get page t= able from current CPU context. + @param PageTableBase Return PageTableBase field. + @param Attributes Return Attributes field. + +**/ +VOID +GetPagingDetails ( + IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, + OUT UINTN **PageTableBase OPTIONAL, + OUT UINT32 **Attributes OPTIONAL + ); + #endif diff --git a/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c b/UefiCpuPkg/CpuDxe/I= a32/PagingAttribute.c new file mode 100644 index 0000000000..120c0f101a --- /dev/null +++ b/UefiCpuPkg/CpuDxe/Ia32/PagingAttribute.c @@ -0,0 +1,34 @@ +/** @file + Return Paging attribute. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CpuPageTable.h" + + +/** + Get paging details. + + @param PagingContextData The paging context. NULL means get page t= able from current CPU context. + @param PageTableBase Return PageTableBase field. + @param Attributes Return Attributes field. + +**/ +VOID +GetPagingDetails ( + IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, + OUT UINTN **PageTableBase OPTIONAL, + OUT UINT32 **Attributes OPTIONAL + ) +{ + if (PageTableBase !=3D NULL) { + *PageTableBase =3D &PagingContextData->Ia32.PageTableBase; + } + if (Attributes !=3D NULL) { + *Attributes =3D &PagingContextData->Ia32.Attributes; + } +} + diff --git a/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c b/UefiCpuPkg/CpuDxe/X6= 4/PagingAttribute.c new file mode 100644 index 0000000000..fe35d33ed9 --- /dev/null +++ b/UefiCpuPkg/CpuDxe/X64/PagingAttribute.c @@ -0,0 +1,34 @@ +/** @file + Return Paging attribute. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CpuPageTable.h" + + +/** + Get paging details. + + @param PagingContextData The paging context. NULL means get page t= able from current CPU context. + @param PageTableBase Return PageTableBase field. + @param Attributes Return Attributes field. + +**/ +VOID +GetPagingDetails ( + IN PAGE_TABLE_LIB_PAGING_CONTEXT_DATA *PagingContextData, + OUT UINTN **PageTableBase OPTIONAL, + OUT UINT32 **Attributes OPTIONAL + ) +{ + if (PageTableBase !=3D NULL) { + *PageTableBase =3D &PagingContextData->X64.PageTableBase; + } + if (Attributes !=3D NULL) { + *Attributes =3D &PagingContextData->X64.Attributes; + } +} + --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47168): https://edk2.groups.io/g/devel/message/47168 Mute This Topic: https://groups.io/mt/34112095/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-