From nobody Sat Apr 27 01:33:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46951+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46951+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1567722010; cv=none; d=zoho.com; s=zohoarc; b=YFNbAK5zY6PflUxBzKTgdH51vaZ4ozPnzKbLZgmKwNbKOclc+JWC+937zytaNc8I01UVhfTYARa5apEmuXfqrgJzyQ7vvPVKRnG/ud/dLqYtpxZAOXTJIujr+6zqof61D+fWsQYI1FM92X3X2pZCkpHiGXd/B5MvRJWubhyhmCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1567722010; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=GQUoQ23BH/FzBLtEKkOWJikhxJnvmoszsZh1X5TWOGQ=; b=J02fZi0OvlfOP8UbFuLJHV7mq04wYIJDOb6LQP41ySZmO67W8hcFwp6GPYuvDW3k92chkUn5ZoUsRwe108bJpl3HJyVMraOeDfVAkaISbzNPgm+2vucTt0j274VGRBpgtmTRO0JXomrcDrY3tYs4gpNx7WuqIcclIrtUBKyHT4o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46951+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1567722010423703.5758058597617; Thu, 5 Sep 2019 15:20:10 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by groups.io with SMTP; Thu, 05 Sep 2019 15:20:09 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Sep 2019 15:20:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,471,1559545200"; d="scan'208";a="195244650" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.9.9]) by orsmga002.jf.intel.com with ESMTP; 05 Sep 2019 15:20:07 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Liming Gao , Eric Dong , Laszlo Ersek Subject: [edk2-devel] [PATCH] UefiCpuPkg/PiSmmCpu: Enable 5L paging only when phy addr line > 48 Date: Fri, 6 Sep 2019 06:19:11 +0800 Message-Id: <20190905221911.197356-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1567722010; bh=KuIB/Jq0Hw1FibGmjDar4CdsthlaSZ3vswYZ7S0Iux8=; h=Cc:Date:From:Reply-To:Subject:To; b=tOq6GWb1WWTbVEkMG41iMdYO/hTfHZ63t50XpmjRNdFwXimomBAhfeWWwxcbIxSwx82 XPxibLCEbcA+oF9xlwLI8cc4WOscxrgrdoZLpPI2SPTN0LlMAXdx4Hf2TsgkuJw9E8uCq dZ3y7YbDgNW98CnLz99dbLthSnGh6kxC8Rg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Today's behavior is to enable 5l paging when CPU supports it (CPUID[7,0].ECX.BIT[16] is set). The patch changes the behavior to enable 5l paging when two conditions are both met: 1. CPU supports it; 2. The max physical address bits is bigger than 48. Because 4-level paging can support to address physical address up to 2^48 - 1, there is no need to enable 5-level paging with max physical address bits <=3D 48. Signed-off-by: Ray Ni Cc: Liming Gao Cc: Eric Dong Cc: Laszlo Ersek Reviewed-by: Eric Dong --- UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 57 +++++++++++++-------- UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm | 4 +- 2 files changed, 39 insertions(+), 22 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c b/UefiCpuPkg/PiSmmCpuD= xeSmm/X64/PageTbl.c index 733d107efd..e5c4788c13 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c @@ -16,8 +16,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent LIST_ENTRY mPagePool =3D INITIALIZE_LIST_HEAD_VAR= IABLE (mPagePool); BOOLEAN m1GPageTableSupport =3D FALSE; BOOLEAN mCpuSmmRestrictedMemoryAccess; -BOOLEAN m5LevelPagingSupport; -X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingSupport; +BOOLEAN m5LevelPagingNeeded; +X86_ASSEMBLY_PATCH_LABEL gPatch5LevelPagingNeeded; =20 /** Disable CET. @@ -63,28 +63,45 @@ Is1GPageSupport ( } =20 /** - Check if 5-level paging is supported by processor or not. - - @retval TRUE 5-level paging is supported. - @retval FALSE 5-level paging is not supported. + The routine returns TRUE when CPU supports it (CPUID[7,0].ECX.BIT[16] is= set) and + the max physical address bits is bigger than 48. Because 4-level paging = can support + to address physical address up to 2^48 - 1, there is no need to enable 5= -level paging + with max physical address bits <=3D 48. =20 + @retval TRUE 5-level paging enabling is needed. + @retval FALSE 5-level paging enabling is not needed. **/ BOOLEAN -Is5LevelPagingSupport ( +Is5LevelPagingNeeded ( VOID ) { - CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags; + CPUID_VIR_PHY_ADDRESS_SIZE_EAX VirPhyAddressSize; + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX ExtFeatureEcx; + UINT32 MaxExtendedFunctionId; =20 + AsmCpuid (CPUID_EXTENDED_FUNCTION, &MaxExtendedFunctionId, NULL, NULL, N= ULL); + if (MaxExtendedFunctionId >=3D CPUID_VIR_PHY_ADDRESS_SIZE) { + AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &VirPhyAddressSize.Uint32, NULL,= NULL, NULL); + } else { + VirPhyAddressSize.Bits.PhysicalAddressBits =3D 36; + } AsmCpuidEx ( CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, - NULL, - NULL, - &EcxFlags.Uint32, - NULL + NULL, NULL, &ExtFeatureEcx.Uint32, NULL ); - return (BOOLEAN) (EcxFlags.Bits.FiveLevelPage !=3D 0); + DEBUG (( + DEBUG_INFO, "PhysicalAddressBits =3D %d, 5LPageTable =3D %d.\n", + VirPhyAddressSize.Bits.PhysicalAddressBits, ExtFeatureEcx.Bits.FiveLev= elPage + )); + + if (VirPhyAddressSize.Bits.PhysicalAddressBits > 4 * 9 + 12) { + ASSERT (ExtFeatureEcx.Bits.FiveLevelPage =3D=3D 1); + return TRUE; + } else { + return FALSE; + } } =20 /** @@ -190,7 +207,7 @@ SetStaticPageTable ( // when 5-Level Paging is disabled. // ASSERT (mPhysicalAddressBits <=3D 52); - if (!m5LevelPagingSupport && mPhysicalAddressBits > 48) { + if (!m5LevelPagingNeeded && mPhysicalAddressBits > 48) { mPhysicalAddressBits =3D 48; } =20 @@ -217,7 +234,7 @@ SetStaticPageTable ( =20 PageMapLevel4Entry =3D PageMap; PageMapLevel5Entry =3D NULL; - if (m5LevelPagingSupport) { + if (m5LevelPagingNeeded) { // // By architecture only one PageMapLevel5 exists - so lets allocate st= orage for it. // @@ -233,7 +250,7 @@ SetStaticPageTable ( // So lets allocate space for them and fill them in in the IndexOfPml4= Entries loop. // When 5-Level Paging is disabled, below allocation happens only once. // - if (m5LevelPagingSupport) { + if (m5LevelPagingNeeded) { PageMapLevel4Entry =3D (UINT64 *) ((*PageMapLevel5Entry) & ~mAddress= EncMask & gPhyMask); if (PageMapLevel4Entry =3D=3D NULL) { PageMapLevel4Entry =3D AllocatePageTableMemory (1); @@ -336,10 +353,10 @@ SmmInitPageTable ( =20 mCpuSmmRestrictedMemoryAccess =3D PcdGetBool (PcdCpuSmmRestrictedMemoryA= ccess); m1GPageTableSupport =3D Is1GPageSupport (); - m5LevelPagingSupport =3D Is5LevelPagingSupport (); + m5LevelPagingNeeded =3D Is5LevelPagingNeeded (); mPhysicalAddressBits =3D CalculateMaximumSupportAddress (); - PatchInstructionX86 (gPatch5LevelPagingSupport, m5LevelPagingSupport, 1); - DEBUG ((DEBUG_INFO, "5LevelPaging Support - %d\n", m5LevelPag= ingSupport)); + PatchInstructionX86 (gPatch5LevelPagingNeeded, m5LevelPagingNeeded, 1); + DEBUG ((DEBUG_INFO, "5LevelPaging Needed - %d\n", m5LevelPag= ingNeeded)); DEBUG ((DEBUG_INFO, "1GPageTable Support - %d\n", m1GPageTab= leSupport)); DEBUG ((DEBUG_INFO, "PcdCpuSmmRestrictedMemoryAccess - %d\n", mCpuSmmRes= trictedMemoryAccess)); DEBUG ((DEBUG_INFO, "PhysicalAddressBits - %d\n", mPhysicalA= ddressBits)); @@ -370,7 +387,7 @@ SmmInitPageTable ( SetSubEntriesNum (Pml4Entry, 3); PTEntry =3D Pml4Entry; =20 - if (m5LevelPagingSupport) { + if (m5LevelPagingNeeded) { // // Fill PML5 entry // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmm= CpuDxeSmm/X64/SmiEntry.nasm index 271492a9d7..db06d22d51 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm @@ -69,7 +69,7 @@ extern ASM_PFX(mXdSupported) global ASM_PFX(gPatchXdSupported) global ASM_PFX(gPatchSmiStack) global ASM_PFX(gPatchSmiCr3) -global ASM_PFX(gPatch5LevelPagingSupport) +global ASM_PFX(gPatch5LevelPagingNeeded) global ASM_PFX(gcSmiHandlerTemplate) global ASM_PFX(gcSmiHandlerSize) =20 @@ -127,7 +127,7 @@ ASM_PFX(gPatchSmiCr3): mov eax, 0x668 ; as cr4.PGE is not set here, ref= resh cr3 =20 mov cl, strict byte 0 ; source operand will be patched -ASM_PFX(gPatch5LevelPagingSupport): +ASM_PFX(gPatch5LevelPagingNeeded): cmp cl, 0 je SkipEnable5LevelPaging ; --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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