From nobody Sun Apr 28 22:34:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46369+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46369+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566845296; cv=none; d=zoho.com; s=zohoarc; b=CHkAB1Ma79QcGiBg24ibx08SvuWzSRbsqzyCJ6PePsCmlwC6jeiWI6Q8fdK9TAVW/TMDjcwlTdPPikwXYpAOMU48BS8DynwmYnUzCOZritMTUXIuiBhyz1VW38MoVCfvM5njEpl6nuFMExrxgd0mRmxNUCSpoTCglKl7ZVggBaY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566845296; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=wpOVgGNSLYUfiqqcB9q3PKSHzPA/dS6VEeIW0lmGLck=; b=IKPYoDukV05G1w5ocdZjYqcqjIdHthI4iVHjvhUcPvlF57GAi4zB92cgr5XU0NAkPgPp9rj8aBRNvd6Uyr5w4u/RBU5uc7NAqICC8q9KxmN2s1b6j3QWYzT+OcUY7NrUttvBSYTaci510FY1Es8yE3vAYvfmk/EeYMsaDP60aLI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46369+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566845296795546.9522932517057; Mon, 26 Aug 2019 11:48:16 -0700 (PDT) Return-Path: X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 26 Aug 2019 11:48:15 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Aug 2019 11:48:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,433,1559545200"; d="scan'208";a="355517547" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga005.jf.intel.com with ESMTP; 26 Aug 2019 11:48:15 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Sai Chaganty Subject: [edk2-devel] [edk2-platforms][PATCH V3 1/2] CoffeelakeSiliconPkg: Fix GCC Build Failures Date: Mon, 26 Aug 2019 11:47:57 -0700 Message-Id: <20190826184758.12440-2-michael.a.kubacki@intel.com> In-Reply-To: <20190826184758.12440-1-michael.a.kubacki@intel.com> References: <20190826184758.12440-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566845296; bh=IMfdZk9UfpSmqa1BLHbd0gFVocQMEI3TUyH2hls/gYU=; h=Cc:Date:From:Reply-To:Subject:To; b=YoP3fE3NOzsPXct729fMqkAK6J27RoB4bSvWLc0ZPTJybHYVwozWX2D4NtKlRleCTNp DboE9zePrX3oAnN3iUr4HgrNqKcQRBsIa9gZsNDhQ8k7OoTkUcXabXItpTxw8HruLMqlj rRCN+iVahzWLKBcZqVXMExeQUZzxd/Re868= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2124 Fixes build failures on GCC7.3.0. Tested on Ubuntu 18.04.1 LTS. Cc: Chasel Chiu Cc: Sai Chaganty Signed-off-by: Michael Kubacki Reviewed-by: Chasel Chiu Reviewed-by: Sai Chaganty --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h= | 2 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h = | 1 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolic= yLib.c | 2 -- Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c = | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdA= udioConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/H= dAudioConfig.h index a810d4f1fc..e2c8730f38 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioCon= fig.h +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioCon= fig.h @@ -9,7 +9,9 @@ #ifndef _HDAUDIO_CONFIG_H_ #define _HDAUDIO_CONFIG_H_ =20 +#include #include +#include =20 #define HDAUDIO_PREMEM_CONFIG_REVISION 1 #define HDAUDIO_CONFIG_REVISION 2 diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h index 25def24fca..ff76e7c60f 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h @@ -11,6 +11,7 @@ #define _GPIO_LIB_H_ =20 #include +#include =20 #define GPIO_NAME_LENGTH_MAX 32 =20 diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib= /PeiPchPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchP= olicyLib/PeiPchPolicyLib.c index 2a1da20667..ece0be8158 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPch= PolicyLib.c +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPch= PolicyLib.c @@ -353,10 +353,8 @@ LoadLanConfigDefault ( ) { PCH_LAN_CONFIG *LanConfig; - UINT16 LpcDid; =20 LanConfig =3D ConfigBlockPointer; - LpcDid =3D PchGetLpcDid (); =20 DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Name =3D %g\n", &LanConfi= g->Header.GuidHob.Name)); DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", LanConfig->Header.GuidHob.Header.HobLength)); diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIn= itDxe.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitD= xe.c index d646e60618..e6980f9a65 100644 --- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c @@ -41,6 +41,7 @@ SaInitEntryPointDxe ( SaInitEntryPoint (); =20 Status =3D SaAcpiInit (ImageHandle); + ASSERT_EFI_ERROR (Status); =20 /// /// Create PCI Enumeration Completed callback for SA --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#46369): https://edk2.groups.io/g/devel/message/46369 Mute This Topic: https://groups.io/mt/33037332/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Apr 28 22:34:08 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+46370+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46370+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566845297; cv=none; d=zoho.com; s=zohoarc; b=TcG0tCmYIYkoTLVIhbPZnxFmDZmQLx1HvcSVJ73rI5ygBBKjfjuJMDQ1BxtZieukXshT/7DxlE2G0xNw7TQTLwHjw+unFdn8NQv7e9f2bLEU5hSlO9RBAoUSkL1S+Jz6btqDRMqnHKh5XfioAV5N1aHH321AmDCCWGFCU/0DkGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566845297; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=n+T1CAtYu5YOf41rwcE9T340H79nw9OFdmGp8RERGF8=; b=mAaHBHKFufNgLT9Z0RkdfOhvqMezRVF5yfxSiUWd0moZLsBUXAc2YQqWsJZtw9q1VkCVYWTX/2P8esit/lBaTBJDUEyxQsi0LacXqBZO1TLzoN8r5kc1GpLfbbl2gLUqeNAVkToPpSbjBye+giBy26r4WYaL+jrvPeHkDhTOb8Q= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+46370+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566845297630194.32471496150492; Mon, 26 Aug 2019 11:48:17 -0700 (PDT) Return-Path: X-Received: from mga05.intel.com (mga05.intel.com []) by groups.io with SMTP; Mon, 26 Aug 2019 11:48:16 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Aug 2019 11:48:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,433,1559545200"; d="scan'208";a="355517553" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga005.jf.intel.com with ESMTP; 26 Aug 2019 11:48:16 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Liming Gao Subject: [edk2-devel] [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix GCC Build Failures Date: Mon, 26 Aug 2019 11:47:58 -0700 Message-Id: <20190826184758.12440-3-michael.a.kubacki@intel.com> In-Reply-To: <20190826184758.12440-1-michael.a.kubacki@intel.com> References: <20190826184758.12440-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566845297; bh=Sj0ZrdxccXNFcf70mctg/75Flv9g6PTsKCeV7lMTpis=; h=Cc:Date:From:Reply-To:Subject:To; b=DlREfj5XOwiEWNkkRb4mdJfAWwOWu9e0z/yxYddsqZcApzJ7FSvTAabTWzcYn/SXI7q 7+fXJ24440ROIlWNm4UqTXyenE5r6QHCIRwiEvON0l63Z5Y64KmIhKowsVkKTCaTLYpqp Ib11eavfIfcq0A3ixcbso/V8UTv48KbPOuM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2110 Fixes build failures on GCC7.3.0. Tested on Ubunutu 18.04.1 LTS. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Signed-off-by: Michael Kubacki --- Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec = | 6 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVe= rbTableLib.inf | 1 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiBoardInitPostMemLib.inf | 8 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPostMemLib.inf | 2 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPreMemLib.inf | 12 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h = | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whiskeylake= URvpId.h | 12 - Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardFunc.h | 2 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiWhiskeylakeURvpInitLib.h | 41 - Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/WhiskeylakeURvpInit.h | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspCpuPolicyInitLib.c | 4 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpi= oExpanderLib.c | 6 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{PchHdaV= erbTables.h =3D> PchHdaVerbTables.c} | 963 +-------= ------------ Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVe= rbTableLib.c | 7 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPchPolicyUpdate.c | 6 - Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSaPolicyUpdatePreMem.c | 15 +- Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c= | 4 - Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmMultiBoardAcpiSupportLib.c | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmWhiskeylakeURvpAcpiEnableLib.c | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardFuncInit.c | 1 - Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardFuncInitPreMem.c | 1 - Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardPchInitPreMemLib.c | 12 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardSaInitPreMemLib.c | 6 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/{GpioTableDefault.h =3D> GpioTableDefault.c} | 16 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/{GpioTableWhlUDdr4.h =3D> GpioTableWhiskeylakeUDdr4Rvp.c} | 20 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/{GpioTableWhlUDdr4PreMem.h =3D> GpioTableWhlUDdr4PreMem.c} | 21 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPostMemLib.c | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPreMemLib.c | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiWhiskeylakeURvpDetect.c | 2 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiWhiskeylakeURvpInitPostMemLib.c | 71 +- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiWhiskeylakeURvpInitPreMemLib.c | 106 ++- 31 files changed, 223 insertions(+), 1173 deletions(-) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec b/Plat= form/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec index 9d56f0e841..8de48077f0 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec @@ -17,12 +17,12 @@ DEC_SPECIFICATION =3D 0x00010017 PACKAGE_NAME =3D OpenBoardPkg PACKAGE_VERSION =3D 0.1 -PACKAGE_GUID =3D 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E +PACKAGE_GUID =3D 8FE3E02F-BC79-41F2-9A0D-10140B292472 =20 [Includes] Include -WhiskeylakeURvp\Include -Features\Tbt\Include +Features/Tbt/Include +WhiskeylakeURvp/Include =20 [Guids] =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PeiHdaVerbTableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library= /PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf index 3c017577b6..b09dc6b139 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.inf @@ -36,6 +36,7 @@ =20 [Sources] PeiHdaVerbTableLib.c + PchHdaVerbTables.c =20 ##########################################################################= ###### # diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf index a8c4869e96..91cc569388 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPostMemLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPostMemLib.inf @@ -19,11 +19,12 @@ =20 [LibraryClasses] BaseLib - DebugLib BaseMemoryLib + DebugLib + GpioExpanderLib + GpioLib HdaVerbTableLib MemoryAllocationLib - GpioExpanderLib PcdLib =20 [Packages] @@ -37,6 +38,8 @@ [Sources] PeiWhiskeylakeURvpInitPostMemLib.c PeiBoardInitPostMemLib.c + GpioTableDefault.c + GpioTableWhiskeylakeUDdr4Rvp.c =20 [Pcd] gBoardModuleTokenSpaceGuid.PcdBoardGpioTable @@ -50,4 +53,3 @@ gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize =20 gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum - diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeO= penBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLi= b.inf index 4831735dc5..c7330439fb 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPostMemLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPostMemLib.inf @@ -44,6 +44,8 @@ PeiMultiBoardInitPostMemLib.c BoardFunc.c BoardFuncInit.c + GpioTableDefault.c + GpioTableWhiskeylakeUDdr4Rvp.c =20 [FixedPcd] =20 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOp= enBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.= inf index 6affc3180e..927a89d401 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPreMemLib.inf @@ -20,17 +20,18 @@ =20 [LibraryClasses] BaseLib - DebugLib BaseMemoryLib + DebugLib + GpioLib MemoryAllocationLib - PcdLib MultiBoardInitSupportLib - StallPpiLib + OcWdtLib + PcdLib PchResetLib PeiPlatformHookLib - PlatformHookLib PeiPolicyInitLib - OcWdtLib + PlatformHookLib + StallPpiLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec @@ -47,6 +48,7 @@ BoardSaInitPreMemLib.c BoardPchInitPreMemLib.c BoardFuncInitPreMem.c + GpioTableWhlUDdr4PreMem.c =20 [Ppis] gEfiPeiReadOnlyVariable2PpiGuid diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverr= ideTable.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverr= ideTable.h index 395d08779c..79f98af2f0 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTabl= e.h +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTabl= e.h @@ -9,7 +9,7 @@ #ifndef _PCIE_DEVICE_OVERRIDE_TABLE_H_ #define _PCIE_DEVICE_OVERRIDE_TABLE_H_ =20 -#include +#include #include =20 #define PCI_CLASS_NETWORK 0x02 diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /WhiskeylakeURvpId.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeUR= vp/Include/WhiskeylakeURvpId.h deleted file mode 100644 index 7d44acccc1..0000000000 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whiske= ylakeURvpId.h +++ /dev/null @@ -1,12 +0,0 @@ -/** @file - - Copyright (c) 2019, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#ifndef _WHISKEYLAKE_ERB_ID_H_ -#define _WHISKEYLAKE_ERB_ID_H_ - -#define BoardIdWhiskeyLakeRvp 0x60 -#endif // _WHISKEYLAKE_RVP3_ID_H_ - diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardFunc.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whiskeyl= akeURvp/Library/BoardInitLib/BoardFunc.h index eca492e72d..9e0ff8d033 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFunc.h +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFunc.h @@ -9,6 +9,8 @@ #ifndef _BOARD_FUNC_H_ #define _BOARD_FUNC_H_ =20 +#include + EFI_STATUS PeiBoardSpecificInitPostMemNull ( VOID diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiWhiskeylakeURvpInitLib.h b/Platform/Intel/WhiskeylakeOpenB= oardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h deleted file mode 100644 index 89c780cc0b..0000000000 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpInitLib.h +++ /dev/null @@ -1,41 +0,0 @@ -/** @file - - Copyright (c) 2019, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent -**/ - -#ifndef _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_ -#define _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -extern const UINT8 mDqByteMapSklRvp3[2][6][2]; -extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8]; -extern const UINT8 mSkylakeRvp3Spd110[]; -extern const UINT16 mSkylakeRvp3Spd110Size; -extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[]; -extern UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size; -extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[]; -extern UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size; - -extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[]; -extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize; - -extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[]; -extern UINT16 mGpioTableIoExpanderSize; -extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel; -extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[]; -extern UINT16 mGpioTableLpDdr3Rvp3Size; - -#endif // _PEI_Whiskeylake_RVP3_BOARD_INIT_LIB_H_ - diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/WhiskeylakeURvpInit.h b/Platform/Intel/WhiskeylakeOpenBoardPk= g/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h new file mode 100644 index 0000000000..325bcb41df --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/WhiskeylakeURvpInit.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _WHISKEY_LAKE_U_RVP_INIT_H_ +#define _WHISKEY_LAKE_U_RVP_INIT_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[]; +extern UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[]; +extern UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size; + +extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[]; +extern UINT16 mGpioTableWhlUDdr4PreMemSize; +extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[]; +extern UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize; +extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[]; +extern UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize; + +extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[]; +extern UINT16 mGpioTableWhlUDdr4_0Size; +extern GPIO_INIT_CONFIG mGpioTableDefault[]; +extern UINT16 mGpioTableDefaultSize; +extern GPIO_INIT_CONFIG mGpioTableWhlUDdr4[]; +extern UINT16 mGpioTableWhlUDdr4Size; + +#endif // _WHISKEY_LAKE_U_RVP_INIT_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspCpuPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c index f38901f2ae..38c95f7b5d 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspCpuPolicyInitLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspCpuPolicyInitLib.c @@ -173,7 +173,7 @@ EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformIn= formation2( // Retrieve BIST data from SecPlatform2 // Status =3D SecPlatformInformation2Ppi->PlatformInformation2 ( - PeiServices, + (CONST EFI_PEI_SERVICES **) PeiS= ervices, &InformationSize, SecPlatformInformation2 ); @@ -240,7 +240,7 @@ EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformIn= formationInfoInFormat2( // Retrieve BIST data from SecPlatform // Status =3D SecPlatformInformationPpi->PlatformInformation ( - PeiServices, + (CONST EFI_PEI_SERVICES **) PeiSe= rvices, &InformationSize, SecPlatformInformation ); diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpande= rLib/BaseGpioExpanderLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library= /BaseGpioExpanderLib/BaseGpioExpanderLib.c index 8498952888..c6009eae12 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.c @@ -70,12 +70,11 @@ GpioExpGetRegister ( IN UINT8 Register ) { - EFI_STATUS Status; UINT8 WriBuf[1]; UINT8 ReBuf[1] =3D {0}; =20 WriBuf[0] =3D Register; - Status =3D I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 1, WriBuf, 1= , ReBuf, WAIT_1_SECOND); + I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 1, WriBuf, 1, ReBuf, = WAIT_1_SECOND); =20 return ReBuf[0]; } @@ -99,13 +98,12 @@ GpioExpSetRegister ( IN UINT8 Value ) { - EFI_STATUS Status; UINT8 WriBuf[2]; =20 WriBuf[0] =3D Register; WriBuf[1] =3D Value; - Status =3D I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 2, WriBuf, 0= , NULL, WAIT_1_SECOND); =20 + I2cWriteRead (Bar0, TCA6424_I2C_ADDRESS + Address, 2, WriBuf, 0, NULL, W= AIT_1_SECOND); } /** Set the input register to a give value mentioned in the function. diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PchHdaVerbTables.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/Pei= HdaVerbTableLib/PchHdaVerbTables.c similarity index 65% rename from Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableL= ib/PchHdaVerbTables.h rename to Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib= /PchHdaVerbTables.c index 0d26e8ad7a..563685b4aa 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pch= HdaVerbTables.h +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pch= HdaVerbTables.c @@ -4,9 +4,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 -#ifndef _PCH_HDA_VERB_TABLES_H_ -#define _PCH_HDA_VERB_TABLES_H_ - +#include #include =20 HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D HDAUDIO_VERB_TABLE_INIT ( @@ -1105,962 +1103,6 @@ HDAUDIO_VERB_TABLE HdaVerbTableAlc274 =3D HDAUDIO_V= ERB_TABLE_INIT ( 0x0204201B ); //HdaVerbTableAlc274 =20 -// -// CFL S Audio Codec -// -STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_IN= IT ( - // - // VerbTable: (Realtek ALC700) CFL S RVP - // Revision ID =3D 0xff - // Codec Verb Table - // Codec Address: CAd value (0/1/2) - // Codec Vendor: 0x10EC0700 - // - 0x10EC, 0x0700, - 0xFF, 0xFF, - - //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D - // - // Realtek Semiconductor Corp. - // - //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D - - //Realtek High Definition Audio Configuration - Version : 5.0.3.1 - //Realtek HD Audio Codec : ALC700 - //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 - //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C - //The number of verb command block : 17 - - // NID 0x12 : 0x90A60130 - // NID 0x13 : 0x40000000 - // NID 0x14 : 0x411111F0 - // NID 0x15 : 0x411111F0 - // NID 0x16 : 0x03011010 - // NID 0x17 : 0x90170120 - // NID 0x18 : 0x411111F0 - // NID 0x19 : 0x04A1103E - // NID 0x1A : 0x411111F0 - // NID 0x1B : 0x03A11040 - // NID 0x1D : 0x40600001 - // NID 0x1E : 0x411111F0 - // NID 0x1F : 0x411111F0 - // NID 0x21 : 0x0421102F - // NID 0x29 : 0x411111F0 - - - //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D - //HDA Codec Subsystem ID : 0x10EC112C - 0x0017202C, - 0x00172111, - 0x001722EC, - 0x00172310, - - - //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D - //Widget node 0x01 : - 0x0017FF00, - 0x0017FF00, - 0x0017FF00, - 0x0017FF00, - //Pin widget 0x12 - DMIC - 0x01271C30, - 0x01271D01, - 0x01271EA6, - 0x01271F90, - //Pin widget 0x13 - DMIC - 0x01371C00, - 0x01371D00, - 0x01371E00, - 0x01371F40, - //Pin widget 0x14 - FRONT (Port-D) - 0x01471CF0, - 0x01471D11, - 0x01471E11, - 0x01471F41, - //Pin widget 0x15 - I2S-OUT - 0x01571CF0, - 0x01571D11, - 0x01571E11, - 0x01571F41, - //Pin widget 0x16 - LINE3 (Port-B) - 0x01671C10, - 0x01671D10, - 0x01671E01, - 0x01671F03, - //Pin widget 0x17 - I2S-OUT - 0x01771C20, - 0x01771D01, - 0x01771E17, - 0x01771F90, - //Pin widget 0x18 - I2S-IN - 0x01871CF0, - 0x01871D11, - 0x01871E11, - 0x01871F41, - //Pin widget 0x19 - MIC2 (Port-F) - 0x01971C3E, - 0x01971D10, - 0x01971EA1, - 0x01971F04, - //Pin widget 0x1A - LINE1 (Port-C) - 0x01A71CF0, - 0x01A71D11, - 0x01A71E11, - 0x01A71F41, - //Pin widget 0x1B - LINE2 (Port-E) - 0x01B71C40, - 0x01B71D10, - 0x01B71EA1, - 0x01B71F03, - //Pin widget 0x1D - PC-BEEP - 0x01D71C01, - 0x01D71D00, - 0x01D71E60, - 0x01D71F40, - //Pin widget 0x1E - S/PDIF-OUT - 0x01E71CF0, - 0x01E71D11, - 0x01E71E11, - 0x01E71F41, - //Pin widget 0x1F - S/PDIF-IN - 0x01F71CF0, - 0x01F71D11, - 0x01F71E11, - 0x01F71F41, - //Pin widget 0x21 - HP-OUT (Port-I) - 0x02171C2F, - 0x02171D10, - 0x02171E21, - 0x02171F04, - //Pin widget 0x29 - I2S-IN - 0x02971CF0, - 0x02971D11, - 0x02971E11, - 0x02971F41, - - //Widget node 0x20 - 0 FAKE JD unplug - 0x02050008, - 0x0204A80F, - 0x02050008, - 0x0204A80F, - //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of= NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14) - 0x0205006B, - 0x02044260, - 0x0205006B, - 0x02044260, - //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700 - 0x05B50010, - 0x05B45C1D, - 0x0205006F, - 0x02040F8B, //Zeek, 0F8Bh - //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent co= ntrol - 0x02050045, - 0x02045089, - 0x0205004A, - 0x0204201B, - //Widget node 0x20 - 4 From JD detect - 0x02050008, - 0x0204A807, - 0x02050008, - 0x0204A807, - //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first - 0x02050090, - 0x02040424, - 0x00171620, - 0x00171720, - - 0x00171520, - 0x01770740, - 0x01770740, - 0x01770740, - - - //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove ALC= 1305 EQ setting - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040000, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400CF, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02045548, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003F, - 0x02050028, - 0x02041000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040600, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FFD0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040080, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02040DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x0204005D, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040442, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040005, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040006, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040008, - 0x02050028, - 0x0204B000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204002E, - 0x02050028, - 0x02040800, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C3, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204D4A0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400CC, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204400A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x020400C1, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040320, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040039, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003B, - 0x02050028, - 0x0204FFFF, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FC20, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x02040006, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x020400C0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FCA0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FCE0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FCF0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040080, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040880, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FCE0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FCA0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003C, - 0x02050028, - 0x0204FC20, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x02040006, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040080, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C0, - 0x02050028, - 0x020401F0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C1, - 0x02050028, - 0x0204C1C7, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C2, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C3, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C4, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C5, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C6, - 0x02050028, - 0x020403E1, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C7, - 0x02050028, - 0x02040F5A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C8, - 0x02050028, - 0x02041E1E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400C9, - 0x02050028, - 0x0204083F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CA, - 0x02050028, - 0x020401F0, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CB, - 0x02050028, - 0x0204C1C7, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CC, - 0x02050028, - 0x02041C00, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CD, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CE, - 0x02050028, - 0x02040200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400CF, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D0, - 0x02050028, - 0x020403E1, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D1, - 0x02050028, - 0x02040F5A, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D2, - 0x02050028, - 0x02041E1E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x020400D3, - 0x02050028, - 0x0204083F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040062, - 0x02050028, - 0x02048000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040063, - 0x02050028, - 0x02045F5F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040064, - 0x02050028, - 0x02042000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040065, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040066, - 0x02050028, - 0x02044004, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040067, - 0x02050028, - 0x02040802, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040068, - 0x02050028, - 0x0204890F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040069, - 0x02050028, - 0x0204E021, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040070, - 0x02050028, - 0x02048012, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040071, - 0x02050028, - 0x02043450, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040072, - 0x02050028, - 0x02040123, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040073, - 0x02050028, - 0x02044543, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040074, - 0x02050028, - 0x02042100, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040075, - 0x02050028, - 0x02044321, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040076, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040050, - 0x02050028, - 0x02048200, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040051, - 0x02050028, - 0x02040707, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040052, - 0x02050028, - 0x02044090, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006A, - 0x02050028, - 0x02040090, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204006C, - 0x02050028, - 0x0204721F, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040012, - 0x02050028, - 0x0204DFDF, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204009E, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040004, - 0x02050028, - 0x02040500, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040060, - 0x02050028, - 0x02042213, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003A, - 0x02050028, - 0x02041DFE, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204003F, - 0x02050028, - 0x02043000, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040040, - 0x02050028, - 0x0204000C, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x02040046, - 0x02050028, - 0x0204C22E, - 0x02050029, - 0x0204B024, - - 0x02050024, - 0x02040010, - 0x02050026, - 0x0204004B, - 0x02050028, - 0x02040000, - 0x02050029, - 0x0204B024 -); - - // // WHL codecs verb tables // @@ -3009,6 +2051,3 @@ HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =3D HDAUDIO_= VERB_TABLE_INIT ( 0x02050029, 0x0204B024 ); // WhlHdaVerbTableAlc700 - -#endif // _PCH_HDA_VERB_TABLES_H_ - diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PeiHdaVerbTableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/P= eiHdaVerbTableLib/PeiHdaVerbTableLib.c index b8afd791f0..46cfe9566c 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.c @@ -13,7 +13,12 @@ #include #include #include -#include "PchHdaVerbTables.h" + +extern HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio; +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc274; +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc700; +extern HDAUDIO_VERB_TABLE HdaVerbTableAlc701; +extern HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700; =20 /** Add verb table helper function. diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c index 3e44c6cc29..e7e5ff5b1a 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPchPolicyUpdate.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPchPolicyUpdate.c @@ -24,7 +24,6 @@ #include #include #include -#include #include =20 VOID @@ -275,7 +274,6 @@ UpdatePeiPchPolicy ( EFI_STATUS Status; UINT8 Index; DMI_HW_WIDTH_CONTROL *DmiHaAWC; - UINT16 LpcDid; PCH_GENERAL_CONFIG *PchGeneralConfig; PCH_PCIE_CONFIG *PcieRpConfig; PCH_SATA_CONFIG *SataConfig; @@ -295,7 +293,6 @@ UpdatePeiPchPolicy ( USB_CONFIG *UsbConfig; PCH_ESPI_CONFIG *EspiConfig; PCH_CNVI_CONFIG *CnviConfig; - PEI_TBT_POLICY *PeiTbtPolicy; SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; =20 Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (V= OID *) &PchGeneralConfig); @@ -345,9 +342,6 @@ UpdatePeiPchPolicy ( ); ASSERT_EFI_ERROR (Status); =20 - PeiTbtPolicy =3D NULL; - LpcDid =3D PchGetLpcDid (); - DmiConfig->PwrOptEnable =3D TRUE; PmConfig->PchSlpS3MinAssert =3D 0; PmConfig->PchSlpS4MinAssert =3D 0; diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoardP= kg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c index 3dc455ab29..0bdd503e2c 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSaPolicyUpdatePreMem.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSaPolicyUpdatePreMem.c @@ -1,9 +1,10 @@ /** @file -Do Platform Stage System Agent initialization. + Platform Stage System Agent initialization. =20 =20 Copyright (c) 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent + **/ =20 #include "PeiSaPolicyUpdate.h" @@ -26,7 +27,7 @@ Do Platform Stage System Agent initialization. /// Memory Reserved should be between 125% to 150% of the Current required= memory /// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resum= e issues. /// -GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTy= peInformation[] =3D { +GLOBAL_REMOVE_IF_UNREFERENCED STATIC EFI_MEMORY_TYPE_INFORMATION mDefaultM= emoryTypeInformation[] =3D { { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory= Size) }, // ASL { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize= ) }, // ACPI NVS (including S3 related) { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz= e) }, // BIOS Reserved (including S3 related) @@ -35,7 +36,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION= mDefaultMemoryTypeInfo { EfiMaxMemoryType, 0 } }; =20 - /** UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization =20 @@ -57,7 +57,6 @@ UpdatePeiSaPolicyPreMem ( UINTN DataSize; EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; EFI_BOOT_MODE BootMode; - UINT8 MorControl; UINT32 TraceHubTotalMemSize; GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig =3D NULL; MEMORY_CONFIGURATION *MemConfig =3D NULL; @@ -67,15 +66,9 @@ UpdatePeiSaPolicyPreMem ( OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig =3D NULL; VTD_CONFIG *Vtd =3D NULL; UINT32 ProcessorTraceTotalMemSize; - UINT16 AdjustedMmioSize; - CPU_FAMILY CpuFamilyId; - CPU_STEPPING CpuStepping; =20 TraceHubTotalMemSize =3D 0; ProcessorTraceTotalMemSize =3D 0; - AdjustedMmioSize =3D PcdGet16 (PcdSaMiscMmioSizeAdjustment); - CpuFamilyId =3D GetCpuFamily(); - CpuStepping =3D GetCpuStepping(); =20 DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdateP= eiSaPolicyPreMem\n")); =20 @@ -106,7 +99,6 @@ UpdatePeiSaPolicyPreMem ( Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (= VOID *)&Vtd); ASSERT_EFI_ERROR(Status); =20 - RcompData =3D MemConfigNoCrc->RcompData; =20 // @@ -124,7 +116,6 @@ UpdatePeiSaPolicyPreMem ( ASSERT_EFI_ERROR(Status); =20 MiscPeiPreMemConfig->S3DataPtr =3D NULL; - MorControl =3D 0; MiscPeiPreMemConfig->UserBd =3D 0; // It's a CRB mobile board by default= (btCRBMB) =20 PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform)= ); diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Bo= ardInitLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/= BoardInitLib.c index 2bba58eed3..09bf3bccfc 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInit= Lib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInit= Lib.c @@ -227,10 +227,6 @@ InitCommonPlatformPcd ( ) { PCD64_BLOB Data64; - TBT_INFO_HOB *TbtInfoHob =3D NULL; - - TbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid); - =20 // // Enable EC SMI# for SMI diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/WhiskeylakeOpe= nBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c index 978e367cda..5fc61861a6 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmMultiBoardAcpiSupportLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmMultiBoardAcpiSupportLib.c @@ -16,7 +16,7 @@ #include #include =20 -#include +#include =20 EFI_STATUS EFIAPI diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c b/Platform/Intel/Whiskeylak= eOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEn= ableLib.c index 97a3fae51b..6dc47984da 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c @@ -15,7 +15,7 @@ #include #include =20 -#include +#include =20 EFI_STATUS EFIAPI diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardFuncInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whis= keylakeURvp/Library/BoardInitLib/BoardFuncInit.c index 5104329825..b8c69166ed 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFuncInit.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFuncInit.c @@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 -#include "BoardInitLib.h" #include "BoardFunc.h" =20 /** diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardFuncInitPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPk= g/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c index 3a42a9bd03..1944a02bf1 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFuncInitPreMem.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFuncInitPreMem.c @@ -6,7 +6,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 -#include "BoardInitLib.h" #include // // Null function for nothing GOP VBT update. diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c index 458a73f892..5305ec7f7c 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardPchInitPreMemLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardPchInitPreMemLib.c @@ -1,17 +1,17 @@ /** @file - Source code for the board PCH configuration Pcd init functions for Pre-Mm= eory Init phase. + Source code for the board PCH configuration Pcd init functions for Pre-Me= mory Init phase. =20 =20 Copyright (c) 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 -#include "BoardInitLib.h" +#include "WhiskeylakeURvpInit.h" #include #include #include // for USB 20 AFE & Root Port Clk = Info. -#include "GpioTableWhlUDdr4PreMem.h" #include +#include =20 /** Board Root Port Clock Info configuration init function for PEI pre-memor= y phase. @@ -346,11 +346,11 @@ GpioTablePreMemInit ( switch (BoardId) { case BoardIdWhiskeyLakeRvp: PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableWhlUDdr4PreMem= ); - PcdSet16S (PcdBoardGpioTablePreMemSize, sizeof (mGpioTableWhlUDdr4Pr= eMem) / sizeof (GPIO_INIT_CONFIG)); + PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTableWhlUDdr4PreMemSize= ); PcdSet32S (PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableWhl= UDdr4WwanOnEarlyPreMem); - PcdSet16S (PcdBoardGpioTableWwanOnEarlyPreMemSize, sizeof (mGpioTabl= eWhlUDdr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG)); + PcdSet16S (PcdBoardGpioTableWwanOnEarlyPreMemSize, mGpioTableWhlUDdr= 4WwanOnEarlyPreMemSize); PcdSet32S (PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableWh= lUDdr4WwanOffEarlyPreMem); - PcdSet16S (PcdBoardGpioTableWwanOffEarlyPreMemSize, sizeof (mGpioTab= leWhlUDdr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG)); + PcdSet16S (PcdBoardGpioTableWwanOffEarlyPreMemSize, mGpioTableWhlUDd= r4WwanOffEarlyPreMemSize); break; =20 default: diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardP= kg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c index 17f12c117d..6c3425b544 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardSaInitPreMemLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardSaInitPreMemLib.c @@ -6,11 +6,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 -#include "BoardInitLib.h" #include "BoardSaConfigPreMem.h" +#include "SaPolicyCommon.h" +#include "WhiskeylakeURvpInit.h" #include #include -#include "SaPolicyCommon.h" =20 // // Display DDI settings for WHL ERB @@ -74,10 +74,8 @@ MrcConfigInit ( ) { CPU_FAMILY CpuFamilyId; - CPU_STEPPING CpuStepping; =20 CpuFamilyId =3D GetCpuFamily(); - CpuStepping =3D GetCpuStepping(); =20 if (CpuFamilyId =3D=3D EnumCpuCflDtHalo) { PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE); diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/GpioTableDefault.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/W= hiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.c similarity index 98% rename from Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/= BoardInitLib/GpioTableDefault.h rename to Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Bo= ardInitLib/GpioTableDefault.c index a943d5bd04..e495965a5f 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableDefault.h +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableDefault.c @@ -1,14 +1,10 @@ /** @file GPIO definition table =20 - Copyright (c) 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 -#ifndef _GPIO_TABLE_DEFAULT_H_ -#define _GPIO_TABLE_DEFAULT_H_ - #include #include #include @@ -18,8 +14,7 @@ // // CNL U DRR4 Board GPIO table configuration is used as default // - -GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableDefault[] =3D +GPIO_INIT_CONFIG mGpioTableDefault[] =3D { // Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, = GPIRoutConfig, PadRstCfg, Term, //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, @@ -215,11 +210,4 @@ GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTa= bleDefault[] =3D //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LANPHY_EN {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDir= Default, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd= 20K }}, // 20K PD for PECI }; - -GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTablePreMemDefault[] = =3D -{ - {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of= Table -}; - -#endif - +UINT16 mGpioTableDefaultSize =3D sizeof (mGpioTableDefault) / sizeof (GPIO= _INIT_CONFIG); diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/GpioTableWhlUDdr4.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/= WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhiskeylakeUDdr4Rvp.c similarity index 98% rename from Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/= BoardInitLib/GpioTableWhlUDdr4.h rename to Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Bo= ardInitLib/GpioTableWhiskeylakeUDdr4Rvp.c index 86b7cb3717..a082b1ceee 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableWhlUDdr4.h +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableWhiskeylakeUDdr4Rvp.c @@ -1,19 +1,16 @@ /** @file - GPIO definition table for WhiskeyLake U Ddr4 RVP - + GPIO definition table for Whiskey Lake U DDR4 RVP =20 Copyright (c) 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent + **/ =20 -#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ -#define _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ - #include #include #include =20 -static GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =3D +GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =3D { // Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, = GPIRoutConfig, PadRstCfg, Term, //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, @@ -220,8 +217,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =3D //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LANPHY_EN {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDir= Default, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd= 20K }}, // 20K PD for PECI }; +UINT16 mGpioTableWhlUDdr4_0Size =3D sizeof (mGpioTableWhlUDdr4_0) / sizeof= (GPIO_INIT_CONFIG); =20 -static GPIO_INIT_CONFIG mGpioTableCflUDdr4[] =3D { +GPIO_INIT_CONFIG mGpioTableCflUDdr4[] =3D { // Pmode, GPI_IS, GpioD= ir, GPIOTxState, RxEvCfg/GPIRoutConfig, PadRstCfg, = Term, // WiGig start {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, Gpio= DirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, G= pioTermWpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U @@ -249,8 +247,9 @@ static GPIO_INIT_CONFIG mGpioTableCflUDdr4[] =3D { {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, G= pioTermNone }} //Unused so disabled / Not used on CNL U // Unused end }; +UINT16 mGpioTableCflUDdr4Size =3D sizeof (mGpioTableCflUDdr4) / sizeof (GP= IO_INIT_CONFIG); =20 -static GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] =3D { +GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] =3D { // Pmode, GPI_IS, GpioD= ir, GPIOTxState, RxEvCfg/GPIRoutConfig, PadRstCfg, = Term, // WiGig start {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTerm= Wpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U @@ -278,7 +277,4 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] =3D { {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTerm= Wpu20K }} //Unused so disabled / WF_CLK_EN on CNL U // Unused end }; - - -#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ - +UINT16 mGpioTableWhlUDdr4Size =3D sizeof (mGpioTableWhlUDdr4) / sizeof (GP= IO_INIT_CONFIG); diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/GpioTableWhlUDdr4PreMem.h b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.c similarity index 84% rename from Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/= BoardInitLib/GpioTableWhlUDdr4PreMem.h rename to Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Bo= ardInitLib/GpioTableWhlUDdr4PreMem.c index 01a6599564..d159f4bd5e 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableWhlUDdr4PreMem.h +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableWhlUDdr4PreMem.c @@ -1,27 +1,25 @@ /** @file - GPIO definition table for WhiskeyLake U Ddr4 RVP Pre-Memory + GPIO definition table for Whiskey Lake U DDR4 RVP Pre-Memory =20 =20 Copyright (c) 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 -#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ -#define _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ - #include #include #include =20 -static GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =3D +GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =3D { {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R= ST_N {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_P= WREN_N {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_RST_N {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_PWREN_N }; +UINT16 mGpioTableWhlUDdr4PreMemSize =3D sizeof (mGpioTableWhlUDdr4PreMem) = / sizeof (GPIO_INIT_CONFIG); =20 -static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =3D +GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =3D { // do not reset SLOT1 due to TR AIC card cannot be reset in S3/S4 resume. //{GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1= _RST_N @@ -29,9 +27,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =3D {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_RST_N {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_PWREN_N }; +UINT16 mGpioTableWhlTbtRvpPreMemSize =3D sizeof (mGpioTableWhlTbtRvpPreMem= ) / sizeof (GPIO_INIT_CONFIG); =20 - -static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =3D +GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =3D { // Turn on WWAN power and de-assert reset pins by default {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu2= 0K, GpioPadConfigUnlock}}, //WWAN_WAKE_N @@ -42,8 +40,9 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreM= em[] =3D {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_DISABLE_N }; +UINT16 mGpioTableWhlUDdr4WwanOnEarlyPreMemSize =3D sizeof (mGpioTableWhlUD= dr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG); =20 -static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =3D +GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =3D { // Assert reset pins and then turn off WWAN power {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu2= 0K, GpioPadConfigUnlock}}, //WWAN_WAKE_N @@ -54,6 +53,4 @@ static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPre= Mem[] =3D {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_DISABLE_N }; - -#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ - +UINT16 mGpioTableWhlUDdr4WwanOffEarlyPreMemSize =3D sizeof (mGpioTableWhlU= Ddr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG); diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpe= nBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c index 965110a5a5..915dadbf8c 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPostMemLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPostMemLib.c @@ -14,7 +14,7 @@ #include #include =20 -#include +#include =20 EFI_STATUS EFIAPI diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpen= BoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c index a2a6efe506..744864f98f 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPreMemLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPreMemLib.c @@ -14,7 +14,7 @@ #include #include =20 -#include +#include =20 EFI_STATUS EFIAPI diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiWhiskeylakeURvpDetect.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c index 0adbed7f53..98aeff519d 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpDetect.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpDetect.c @@ -27,7 +27,7 @@ #include #include =20 -#include "PeiWhiskeylakeURvpInitLib.h" +#include "WhiskeylakeURvpInit.h" =20 #include #include diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c b/Platform/Intel/Whiskeyla= keOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitP= ostMemLib.c index 80b0a97612..81e8df503b 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpInitPostMemLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpInitPostMemLib.c @@ -25,14 +25,12 @@ #include #include #include -#include "PeiWhiskeylakeURvpInitLib.h" -#include "GpioTableDefault.h" -#include "GpioTableWhlUDdr4.h" #include #include #include #include #include +#include "WhiskeylakeURvpInit.h" =20 EFI_STATUS BoardFunctionInit( @@ -49,7 +47,7 @@ GPIO init function for PEI post memory phase. EFI_STATUS BoardGpioInit( IN UINT16 BoardId -) + ) { // // GPIO Table Init. @@ -57,16 +55,16 @@ BoardGpioInit( switch (BoardId) { =20 case BoardIdWhiskeyLakeRvp: - PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableWhlUDdr4_0); - PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableWhlUDdr4_0) / size= of(GPIO_INIT_CONFIG)); - PcdSet32S(PcdBoardGpioTable2, (UINTN)mGpioTableWhlUDdr4); - PcdSet16S(PcdBoardGpioTable2Size, sizeof(mGpioTableWhlUDdr4) / sizeo= f(GPIO_INIT_CONFIG)); + PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableWhlUDdr4_0); + PcdSet16S (PcdBoardGpioTableSize, mGpioTableWhlUDdr4_0Size); + PcdSet32S (PcdBoardGpioTable2, (UINTN) mGpioTableWhlUDdr4); + PcdSet16S (PcdBoardGpioTable2Size, mGpioTableWhlUDdr4Size); break; =20 default: - DEBUG((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...\= n")); - PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableDefault); - PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableDefault) / sizeof(= GPIO_INIT_CONFIG)); + DEBUG ((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...= \n")); + PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableDefault); + PcdSet16S (PcdBoardGpioTableSize, mGpioTableDefaultSize); break; } =20 @@ -148,31 +146,56 @@ BoardSecurityInit ( } =20 /** -WhiskeyLake board configuration init function for PEI post memory phase. + Board configuration initialization in the post-memory boot phase. =20 -@param[in] Content pointer to the buffer contain init information for bo= ard init. + @retval EFI_SUCCESS The function completed successfully. + @retval Others An error occurred during board configura= tion initialization. =20 -@retval EFI_SUCCESS The function completed successfully. -@retval EFI_INVALID_PARAMETER The parameter is NULL. **/ EFI_STATUS -BoardConfigInit( +BoardConfigInit ( VOID -) + ) { EFI_STATUS Status; + EFI_STATUS Status2; UINT16 BoardId; =20 + Status =3D EFI_SUCCESS; BoardId =3D BoardIdWhiskeyLakeRvp; =20 - Status =3D BoardGpioInit(BoardId); - Status =3D TouchPanelGpioInit(BoardId); - Status =3D HdaVerbTableInit(BoardId); - Status =3D BoardMiscInit(BoardId); - Status =3D BoardFunctionInit(BoardId); - Status =3D BoardSecurityInit(BoardId); + Status2 =3D BoardGpioInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D TouchPanelGpioInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D HdaVerbTableInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D BoardMiscInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D BoardFunctionInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D BoardSecurityInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } =20 - return EFI_SUCCESS; + return Status; } =20 //@todo Review this functionality and if it is required for WHL SDS diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c b/Platform/Intel/Whiskeylak= eOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPr= eMemLib.c index 519a5be216..0ce77728d0 100644 --- a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpInitPreMemLib.c +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpInitPreMemLib.c @@ -27,7 +27,7 @@ #include #include =20 -#include "PeiWhiskeylakeURvpInitLib.h" +#include "WhiskeylakeURvpInit.h" #include #include #include @@ -274,36 +274,81 @@ EarlyPlatformPchInit( } =20 /** -Board init function for PEI pre-memory phase. + Board configuration initialization in the pre-memory boot phase. =20 -@param Content pointer to the buffer contain init information for board = init. + @retval EFI_SUCCESS The function completed successfully. + @retval Others An error occurred during board configura= tion initialization. =20 -@retval EFI_SUCCESS The function completed successfully. -@retval EFI_INVALID_PARAMETER The parameter is NULL. **/ EFI_STATUS -BoardConfigInitPreMem( +BoardConfigInitPreMem ( VOID -) + ) { EFI_STATUS Status; + EFI_STATUS Status2; UINT16 BoardId; =20 + Status =3D EFI_SUCCESS; BoardId =3D BoardIdWhiskeyLakeRvp; =20 - Status =3D MrcConfigInit(BoardId); - Status =3D SaGpioConfigInit(BoardId); - Status =3D SaMiscConfigInit(BoardId); - Status =3D RootPortClkInfoInit(BoardId); - Status =3D UsbConfigInit(BoardId); - Status =3D GpioGroupTierInit(BoardId); - Status =3D GpioTablePreMemInit(BoardId); - Status =3D PchPmConfigInit(BoardId); - Status =3D BoardMiscInitPreMem(BoardId); - Status =3D SaDisplayConfigInit(BoardId); - Status =3D BoardFunctionInitPreMem(BoardId); + Status2 =3D MrcConfigInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D SaGpioConfigInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D SaMiscConfigInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D RootPortClkInfoInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D UsbConfigInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D GpioGroupTierInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D GpioTablePreMemInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D PchPmConfigInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D BoardMiscInitPreMem (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D SaDisplayConfigInit (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } + Status2 =3D BoardFunctionInitPreMem (BoardId); + if (EFI_ERROR (Status2)) { + Status =3D Status2; + ASSERT_EFI_ERROR (Status); + } =20 - return EFI_SUCCESS; + return Status; } =20 /** @@ -328,7 +373,6 @@ PlatformInitPreMemCallBack( EFI_STATUS Status; UINT16 ABase; UINT8 FwConfig; - UINT8 SynchDelay; =20 // // Init Board Config Pcd. @@ -337,7 +381,6 @@ PlatformInitPreMemCallBack( =20 DEBUG((DEBUG_ERROR, "Fail to get System Configuration and set the config= uration to production mode!\n")); FwConfig =3D FwConfigProduction; - SynchDelay =3D 0; PcdSetBoolS(PcdPcieWwanEnable, FALSE); PcdSetBoolS(PcdWwanResetWorkaround, FALSE); =20 @@ -586,18 +629,16 @@ WhiskeylakeURvpBoardDebugInit ( VOID ) { - UINT64 LpcBaseAddress; - /// /// LPC I/O Configuration /// - PchLpcIoDecodeRangesSet( + PchLpcIoDecodeRangesSet ( (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) | (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) | (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA) - ); + ); =20 - PchLpcIoEnableDecodingSet( + PchLpcIoEnableDecodingSet ( B_LPC_CFG_IOE_ME2 | B_LPC_CFG_IOE_SE | B_LPC_CFG_IOE_ME1 | @@ -608,18 +649,7 @@ WhiskeylakeURvpBoardDebugInit ( B_LPC_CFG_IOE_PPE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE - ); - - /// - /// Enable LPC IO decode for EC access - /// - LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS( - DEFAULT_PCI_SEGMENT_NUMBER_PCH, - DEFAULT_PCI_BUS_NUMBER_PCH, - PCI_DEVICE_NUMBER_PCH_LPC, - PCI_FUNCTION_NUMBER_PCH_LPC, - 0 - ); + ); =20 return EFI_SUCCESS; } --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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