From nobody Fri Dec 19 21:48:54 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45909+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45909+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001031; cv=none; d=zoho.com; s=zohoarc; b=TZaTME+XO4l75KQ3VcTAOme/tNnvzmNxzKtTt2Np8uz78kdl2yT/mqwe8nBwQOb6aaOgiALdcV8SinsjabbeGKMrt8qDj13qSdo+oOOcOZmBCpNl8PaTGOzp369hIjQSh6lgkHstm1NEfCIAb3xc8lldGi7MWKQvJLGusEQbYgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001031; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=R11r2kA6QcBPWz22+J3G+2h3R4CbCkFKA8faTZO8P0M=; b=MjMudKA4z+IYxxgqnWI3tCfiZI0vdIqv2QTMR3OBX6PxvcE8wpqpkzGrSl3L3chtp9QScW6BO231Mwi8zu4glVS0tDdabos7V7bFq5nGGNt8LK0jEDU8KkAS7f5OGjMpXPvOfwnuB/432XNRnobUFlGmuVZV5cBHG3KYDbZBDA4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45909+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156600103135816.26224535877384; Fri, 16 Aug 2019 17:17:11 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:10 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319355" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:58 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers Date: Fri, 16 Aug 2019 17:15:58 -0700 Message-Id: <20190817001603.30632-33-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001031; bh=cYu8E+YsH/x6Ps9C73up11gGGA1PnpltXrs8XfKb+mk=; h=Cc:Date:From:Reply-To:Subject:To; b=xVV2JIwTkX1kUnyxAZVkjDIJp+U0AbP8fyEumC3wMp9C1j6goUE8ALeaY4rGiASLII1 rP0VH9EBIwsncZkJOUjQWWvAXOaQjai4cJ8blwn/e+kpGq9tPVxxj6VlkZOyMYVWSFAV0 2SaGHtawcAj0GDPnAeiqrJAeOxvbzKKhPlE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 Header files for the WhiskeylakeURvp board instance. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatform= HookLib.h | 131 ++++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatform= Lib.h | 40 ++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoa= rdConfig.h | 105 ++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformInf= o.h | 44 +++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whiskeylake= URvpId.h | 12 ++ 5 files changed, 332 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /PeiPlatformHookLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeU= Rvp/Include/PeiPlatformHookLib.h new file mode 100644 index 0000000000..bd849b9ee2 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPla= tformHookLib.h @@ -0,0 +1,131 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PLATFORM_HOOK_LIB_H_ +#define _PEI_PLATFORM_HOOK_LIB_H_ + +#include +#include +#include + + +//EC Command to provide one byte of debug indication +#define BSSB_DEBUG_INDICATION 0xAE +/** + Configure EC for specific devices + + @param[in] PchLan - The PchLan of PCH_SETUP variable. + @param[in] BootMode - The current boot mode. +**/ +VOID +EcInit ( + IN UINT8 PchLan, + IN EFI_BOOT_MODE BootMode + ); + +/** + Checks if Premium PMIC present + + @retval TRUE if present + @retval FALSE it discrete/other PMIC +**/ +BOOLEAN +IsPremiumPmicPresent ( + VOID + ); + +/** + Pmic Programming to supprort LPAL Feature + + @retval NONE +**/ +VOID +PremiumPmicDisableSlpS0Voltage ( + VOID + ); + +/** +Pmic Programming to supprort LPAL Feature + @retval NONE +**/ +VOID +PremiumPmicEnableSlpS0Voltage( + VOID + ); + +/** + Do platform specific programming pre-memory. For example, EC init, Chips= et programming + + @retval Status +**/ +EFI_STATUS +PlatformSpecificInitPreMem ( + VOID + ); + +/** + Do platform specific programming post-memory. + + @retval Status +**/ +EFI_STATUS +PlatformSpecificInit ( + VOID + ); + +/** + Configure GPIO and SIO Before Memory is ready. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitPreMem ( + VOID + ); + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + VOID + ); + +/** +Voltage Margining Routine + +@retval EFI_SUCCESS Operation success +**/ +EFI_STATUS +VoltageMarginingRoutine( + VOID + ); + +/** + Detect recovery mode + + @retval EFI_SUCCESS System in Recovery Mode + @retval EFI_UNSUPPORTED System doesn't support Recovery Mode + @retval EFI_NOT_FOUND System is not in Recovery Mode +**/ +EFI_STATUS +IsRecoveryMode ( + VOID + ); + +/** + Early board Configuration before Memory is ready. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitEarlyPreMem ( + VOID + ); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /PeiPlatformLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/= Include/PeiPlatformLib.h new file mode 100644 index 0000000000..d65586dbb9 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPla= tformLib.h @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PLATFORM_LIB_H_ +#define _PEI_PLATFORM_LIB_H_ + + + +#define PEI_DEVICE_DISABLED 0 +#define PEI_DEVICE_ENABLED 1 + +typedef struct { + UINT8 Register; + UINT32 Value; +} PCH_GPIO_DEV; + +// +// GPIO Initialization Data Structure +// +typedef struct{ + PCH_GPIO_DEV Use_Sel; + PCH_GPIO_DEV Use_Sel2; + PCH_GPIO_DEV Use_Sel3; + PCH_GPIO_DEV Io_Sel; + PCH_GPIO_DEV Io_Sel2; + PCH_GPIO_DEV Io_Sel3; + PCH_GPIO_DEV Lvl; + PCH_GPIO_DEV Lvl2; + PCH_GPIO_DEV Lvl3; + PCH_GPIO_DEV Inv; + PCH_GPIO_DEV Blink; + PCH_GPIO_DEV Rst_Sel; + PCH_GPIO_DEV Rst_Sel2; +} GPIO_INIT_STRUCT; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /PlatformBoardConfig.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whiskeylake= URvp/Include/PlatformBoardConfig.h new file mode 100644 index 0000000000..44b4059f8e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Platfo= rmBoardConfig.h @@ -0,0 +1,105 @@ +/** @file + Header file for Platform Boards Configurations. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_BOARD_CONFIG_H +#define _PLATFORM_BOARD_CONFIG_H + +#include +#include +#include +#include +#include + +#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1) +#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16)= & 0xFFF0)) + +#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001 +#define BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001 +#define BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001 +#define BOARD_NO_BATTERY_SUPPORT 0 +#define BOARD_REAL_BATTERY_SUPPORTED BIT0 +#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1 + +#pragma pack(1) + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header +} BOARD_CONFIG_BLOCK; + +typedef struct { + UINT8 GpioSupport; + UINT32 WakeGpioNo; + UINT8 HoldRstExpanderNo; + UINT32 HoldRstGpioNo; + BOOLEAN HoldRstActive; + UINT8 PwrEnableExpanderNo; + UINT32 PwrEnableGpioNo; + BOOLEAN PwrEnableActive; +} SWITCH_GRAPHIC_GPIO; + +typedef struct { + UINT8 ClkReqNumber : 4; + UINT8 ClkReqSupported : 1; + UINT8 DeviceResetPadActiveHigh : 1; + UINT32 DeviceResetPad; +} ROOT_PORT_CLK_INFO; + +typedef struct { + UINT8 Section; + UINT8 Pin; +} EXPANDER_GPIO_CONFIG; + +typedef enum { + BoardGpioTypePch, + BoardGpioTypeExpander, + BoardGpioTypeNotSupported =3D 0xFF +} BOARD_GPIO_TYPE; + +typedef struct { + UINT8 Type; + UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG + union { + UINT32 Pin; + EXPANDER_GPIO_CONFIG Expander; + } u; +} BOARD_GPIO_CONFIG; + +// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAG= E from PCH RC. +#define NOT_USED 0xFF +#define FREE_RUNNING 0x80 +#define LAN_CLOCK 0x70 +#define PCIE_PEG 0x40 +#define PCIE_PCH 0x00 + +typedef struct { + UINT32 ClockUsage; + UINT32 ClkReqSupported; +} PCIE_CLOCK_CONFIG; + +typedef union { + UINT64 Blob; + BOARD_GPIO_CONFIG BoardGpioConfig; + ROOT_PORT_CLK_INFO Info; + PCIE_CLOCK_CONFIG PcieClock; +} PCD64_BLOB; + +typedef union { + UINT32 Blob; + USB20_AFE Info; +} PCD32_BLOB; + +#ifndef IO_EXPANDER_DISABLED +#define IO_EXPANDER_DISABLED 0xFF +#endif + +#define SPD_DATA_SIZE 512 + +#pragma pack() + +#endif // _PLATFORM_BOARD_CONFIG_H + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /PlatformInfo.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/In= clude/PlatformInfo.h new file mode 100644 index 0000000000..0e0b6c4f6c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Platfo= rmInfo.h @@ -0,0 +1,44 @@ +/** @file + GUID used for Platform Info Data entries in the HOB list. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INFO_H_ +#define _PLATFORM_INFO_H_ + +#pragma pack(1) + +/// +/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h +/// +typedef UINT32 PCH_GPIO_PAD; //Copied from GpioConfig.h (need to change it= based on include) + +typedef struct { +UINT8 Expander; +UINT8 Pin; +UINT16 Reserved; // Reserved for future use +} IO_EXPANDER_PAD; + +typedef union { +PCH_GPIO_PAD PchGpio; +IO_EXPANDER_PAD IoExpGpio; +} GPIO_PAD_CONFIG; + +typedef struct { +UINT8 GpioType; // 0: Disabled (no GPIO support), 1: PCH= , 2: I/O Expander +UINT8 Reserved[3]; // Reserved for future use +GPIO_PAD_CONFIG GpioData; +} PACKED_GPIO_CONFIG; + +typedef union { +PACKED_GPIO_CONFIG PackedGpio; +UINT64 Data64; +} COMMON_GPIO_CONFIG; + +#pragma pack() + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /WhiskeylakeURvpId.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeUR= vp/Include/WhiskeylakeURvpId.h new file mode 100644 index 0000000000..7d44acccc1 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whiske= ylakeURvpId.h @@ -0,0 +1,12 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _WHISKEYLAKE_ERB_ID_H_ +#define _WHISKEYLAKE_ERB_ID_H_ + +#define BoardIdWhiskeyLakeRvp 0x60 +#endif // _WHISKEYLAKE_RVP3_ID_H_ + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45909): https://edk2.groups.io/g/devel/message/45909 Mute This Topic: https://groups.io/mt/32918203/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-