From nobody Fri Dec 19 20:16:06 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45905+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45905+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001019; cv=none; d=zoho.com; s=zohoarc; b=Ec+XjKgTxB70fdyir9JaLGyx1BM+ZeSVe1AurEJlgHl52hR09w2a1NNOjLbpl+ypS9DwTK2OJvXZpxAGCDbFxEAvo1qaxgWWiOPju5A+xCq49Y1HMEq4ijRuJa1EcUTN5FEqm4fUSDlD2PH1J2rOAoI7hZqKlHUJzulURIIFszc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001019; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZPQooGbGHBeoBZsuk67HJCUENmHiR59fFcGifp2AigM=; b=QYFQ+q4wl3gDEtWsdbI9XOe3T1f6UahVAM2NyVBT4NhPbPCWJyn+p8a3llV209Zp7UCENcccSlt0hbnmq7NwSmSrkhpAVDAVcvtghTv4lAd+hNW7maHsBUxBbpA0mtFNl8I62bcIQb6+jiynwXb+DXJBRQatO8SyfGbFJKOPnqk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45905+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156600101956615.237835320601448; Fri, 16 Aug 2019 17:16:59 -0700 (PDT) Return-Path: X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:58 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319331" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:57 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files Date: Fri, 16 Aug 2019 17:15:55 -0700 Message-Id: <20190817001603.30632-30-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001019; bh=Ytp9yrpdNVlR6lNZPecvXen26E+kGhsoOrIqMBYvdqI=; h=Cc:Date:From:Reply-To:Subject:To; b=fAmKM3umK17tWHTOSrYjMQPrNMZR8/CTLVC9T0SIMmSskqTvGOd25VnqpELlmStn8HH FPWkn9SGPy0kpvYI73fEg73pUO/0zpA4njgkeCmhLCJo5fW8lngJibrpcwwyC+bwektHs sbezJpg9SX4sHXj1MFRPuwO845NcpBYKv40= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki --- Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 215 ++++++++= ++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc | 130 ++++++++= ++++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc | 69 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc | 33 +++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc | 37 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc | 21 ++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc | 44 ++++ 7 files changed, 549 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc b/= Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc new file mode 100644 index 0000000000..37c77d8f63 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc @@ -0,0 +1,215 @@ +## @file +# Component description file for the Coffee Lake silicon package DSC file. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFeatureFlag] +gSiPkgTokenSpaceGuid.PcdTraceHubEnable |FALSE +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE +gSiPkgTokenSpaceGuid.PcdSiCsmEnable |FALSE +gSiPkgTokenSpaceGuid.PcdUseHpetTimer |TRUE +gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE +gSiPkgTokenSpaceGuid.PcdAcpiEnable |FALSE +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE +gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE +gSiPkgTokenSpaceGuid.PcdIpuEnable |TRUE +gSiPkgTokenSpaceGuid.PcdGnaEnable |TRUE +gSiPkgTokenSpaceGuid.PcdSaOcEnable |TRUE +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE +gSiPkgTokenSpaceGuid.PcdCflCpuEnable |FALSE +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |TRUE +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE + +[PcdsFixedAtBuild.common] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000 + + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |10 + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |18 + +[PcdsDynamicDefault.common] +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000 + +## Specifies the AP wait loop state during POST phase. +# The value is defined as below. +# 1: Place AP in the Hlt-Loop state. +# 2: Place AP in the Mwait-Loop state. +# 3: Place AP in the Run-Loop state. +# @Prompt The AP wait loop state. +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 +## Specifies the AP target C-state for Mwait during POST phase. +# The default value 0 means C1 state. +# The value is defined as below.

+# @Prompt The specified AP target C-state for Mwait. +gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 + +[Defines] + PLATFORM_NAME =3D CoffeelakeSiliconPkg + PLATFORM_GUID =3D A45CA44C-AB04-4932-A77C-5A7179F66A22 + PLATFORM_VERSION =3D 0.4 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/CoffeelakeSiliconPkg + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + + DEFINE PLATFORM_SI_PACKAGE =3D CoffeelakeSiliconPkg + + # + # Definition for Build Flag + # + !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc + +[LibraryClasses.common] + # + # Entry point + # + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + # + # UEFI & PI + # + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + + S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL= ibNull.inf + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf + + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + SmiHandlerProfileLib|Edk2/MdePkg/Library/SmiHandlerProfileLibNull/SmiHan= dlerProfileLibNull.inf + + # + # Misc + # + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf + PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + MtrrLib|ClientSiliconPkg/Override/UefiCpuPkg/Library/MtrrLib/MtrrLib.inf= # CSPO-0012: RoyalParkOverrideContent + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf + +##########################################################################= ########################### + +# +# Silicon Init Common Library +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +ConfigBlockLib|ClientSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlock= Lib.inf +PchTraceHubInitLib|ClientSiliconPkg/Library/BasePchTraceHubInitLib/BasePch= TraceHubInitLib.inf + +[LibraryClasses.IA32] +# +# PEI phase common +# + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + +##########################################################################= ########################################################### + +# +# Silicon Init Pei Library +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc + +[LibraryClasses.IA32.SEC] + +[LibraryClasses.X64] + # + # DXE phase common + # + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + +# +# Hsti +# + HstiLib|MdePkg/Library/DxeHstiLib/DxeHstiLib.inf + +##########################################################################= ######################### +# +# Silicon Init Dxe Library +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +[LibraryClasses.X64.PEIM] + +[LibraryClasses.X64.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.X64.DXE_SMM_DRIVER] + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableL= ib.inf + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAlloc= ationLib.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + +[LibraryClasses.X64.SMM_CORE] + +[LibraryClasses.X64.UEFI_DRIVER] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.X64.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +[Components.IA32] +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +[Components.X64] +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc b/Sili= con/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc new file mode 100644 index 0000000000..b6d2058669 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc @@ -0,0 +1,130 @@ +## @file +# Silicon build option configuration file. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions] +# Define Build Options both for EDK and EDKII drivers. + +# SA +!if gSiPkgTokenSpaceGuid.PcdPttEnable =3D=3D TRUE + DEFINE PTT_BUILD_OPTION =3D -DPTT_FLAG=3D1 +!else + DEFINE PTT_BUILD_OPTION =3D +!endif + +# +# System Agent +# +!if gSiPkgTokenSpaceGuid.PcdSgEnable =3D=3D TRUE + DEFINE DSC_SG_BUILD_OPTIONS =3D -DSG_SUPPORT=3D1 +!else + DEFINE DSC_SG_BUILD_OPTIONS =3D +!endif + +!if gSiPkgTokenSpaceGuid.PcdBdatEnable =3D=3D TRUE + DEFINE BDAT_BUILD_OPTION =3D -DBDAT_SUPPORT=3D1 +!else + DEFINE BDAT_BUILD_OPTION =3D +!endif + + DEFINE SLE_BUILD_OPTIONS =3D +!if $(TARGET) =3D=3D RELEASE +!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable =3D=3D TRUE + DEFINE DEBUG_BUILD_OPTIONS =3D +!else + # MDEPKG_NDEBUG is introduced for the intention + # of size reduction when compiler optimization is disabled. If MDEPKG_ND= EBUG is + # defined, then debug and assert related macros wrapped by it are the NU= LL implementations. + DEFINE DEBUG_BUILD_OPTIONS =3D -DMDEPKG_NDEBUG +!endif +!else + DEFINE DEBUG_BUILD_OPTIONS =3D +!endif + +!if ($(TARGET) =3D=3D RELEASE) AND (gSiPkgTokenSpaceGuid.PcdSiCatalogDebug= Enable =3D=3D TRUE) + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =3D -DRELEASE_CATALOG +!else + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =3D +!endif + +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL- +!else + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D +!endif + + DEFINE HSLE_BUILD_OPTIONS =3D + +!if gSiPkgTokenSpaceGuid.PcdCflCpuEnable =3D=3D TRUE + DEFINE CPU_FLAGS =3D -DCPU_CFL +!else + DEFINE CPU_FLAGS =3D +!endif + + +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =3D $(BDAT_BUILD_OPTION) $(PTT_BUIL= D_OPTION) $(DEBUG_BUILD_OPTIONS) +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIO= NS) $(DSC_SG_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(CPU_FLAGS) $(HSLE_BUI= LD_OPTIONS) $(RELEASE_CATALOG_BUILD_OPTIONS) $(DSC_TXT_BUILD_OPTIONS) + +!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable =3D=3D TRUE + *_*_X64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +[BuildOptions.Common.EDKII] + +# +# For IA32 Global Build Flag +# + *_*_IA32_PP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI= _SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI + *_*_IA32_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For IA32 Specific Build Flag +# +MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI +MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) + +# +# For X64 Global Build Flag +# + *_*_X64_PP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI= _SPECIFICATION_VERSION=3D0x00010015 + *_*_X64_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For X64 Specific Build Flag +# +MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 +MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For Xcode Specific Build Flag +# +# Override assembly code build order +*_XCODE5_*_*_BUILDRULEORDER =3D nasm S s +# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of VA_ST= ART in undefined way +*_XCODE5_*_CC_FLAGS =3D -Wno-varargs + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection of runtime modules +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096 + GCC: *_GCC*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc b/Silico= n/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc new file mode 100644 index 0000000000..2df08c6d01 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc @@ -0,0 +1,69 @@ +## @file +# Component description file for the Coffee Lake silicon package both PEI= and DXE libraries DSC file. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Set PCH generation according PCD. +# The DEFINE will be used to select PCH library INF file corresponding to = PCH generation +# +DEFINE PCH =3D Cnl + +# +# Cpu +# + CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatformLib= /PeiDxeSmmCpuPlatformLib.inf + CpuMailboxLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/BaseCpuMailboxLibNull/Ba= seCpuMailboxLibNull.inf + +# +# Me +# + +# +# Pch +# + PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCycleD= ecodingLib/PeiDxeSmmPchCycleDecodingLib.inf + PchGbeLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchGbeLib/PeiDxeSmm= PchGbeLib.inf + PchInfoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeS= mmPchInfoLib$(PCH).inf + SataLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmSataLib/PeiDxeSmmSata= Lib$(PCH).inf + PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcieRpLib/Pei= DxeSmmPchPcieRpLib.inf + PchPcrLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcrLib/PeiDxeSmm= PchPcrLib.inf + PmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib= .inf + + PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSbiAccessL= ib/PeiDxeSmmPchSbiAccessLib.inf + GpioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpio= Lib.inf +!if gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable =3D=3D TRUE + PchSerialIoUartLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSerialI= oUartLib/PeiDxeSmmPchSerialIoUartLib.inf +!else + PchSerialIoUartLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchSerialIoUart= LibNull/BasePchSerialIoUartLibNull.inf +!endif + PchSerialIoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSerialIoLib= /PeiDxeSmmPchSerialIoLibCnl.inf + PchEspiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchEspiLib/PeiDxeS= mmPchEspiLib.inf + PchWdtCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchWdtCommonL= ib/PeiDxeSmmPchWdtCommonLib.inf + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/Base= ResetSystemLib.inf + SmbusLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf + BiosLockLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmBiosLockLib/PeiDx= eSmmBiosLockLib.inf + #private + PchPciExpressHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxe= SmmPchPciExpressHelpersLib/PeiDxeSmmPchPciExpressHelpersLib.inf + PchInitCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchI= nitCommonLib/PeiDxeSmmPchInitCommonLib.inf + PchSpiCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BasePchSpiComm= onLib/BasePchSpiCommonLib.inf + GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmGpioPr= ivateLib/PeiDxeSmmGpioPrivateLibCnl.inf + PchPsfPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchP= sfPrivateLib/PeiDxeSmmPchPsfPrivateLib$(PCH).inf + PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPmcPriv= ateLib/PeiDxeSmmPmcPrivateLibCnl.inf + PmcPrivateLibWithS3|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmP= mcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf + PchDmiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchDmiLib/P= eiDxeSmmPchDmiLib.inf + PchDmiWithS3Lib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PeiDxeSmmPchDmiWithS3Lib.inf + SiScheduleResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BaseSiSched= uleResetLib/BaseSiScheduleResetLib.inf + +# +# SA +# + SaPlatformLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiDxeSmmSaPlatf= ormLib/PeiDxeSmmSaPlatformLib.inf + +# +# Memory +# diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc b/Silicon/Inte= l/CoffeelakeSiliconPkg/SiPkgDxe.dsc new file mode 100644 index 0000000000..07677ece1a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc @@ -0,0 +1,33 @@ +## @file +# Component description file for the Coffee Lake silicon package DXE driv= ers. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Common +# + +# +# Pch +# + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf + $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf + + $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf + + $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf + +# +# SystemAgent +# + $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf + +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf +!endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc b/Silicon/I= ntel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc new file mode 100644 index 0000000000..214de06d58 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc @@ -0,0 +1,37 @@ +## @file +# Component description file for the Coffee Lake silicon package DXE libr= aries. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Silicon Init Dxe Library +# + +# +# Common +# +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE + AslUpdateLib|$(PLATFORM_SI_PACKAGE)/Library/DxeAslUpdateLib/DxeAslUpdateL= ib.inf +!else + AslUpdateLib|$(PLATFORM_SI_PACKAGE)/Library/DxeAslUpdateLibNull/DxeAslUpd= ateLibNull.inf +!endif + SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/Base= SiConfigBlockLib.inf + +# +# Pch +# + PchHdaLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/DxePchHdaLib/DxePchH= daLib.inf + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeResetSystemLib/DxeRe= setSystemLib.inf + DxePchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxePchPolicyLib/DxePch= PolicyLib.inf + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BaseGpioHelpers= LibNull/BaseGpioHelpersLibNull.inf + GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/DxeGpioNameB= ufferLib/DxeGpioNameBufferLib.inf + SmmPchPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/SmmPchPrivate= Lib/SmmPchPrivateLib.inf + +# +# SystemAgent +# + DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaPolicyLib/= DxeSaPolicyLib.inf diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc b/Silicon/Inte= l/CoffeelakeSiliconPkg/SiPkgPei.dsc new file mode 100644 index 0000000000..f30c7e0ae1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc @@ -0,0 +1,21 @@ +## @file +# Component description file for theCoffee Lake silicon package PEI drive= rs. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Common +# + +# +# SystemAgent +# + +# +# Cpu +# + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc b/Silicon/I= ntel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc new file mode 100644 index 0000000000..6e244a6ded --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc @@ -0,0 +1,44 @@ +## @file +# Component description file for the Coffee Lake silicon package PEI libr= aries. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Silicon Init Pei Library +# + SiPolicyLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiPolicyLib/PeiSiPolicyLib.= inf + SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/Base= SiConfigBlockLib.inf + StallPpiLib|$(PLATFORM_SI_PACKAGE)/Library/PeiInstallStallPpiLib/PeiStall= PpiLib.inf + +# +# Pch +# + PchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchPolicyLib/PeiPchPol= icyLibCnl.inf +!if gSiPkgTokenSpaceGuid.PcdOcWdtEnable =3D=3D TRUE + OcWdtLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiOcWdtLib/PeiOcWdtLib.inf +!else + OcWdtLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiOcWdtLibNull/PeiOcWdtLibNu= ll.inf +!endif + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiResetSystemLib/PeiRe= setSystemLib.inf + PchResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchResetLib/PeiPchReset= Lib.inf + SpiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiSpiLib/PeiSpiLib.inf + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiGpioHelpersL= ib/PeiGpioHelpersLib.inf + GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiGpioNameB= ufferLib/PeiGpioNameBufferLib.inf + +# +# Me +# + PeiMePolicyLib|$(PLATFORM_SI_PACKAGE)/Me/Library/PeiMePolicyLib/PeiMePoli= cyLib.inf + +# +# SA +# + PeiSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiSaPolicyLib= /PeiSaPolicyLib.inf +# +# Cpu +# + CpuPolicyLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol= icyLib.inf --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45905): https://edk2.groups.io/g/devel/message/45905 Mute This Topic: https://groups.io/mt/32918198/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-