From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45878+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45878+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001011; cv=none; d=zoho.com; s=zohoarc; b=I5cGbistuTyA7+sgIKezMbhEiJKL6d/Z1ELKHGCHKCJSnqdVwVYoxYf7g6361fluq9kJocmrsSoz7N22FAXm54artBli4mnbJgPdIj/i+Hx1mja6siXbcnmqM3q5xV+UFfLe3ytI4GqYD9ES7PilvTB9ftf96WvWnPtoIlEqU88= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001011; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=AV82DOI5/wrg4pb4+Gkw/UMB7cJVmCxXYy47xRSTsDc=; b=BYQ5+apLlfcUBiPNE0NdoNOvY4FqLgMdMXXxf8WlFz7Z/anMzamSpZh4XVuvLPsZuGsN74JVpIxAR+FE6s+yPh1Xsml7JqoPMLdmQv2ECM6tYXnx6O+Yz6qAcSivPBUP6bBeqHUpwWtAOhTzmbGgZqO8oV/n9u3hUwP9KlaBI7Y= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45878+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001011318986.048646157402; Fri, 16 Aug 2019 17:16:51 -0700 (PDT) Return-Path: X-Received: from mga14.intel.com (mga14.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:50 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319224" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:48 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 01/37] CoffeelakeSiliconPkg: Add package and Include headers Date: Fri, 16 Aug 2019 17:15:27 -0700 Message-Id: <20190817001603.30632-2-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001010; bh=zeS6SHbes+0q/+OvZNdVgvN+9YdlDu11Ik/UFXX62IE=; h=Cc:Date:From:Reply-To:Subject:To; b=AgvMiubogCtUkGEDr0j+ZGler6A6uopmIJYsVze1xuFYNN8k7W4m/eShlLwtA9eGYrx 8LY9HQGxPTKzlxo9FI7FC2DhCmxyICwYczxJ/qZG1uQZUchjMtbPEH+T2SN5rsYBMBJCr vAMbYR8damsQ/Y2Zg0j5uFVZhhR3CDAWh/U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Create the CoffeelakeSiliconPkg to provide an initial package for silicon initialization code for Coffee Lake (CFL) and Whiskey Lake (WHL) generation products. * Major areas of functionality are categorized into CPU, Management Engine (ME), Platform Controller Hub (PCH), and System Agent subdirectories. * Common libraries and headers are kept at the root of the package. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone Reviewed-by: Sai Chaganty =20 --- Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec = | 714 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h = | 53 ++ Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h = | 89 +++ Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h = | 291 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h = | 157 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h = | 64 ++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h = | 28 + Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateLib.h = | 123 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h = | 58 ++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h = | 110 +++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h = | 22 + Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h = | 34 + Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h = | 319 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h = | 29 + Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLib.h = | 26 + Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib.h = | 71 ++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h = | 60 ++ Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h = | 55 ++ Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h = | 19 + Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h = | 65 ++ Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h = | 23 + 21 files changed, 2410 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec b/Silicon/Intel/C= offeelakeSiliconPkg/SiPkg.dec new file mode 100644 index 0000000000..fa8c11e93d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkg.dec @@ -0,0 +1,714 @@ +## @file +# Component description file for the Silicon Reference Code. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +DEC_SPECIFICATION =3D 0x00010017 +PACKAGE_NAME =3D SiPkg +PACKAGE_VERSION =3D 0.1 +PACKAGE_GUID =3D F245E276-44A0-46b3-AEB5-9898BBCF008D + +[Includes] + Include + SampleCode/Include + SampleCode/MdeModulePkg/Include + SampleCode/IntelFrameworkPkg/Include + # + # SystemAgent + # + SystemAgent/Include + SystemAgent/MemoryInit/Include + SystemAgent/AcpiTables + # + # Cpu + # + Cpu/Include + # + # Me + # + Me/Include + # + # Pch + # + Pch/Include + +[Guids.common.Private] + # + # PCH + # + gPchDeviceTableHobGuid =3D { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0= x66, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }} + gPchConfigHobGuid =3D { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0= xd9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }} + gGpioLibUnlockHobGuid =3D { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0= xD6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }} + gSiScheduleResetHobGuid =3D { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0= xC1, 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }} + +[Guids] +## +## MdeModulePkg +## +gEfiMemoryTypeInformationGuid =3D {0x4c19049f, 0x4137, 0x4dd3, {0x9c, 0x= 10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}} +gEfiCapsuleVendorGuid =3D {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36= , 0xec, 0xbd, 0x3c, 0x8b, 0xe2}} +gEfiConsoleOutDeviceGuid =3D { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0= x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}} + +## +## IntelFrameworkPkg +## +gEfiSmmPeiSmramMemoryReserveGuid =3D {0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, = 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}} + +## +## Common +## +## Include/ConfigBlock/SiConfig.h +gSiConfigGuid =3D {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x9= 7, 0x38, 0x59, 0xd8 }} +gSiPkgTokenSpaceGuid =3D {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43,= 0x66, 0x99, 0xcb, 0xe4, 0x5b}} + +## Include/SiConfigHob.h +gSiConfigHobGuid =3D {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0x5f,= 0x8f, 0xd7, 0x65, 0x4e}} + +## +## System Agent +## +gSaAcpiTableStorageGuid =3D {0x3c0ed5e2, 0x91ea, 0x4b94, { 0x82, 0xd, 0x= 9d, 0xaf, 0x9a, 0x3b, 0xb4, 0xa2}} +gSaDataHobGuid =3D {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2, 0xc4= , 0x4a, 0x0e, 0xd6, 0xd0}} +gSaConfigHobGuid =3D {0x762fa2e6, 0xea3b, 0x41c8, { 0x8c, 0x52, 0x63, 0x7= 6, 0x6d, 0x70, 0x39, 0xe0}} +gSaPegHobGuid =3D {0x440ab2e5, 0xa3ea, 0x466f, { 0x84, 0x96, 0xdf, 0xb1, = 0x3b, 0x75, 0x29, 0x95}} +gSgAcpiTableStorageGuid =3D {0x8de8964f, 0x2939, 0x4b49, { 0xa3, 0x48, 0= xf6, 0xb2, 0xb2, 0xde, 0x4a, 0x42}} +gSaSsdtAcpiTableStorageGuid =3D {0xca89914d, 0x2317, 0x452e, { 0xb2, 0x4= 5, 0x36, 0xc6, 0xfb, 0x77, 0xa9, 0xc6}} +gPegSsdtAcpiTableStorageGuid =3D {0xE05B8635, 0xE5C0, 0x4D88, { 0xB6, 0x= 29, 0x19, 0xD6, 0xA2, 0xC6, 0xE9, 0x2E}} +gSgAcpiTablePchStorageGuid =3D {0xe3164526, 0x690a, 0x4e0d, { 0xb0, 0x28= , 0xae, 0xa1, 0x6f, 0xe2, 0xbc, 0xf3}} +gSaMiscPeiPreMemConfigGuid =3D {0x4a525577, 0x3469, 0x4f11, { 0x99, 0xcf= , 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}} +gSaMiscPeiConfigGuid =3D {0x1def8e6, 0xe998, 0x4e27, { 0x89, 0x98, 0x9c,= 0xfa, 0xb2, 0x92, 0xbc, 0x50}} +gSaPciePeiPreMemConfigGuid =3D { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, 0x2= 1, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}} +gSaPciePeiConfigGuid =3D { 0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x8= 2, 0x3a, 0x55, 0xc7, 0xb5, 0xb3}} +gGraphicsPeiPreMemConfigGuid =3D { 0x0319c56b, 0xc43a, 0x42f1, { 0x80, 0= xbe, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}} +gGraphicsPeiConfigGuid =3D { 0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e, 0= xa7, 0x04, 0x2a, 0x06, 0x2f, 0x5d}} +gSwitchableGraphicsConfigGuid =3D { 0xc7956998, 0xc065, 0x46c4, { 0x8e, = 0x2f, 0x58, 0x2b, 0x67, 0xeb, 0xbe, 0x2f}} +gCpuTraceHubConfigGuid =3D { 0xf2e17477, 0x93f3, 0x430d, { 0x9e, 0x08, 0x= 3c, 0xcc, 0x6e, 0x2f, 0x6c, 0x4b}} +gMemoryConfigGuid =3D { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1, = 0x97, 0xb8, 0xa1, 0xe4, 0xbf}} +gMemoryConfigNoCrcGuid =3D { 0xc56c73d0, 0x1cdb, 0x4c0c, { 0xa9, 0x57, 0= xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}} +gIpuPreMemConfigGuid =3D { 0x830a222b, 0x3ff5, 0x432e, { 0x9d, 0xd5, 0x4= e, 0xe3, 0xfc, 0xa2, 0xaa, 0xa2}} +gGnaConfigGuid =3D { 0x53e0ef18, 0xb8a8, 0x4795, { 0xa6, 0x6d, 0xe4, 0x7= 7, 0x2c, 0xc3, 0xae, 0x82}} +gVtdConfigGuid =3D { 0x03e5cf63, 0xbebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x5= 4, 0x61, 0x20, 0xf1, 0xc5}} +gGraphicsDxeConfigGuid =3D {0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xd= b, 0x67, 0x16, 0x42, 0x39, 0x24}} +gMiscDxeConfigGuid =3D {0x7ce5f5ef, 0x4ef1, 0x4f9f, {0x8e, 0x29, 0x5f, 0= xf4, 0x5f, 0x2f, 0xd8, 0xaf}} +gPcieDxeConfigGuid =3D {0x1ed2d6f1, 0xa9d2, 0x476e, {0x8e, 0x74, 0xad, 0= xd9, 0x5b, 0x5, 0x10, 0x82}} +gMemoryDxeConfigGuid =3D {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40, 0xf8,= 0x2, 0xd, 0x84, 0x4c, 0x94}} +gVbiosDxeConfigGuid =3D {0x8df0f30a, 0x8156, 0x4897, {0xa2, 0x18, 0x1f, = 0xd3, 0x91, 0xbc, 0x46, 0x26}} +gSaOverclockingPreMemConfigGuid =3D { 0x09ecc29d, 0xdbbe, 0x49fb, { 0xa6= , 0x49, 0x4b, 0xf6, 0x40, 0xe2, 0xeb, 0xd6}} +gFspReservedMemoryResourceHobTsegGuid =3D { 0xd038747c, 0xd00c, 0x4980, = { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}} + +## Include/Guid/AcpiS3Context.h +gEfiAcpiVariableGuid =3D {0xaf9ffd67, 0xec10, 0x488a, {0x9d, 0xfc, 0x6c,= 0xbf, 0x5e, 0xe2, 0x2c, 0x2e}} + +## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as gFspNo= nVolatileStorageHobGuid +gSiMemoryS3DataGuid =3D { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, = 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } } +gSiMemoryInfoDataGuid =3D { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, = 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } } +gSiMemoryPlatformDataGuid =3D { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, = 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } } + +## Include/MrcRmtData.h +gEfiMemorySchemaGuid =3D { 0xCE3F6794, 0x4883, 0x492C, { 0x8D, 0xBA, 0x2F= , 0xC0, 0x98, 0x44, 0x77, 0x10}} +gMrcSchemaListHobGuid =3D { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xCB, 0xEA= , 0xAD, 0x0A, 0x88, 0x86, 0x1B}} + +## Include/SsaCommonConfig.h +gSsaPostcodeHookGuid =3D {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46, 0= x87, 0xE7, 0x9E, 0x6F, 0xBB}} +gSsaBiosVariablesGuid =3D {0x43eeffe8, 0xa978, 0x41dc, {0x9d, 0xb6, 0x54, = 0xc4, 0x27, 0xf2, 0x7e, 0x2a}} +gSsaBiosResultsGuid =3D {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47, 0x9f= , 0xda, 0x27, 0x9d, 0xb6}} +gHobUsageDataGuid =3D {0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x2= 0, 0xfc, 0x7c, 0xe1, 0xf6 }} + +## +## Cpu +## +gSmramCpuDataHeaderGuid =3D {0x5848fd2d, 0xd6af, 0x474b, {0x82, 0x75, 0x= 95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23}} +gCpuAcpiTableStorageGuid =3D {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44, 0= x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}} +gHtBistHobGuid =3D {0xbe644001, 0xe7d4, 0x48b1, {0xb0, 0x96, 0x8b, 0xa0,= 0x47, 0xbc, 0x7a, 0xe7}} +gCpuInitDataHobGuid =3D {0x266e31cc, 0x13c5, 0x4807, {0xb9, 0xdc, 0x39, = 0xa6, 0xba, 0x88, 0xff, 0x1a}} +gEpcBiosDataGuid =3D {0xc60aa7f6, 0xe8d6, 0x4956, {0x8b, 0xa1, 0xfe, 0x2= 6, 0x29, 0x8f, 0x5e, 0x87}} +gCpuSecurityPreMemConfigGuid =3D {0xfd5c346, 0x8260, 0x4067, {0x94, 0x69, = 0xcf, 0x91, 0x68, 0xa3, 0x42, 0x90}} +gCpuConfigLibPreMemConfigGuid =3D {0xfc1c0ec2, 0xc6b4, 0x4f05, {0xbb, 0x85= , 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}} +gCpuSgxConfigGuid =3D {0xc30bc5ac, 0x828a, 0x45ae, {0x83, 0x1b, 0x8e, 0xb,= 0x73, 0x9a, 0xb2, 0xf2}} +gCpuTestConfigGuid =3D {0xd4dba957, 0xd9c, 0x4af2, {0x9d, 0x40, 0x35, 0xa8= , 0x44, 0xe4, 0x93, 0xad}} +gCpuConfigGuid =3D {0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x= 5f, 0x46, 0x53, 0x41}} +gCpuOverclockingPreMemConfigGuid =3D {0x396223b6, 0x6088, 0x44e7, {0x99, 0= xcb, 0xfa, 0x8b, 0x99, 0x3d, 0xed, 0x4c}} +gCpuPidTestConfigGuid =3D {0x2511095f, 0xd49e, 0x4537, {0xa6, 0x60, 0x88, = 0x71, 0x31, 0xd1, 0x53, 0xda}} +gCpuPowerMgmtBasicConfigGuid =3D {0xa021e31d, 0x7c14, 0x47da, {0xb5, 0xec,= 0xca, 0xbb, 0x4d, 0x76, 0xed, 0xc8}} +gCpuPowerMgmtCustomConfigGuid =3D {0x562fa1c8, 0x55ee, 0x4e2f, {0x91, 0xca= , 0x8d, 0x84, 0x50, 0x3, 0x2f, 0xe}} +gCpuPowerMgmtTestConfigGuid =3D {0x5161ed3d, 0x90bf, 0x436f, {0xb8, 0x33, = 0xd7, 0x17, 0x89, 0xb3, 0x48, 0xc1}} + +## +## Me +## +gMePeiPreMemConfigGuid =3D {0x67ed113b, 0xd4ab, 0x43f5, {0x9c, 0x3c, 0x3= 5, 0x44, 0x15, 0xaa, 0x47, 0x5c}} +gMePeiConfigGuid =3D {0x9bad5628, 0x657b, 0x48e3, {0xb1, 0x11, 0xc3, 0xb= 9, 0xeb, 0xea, 0xee, 0x17}} +gMeEopDoneHobGuid =3D {0x247323af, 0xc8f1, 0x4b8c, {0x90, 0x87, 0xaa, 0x4b= , 0xa7, 0xb7, 0x6d, 0x6a}} +gMePreMemPolicyHobGuid =3D {0xe6de74a5, 0x21b, 0x4f78, {0xa3, 0xcd, 0x34, = 0xd6, 0x7e, 0xe4, 0x82, 0xbf}} +gMePolicyHobGuid =3D {0x0341cf17, 0xbc8f, 0x4a20, {0xac, 0x28, 0x6c, 0x3c= , 0x32, 0x4c, 0xd4, 0x17}} + +## +## PCH +## +gEfiSmbusArpMapGuid =3D {0x707be83e, 0x0bf6, 0x40a5, {0xbe, 0x64, 0x34, = 0xc0, 0x3a, 0xa0, 0xb8, 0xe2}} +gIrmtAcpiTableStorageGuid =3D {0x6684d675, 0xee06, 0x49b2, {0x87, 0x6f, = 0x79, 0xc5, 0x8f, 0xdd, 0xa5, 0xb7}} +gPchGlobalResetGuid =3D { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18= , 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }} +gI2c0MasterGuid =3D {0xa121a5db, 0xb0cb, 0x46ec, {0xa0, 0xcb, 0x27, 0xf8= , 0xda, 0x72, 0xd4, 0x0e}} +gI2c1MasterGuid =3D {0x55e3d0f9, 0xc954, 0x422d, {0x9c, 0x4c, 0xcc, 0x46= , 0x12, 0x7c, 0x5b, 0xa8}} +gI2c2MasterGuid =3D {0x9289aa40, 0xdf32, 0x474e, {0xb0, 0x3a, 0xc7, 0x7f= , 0x76, 0xd3, 0x45, 0x21}} +gI2c3MasterGuid =3D {0xd8b2c17f, 0x4117, 0x4166, {0x90, 0x17, 0x01, 0x68= , 0xb4, 0x81, 0xac, 0x18}} +gI2c4MasterGuid =3D {0x513d943d, 0x15d9, 0x4bd0, {0xb1, 0x41, 0x14, 0x50= , 0x2b, 0xbf, 0xa9, 0xf2}} +gI2c5MasterGuid =3D {0x50df382a, 0xb6bf, 0x4435, {0xae, 0xe6, 0x21, 0xf4= , 0x85, 0x7c, 0xa8, 0xb4}} +gChipsetInitHobGuid =3D {0x8c7ee32c, 0x0870, 0x4bfa, {0x84, 0x79, 0x5b, 0x= a5, 0x67, 0xc4, 0xae, 0x5b}} + +gPchGeneralPreMemConfigGuid =3D {0xC65F62FA, 0x52B9, 0x4837, {0x86, 0xEB,= 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}} +gDciPreMemConfigGuid =3D {0xAB4AF366, 0x2250, 0x40C3, {0x92, 0xDB, 0x36= , 0x61, 0xC6, 0x71, 0x3C, 0x5A}} +gWatchDogPreMemConfigGuid =3D {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88, = 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}} +gTraceHubPreMemConfigGuid =3D {0xC26AC3F6, 0xDAD0, 0x4E91, {0xB6, 0xD6, = 0xD8, 0x51, 0x6F, 0x8F, 0x9B, 0x7B}} +gPchTraceHubPreMemConfigGuid =3D {0x8456c11, 0xdb85, 0x4914, {0x8d, 0x1a,= 0xe5, 0xac, 0x64, 0x37, 0xe8, 0x96}} +gPcieRpPreMemConfigGuid =3D {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1, 0= x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}} +gHpetPreMemConfigGuid =3D {0x7C75C0F1, 0xA20F, 0x42EB, {0x83, 0xDE, 0xE8= , 0x58, 0xAB, 0x81, 0xC5, 0xDC}} +gSmbusPreMemConfigGuid =3D {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0x2= 3, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}} +gLpcPreMemConfigGuid =3D {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC6,= 0x30, 0xC6, 0xC4, 0x11, 0x8E}} +gHsioPciePreMemConfigGuid =3D {0xE8FB0C12, 0x0DA1, 0x4A20, {0xB3, 0x36, = 0xFB, 0x75, 0x93, 0x8C, 0xE0, 0x14}} +gHsioSataPreMemConfigGuid =3D {0x732260D0, 0xA5C1, 0x4119, {0xAA, 0x0C, = 0x93, 0xDC, 0xAC, 0x67, 0x0A, 0x31}} +gHsioPreMemConfigGuid =3D {0xbc9e5787, 0x3ddb, 0x4916, {0x8c, 0xcc, 0x82= , 0xb8, 0x9, 0x43, 0xe2, 0xf0}} #deprecated + +gPchGeneralConfigGuid =3D {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0xCA= , 0x4D, 0xE2, 0x95, 0x4B, 0x5D}} +gPcieRpConfigGuid =3D {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0x= DE, 0x10, 0x6D, 0x94, 0x84}} +gSataConfigGuid =3D {0xF5F87B4F, 0xCC3C, 0x408D, {0x89, 0xE3, 0x61, 0xC5= , 0x9C, 0x54, 0x07, 0xC4}} +gIoApicConfigGuid =3D {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, 0x= 68, 0xBA, 0x87, 0x3E, 0x6C}} +gCio2ConfigGuid =3D {0xFBC4C192, 0x789D, 0x4038, {0x90, 0xE1, 0x5E, 0x6D= , 0xFD, 0x52, 0xAF, 0x8A}} +gDmiConfigGuid =3D {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3, 0x42,= 0x9C, 0x4F, 0x17, 0xBD}} +gFlashProtectionConfigGuid =3D {0xD0F71512, 0x9E32, 0x4CC9, {0xA5, 0xA3,= 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8}} +gHdAudioPreMemConfigGuid =3D {0xD38F1E2B, 0x21B3, 0x43D1, {0x9F, 0xA8, 0= xA5, 0xE1, 0x78, 0x73, 0x1E, 0x88}} +gHdAudioConfigGuid =3D {0x7EB3CE7E, 0x82E0, 0x4CD7, {0xBD, 0xE5, 0xB2, 0= xBF, 0x4E, 0x91, 0xC3, 0x4C}} +gHdAudioDxeConfigGuid =3D {0x22EFC2DE, 0x66EB, 0x412D, {0x97, 0x17, 0xE7= , 0x7A, 0xA1, 0x4E, 0x87, 0x76}} +gInterruptConfigGuid =3D {0x09A2B815, 0xBE29, 0x45EF, {0xBF, 0xBF, 0x58,= 0xEA, 0xAC, 0x5E, 0x29, 0x78}} +gIshPreMemConfigGuid =3D {0x7C24E649, 0xC1F0, 0x4CF9, {0x87, 0x96, 0xE7,= 0xA0, 0xEE, 0x34, 0x43, 0xF8}} +gIshConfigGuid =3D {0x433AE2AA, 0xC5A6, 0x46ED, {0x94, 0x19, 0x1E, 0x5D,= 0xB8, 0x1C, 0x57, 0x40}} +gLanConfigGuid =3D {0x4B2DE99E, 0x7517, 0x4D04, {0x8C, 0x02, 0xF1, 0x1A,= 0x59, 0x2B, 0x14, 0x2F}} +gLockDownConfigGuid =3D {0x8A838E0A, 0xA639, 0x46F0, {0xA9, 0xCE, 0x70, = 0xC4, 0x85, 0xFB, 0xA8, 0x0D}} +gP2sbConfigGuid =3D {0x2474DCB8, 0x4BB4, 0x49DA, {0x87, 0x83, 0x7C, 0xD3= , 0xD3, 0x85, 0xFF, 0x07}} +gPmConfigGuid =3D {0x93826157, 0xDC85, 0x4E34, {0xAE, 0xD9, 0x6E, 0xA1, = 0x0D, 0xF9, 0xE3, 0xA7}} +gPort61ConfigGuid =3D {0x59913475, 0x1960, 0x4099, {0x80, 0xEC, 0xAF, 0x= C7, 0xCF, 0x5F, 0x9F, 0xAC}} +gScsConfigGuid =3D {0xF4DE6D52, 0xB5C9, 0x48C0, {0xA0, 0x4A, 0x68, 0x54,= 0x20, 0x94, 0x05, 0xD0}} +gSerialIoConfigGuid =3D {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA, = 0x09, 0xE5, 0x78, 0x3A, 0xDB}} +gSerialIrqConfigGuid =3D {0x251701E7, 0xE266, 0x4623, {0x99, 0x68, 0x73,= 0x8C, 0xD2, 0x23, 0x10, 0x96}} +gSpiConfigGuid =3D {0x150360EF, 0x99BE, 0x4E43, {0x94, 0xBB, 0xBD, 0x40,= 0x26, 0xCA, 0x34, 0x57}} +gEspiConfigGuid =3D {0x60FBF3B8, 0x96D4, 0x4187, {0x84, 0x9E, 0xAA, 0xF7= , 0x5C, 0x4B, 0xE1, 0xE3}} +gThermalConfigGuid =3D {0x4416506D, 0x1197, 0x4722, {0xA5, 0xB4, 0x46, 0= x11, 0xF9, 0x23, 0x9E, 0xAE}} +gUsbConfigGuid =3D {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xFB,= 0xB7, 0x66, 0x8B, 0xDE}} +gPchPcieStorageDetectHobGuid =3D {0xC682F3F4, 0x2F46, 0x495E, {0x98, 0xAA,= 0x43, 0x14, 0x4B, 0xA5, 0xA4, 0x85}} +gCnviConfigGuid =3D {0xE53EBEF7, 0x103D, 0x4A70, {0x9B, 0x6A, 0x73, 0xEE, = 0x5F, 0x4C, 0x8D, 0xF5}} +gHsioConfigGuid =3D {0xE53EBEE7, 0x103D, 0x4A71, {0x9B, 0x6A, 0x74, 0xEE, = 0x5F, 0x4C, 0x8D, 0xF5}} +gPchRstHobGuid =3D {0x4ECA680C, 0x660D, 0x48F8, {0xAA, 0xD8, 0x94, 0xD6, = 0x56, 0x10, 0xF9, 0x86}} +gPchInfoHobGuid =3D {0x99FD5E18, 0xE262, 0x4E6A, {0x82, 0x66, 0x77, 0xD0= , 0x36, 0x5F, 0xD6, 0x3E}} +gGpioDxeConfigGuid =3D {0x06985984, 0xAFA3, 0x429C, {0x80, 0xCD, 0x69, 0= x43, 0xF3, 0x38, 0x31, 0x4D}} + +## +## SecurityPkg +## +## GUID used to "Tcg2PhysicalPresence" variable and "Tcg2PhysicalPresenceF= lags" variable for TPM2 request and response. +# Include/Guid/Tcg2PhysicalPresenceData.h +gEfiTcg2PhysicalPresenceGuid =3D { 0xaeb9c5c1, 0x94f1, 0x4d02, { = 0xbf, 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }} +gTpmDeviceInstanceTpm20PttGuid =3D {0x72cd3a7b, 0xfea5, 0x4f5e, {0= x91, 0x65, 0x4d, 0xd1, 0x21, 0x87, 0xbb, 0x13}} +gTpmDeviceInstanceTpm20PttPtpGuid =3D {0x93d66f66, 0x55da, 0x4f03, {0= x9b, 0x5f, 0x32, 0xcf, 0x9e, 0x54, 0x3b, 0x3a}} +gEfiTrEEPhysicalPresenceGuid =3D {0xf24643c2, 0xc622, 0x494e, {0= x8a, 0x0d, 0x46, 0x32, 0x57, 0x9c, 0x2d, 0x5b}} +gTcoWdtHobGuid =3D { 0x3e405418, 0x0d8c, 0x4f1a, { = 0xb0, 0x55, 0xbe, 0xf9, 0x08, 0x41, 0x46, 0x8d }} + +## +## Pre-Memory Performance +## +gPerfPchPrePolicyGuid =3D {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, 0x= 3E, 0x25, 0xEE, 0x81, 0x92, 0xA4}} +gPerfSiValidateGuid =3D {0x681F96E6, 0xF9CF, 0x464D, {0x97, 0x9A, 0x= B1, 0x11, 0x33, 0xDE, 0x37, 0xA9}} +gPerfPchValidateGuid =3D {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, 0x= 29, 0x0B, 0x38, 0xC5, 0x32, 0x25}} +gPerfAmtValidateGuid =3D {0x9E949422, 0x4A7A, 0x4E41, {0xB0, 0xAB, 0x= 3C, 0x0D, 0x88, 0x0A, 0x00, 0xFF}} +gPerfCpuValidateGuid =3D {0xB760CFCC, 0xDEEF, 0x4C7E, {0x99, 0x5B, 0x= ED, 0xFE, 0xF2, 0x23, 0xB2, 0x09}} +gPerfMeValidateGuid =3D {0x8CF7A498, 0x588D, 0x4D39, {0xBD, 0xAC, 0x= 51, 0x0C, 0x31, 0xAF, 0x45, 0xD0}} +gPerfSaValidateGuid =3D {0xA73B382B, 0x62D4, 0x4A19, {0xBB, 0xF9, 0x= 09, 0x3E, 0xC5, 0xA5, 0x93, 0x11}} +gPerfHeciPreMemGuid =3D {0xD815D922, 0x4994, 0x40B3, {0x97, 0xCC, 0x= 07, 0xF3, 0x7D, 0x42, 0xE7, 0x97}} +gPerfPchPreMemGuid =3D {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A, 0x= 52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}} +gPerfCpuPreMemGuid =3D {0xAC5FCBC6, 0x084D, 0x445D, {0xB3, 0xF3, 0x= CA, 0x16, 0xDE, 0xE9, 0xBB, 0x47}} +gPerfMePreMemGuid =3D {0x6051338E, 0x0FFA, 0x40F7, {0xAF, 0xEF, 0x= AB, 0x86, 0x7A, 0x38, 0xCC, 0xF3}} +gPerfAmtPreMemGuid =3D {0xDB732D50, 0x9BB8, 0x489A, {0xA1, 0xD1, 0x= DD, 0xD2, 0x16, 0x1D, 0x72, 0xB8}} +gPerfAmtPostMemGuid =3D {0x0329D610, 0x4269, 0xD28F, {0x61, 0xBF, 0x= B9, 0xA2, 0xD9, 0xFA, 0x96, 0x93}} +gPerfSaPreMemGuid =3D {0x76F18BDA, 0x2195, 0x4FB6, {0x9A, 0x94, 0x= 0E, 0x0B, 0xAC, 0xDE, 0xEC, 0xAB}} +gPerfEvlGuid =3D {0x8221518B, 0xAC19, 0x4E32, {0xAB, 0x5F, 0x= 00, 0x47, 0x0A, 0x50, 0x69, 0x40}} +gPerfMemGuid =3D {0x2B57B316, 0x5CF7, 0x4847, {0xB0, 0x76, 0x= 6B, 0x5D, 0x23, 0xC3, 0xAA, 0x3E}} + +## +## Post-Memory Performance +## +gPerfPchPostMemGuid =3D {0x70B67A99, 0x5556, 0x4315, {0xB3, 0x05, 0x= D5, 0xDC, 0x4A, 0x35, 0x63, 0x70}} +gPerfSaPostMemGuid =3D {0x9FF0CE92, 0x883F, 0x43DC, {0x8A, 0x07, 0x= E0, 0xCB, 0x6D, 0x56, 0x7D, 0xE0}} +gPerfS3CpuInitPostMemGuid =3D {0x976262C2, 0xD202, 0x4D12, {0x82, 0xAD, 0x= F4, 0xA9, 0x8F, 0x9B, 0x96, 0x01}} +gPerfSaSecLockPostMemGuid =3D {0x272AC110, 0x0B60, 0x4D07, {0xA5, 0x58, 0x= 6D, 0x73, 0xE2, 0x43, 0x85, 0x95}} +gPerfCpuStrapPostMemGuid =3D {0x8EF4372B, 0x68F0, 0x4957, {0xBC, 0x4D, 0x= 7E, 0x5C, 0xFE, 0xDA, 0xB6, 0x3E}} +gPerfMpPostMemGuid =3D {0xA59BAC5B, 0xC6A4, 0x4AEB, {0x84, 0x32, 0x= 7A, 0x8B, 0x6B, 0x68, 0x5F, 0x37}} +gPerfCpuPostMemGuid =3D {0xE2FE5ED3, 0x1417, 0x451A, {0x95, 0xC9, 0x= D0, 0xB2, 0xB9, 0x7B, 0xE0, 0x54}} +gPerfSaResetPostMemGuid =3D {0xBE152BEE, 0xFD19, 0x4274, {0xA8, 0xBA, 0x= FB, 0x31, 0x42, 0xB5, 0xB5, 0xC3}} +gPerfCpuPowerMgmtGuid =3D {0x9ED307D6, 0x4AEB, 0x44A9, {0x9B, 0x11, 0x= D8, 0x21, 0x84, 0x9A, 0xCB, 0xF7}} +gPerfMePostMemGuid =3D {0x2CC8626D, 0x3387, 0x4817, {0xAB, 0xF6, 0x= 86, 0x9A, 0xF5, 0xF0, 0x51, 0xAA}} +gPerfHdaPostMemGuid =3D {0xB31883B7, 0x5A05, 0x4040, {0x40, 0x80, 0x= 66, 0x8D, 0x29, 0x13, 0xD7, 0x84}} + +[Protocols.common.Private] + # + # SA + # + gSaIotrapSmiProtocolGuid =3D { 0x1861e089, 0xcaa3, 0x473e, { 0x84= , 0x32, 0xdc, 0x1f, 0x94, 0xc6, 0xc1, 0xa6 }} + + # + # CPU + # + gPchPcieIoTrapProtocolGuid =3D { 0xd66a1cf, 0x79ad, 0x494b, { 0x97= , 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }} + +[Protocols] +## +## IntelFrameworkPkg +## +gEfiLegacyBiosProtocolGuid =3D {0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b,= 0xe5, 0x38, 0x7f, 0xdb, 0x2e, 0x2d}} +gEfiLegacyInterruptProtocolGuid =3D {0x31ce593d, 0x108a, 0x485d, {0xad, = 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66, 0xbe}} +gEfiDataHubProtocolGuid =3D {0xae80d021, 0x618e, 0x11d4, {0xbc, 0xd7, 0x= 00, 0x80, 0xc7, 0x3c, 0x88, 0x81}} + +## +## MdeModulePkg +## +gEfiSmmVariableProtocolGuid =3D {0xed32d533, 0x99e6, 0x4209, {0x9c, 0xc0= , 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7}} + +## +## SystemAgent +## +gBdatAccessGuid =3D {0x9477482c, 0x8717, 0x4725, {0x98, 0= x28, 0x7b, 0xd8, 0xc9, 0xa3, 0x75, 0x6a}} +gIgdOpRegionProtocolGuid =3D {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0= xa5, 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}} +gMemInfoProtocolGuid =3D {0xd4d2f201, 0x50e8, 0x4d45, {0x8e, 0= x5, 0xfd, 0x49, 0xa8, 0x2a, 0x15, 0x69}} +gSaPolicyProtocolGuid =3D {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0= x63, 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}} +gSaNvsAreaProtocolGuid =3D {0x149a10a5, 0x9d06, 0x4c6b, {0xbe, 0= x44, 0x08, 0x92, 0xce, 0x20, 0x61, 0xac}} +gGopPolicyProtocolGuid =3D {0xec2e931b, 0x3281, 0x48a5, {0x81, 0= x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}} +gGopComponentName2ProtocolGuid =3D {0x651b7ebd, 0xce13, 0x41d0, {0x82, 0= xe5, 0xa0, 0x63, 0xab, 0xbe, 0x9b, 0xb6}} +gGopOverrideProtocolGuid =3D {0x4a89a16e, 0x67b8, 0x4429, {0x8c, 0= x47, 0x43, 0x67, 0x90, 0xf2, 0xf2, 0x69}} + +## +## AcpiTables +## +gEfiGlobalNvsAreaProtocolGuid =3D {0x074e1e48, 0x8132, 0x47a1, {0x8c, 0x= 2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc}} + +## +## Cpu +## +gCpuInfoProtocolGuid =3D {0xe223cf65, 0xf6ce, 0x4122, {0xb3, 0xaf, 0x4b,= 0xd1, 0x8a, 0xff, 0x40, 0xa1}} +gCpuNvsAreaProtocolGuid =3D {0xb9cf3f43, 0xbe3e, 0x4e45, {0xa0, 0xbe, 0x= 1a, 0x4, 0x89, 0xdf, 0x1a, 0xc9}} +gDxeCpuPolicyProtocolGuid =3D {0x8282b977, 0x22f9, 0x4134, {0x99, 0x43, = 0x7b, 0xcc, 0x5f, 0x40, 0x33, 0x52}} + +## +## Me +## +gDxeMePolicyGuid =3D {0xa0b5dc52, 0x4f34, 0x3990, {0xd4, 0= x91, 0x10, 0x8b, 0xe8, 0xba, 0x75, 0x42}} + +## +## PCH +## +gPchSpiProtocolGuid =3D {0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x2= 6, 0x9d, 0xe, 0xf3, 0x4a}} +gWdtProtocolGuid =3D {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5= b, 0xe6, 0xcf, 0x09, 0xb1}} +gPchSerialIoUartDebugInfoProtocolGuid =3D {0x2fd2b1bd, 0x0387, 0x4ec6, {= 0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6}} +gEfiSmmSmbusProtocolGuid =3D {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0= x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}} +gPchSmmSpiProtocolGuid =3D {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf= , 0x1, 0x9d, 0x72, 0xc7, 0xe1}} +gPchSmmIoTrapControlGuid =3D {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6, 0= x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}} +gPchTcoSmiDispatchProtocolGuid =3D {0x9e71d609, 0x6d24, 0x47fd, {0xb5, 0= x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}} +gPchPcieSmiDispatchProtocolGuid =3D {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f, = 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}} +gPchAcpiSmiDispatchProtocolGuid =3D {0xd52bb262, 0xf022, 0x49ec, {0x86, = 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}} +gPchSmiDispatchProtocolGuid =3D {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, 0xBE= , 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}} +gPchResetCallbackProtocolGuid =3D {0x3a3300ab, 0xc929, 0x487d, {0xab, 0x= 34, 0x15, 0x9b, 0xc1, 0x35, 0x62, 0xc0}} +gPchNvsAreaProtocolGuid =3D {0x2e058b2b, 0xedc1, 0x4431, {0x87, 0xd9, 0x= c6, 0xc4, 0xea, 0x10, 0x2b, 0xe3}} +gPchEmmcTuningProtocolGuid =3D {0x10fe7e3b, 0xdbe5, 0x4cfa, {0x90, 0x25,= 0x40, 0x02, 0xcf, 0xdd, 0xbb, 0x89}} +gPchEspiSmiDispatchProtocolGuid =3D {0xB3C14FF3, 0xBAE8, 0x456C, {0x86, = 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}} +gPchSmmPeriodicTimerControlGuid =3D {0x6906E93B, 0x603B, 0x4A0F, {0x86, = 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}} +gIoTrapExDispatchProtocolGuid =3D {0x5B48E913, 0x707B, 0x4F9D, {0xAF, 0x= 2E, 0xEE, 0x03, 0x5B, 0xCE, 0x39, 0x5D}} +gPchPolicyProtocolGuid =3D {0x543d5c93, 0x6a28, 0x4513, {0x85, 0x9a, 0x8= 2, 0xa7, 0xb9, 0x12, 0xcb, 0xbe}} +gPchSraProtocolGuid =3D {0x7AE12E27, 0x5087, 0x46C8, {0xBF, 0xF0, 0x83, 0x= 9C, 0x53, 0x7B, 0x25, 0xEB}} + +## +## Hsti +## +## HstiSiliconDxe Driver Entry Point +gHstiProtocolGuid =3D { 0x1b05de41, 0xc93b, 0x4bb4, { 0xad, 0x47, 0x2a, 0x= 78, 0xac, 0xf, 0xc9, 0xe4 }} +## Handler to gather and publish HSTI results on ReadyToBootEvent +gHstiPublishCompleteProtocolGuid =3D {0x0f500be6, 0xece4, 0x4ed8, { 0x90,= 0x81, 0x9a, 0xa9, 0xa5, 0x23, 0xfb, 0x7b}} +gEfiAdapterInformationProtocolGuid =3D { 0xE5DD1403, 0xD622, 0xC24E, {0x84= , 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 }} + +## +## Silicon Policy +## +## Include/Protocol/SiPolicyProtocol.h +gDxeSiPolicyProtocolGuid =3D { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94, 0= x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }} + +[Ppis.common.Private] + +[Ppis] +## +## MdeModulePkg +## +gPeiCapsulePpiGuid =3D {0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0= x54, 0xd2, 0xe1, 0x32, 0x3d}} +gPeiSmmAccessPpiGuid =3D {0x268f33a9, 0xcccd, 0x48be, {0x88, 0x17, 0x86,= 0x05, 0x3a, 0xc3, 0x2e, 0xd6}} +gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7= , 0x43, 0x05, 0xce, 0x74, 0xc5}} + +## +## SecurityPkg +## +gPeiTpmInitializationDonePpiGuid =3D {0xa030d115, 0x54dd, 0x447b, { 0x90, = 0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}} + +## +## Common +## +## Include/Ppi/SiPolicy.h +gSiPolicyPpiGuid =3D {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x8= 4, 0x8c, 0x5e, 0x86, 0x70}} + +## Include/Ppi/SiPolicy.h +gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97,= 0xc1, 0x89, 0xd0, 0xab, 0x8d}} + +## +## SystemAgent +## +gSsaBiosCallBacksPpiGuid =3D {0x99b56126, 0xe16c, 0x4d9b, {0xbb, 0x71, 0= xaa, 0x35, 0x46, 0x1a, 0x70, 0x2f}} +gSsaBiosServicesPpiGuid =3D {0x55750d10, 0x6d3d, 0x4bf5, {0x89, 0xd8, 0= xe3, 0x5e, 0xf0, 0xb0, 0x90, 0xf4}} +gEnablePeiGraphicsPpiGuid =3D {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0, 0= x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}} + +## +## Cpu +## +gPeiCachePpiGuid =3D {0x09be4bc2, 0x790e, 0x4dea, {0x8b, 0xdc, 0x38, 0x0= 5, 0x16, 0x98, 0x39, 0x44}} + +## +## Me +## +gMeDidSentPpiGuid =3D {0x45dc3106, 0xef67, 0x4c71, {0xb0, 0xf0, 0x97, 0x15= , 0x9c, 0x7d, 0xbb, 0x7c}} + +## +## PCH +## +gWdtPpiGuid =3D {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c, 0x= 21, 0x83, 0x57, 0x0d}} +gPchSpiPpiGuid =3D {0xdade7ce3, 0x6971, 0x4b75, {0x82, 0x5e, 0xe, 0xe0, = 0xeb, 0x17, 0x72, 0x2d}} +gPeiSmbusPolicyPpiGuid =3D {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb= 7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}} +gPchResetCallbackPpiGuid =3D {0x17865dc0, 0x0b8b, 0x4da8, {0x8b, 0x42, 0= x7c, 0x46, 0xb8, 0x5c, 0xca, 0x4d}} + +[LibraryClasses] +## +## Common +## +AslUpdateLib|Include/Library/AslUpdateLib.h +SiPolicyLib|Include/Library/SiPolicyLib.h +UsbLib|Include/Library/UsbLib.h +UsbInitLib|Include/Private/Library/UsbInitLib.h + +## +## CPU +## +CpuMailboxLib|Cpu/Include/Library/CpuMailboxLib.h +CpuPlatformLib|Cpu/Include/Library/CpuPlatformLib.h +CpuPolicyLib|Cpu/Include/Library/CpuPolicyLib.h + +## +## Me +## +PeiMePolicyLib|Me/Include/Library/PeiMePolicyLib.h + +## +## Pch +## +GpioLib|Pch/Include/Library/GpioLib.h +GpioLib|Pch/Include/Library/GpioNativeLib.h +PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h +PchEspiLib|Pch/Include/Library/PchEspiLib.h +PchGbeLib|Pch/Include/Library/PchGbeLib.h +GbeMdiLib|Pch/Include/Library/GbeMdiLib.h +PchInfoLib|Pch/Include/Library/PchInfoLib.h +PchP2sbLib|Pch/Include/Library/PchP2sbLib.h +PchPcieRpLib|Pch/Include/Library/PchPcieRpLib.h +PchPcrLib|Pch/Include/Library/PchPcrLib.h +PchPmcLib|Pch/Include/Library/PchPmcLib.h +PchPolicyLib|Pch/Include/Library/PchPolicyLib.h +PchSbiAccessLib|Pch/Include/Library/PchSbiAccessLib.h +PchSerialIoLib|Pch/Include/Library/PchSerialIoLib.h +PchSerialIoUartLib|Pch/Include/Library/PchSerialIoUartLib.h +SecPchLib|Pch/Include/Library/SecPchLib.h +PchTraceHubLib|Pch/Include/Private/Library/PchTraceHubLib.h +PchSmmControlLib|Pch/IncludePrivate/Library/PchSmmControlLib.h +PchWdtCommonLib|Pch/Include/Library/PchWdtCommonLib.h +OcWdtLib|Pch/Include/Library/OcWdtLib.h +PchResetLib|Pch/Include/Library/PchResetLib.h +DxePchPolicyLib|Pch/Include/Library/DxePchPolicyLib.h +GpioNameBufferLib|Pch/IncludePrivate/Library/GpioNameBufferLib.h + +## +## Sa +## +DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h +PeiSaPolicyLib|SystemAgent/Include/Library/PeiSaPolicyLib.h +SaPlatformLib|SystemAgent/Include/Library/SaPlatformLib.h + +## +## Memory +## + +[PcdsFixedAtBuild] +## From MdeModulePkg.dec +## Progress Code for S3 Suspend end. +## PROGRESS_CODE_S3_SUSPEND_END =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_= SPECIFIC | 0x00000001)) =3D 0x03078001 +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001= 033 + +## +## PcdNemCodeCacheBase is usally the same as PEI FV Base address, +## FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from PlatformPkg.fdf. +## +## Restriction: +## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + PcdTemporaryRamSize) >= =3D 4K +## 2) PcdTemporaryRamBase >=3D 4G - 64M +## +gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20000009 + +## +## NemCodeCacheSize is usally the same as PEI FV Size, +## FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf. +## +## Restriction: +## 1) PcdNemTotalCacheSize =3D NemCodeCacheSize + PcdTemporaryRamSize +## <=3D Maximun CPU NEM total size (Code + Data) +## =3D LLC size - 0.5M +## 2) PcdTemporaryRamSize <=3D Maximum CPU NEM data size +## =3D MLC size +## NOTE: The size restriction may be changed in next generation processor. +## Please refer to Processor BWG for detail. +## +gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x10000001 +gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002 +gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x00010028 +gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x00010029 +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|0xFFE60000|UINT32|0x30000004 +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32|0x30000005 +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT32|0x30000006 + +## +## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection +## value of the struct +## 0x00 EfiGcdAllocateAnySearchBottomUp +## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp +## 0x03 EfiGcdAllocateAnySearchTopDown +## 0x04 EfiGcdAllocateMaxAddressSearchTopDown +## +## below value should not using in this situation +## 0x05 EfiGcdMaxAllocateType : design for max value of struct +## 0x02 EfiGcdAllocateAddress : design for speccification address allocate +## +gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000 + +gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi|0x55|UINT8|0x0010005 +gSiPkgTokenSpaceGuid.PcdHwpSmi|0x27|UINT8|0x40000001 +gSiPkgTokenSpaceGuid.PcdItbmSmi|0x29|UINT8|0x40000002 + +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioBase|0x0000004000000000|UINT64|0x40000= 003 +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioSize|0x0000004000000000|UINT64|0x40000= 004 + +[PcdsDynamic, PcdsPatchableInModule] +## From MdeModulePkg.dec +## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to= follow ACPI specification. +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034 +## Default OEM Table ID for ACPI table creation, it is "EDK2 ". +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x= 30001035 +## Default OEM Revision for ACPI table creation. +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x30001036 +## Default Creator ID for ACPI table creation. +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037 +## Default Creator Revision for ACPI table creation. +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x300= 01038 + +[PcdsFixedAtBuild, PcdsPatchableInModule] +## Maximun number of performance log entries during PEI phase. +gSiPkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40|UINT8|0x0001002f +## This value is used to set the base address of MCH +gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFED10000|UINT64|0x00010030 +## This value is used to set the base address of PCH devices +gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031 +gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010034 +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035 + +## 32KB window +gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x8000|UINT32|0x50000000 + +## Stack size in the temporary RAM. +## 0 means half of TemporaryRamSize. +gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x00010036 +## +## PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined = in SMBIOS, +## values 0-0x7F will be treated as disable FVI reporting. +## FVI structure uses it as SMBIOS OEM type to provide version information. +## +gSiPkgTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037 +gSiPkgTokenSpaceGuid.PcdSaPciPrint|FALSE|BOOLEAN|0x00010039 +## +## SMBIOS defaults +## +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSocketDesignation|"U3E1"|VOID*|0x0001= 003a +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSerialNumber|"To Be Filled By O.E.M."= |VOID*|0x0001003b +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultAssetTag|"To Be Filled By O.E.M."|VOI= D*|0x0001003c +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultPartNumber|"To Be Filled By O.E.M."|V= OID*|0x0001003d + +## +## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices +## If PcdPciReservedMemLimit =3D0 Pci Reserved default MMIO Limit is 0xE= 0000000 else use PcdPciReservedMemLimit . +## +gSiPkgTokenSpaceGuid.PcdPciReservedIobase |0x2000 |UINT16|0x00010041 +gSiPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF |UINT16|0x00010042 +gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000 |UINT32|0x00010043 + +## +## Default 8MB TSEG +## +gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000|UINT32|0x00010046 +## +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type = (0x80 to 0xFF) defined +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS report= ing. +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information. +## +gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047 + +## +## Maximum Address the AP Wakeup Buffer can start. +## +gSiPkgTokenSpaceGuid.PcdCpuApWakeupBufferMaxAddr|0x58000|UINT32|0x00010048 + +## +## Silicon Reference Code versions +## + +##Major:To represent code generation +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor |0x07|UINT8|0x00010049 + +##Revision:Weekly build number +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x57|UINT8|0x00010051 + +##Build[7:4]:Daily build number. +##Build[3:0]:Patch build number. +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild |0x40|UINT8|0x00010052 + + +## +## Temp MEM IO resource +## +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |2 |UINT8 |0x0= 0010053 +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |10 |UINT8 |0x0= 0010054 +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0x0= 0010055 +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize |0x00200000|UINT32|0x0= 0010056 + +## +## This PCD specifies the base address of the HPET timer. +## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and 0xFED= 03000 +## +gSiPkgTokenSpaceGuid.PcdHpetBaseAddress |0xFED00000|UINT32|0x00010057 +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x00010060 +## +## This PCD specifies the base address of the IO APIC. +## The acceptable values are 0xFECxx000. +## +#gSiPkgTokenSpaceGuid.PcdIoApicBaseAddress |0xFEC00000|UINT32|0x00010058 +## +## Regbar Base Address +## +gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress|0xFC000000|UINT32|0x00010059 + +## Null-terminated string of the Version of Physical Presence interface su= pported by platform. +# @Prompt Version of Physical Presence interface supported by platform. +gSiPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|"1.3"|VOID*|0x0000= 0008 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] +## +## SerialIo Uart Configuration +## +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8 |0x00100001= # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing +gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8 |0x00100002 +gSiPkgTokenSpaceGuid.PcdSerialIoUartInputClock |1843200|UINT32|0x00100003 +gSiPkgTokenSpaceGuid.PcdSerialIoUart0PinMuxing |0 |UINT8 |0x00100009= # 0: default pins, 1: pins muxed with CNV_BRI/RGI +## +## PCI Express MMIO region length +## Valid settings: 0x10000000/256MB, 0x8000000/128MB, 0x4000000/64MB +## +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0010004 + +## Indidates if SMM Save State saved in MSRs. +# if enabled, SMM Save State will use the MSRs instead of the memory.
=
+# TRUE - SMM Save State will use the MSRs.
+# FALSE - SMM Save State will use the memory.
+# @Prompt SMM Save State uses MSRs. +gSiPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE|BOOLEAN|0x20000001 +[PcdsDynamic] + +## Indidates if SMM Delay feature is supported.

+# TRUE - SMM Delay feature is supported.
+# FALSE - SMM Delay feature is not supported.
+# @Prompt SMM Delay feature. +gSiPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|TRUE|BOOLEAN|0x0010009 + +## Indidates if SMM Block feature is supported.

+# TRUE - SMM Block feature is supported.
+# FALSE - SMM Block feature is not supported.
+# @Prompt SMM Block feature. +gSiPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|TRUE|BOOLEAN|0x001000A + +## Indidates if SMM Enable/Disable feature is supported.

+# TRUE - SMM Enable/Disable feature is supported.
+# FALSE - SMM Enable/Disable feature is not supported.
+# @Prompt SMM Enable/Disable feature. +gSiPkgTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication|TRUE|BOOLEAN|0x001000B + +## Indidates if SMM PROT MODE feature is supported.

+# TRUE - SMM PROT MODE feature is supported.
+# FALSE - SMM PROT MODE feature is not supported.
+# @Prompt SMM PROT MODE feature. +gSiPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|TRUE|BOOLEAN|0x001000C + +## Indidates if SMM Code Access Check feature is supported.

+# TRUE - SMM Code Access Check feature is supported.
+# FALSE - SMM Code Access Check feature is not supported.
+# @Prompt SMM Code Access Check feature. +gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x001000D + +[PcdsFeatureFlag] +## +## Those PCDs are used to control build process. +## +gSiPkgTokenSpaceGuid.PcdTraceHubEnable |FALSE|BOOLEAN|0xF000= 0001 +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |FALSE|BOOLEAN|0xF000= 0002 +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE|BOOLEAN|0xF000= 0004 +gSiPkgTokenSpaceGuid.PcdSiCsmEnable |FALSE|BOOLEAN|0xF000= 0005 +gSiPkgTokenSpaceGuid.PcdUseHpetTimer |TRUE |BOOLEAN|0xF000= 0006 +gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE |BOOLEAN|0xF000= 0008 +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE |BOOLEAN|0xF000= 0009 +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE|BOOLEAN|0xF000= 000B +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE |BOOLEAN|0xF000= 000C +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE|BOOLEAN|0xF000= 000F +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE|BOOLEAN|0xF000= 0011 +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE|BOOLEAN|0xF000= 0012 +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE |BOOLEAN|0xF000= 0014 +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE |BOOLEAN|0xF000= 0015 +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE|BOOLEAN|0xF000= 0016 +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE|BOOLEAN|0xF000= 0017 +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE |BOOLEAN|0xF000= 001A +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE |BOOLEAN|0xF000= 001B +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE |BOOLEAN|0xF000= 001C +gSiPkgTokenSpaceGuid.PcdIpuEnable |TRUE |BOOLEAN|0xF000= 001D +gSiPkgTokenSpaceGuid.PcdGnaEnable |TRUE |BOOLEAN|0xF000= 001E +gSiPkgTokenSpaceGuid.PcdSaOcEnable |TRUE |BOOLEAN|0xF000= 001F +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE |BOOLEAN|0xF000= 0020 +gSiPkgTokenSpaceGuid.PcdBdatEnable |FALSE|BOOLEAN|0xF000= 0023 +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE |BOOLEAN|0xF000= 0024 +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE |BOOLEAN|0xF000= 0025 +gSiPkgTokenSpaceGuid.PcdCflCpuEnable |FALSE|BOOLEAN|0xF000= 0027 +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |FALSE|BOOLEAN|0xF000= 0029 +gSiPkgTokenSpaceGuid.PcdMinTreeEnable |FALSE|BOOLEAN|0xF000= 002A # To separate modules used in mininal source tree and advanced featur= es +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |FALSE|BOOLEAN|0xF000= 0033 +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE|BOOLEAN|0xF000= 0034 + +gSiPkgTokenSpaceGuid.PcdEdk2MasterEnable |FALSE|BOOLEAN|0xF000= 0035 +gSiPkgTokenSpaceGuid.PcdPpamEnable |TRUE |BOOLEAN|0xF000= 0036 + +#This PCD is used to enable WDT for debug purposes in OverClocking. +gSiPkgTokenSpaceGuid.PcdOcEnableWdtforDebug |FALSE|BOOLEAN|0xF000= 0037 diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h new file mode 100644 index 0000000000..d0e3d94418 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock.h @@ -0,0 +1,53 @@ +/** @file + Header file for Config Block Lib implementation + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CONFIG_BLOCK_H_ +#define _CONFIG_BLOCK_H_ + +#include +#include +#include +#include + +#pragma pack (push,1) + +/// +/// Config Block Header +/// +typedef struct _CONFIG_BLOCK_HEADER { + EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID e= xtension HOB header + UINT8 Revision; ///< Offset 24 Revisi= on of this config block + UINT8 Attributes; ///< Offset 25 The ma= in revision for config block + UINT8 Reserved[2]; ///< Offset 26-27 Reserv= ed for future use +} CONFIG_BLOCK_HEADER; + +/// +/// Config Block +/// +typedef struct _CONFIG_BLOCK { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header= of config block + // + // Config Block Data + // +} CONFIG_BLOCK; + +/// +/// Config Block Table Header +/// +typedef struct _CONFIG_BLOCK_TABLE_STRUCT { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID n= umber for main entry of config block + UINT8 Rsvd0[2]; ///< Offset 28-29 Reserv= ed for future use + UINT16 NumberOfBlocks; ///< Offset 30-31 Number= of config blocks (N) + UINT32 AvailableSize; ///< Offset 32-35 Curren= t config block table size +/// +/// Individual Config Block Structures are added here in memory as part of= AddConfigBlock() +/// +} CONFIG_BLOCK_TABLE_HEADER; +#pragma pack (pop) + +#endif // _CONFIG_BLOCK_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfi= g.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h new file mode 100644 index 0000000000..27b5a9440e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/SiConfig.h @@ -0,0 +1,89 @@ +/** @file + Si Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_CONFIG_H_ +#define _SI_CONFIG_H_ + +#define SI_CONFIG_REVISION 3 + +extern EFI_GUID gSiConfigGuid; + + +#pragma pack (push,1) + +/** + The Silicon Policy allows the platform code to publish a set of configur= ation + information that the RC drivers will use to configure the silicon hardwa= re. + + Revision 1: + - Initial version. + Revision 2: + - Added TraceHubMemBase + Revision 3 + - Deprecated SkipPostBootSai +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header + // + // Platform specific common policies that used by several silicon compon= ents. + // + UINT32 CsmFlag : 1; ///< Offset 44 BIT0: CSM status flag. + /** + @deprecated since revision 3 + **/ + UINT32 SkipPostBootSai : 1; + UINT32 RsvdBits : 30; ///< Reserved + UINT32 *SsidTablePtr; // Offset 48 + UINT16 NumberOfSsidTableEntry; // Offset 52 + UINT16 Reserved; // Offset 54 + /** + If Trace Hub is enabled and trace to memory is desired, Platform code = or BootLoader needs to allocate trace hub memory + as reserved, and save allocated memory base to TraceHubMemBase to ensu= re Trace Hub memory is configured properly. + To get total trace hub memory size please refer to TraceHubCalculateTo= talBufferSize () + + Noted: If EDKII memory service is used to allocate memory, it will req= uire double memory size to support size-aligned memory allocation, + so Platform code or FSP Wrapper code should ensure enough memory avail= able for size-aligned TraceHub memory allocation. + **/ + UINT32 TraceHubMemBase; // Offset 58 +} SI_CONFIG; + +#pragma pack (pop) + +#define DEFAULT_SSVID 0x8086 +#define DEFAULT_SSDID 0x7270 +#define MAX_DEVICE_COUNT 70 + +/// +/// Subsystem Vendor ID / Subsystem ID +/// +typedef struct { + UINT16 SubSystemVendorId; + UINT16 SubSystemId; +} SVID_SID_VALUE; + +// +// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to= PciSegmentRead/Write functions. +// +typedef struct { + union { + struct { + UINT64 Register:12; + UINT64 Function:3; + UINT64 Device:5; + UINT64 Bus:8; + UINT64 Reserved1:4; + UINT64 Segment:16; + UINT64 Reserved2:16; + } Bits; + UINT64 SegBusDevFuncRegister; + } Address; + SVID_SID_VALUE SvidSidValue; + UINT32 Reserved; +} SVID_SID_INIT_ENTRY; + +#endif // _SI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConf= ig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h new file mode 100644 index 0000000000..8b51e2d47a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/ConfigBlock/UsbConfig.h @@ -0,0 +1,291 @@ +/** @file + Common USB policy shared between PCH and CPU + Contains general features settings for xHCI and xDCI + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USB_CONFIG_H_ +#define _USB_CONFIG_H_ + +#define USB_CONFIG_REVISION 3 +extern EFI_GUID gUsbConfigGuid; + +#define MAX_USB2_PORTS 16 +#define MAX_USB3_PORTS 10 + +#pragma pack (push,1) + +#define PCH_USB_OC_PINS_MAX 8 ///< Maximal possible number of USB Over C= urrent pins + +/// +/// Overcurrent pins, the values match the setting of EDS, please refer to= EDS for more details +/// +typedef enum { + UsbOverCurrentPin0 =3D 0, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin4, + UsbOverCurrentPin5, + UsbOverCurrentPin6, + UsbOverCurrentPin7, + UsbOverCurrentPinMax, + UsbOverCurrentPinSkip =3D 0xFF +} USB_OVERCURRENT_PIN; + +/** + This structure configures per USB2 AFE settings. + It allows to setup the port electrical parameters. +**/ +typedef struct { +/** Per Port HS Preemphasis Bias (PERPORTPETXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Petxiset; +/** Per Port HS Transmitter Bias (PERPORTTXISET) + 000b - 0mV + 001b - 11.25mV + 010b - 16.9mV + 011b - 28.15mV + 100b - 28.15mV + 101b - 39.35mV + 110b - 45mV + 111b - 56.3mV +**/ + UINT8 Txiset; +/** + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN) + 00b - Emphasis OFF + 01b - De-emphasis ON + 10b - Pre-emphasis ON + 11b - Pre-emphasis & De-emphasis ON +**/ + UINT8 Predeemp; +/** + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF) + 1b - half-bit pre-emphasis + 0b - full-bit pre-emphasis +**/ + UINT8 Pehalfbit; +} USB20_AFE; + +/** + This structure configures per USB2 port physical settings. + It allows to setup the port location and port length, and configures the= port strength accordingly. +**/ +typedef struct { + /** + These members describe the specific over current pin number of USB 2.0= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same + OC pin (see: USB_OVERCURRENT_PIN). + **/ + UINT32 OverCurrentPin : 8; + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 23; ///< Reserved bits + /** + Changing this policy values from default ones may require disabling US= B2 PHY Sus Well Power Gating + through Usb2PhySusPgEnable on PCH-LP + **/ + USB20_AFE Afe; ///< USB2 AFE settings +} USB20_PORT_CONFIG; + +/** + This structure describes whether the USB3 Port N is enabled by platform = modules. +**/ +typedef struct { + /** + These members describe the specific over current pin number of USB 3.x= Port N. + It is SW's responsibility to ensure that a given port's bit map is set= only for + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same + OC pin (see: USB_OVERCURRENT_PIN). + **/ + UINT32 OverCurrentPin : 8; + + /** + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin) + HSIO_TX_DWORD8[21:16] + Default =3D 00h + **/ + UINT32 HsioTxDownscaleAmp : 8; + /** + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2dee= mph3p5) + HSIO_TX_DWORD5[21:16] + Default =3D 29h (approximately -3.5dB De-Emphasis) + **/ + UINT32 HsioTxDeEmph : 8; + + UINT32 Enable : 1; ///< 0: Disable; 1: Enable. + UINT32 HsioTxDeEmphEnable : 1; ///< Enable the write to USB 3.0= TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable. + UINT32 HsioTxDownscaleAmpEnable : 1; ///< Enable the write to USB 3.0= TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 5; ///< Reserved bits +} USB30_PORT_CONFIG; + +/** + The XDCI_CONFIG block describes the configurations + of the xDCI Usb Device controller. +**/ +typedef struct { + /** + This member describes whether or not the xDCI controller should be ena= bled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} XDCI_CONFIG; + +// +// Below defines are for proper UPD construction and values syncing betwee= n UPD and policy +// +#define B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN BIT0 ///< Enable the wr= ite to Signed Magnatude number added to the CTLE code bit +#define B_XHCI_HSIO_FILTER_SELECT_N_EN BIT1 ///< Enable the wr= ite to LFPS filter select for n +#define B_XHCI_HSIO_FILTER_SELECT_P_EN BIT2 ///< Enable the wr= ite to LFPS filter select for p +#define B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN BIT3 ///< Enable the wr= ite to olfpscfgpullupdwnres +#define N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG 3 +#define N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES 0 +#define N_XHCI_UPD_HSIO_FILTER_SELECT_P 0 +#define N_XHCI_UPD_HSIO_FILTER_SELECT_N 4 + +typedef struct { + /** + Signed Magnatude number added to the CTLE code.(ctle_adapt_offset_cfg_= 4_0) + HSIO_RX_DWORD25 [20:16] + Ex: -1 -- 1_0001. +1: 0_0001 + Default =3D 0h + **/ + UINT32 HsioCtrlAdaptOffsetCfg : 5; + /** + LFPS filter select for n (filter_sel_n_2_0) + HSIO_RX_DWORD51 [29:27] + 0h:1.6ns + 1h:2.4ns + 2h:3.2ns + 3h:4.0ns + 4h:4.8ns + 5h:5.6ns + 6h:6.4ns + Default =3D 0h + **/ + UINT32 HsioFilterSelN : 3; + /** + LFPS filter select for p (filter_sel_p_2_0) + HSIO_RX_DWORD51 [26:24] + 0h:1.6ns + 1h:2.4ns + 2h:3.2ns + 3h:4.0ns + 4h:4.8ns + 5h:5.6ns + 6h:6.4ns + Default =3D 0h + **/ + UINT32 HsioFilterSelP : 3; + /** + Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0) + HSIO_RX_DWORD51 [2:0] + 000 Prohibited + 001 45K + 010 Prohibited + 011 31K + 100 36K + 101 36K + 110 36K + 111 36K + Default =3D 3h + **/ + UINT32 HsioOlfpsCfgPullUpDwnRes : 3; + + UINT32 HsioCtrlAdaptOffsetCfgEnable : 1; ///< Enable the write to S= igned Magnatude number added to the CTLE code, 0: Disable; 1: Enable. + UINT32 HsioFilterSelNEnable : 1; ///< Enable the write to L= FPS filter select for n, 0: Disable; 1: Enable. + UINT32 HsioFilterSelPEnable : 1; ///< Enable the write to L= FPS filter select for p, 0: Disable; 1: Enable. + UINT32 HsioOlfpsCfgPullUpDwnResEnable : 1; ///< Enable the write to o= lfpscfgpullupdwnres, 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 14; ///< Reserved bits +} USB30_HSIO_RX_CONFIG; + + +/** + This member describes the expected configuration of the USB controller, + Platform modules may need to refer Setup options, schematic, BIOS specif= ication to update this field. + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated = by referring the schematic. + + Revision 1: + - Initial version. + Revision 2: + - Added Usb2PhySusPgEnable - for enabling/disabling USB2 PHY SUS Well Po= wer Gating + Revision 3: + Added HSIO Rx tuning policy options structure USB30_HSIO_RX_CONFIG +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er + /** + This policy setting controls state of Compliance Mode enabling. + Compliance Mode can be enabled for testing through this option but def= ualt setting is Disabled. + 0:Disable, 1: Enable + **/ + UINT32 EnableComplianceMode : 1; + /** + This policy option when set will make BIOS program Port Disable Overri= de register during PEI phase. + When disabled BIOS will not program the PDO during PEI phase and leave= PDO register unlocked for later programming. + If this is disabled, platform code MUST set it before booting into OS. + 1: Enable, 0: Disable + **/ + UINT32 PdoProgramming : 1; + /** + This option allows for control whether USB should program the Overcurr= ent Pins mapping into xHCI. + Disabling this feature will disable overcurrent detection functionalit= y. + Overcurrent Pin mapping data is contained in respective port structure= s (i.e. USB30_PORT_CONFIG) in OverCurrentPin field. + By default this Overcurrent functionality should be enabled and disabl= ed only for OBS debug usage. + 1: Will program USB OC pin mapping in respective xHCI controller re= gisters + 0: Will clear OC pin mapping allow for OBS usage of OC pins + **/ + UINT32 OverCurrentEnable : 1; + /** + (Test) + If this policy option is enabled then BIOS will program OCCFDONE bit i= n xHCI meaning that OC mapping data will be + consumed by xHCI and OC mapping registers will be locked. OverCurrent = mapping data is taken from respective port data + structure from OverCurrentPin field. + If EnableOverCurrent policy is enabled this also should be enabled, ot= herwise xHCI won't consume OC mapping data. + 1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping d= ata + 0: Do not program OCCFDONE bit making it possible to use OBS debug on = OC pins. + **/ + UINT32 XhciOcLock : 1; + /** + (Test) + This policy option enables USB2 PHY SUS Well Power Gating functionalit= y. + Please note this is ignored on PCH H + 0: disable USB2 PHY SUS Well Power Gating + 1: enable USB2 PHY SUS Well Power Gating + **/ + UINT32 Usb2PhySusPgEnable : 1; + UINT32 RsvdBits0 : 27; ///< Rese= rved bits + /** + These members describe whether the USB2 Port N of PCH is enabled by pl= atform modules. + **/ + USB20_PORT_CONFIG PortUsb20[MAX_USB2_PORTS]; + /** + These members describe whether the USB3 Port N of PCH is enabled by pl= atform modules. + **/ + USB30_PORT_CONFIG PortUsb30[MAX_USB3_PORTS]; + /** + This member describes whether or not the xDCI controller should be ena= bled. + **/ + XDCI_CONFIG XdciConfig; + /** + This member describes policy options for RX signal tuning in ModPHY + **/ + USB30_HSIO_RX_CONFIG PortUsb30HsioRx[MAX_USB3_PORTS]; +} USB_CONFIG; + +#pragma pack (pop) + +#endif // _USB_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLi= b.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h new file mode 100644 index 0000000000..39baa6c03a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/AslUpdateLib.h @@ -0,0 +1,157 @@ +/** @file + ASL dynamic update library definitions. + This library provides dymanic update to various ASL structures. + There may be different libraries for different environments (PEI, BS, RT= , SMM). + Make sure you meet the requirements for the library (protocol dependenci= es, use + restrictions, etc). + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ASL_UPDATE_LIB_H_ +#define _ASL_UPDATE_LIB_H_ + +// +// Include files +// +#include +#include +#include + +// +// AML parsing definitions +// +#define AML_RESRC_TEMP_END_TAG 0x0079 + +// +// ASL PSS package structure layout +// +#pragma pack (1) +typedef struct { + UINT8 NameOp; // 12h ;First opcode is a NameOp. + UINT8 PackageLead; // 20h ;First opcode is a NameOp. + UINT8 NumEntries; // 06h ;First opcode is a NameOp. + UINT8 DwordPrefix1; // 0Ch + UINT32 CoreFrequency; // 00h + UINT8 DwordPrefix2; // 0Ch + UINT32 Power; // 00h + UINT8 DwordPrefix3; // 0Ch + UINT32 TransLatency; // 00h + UINT8 DwordPrefix4; // 0Ch + UINT32 BmLatency; // 00h + UINT8 DwordPrefix5; // 0Ch + UINT32 Control; // 00h + UINT8 DwordPrefix6; // 0Ch + UINT32 Status; // 00h +} PSS_PACKAGE_LAYOUT; +#pragma pack() + +/** + Initialize the ASL update library state. + This must be called prior to invoking other library functions. + + + @retval EFI_SUCCESS The function completed successfull= y. +**/ +EFI_STATUS +InitializeAslUpdateLib ( + VOID + ); + +/** + This procedure will update immediate value assigned to a Name + + @param[in] AslSignature The signature of Operation Region = that we want to update. + @param[in] Buffer source of data to be written over = original aml + @param[in] Length length of data to be overwritten + + @retval EFI_SUCCESS The function completed successfull= y. +**/ +EFI_STATUS +UpdateNameAslCode( + IN UINT32 AslSignature, + IN VOID *Buffer, + IN UINTN Length + ); + +/** + This procedure will update the name of ASL Method + + @param[in] AslSignature - The signature of Operation Region that we= want to update. + @param[in] Buffer - source of data to be written over origina= l aml + @param[in] Length - length of data to be overwritten + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_NOT_FOUND - Failed to locate AcpiTable. +**/ +EFI_STATUS +UpdateMethodAslCode ( + IN UINT32 AslSignature, + IN VOID *Buffer, + IN UINTN Length + ); + +/** + This function uses the ACPI support protocol to locate an ACPI table usi= ng the . + It is really only useful for finding tables that only have a single inst= ance, + e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc. + Matches are determined by finding the table with ACPI table that has + a matching signature and version. + + @param[in] Signature Pointer to an ASCII string contain= ing the Signature to match + @param[in, out] Table Updated with a pointer to the table + @param[in, out] Handle AcpiSupport protocol table handle = for the table found + @param[in, out] Version On input, the version of the table= desired, + on output, the versions the table = belongs to + @see AcpiSupport protocol for deta= ils + + @retval EFI_SUCCESS The function completed successfull= y. +**/ +EFI_STATUS +LocateAcpiTableBySignature ( + IN UINT32 Signature, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle + ); + +/** + This function uses the ACPI support protocol to locate an ACPI SSDT tabl= e. + The table is located by searching for a matching OEM Table ID field. + Partial match searches are supported via the TableIdSize parameter. + + @param[in] TableId Pointer to an ASCII string contain= ing the OEM Table ID from the ACPI table header + @param[in] TableIdSize Length of the TableId to match. T= able ID are 8 bytes long, this function + will consider it a match if the fi= rst TableIdSize bytes match + @param[in, out] Table Updated with a pointer to the table + @param[in, out] Handle AcpiSupport protocol table handle = for the table found + @param[in, out] Version See AcpiSupport protocol, GetAcpiT= able function for use + + @retval EFI_SUCCESS The function completed successfull= y. +**/ +EFI_STATUS +LocateAcpiTableByOemTableId ( + IN UINT8 *TableId, + IN UINT8 TableIdSize, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle + ); + +/** + This function calculates and updates an UINT8 checksum. + + @param[in] Buffer Pointer to buffer to checksum + @param[in] Size Number of bytes to checksum + @param[in] ChecksumOffset Offset to place the checksum resul= t in + + @retval EFI_SUCCESS The function completed successfull= y. +**/ +EFI_STATUS +AcpiChecksum ( + IN VOID *Buffer, + IN UINTN Size, + IN UINTN ChecksumOffset + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlock= Lib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h new file mode 100644 index 0000000000..9a3bf373a6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/ConfigBlockLib.h @@ -0,0 +1,64 @@ +/** @file + Header file for Config Block Lib implementation + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CONFIG_BLOCK_LIB_H_ +#define _CONFIG_BLOCK_LIB_H_ + +/** + Create config block table + + @param[in] TotalSize - Max size to be allocated f= or the Config Block Table + @param[out] ConfigBlockTableAddress - On return, points to a poi= nter to the beginning of Config Block Table Address + + @retval EFI_INVALID_PARAMETER - Invalid Parameter + @retval EFI_OUT_OF_RESOURCES - Out of resources + @retval EFI_SUCCESS - Successfully created Config Block Table = at ConfigBlockTableAddress +**/ +EFI_STATUS +EFIAPI +CreateConfigBlockTable ( + IN UINT16 TotalSize, + OUT VOID **ConfigBlockTableAddress + ); + +/** + Add config block into config block table structure + + @param[in] ConfigBlockTableAddress - A pointer to the beginning= of Config Block Table Address + @param[out] ConfigBlockAddress - On return, points to a poi= nter to the beginning of Config Block Address + + @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add= new Config Block or + Config Block Offset Table is full and can= not add new Config Block. + @retval EFI_SUCCESS - Successfully added Config Block +**/ +EFI_STATUS +EFIAPI +AddConfigBlock ( + IN VOID *ConfigBlockTableAddress, + OUT VOID **ConfigBlockAddress + ); + +/** + Retrieve a specific Config Block data by GUID + + @param[in] ConfigBlockTableAddress - A pointer to the beginnin= g of Config Block Table Address + @param[in] ConfigBlockGuid - A pointer to the GUID use= s to search specific Config Block + @param[out] ConfigBlockAddress - On return, points to a po= inter to the beginning of Config Block Address + + @retval EFI_NOT_FOUND - Could not find the Config Block + @retval EFI_SUCCESS - Config Block found and return +**/ +EFI_STATUS +EFIAPI +GetConfigBlock ( + IN VOID *ConfigBlockTableAddress, + IN EFI_GUID *ConfigBlockGuid, + OUT VOID **ConfigBlockAddress + ); + +#endif // _CONFIG_BLOCK_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h new file mode 100644 index 0000000000..858f8ac5e6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/MmPciLib.h @@ -0,0 +1,28 @@ +/** @file + Get Pci Express address library implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MM_PCI_LIB_H_ +#define _MM_PCI_LIB_H_ + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function +); + +#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicy= UpdateLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolic= yUpdateLib.h new file mode 100644 index 0000000000..c6eb70f6e2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/PeiSiPolicyUpdateL= ib.h @@ -0,0 +1,123 @@ +/** @file + Header file for PEI SiPolicyUpdate Library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SI_POLICY_UPDATE_LIB_H_ +#define _PEI_SI_POLICY_UPDATE_LIB_H_ + +#include + +/** + This function performs Silicon PEI Policy initialization. + + @param[in, out] SiPolicy The Silicon Policy PPI instance + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicy ( + IN OUT SI_POLICY_PPI *SiPolicy + ); + +/** + This function performs CPU PEI Policy initialization in Post-memory. + + @param[in, out] SiPolicyPpi The SI Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs SI PEI Policy initialization. + + @param[in, out] SiPolicyPpi The SA Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + + +/** +This function performs SA PEI Policy initialization for PreMem. + +@param[in, out] SiPreMemPolicyPpi The SI PreMem Policy PPI instance + +@retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyPreMem ( +IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi +); + +/** + This function performs PCH PEI Policy initialization. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT SI_POLICY_PPI *SiPolicy + ); + +/** + This function performs PCH PEI Policy initialization. + + @param[in, out] SiPreMemPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy + ); + +/** + Update the ME Policy Library + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +UpdatePeiMePolicy ( + IN OUT SI_POLICY_PPI *SiPolicy + ); + +/** + Update the ME Policy Library + + @param[in, out] SiPreMemPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +UpdatePeiMePolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlo= ckLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockL= ib.h new file mode 100644 index 0000000000..fd8582b981 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiConfigBlockLib.h @@ -0,0 +1,58 @@ +/** @file + Prototype of the SiConfigBlockLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_CONFIG_BLOCK_LIB_H_ +#define _SI_CONFIG_BLOCK_LIB_H_ + + +typedef +VOID +(*LOAD_DEFAULT_FUNCTION) ( + IN VOID *ConfigBlockPointer + ); + +typedef struct { + EFI_GUID *Guid; + UINT16 Size; + UINT8 Revision; + LOAD_DEFAULT_FUNCTION LoadDefault; +} COMPONENT_BLOCK_ENTRY; + +/** + GetComponentConfigBlockTotalSize get config block table total size. + + @param[in] ComponentBlocks Component blocks array + @param[in] TotalBlockCount Number of blocks + + @retval Size of config block table +**/ +UINT16 +EFIAPI +GetComponentConfigBlockTotalSize ( + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, + IN UINT16 TotalBlockCount + ); + +/** + AddComponentConfigBlocks add all config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add config blocks + @param[in] ComponentBlocks Config blocks array + @param[in] TotalBlockCount Number of blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +AddComponentConfigBlocks ( + IN VOID *ConfigBlockTableAddress, + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, + IN UINT16 TotalBlockCount + ); +#endif // _SI_CONFIG_BLOCK_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h new file mode 100644 index 0000000000..5633e2892c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/SiPolicyLib.h @@ -0,0 +1,110 @@ +/** @file + Prototype of the SiPolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_POLICY_LIB_H_ +#define _SI_POLICY_LIB_H_ + +#include + +/** + Print whole SI_PREMEM_POLICY_PPI and serial out. + + @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance +**/ +VOID +EFIAPI +SiPreMemPrintPolicyPpi ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + Print whole SI_POLICY_PPI and serial out. + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +SiPrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + SiCreatePreMemConfigBlocks creates the config blocksg of Silicon Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] SiPreMemPolicyPpi The pointer to get Silicon PREMEM Policy= PPI instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiCreatePreMemConfigBlocks ( + OUT SI_PREMEM_POLICY_PPI **SiPreMemPolicyPpi + ); + +/** + SiCreateConfigBlocks creates the config blocksg of Silicon Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] SiPolicyPpi The pointer to get Silicon Policy PPI in= stance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiCreateConfigBlocks ( + OUT SI_POLICY_PPI **SiPolicyPpi + ); + +/** + SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] SiPreMemPolicyPpi The pointer to Silicon PREMEM Policy PPI = instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyPpi ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + SiInstallPolicyPpi installs SiPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Print out all silicon policy information. + + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance + + @retval none +**/ +VOID +DumpSiPolicy ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +#endif // _SI_PREMEM_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h new file mode 100644 index 0000000000..cab5342c54 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/StallPpiLib.h @@ -0,0 +1,22 @@ +/** @file + Header file for a library to install StallPpi. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _STALL_PPI_LIB_H_ +#define _STALL_PPI_LIB_H_ + +/** + This function is to install StallPpi + + @retval EFI_SUCCESS if Ppi is installed successfully. +**/ +EFI_STATUS +EFIAPI +InstallStallPpi( + VOID + ); +#endif //_STALL_PPI_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h new file mode 100644 index 0000000000..a7cd305c62 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Library/UsbLib.h @@ -0,0 +1,34 @@ +/** @file + Header file of available functions in general USB Library + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USB_LIB_H_ +#define _USB_LIB_H_ + +#include + +/* + Disables requested ports through Port Disable Override register programm= ing + + @param[in] XhciMmioBase xHCI Memory BAR0 address + @param[in] Usb2DisabledPorts Disabled ports bitmask with a bit for ea= ch USB2 port + i.e. BIT0 is Port 0, BIT1 is Port 1 etc + @param[in] Usb3DisabledPorts Disabled ports bitmask with a bit for ea= ch USB3 port + i.e. BIT0 is Port 0, BIT1 is Port 1 etc + + @retval EFI_SUCCESS Programming ended successfully and no er= rors occured + EFI_ACCESS_DENIED Port Disable Override register was locke= d and write + didn't go through. Platform may require = restart to unlock. +*/ +EFI_STATUS +UsbDisablePorts ( + IN UINTN XhciMmioBase, + IN UINT32 Usb2DisabledPorts, + IN UINT32 Usb3DisabledPorts + ); + +#endif // _USB_LIB_H diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h b/Silico= n/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h new file mode 100644 index 0000000000..86bed53c6f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/PcieRegs.h @@ -0,0 +1,319 @@ +/** @file + Register names for PCIE standard register + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_REGS_H_ +#define _PCIE_REGS_H_ + +#include + +// +// PCI type 0 Header +// +#define R_PCI_PI_OFFSET 0x09 +#define R_PCI_SCC_OFFSET 0x0A +#define R_PCI_BCC_OFFSET 0x0B + +// +// PCI type 1 Header +// +#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Reg= ister +#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordin= ate Bus Number +#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondar= y Bus Number +#define B_PCI_BRIDGE_BNUM_PBN 0x000000FF ///< Primary = Bus Number +#define B_PCI_BRIDGE_BNUM_SBBN_SCBN (B_PCI_BRIDGE_BNUM_SBBN = | B_PCI_BRIDGE_BNUM_SCBN) + +#define R_PCI_BRIDGE_IOBL 0x1C ///< I/O Base and L= imit Register + +#define R_PCI_BRIDGE_MBL 0x20 ///< Memory Base an= d Limit Register +#define B_PCI_BRIDGE_MBL_ML 0xFFF00000 ///< Memory L= imit +#define B_PCI_BRIDGE_MBL_MB 0x0000FFF0 ///< Memory B= ase + +#define R_PCI_BRIDGE_PMBL 0x24 ///< Prefetchable M= emory Base and Limit Register +#define B_PCI_BRIDGE_PMBL_PML 0xFFF00000 ///< Prefetch= able Memory Limit +#define B_PCI_BRIDGE_PMBL_I64L 0x000F0000 ///< 64-bit I= ndicator +#define B_PCI_BRIDGE_PMBL_PMB 0x0000FFF0 ///< Prefetch= able Memory Base +#define B_PCI_BRIDGE_PMBL_I64B 0x0000000F ///< 64-bit I= ndicator + +#define R_PCI_BRIDGE_PMBU32 0x28 ///< Prefetchable M= emory Base Upper 32-Bit Register +#define B_PCI_BRIDGE_PMBU32 0xFFFFFFFF + +#define R_PCI_BRIDGE_PMLU32 0x2C ///< Prefetchable M= emory Limit Upper 32-Bit Register +#define B_PCI_BRIDGE_PMLU32 0xFFFFFFFF + +// +// PCIE capabilities register +// +#define R_PCIE_CAP_ID_OFFSET 0x00 ///< Capability ID +#define R_PCIE_CAP_NEXT_PRT_OFFSET 0x01 ///< Next Capabilit= y Capability ID Pointer + +// +// PCI Express Capability List Register (CAPID:10h) +// +#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Ca= pabilities Register (Offset 02h) +#define S_PCIE_XCAP 2 +#define B_PCIE_XCAP_SI BIT8 ///< Slot Implement= ed +#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BI= T4) ///< Device/Port Type +#define N_PCIE_XCAP_DT 4 + +#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabil= ities Register (Offset 04h) +#define S_PCIE_DCAP 4 +#define B_PCIE_DCAP_RBER BIT15 ///< Role-Based Er= ror Reporting +#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) /= //< Endpoint L1 Acceptable Latency +#define N_PCIE_DCAP_E1AL 9 +#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///= < Endpoint L0s Acceptable Latency +#define N_PCIE_DCAP_E0AL 6 +#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///= < Max_Payload_Size Supported + +#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control= Register (Offset 08h) +#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///= < Max_Payload_Size +#define N_PCIE_DCTL_MPS 5 +#define B_PCIE_DCTL_URE BIT3 ///< Unsupported Re= quest Reporting Enable +#define B_PCIE_DCTL_FEE BIT2 ///< Fatal Error Re= porting Enable +#define B_PCIE_DCTL_NFE BIT1 ///< Non-Fatal Erro= r Reporting Enable +#define B_PCIE_DCTL_CEE BIT0 ///< Correctable Er= ror Reporting Enable + +#define R_PCIE_DSTS_OFFSET 0x0A ///< Device Status = Register (Offset 0Ah) +#define B_PCIE_DSTS_TDP BIT5 ///< Transactions P= ending +#define B_PCIE_DSTS_APD BIT4 ///< AUX Power Dete= cted +#define B_PCIE_DSTS_URD BIT3 ///< Unsupported Re= quest Detected +#define B_PCIE_DSTS_FED BIT2 ///< Fatal Error De= tected +#define B_PCIE_DSTS_NFED BIT1 ///< Non-Fatal Erro= r Detected +#define B_PCIE_DSTS_CED BIT0 ///< Correctable Er= ror Detected + +#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilit= ies Register (Offset 0Ch) +#define B_PCIE_LCAP_ASPMOC BIT22 ///< ASPM Optional= ity Compliance +#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power M= anagement +#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) = ///< L1 Exit Latency +#define N_PCIE_LCAP_EL1 15 +#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) = ///< L0s Exit Latency +#define N_PCIE_LCAP_EL0 12 +#define B_PCIE_LCAP_APMS (BIT11 | BIT10) ///< Act= ive State Power Management (ASPM) Support +#define B_PCIE_LCAP_APMS_L0S BIT10 +#define B_PCIE_LCAP_APMS_L1 BIT11 +#define N_PCIE_LCAP_APMS 10 +#define B_PCIE_LCAP_MLW 0x000003F0 ///< Maximum = Link Width +#define N_PCIE_LCAP_MLW 4 +#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BI= T0) ///< Max Link Speed +#define V_PCIE_LCAP_MLS_GEN3 3 + +#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control R= egister (Offset 10h) +#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock P= ower Management +#define B_PCIE_LCTL_ES BIT7 ///< Extended Synch +#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock C= onfiguration +#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link +#define B_PCIE_LCTL_LD BIT4 ///< Link Disable +#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Activ= e State Power Management (ASPM) Control +#define V_PCIE_LCTL_ASPM_L0S 1 +#define V_PCIE_LCTL_ASPM_L1 2 +#define V_PCIE_LCTL_ASPM_L0S_L1 3 + +#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Re= gister (Offset 12h) +#define B_PCIE_LSTS_LA BIT13 ///< Data Link Lay= er Link Active +#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Co= nfiguration +#define B_PCIE_LSTS_LT BIT11 ///< Link Training +#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated L= ink Width +#define N_PCIE_LSTS_NLW 4 +#define V_PCIE_LSTS_NLW_1 0x0010 +#define V_PCIE_LSTS_NLW_2 0x0020 +#define V_PCIE_LSTS_NLW_4 0x0040 +#define B_PCIE_LSTS_CLS 0x000F ///< Current Link= Speed +#define V_PCIE_LSTS_CLS_GEN1 1 +#define V_PCIE_LSTS_CLS_GEN2 2 +#define V_PCIE_LSTS_CLS_GEN3 3 + +#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilit= ies Register (Offset 14h) +#define S_PCIE_SLCAP 4 +#define B_PCIE_SLCAP_PSN 0xFFF80000 ///< Physical= Slot Number +#define B_PCIE_SLCAP_SLS 0x00018000 ///< Slot Pow= er Limit Scale +#define B_PCIE_SLCAP_SLV 0x00007F80 ///< Slot Pow= er Limit Value +#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug Capab= le +#define B_PCIE_SLCAP_HPS BIT5 ///< Hot-Plug Surpr= ise + +#define R_PCIE_SLCTL_OFFSET 0x18 ///< Slot Control R= egister (Offset 18h) +#define S_PCIE_SLCTL 2 +#define B_PCIE_SLCTL_HPE BIT5 ///< Hot Plug Inter= rupt Enable +#define B_PCIE_SLCTL_PDE BIT3 ///< Presence Detec= t Changed Enable + +#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Re= gister (Offset 1Ah) +#define S_PCIE_SLSTS 2 +#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detec= t State +#define B_PCIE_SLSTS_PDC BIT3 ///< Presence Detec= t Changed + +#define R_PCIE_RCTL_OFFSET 0x1C ///< Root Control R= egister (Offset 1Ch) +#define S_PCIE_RCTL 2 +#define B_PCIE_RCTL_PIE BIT3 ///< PME Interrupt = Enable +#define B_PCIE_RCTL_SFE BIT2 ///< System Error o= n Fatal Error Enable +#define B_PCIE_RCTL_SNE BIT1 ///< System Error o= n Non-Fatal Error Enable +#define B_PCIE_RCTL_SCE BIT0 ///< System Error o= n Correctable Error Enable + +#define R_PCIE_RSTS_OFFSET 0x20 ///< Root Status Re= gister (Offset 20h) +#define S_PCIE_RSTS 4 + +#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabil= ities 2 Register (Offset 24h) +#define B_PCIE_DCAP2_OBFFS (BIT19 | BIT18) ///< OBF= F Supported +#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism= Supported + +#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control= 2 Register (Offset 28h) +#define B_PCIE_DCTL2_OBFFEN (BIT14 | BIT13) ///< OBF= F Enable +#define N_PCIE_DCTL2_OBFFEN 13 +#define V_PCIE_DCTL2_OBFFEN_DIS 0 ///< Disabled +#define V_PCIE_DCTL2_OBFFEN_WAKE 3 ///< Enabled using WAK= E# signaling +#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism= Enable +#define B_PCIE_DCTL2_CTD BIT4 ///< Completion Tim= eout Disable +#define B_PCIE_DCTL2_CTV (BIT3 | BIT2 | BIT1 | BI= T0) ///< Completion Timeout Value +#define V_PCIE_DCTL2_CTV_DEFAULT 0x0 +#define V_PCIE_DCTL2_CTV_40MS_50MS 0x5 +#define V_PCIE_DCTL2_CTV_160MS_170MS 0x6 +#define V_PCIE_DCTL2_CTV_400MS_500MS 0x9 +#define V_PCIE_DCTL2_CTV_1P6S_1P7S 0xA + +#define R_PCIE_LCTL2_OFFSET 0x30 ///< Link Control 2= Register (Offset 30h) +#define B_PCIE_LCTL2_SD BIT6 ///< Selectable de-= emphasis (0 =3D -6dB, 1 =3D -3.5dB) +#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BI= T0) ///< Target Link Speed +#define V_PCIE_LCTL2_TLS_GEN1 1 +#define V_PCIE_LCTL2_TLS_GEN2 2 +#define V_PCIE_LCTL2_TLS_GEN3 3 + +#define R_PCIE_LSTS2_OFFSET 0x32 ///< Link Status 2 = Register (Offset 32h) +#define B_PCIE_LSTS2_LER BIT5 ///< Link Equalizat= ion Request +#define B_PCIE_LSTS2_EQP3S BIT4 ///< Equalization P= hase 3 Successful +#define B_PCIE_LSTS2_EQP2S BIT3 ///< Equalization P= hase 2 Successful +#define B_PCIE_LSTS2_EQP1S BIT2 ///< Equalization P= hase 1 Successful +#define B_PCIE_LSTS2_EC BIT1 ///< Equalization C= omplete +#define B_PCIE_LSTS2_CDL BIT0 ///< Current De-emp= hasis Level + +// +// PCI Power Management Capability (CAPID:01h) +// +#define R_PCIE_PMC_OFFSET 0x02 ///< Power Manageme= nt Capabilities Register +#define S_PCIE_PMC 2 +#define B_PCIE_PMC_PMES (BIT15 | BIT14 | BIT13 |= BIT12 | BIT11) ///< PME Support +#define B_PCIE_PMC_PMEC BIT3 ///< PME Clock + +#define R_PCIE_PMCS_OFFST 0x04 ///< Power Manageme= nt Status/Control Register +#define S_PCIE_PMCS 4 +#define B_PCIE_PMCS_BPCE BIT23 ///< Bus Power/Clo= ck Control Enable +#define B_PCIE_PMCS_B23S BIT22 ///< B2/B3 Support +#define B_PCIE_PMCS_PMES BIT15 ///< PME_Status +#define B_PCIE_PMCS_PMEE BIT8 ///< PME Enable +#define B_PCIE_PMCS_NSR BIT3 ///< No Soft Reset +#define B_PCIE_PMCS_PS (BIT1 | BIT0) ///< Power= State +#define V_PCIE_PMCS_PS_D0 0 +#define V_PCIE_PMCS_PS_D3H 3 + +// +// PCIE Extension Capability Register +// +#define B_PCIE_EXCAP_NCO 0xFFF00000 ///< Next Cap= ability Offset +#define N_PCIE_EXCAP_NCO 20 +#define V_PCIE_EXCAP_NCO_LISTEND 0 +#define B_PCIE_EXCAP_CV 0x000F0000 ///< Capabili= ty Version +#define N_PCIE_EXCAP_CV 16 +#define B_PCIE_EXCAP_CID 0x0000FFFF ///< Capabili= ty ID + +// +// Advanced Error Reporting Capability (CAPID:0001h) +// +#define V_PCIE_EX_AEC_CID 0x0001 ///< Capability ID +#define R_PCIE_EX_UEM_OFFSET 0x08 ///< Uncorrectable = Error Mask Register +#define B_PCIE_EX_UEM_CT BIT14 ///< Completion Ti= meout Mask +#define B_PCIE_EX_UEM_UC BIT16 ///< Unexpected Co= mpletion + +// +// ACS Extended Capability (CAPID:000Dh) +// +#define V_PCIE_EX_ACS_CID 0x000D ///< Capability ID +#define R_PCIE_EX_ACSCAPR_OFFSET 0x04 ///< ACS Capability= Register +//#define R_PCIE_EX_ACSCTLR_OFFSET 0x08 ///< ACS Control = Register (NOTE: register size in PCIE spce is not match the PCH register si= ze) + + +// +// Latency Tolerance Reporting Extended Capability Registers (CAPID:0018h) +// +#define R_PCH_PCIE_LTRECH_CID 0x0018 +#define R_PCH_PCIE_LTRECH_MSLR_OFFSET 0x04 +#define N_PCH_PCIE_LTRECH_MSLR_VALUE 0 +#define N_PCH_PCIE_LTRECH_MSLR_SCALE 10 +#define R_PCH_PCIE_LTRECH_MNSLR_OFFSET 0x06 +#define N_PCH_PCIE_LTRECH_MNSLR_VALUE 0 +#define N_PCH_PCIE_LTRECH_MNSLR_SCALE 10 +// +// Secondary PCI Express Extended Capability Header (CAPID:0019h) +// +#define V_PCIE_EX_SPE_CID 0x0019 ///< Capability ID +#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3= Register +#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equali= zation +#define R_PCIE_EX_LES_OFFSET 0x08 ///< Lane Error Sta= tus +#define R_PCIE_EX_L01EC_OFFSET 0x0C ///< Lane 0 and Lan= 1 Equalization Control Register (Offset 0Ch) +#define B_PCIE_EX_L01EC_UPL1TP 0x0F000000 ///< Upstream= Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_UPL1TP 24 +#define B_PCIE_EX_L01EC_DPL1TP 0x000F0000 ///< Downstre= am Port Lane 1 Transmitter Preset +#define N_PCIE_EX_L01EC_DPL1TP 16 +#define B_PCIE_EX_L01EC_UPL0TP 0x00000F00 ///< Upstream= Port Transmitter Preset +#define N_PCIE_EX_L01EC_UPL0TP 8 +#define B_PCIE_EX_L01EC_DPL0TP 0x0000000F ///< Downstre= am Port Transmitter Preset +#define N_PCIE_EX_L01EC_DPL0TP 0 + +#define R_PCIE_EX_L23EC_OFFSET 0x10 ///< Lane 2 and Lan= e 3 Equalization Control Register (Offset 10h) +#define B_PCIE_EX_L23EC_UPL3TP 0x0F000000 ///< Upstream= Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL3TP 24 +#define B_PCIE_EX_L23EC_DPL3TP 0x000F0000 ///< Downstre= am Port Lane 3 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL3TP 16 +#define B_PCIE_EX_L23EC_UPL2TP 0x00000F00 ///< Upstream= Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_UPL2TP 8 +#define B_PCIE_EX_L23EC_DPL2TP 0x0000000F ///< Downstre= am Port Lane 2 Transmitter Preset +#define N_PCIE_EX_L23EC_DPL2TP 0 + + +// +// L1 Sub-States Extended Capability Register (CAPID:001Eh) +// +#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID +#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States = Capabilities +#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpow= er_on value +#define N_PCIE_EX_L1SCAP_PTV 19 +#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port Tpow= er_on scale +#define N_PCIE_EX_L1SCAP_PTPOS 16 +#define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common Mo= de Restore time +#define N_PCIE_EX_L1SCAP_CMRT 8 +#define V_PCIE_EX_L1SCAP_PTPOS_2us 0 +#define V_PCIE_EX_L1SCAP_PTPOS_10us 1 +#define V_PCIE_EX_L1SCAP_PTPOS_100us 2 +#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substate= s supported +#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 supp= orted +#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 supp= orted +#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1 su= pported +#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2 su= pported +#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States = Control 1 +#define N_PCIE_EX_L1SCTL1_L12LTRTLSV 29 +#define N_PCIE_EX_L1SCTL1_L12LTRTLV 16 +#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States = Control 2 +#define N_PCIE_EX_L1SCTL2_POWT 3 + +// +// Base Address Offset +// +#define R_BASE_ADDRESS_OFFSET_0 0x0010 ///< Base Address= Register 0 +#define R_BASE_ADDRESS_OFFSET_1 0x0014 ///< Base Address= Register 1 +#define R_BASE_ADDRESS_OFFSET_2 0x0018 ///< Base Address= Register 2 +#define R_BASE_ADDRESS_OFFSET_3 0x001C ///< Base Address= Register 3 +#define R_BASE_ADDRESS_OFFSET_4 0x0020 ///< Base Address= Register 4 +#define R_BASE_ADDRESS_OFFSET_5 0x0024 ///< Base Address= Register 5 +#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2) +#define B_PCI_BAR_MEMORY_TYPE_64 BIT2 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h b/Si= licon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h new file mode 100644 index 0000000000..ac270e24fb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Ppi/SiPolicy.h @@ -0,0 +1,29 @@ +/** @file + Silicon Policy PPI is used for specifying platform + related Intel silicon information and policy setting. + This PPI is consumed by the silicon PEI modules and carried + over to silicon DXE modules. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_POLICY_PPI_H_ +#define _SI_POLICY_PPI_H_ + +#include +#include +#include +#include +#include +#include + +extern EFI_GUID gSiPreMemPolicyPpiGuid; +extern EFI_GUID gSiPolicyPpiGuid; + +typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI; +typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI; + +#endif // _SI_POLICY_PPI_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/Pci= eInitLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/Pci= eInitLib.h new file mode 100644 index 0000000000..fe676f8519 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/PcieInitLi= b.h @@ -0,0 +1,26 @@ +/** @file + PCIe Initialization Library header file + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_INIT_LIB_H_ +#define _PCIE_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/Usb= InitLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbI= nitLib.h new file mode 100644 index 0000000000..f05cf0fdea --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Private/Library/UsbInitLib= .h @@ -0,0 +1,71 @@ +/** @file + Header file for USB initialization library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USB_INIT_LIB_H_ +#define _USB_INIT_LIB_H_ + +#include + +/** + Common entry point for PCH and CPU xDCI controller + + @param[in] UsbConfig The USB_CONFIG policy instance + @param[in] XdciPciMmBase xDCI PCI config space address +**/ +VOID +XdciConfigure ( + IN USB_CONFIG *UsbConfig, + IN UINT64 XhciPciMmBase + ); + +/** + Common entry point for PCH and CPU xHCI controller + + @param[in] UsbConfig The USB_CONFIG policy instance + @param[in] XhciPciMmBase xHCI PCI config space address +**/ +VOID +XhciConfigure ( + IN USB_CONFIG *UsbConfig, + IN UINT64 XhciPciMmBase + ); + +/** + Configure xHCI after initialization + + @param[in] UsbConfig The USB_CONFIG policy instance + @param[in] XhciPciMmBase XHCI PCI CFG Base Address +**/ +VOID +XhciConfigureAfterInit ( + IN USB_CONFIG *UsbConfig, + IN UINT64 XhciPciMmBase + ); + +/** + Locks xHCI configuration by setting the proper lock bits in controller + + @param[in] UsbConfig The USB_CONFIG policy instance + @param[in] XhciPciBase xHCI PCI config space address +**/ +VOID +XhciLockConfiguration ( + IN USB_CONFIG *UsbConfig, + IN UINT64 XhciPciBase + ); + +/** + Tune the USB 2.0 high-speed signals quality. + + @param[in] UsbConfig The USB_CONFIG policy instance +**/ +VOID +Usb2AfeProgramming ( + IN USB_CONFIG *UsbConfig + ); +#endif // _USB_INIT_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyPr= otocol.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProt= ocol.h new file mode 100644 index 0000000000..671e94b3bc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Protocol/SiPolicyProtocol.h @@ -0,0 +1,60 @@ +/** @file + Protocol used for specifying platform related Silicon information and po= licy setting. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_POLICY_PROTOCOL_H_ +#define _SI_POLICY_PROTOCOL_H_ + +#include + +// +// DXE_SI_POLICY_PROTOCOL revisions +// +#define DXE_SI_POLICY_PROTOCOL_REVISION 2 + +extern EFI_GUID gDxeSiPolicyProtocolGuid; + +#pragma pack (push,1) + +/** + The protocol allows the platform code to publish a set of configuration = information that the + Silicon drivers will use to configure the processor in the DXE phase. + This Policy Protocol needs to be initialized for Silicon configuration. + @note The Protocol has to be published before processor DXE drivers are = dispatched. +**/ +typedef struct { + /** + This member specifies the revision of the Si Policy protocol. This field= is used to indicate backward + compatible changes to the protocol. Any such changes to this protocol wi= ll result in an update in the revision number. + + Revision 1: + - Initial version + Revision 2: + - Added SmbiosOemTypeFirmwareVersionInfo to determines the SMBIOS OEM t= ype + **/ + UINT8 Revision; + /** + SmbiosOemTypeFirmwareVersionInfo determines the SMBIOS OEM type (0x80 = to 0xFF) defined in SMBIOS, + values 0-0x7F will be treated as disable FVI reporting. + FVI structure uses it as SMBIOS OEM type to provide version informatio= n. + **/ + UINT8 SmbiosOemTypeFirmwareVersionInfo; + UINT8 ReservedByte[6]; ///< Reserved bytes, al= ign to multiple 8. + /** + This member describes a pointer to Hsti results from previous boot. In= order to mitigate the large performance cost + of performing all of the platform security tests on each boot, we can = save the results across boots and retrieve + and point this policy to them prior to the launch of HstiSiliconDxe. L= ogic should be implemented to not populate this + upon major platform changes (i.e changes to setup option or platform h= w)to ensure that results accurately reflect the + configuration of the platform. + **/ + ADAPTER_INFO_PLATFORM_SECURITY *Hsti; ///< This is a pointer to Hsti = results from previous boot + UINTN HstiSize; ///< Size of results, if settin= g Hsti policy to point to previous results +} DXE_SI_POLICY_PROTOCOL; + +#pragma pack (pop) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h new file mode 100644 index 0000000000..58a185c8fd --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/Register/RegsUsb.h @@ -0,0 +1,55 @@ +/** @file + Register names for USB Host and device controller + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _REGS_USB_H_ +#define _REGS_USB_H_ + +// +// USB3 (XHCI) related definitions +// @todo: Add CPU PCI defs for xHCI +// +#define PCI_BUS_NUMBER_PCH_XHCI 0 +#define PCI_DEVICE_NUMBER_PCH_XHCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0 + +// +// xDCI (OTG) USB Device Controller +// +#define PCI_DEVICE_NUMBER_PCH_XDCI 20 +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1 +#endif // _REGS_USB_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h new file mode 100644 index 0000000000..b5aeccbe5d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiConfigHob.h @@ -0,0 +1,19 @@ +/** @file + Silicon Config HOB is used for gathering platform + related Intel silicon information and config setting. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_CONFIG_HOB_H_ +#define _SI_CONFIG_HOB_H_ + +#include + +extern EFI_GUID gSiConfigHobGuid; + +// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB= structure. +typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA; +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h new file mode 100644 index 0000000000..da16aad257 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/SiPolicyStruct.h @@ -0,0 +1,65 @@ +/** @file + Intel reference code configuration policies. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_POLICY_STRUCT_H_ +#define _SI_POLICY_STRUCT_H_ + +#include +#include + +/** + Silicon Policy revision number + Any change to this structure will result in an update in the revision nu= mber + + This member specifies the revision of the Silicon Policy. This field is = used to indicate change + to the policy structure. + + Revision 1: + - Initial version. +**/ +#define SI_POLICY_REVISION 1 + +/** + Silicon pre-memory Policy revision number + Any change to this structure will result in an update in the revision nu= mber + + Revision 1: + - Initial version. +**/ +#define SI_PREMEM_POLICY_REVISION 1 + + +/** + SI Policy PPI in Pre-Mem\n + All SI config block change history will be listed here\n\n + + - Revision 1: + - Initial version.\n +**/ +struct _SI_PREMEM_POLICY_STRUCT { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +}; + +/** + SI Policy PPI\n + All SI config block change history will be listed here\n\n + + - Revision 1: + - Initial version.\n +**/ +struct _SI_POLICY_STRUCT { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +}; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfi= g.h b/Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h new file mode 100644 index 0000000000..7e056a25af --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Include/TraceHubCommonConfig.h @@ -0,0 +1,23 @@ +/** @file + Common configurations for CPU and PCH trace hub + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TRACE_HUB_COMMON_CONFIG_H_ +#define _TRACE_HUB_COMMON_CONFIG_H_ + +/// +/// The TRACE_HUB_ENABLE_MODE describes the desired TraceHub mode of opera= tion +/// +typedef enum { + TraceHubModeDisabled =3D 0, ///< TraceHub Disabled + TraceHubModeTargetDebugger =3D 1, ///< TraceHub Target Debugger mo= de, debug on target device itself, config to PCI mode + TraceHubModeHostDebugger =3D 2, ///< TraceHub Host Debugger mode= , debugged by host with cable attached, config to ACPI mode + TraceHubModeMax +} TRACE_HUB_ENABLE_MODE; + + +#endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45878): https://edk2.groups.io/g/devel/message/45878 Mute This Topic: https://groups.io/mt/32918169/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45879+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45879+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001011; cv=none; d=zoho.com; s=zohoarc; b=IXu0XZk6cG+xfTYI2ihWtrPVEA1ltl+cUugj9fY89Q9S/8iMRS3qO2RwY0FF2MNfdQTXnfUKxct0O64jXhBw7RwRJDM257pa7ZjM5DLCj9SDclyqzKhZOpbM2d7yppgiWCZFgRNzbfR52HKmglWuEQO1YLPwR654aRBp1uG15Js= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001011; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=A8FJ1diW9SzTBNKiPxr5rJqqmT5jMb/YtY4l1TGuQpo=; b=IrHSRcYVGo5NZZeaw0VNa8X6gB6Sq7bDVd2ZUrHY/RAcRhHTAoHo8cv+Kst43QkvrCzTcHAnrq29vJr0dHdr6yl7vhBJrZxHobzkNk7wjFaSDIWI5SW15Vf8ySv3ggmJvlMeiBIhSplN30CcQdlzAL3n+S14MMafuZspPNf9+W0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45879+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001011918996.8885868355615; Fri, 16 Aug 2019 17:16:51 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:50 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319227" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:48 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 02/37] CoffeelakeSiliconPkg/Cpu: Add Include headers Date: Fri, 16 Aug 2019 17:15:28 -0700 Message-Id: <20190817001603.30632-3-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001011; bh=/E3SGLBMDX+RDuq/c40vnKDe3L/Gn1zEwxJt7q4zQ1E=; h=Cc:Date:From:Reply-To:Subject:To; b=jnpRTJVsIX9gjtyJ61pfaxFF9WIlayKK33aChk4s0xV6wfR1QItOu/26vfWdyglAkXJ kPgt08bNqSgh4pPEMA6cDEsBxvl/KkQMk/Cy/XsmUwj1TFi/k3Gsp834AdedEBh6VIrL3 iqYoljUqmn1EnOnSAdJ3Ux94W6GHLYkLYI4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds header files common to CPU modules. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone Reviewed-by: Sai Chaganty =20 --- Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h = | 45 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPre= MemConfig.h | 106 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclocking= Config.h | 141 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfi= g.h | 54 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBas= icConfig.h | 179 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCus= tomConfig.h | 78 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTes= tConfig.h | 149 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h= | 66 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h = | 16 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h = | 113 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h = | 88 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h = | 23 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h = | 100 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h = | 261 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h = | 90 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib.h = | 118 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h = | 84 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h = | 123 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPolicyProtocol.= h | 50 ++++ 19 files changed, 1884 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= Config.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuCo= nfig.h new file mode 100644 index 0000000000..47a98131d0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h @@ -0,0 +1,45 @@ +/** @file + CPU Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_CONFIG_H_ +#define _CPU_CONFIG_H_ + +#define CPU_CONFIG_REVISION 3 + +extern EFI_GUID gCpuConfigGuid; + +#pragma pack (push,1) + +/** + CPU Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Deprecate and move SkipMpInit to CpuConfigLibPreMemConfig. + Revision 3: + - Move DebugInterfaceEnable from CPU_TEST_CONFIG. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Enable or Disable Advanced Encryption Standard (AES) feature. + For some countries, this should be disabled for legal reasons. + - 0: Disable + - 1: Enable + **/ + UINT32 AesEnable : 1; + UINT32 SkipMpInit : 1; ///< @deprecated since r= evision 2. For Fsp only, Silicon Initialization will skip MP Initialization= (including BSP) if enabled. For non-FSP, this should always be 0. + UINT32 DebugInterfaceEnable : 1; ///< Enable or Disable p= rocessor debug features; 0: Disable; 1: Enable. + UINT32 RsvdBits : 28; ///< Reserved for future= use + EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcod= e patch that is suitable for this processor. +} CPU_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= ConfigLibPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Co= nfigBlock/CpuConfigLibPreMemConfig.h new file mode 100644 index 0000000000..ce965a7510 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigL= ibPreMemConfig.h @@ -0,0 +1,106 @@ +/** @file + CPU Security PreMemory Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ +#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ + +#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 5 + +extern EFI_GUID gCpuConfigLibPreMemConfigGuid; + +#pragma pack (push,1) + +/** + CPU Config Library PreMemory Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Update for JTAG Power Gate comment. + Revision 3: + - Add PeciSxReset and PeciC10Reset + Revision 4: + - Add SkipMpInit + Revision 5: + - Add DpSscMarginEnable +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Thre= ading; 0: Disable; 1: Enable. + /** + Sets the boot frequency starting from reset vector. + - 0: Maximum battery performance. + - 1: Maximum non-turbo performance. + - 2: Turbo performance. + @note If Turbo is selected BIOS will start in max non-turbo mode and swi= tch to Turbo mode. + **/ + UINT32 BootFrequency : 2; + /** + Number of processor cores to enable. + - 0: All cores + - 1: 1 core + - 2: 2 cores + - 3: 3 cores + **/ + UINT32 ActiveCoreCount : 3; + UINT32 JtagC10PowerGateDisable : 1; ///< False: JTAG is power gated i= n C10 state. True: keeps the JTAG power up during C10 and deeper power stat= es for debug purpose. 0: False<\b>; 1: True. + UINT32 BistOnReset : 1; ///< (Test) Enable or Disa= ble BIST on Reset; 0: Disable; 1: Enable. + /** + Enable or Disable Virtual Machine Extensions (VMX) feature. + - 0: Disable + - 1: Enable + **/ + UINT32 VmxEnable : 1; + /** + Processor Early Power On Configuration FCLK setting. + - 0: 800 MHz (ULT/ULX). + - 1: 1 GHz (DT/Halo). Not supported on ULT/ULX. + - 2: 400 MHz. + - 3: Reserved. + **/ + UINT32 FClkFrequency : 2; + /** + Enables a mailbox command to resolve rare PECI related Sx issues. + @note This should only be used on systems that observe PECI Sx issues. + - 0: Disable + - 1: Enable + **/ + UINT32 PeciSxReset : 1; + /** + Enables the mailbox command to resolve PECI reset issues during Pkg-C1= 0 exit. + If Enabled, BIOS will send the CPU message to disable peci reset on C1= 0 exit. + The default value is 0: Disable for CNL, and 1: Enable f= or all other CPU's + - 0: Disable + - 1: Enable + **/ + UINT32 PeciC10Reset : 1; + /** + For Fsp only, Silicon Initialization will skip MP Initialization + (including BSP) if enabled. For non-FSP, this should always be 0. + - 0: Disable + - 1: Enable + **/ + UINT32 SkipMpInit : 1; + /** + Enable DisplayPort SSC range reduction + @note This should only be used on systems that exceeds allowed SSC mod= ulation range as defined in VESA's spec. + - 0: Disable + - 1: Enable + **/ + UINT32 DpSscMarginEnable : 1; + UINT32 RsvdBits : 17; + /** + CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRati= o. 0: Disabled If disabled, doesn't override max-non turbo ratio. + **/ + UINT8 CpuRatio; + UINT8 Reserved[3]; ///< Reserved for alignment +} CPU_CONFIG_LIB_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= OverclockingConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Confi= gBlock/CpuOverclockingConfig.h new file mode 100644 index 0000000000..a0b8a208e6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuOverclo= ckingConfig.h @@ -0,0 +1,141 @@ +/** @file + CPU Overclocking Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_OVERCLOCKING_PREMEM_CONFIG_H_ +#define _CPU_OVERCLOCKING_PREMEM_CONFIG_H_ + +#define CPU_OVERCLOCKING_CONFIG_REVISION 4 + +extern EFI_GUID gCpuOverclockingPreMemConfigGuid; + +#pragma pack (push,1) + +/** + CPU Overclocking Configuration Structure. + + Revision 1: + - Initial version. + Revision 2 + - Deprecate RingMinOcRatio + Revision 3 + - Change RingDownBin default to 'Enabled' + Revision 4 + - Add TvbRatioClipping, TvbVoltageOptimization + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Overclocking support. This controls whether OC mailbox transactions are = sent. + If disabled, all policies in this config block besides OcSupport and OcL= ock will be ignored. + 0: Disable; + 1: Enable. + @note If PcdOverclockEnable is disabled, this should also be disabled. + **/ + UINT32 OcSupport : 1; + UINT32 OcLock : 1; ///< If enabled, sets OC= lock bit in MSR 0x194[20], locking the OC mailbox and other OC configurati= on settings.; 0: Disable; 1: Enable (Lock). + /** + Core voltage mode, specifies which voltage mode the processor will be op= erating. + 0: Adaptive Mode allows the processor to interpolate a voltage cu= rve when beyond fused P0 range; + 1: Override, sets one voltage for for the entire frequency range, Pn-P0. + **/ + UINT32 CoreVoltageMode : 1; + UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage of= fset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. = 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize= possible ratio for SSE workload. + UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset. = 0: No offset. Range is 0-31. Used to lower the AVX3 ratio to maximiz= e possible ratio for SSE workload. + UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Volta= ge enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/= F curves are aware of BCLK frequency when calculated. + /** + Ring Downbin enable/disable. + When enabled, the CPU will force the ring ratio to be lower than the cor= e ratio. + Disabling will allow the ring and core ratios to run at the same frequen= cy. + Uses OC Mailbox command 0x19. + 0: Disables Ring Downbin feature. 1: Enables Ring downbin feature. + **/ + UINT32 RingDownBin : 1; + /** + Ring voltage mode, specifies which voltage mode the processor will be op= erating. + 0: Adaptive Mode allows the processor to interpolate a voltage cu= rve when beyond fused P0 range; + 1: Override, sets one voltage for for the entire frequency range, Pn-P0. + **/ + UINT32 RingVoltageMode : 1; + UINT32 RsvdBits : 10; ///< Reserved for future= use + + /** + Maximum core turbo ratio override allows to increase CPU core frequency = beyond the fused max turbo ratio limit (P0). + 0. no override/HW defaults.. Range 0-255. Max range varies by CPU= sku. + **/ + UINT8 CoreMaxOcRatio; + /** + The core voltage override which is applied to the entire range of cpu co= re frequencies. + Used when CoreVoltageMode =3D Override. + 0. no override. Range 0-2000 mV. + **/ + UINT16 CoreVoltageOverride; + /** + Adaptive Turbo voltage target used to define the interpolation voltage p= oint when the cpu is operating in turbo mode range. + Used when CoreVoltageMode =3D Adaptive. + 0. no override. Range 0-2000mV. + **/ + UINT16 CoreVoltageAdaptive; + /** + The core voltage offset applied on top of all other voltage modes. This = offset is applied over the entire frequency range. + This is a 2's complement number in mV units. Default: 0 Range: -1= 000 to 1000. + **/ + INT16 CoreVoltageOffset; + /** + Maximum ring ratio override allows to increase CPU ring frequency beyond= the fused max ring ratio limit. + 0. no override/HW defaults.. Range 0-255. Max range varies by CPU= sku. + **/ + UINT8 RingMaxOcRatio; + /** + The ring voltage override which is applied to the entire range of cpu ri= ng frequencies. + Used when RingVoltageMode =3D Override. + 0. no override. Range 0-2000 mV. + **/ + UINT16 RingVoltageOverride; + /** + Adaptive Turbo voltage target used to define the interpolation voltage p= oint when the ring is operating in turbo mode range. + Used when RingVoltageMode =3D Adaptive. + 0. no override. Range 0-2000mV. + **/ + UINT16 RingVoltageAdaptive; + /** + The ring voltage offset applied on top of all other voltage modes. This = offset is applied over the entire frequency range. + This is a 2's complement number in mV units. Default: 0 Range: -1= 000 to 1000. + **/ + INT16 RingVoltageOffset; + UINT8 RingMinOcRatio; ///< Deprecated since re= v 2. Minimum ring ratio override. 0: Hardware defaults. Range: 0-83. + UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offs= et. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage of= fset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL vo= ltage offset. 0: No offset. Range 0-63 in 17.5mv units. + UINT32 McPllVoltageOffset : 6; ///< Memory Controller P= LL voltage offset. 0: No offset. Range 0-63 in 17.5mv units. + /** + This service controls Core frequency reduction caused by high package te= mperatures for processors that + implement the Intel Thermal Velocity Boost (TVB) feature. It is required= to be disabled for supporting + overclocking at frequencies higher than the default max turbo frequency. + 0: Disables TVB ratio clipping. 1: Enables TVB ratio clipping. + **/ + UINT32 TvbRatioClipping : 1; + /** + This service controls thermal based voltage optimizations for processors= that implement the Intel + Thermal Velocity Boost (TVB) feature. + 0: Disables TVB voltage optimization. 1: Enables TVB voltage optimiza= tion. + **/ + UINT32 TvbVoltageOptimization : 1; + + UINT32 RsvdBits1 : 6; + /** + TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offs= et) to support TjMax in the range of 62 to 115 deg Celsius. + Default: 0 Hardware Defaults Range 0 to 63. + **/ + UINT8 TjMaxOffset; +} CPU_OVERCLOCKING_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_OVERCLOCKING_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= PidTestConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBloc= k/CpuPidTestConfig.h new file mode 100644 index 0000000000..e45f335ff9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTest= Config.h @@ -0,0 +1,54 @@ +/** @file + CPU PID Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PID_TEST_CONFIG_H_ +#define _CPU_PID_TEST_CONFIG_H_ + +#define CPU_PID_TEST_CONFIG_REVISION 1 + +extern EFI_GUID gCpuPidTestConfigGuid; + +#pragma pack (push,1) + +/** + PID Tuning Configuration Structure. + Domain is mapped to Kp =3D 0, Ki =3D 1, Kd =3D 2. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT16 Ratl[3]; ///< RATL setting, in 1/= 256 units. Range is 0 - 65280 + UINT16 VrTdcVr0[3]; ///< VR Thermal Design C= urrent for VR0. In 1/256 units. Range is 0 - 65280 + UINT16 VrTdcVr1[3]; ///< VR Thermal Design C= urrent for VR1. In 1/256 units. Range is 0 - 65280 + UINT16 VrTdcVr2[3]; ///< VR Thermal Design C= urrent for VR2. In 1/256 units. Range is 0 - 65280 + UINT16 VrTdcVr3[3]; ///< VR Thermal Design C= urrent for VR3. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPsysPl1Msr[3]; ///< Power Budget Manage= ment Psys PL1 MSR. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPsysPl1MmioPcs[3]; ///< Power Budget Manage= ment Psys PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPsysPl2Msr[3]; ///< Power Budget Manage= ment Psys PL2 MSR. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPsysPl2MmioPcs[3]; ///< Power Budget Manage= ment Psys PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPkgPl1Msr[3]; ///< Power Budget Manage= ment Package PL1 MSR. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPkgPl1MmioPcs[3]; ///< Power Budget Manage= ment Package PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPkgPl2Msr[3]; ///< Power Budget Manage= ment Package PL2 MSR. In 1/256 units. Range is 0 - 65280 + UINT16 PbmPkgPl2MmioPcs[3]; ///< Power Budget Manage= ment Package PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280 + UINT16 DdrPl1Msr[3]; ///< DDR PL1 MSR. In 1/2= 56 units. Range is 0 - 65280 + UINT16 DdrPl1MmioPcs[3]; ///< DDR PL1 MMIO/PCS. I= n 1/256 units. Range is 0 - 65280 + UINT16 DdrPl2Msr[3]; ///< DDR PL2 MSR. In 1/2= 56 units. Range is 0 - 65280 + UINT16 DdrPl2MmioPcs[3]; ///< DDR PL2 MMIO/PCS. I= n 1/256 units. Range is 0 - 65280 + /** + Enable or Disable PID Tuning programming flow. + If disabled, all other policies in this config block are ignored. + **/ + UINT8 PidTuning; + UINT8 Rsvd; ///< Reserved for DWORD = alignment. +} CPU_PID_TEST_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_PID_TEST_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= PowerMgmtBasicConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Con= figBlock/CpuPowerMgmtBasicConfig.h new file mode 100644 index 0000000000..2ad474b7e9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMg= mtBasicConfig.h @@ -0,0 +1,179 @@ +/** @file + CPU Power Management Basic Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_ +#define _CPU_POWER_MGMT_BASIC_CONFIG_H_ + +#define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 2 + +extern EFI_GUID gCpuPowerMgmtBasicConfigGuid; + +#pragma pack (push,1) + +/** + CPU Power Management Basic Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Added MinRingRatioLimit + - Added MaxRingRatioLimit +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Sets the boot frequency starting from reset vector. + - 0: Maximum battery performance. + - 1: Maximum non-turbo performance. + - 2: Turbo performance. + @note If Turbo is selected BIOS will start in max non-turbo mode and swi= tch to Turbo mode. + **/ + UINT32 BootFrequency : 2; + UINT32 SkipSetBootPState : 1; ///< Choose whether to s= kip SetBootPState function for all APs; 0: Do not skip; 1: Skip. + /** + Enable or Disable Intel Speed Shift Technology. + Enabling allows for processor control of P-state transitions. + 0: Disable; 1: Enable; Bit 1 is ignored. + @note Currently this feature is recommended to be enabled only on win10 + **/ + UINT32 Hwp : 2; + /** + Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved + HDC enables the processor to autonomously force components to enter into= an idle state to lower effective frequency. + This allows for increased package level C6 residency. + @note Currently this feature is recommended to be enabled only on win10 + **/ + UINT32 HdcControl : 2; + UINT32 PowerLimit2 : 1; ///< Enable or Disable s= hort duration Power Limit (PL2). 0: Disable; 1: Enable + UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and 0= x618[63]: Locks all Turbo power limit settings to read-only; 0: Disable<= /b>; 1: Enable (Lock). + UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty Cy= cle. Specifies the PL3 duty cycle percentage, Range 0-100. Default: 0. + UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 615= h lock; 0: Disable; 1: Enable (Lock). + UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 601= h lock; 0: Disable; 1: Enable (Lock). + /** + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU= to throttle below P1. + For Y SKU, the recommended default for this policy is 1: Enabled,= which indicates throttling below P1 is allowed. + For all other SKUs the recommended default are 0: Disabled. + **/ + UINT32 TccOffsetClamp : 1; + UINT32 TccOffsetLock : 1; ///< Tcc Offset Lock for= Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A= 2h; 0: Disabled; 1: Enabled (Lock). + UINT32 TurboMode : 1; ///< Enable or Disable T= urbo Mode. Disable; 1: Enable + UINT32 HwpInterruptControl : 1; ///< Set HW P-State Inte= rrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; 0: Disable; 1: Enabl= e. + + UINT32 RsvdBits : 9; ///< Reserved for future= use. + + /** + 1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking p= arts: LFM to Fused 1-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 1-Core Ratio Limit Must be greater than or equal to 2-Core Rat= io Limit, 3-Core Ratio Limit, 4-Core Ratio Limit. + **/ + UINT8 OneCoreRatioLimit; + /** + 2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking p= art: LFM to Fused 2-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 TwoCoreRatioLimit; + /** + 3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking p= art: LFM to Fused 3-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 ThreeCoreRatioLimit; + /** + 4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking p= art: LFM to Fused 4-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 FourCoreRatioLimit; + /** + 5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking p= art: LFM to Fused 5-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 FiveCoreRatioLimit; + /** + 6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking p= art: LFM to Fused 6-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 SixCoreRatioLimit; + /** + 7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking p= art: LFM to Fused 7-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 SevenCoreRatioLimit; + /** + 8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking p= art: LFM to Fused 8-Core Ratio Limit + OC Bins. + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 255. + - This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit. + **/ + UINT8 EightCoreRatioLimit; + /** + TCC Activation Offset. Offset from factory set TCC activation temperatur= e at which the Thermal Control Circuit must be activated. + TCC will be activated at (TCC Activation Temperature - TCC Activation Of= fset), in degrees Celcius. + For Y SKU, the recommended default for this policy is 15 + For all other SKUs the recommended default are 0, causing TCC to = activate at TCC Activation temperature. + @note The policy is recommended for validation purpose only. + **/ + UINT8 TccActivationOffset; + /** + Intel Turbo Boost Max Technology 3.0 + Enabling it on processors with OS support will allow OS to exploit the d= iversity in max turbo frequency of the cores. + 0: Disable; 1: Enable; + **/ + UINT8 EnableItbm : 1; + /** + Intel Turbo Boost Max Technology 3.0 Driver + Enabling it will load the driver upon ACPI device with HID =3D INT3510. + 0: Disable; 1: Enable; + **/ + UINT8 EnableItbmDriver : 1; + UINT8 ReservedBits1 : 6; ///< Reserved for future= use. + UINT8 MinRingRatioLimit; ///< Minimum Ring Ratio = Limit. Range from 0 to Max Turbo Ratio. 0 =3D AUTO/HW Default + UINT8 MaxRingRatioLimit; ///< Maximum Ring Ratio = Limit. Range from 0 to Max Turbo Ratio. 0 =3D AUTO/HW Default + + /** + Package Long duration turbo mode power limit (PL1). + Default is the TDP power limit of processor. Units are based on POWER_MG= MT_CONFIG.CustomPowerUnit. + **/ + UINT16 PowerLimit1; + /** + Package Short duration turbo mode power limit (PL2). Allows for short ex= cursions above TDP power limit. + Default =3D 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG= .CustomPowerUnit. + **/ + UINT16 PowerLimit2Power; + /** + Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit. + Default: 0. Range 0-65535. Units are based on POWER_MGMT_CONFIG.C= ustomPowerUnit. + **/ + UINT16 PowerLimit3; + /** + Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power Limi= t, it will never be exceeded. + Power is premptively lowered before limit is reached. Default: 0.= Range 0-65535. + Units are based on POWER_MGMT_CONFIG.CustomPowerUnit. + **/ + UINT16 PowerLimit4; + /** + Package Long duration turbo mode power limit (PL1) time window in second= s. + Used in calculating the average power over time. + Default: 0 - AUTO, auto will program 28 seconds. + Range: 0 - 128s + **/ + UINT32 PowerLimit1Time; + UINT32 PowerLimit3Time; ///< Package PL3 time wi= ndow. Range from 3ms to 64ms. + /** + Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Averag= e Temperature Limit (RATL). + For Y SKU, the recommended default for this policy is 5000: 5 seconds= , For all other SKUs the recommended default are 0: Disabled + **/ + UINT32 TccOffsetTimeWindowForRatl; +} CPU_POWER_MGMT_BASIC_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= PowerMgmtCustomConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Co= nfigBlock/CpuPowerMgmtCustomConfig.h new file mode 100644 index 0000000000..7eb91fa3ee --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMg= mtCustomConfig.h @@ -0,0 +1,78 @@ +/** @file + CPU Power Managment Custom Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ +#define _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ + +#define CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION 1 + +extern EFI_GUID gCpuPowerMgmtCustomConfigGuid; + +#pragma pack (push,1) + +/// +/// Defines the maximum number of custom ratio states supported. +/// +#define MAX_CUSTOM_RATIO_TABLE_ENTRIES 40 +#define MAX_16_CUSTOM_RATIO_TABLE_ENTRIES 16 + +/// +/// Defines the maximum number of custom ConfigTdp entries supported. +/// @warning: Changing this define would cause DWORD alignment issues in p= olicy structures. +/// +#define MAX_CUSTOM_CTDP_ENTRIES 3 + +/// +/// This structure is used to describe the custom processor ratio table de= sired by the platform. +/// +typedef struct { + UINT8 MaxRatio; ///< The maxi= mum ratio of the custom ratio table. + UINT8 NumberOfEntries; ///< The numb= er of custom ratio state entries, ranges from 2 to 40 for a valid custom ra= tio table. + UINT8 Rsvd0[2]; ///< Reserved= for DWORD alignment. + UINT32 Cpuid; ///< The CPU = ID for which this custom ratio table applies. + UINT8 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The proc= essor ratios in the custom ratio table. + /// + /// If there are more than 16 total entries in the StateRatio table, the= n use these 16 entries to fill max 16 table. + /// @note If NumberOfEntries is 16 or less, or the first entry of this t= able is 0, then this table is ignored, + /// and up to the top 16 values from the StateRatio table is used instea= d. + /// + UINT8 StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES]; +#if ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) = % 4) + UINT8 Rsvd1[4 - ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_= TABLE_ENTRIES) % 4)]; ///< If needed, add padding for dword alignment. +#endif +} PPM_CUSTOM_RATIO_TABLE; + +/// +/// PPM Custom ConfigTdp Settings +/// +typedef struct _PPM_CUSTOM_CTDP_TABLE { + UINT32 CustomPowerLimit1Time : 8; ///< Short term Power= Limit time window value for custom cTDP level. + UINT32 CustomTurboActivationRatio : 8; ///< Turbo Activation= Ratio for custom cTDP level. + UINT32 RsvdBits : 16; ///< Bits reserved fo= r DWORD alignment. + UINT16 CustomPowerLimit1; ///< Short term Power= Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.Cu= stomPowerUnit. + UINT16 CustomPowerLimit2; ///< Long term Power = Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.Cus= tomPowerUnit. +} PPM_CUSTOM_CTDP_TABLE; + +/** + CPU Power Management Custom Configuration Structure. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header + PPM_CUSTOM_RATIO_TABLE CustomRatioTable; = ///< Custom Processor Ratio Table Instance + PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]; = ///< Custom ConfigTdp Settings Instance + UINT32 ConfigTdpLock : 1; = ///< Lock the ConfigTdp mode settings from runtime changes; 0: Dis= able; 1: Enable. + UINT32 ConfigTdpBios : 1; = ///< Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; = ///< Reserved for future use +} CPU_POWER_MGMT_CUSTOM_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_POWER_MGMT_CUSTOM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= PowerMgmtTestConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Conf= igBlock/CpuPowerMgmtTestConfig.h new file mode 100644 index 0000000000..cb9b20249f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMg= mtTestConfig.h @@ -0,0 +1,149 @@ +/** @file + CPU Power Management Test Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_ +#define _CPU_POWER_MGMT_TEST_CONFIG_H_ + +#define CPU_POWER_MGMT_TEST_CONFIG_REVISION 3 + +extern EFI_GUID gCpuPowerMgmtTestConfigGuid; + +#pragma pack (push,1) + +/// +/// PPM Package C State Limit +/// +typedef enum { + PkgC0C1 =3D 0, + PkgC2, + PkgC3, + PkgC6, + PkgC7, + PkgC7s, + PkgC8, + PkgC9, + PkgC10, + PkgCMax, + PkgCpuDefault =3D 254, + PkgAuto =3D 255 +} MAX_PKG_C_STATE; + +/// +/// PPM Package C State Time Limit +/// +typedef enum { + TimeUnit1ns =3D 0, + TimeUnit32ns, + TimeUnit1024ns, + TimeUnit32768ns, + TimeUnit1048576ns, + TimeUnit33554432ns, + TimeUnitMax +} C_STATE_TIME_UNIT; + +/// +/// Custom Power Units. User can choose to enter in watts or 125 milliwatt= increments. +/// +typedef enum { + PowerUnitWatts =3D 0, ///< in Watts. + PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90 po= wer units times 125 mW equals 11.250 W. + PowerUnitMax +} CUSTOM_POWER_UNIT; + +/// +/// PPM Interrupt Redirection Mode Selection +/// +typedef enum { + PpmIrmFixedPriority =3D 0, + PpmIrmRoundRobin, + PpmIrmHashVector, + PpmIrmReserved1, + PpmIrmPairFixedPriority, + PpmIrmPairRoundRobin, + PpmIrmPairHashVector, + PpmIrmNoChange +} PPM_IRM_SETTING; + +/** + CPU Power Management Test Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Update PkgCStateDemotion and PkgCStateUnDemotion to be Disable. + Revision 3: + - Add CstateLatencyControl0TimeUnit for CFL only + - Add CstateLatencyControl0Irtl for CFL only +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Confi= g Block Header + UINT32 Eist : 1; ///< Offset 28-31 Enabl= e or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable + UINT32 EnergyEfficientPState : 1; ///< Enabl= e or Disable Energy Efficient P-state will be applied in Turbo mode. Disabl= e; 1: Enable + UINT32 EnergyEfficientTurbo : 1; ///< Enabl= e or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable= ; 1: Enable + UINT32 TStates : 1; ///< Enabl= e or Disable T states; 0: Disable; 1: Enable. + UINT32 BiProcHot : 1; ///< Enabl= e or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable. + UINT32 DisableProcHotOut : 1; ///< Enabl= e or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Ena= ble. + UINT32 ProcHotResponse : 1; ///< Enabl= e or Disable PROCHOT# Response; 0: Disable; 1: Enable. + UINT32 DisableVrThermalAlert : 1; ///< Enabl= e or Disable VR Thermal Alert; 0: Disable; 1: Enable. + UINT32 AutoThermalReporting : 1; ///< Enabl= e or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enabl= e. + UINT32 ThermalMonitor : 1; ///< Enabl= e or Disable Thermal Monitor; 0: Disable; 1: Enable. + UINT32 Cx : 1; ///< Enabl= e or Disable CPU power states (C-states). 0: Disable; 1: Enable + UINT32 PmgCstCfgCtrlLock : 1; ///< If en= abled, sets MSR 0xE2[15]; 0: Disable; 1: Enable. + UINT32 C1e : 1; ///< Enabl= e or Disable Enhanced C-states. 0: Disable; 1: Enable + UINT32 C1AutoDemotion : 1; ///< Enabl= e or Disable C6/C7 auto demotion to C1. 0: Disabled; 1: C1 Auto demotion= + UINT32 C1UnDemotion : 1; ///< Enabl= e or Disable C1UnDemotion. 0: Disabled; 1: C1 Auto undemotion + UINT32 C3AutoDemotion : 1; ///< [Coff= eeLake Only] Enable or Disable C6/C7 auto demotion to C3 0: Disabled; 1= : C3 Auto demotion + UINT32 C3UnDemotion : 1; ///< [Coff= eeLake Only] Enable or Disable C3UnDemotion. 0: Disabled; 1: C3 Auto und= emotion + UINT32 PkgCStateDemotion : 1; ///< Enabl= e or Disable Package Cstate Demotion. [Cannonlake Y] 0: Disable; 1: Enab= le [CoffeeLake] Disable; 1: Enable + UINT32 PkgCStateUnDemotion : 1; ///< Enabl= e or Disable Package Cstate UnDemotion. 0: [Cannonlake Y] 0: Disable; 1= : Enable [CoffeeLake] Disable; 1: Enable + UINT32 CStatePreWake : 1; ///< Enabl= e or Disable CState-Pre wake. Disable; 1: Enable + UINT32 TimedMwait : 1; ///< Enabl= e or Disable TimedMwait Support. Disable; 1: Enable + UINT32 CstCfgCtrIoMwaitRedirection : 1; ///< Enabl= e or Disable IO to MWAIT redirection; 0: Disable; 1: Enable. + UINT32 ProcHotLock : 1; ///< If en= abled, sets MSR 0x1FC[23]; 0: Disable; 1: Enable. + UINT32 RaceToHalt : 1; ///< Enabl= e or Disable Race To Halt feature; 0: Disable; 1: Enable . RTH will = dynamically increase CPU frequency in order to enter pkg C-State faster to = reduce overall power. (RTH is controlled through MSR 1FC bit 20) + UINT32 ConfigTdpLevel : 8; ///< Confi= guration for boot TDP selection; 0: TDP Nominal; 1: TDP Down; 2: TDP= Up. + UINT16 CstateLatencyControl1Irtl; ///< Offset 32-33 Inter= rupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0]. + UINT16 CstateLatencyControl2Irtl; ///< Offset 34-35 Inter= rupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0]. + UINT16 CstateLatencyControl3Irtl; ///< Offset 36-37 Inter= rupt Response Time Limit of LatencyContol3 MSR 0x633[9:0]. + UINT16 CstateLatencyControl4Irtl; ///< Offset 38-39 Inter= rupt Response Time Limit of LatencyContol4 MSR 0x634[9:0]. + UINT16 CstateLatencyControl5Irtl; ///< Offset 40-41 Inter= rupt Response Time Limit of LatencyContol5 MSR 0x635[9:0]. + UINT16 CstateLatencyControl0Irtl; ///< Offset 42-43 Inter= rupt Response Time Limit of LatencyContol1 MSR 0x60A[9:0]. + MAX_PKG_C_STATE PkgCStateLimit; ///< Offset 44 This = field is used to set the Max Pkg Cstate. Default set to Auto which limits t= he Max Pkg Cstate to deep C-state. + /** + @todo: The following enums have to be replaced with policies. + **/ + C_STATE_TIME_UNIT CstateLatencyControl0TimeUnit; ///< Offset 45 TimeU= nit for Latency Control0 MSR 0x60A[12:10]; (CFL)2: 1024ns + C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46 TimeU= nit for Latency Control1 MSR 0x60B[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47 TimeU= nit for Latency Control2 MSR 0x60C[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48 TimeU= nit for Latency Control3 MSR 0x633[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49 TimeU= nit for Latency Control4 MSR 0x634[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50 TimeU= nit for Latency Control5 MSR 0x635[12:10]; (CFL)2: 1024ns, (CNL)3: 32768ns + /** + Offset 51 Default power unit in watts or in 125 milliwatt increments. + - 0: PowerUnitWatts. + - 1: PowerUnit125MilliWatts. + **/ + CUSTOM_POWER_UNIT CustomPowerUnit; + /** + Offset 52 Interrupt Redirection Mode Select. + - 0: Fixed priority. + - 1: Round robin. + - 2: Hash vector. + - 4: PAIR with fixed priority. + - 5: PAIR with round robin. + - 6: PAIR with hash vector. + - 7: No change. + **/ + PPM_IRM_SETTING PpmIrmSetting; + // Move the padding to previous offset to align the structure at 32-bit = address. + UINT8 Rsvd[4]; ///< Offset 53-56 Reserv= ed for future use and config block alignment +} CPU_POWER_MGMT_TEST_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_POWER_MGMT_TEST_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= TestConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/C= puTestConfig.h new file mode 100644 index 0000000000..b94eb5e263 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestCon= fig.h @@ -0,0 +1,66 @@ +/** @file + CPU Test Config Block. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_TEST_CONFIG_H_ +#define _CPU_TEST_CONFIG_H_ + +#define CPU_TEST_CONFIG_REVISION 4 + +extern EFI_GUID gCpuTestConfigGuid; + +#pragma pack (push,1) + +/** + CPU Test Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Fixed RsvdBits incorrect value. + Revision 3: + - Added CpuWakeUpTimer + Revision 4: + - Deprecate and move DebugInterfaceEnable to CPU_CONFIG. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 MlcStreamerPrefetcher : 1; ///< Enab= le or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable. + UINT32 MlcSpatialPrefetcher : 1; ///< Enab= le or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable. + UINT32 MonitorMwaitEnable : 1; ///< Enab= le or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable. + UINT32 MachineCheckEnable : 1; ///< Enab= le or Disable initialization of machine check registers; 0: Disable; 1: = Enable. + UINT32 DebugInterfaceEnable : 1; ///< @dep= recated Enable or Disable processor debug features; 0: Disable; 1: E= nable. + UINT32 DebugInterfaceLockEnable : 1; ///< Lock= or Unlock debug interface features; 0: Disable; 1: Enable. + UINT32 ProcessorTraceOutputScheme : 1; ///< Cont= rol on Processor Trace output scheme; 0: Single Range Output; 1: ToP= A Output. + UINT32 ProcessorTraceEnable : 1; ///< Enab= le or Disable Processor Trace feature; 0: Disable; 1: Enable. + UINT32 ThreeStrikeCounterDisable : 1; ///< Disa= ble Three strike counter; 0: FALSE; 1: TRUE. + /** + This policy should be used to enable or disable Voltage Optimization f= eature. + Recommended defaults: + Enable - For Mobile SKUs(U/Y) + Disable - Rest of all SKUs other than Mobile. + **/ + UINT32 VoltageOptimization : 1; + UINT32 CpuWakeUpTimer : 1; ///< Ena= ble or Disable long CPU wake up timer. 0: Disabled (8s); 1: Enabled (180= s). + UINT32 RsvdBits : 21; ///< Res= erved for future use + /** + Base address of memory region allocated for Processor Trace. + Processor Trace requires 2^N alignment and size in bytes per thread, = from 4KB to 128MB. + - NULL: Disable + **/ + EFI_PHYSICAL_ADDRESS ProcessorTraceMemBase; + /** + Length in bytes of memory region allocated for Processor Trace. + Processor Trace requires 2^N alignment and size in bytes per thread, = from 4KB to 128MB. + - 0: Disable + **/ + UINT32 ProcessorTraceMemLength; +} CPU_TEST_CONFIG; + +#pragma pack (pop) + +#endif // _CPU_TEST_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h b/S= ilicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h new file mode 100644 index 0000000000..48fdbdd012 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuAccess.h @@ -0,0 +1,16 @@ +/** @file + Macros to simplify and abstract the interface to CPU configuration. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPUACCESS_H_ +#define _CPUACCESS_H_ + +#include "CpuRegs.h" +#include "CpuDataStruct.h" +#include "CpuPowerMgmt.h" + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h= b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h new file mode 100644 index 0000000000..2382e60dca --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuDataStruct.h @@ -0,0 +1,113 @@ +/** @file + This file declares various data structures used in CPU reference code. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_DATA_STRUCT_H +#define _CPU_DATA_STRUCT_H + +// +// The reason for changing the state of the processor Only applies to Disa= bling processors. +// In future, we can add add/remove support +// +#define CPU_CAUSE_NOT_DISABLED 0x0000 +#define CPU_CAUSE_INTERNAL_ERROR 0x0001 +#define CPU_CAUSE_THERMAL_ERROR 0x0002 +#define CPU_CAUSE_SELFTEST_FAILURE 0x0004 +#define CPU_CAUSE_PREBOOT_TIMEOUT 0x0008 +#define CPU_CAUSE_FAILED_TO_START 0x0010 +#define CPU_CAUSE_CONFIG_ERROR 0x0020 +#define CPU_CAUSE_USER_SELECTION 0x0080 +#define CPU_CAUSE_BY_ASSOCIATION 0x0100 +#define CPU_CAUSE_UNSPECIFIED 0x8000 + +typedef UINT32 CPU_STATE_CHANGE_CAUSE; + +/// +/// Structure to hold the return value of AsmCpuid instruction +/// +typedef struct { + UINT32 RegEax; ///< Value of EAX. + UINT32 RegEbx; ///< Value of EBX. + UINT32 RegEcx; ///< Value of ECX. + UINT32 RegEdx; ///< Value of EDX. +} EFI_CPUID_REGISTER; + +/// +/// Structure to describe microcode header +/// +typedef struct { + UINT32 HeaderVersion; ///< Version number of the update header. + UINT32 UpdateRevision; ///< Unique version number for the update. + UINT32 Date; ///< Date of the update creation. + UINT32 ProcessorId; ///< Signature of the processor that requires thi= s update. + UINT32 Checksum; ///< Checksum of update data and header. + UINT32 LoaderRevision; ///< Version number of the microcode loader progr= am. + UINT32 ProcessorFlags; ///< Lower 4 bits denoting platform type informat= ion. + UINT32 DataSize; ///< Size of encoded data in bytes. + UINT32 TotalSize; ///< Total size of microcode update in bytes. + UINT8 Reserved[12]; ///< Reserved bits. +} CPU_MICROCODE_HEADER; + +/// +/// Structure to describe the extended signature table header of the micro= code update +/// +typedef struct { + UINT32 ExtendedSignatureCount; ///< Number of extended signature structu= res. + UINT32 ExtendedTableChecksum; ///< Checksum of update extended processo= r signature table. + UINT8 Reserved[12]; ///< Reserved bits. +} CPU_MICROCODE_EXTENDED_TABLE_HEADER; + +/// +/// Structure to describe the data of the extended table of the microcode = update +/// +typedef struct { + UINT32 ProcessorSignature; ///< Extended signature of the processor that= requires this update + UINT32 ProcessorFlag; ///< Lower 4 bits denoting platform type info= rmation + UINT32 ProcessorChecksum; ///< checksum of each of the extended update +} CPU_MICROCODE_EXTENDED_TABLE; + +#pragma pack(1) +/// +/// MSR_REGISTER definition as a Union of QWORDS, DWORDS and BYTES +/// +typedef union _MSR_REGISTER { + UINT64 Qword; ///< MSR value in 64 bit QWORD. + + /// + /// MSR value represented in two DWORDS + /// + struct { + UINT32 Low; ///< Lower DWORD of the 64 bit MSR value. + UINT32 High; ///< Higher DWORD of the 64 bit MSR value. + } Dwords; + + /// + /// MSR value represented in eight bytes. + /// + struct { + UINT8 FirstByte; ///< First byte of the 64 bit MSR value. + UINT8 SecondByte; ///< Second byte of the 64 bit MSR value. + UINT8 ThirdByte; ///< Third byte of the 64 bit MSR value. + UINT8 FouthByte; ///< Fourth byte of the 64 bit MSR value. + UINT8 FifthByte; ///< Fifth byte of the 64 bit MSR value. + UINT8 SixthByte; ///< Sixth byte of the 64 bit MSR value. + UINT8 SeventhByte; ///< Seventh byte of the 64 bit MSR value. + UINT8 EighthByte; ///< Eigth byte of the 64 bit MSR value. + } Bytes; +} MSR_REGISTER; + +/// +/// Store BIST data for BSP. +/// +typedef struct { + UINT32 ApicId; ///< APIC ID + UINT32 Health; ///< BIST result +} BIST_HOB_DATA; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h= b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h new file mode 100644 index 0000000000..4862d62975 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuNvsAreaDef.h @@ -0,0 +1,88 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // + // Define CPU NVS Area operation region. + // + +#ifndef _CPU_NVS_AREA_DEF_H_ +#define _CPU_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + UINT8 Revision; ///< Offset 0 CP= U GlobalNvs Revision + UINT32 PpmFlags; ///< Offset 1 PP= M Flags Values + UINT8 Reserved0[1]; ///< Offset 5:5 + UINT8 AutoCriticalTripPoint; ///< Offset 6 Au= to Critical Trip Point + UINT8 AutoPassiveTripPoint; ///< Offset 7 Au= to Passive Trip Point + UINT8 AutoActiveTripPoint; ///< Offset 8 Au= to Active Trip Point + UINT32 Cpuid; ///< Offset 9 CP= UID + UINT8 ConfigurablePpc; ///< Offset 13 Bo= ot Mode vlues for _PPC + UINT8 CtdpLevelsSupported; ///< Offset 14 Co= nfigTdp Number Of Levels + UINT8 ConfigTdpBootModeIndex; ///< Offset 15 CT= DP Boot Mode Index + UINT16 CtdpPowerLimit1[3]; ///< Offset 16 CT= DP Level 0 Power Limit1 + ///< Offset 18 CT= DP Level 1 Power Limit1 + ///< Offset 20 CT= DP Level 2 Power Limit1 + UINT16 CtdpPowerLimit2[3]; ///< Offset 22 CT= DP Level 0 Power Limit2 + ///< Offset 24 CT= DP Level 1 Power Limit2 + ///< Offset 26 CT= DP Level 2 Power Limit2 + UINT8 CtdpPowerLimitWindow[3]; ///< Offset 28 CT= DP Level 0 Power Limit1 Time Window + ///< Offset 29 CT= DP Level 1 Power Limit1 Time Window + ///< Offset 30 CT= DP Level 2 Power Limit1 Time Window + UINT8 CtdpCtc[3]; ///< Offset 31 CT= DP Level 0 CTC + ///< Offset 32 CT= DP Level 1 CTC + ///< Offset 33 CT= DP Level 2 CTC + UINT8 CtdpTar[3]; ///< Offset 34 CT= DP Level 0 TAR + ///< Offset 35 CT= DP Level 1 TAR + ///< Offset 36 CT= DP Level 2 TAR + UINT8 CtdpPpc[3]; ///< Offset 37 CT= DP Level 0 PPC + ///< Offset 38 CT= DP Level 1 PPC + ///< Offset 39 CT= DP Level 2 PPC + UINT8 Reserved1[1]; ///< Offset 40:40 + UINT8 C6MwaitValue; ///< Offset 41 Mw= ait Hint value for C6 + UINT8 C7MwaitValue; ///< Offset 42 Mw= ait Hint value for C7/C7s + UINT8 CDMwaitValue; ///< Offset 43 Mw= ait Hint value for C7/C8/C9/C10 + UINT8 Reserved2[2]; ///< Offset 44:45 + UINT16 C6Latency; ///< Offset 46 La= tency Value for C6 + UINT16 C7Latency; ///< Offset 48 La= tency Value for C7/C7S + UINT16 CDLatency; ///< Offset 50 La= tency Value for C8/C9/C10 + UINT16 CDIOLevel; ///< Offset 52 IO= LVL value for C8/C9/C10 + UINT16 CDPowerValue; ///< Offset 54 Po= wer value for C8/C9/C10 + UINT8 MiscPowerManagementFlags; ///< Offset 56 Mi= scPowerManagementFlags + UINT8 EnableDigitalThermalSensor; ///< Offset 57 Di= gital Thermal Sensor Enable + UINT8 BspDigitalThermalSensorTemperature; ///< Offset 58 Di= gital Thermal Sensor 1 Readingn for BSP + UINT8 ApDigitalThermalSensorTemperature; ///< Offset 59 Di= gital Thermal Sensor 2 Reading for AP1 + UINT8 DigitalThermalSensorSmiFunction; ///< Offset 60 DT= S SMI Function Call via DTS IO Trap + UINT8 PackageDTSTemperature; ///< Offset 61 Pa= ckage Temperature + UINT8 IsPackageTempMSRAvailable; ///< Offset 62 Pa= ckage Temperature MSR available + UINT8 Ap2DigitalThermalSensorTemperature; ///< Offset 63 Di= gital Thermal Sensor 3 Reading for AP2 + UINT8 Ap3DigitalThermalSensorTemperature; ///< Offset 64 Di= gital Thermal Sensor 4 Reading for AP3 + UINT64 BiosGuardMemAddress; ///< Offset 65 BI= OS Guard Memory Address for Tool Interface + UINT8 BiosGuardMemSize; ///< Offset 73 BI= OS Guard Memory Size for Tool Interface + UINT16 BiosGuardIoTrapAddress; ///< Offset 74 BI= OS Guard IoTrap Address for Tool Interface + UINT16 BiosGuardIoTrapLength; ///< Offset 76 BI= OS Guard IoTrap Length for Tool Interface + UINT16 DtsIoTrapAddress; ///< Offset 78 DT= S IO trap Address + UINT8 DtsIoTrapLength; ///< Offset 80 DT= S IO trap Length + UINT8 DtsAcpiEnable; ///< Offset 81 DT= S is in ACPI Mode Enabled + UINT8 SgxStatus; ///< Offset 82 SG= X Status + UINT64 EpcBaseAddress; ///< Offset 83 EP= C Base Address + UINT64 EpcLength; ///< Offset 91 EP= C Length + UINT8 HwpVersion; ///< Offset 99 HW= P Version + UINT8 HwpInterruptStatus; ///< Offset 100 HW= P Interrupt Status + UINT8 DtsInterruptStatus; ///< Offset 101 DT= S Interrupt Status + UINT8 HwpSmi; ///< Offset 102 SM= I to setup HWP LVT tables + UINT8 LowestMaxPerf; ///< Offset 103 Ma= x ratio of the slowest core. + UINT8 EnableItbm; ///< Offset 104 En= able/Disable Intel Turbo Boost Max Technology 3.0. + UINT8 EnableItbmDriver; ///< Offset 105 En= able/Disable Intel Turbo Boost Max Technology 3.0 Driver. + UINT8 ItbmInterruptStatus; ///< Offset 106 In= tel Turbo Boost Max Technology 3.0 interrupt status. + UINT8 ItbmSmi; ///< Offset 107 SM= I to resume periodic SMM for Intel Turbo Boost Max Technology 3.0. + UINT8 OcBins; ///< Offset 108 In= dicates bins of Oc support. MSR 194h FLEX_RATIO Bits (19:17) + UINT8 C3MwaitValue; ///< Offset 109 Mw= ait Hint value for C3 (CFL only) + UINT16 C3Latency; ///< Offset 110 La= tency Value for C3 (CFL only) +} CPU_NVS_AREA; + +#pragma pack(pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h new file mode 100644 index 0000000000..a9abd426f9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h @@ -0,0 +1,23 @@ +/** @file + CPU Policy structure definition which will contain several config blocks= during runtime. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_COMMON_H_ +#define _CPU_POLICY_COMMON_H_ + +#include "CpuPowerMgmt.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif // _CPU_POLICY_COMMON_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h new file mode 100644 index 0000000000..af1f70b34f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuPowerMgmt.h @@ -0,0 +1,100 @@ +/** @file + This file contains define definitions specific to processor + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _POWER_MGMT_DEFINITIONS_H_ +#define _POWER_MGMT_DEFINITIONS_H_ + +#define CSTATE_SUPPORTED 0x1 +#define ENHANCED_CSTATE_SUPPORTED 0x2 +#define C6_C7_SHORT_LATENCY_SUPPORTED 0x01 +#define C6_C7_LONG_LATENCY_SUPPORTED 0x02 +#define C7s_SHORT_LATENCY_SUPPORTED 0x03 +#define C7s_LONG_LATENCY_SUPPORTED 0x04 +// +// Voltage offset definitions +// +#define OC_LIB_OFFSET_ADAPTIVE 0 +#define OC_LIB_OFFSET_OVERRIDE 1 +// +// Platform Power Management Flags Bit Definitions: +// These defines are also used in CPU0CST.ASL to check platform configur= ation +// and build C-state table accordingly. +// +#define PPM_EIST BIT0 ///< Enhanced Intel Speed Step Tech= nology. +#define PPM_C1 BIT1 ///< C1 enabled, supported. +#define PPM_C1E BIT2 ///< C1E enabled. +#define PPM_C3 BIT3 ///< C3 enabled, supported. +#define PPM_C6 BIT4 ///< C6 enabled, supported. +#define PPM_C7 BIT5 ///< C7 enabled, supported. +#define PPM_C7S BIT6 ///< C7S enabled, supported +#define PPM_TM BIT7 ///< Adaptive Thermal Monitor. +#define PPM_TURBO BIT8 ///< Long duration turbo mode +#define PPM_CMP BIT9 ///< CMP. +#define PPM_TSTATES BIT10 ///< CPU throttling states +#define PPM_MWAIT_EXT BIT11 ///< MONITIOR/MWAIT Extensions supp= orted. +#define PPM_EEPST BIT12 ///< Energy efficient P-State Featu= re enabled +#define PPM_TSTATE_FINE_GRAINED BIT13 ///< Fine grained CPU Throttling st= ates +#define PPM_CD BIT14 ///< Deep Cstate - C8/C9/C10 +#define PPM_TIMED_MWAIT BIT15 ///< Timed Mwait support +#define C6_LONG_LATENCY_ENABLE BIT16 ///< 1=3DC6 Long and Short,0=3DC6 S= hort only +#define C7_LONG_LATENCY_ENABLE BIT17 ///< 1=3DC7 Long and Short,0=3DC7 S= hort only +#define C7s_LONG_LATENCY_ENABLE BIT18 ///< 1=3DC7s Long and Short,0=3DC7s= Short only +#define PPM_C8 BIT19 ///< 1=3D C8 enabled/supported +#define PPM_C9 BIT20 ///< 1=3D C9 enabled/supported +#define PPM_C10 BIT21 ///< 1=3D C10 enabled/supported +#define PPM_HWP BIT22 ///< 1=3D HWP enabled/supported +#define PPM_HWP_LVT BIT23 ///< 1=3D HWP LVT enabled/supported +#define PPM_OC_UNLOCKED BIT24 ///< 1=3D Overclocking fully unlock= ed + +#define PPM_C_STATES 0x7A ///< PPM_C1 + PPM_C3 + PPM_C6 + PP= M_C7 + PPM_C7S +#define C3_LATENCY 0x4E +#define C6_C7_SHORT_LATENCY 0x76 +#define C6_C7_LONG_LATENCY 0x94 +#define C8_LATENCY 0xFA +#define C9_LATENCY 0x14C +#define C10_LATENCY 0x3F2 + +// +// The following definitions are based on assumed location for the ACPI +// Base Address. Modify as necessary base on platform-specific requiremen= ts. +// +#define PCH_ACPI_PBLK 0x1810 +#define PCH_ACPI_LV2 0x1814 +#define PCH_ACPI_LV3 0x1815 +#define PCH_ACPI_LV4 0x1816 +#define PCH_ACPI_LV6 0x1818 +#define PCH_ACPI_LV5 0x1817 +#define PCH_ACPI_LV7 0x1819 + +// +// C-State Latency (us) and Power (mW) for C1 +// +#define C1_LATENCY 1 +#define C1_POWER 0x3E8 +#define C3_POWER 0x1F4 +#define C6_POWER 0x15E +#define C7_POWER 0xC8 +#define C8_POWER 0xC8 +#define C9_POWER 0xC8 +#define C10_POWER 0xC8 + + +#define PID_DOMAIN_KP 0 +#define PID_DOMAIN_KI 1 +#define PID_DOMAIN_KD 2 +#define MAILBOX_PARAM_1_OFFSET 8 + +/// +/// VR Domain Definitions +/// +#define CPU_VR_DOMAIN_SA 0x0 +#define CPU_VR_DOMAIN_IA 0x1 +#define CPU_VR_DOMAIN_RING 0x2 +#define CPU_VR_DOMAIN_GT 0x3 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h new file mode 100644 index 0000000000..68f2c019e2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/CpuRegs.h @@ -0,0 +1,261 @@ +/** @file + Register names for CPU registers + + Conventions + - Definitions beginning with "MSR_" are MSRs + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within t= he registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_REGS_H_ +#define _CPU_REGS_H_ + +#define MSR_CORE_THREAD_COUNT 0x00= 000035 +#define B_THREAD_COUNT_MASK 0xFF= FF +#define MSR_SPCL_CHIPSET_USAGE_ADDR 0x00= 0001FE +/// +/// Arch-specific MSR defines in SDM +/// @{ + +#define MSR_PLATFORM_INFO 0x00= 0000CE +#define N_PLATFORM_INFO_MIN_RATIO 40 +#define B_PLATFORM_INFO_RATIO_MASK 0xFF +#define N_PLATFORM_INFO_MAX_RATIO 8 +#define B_MSR_PLATFORM_INFO_BIOSGUARD_AVAIL BIT35 +#define N_MSR_PLATFORM_INFO_CONFIG_TDP_NUM_LEVELS_OFFSET 33 +#define V_CONFIG_TDP_NUM_LEVELS_MASK (BIT= 34 | BIT33) +#define B_PLATFORM_INFO_TDC_TDP_LIMIT BIT29 +#define N_PLATFORM_INFO_RATIO_LIMIT 28 +#define B_PLATFORM_INFO_RATIO_LIMIT BIT28 +#define B_PLATFORM_INFO_SAMPLE_PART BIT27 +#define B_PLATFORM_INFO_SMM_SAVE_CONTROL BIT16 +#define N_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET 30 +#define B_PLATFORM_INFO_PROG_TCC_ACTIVATION_OFFSET BIT30 +#define B_PLATFORM_INFO_TIMED_MWAIT_SUPPORTED BIT37 +#define B_PLATFORM_INFO_EDRAM_EN BIT57 + +// +// MSR_BROADWELL_PKG_CST_CONFIG_CONTROL: related defines +// +#define B_TIMED_MWAIT_ENABLE BIT3= 1 ///< @todo Remove when bitfield definition is available. +#define V_CSTATE_LIMIT_C1 0x01 +#define V_CSTATE_LIMIT_C3 0x02 +#define V_CSTATE_LIMIT_C6 0x03 +#define V_CSTATE_LIMIT_C7 0x04 +#define V_CSTATE_LIMIT_C7S 0x05 +#define V_CSTATE_LIMIT_C8 0x06 +#define V_CSTATE_LIMIT_C9 0x07 +#define V_CSTATE_LIMIT_C10 0x08 + +#define MSR_PMG_IO_CAPTURE_BASE 0x00= 0000E4 +#define B_MSR_PMG_CST_RANGE (BIT= 18 | BIT17 | BIT16) +#define V_IO_CAPT_LVL2 (0x0= << 16) ///< C3 +#define V_IO_CAPT_LVL3 (0x1= << 16) ///< C6 +#define V_IO_CAPT_LVL4 (0x2= << 16) ///< C7 +#define V_IO_CAPT_LVL5 (0x3= << 16) ///< C8 +#define V_IO_CAPT_LVL6 (0x4= << 16) ///< C9 +#define V_IO_CAPT_LVL7 (0x5= << 16) ///< C10 +#define V_IO_CAPT_LVL2_BASE_ADDR_MASK 0xFF= FF + +#define MSR_TEMPERATURE_TARGET 0x00= 0001A2 +#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LOCK BIT31 +#define N_MSR_TEMPERATURE_TARGET_TCC_OFFSET_LIMIT 24 +#define V_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_OFFSET_MASK 0x3F +#define N_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_OFFSET (16) +#define B_MSR_TEMPERATURE_TARGET_TCC_ACTIVATION_TEMPERATURE_MASK (0xF= F << 16) +#define N_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET 8 +#define B_MSR_TEMPERATURE_TARGET_FAN_TEMP_TARGET_OFFSET (0xF= F << 8) +#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_TIME_WINDOW (0x7= F) +#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_MASK 0xFF +#define B_MSR_TEMPERATURE_TARGET_TCC_OFFSET_CLAMP_BIT BIT7 + + +#define MSR_TURBO_RATIO_LIMIT 0x00= 0001AD +#define N_MSR_TURBO_RATIO_LIMIT_1C 0 +#define B_MSR_TURBO_RATIO_LIMIT_1C (0xF= F << 0) +#define N_MSR_TURBO_RATIO_LIMIT_2C 8 +#define B_MSR_TURBO_RATIO_LIMIT_2C (0xF= F << 8) +#define N_MSR_TURBO_RATIO_LIMIT_3C 16 +#define B_MSR_TURBO_RATIO_LIMIT_3C (0xF= F << 16) +#define N_MSR_TURBO_RATIO_LIMIT_4C 24 +#define B_MSR_TURBO_RATIO_LIMIT_4C (0xF= F << 24) +#define N_MSR_TURBO_RATIO_LIMIT_5C 32 +#define B_MSR_TURBO_RATIO_LIMIT_5C (0xF= F << 32) +#define N_MSR_TURBO_RATIO_LIMIT_6C 40 +#define B_MSR_TURBO_RATIO_LIMIT_6C (0xF= F << 40) +#define N_MSR_TURBO_RATIO_LIMIT_7C 48 +#define B_MSR_TURBO_RATIO_LIMIT_7C (0xF= F << 48) +#define N_MSR_TURBO_RATIO_LIMIT_8C 56 +#define B_MSR_TURBO_RATIO_LIMIT_8C (0xF= F << 56) + +#define MSR_IA32_FEATURE_CONFIG 0x00= 00013C +#define B_IA32_FEATURE_CONFIG_AES_DIS BIT1 +#define B_IA32_FEATURE_CONFIG_LOCK BIT0 + +// +// MSRs for SMM State Save Register +// +#define MSR_SMM_MCA_CAP 0x00= 00017D +#define B_TARGETED_SMI BIT56 +#define N_TARGETED_SMI 56 +#define B_SMM_CPU_SVRSTR BIT57 +#define N_SMM_CPU_SVRSTR 57 +#define B_SMM_CODE_ACCESS_CHK BIT58 +#define N_SMM_CODE_ACCESS_CHK 58 +#define B_LONG_FLOW_INDICATION BIT59 +#define N_LONG_FLOW_INDICATION 59 +#define MSR_SMM_FEATURE_CONTROL 0x00= 0004E0 +#define B_SMM_FEATURE_CONTROL_LOCK BIT0 +#define B_SMM_CPU_SAVE_EN BIT1 +#define B_SMM_CODE_CHK_EN BIT2 + +/// @} + + +/// +/// Bit defines for MSRs defined in UefiCpuPkg/Include/Register/Architectu= ralMsr.h. +/// @{ + +// +// Number of fixed MTRRs +// +#define V_FIXED_MTRR_NUMBER 11 + +// +// Number of variable MTRRs +// +#define V_MAXIMUM_VARIABLE_MTRR_NUMBER 10 + +// +// Bit defines for MSR_IA32_MTRR_DEF_TYPE +// +#define B_CACHE_MTRR_VALID BIT11 +#define B_CACHE_FIXED_MTRR_VALID BIT10 + +// +// Bit defines for MSR_IA32_DEBUG_INTERFACE +// +#define B_DEBUG_INTERFACE_ENABLE BIT0 +#define B_DEBUG_INTERFACE_LOCK BIT30 +#define B_DEBUG_INTERFACE_DEBUG_STATUS BIT31 + +/// @} + +/// +/// Other defines +/// +#ifndef TRIGGER_MODE_EDGE +#define TRIGGER_MODE_EDGE 0x00 +#endif +#ifndef TRIGGER_MODE_LEVEL +#define TRIGGER_MODE_LEVEL 0x01 +#endif + +#ifndef CPU_FEATURE_DISABLE +#define CPU_FEATURE_DISABLE 0 +#endif +#ifndef CPU_FEATURE_ENABLE +#define CPU_FEATURE_ENABLE 1 +#endif + +#define CACHE_UNCACHEABLE 0 +#define CACHE_WRITECOMBINING 1 +#define CACHE_WRITETHROUGH 4 +#define CACHE_WRITEPROTECTED 5 +#define CACHE_WRITEBACK 6 + + +// +// Processor Definitions +// +#define CPUID_FULL_STEPPING 0x0000000F +#define CPUID_FULL_FAMILY_MODEL 0x0FFF0FF0 +#define CPUID_FULL_FAMILY_MODEL_STEPPING 0x0FFF0FFF +#define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX 0x000806E0 +#define CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO 0x000906E0 +#define CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO 0x00060670 + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_MILLI_SECOND +#define STALL_ONE_MILLI_SECOND 1000 +#endif + +#define BITS(x) (1 << (x)) + +/** +Notes : + 1. Bit position always starts at 0. + 2. Following macros are applicable only for Word aligned integers. +**/ +#define BIT(Pos, Value) (1 << (Pos) & (Value)) +#define BITRANGE(From, Width, Value) (((Value) >> (From)) & ((1 << (Width= )) - 1)) + +/// +/// Enums for CPU Family IDs +/// +typedef enum { + EnumCpuCflUltUlx =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX, + EnumCpuCflDtHalo =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO, + EnumCpuCnlDtHalo =3D CPUID_FULL_FAMILY_MODEL_CANNONLAKE_DT_HALO, + EnumCpuMax =3D CPUID_FULL_FAMILY_MODEL +} CPU_FAMILY; + +/// +/// Enums for CPU Stepping IDs +/// +typedef enum { + /// + /// Coffeelake ULX/ULT Steppings + /// + EnumKblH0 =3D 9, + EnumCflD0 =3D 0xA, + + /// Whiskey Lake ULT Steppings + EnumCflW0 =3D 0xB, + EnumCflV0 =3D 0xC, + + EnumCflMaxUltUlxStep =3D EnumCflV0, + + /// + /// Coffeelake DT/Halo Steppings + /// + EnumCflU0 =3D 0xA, + EnumCflB0 =3D 0xB, + EnumCflP0 =3D 0xC, + EnumCflR0 =3D 0xD, + EnumCflMaxDtHaloStep =3D EnumCflR0, + + /// + /// Max Stepping + /// + EnumCpuSteppingMax =3D CPUID_FULL_STEPPING +} CPU_STEPPING; + +/// +/// Enums for CPU SKU IDs +/// +typedef enum { + EnumCpuUlt =3D 0, + EnumCpuTrad, + EnumCpuUlx, + EnumCpuHalo, + EnumCpuUnknown +} CPU_SKU; + +/// +/// Enums for CPU Generation +/// +typedef enum { + EnumCflCpu =3D 0, + EnumCpuUnknownGeneration =3D 255 +} CPU_GENERATION; +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMail= boxLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailbo= xLib.h new file mode 100644 index 0000000000..79dff36783 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuMailboxLib.h @@ -0,0 +1,90 @@ +/** @file + Header file for Cpu Mailbox Lib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_MAILBOX_LIB_H_ +#define _CPU_MAILBOX_LIB_H_ + +// +// Mailbox Related Definitions +// + +/** + Generic Mailbox function for mailbox write commands. This function will + poll the mailbox interface for control, issue the write request, poll + for completion, and verify the write was succussful. + + @param[in] MailboxType The type of mailbox interface to read. The O= verclocking mailbox is defined as MAILBOX_TYPE_OC =3D 2. + @param[in] MailboxCommand Overclocking mailbox command data + @param[in] MailboxData Overclocking mailbox interface data + @param[out] *MailboxStatus Pointer to the mailbox status returned from = pcode. Possible mailbox status values are: + - SUCCESS (0) Command succeede= d. + - OC_LOCKED (1) Overclocking is = locked. Service is read-only. + - INVALID_DOMAIN (2) Invalid Domain I= D provided in command data. + - MAX_RATIO_EXCEEDED (3) Ratio exceeds ma= ximum overclocking limits. + - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds = input VR's max voltage. + - OC_NOT_SUPPORTED (5) Domain does not = support overclocking. + + @retval EFI_STATUS + - EFI_SUCCESS Command succeeded. + - EFI_INVALID_PARAMETER Invalid read data detected from pcode. + - EFI_UNSUPPORTED Unsupported MailboxType parameter. +**/ +EFI_STATUS +EFIAPI +MailboxWrite ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + IN UINT32 MailboxData, + OUT UINT32 *MailboxStatus + ); + +/** + Generic Mailbox function for mailbox read commands. This function will w= rite + the read request from MailboxType, and populate the read results in the = MailboxDataPtr. + + @param[in] MailboxType The type of mailbox interface to read. The O= verclocking mailbox is defined as MAILBOX_TYPE_OC =3D 2. + @param[in] MailboxCommand Overclocking mailbox command data + @param[out] *MailboxDataPtr Pointer to the overclocking mailbox interfac= e data + @param[out] *MailboxStatus Pointer to the mailbox status returned from = pcode. Possible mailbox status are + - SUCCESS (0) Command succeede= d. + - OC_LOCKED (1) Overclocking is = locked. Service is read-only. + - INVALID_DOMAIN (2) Invalid Domain I= D provided in command data. + - MAX_RATIO_EXCEEDED (3) Ratio exceeds ma= ximum overclocking limits. + - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds = input VR's max voltage. + - OC_NOT_SUPPORTED (5) Domain does not = support overclocking. + + @retval EFI_STATUS + - EFI_SUCCESS Command succeeded. + - EFI_INVALID_PARAMETER Invalid read data detected from pcode. + - EFI_UNSUPPORTED Unsupported MailboxType parameter. + +**/ +EFI_STATUS +EFIAPI +MailboxRead ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + OUT UINT32 *MailboxDataPtr, + OUT UINT32 *MailboxStatus + ); + +/** + Poll the run/busy bit of the mailbox until available or timeout expires. + + @param[in] MailboxType + + @retval EFI_STATUS + - EFI_SUCCESS Command succeeded. + - EFI_TIMEOUT Command timeout. +**/ +EFI_STATUS +EFIAPI +PollMailboxReady ( + IN UINT32 MailboxType + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlat= formLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatf= ormLib.h new file mode 100644 index 0000000000..a2dc83efb5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPlatformLib= .h @@ -0,0 +1,118 @@ +/** @file + Header file for CpuPlatform Lib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PLATFORM_LIB_H_ +#define _CPU_PLATFORM_LIB_H_ + +#include +#include +#include + +/** + Check CPU Type of the platform + + @retval CPU_FAMILY CPU type +**/ +CPU_FAMILY +EFIAPI +GetCpuFamily ( + VOID + ); + +/** + Return Cpu stepping type + + @retval CPU_STEPPING Cpu stepping type +**/ +CPU_STEPPING +EFIAPI +GetCpuStepping ( + VOID + ); + +/** + Return CPU Sku + + @retval UINT8 CPU Sku +**/ +UINT8 +EFIAPI +GetCpuSku ( + VOID + ); + +/** + Returns the processor microcode revision of the processor installed in t= he system. + + @retval Processor Microcode Revision +**/ +UINT32 +GetCpuUcodeRevision ( + VOID + ); + +/** + Check if this microcode is correct one for processor + + @param[in] Cpuid - processor CPUID + @param[in] MicrocodeEntryPoint - entry point of microcode + @param[in] Revision - revision of microcode + + @retval CorrectMicrocode if this microcode is correct +**/ +BOOLEAN +CheckMicrocode ( + IN UINT32 Cpuid, + IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint, + IN UINT32 *Revision + ); + +/** + Check on the processor if SGX is supported. + + @retval True if SGX supported or FALSE if not +**/ +BOOLEAN +IsSgxSupported ( + VOID + ); + +/** + Get processor generation + + @retval CPU_GENERATION Returns the executing thread's processor generat= ion. +**/ +CPU_GENERATION +GetCpuGeneration ( + VOID + ); + +/** + Check if Disable CPU Debug (DCD) bit is set from FIT CPU Debugging [Disa= bled]. + If it is set, CPU probe mode is disabled. + + @retval TRUE DCD is set + @retval FALSE DCD is clear +**/ +BOOLEAN +IsCpuDebugDisabled ( + VOID + ); + +/** + Is Whiskey Lake CPU. + + @retval TRUE The CPUID corresponds with a Whiskey Lake CPU + @retval FALSE The CPUID does not correspond with a Whiskey Lake CPU +**/ +BOOLEAN +IsWhlCpu ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPoli= cyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyL= ib.h new file mode 100644 index 0000000000..88f4353e91 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Library/CpuPolicyLib.h @@ -0,0 +1,84 @@ +/** @file + Prototype of the CpuPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_LIB_H_ +#define _CPU_POLICY_LIB_H_ + +#include + +/** + Print whole CPU related config blocks of SI_PREMEM_POLICY_PPI and serial= out. + + @param[in] SiPreMemPolicyPpi The Si PreMem Policy PPI instan= ce +**/ +VOID +CpuPreMemPrintPolicy ( +IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi +); + +/** + Get CPU PREMEM config block table total size. + + @retval Size of CPU PREMEM config block table +**/ +UINT16 +EFIAPI +CpuGetPreMemConfigBlockTotalSize ( + VOID + ); + +/** + CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add CPU PREMEM conf= ig blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CpuAddPreMemConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +/** + Print whole CPU config blocks of SiPolicyPpi and serial out. + + @param[in] SiPolicyPpi The SI Policy PPI instance +**/ +VOID +CpuPrintPolicy ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Get CPU config block table total size. + + @retval Size of CPU config block table +**/ +UINT16 +EFIAPI +CpuGetConfigBlockTotalSize ( + VOID + ); + +/** + CpuAddConfigBlocks add all Cpu config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add CPU config bloc= ks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CpuAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _PEI_CPU_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInf= o.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h new file mode 100644 index 0000000000..67f88ce987 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuInfo.h @@ -0,0 +1,123 @@ +/** @file + Protocol used to report CPU information + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_INFO_H_ +#define _CPU_INFO_H_ + +#include + +typedef struct _CPU_INFO_PROTOCOL CPU_INFO_PROTOCOL; + + +extern EFI_GUID gCpuInfoProtocolGuid; + +// +// DXE_CPU_INFO_PROTOCOL revisions +// +#define CPU_INFO_PROTOCOL_REVISION 1 + +// +// Processor feature definitions. +// +#define TXT_SUPPORT BIT0 +#define VMX_SUPPORT BIT1 +#define XD_SUPPORT BIT2 +#define DCA_SUPPORT BIT3 +#define X2APIC_SUPPORT BIT4 +#define AES_SUPPORT BIT5 +#define HT_SUPPORT BIT6 +#define DEBUG_SUPPORT BIT7 +#define DEBUG_LOCK_SUPPORT BIT8 +#define PROC_TRACE_SUPPORT BIT9 +#define HDC_SUPPORT BIT10 + + +#pragma pack(1) +/// +/// Cache descriptor information +/// +typedef struct { + UINT8 Desc; ///< Cache Descriptor + UINT8 Level; ///< Cache Level + UINT8 Type; ///< Cache Type. 0: Dat= a, 1: Instruction, 3: Unified + UINT32 Size; ///< Cache Size. + UINT16 Associativity; ///< Cache Ways of Asso= ciativity. +} CACHE_DESCRIPTOR_INFO; + +/// +/// Processor information +/// +typedef struct { + UINT32 CpuSignature; ///< Processor signatu= re and version information. + UINT64 Features; ///< Features availabi= lity in the CPU based on reading ECX after doing Asmcpuid(EAX=3D1). + CHAR8 *BrandString; ///< Processor Brand S= tring. + UINT8 NumSupportedCores; ///< Total Number of S= upported Cores in CPU Package. If Dual core, 2 cores. + UINT8 NumSupportedThreadsPerCore; ///< Number of Support= ed Threads per Core. + UINT8 NumCores; ///< Number of Enabled= or Active Cores. + UINT8 NumHts; ///< Number of Enabled= Threads per Core. This will be 1 or 2. + UINT32 IntendedFreq; ///< Maximum non turbo= ratio in MHz + UINT32 ActualFreq; ///< Actual frequency = in MHz + UINT32 Voltage; ///< Current operating= voltage. + CACHE_DESCRIPTOR_INFO *CacheInfo; ///< Cache descriptor = information. + UINT8 MaxCacheSupported; ///< Maximum cache sup= ported. + UINT8 SmmbaseSwSmiNumber; ///< Software SMI Numb= er from Smbase. @Note: This is unused. + UINT16 NumberOfPStates; ///< Number of P-State= s. +} CPU_INFO; + +/// +/// This HOB is data structure representing two different address location= in SMRAM to hold SMRAM CPU DATA. +/// +typedef struct { + EFI_PHYSICAL_ADDRESS LockBoxData; ///< First location (address) of SMRA= M CPU DATA. + EFI_PHYSICAL_ADDRESS SmramCpuData; ///< Second location (Address) of SMR= AM CPU DATA. + UINT64 LockBoxSize; ///< Size of SMRAM CPU DATA. +} SMRAM_CPU_INFO; + +/// +/// SGX Information +/// +typedef struct { + UINT64 SgxSinitNvsData; ///< Sinit SE SVN Version saved and passed bac= k in next boot +} SGX_INFO; + +#pragma pack() + +/// +/// This protocol provides information about the common features available= in this CPU. +/// +struct _CPU_INFO_PROTOCOL { + /** + Revision for the protocol structure. + Any backwards compatible changes to this protocol will result in an upda= te in the revision number. + Major changes will require publication of a new protocol + + Revision 1: + - Initial version + **/ + UINT8 Revision; + /** + CPU Supported Feature. + - BIT0: If set then processor supports TXT. + - BIT1: If set then processor supports virtual mode extensions. + - BIT2: If set then processor supports execute disable bit. + - BIT3: If set then processor supports DCA. + - BIT4: If set then processor supports X2APIC. + - BIT5: If set then processor supports Advanced Encryption Standard. + - BIT6: If set then processor supports hyperthreading. + - BIT7: If set then processor supports debug interface. + - BIT8: If set then processor supports debug interface lock. + - BIT9: If set then processor supports processor trace. + - BIT10: If Set then processor supports supports HDC. + **/ + UINT64 CpuCommonFeatures; + CPU_INFO *CpuInfo; ///< Processor Basic Information + SMRAM_CPU_INFO *SmramCpuInfo; ///< SMRAM CPU Information + SGX_INFO *SgxInfo; ///< SGX Information +}; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPol= icyProtocol.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/Cpu= PolicyProtocol.h new file mode 100644 index 0000000000..ed056025b7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Include/Protocol/CpuPolicyProt= ocol.h @@ -0,0 +1,50 @@ +/** @file + Protocol used for specifying platform related CPU information and policy= setting. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_PROTOCOL_H_ +#define _CPU_POLICY_PROTOCOL_H_ + +// +// DXE_CPU_POLICY_PROTOCOL revisions +// +#define DXE_CPU_POLICY_PROTOCOL_REVISION 1 + +extern EFI_GUID gDxeCpuPolicyProtocolGuid; + +#pragma pack (push,1) + +/** + The protocol allows the platform code to publish a set of configuration = information that the + CPU drivers will use to configure the processor in the DXE phase. + This Policy Protocol needs to be initialized for CPU configuration. + @note The Protocol has to be published before processor DXE drivers are = dispatched. +**/ +typedef struct { + /** + This member specifies the revision of the Cpu Policy protocol. This fiel= d is used to indicate backward + compatible changes to the protocol. Any such changes to this protocol wi= ll result in an update in the revision number. + + Revision 1: + - Initial version + **/ + /** + Policies to obtain CPU temperature. + - 0: ACPI thermal management uses EC reported temperature values. + - 1: ACPI thermal management uses DTS SMM mechanism to obtain CPU tempe= rature values. + - 2: ACPI Thermal Management uses EC reported temperature values and DT= S SMM is used to handle Out of Spec condition. + **/ + UINT32 EnableDts : 2; + UINT32 RsvdBit : 30; ///< Reserved = bits, align to multiple 32; + + UINT8 Revision; ///< Current r= evision of policy. + UINT8 ReservedByte[3]; ///< Reserved = bytes, align to multiple 8. +} DXE_CPU_POLICY_PROTOCOL; + +#pragma pack (pop) + +#endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45879): https://edk2.groups.io/g/devel/message/45879 Mute This Topic: https://groups.io/mt/32918170/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45881+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45881+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001012; cv=none; d=zoho.com; s=zohoarc; b=CgurCjH2tPMTsJVfqmJWkFK/Ol2IDn/+cQeNb2vD9SR9gUvdKMBSYuPa7m6mnyy9iHUP/GCeLAn8N90oC0mXuxN+ygv0sfeJIiwGfYem7YXhRHsPubfM7bzF+y7GnxwTXfdP+gjq/1cjswbSscv/jW/ApLEX4BUv4xC6SkfXTK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001012; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=TzkuDv3s3ffuwejDqFvM1CDTIj2idPyOgtXBQaQG5G4=; b=R1MHkCnky0k6bfFgAUJAKh9xekYabt4Kiaw8w6j0nVyVEyCUwR1OKwYlaByNeKgMRf5QXM7w+2qTyAf41EzTFOXenNBmblLODnKYQAycCe7F0MJPT+2lGavsCIS8AbbwwQt1Z3FP+LuxZ060pV8jg7c5DcORHz8BiXTgwWpBSdU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45881+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001012467238.9747103013051; Fri, 16 Aug 2019 17:16:52 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:51 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319230" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:49 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 03/37] CoffeelakeSiliconPkg/Me: Add Include headers Date: Fri, 16 Aug 2019 17:15:29 -0700 Message-Id: <20190817001603.30632-4-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001012; bh=rDzsNtDGsWilijOLkDZLIxCnA6lR3FRruLhwj0Jun0o=; h=Cc:Date:From:Reply-To:Subject:To; b=TxS07VxpK2+0f7R5Sqx1pFEN2wOxtInGMMXrWDnTzAA2Lom97oh1ysLdc+j6aHqcrvH aaS+NZk3WvqAZ7674m/h8IUR3MlqOYBJ4QxjPvlKBy/8xAXF+ZxRvWsrFgeP8RIYLxqVN +2GlEzmJsxNeDuk20nmoam0IpsCYbrJHQH8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds header files common to ME modules. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone Reviewed-by: Sai Chaganty --- Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig.h | = 124 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyLib.h | = 59 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyLib.h | = 87 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h | = 172 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h | = 17 ++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h | = 19 +++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h | = 41 +++++ 7 files changed, 519 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePe= iConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePei= Config.h new file mode 100644 index 0000000000..102fb43bd1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/ConfigBlock/MePeiConfig= .h @@ -0,0 +1,124 @@ +/** @file + ME config block for PEI phase + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ME_PEI_CONFIG_H_ +#define _ME_PEI_CONFIG_H_ + +#include + +#define ME_PEI_PREMEM_CONFIG_REVISION 2 +extern EFI_GUID gMePeiPreMemConfigGuid; + +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif + +#pragma pack (push,1) + +/** + ME Pei Pre-Memory Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Change DidInitStat bit width. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 HeciTimeouts : 1; ///< 0: Disable; 1: Ena= ble - HECI Send/Receive Timeouts. + /** + (Test) + 0: Disabled + 1: ME DID init stat 0 - Success + 2: ME DID init stat 1 - No Memory in Channels + 3: ME DID init stat 2 - Memory Init Error + **/ + UINT32 DidInitStat : 2; + /** + (Test) + 0: Set to 0 to enable polling for CPU replacement + 1: Set to 1 will disable polling for CPU replacement + **/ + UINT32 DisableCpuReplacedPolling : 1; + UINT32 SendDidMsg : 1; ///< (Test) 0: Disa= ble; 1: Enable - Enable/Disable to send DID message. + /** + (Test) + 0: Set to 0 to enable retry mechanism for HECI APIs + 1: Set to 1 will disable retry mechanism for HECI APIs + **/ + UINT32 DisableHeciRetry : 1; + /** + (Test) + 0: ME BIOS will check each messages before sending + 1: ME BIOS always sends messages without checking + **/ + UINT32 DisableMessageCheck : 1; + /** + (Test) + The SkipMbpHob policy determines whether ME BIOS Payload data will be = requested during boot + in a MBP message. If set to 1, BIOS will send the MBP message with Ski= pMbp flag + set causing CSME to respond with MKHI header only and no MBP data + 0: ME BIOS will keep MBP and create HOB for MBP data + 1: ME BIOS will skip MBP data + **/ + UINT32 SkipMbpHob : 1; + UINT32 HeciCommunication2 : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable HECI2. + UINT32 KtDeviceEnable : 1; ///< (Test) 0: Disa= ble; 1: Enable - Enable/Disable Kt Device. + UINT32 RsvdBits : 22; ///< Reserved for future u= se & Config block alignment + UINT32 Heci1BarAddress; ///< HECI1 BAR address. + UINT32 Heci2BarAddress; ///< HECI2 BAR address. + UINT32 Heci3BarAddress; ///< HECI3 BAR address. +} ME_PEI_PREMEM_CONFIG; +#pragma pack (pop) + + +#define ME_PEI_CONFIG_REVISION 2 +extern EFI_GUID gMePeiConfigGuid; + +#pragma pack (push,1) + +/** + ME Pei Post-Memory Configuration Structure. + + Revision 1: + - Initial version. + Revision 2: + - Add MctpBroadcastCycle test setting. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send = in PEI; 2: Send in DXE - Send EOP at specific phase. + /** + HECI3 state from Mbp for reference in S3 path only + 0: Disabled; 1: Enabled + **/ + UINT32 Heci3Enabled : 1; + UINT32 DisableD0I3SettingForHeci : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable D0i3 for HECI. + /** + Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send Me= UnconfigOnRtcClearDisable Msg with parameter 0. + It will cause ME to unconfig if RTC is cleared. + - 0: Disable + - 1: Enable + - 2: Cmos is clear, status unkonwn + - 3: Reserved + **/ + UINT32 MeUnconfigOnRtcClear : 2; + UINT32 MctpBroadcastCycle : 1; ///< (Test) 0: = Disable; 1: Enable - Program registers for MCTP Cycle. + UINT32 RsvdBits : 25; ///< Reserved for future = use & Config block alignment +} ME_PEI_CONFIG; + +#pragma pack (pop) + +#endif // _ME_PEI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePol= icyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolic= yLib.h new file mode 100644 index 0000000000..46f7f86021 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/DxeMePolicyLib.h @@ -0,0 +1,59 @@ +/** @file + Prototype of the DxeMePolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_ME_POLICY_LIB_H_ +#define _DXE_ME_POLICY_LIB_H_ + +#include + +/** + This function prints the ME DXE phase policy. + + @param[in] DxeMePolicy - ME DXE Policy protocol +**/ +VOID +MePrintPolicyProtocol ( + IN ME_POLICY_PROTOCOL *DxeMePolicy + ); + +/** + MeCreatePolicyDefaults creates the default setting of ME Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[in, out] DxeMePolicy The pointer to get ME Policy proto= col instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +MeCreatePolicyDefaults ( + IN OUT ME_POLICY_PROTOCOL **DxeMePolicy + ); + +/** + MeInstallPolicyProtocol installs ME Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] DxeMePolicy The pointer to ME Policy Protocol = instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +MeInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN ME_POLICY_PROTOCOL *DxeMePolicy + ); + +#endif // _DXE_ME_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePol= icyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolic= yLib.h new file mode 100644 index 0000000000..5db4714346 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Library/PeiMePolicyLib.h @@ -0,0 +1,87 @@ +/** @file + Prototype of the MePolicyLibPei library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_ME_POLICY_LIB_H_ +#define _PEI_ME_POLICY_LIB_H_ + +#include +#include + +/** + This function prints the PEI phase PreMem policy. + + @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI insta= nce +**/ +VOID +EFIAPI +MePrintPolicyPpiPreMem ( + IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi + ); + +/** + This function prints the PEI phase policy. + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +MePrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Get Me config block table total size. + + @retval Size of Me config block table +**/ +UINT16 +EFIAPI +MeGetConfigBlockTotalSize ( + VOID + ); + +/** + Get ME config block table total size. + + @retval Size of ME config block table +**/ +UINT16 +EFIAPI +MeGetConfigBlockTotalSizePreMem ( + VOID + ); + +/** + MeAddConfigBlocksPreMem add all ME config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add ME config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +MeAddConfigBlocksPreMem ( + IN VOID *ConfigBlockTableAddress + ); + +/** + MeAddConfigBlocks add all ME config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add ME config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +MeAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _PEI_ME_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h b/Si= licon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h new file mode 100644 index 0000000000..f29f9bc8bd --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MeChipset.h @@ -0,0 +1,172 @@ +/** @file + Chipset definition for ME Devices. + + Conventions: + + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - Registers / bits that are different between PCH generations are denote= d by + "_ME_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "PCH_H_" in reg= ister/bit names. + Registers / bits that are specific to PCH-LP denoted by "PCH_LP_" in r= egister/bit names. + e.g., "_ME_PCH_H_", "_ME_PCH_LP_" + Registers / bits names without _PCH_H_ or _PCH_LP_ apply for both H an= d LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be= just named + as "_ME_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ME_CHIPSET_H_ +#define _ME_CHIPSET_H_ + +#define ME_SEGMENT 0 +#define ME_BUS 0 +#define ME_DEVICE_NUMBER 22 +#define HECI_MIN_FUNC 0 +#define HECI_MAX_FUNC 5 + +#define HECI_FUNCTION_NUMBER 0x00 +#define HECI2_FUNCTION_NUMBER 0x01 +#define IDER_FUNCTION_NUMBER 0x02 +#define SOL_FUNCTION_NUMBER 0x03 +#define HECI3_FUNCTION_NUMBER 0x04 +#define HECI4_FUNCTION_NUMBER 0x05 + +#define IDER_BUS_NUMBER ME_BUS +#define IDER_DEVICE_NUMBER ME_DEVICE_NUMBER +#define SOL_BUS_NUMBER ME_BUS +#define SOL_DEVICE_NUMBER ME_DEVICE_NUMBER + + /// +/// Convert to HECI# defined in BWG from Fun# +/// +#define HECI_NAME_MAP(a) ((a < 2) ? (a + 1) : (a - 1)) + +/// +/// ME-related Chipset Definition +/// +#define HeciEnable() MeDeviceControl (HECI1, Enabled); +#define Heci2Enable() MeDeviceControl (HECI2, Enabled); +#define Heci3Enable() MeDeviceControl (HECI3, Enabled); +#define Heci4Enable() MeDeviceControl (HECI4, Enabled); +#define IderEnable() MeDeviceControl (IDER, Enabled); +#define SolEnable() MeDeviceControl (SOL, Enabled); + +#define HeciDisable() MeDeviceControl (HECI1, Disabled); +#define Heci2Disable() MeDeviceControl (HECI2, Disabled); +#define Heci3Disable() MeDeviceControl (HECI3, Disabled); +#define IderDisable() MeDeviceControl (IDER, Disabled); +#define SolDisable() MeDeviceControl (SOL, Disabled); + +#define DisableAllMeDevices() \ + HeciDisable (); \ + Heci2Disable (); \ + Heci3Disable (); \ + IderDisable (); \ + SolDisable (); + +/// +/// HECI Device Id Definitions +/// + #define IS_PCH_H_HECI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_HECI_DEVICE_ID) \ + ) + + #define IS_PCH_LP_HECI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_HECI_DEVICE_ID) \ + ) + + #define IS_HECI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_HECI_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_HECI_DEVICE_ID(DeviceId) \ + ) + +/// +/// HECI2 Device Id Definitions +/// +#define IS_PCH_H_HECI2_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_HECI2_DEVICE_ID) \ + ) + +#define IS_PCH_LP_HECI2_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_HECI2_DEVICE_ID) \ + ) + +#define IS_HECI2_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_HECI2_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_HECI2_DEVICE_ID(DeviceId) \ + ) + +/// +/// HECI3 Device Id Definitions +/// +#define IS_PCH_H_HECI3_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_HECI3_DEVICE_ID) \ + ) + +#define IS_PCH_LP_HECI3_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_HECI3_DEVICE_ID) \ + ) + +#define IS_HECI3_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_HECI3_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_HECI3_DEVICE_ID(DeviceId) \ + ) + +/// +/// HECI4 Device Id Definitions +/// +#define IS_PCH_H_HECI4_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_HECI4_DEVICE_ID) \ + ) + +#define IS_PCH_LP_HECI4_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_HECI4_DEVICE_ID) \ + ) + +#define IS_HECI4_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_HECI4_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_HECI4_DEVICE_ID(DeviceId) \ + ) + +/// +/// SoL Device Id Definitions +/// +#define IS_PCH_H_SOL_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_H_SOL_DEVICE_ID) \ + ) + +#define IS_PCH_LP_SOL_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_ME_PCH_LP_SOL_DEVICE_ID) \ + ) + +#define IS_PCH_SOL_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SOL_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SOL_DEVICE_ID(DeviceId) \ + ) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h new file mode 100644 index 0000000000..a24973ce32 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MePolicyHob.h @@ -0,0 +1,17 @@ +/** @file + This file contains definitions of ME Policy HOB. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ME_POLICY_HOB_H_ +#define _ME_POLICY_HOB_H_ + +#include + +extern EFI_GUID gMePolicyHobGuid; +extern EFI_GUID gMePreMemPolicyHobGuid; + +#endif // _ME_POLICY_HOB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h new file mode 100644 index 0000000000..2d8ef1cf7a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/MkhiMsgs.h @@ -0,0 +1,19 @@ +/** @file + MKHI Messages + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MKHI_MSGS_H +#define _MKHI_MSGS_H + +/// +/// End of Post +/// +#define EOP_DISABLED 0 +#define EOP_SEND_IN_PEI 1 +#define EOP_SEND_IN_DXE 2 + +#endif // _MKHI_MSGS_H diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolic= y.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h new file mode 100644 index 0000000000..518041cb58 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Include/Protocol/MePolicy.h @@ -0,0 +1,41 @@ +/** @file + Interface definition details between ME and platform drivers during DXE = phase. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ME_POLICY_H_ +#define _ME_POLICY_H_ + +#include + +/** + ME Policy Protocol. + All ME Policy Protocol change history listed here. + +**/ +#define ME_POLICY_PROTOCOL_REVISION 1 + +extern EFI_GUID gDxeMePolicyGuid; + +#pragma pack (push,1) + +/** + ME policy provided by platform for DXE phase + This protocol provides an interface to get Intel ME Configuration inform= ation + + Revision 1: + - Initial version. +**/ +typedef struct _ME_POLICY_PROTOCOL { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +} ME_POLICY_PROTOCOL; + +#pragma pack (pop) + +#endif // _ME_POLICY_H_ --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45881): https://edk2.groups.io/g/devel/message/45881 Mute This Topic: https://groups.io/mt/32918172/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45886+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45886+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001014; cv=none; d=zoho.com; s=zohoarc; b=a8rBc+qLd68ZExfGGKHCluQtRvKt5zeh59x851VVj5iJw8mFGfwXFyUUANalVkl87F2H/Fsnpxz0ROWEN6KbIm6tLh00IJR7xmJsbD5AfxAiAwuodXrbTzrlanf5LitLOTBzxF3RWuR0gmcC7jnlMFPzxNkbMrkwLvA+kqmyzu0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001014; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=fH6BmxUho5LAsm/ui8NrspsMc4326JjxoLmd3tdetoE=; b=mafQeF5aAwbGnBuj7trG0/cp6IjcBU+2eHClxSA/vxRhIpIMj4eHWww6voaWzkgK1nOqsIRMJDMadrIRiMt1TPRfaklSTkjA/hbRhFyV+N1QC62h/cX2v9hFKUQoVac07nFtSat0oeJWD9a8cDA5/EDHPqj4fMMcoIu7DBnT0h8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45886+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001014126536.7027566960284; Fri, 16 Aug 2019 17:16:54 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:52 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319235" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:49 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 04/37] CoffeelakeSiliconPkg/Pch: Add include headers Date: Fri, 16 Aug 2019 17:15:30 -0700 Message-Id: <20190817001603.30632-5-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001013; bh=yYrGeUrU0eTfllbHr/JZoC4UsDwzTF+VB4KhyMsIdxM=; h=Cc:Date:From:Reply-To:Subject:To; b=JzUbsFFejNRgbRBrWHUMq3mtGcYb4uKsOUe0RU7eEVmp7EEn0OZuzUpL0WuIdCrbEXS CCPd2zrFXP2KokHr+w0GeF13r2uEcijp6JWcS7uZE00+2aI6l0MkjmaIBtq9zHVB0s1cL dgGgMfhtLnYnOVKmSISBcH3Hu5yUPyXYx1g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds Pch/Include headers. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h = | 135 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h = | 326 +++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h = | 381 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h = | 340 +++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h = | 241 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h = | 200 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h = | 54 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h = | 38 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h = | 80 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h = | 53 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageDetectHob.h = | 47 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h = | 47 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h = | 59 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResources.h = | 53 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h = | 23 ++ 15 files changed, 2077 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h new file mode 100644 index 0000000000..91222fd54d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/DxeHdaNhlt.h @@ -0,0 +1,135 @@ +/** @file + Header file for DxePchHdaNhltLib - NHLT structure definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_HDA_NHLT_H_ +#define _DXE_HDA_NHLT_H_ + +#include + +// +// ACPI support protocol instance signature definition. +// +#define NHLT_ACPI_TABLE_SIGNATURE SIGNATURE_32 ('N', 'H', 'L', 'T') + +// MSFT defined structures +#define SPEAKER_FRONT_LEFT 0x1 +#define SPEAKER_FRONT_RIGHT 0x2 +#define SPEAKER_FRONT_CENTER 0x4 +#define SPEAKER_BACK_LEFT 0x10 +#define SPEAKER_BACK_RIGHT 0x20 + +#define KSAUDIO_SPEAKER_MONO (SPEAKER_FRONT_CENTER) +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT) +#define KSAUDIO_SPEAKER_QUAD (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT |= SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT) + +#define WAVE_FORMAT_EXTENSIBLE 0xFFFE +#define KSDATAFORMAT_SUBTYPE_PCM \ + {0x00000001, 0x0000, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, = 0x9b, 0x71}} + +#pragma pack (push, 1) + +typedef struct { + UINT16 wFormatTag; + UINT16 nChannels; + UINT32 nSamplesPerSec; + UINT32 nAvgBytesPerSec; + UINT16 nBlockAlign; + UINT16 wBitsPerSample; + UINT16 cbSize; +} WAVEFORMATEX; + +typedef struct { + WAVEFORMATEX Format; + union { + UINT16 wValidBitsPerSample; + UINT16 wSamplesPerBlock; + UINT16 wReserved; + } Samples; + UINT32 dwChannelMask; + GUID SubFormat; +} WAVEFORMATEXTENSIBLE; + +// +// List of supported link type. +// +enum NHLT_LINK_TYPE +{ + HdaNhltLinkHd =3D 0, + HdaNhltLinkDsp =3D 1, + HdaNhltLinkDmic =3D 2, + HdaNhltLinkSsp =3D 3, + HdaNhltLinkInvalid +}; + +// +// List of supported device type. +// +enum NHLT_DEVICE_TYPE +{ + HdaNhltDeviceBt =3D 0, + HdaNhltDeviceDmic =3D 1, + HdaNhltDeviceI2s =3D 4, + HdaNhltDeviceInvalid +}; + +typedef struct { + UINT32 CapabilitiesSize; + UINT8 Capabilities[1]; +} SPECIFIC_CONFIG; + +typedef struct { + WAVEFORMATEXTENSIBLE Format; + SPECIFIC_CONFIG FormatConfiguration; +} FORMAT_CONFIG; + +typedef struct { + UINT8 FormatsCount; + FORMAT_CONFIG FormatsConfiguration[1]; +} FORMATS_CONFIG; + +typedef struct { + UINT8 DeviceId[16]; + UINT8 DeviceInstanceId; + UINT8 DevicePortId; +} DEVICE_INFO; + +typedef struct { + UINT8 DeviceInfoCount; + DEVICE_INFO DeviceInformation[1]; +} DEVICES_INFO; + +typedef struct { + UINT32 EndpointDescriptorLength; + UINT8 LinkType; + UINT8 InstanceId; + UINT16 HwVendorId; + UINT16 HwDeviceId; + UINT16 HwRevisionId; + UINT32 HwSubsystemId; + UINT8 DeviceType; + UINT8 Direction; + UINT8 VirtualBusId; + SPECIFIC_CONFIG EndpointConfig; + FORMATS_CONFIG FormatsConfig; + DEVICES_INFO DevicesInformation; +} ENDPOINT_DESCRIPTOR; + +// +// High Level Table structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'} + UINT8 EndpointCount; // Actual number of endpoin= ts + ENDPOINT_DESCRIPTOR EndpointDescriptors[1]; + SPECIFIC_CONFIG OedConfiguration; +} NHLT_ACPI_TABLE; + +#pragma pack (pop) + +#endif // _DXE_HDA_NHLT_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h new file mode 100644 index 0000000000..babbf1ce3a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioConfig.h @@ -0,0 +1,326 @@ +/** @file + Header file for GpioConfig structure used by GPIO library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_CONFIG_H_ +#define _GPIO_CONFIG_H_ + +#pragma pack(push, 1) + +/// +/// For any GpioPad usage in code use GPIO_PAD type +/// +typedef UINT32 GPIO_PAD; + + +/// +/// For any GpioGroup usage in code use GPIO_GROUP type +/// +typedef UINT32 GPIO_GROUP; + +/** + GPIO configuration structure used for pin programming. + Structure contains fields that can be used to configure pad. +**/ +typedef struct { + /** + Pad Mode + Pad can be set as GPIO or one of its native functions. + When in native mode setting Direction (except Inversion), OutputState, + InterruptConfig, Host Software Pad Ownership and OutputStateLock are unn= ecessary. + Refer to definition of GPIO_PAD_MODE. + Refer to EDS for each native mode according to the pad. + **/ + UINT32 PadMode : 5; + /** + Host Software Pad Ownership + Set pad to ACPI mode or GPIO Driver Mode. + Refer to definition of GPIO_HOSTSW_OWN. + **/ + UINT32 HostSoftPadOwn : 2; + /** + GPIO Direction + Can choose between In, In with inversion, Out, both In and Out, both In = with inversion and out or disabling both. + Refer to definition of GPIO_DIRECTION for supported settings. + **/ + UINT32 Direction : 6; + /** + Output State + Set Pad output value. + Refer to definition of GPIO_OUTPUT_STATE for supported settings. + This setting takes place when output is enabled. + **/ + UINT32 OutputState : 2; + /** + GPIO Interrupt Configuration + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). + This setting is applicable only if GPIO is in GpioMode with input enable= d. + Refer to definition of GPIO_INT_CONFIG for supported settings. + **/ + UINT32 InterruptConfig : 9; + /** + GPIO Power Configuration. + This setting controls Pad Reset Configuration. + Refer to definition of GPIO_RESET_CONFIG for supported settings. + **/ + UINT32 PowerConfig : 8; + /** + GPIO Electrical Configuration + This setting controls pads termination. + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. + **/ + UINT32 ElectricalConfig : 9; + /** + GPIO Lock Configuration + This setting controls pads lock. + Refer to definition of GPIO_LOCK_CONFIG for supported settings. + **/ + UINT32 LockConfig : 4; + /** + Additional GPIO configuration + Refer to definition of GPIO_OTHER_CONFIG for supported settings. + **/ + UINT32 OtherSettings : 9; + UINT32 RsvdBits : 10; ///< Reserved bits for future extension +} GPIO_CONFIG; + + +typedef enum { + GpioHardwareDefault =3D 0x0 ///< Leave setting unmodified +} GPIO_HARDWARE_DEFAULT; + +/** + GPIO Pad Mode + Refer to GPIO documentation on native functions available for certain pa= d. + If GPIO is set to one of NativeX modes then following settings are not a= pplicable + and can be skipped: + - Interrupt related settings + - Host Software Ownership + - Output/Input enabling/disabling + - Output lock +**/ +typedef enum { + GpioPadModeGpio =3D 0x1, + GpioPadModeNative1 =3D 0x3, + GpioPadModeNative2 =3D 0x5, + GpioPadModeNative3 =3D 0x7, + GpioPadModeNative4 =3D 0x9, + GpioPadModeNative5 =3D 0xB +} GPIO_PAD_MODE; + +/** + Host Software Pad Ownership modes + This setting affects GPIO interrupt status registers. Depending on chose= n ownership + some GPIO Interrupt status register get updated and other masked. + Please refer to EDS for HOSTSW_OWN register description. +**/ +typedef enum { + GpioHostOwnDefault =3D 0x0, ///< Leave ownership value unmodified + /** + Set HOST ownership to ACPI. + Use this setting if pad is not going to be used by GPIO OS driver. + If GPIO is configured to generate SCI/SMI/NMI then this setting must be + used for interrupts to work + **/ + GpioHostOwnAcpi =3D 0x1, + /** + Set HOST ownership to GPIO Driver mode. + Use this setting only if GPIO pad should be controlled by GPIO OS Driver. + GPIO OS Driver will be able to control the pad if appropriate entry in + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descript= ors) + **/ + GpioHostOwnGpio =3D 0x3 +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault =3D 0x0, ///< Leave pad direction = setting unmodified + GpioDirInOut =3D (0x1 | (0x1 << 3)), ///< Set pad for both out= put and input + GpioDirInInvOut =3D (0x1 | (0x3 << 3)), ///< Set pad for both out= put and input with inversion + GpioDirIn =3D (0x3 | (0x1 << 3)), ///< Set pad for input on= ly + GpioDirInInv =3D (0x3 | (0x3 << 3)), ///< Set pad for input wi= th inversion + GpioDirOut =3D 0x5, ///< Set pad for output o= nly + GpioDirNone =3D 0x7 ///< Disable both output = and input +} GPIO_DIRECTION; + +/** + GPIO Output State + This field is relevant only if output is enabled +**/ +typedef enum { + GpioOutDefault =3D 0x0, ///< Leave output value unmodified + GpioOutLow =3D 0x1, ///< Set output to low + GpioOutHigh =3D 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/** + GPIO interrupt configuration + This setting is applicable only if pad is in GPIO mode and has input ena= bled. + GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/S= CI/SMI/NMI) + and how it is triggered (edge or level). Refer to PADCFG_DW0 register de= scription in + EDS for details on this settings. + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to G= pioIntBothEdge + to describe an interrupt e.g. GpioIntApic | GpioIntLevel + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this = pad. + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this = pad. + Not all GPIO are capable of generating an SMI or NMI interrupt. + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as t= his + interrupt cannot be shared and its IRQn number is not configurable. + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel) + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt des= criptor + exist then use only trigger type setting (from GpioIntLevel to GpioIntBo= thEdge). + This type of GPIO Driver interrupt doesn't have any additional routing s= etting + required to be set by BIOS. Interrupt is handled by GPIO OS Driver. +**/ + +typedef enum { + GpioIntDefault =3D 0x0, ///< Leave value of interrupt routing= unmodified + GpioIntDis =3D 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI inte= rrupt generation + GpioIntNmi =3D 0x3, ///< Enable NMI interrupt only + GpioIntSmi =3D 0x5, ///< Enable SMI interrupt only + GpioIntSci =3D 0x9, ///< Enable SCI interrupt only + GpioIntApic =3D 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel =3D (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge =3D (0x3 << 5), ///< Set interrupt as edge triggered = (type of edge depends on input inversion) + GpioIntLvlEdgDis =3D (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge =3D (0x7 << 5) ///< Set interrupt as both edge trigg= ered +} GPIO_INT_CONFIG; + +#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CON= FIG for interrupt source +#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CON= FIG for interrupt type + +/** + GPIO Power Configuration + GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) w= hich will + be used to reset certain GPIO settings. + Refer to EDS for settings that are controllable by PadRstCfg. +**/ +typedef enum { + GpioResetDefault =3D 0x00, ///< Leave value of pad reset unmodi= fied + /** + Resume Reset (RSMRST) + GPP: PadRstCfg =3D 00b =3D "Powergood" + GPD: PadRstCfg =3D 11b =3D "Resume Reset" + Pad setting will reset on: + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + **/ + GpioResumeReset =3D 0x01, + /** + Host Deep Reset + PadRstCfg =3D 01b =3D "Deep GPIO Reset" + Pad settings will reset on: + - Warm/Cold/Global reset + - DeepSx transition + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + **/ + GpioHostDeepReset =3D 0x03, + /** + Platform Reset (PLTRST) + PadRstCfg =3D 10b =3D "GPIO Reset" + Pad settings will reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + - G3 + **/ + GpioPlatformReset =3D 0x05, + /** + Deep Sleep Well Reset (DSW_PWROK) + GPP: not applicable + GPD: PadRstCfg =3D 00b =3D "Powergood" + Pad settings will reset on: + - G3 + Pad settings will not reset on: + - S3/S4/S5 transition + - Warm/Cold/Global reset + - DeepSx transition + **/ + GpioDswReset =3D 0x07 +} GPIO_RESET_CONFIG; + +/** + GPIO Electrical Configuration + Configuration options for GPIO termination setting +**/ +typedef enum { + GpioTermDefault =3D 0x0, ///< Leave termination setting unmodi= fied + GpioTermNone =3D 0x1, ///< none + GpioTermWpd5K =3D 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K =3D 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K =3D 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K =3D 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K =3D 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K =3D 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K =3D 0x1B, ///< 1kOhm & 2kOhm weak pull-up + /** + Native function controls pads termination + This setting is applicable only to some native modes. + Please check EDS to determine which native functionality + can control pads termination + **/ + GpioTermNative =3D 0x1F +} GPIO_ELECTRICAL_CONFIG; + +#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for = GPIO_ELECTRICAL_CONFIG for termination value + +/** + GPIO LockConfiguration + Set GPIO configuration lock and output state lock. + GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed. + By default GPIO pads will be locked unless GPIO lib is explicitly + informed that certain pad is to be left unlocked. + Lock settings reset is in Powergood domain. Care must be taken when usin= g this setting + as fields it locks may be reset by a different signal and can be control= led + by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library pro= vides + functions which allow to unlock a GPIO pad. If possible each GPIO lib fu= nction will try to unlock + an already locked pad upon request for reconfiguration +**/ +typedef enum { + /** + Perform default action + - if pad is an GPO, lock configuration but leave output unlocked + - if pad is an GPI, lock everything + - if pad is in native, lock everything +**/ + GpioLockDefault =3D 0x0, + GpioPadConfigUnlock =3D 0x3, ///< Leave Pad configuration unlocked + GpioPadConfigLock =3D 0x1, ///< Lock Pad configuration + GpioOutputStateUnlock =3D 0xC, ///< Leave Pad output control unlocked + GpioPadUnlock =3D 0xF, ///< Leave both Pad configuration and ou= tput control unlocked + GpioPadLock =3D 0x5 ///< Lock both Pad configuration and out= put control +} GPIO_LOCK_CONFIG; + +#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOC= K_CONFIG for Pad Configuration Lock +#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOC= K_CONFIG for Pad Output Lock + +/** + Other GPIO Configuration + GPIO_OTHER_CONFIG is used for less often settings and for future extensi= ons + Supported settings: + - RX raw override to '1' - allows to override input value to '1' + This setting is applicable only if in input mode (both in GPIO and n= ative usage). + The override takes place at the internal pad state directly from buf= fer and before the RXINV. +**/ +typedef enum { + GpioRxRaw1Default =3D 0x0, ///< Use default input override va= lue + GpioRxRaw1Dis =3D 0x1, ///< Don't override input + GpioRxRaw1En =3D 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_= OTHER_CONFIG for RxRaw1 setting + +#pragma pack(pop) + +#endif //_GPIO_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h new file mode 100644 index 0000000000..524328d3e3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlH.h @@ -0,0 +1,381 @@ +/** @file + GPIO pins, + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_CNL_H_H_ +#define _GPIO_PINS_CNL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// Unique ID used in GpioPad defines +/// +#define GPIO_CNL_H_CHIPSET_ID 0x3 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_CNL_H_GROUP_GPP_A 0x0300 +#define GPIO_CNL_H_GROUP_GPP_B 0x0301 +#define GPIO_CNL_H_GROUP_GPP_C 0x0302 +#define GPIO_CNL_H_GROUP_GPP_D 0x0303 +#define GPIO_CNL_H_GROUP_GPP_E 0x0304 +#define GPIO_CNL_H_GROUP_GPP_F 0x0305 +#define GPIO_CNL_H_GROUP_GPP_G 0x0306 +#define GPIO_CNL_H_GROUP_GPP_H 0x0307 +#define GPIO_CNL_H_GROUP_GPP_I 0x0308 +#define GPIO_CNL_H_GROUP_GPP_J 0x0309 +#define GPIO_CNL_H_GROUP_GPP_K 0x030A +#define GPIO_CNL_H_GROUP_GPD 0x030B +#define GPIO_CNL_H_GROUP_VGPIO 0x030C +#define GPIO_CNL_H_GROUP_SPI 0x030D +#define GPIO_CNL_H_GROUP_AZA 0x030E +#define GPIO_CNL_H_GROUP_CPU 0x030F +#define GPIO_CNL_H_GROUP_JTAG 0x0310 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_CNL_H_GPP_A0 0x03000000 +#define GPIO_CNL_H_GPP_A1 0x03000001 +#define GPIO_CNL_H_GPP_A2 0x03000002 +#define GPIO_CNL_H_GPP_A3 0x03000003 +#define GPIO_CNL_H_GPP_A4 0x03000004 +#define GPIO_CNL_H_GPP_A5 0x03000005 +#define GPIO_CNL_H_GPP_A6 0x03000006 +#define GPIO_CNL_H_GPP_A7 0x03000007 +#define GPIO_CNL_H_GPP_A8 0x03000008 +#define GPIO_CNL_H_GPP_A9 0x03000009 +#define GPIO_CNL_H_GPP_A10 0x0300000A +#define GPIO_CNL_H_GPP_A11 0x0300000B +#define GPIO_CNL_H_GPP_A12 0x0300000C +#define GPIO_CNL_H_GPP_A13 0x0300000D +#define GPIO_CNL_H_GPP_A14 0x0300000E +#define GPIO_CNL_H_GPP_A15 0x0300000F +#define GPIO_CNL_H_GPP_A16 0x03000010 +#define GPIO_CNL_H_GPP_A17 0x03000011 +#define GPIO_CNL_H_GPP_A18 0x03000012 +#define GPIO_CNL_H_GPP_A19 0x03000013 +#define GPIO_CNL_H_GPP_A20 0x03000014 +#define GPIO_CNL_H_GPP_A21 0x03000015 +#define GPIO_CNL_H_GPP_A22 0x03000016 +#define GPIO_CNL_H_GPP_A23 0x03000017 +#define GPIO_CNL_H_ESPI_CLK_LOOPBK 0x03000018 + +#define GPIO_CNL_H_GPP_B0 0x03010000 +#define GPIO_CNL_H_GPP_B1 0x03010001 +#define GPIO_CNL_H_GPP_B2 0x03010002 +#define GPIO_CNL_H_GPP_B3 0x03010003 +#define GPIO_CNL_H_GPP_B4 0x03010004 +#define GPIO_CNL_H_GPP_B5 0x03010005 +#define GPIO_CNL_H_GPP_B6 0x03010006 +#define GPIO_CNL_H_GPP_B7 0x03010007 +#define GPIO_CNL_H_GPP_B8 0x03010008 +#define GPIO_CNL_H_GPP_B9 0x03010009 +#define GPIO_CNL_H_GPP_B10 0x0301000A +#define GPIO_CNL_H_GPP_B11 0x0301000B +#define GPIO_CNL_H_GPP_B12 0x0301000C +#define GPIO_CNL_H_GPP_B13 0x0301000D +#define GPIO_CNL_H_GPP_B14 0x0301000E +#define GPIO_CNL_H_GPP_B15 0x0301000F +#define GPIO_CNL_H_GPP_B16 0x03010010 +#define GPIO_CNL_H_GPP_B17 0x03010011 +#define GPIO_CNL_H_GPP_B18 0x03010012 +#define GPIO_CNL_H_GPP_B19 0x03010013 +#define GPIO_CNL_H_GPP_B20 0x03010014 +#define GPIO_CNL_H_GPP_B21 0x03010015 +#define GPIO_CNL_H_GPP_B22 0x03010016 +#define GPIO_CNL_H_GPP_B23 0x03010017 +#define GPIO_CNL_H_GSPI0_CLK_LOOPBK 0x03010018 +#define GPIO_CNL_H_GSPI1_CLK_LOOPBK 0x03010019 + +#define GPIO_CNL_H_GPP_C0 0x03020000 +#define GPIO_CNL_H_GPP_C1 0x03020001 +#define GPIO_CNL_H_GPP_C2 0x03020002 +#define GPIO_CNL_H_GPP_C3 0x03020003 +#define GPIO_CNL_H_GPP_C4 0x03020004 +#define GPIO_CNL_H_GPP_C5 0x03020005 +#define GPIO_CNL_H_GPP_C6 0x03020006 +#define GPIO_CNL_H_GPP_C7 0x03020007 +#define GPIO_CNL_H_GPP_C8 0x03020008 +#define GPIO_CNL_H_GPP_C9 0x03020009 +#define GPIO_CNL_H_GPP_C10 0x0302000A +#define GPIO_CNL_H_GPP_C11 0x0302000B +#define GPIO_CNL_H_GPP_C12 0x0302000C +#define GPIO_CNL_H_GPP_C13 0x0302000D +#define GPIO_CNL_H_GPP_C14 0x0302000E +#define GPIO_CNL_H_GPP_C15 0x0302000F +#define GPIO_CNL_H_GPP_C16 0x03020010 +#define GPIO_CNL_H_GPP_C17 0x03020011 +#define GPIO_CNL_H_GPP_C18 0x03020012 +#define GPIO_CNL_H_GPP_C19 0x03020013 +#define GPIO_CNL_H_GPP_C20 0x03020014 +#define GPIO_CNL_H_GPP_C21 0x03020015 +#define GPIO_CNL_H_GPP_C22 0x03020016 +#define GPIO_CNL_H_GPP_C23 0x03020017 + +#define GPIO_CNL_H_GPP_D0 0x03030000 +#define GPIO_CNL_H_GPP_D1 0x03030001 +#define GPIO_CNL_H_GPP_D2 0x03030002 +#define GPIO_CNL_H_GPP_D3 0x03030003 +#define GPIO_CNL_H_GPP_D4 0x03030004 +#define GPIO_CNL_H_GPP_D5 0x03030005 +#define GPIO_CNL_H_GPP_D6 0x03030006 +#define GPIO_CNL_H_GPP_D7 0x03030007 +#define GPIO_CNL_H_GPP_D8 0x03030008 +#define GPIO_CNL_H_GPP_D9 0x03030009 +#define GPIO_CNL_H_GPP_D10 0x0303000A +#define GPIO_CNL_H_GPP_D11 0x0303000B +#define GPIO_CNL_H_GPP_D12 0x0303000C +#define GPIO_CNL_H_GPP_D13 0x0303000D +#define GPIO_CNL_H_GPP_D14 0x0303000E +#define GPIO_CNL_H_GPP_D15 0x0303000F +#define GPIO_CNL_H_GPP_D16 0x03030010 +#define GPIO_CNL_H_GPP_D17 0x03030011 +#define GPIO_CNL_H_GPP_D18 0x03030012 +#define GPIO_CNL_H_GPP_D19 0x03030013 +#define GPIO_CNL_H_GPP_D20 0x03030014 +#define GPIO_CNL_H_GPP_D21 0x03030015 +#define GPIO_CNL_H_GPP_D22 0x03030016 +#define GPIO_CNL_H_GPP_D23 0x03030017 + +#define GPIO_CNL_H_GPP_E0 0x03040000 +#define GPIO_CNL_H_GPP_E1 0x03040001 +#define GPIO_CNL_H_GPP_E2 0x03040002 +#define GPIO_CNL_H_GPP_E3 0x03040003 +#define GPIO_CNL_H_GPP_E4 0x03040004 +#define GPIO_CNL_H_GPP_E5 0x03040005 +#define GPIO_CNL_H_GPP_E6 0x03040006 +#define GPIO_CNL_H_GPP_E7 0x03040007 +#define GPIO_CNL_H_GPP_E8 0x03040008 +#define GPIO_CNL_H_GPP_E9 0x03040009 +#define GPIO_CNL_H_GPP_E10 0x0304000A +#define GPIO_CNL_H_GPP_E11 0x0304000B +#define GPIO_CNL_H_GPP_E12 0x0304000C + +#define GPIO_CNL_H_GPP_F0 0x03050000 +#define GPIO_CNL_H_GPP_F1 0x03050001 +#define GPIO_CNL_H_GPP_F2 0x03050002 +#define GPIO_CNL_H_GPP_F3 0x03050003 +#define GPIO_CNL_H_GPP_F4 0x03050004 +#define GPIO_CNL_H_GPP_F5 0x03050005 +#define GPIO_CNL_H_GPP_F6 0x03050006 +#define GPIO_CNL_H_GPP_F7 0x03050007 +#define GPIO_CNL_H_GPP_F8 0x03050008 +#define GPIO_CNL_H_GPP_F9 0x03050009 +#define GPIO_CNL_H_GPP_F10 0x0305000A +#define GPIO_CNL_H_GPP_F11 0x0305000B +#define GPIO_CNL_H_GPP_F12 0x0305000C +#define GPIO_CNL_H_GPP_F13 0x0305000D +#define GPIO_CNL_H_GPP_F14 0x0305000E +#define GPIO_CNL_H_GPP_F15 0x0305000F +#define GPIO_CNL_H_GPP_F16 0x03050010 +#define GPIO_CNL_H_GPP_F17 0x03050011 +#define GPIO_CNL_H_GPP_F18 0x03050012 +#define GPIO_CNL_H_GPP_F19 0x03050013 +#define GPIO_CNL_H_GPP_F20 0x03050014 +#define GPIO_CNL_H_GPP_F21 0x03050015 +#define GPIO_CNL_H_GPP_F22 0x03050016 +#define GPIO_CNL_H_GPP_F23 0x03050017 + +#define GPIO_CNL_H_GPP_G0 0x03060000 +#define GPIO_CNL_H_GPP_G1 0x03060001 +#define GPIO_CNL_H_GPP_G2 0x03060002 +#define GPIO_CNL_H_GPP_G3 0x03060003 +#define GPIO_CNL_H_GPP_G4 0x03060004 +#define GPIO_CNL_H_GPP_G5 0x03060005 +#define GPIO_CNL_H_GPP_G6 0x03060006 +#define GPIO_CNL_H_GPP_G7 0x03060007 + +#define GPIO_CNL_H_GPP_H0 0x03070000 +#define GPIO_CNL_H_GPP_H1 0x03070001 +#define GPIO_CNL_H_GPP_H2 0x03070002 +#define GPIO_CNL_H_GPP_H3 0x03070003 +#define GPIO_CNL_H_GPP_H4 0x03070004 +#define GPIO_CNL_H_GPP_H5 0x03070005 +#define GPIO_CNL_H_GPP_H6 0x03070006 +#define GPIO_CNL_H_GPP_H7 0x03070007 +#define GPIO_CNL_H_GPP_H8 0x03070008 +#define GPIO_CNL_H_GPP_H9 0x03070009 +#define GPIO_CNL_H_GPP_H10 0x0307000A +#define GPIO_CNL_H_GPP_H11 0x0307000B +#define GPIO_CNL_H_GPP_H12 0x0307000C +#define GPIO_CNL_H_GPP_H13 0x0307000D +#define GPIO_CNL_H_GPP_H14 0x0307000E +#define GPIO_CNL_H_GPP_H15 0x0307000F +#define GPIO_CNL_H_GPP_H16 0x03070010 +#define GPIO_CNL_H_GPP_H17 0x03070011 +#define GPIO_CNL_H_GPP_H18 0x03070012 +#define GPIO_CNL_H_GPP_H19 0x03070013 +#define GPIO_CNL_H_GPP_H20 0x03070014 +#define GPIO_CNL_H_GPP_H21 0x03070015 +#define GPIO_CNL_H_GPP_H22 0x03070016 +#define GPIO_CNL_H_GPP_H23 0x03070017 + +#define GPIO_CNL_H_GPP_I0 0x03080000 +#define GPIO_CNL_H_GPP_I1 0x03080001 +#define GPIO_CNL_H_GPP_I2 0x03080002 +#define GPIO_CNL_H_GPP_I3 0x03080003 +#define GPIO_CNL_H_GPP_I4 0x03080004 +#define GPIO_CNL_H_GPP_I5 0x03080005 +#define GPIO_CNL_H_GPP_I6 0x03080006 +#define GPIO_CNL_H_GPP_I7 0x03080007 +#define GPIO_CNL_H_GPP_I8 0x03080008 +#define GPIO_CNL_H_GPP_I9 0x03080009 +#define GPIO_CNL_H_GPP_I10 0x0308000A +#define GPIO_CNL_H_GPP_I11 0x0308000B +#define GPIO_CNL_H_GPP_I12 0x0308000C +#define GPIO_CNL_H_GPP_I13 0x0308000D +#define GPIO_CNL_H_GPP_I14 0x0308000E +#define GPIO_CNL_H_SYS_PWROK 0x0308000F +#define GPIO_CNL_H_SYS_RESETB 0x03080010 +#define GPIO_CNL_H_MLK_RSTB 0x03080011 + +#define GPIO_CNL_H_GPP_J0 0x03090000 +#define GPIO_CNL_H_GPP_J1 0x03090001 +#define GPIO_CNL_H_GPP_J2 0x03090002 +#define GPIO_CNL_H_GPP_J3 0x03090003 +#define GPIO_CNL_H_GPP_J4 0x03090004 +#define GPIO_CNL_H_GPP_J5 0x03090005 +#define GPIO_CNL_H_GPP_J6 0x03090006 +#define GPIO_CNL_H_GPP_J7 0x03090007 +#define GPIO_CNL_H_GPP_J8 0x03090008 +#define GPIO_CNL_H_GPP_J9 0x03090009 +#define GPIO_CNL_H_GPP_J10 0x0309000A +#define GPIO_CNL_H_GPP_J11 0x0309000B + +#define GPIO_CNL_H_GPP_K0 0x030A0000 +#define GPIO_CNL_H_GPP_K1 0x030A0001 +#define GPIO_CNL_H_GPP_K2 0x030A0002 +#define GPIO_CNL_H_GPP_K3 0x030A0003 +#define GPIO_CNL_H_GPP_K4 0x030A0004 +#define GPIO_CNL_H_GPP_K5 0x030A0005 +#define GPIO_CNL_H_GPP_K6 0x030A0006 +#define GPIO_CNL_H_GPP_K7 0x030A0007 +#define GPIO_CNL_H_GPP_K8 0x030A0008 +#define GPIO_CNL_H_GPP_K9 0x030A0009 +#define GPIO_CNL_H_GPP_K10 0x030A000A +#define GPIO_CNL_H_GPP_K11 0x030A000B +#define GPIO_CNL_H_GPP_K12 0x030A000C +#define GPIO_CNL_H_GPP_K13 0x030A000D +#define GPIO_CNL_H_GPP_K14 0x030A000E +#define GPIO_CNL_H_GPP_K15 0x030A000F +#define GPIO_CNL_H_GPP_K16 0x030A0010 +#define GPIO_CNL_H_GPP_K17 0x030A0011 +#define GPIO_CNL_H_GPP_K18 0x030A0012 +#define GPIO_CNL_H_GPP_K19 0x030A0013 +#define GPIO_CNL_H_GPP_K20 0x030A0014 +#define GPIO_CNL_H_GPP_K21 0x030A0015 +#define GPIO_CNL_H_GPP_K22 0x030A0016 +#define GPIO_CNL_H_GPP_K23 0x030A0017 + +#define GPIO_CNL_H_GPD0 0x030B0000 +#define GPIO_CNL_H_GPD1 0x030B0001 +#define GPIO_CNL_H_GPD2 0x030B0002 +#define GPIO_CNL_H_GPD3 0x030B0003 +#define GPIO_CNL_H_GPD4 0x030B0004 +#define GPIO_CNL_H_GPD5 0x030B0005 +#define GPIO_CNL_H_GPD6 0x030B0006 +#define GPIO_CNL_H_GPD7 0x030B0007 +#define GPIO_CNL_H_GPD8 0x030B0008 +#define GPIO_CNL_H_GPD9 0x030B0009 +#define GPIO_CNL_H_GPD10 0x030B000A +#define GPIO_CNL_H_GPD11 0x030B000B +#define GPIO_CNL_H_SLP_LANB 0x030B000C +#define GPIO_CNL_H_SLP_SUSB 0x030B000D +#define GPIO_CNL_H_SLP_WAKEB 0x030B000E +#define GPIO_CNL_H_SLP_DRAM_RESETB 0x030B000F + +#define GPIO_CNL_H_VGPIO0 0x030C0000 +#define GPIO_CNL_H_VGPIO1 0x030C0001 +#define GPIO_CNL_H_VGPIO2 0x030C0002 +#define GPIO_CNL_H_VGPIO3 0x030C0003 +#define GPIO_CNL_H_VGPIO4 0x030C0004 +#define GPIO_CNL_H_VGPIO5 0x030C0005 +#define GPIO_CNL_H_VGPIO6 0x030C0006 +#define GPIO_CNL_H_VGPIO7 0x030C0007 +#define GPIO_CNL_H_VGPIO8 0x030C0008 +#define GPIO_CNL_H_VGPIO9 0x030C0009 +#define GPIO_CNL_H_VGPIO10 0x030C000A +#define GPIO_CNL_H_VGPIO11 0x030C000B +#define GPIO_CNL_H_VGPIO12 0x030C000C +#define GPIO_CNL_H_VGPIO13 0x030C000D +#define GPIO_CNL_H_VGPIO14 0x030C000E +#define GPIO_CNL_H_VGPIO15 0x030C000F +#define GPIO_CNL_H_VGPIO16 0x030C0010 +#define GPIO_CNL_H_VGPIO17 0x030C0011 +#define GPIO_CNL_H_VGPIO18 0x030C0012 +#define GPIO_CNL_H_VGPIO19 0x030C0013 +#define GPIO_CNL_H_VGPIO20 0x030C0014 +#define GPIO_CNL_H_VGPIO21 0x030C0015 +#define GPIO_CNL_H_VGPIO22 0x030C0016 +#define GPIO_CNL_H_VGPIO23 0x030C0017 +#define GPIO_CNL_H_VGPIO24 0x030C0018 +#define GPIO_CNL_H_VGPIO25 0x030C0019 +#define GPIO_CNL_H_VGPIO26 0x030C001A +#define GPIO_CNL_H_VGPIO27 0x030C001B +#define GPIO_CNL_H_VGPIO28 0x030C001C +#define GPIO_CNL_H_VGPIO29 0x030C001D +#define GPIO_CNL_H_VGPIO30 0x030C001E +#define GPIO_CNL_H_VGPIO31 0x030C001F +#define GPIO_CNL_H_VGPIO32 0x030C0020 +#define GPIO_CNL_H_VGPIO33 0x030C0021 +#define GPIO_CNL_H_VGPIO34 0x030C0022 +#define GPIO_CNL_H_VGPIO35 0x030C0023 +#define GPIO_CNL_H_VGPIO36 0x030C0024 +#define GPIO_CNL_H_VGPIO37 0x030C0025 +#define GPIO_CNL_H_VGPIO38 0x030C0026 +#define GPIO_CNL_H_VGPIO39 0x030C0027 + +#define GPIO_CNL_H_SPI0_IO_2 0x030D0000 +#define GPIO_CNL_H_SPI0_IO_3 0x030D0001 +#define GPIO_CNL_H_SPI0_MOSI_IO_0 0x030D0002 +#define GPIO_CNL_H_SPI0_MOSI_IO_1 0x030D0003 +#define GPIO_CNL_H_SPI0_TPM_CSB 0x030D0004 +#define GPIO_CNL_H_SPI0_FLASH_0_CSB 0x030D0005 +#define GPIO_CNL_H_SPI0_FLASH_1_CSB 0x030D0006 +#define GPIO_CNL_H_SPI0_CLK 0x030D0007 +#define GPIO_CNL_H_SPI0_CLK_LOOPBK 0x030D0008 + +#define GPIO_CNL_H_HDA_BCLK 0x030E0000 +#define GPIO_CNL_H_HDA_RSTB 0x030E0001 +#define GPIO_CNL_H_HDA_SYNC 0x030E0002 +#define GPIO_CNL_H_HDA_SDO 0x030E0003 +#define GPIO_CNL_H_HDA_SDI_0 0x030E0004 +#define GPIO_CNL_H_HDA_SDI_1 0x030E0005 +#define GPIO_CNL_H_SSP1_SFRM 0x030E0006 +#define GPIO_CNL_H_SSP1_TXD 0x030E0007 + +#define GPIO_CNL_H_HDACPU_SDI 0x030F0000 +#define GPIO_CNL_H_HDACPU_SDO 0x030F0001 +#define GPIO_CNL_H_HDACPU_SCLK 0x030F0002 +#define GPIO_CNL_H_PM_SYNC 0x030F0003 +#define GPIO_CNL_H_PECI 0x030F0004 +#define GPIO_CNL_H_CPUPWRGD 0x030F0005 +#define GPIO_CNL_H_THRMTRIPB 0x030F0006 +#define GPIO_CNL_H_PLTRST_CPUB 0x030F0007 +#define GPIO_CNL_H_PM_DOWN 0x030F0008 +#define GPIO_CNL_H_TRIGGER_IN 0x030F0009 +#define GPIO_CNL_H_TRIGGER_OUT 0x030F000A + +#define GPIO_CNL_H_JTAG_TDO 0x03100000 +#define GPIO_CNL_H_JTAGX 0x03100001 +#define GPIO_CNL_H_PRDYB 0x03100002 +#define GPIO_CNL_H_PREQB 0x03100003 +#define GPIO_CNL_H_CPU_TRSTB 0x03100004 +#define GPIO_CNL_H_JTAG_TDI 0x03100005 +#define GPIO_CNL_H_JTAG_TMS 0x03100006 +#define GPIO_CNL_H_JTAG_TCK 0x03100007 +#define GPIO_CNL_H_ITP_PMODE 0x03100008 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h= b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h new file mode 100644 index 0000000000..9ce5875ca5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsCnlLp.h @@ -0,0 +1,340 @@ +/** @file + GPIO pins, + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_CNL_LP_H_ +#define _GPIO_PINS_CNL_LP_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// Unique ID used in GpioPad defines +/// +#define GPIO_CNL_LP_CHIPSET_ID 0x4 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_CNL_LP_GROUP_GPP_A 0x0400 +#define GPIO_CNL_LP_GROUP_GPP_B 0x0401 +#define GPIO_CNL_LP_GROUP_GPP_C 0x0402 +#define GPIO_CNL_LP_GROUP_GPP_D 0x0403 +#define GPIO_CNL_LP_GROUP_GPP_E 0x0404 +#define GPIO_CNL_LP_GROUP_GPP_F 0x0405 +#define GPIO_CNL_LP_GROUP_GPP_G 0x0406 +#define GPIO_CNL_LP_GROUP_GPP_H 0x0407 +#define GPIO_CNL_LP_GROUP_GPD 0x0408 +#define GPIO_CNL_LP_GROUP_VGPIO 0x0409 +#define GPIO_CNL_LP_GROUP_SPI 0x040A +#define GPIO_CNL_LP_GROUP_AZA 0x040B +#define GPIO_CNL_LP_GROUP_CPU 0x040C +#define GPIO_CNL_LP_GROUP_JTAG 0x040D +#define GPIO_CNL_LP_GROUP_HVMOS 0x040E + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_CNL_LP_GPP_A0 0x04000000 +#define GPIO_CNL_LP_GPP_A1 0x04000001 +#define GPIO_CNL_LP_GPP_A2 0x04000002 +#define GPIO_CNL_LP_GPP_A3 0x04000003 +#define GPIO_CNL_LP_GPP_A4 0x04000004 +#define GPIO_CNL_LP_GPP_A5 0x04000005 +#define GPIO_CNL_LP_GPP_A6 0x04000006 +#define GPIO_CNL_LP_GPP_A7 0x04000007 +#define GPIO_CNL_LP_GPP_A8 0x04000008 +#define GPIO_CNL_LP_GPP_A9 0x04000009 +#define GPIO_CNL_LP_GPP_A10 0x0400000A +#define GPIO_CNL_LP_GPP_A11 0x0400000B +#define GPIO_CNL_LP_GPP_A12 0x0400000C +#define GPIO_CNL_LP_GPP_A13 0x0400000D +#define GPIO_CNL_LP_GPP_A14 0x0400000E +#define GPIO_CNL_LP_GPP_A15 0x0400000F +#define GPIO_CNL_LP_GPP_A16 0x04000010 +#define GPIO_CNL_LP_GPP_A17 0x04000011 +#define GPIO_CNL_LP_GPP_A18 0x04000012 +#define GPIO_CNL_LP_GPP_A19 0x04000013 +#define GPIO_CNL_LP_GPP_A20 0x04000014 +#define GPIO_CNL_LP_GPP_A21 0x04000015 +#define GPIO_CNL_LP_GPP_A22 0x04000016 +#define GPIO_CNL_LP_GPP_A23 0x04000017 +#define GPIO_CNL_LP_ESPI_CLK_LOOPBK 0x04000018 + +#define GPIO_CNL_LP_GPP_B0 0x04010000 +#define GPIO_CNL_LP_GPP_B1 0x04010001 +#define GPIO_CNL_LP_GPP_B2 0x04010002 +#define GPIO_CNL_LP_GPP_B3 0x04010003 +#define GPIO_CNL_LP_GPP_B4 0x04010004 +#define GPIO_CNL_LP_GPP_B5 0x04010005 +#define GPIO_CNL_LP_GPP_B6 0x04010006 +#define GPIO_CNL_LP_GPP_B7 0x04010007 +#define GPIO_CNL_LP_GPP_B8 0x04010008 +#define GPIO_CNL_LP_GPP_B9 0x04010009 +#define GPIO_CNL_LP_GPP_B10 0x0401000A +#define GPIO_CNL_LP_GPP_B11 0x0401000B +#define GPIO_CNL_LP_GPP_B12 0x0401000C +#define GPIO_CNL_LP_GPP_B13 0x0401000D +#define GPIO_CNL_LP_GPP_B14 0x0401000E +#define GPIO_CNL_LP_GPP_B15 0x0401000F +#define GPIO_CNL_LP_GPP_B16 0x04010010 +#define GPIO_CNL_LP_GPP_B17 0x04010011 +#define GPIO_CNL_LP_GPP_B18 0x04010012 +#define GPIO_CNL_LP_GPP_B19 0x04010013 +#define GPIO_CNL_LP_GPP_B20 0x04010014 +#define GPIO_CNL_LP_GPP_B21 0x04010015 +#define GPIO_CNL_LP_GPP_B22 0x04010016 +#define GPIO_CNL_LP_GPP_B23 0x04010017 +#define GPIO_CNL_LP_GSPI0_CLK_LOOPBK 0x04010018 +#define GPIO_CNL_LP_GSPI1_CLK_LOOPBK 0x04010019 + +#define GPIO_CNL_LP_GPP_C0 0x04020000 +#define GPIO_CNL_LP_GPP_C1 0x04020001 +#define GPIO_CNL_LP_GPP_C2 0x04020002 +#define GPIO_CNL_LP_GPP_C3 0x04020003 +#define GPIO_CNL_LP_GPP_C4 0x04020004 +#define GPIO_CNL_LP_GPP_C5 0x04020005 +#define GPIO_CNL_LP_GPP_C6 0x04020006 +#define GPIO_CNL_LP_GPP_C7 0x04020007 +#define GPIO_CNL_LP_GPP_C8 0x04020008 +#define GPIO_CNL_LP_GPP_C9 0x04020009 +#define GPIO_CNL_LP_GPP_C10 0x0402000A +#define GPIO_CNL_LP_GPP_C11 0x0402000B +#define GPIO_CNL_LP_GPP_C12 0x0402000C +#define GPIO_CNL_LP_GPP_C13 0x0402000D +#define GPIO_CNL_LP_GPP_C14 0x0402000E +#define GPIO_CNL_LP_GPP_C15 0x0402000F +#define GPIO_CNL_LP_GPP_C16 0x04020010 +#define GPIO_CNL_LP_GPP_C17 0x04020011 +#define GPIO_CNL_LP_GPP_C18 0x04020012 +#define GPIO_CNL_LP_GPP_C19 0x04020013 +#define GPIO_CNL_LP_GPP_C20 0x04020014 +#define GPIO_CNL_LP_GPP_C21 0x04020015 +#define GPIO_CNL_LP_GPP_C22 0x04020016 +#define GPIO_CNL_LP_GPP_C23 0x04020017 + +#define GPIO_CNL_LP_GPP_D0 0x04030000 +#define GPIO_CNL_LP_GPP_D1 0x04030001 +#define GPIO_CNL_LP_GPP_D2 0x04030002 +#define GPIO_CNL_LP_GPP_D3 0x04030003 +#define GPIO_CNL_LP_GPP_D4 0x04030004 +#define GPIO_CNL_LP_GPP_D5 0x04030005 +#define GPIO_CNL_LP_GPP_D6 0x04030006 +#define GPIO_CNL_LP_GPP_D7 0x04030007 +#define GPIO_CNL_LP_GPP_D8 0x04030008 +#define GPIO_CNL_LP_GPP_D9 0x04030009 +#define GPIO_CNL_LP_GPP_D10 0x0403000A +#define GPIO_CNL_LP_GPP_D11 0x0403000B +#define GPIO_CNL_LP_GPP_D12 0x0403000C +#define GPIO_CNL_LP_GPP_D13 0x0403000D +#define GPIO_CNL_LP_GPP_D14 0x0403000E +#define GPIO_CNL_LP_GPP_D15 0x0403000F +#define GPIO_CNL_LP_GPP_D16 0x04030010 +#define GPIO_CNL_LP_GPP_D17 0x04030011 +#define GPIO_CNL_LP_GPP_D18 0x04030012 +#define GPIO_CNL_LP_GPP_D19 0x04030013 +#define GPIO_CNL_LP_GPP_D20 0x04030014 +#define GPIO_CNL_LP_GPP_D21 0x04030015 +#define GPIO_CNL_LP_GPP_D22 0x04030016 +#define GPIO_CNL_LP_GPP_D23 0x04030017 + +#define GPIO_CNL_LP_GPP_E0 0x04040000 +#define GPIO_CNL_LP_GPP_E1 0x04040001 +#define GPIO_CNL_LP_GPP_E2 0x04040002 +#define GPIO_CNL_LP_GPP_E3 0x04040003 +#define GPIO_CNL_LP_GPP_E4 0x04040004 +#define GPIO_CNL_LP_GPP_E5 0x04040005 +#define GPIO_CNL_LP_GPP_E6 0x04040006 +#define GPIO_CNL_LP_GPP_E7 0x04040007 +#define GPIO_CNL_LP_GPP_E8 0x04040008 +#define GPIO_CNL_LP_GPP_E9 0x04040009 +#define GPIO_CNL_LP_GPP_E10 0x0404000A +#define GPIO_CNL_LP_GPP_E11 0x0404000B +#define GPIO_CNL_LP_GPP_E12 0x0404000C +#define GPIO_CNL_LP_GPP_E13 0x0404000D +#define GPIO_CNL_LP_GPP_E14 0x0404000E +#define GPIO_CNL_LP_GPP_E15 0x0404000F +#define GPIO_CNL_LP_GPP_E16 0x04040010 +#define GPIO_CNL_LP_GPP_E17 0x04040011 +#define GPIO_CNL_LP_GPP_E18 0x04040012 +#define GPIO_CNL_LP_GPP_E19 0x04040013 +#define GPIO_CNL_LP_GPP_E20 0x04040014 +#define GPIO_CNL_LP_GPP_E21 0x04040015 +#define GPIO_CNL_LP_GPP_E22 0x04040016 +#define GPIO_CNL_LP_GPP_E23 0x04040017 + +#define GPIO_CNL_LP_GPP_F0 0x04050000 +#define GPIO_CNL_LP_GPP_F1 0x04050001 +#define GPIO_CNL_LP_GPP_F2 0x04050002 +#define GPIO_CNL_LP_GPP_F3 0x04050003 +#define GPIO_CNL_LP_GPP_F4 0x04050004 +#define GPIO_CNL_LP_GPP_F5 0x04050005 +#define GPIO_CNL_LP_GPP_F6 0x04050006 +#define GPIO_CNL_LP_GPP_F7 0x04050007 +#define GPIO_CNL_LP_GPP_F8 0x04050008 +#define GPIO_CNL_LP_GPP_F9 0x04050009 +#define GPIO_CNL_LP_GPP_F10 0x0405000A +#define GPIO_CNL_LP_GPP_F11 0x0405000B +#define GPIO_CNL_LP_GPP_F12 0x0405000C +#define GPIO_CNL_LP_GPP_F13 0x0405000D +#define GPIO_CNL_LP_GPP_F14 0x0405000E +#define GPIO_CNL_LP_GPP_F15 0x0405000F +#define GPIO_CNL_LP_GPP_F16 0x04050010 +#define GPIO_CNL_LP_GPP_F17 0x04050011 +#define GPIO_CNL_LP_GPP_F18 0x04050012 +#define GPIO_CNL_LP_GPP_F19 0x04050013 +#define GPIO_CNL_LP_GPP_F20 0x04050014 +#define GPIO_CNL_LP_GPP_F21 0x04050015 +#define GPIO_CNL_LP_GPP_F22 0x04050016 +#define GPIO_CNL_LP_GPP_F23 0x04050017 + +#define GPIO_CNL_LP_GPP_G0 0x04060000 +#define GPIO_CNL_LP_GPP_G1 0x04060001 +#define GPIO_CNL_LP_GPP_G2 0x04060002 +#define GPIO_CNL_LP_GPP_G3 0x04060003 +#define GPIO_CNL_LP_GPP_G4 0x04060004 +#define GPIO_CNL_LP_GPP_G5 0x04060005 +#define GPIO_CNL_LP_GPP_G6 0x04060006 +#define GPIO_CNL_LP_GPP_G7 0x04060007 + +#define GPIO_CNL_LP_GPP_H0 0x04070000 +#define GPIO_CNL_LP_GPP_H1 0x04070001 +#define GPIO_CNL_LP_GPP_H2 0x04070002 +#define GPIO_CNL_LP_GPP_H3 0x04070003 +#define GPIO_CNL_LP_GPP_H4 0x04070004 +#define GPIO_CNL_LP_GPP_H5 0x04070005 +#define GPIO_CNL_LP_GPP_H6 0x04070006 +#define GPIO_CNL_LP_GPP_H7 0x04070007 +#define GPIO_CNL_LP_GPP_H8 0x04070008 +#define GPIO_CNL_LP_GPP_H9 0x04070009 +#define GPIO_CNL_LP_GPP_H10 0x0407000A +#define GPIO_CNL_LP_GPP_H11 0x0407000B +#define GPIO_CNL_LP_GPP_H12 0x0407000C +#define GPIO_CNL_LP_GPP_H13 0x0407000D +#define GPIO_CNL_LP_GPP_H14 0x0407000E +#define GPIO_CNL_LP_GPP_H15 0x0407000F +#define GPIO_CNL_LP_GPP_H16 0x04070010 +#define GPIO_CNL_LP_GPP_H17 0x04070011 +#define GPIO_CNL_LP_GPP_H18 0x04070012 +#define GPIO_CNL_LP_GPP_H19 0x04070013 +#define GPIO_CNL_LP_GPP_H20 0x04070014 +#define GPIO_CNL_LP_GPP_H21 0x04070015 +#define GPIO_CNL_LP_GPP_H22 0x04070016 +#define GPIO_CNL_LP_GPP_H23 0x04070017 + +#define GPIO_CNL_LP_GPD0 0x04080000 +#define GPIO_CNL_LP_GPD1 0x04080001 +#define GPIO_CNL_LP_GPD2 0x04080002 +#define GPIO_CNL_LP_GPD3 0x04080003 +#define GPIO_CNL_LP_GPD4 0x04080004 +#define GPIO_CNL_LP_GPD5 0x04080005 +#define GPIO_CNL_LP_GPD6 0x04080006 +#define GPIO_CNL_LP_GPD7 0x04080007 +#define GPIO_CNL_LP_GPD8 0x04080008 +#define GPIO_CNL_LP_GPD9 0x04080009 +#define GPIO_CNL_LP_GPD10 0x0408000A +#define GPIO_CNL_LP_GPD11 0x0408000B +#define GPIO_CNL_LP_SLP_LANB 0x0408000C +#define GPIO_CNL_LP_SLP_SUSB 0x0408000D +#define GPIO_CNL_LP_SLP_WAKEB 0x0408000E +#define GPIO_CNL_LP_SLP_DRAM_RESETB 0x0408000F + +#define GPIO_CNL_LP_VGPIO0 0x04090000 +#define GPIO_CNL_LP_VGPIO1 0x04090001 +#define GPIO_CNL_LP_VGPIO2 0x04090002 +#define GPIO_CNL_LP_VGPIO3 0x04090003 +#define GPIO_CNL_LP_VGPIO4 0x04090004 +#define GPIO_CNL_LP_VGPIO5 0x04090005 +#define GPIO_CNL_LP_VGPIO6 0x04090006 +#define GPIO_CNL_LP_VGPIO7 0x04090007 +#define GPIO_CNL_LP_VGPIO8 0x04090008 +#define GPIO_CNL_LP_VGPIO9 0x04090009 +#define GPIO_CNL_LP_VGPIO10 0x0409000A +#define GPIO_CNL_LP_VGPIO11 0x0409000B +#define GPIO_CNL_LP_VGPIO12 0x0409000C +#define GPIO_CNL_LP_VGPIO13 0x0409000D +#define GPIO_CNL_LP_VGPIO14 0x0409000E +#define GPIO_CNL_LP_VGPIO15 0x0409000F +#define GPIO_CNL_LP_VGPIO16 0x04090010 +#define GPIO_CNL_LP_VGPIO17 0x04090011 +#define GPIO_CNL_LP_VGPIO18 0x04090012 +#define GPIO_CNL_LP_VGPIO19 0x04090013 +#define GPIO_CNL_LP_VGPIO20 0x04090014 +#define GPIO_CNL_LP_VGPIO21 0x04090015 +#define GPIO_CNL_LP_VGPIO22 0x04090016 +#define GPIO_CNL_LP_VGPIO23 0x04090017 +#define GPIO_CNL_LP_VGPIO24 0x04090018 +#define GPIO_CNL_LP_VGPIO25 0x04090019 +#define GPIO_CNL_LP_VGPIO26 0x0409001A +#define GPIO_CNL_LP_VGPIO27 0x0409001B +#define GPIO_CNL_LP_VGPIO28 0x0409001C +#define GPIO_CNL_LP_VGPIO29 0x0409001D +#define GPIO_CNL_LP_VGPIO30 0x0409001E +#define GPIO_CNL_LP_VGPIO31 0x0409001F +#define GPIO_CNL_LP_VGPIO32 0x04090020 +#define GPIO_CNL_LP_VGPIO33 0x04090021 +#define GPIO_CNL_LP_VGPIO34 0x04090022 +#define GPIO_CNL_LP_VGPIO35 0x04090023 +#define GPIO_CNL_LP_VGPIO36 0x04090024 +#define GPIO_CNL_LP_VGPIO37 0x04090025 +#define GPIO_CNL_LP_VGPIO38 0x04090026 +#define GPIO_CNL_LP_VGPIO39 0x04090027 + +#define GPIO_CNL_LP_SPI0_IO_2 0x040A0000 +#define GPIO_CNL_LP_SPI0_IO_3 0x040A0001 +#define GPIO_CNL_LP_SPI0_MOSI_IO_0 0x040A0002 +#define GPIO_CNL_LP_SPI0_MOSI_IO_1 0x040A0003 +#define GPIO_CNL_LP_SPI0_TPM_CSB 0x040A0004 +#define GPIO_CNL_LP_SPI0_FLASH_0_CSB 0x040A0005 +#define GPIO_CNL_LP_SPI0_FLASH_1_CSB 0x040A0006 +#define GPIO_CNL_LP_SPI0_CLK 0x040A0007 +#define GPIO_CNL_LP_SPI0_CLK_LOOPBK 0x040A0008 + +#define GPIO_CNL_LP_HDA_BCLK 0x040B0000 +#define GPIO_CNL_LP_HDA_RSTB 0x040B0001 +#define GPIO_CNL_LP_HDA_SYNC 0x040B0002 +#define GPIO_CNL_LP_HDA_SDO 0x040B0003 +#define GPIO_CNL_LP_HDA_SDI_0 0x040B0004 +#define GPIO_CNL_LP_HDA_SDI_1 0x040B0005 +#define GPIO_CNL_LP_SSP1_SFRM 0x040B0006 +#define GPIO_CNL_LP_SSP1_TXD 0x040B0007 + +#define GPIO_CNL_LP_HDACPU_SDI 0x040C0000 +#define GPIO_CNL_LP_HDACPU_SDO 0x040C0001 +#define GPIO_CNL_LP_HDACPU_SCLK 0x040C0002 +#define GPIO_CNL_LP_PM_SYNC 0x040C0003 +#define GPIO_CNL_LP_PECI 0x040C0004 +#define GPIO_CNL_LP_CPUPWRGD 0x040C0005 +#define GPIO_CNL_LP_THRMTRIPB 0x040C0006 +#define GPIO_CNL_LP_PLTRST_CPUB 0x040C0007 +#define GPIO_CNL_LP_PM_DOWN 0x040C0008 +#define GPIO_CNL_LP_TRIGGER_IN 0x040C0009 +#define GPIO_CNL_LP_TRIGGER_OUT 0x040C000A + +#define GPIO_CNL_LP_JTAG_TDO 0x040D0000 +#define GPIO_CNL_LP_JTAGX 0x040D0001 +#define GPIO_CNL_LP_PRDYB 0x040D0002 +#define GPIO_CNL_LP_PREQB 0x040D0003 +#define GPIO_CNL_LP_CPU_TRSTB 0x040D0004 +#define GPIO_CNL_LP_JTAG_TDI 0x040D0005 +#define GPIO_CNL_LP_JTAG_TMS 0x040D0006 +#define GPIO_CNL_LP_JTAG_TCK 0x040D0007 +#define GPIO_CNL_LP_ITP_PMODE 0x040D0008 + +#define GPIO_CNL_LP_HVMOS_L_BKLTEN 0x040E0000 +#define GPIO_CNL_LP_HVMOS_L_BKLTCTL 0x040E0001 +#define GPIO_CNL_LP_HVMOS_L_VDDEN 0x040E0002 +#define GPIO_CNL_LP_HVMOS_SYS_PWROK 0x040E0003 +#define GPIO_CNL_LP_HVMOS_SYS_RESETB 0x040E0004 +#define GPIO_CNL_LP_HVMOS_MLK_RSTB 0x040E0005 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h new file mode 100644 index 0000000000..d3aad4172f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklH.h @@ -0,0 +1,241 @@ +/** @file + GPIO pins + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_SKL_H_H_ +#define _GPIO_PINS_SKL_H_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_H_GROUP_GPP_A 0x0100 +#define GPIO_SKL_H_GROUP_GPP_B 0x0101 +#define GPIO_SKL_H_GROUP_GPP_C 0x0102 +#define GPIO_SKL_H_GROUP_GPP_D 0x0103 +#define GPIO_SKL_H_GROUP_GPP_E 0x0104 +#define GPIO_SKL_H_GROUP_GPP_F 0x0105 +#define GPIO_SKL_H_GROUP_GPP_G 0x0106 +#define GPIO_SKL_H_GROUP_GPP_H 0x0107 +#define GPIO_SKL_H_GROUP_GPP_I 0x0108 +#define GPIO_SKL_H_GROUP_GPD 0x0109 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_H_GPP_A0 0x01000000 +#define GPIO_SKL_H_GPP_A1 0x01000001 +#define GPIO_SKL_H_GPP_A2 0x01000002 +#define GPIO_SKL_H_GPP_A3 0x01000003 +#define GPIO_SKL_H_GPP_A4 0x01000004 +#define GPIO_SKL_H_GPP_A5 0x01000005 +#define GPIO_SKL_H_GPP_A6 0x01000006 +#define GPIO_SKL_H_GPP_A7 0x01000007 +#define GPIO_SKL_H_GPP_A8 0x01000008 +#define GPIO_SKL_H_GPP_A9 0x01000009 +#define GPIO_SKL_H_GPP_A10 0x0100000A +#define GPIO_SKL_H_GPP_A11 0x0100000B +#define GPIO_SKL_H_GPP_A12 0x0100000C +#define GPIO_SKL_H_GPP_A13 0x0100000D +#define GPIO_SKL_H_GPP_A14 0x0100000E +#define GPIO_SKL_H_GPP_A15 0x0100000F +#define GPIO_SKL_H_GPP_A16 0x01000010 +#define GPIO_SKL_H_GPP_A17 0x01000011 +#define GPIO_SKL_H_GPP_A18 0x01000012 +#define GPIO_SKL_H_GPP_A19 0x01000013 +#define GPIO_SKL_H_GPP_A20 0x01000014 +#define GPIO_SKL_H_GPP_A21 0x01000015 +#define GPIO_SKL_H_GPP_A22 0x01000016 +#define GPIO_SKL_H_GPP_A23 0x01000017 +#define GPIO_SKL_H_GPP_B0 0x01010000 +#define GPIO_SKL_H_GPP_B1 0x01010001 +#define GPIO_SKL_H_GPP_B2 0x01010002 +#define GPIO_SKL_H_GPP_B3 0x01010003 +#define GPIO_SKL_H_GPP_B4 0x01010004 +#define GPIO_SKL_H_GPP_B5 0x01010005 +#define GPIO_SKL_H_GPP_B6 0x01010006 +#define GPIO_SKL_H_GPP_B7 0x01010007 +#define GPIO_SKL_H_GPP_B8 0x01010008 +#define GPIO_SKL_H_GPP_B9 0x01010009 +#define GPIO_SKL_H_GPP_B10 0x0101000A +#define GPIO_SKL_H_GPP_B11 0x0101000B +#define GPIO_SKL_H_GPP_B12 0x0101000C +#define GPIO_SKL_H_GPP_B13 0x0101000D +#define GPIO_SKL_H_GPP_B14 0x0101000E +#define GPIO_SKL_H_GPP_B15 0x0101000F +#define GPIO_SKL_H_GPP_B16 0x01010010 +#define GPIO_SKL_H_GPP_B17 0x01010011 +#define GPIO_SKL_H_GPP_B18 0x01010012 +#define GPIO_SKL_H_GPP_B19 0x01010013 +#define GPIO_SKL_H_GPP_B20 0x01010014 +#define GPIO_SKL_H_GPP_B21 0x01010015 +#define GPIO_SKL_H_GPP_B22 0x01010016 +#define GPIO_SKL_H_GPP_B23 0x01010017 +#define GPIO_SKL_H_GPP_C0 0x01020000 +#define GPIO_SKL_H_GPP_C1 0x01020001 +#define GPIO_SKL_H_GPP_C2 0x01020002 +#define GPIO_SKL_H_GPP_C3 0x01020003 +#define GPIO_SKL_H_GPP_C4 0x01020004 +#define GPIO_SKL_H_GPP_C5 0x01020005 +#define GPIO_SKL_H_GPP_C6 0x01020006 +#define GPIO_SKL_H_GPP_C7 0x01020007 +#define GPIO_SKL_H_GPP_C8 0x01020008 +#define GPIO_SKL_H_GPP_C9 0x01020009 +#define GPIO_SKL_H_GPP_C10 0x0102000A +#define GPIO_SKL_H_GPP_C11 0x0102000B +#define GPIO_SKL_H_GPP_C12 0x0102000C +#define GPIO_SKL_H_GPP_C13 0x0102000D +#define GPIO_SKL_H_GPP_C14 0x0102000E +#define GPIO_SKL_H_GPP_C15 0x0102000F +#define GPIO_SKL_H_GPP_C16 0x01020010 +#define GPIO_SKL_H_GPP_C17 0x01020011 +#define GPIO_SKL_H_GPP_C18 0x01020012 +#define GPIO_SKL_H_GPP_C19 0x01020013 +#define GPIO_SKL_H_GPP_C20 0x01020014 +#define GPIO_SKL_H_GPP_C21 0x01020015 +#define GPIO_SKL_H_GPP_C22 0x01020016 +#define GPIO_SKL_H_GPP_C23 0x01020017 +#define GPIO_SKL_H_GPP_D0 0x01030000 +#define GPIO_SKL_H_GPP_D1 0x01030001 +#define GPIO_SKL_H_GPP_D2 0x01030002 +#define GPIO_SKL_H_GPP_D3 0x01030003 +#define GPIO_SKL_H_GPP_D4 0x01030004 +#define GPIO_SKL_H_GPP_D5 0x01030005 +#define GPIO_SKL_H_GPP_D6 0x01030006 +#define GPIO_SKL_H_GPP_D7 0x01030007 +#define GPIO_SKL_H_GPP_D8 0x01030008 +#define GPIO_SKL_H_GPP_D9 0x01030009 +#define GPIO_SKL_H_GPP_D10 0x0103000A +#define GPIO_SKL_H_GPP_D11 0x0103000B +#define GPIO_SKL_H_GPP_D12 0x0103000C +#define GPIO_SKL_H_GPP_D13 0x0103000D +#define GPIO_SKL_H_GPP_D14 0x0103000E +#define GPIO_SKL_H_GPP_D15 0x0103000F +#define GPIO_SKL_H_GPP_D16 0x01030010 +#define GPIO_SKL_H_GPP_D17 0x01030011 +#define GPIO_SKL_H_GPP_D18 0x01030012 +#define GPIO_SKL_H_GPP_D19 0x01030013 +#define GPIO_SKL_H_GPP_D20 0x01030014 +#define GPIO_SKL_H_GPP_D21 0x01030015 +#define GPIO_SKL_H_GPP_D22 0x01030016 +#define GPIO_SKL_H_GPP_D23 0x01030017 +#define GPIO_SKL_H_GPP_E0 0x01040000 +#define GPIO_SKL_H_GPP_E1 0x01040001 +#define GPIO_SKL_H_GPP_E2 0x01040002 +#define GPIO_SKL_H_GPP_E3 0x01040003 +#define GPIO_SKL_H_GPP_E4 0x01040004 +#define GPIO_SKL_H_GPP_E5 0x01040005 +#define GPIO_SKL_H_GPP_E6 0x01040006 +#define GPIO_SKL_H_GPP_E7 0x01040007 +#define GPIO_SKL_H_GPP_E8 0x01040008 +#define GPIO_SKL_H_GPP_E9 0x01040009 +#define GPIO_SKL_H_GPP_E10 0x0104000A +#define GPIO_SKL_H_GPP_E11 0x0104000B +#define GPIO_SKL_H_GPP_E12 0x0104000C +#define GPIO_SKL_H_GPP_F0 0x01050000 +#define GPIO_SKL_H_GPP_F1 0x01050001 +#define GPIO_SKL_H_GPP_F2 0x01050002 +#define GPIO_SKL_H_GPP_F3 0x01050003 +#define GPIO_SKL_H_GPP_F4 0x01050004 +#define GPIO_SKL_H_GPP_F5 0x01050005 +#define GPIO_SKL_H_GPP_F6 0x01050006 +#define GPIO_SKL_H_GPP_F7 0x01050007 +#define GPIO_SKL_H_GPP_F8 0x01050008 +#define GPIO_SKL_H_GPP_F9 0x01050009 +#define GPIO_SKL_H_GPP_F10 0x0105000A +#define GPIO_SKL_H_GPP_F11 0x0105000B +#define GPIO_SKL_H_GPP_F12 0x0105000C +#define GPIO_SKL_H_GPP_F13 0x0105000D +#define GPIO_SKL_H_GPP_F14 0x0105000E +#define GPIO_SKL_H_GPP_F15 0x0105000F +#define GPIO_SKL_H_GPP_F16 0x01050010 +#define GPIO_SKL_H_GPP_F17 0x01050011 +#define GPIO_SKL_H_GPP_F18 0x01050012 +#define GPIO_SKL_H_GPP_F19 0x01050013 +#define GPIO_SKL_H_GPP_F20 0x01050014 +#define GPIO_SKL_H_GPP_F21 0x01050015 +#define GPIO_SKL_H_GPP_F22 0x01050016 +#define GPIO_SKL_H_GPP_F23 0x01050017 +#define GPIO_SKL_H_GPP_G0 0x01060000 +#define GPIO_SKL_H_GPP_G1 0x01060001 +#define GPIO_SKL_H_GPP_G2 0x01060002 +#define GPIO_SKL_H_GPP_G3 0x01060003 +#define GPIO_SKL_H_GPP_G4 0x01060004 +#define GPIO_SKL_H_GPP_G5 0x01060005 +#define GPIO_SKL_H_GPP_G6 0x01060006 +#define GPIO_SKL_H_GPP_G7 0x01060007 +#define GPIO_SKL_H_GPP_G8 0x01060008 +#define GPIO_SKL_H_GPP_G9 0x01060009 +#define GPIO_SKL_H_GPP_G10 0x0106000A +#define GPIO_SKL_H_GPP_G11 0x0106000B +#define GPIO_SKL_H_GPP_G12 0x0106000C +#define GPIO_SKL_H_GPP_G13 0x0106000D +#define GPIO_SKL_H_GPP_G14 0x0106000E +#define GPIO_SKL_H_GPP_G15 0x0106000F +#define GPIO_SKL_H_GPP_G16 0x01060010 +#define GPIO_SKL_H_GPP_G17 0x01060011 +#define GPIO_SKL_H_GPP_G18 0x01060012 +#define GPIO_SKL_H_GPP_G19 0x01060013 +#define GPIO_SKL_H_GPP_G20 0x01060014 +#define GPIO_SKL_H_GPP_G21 0x01060015 +#define GPIO_SKL_H_GPP_G22 0x01060016 +#define GPIO_SKL_H_GPP_G23 0x01060017 +#define GPIO_SKL_H_GPP_H0 0x01070000 +#define GPIO_SKL_H_GPP_H1 0x01070001 +#define GPIO_SKL_H_GPP_H2 0x01070002 +#define GPIO_SKL_H_GPP_H3 0x01070003 +#define GPIO_SKL_H_GPP_H4 0x01070004 +#define GPIO_SKL_H_GPP_H5 0x01070005 +#define GPIO_SKL_H_GPP_H6 0x01070006 +#define GPIO_SKL_H_GPP_H7 0x01070007 +#define GPIO_SKL_H_GPP_H8 0x01070008 +#define GPIO_SKL_H_GPP_H9 0x01070009 +#define GPIO_SKL_H_GPP_H10 0x0107000A +#define GPIO_SKL_H_GPP_H11 0x0107000B +#define GPIO_SKL_H_GPP_H12 0x0107000C +#define GPIO_SKL_H_GPP_H13 0x0107000D +#define GPIO_SKL_H_GPP_H14 0x0107000E +#define GPIO_SKL_H_GPP_H15 0x0107000F +#define GPIO_SKL_H_GPP_H16 0x01070010 +#define GPIO_SKL_H_GPP_H17 0x01070011 +#define GPIO_SKL_H_GPP_H18 0x01070012 +#define GPIO_SKL_H_GPP_H19 0x01070013 +#define GPIO_SKL_H_GPP_H20 0x01070014 +#define GPIO_SKL_H_GPP_H21 0x01070015 +#define GPIO_SKL_H_GPP_H22 0x01070016 +#define GPIO_SKL_H_GPP_H23 0x01070017 +#define GPIO_SKL_H_GPP_I0 0x01080000 +#define GPIO_SKL_H_GPP_I1 0x01080001 +#define GPIO_SKL_H_GPP_I2 0x01080002 +#define GPIO_SKL_H_GPP_I3 0x01080003 +#define GPIO_SKL_H_GPP_I4 0x01080004 +#define GPIO_SKL_H_GPP_I5 0x01080005 +#define GPIO_SKL_H_GPP_I6 0x01080006 +#define GPIO_SKL_H_GPP_I7 0x01080007 +#define GPIO_SKL_H_GPP_I8 0x01080008 +#define GPIO_SKL_H_GPP_I9 0x01080009 +#define GPIO_SKL_H_GPP_I10 0x0108000A +#define GPIO_SKL_H_GPD0 0x01090000 +#define GPIO_SKL_H_GPD1 0x01090001 +#define GPIO_SKL_H_GPD2 0x01090002 +#define GPIO_SKL_H_GPD3 0x01090003 +#define GPIO_SKL_H_GPD4 0x01090004 +#define GPIO_SKL_H_GPD5 0x01090005 +#define GPIO_SKL_H_GPD6 0x01090006 +#define GPIO_SKL_H_GPD7 0x01090007 +#define GPIO_SKL_H_GPD8 0x01090008 +#define GPIO_SKL_H_GPD9 0x01090009 +#define GPIO_SKL_H_GPD10 0x0109000A +#define GPIO_SKL_H_GPD11 0x0109000B + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h= b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h new file mode 100644 index 0000000000..8d430afd14 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/GpioPinsSklLp.h @@ -0,0 +1,200 @@ +/** @file + GPIO pins + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PINS_SKL_LP_H_ +#define _GPIO_PINS_SKL_LP_H_ +/// +/// This header file should be used together with +/// PCH GPIO lib in C and ASL. All defines used +/// must match both ASL/C syntax +/// + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioGroup as argument +/// +#define GPIO_SKL_LP_GROUP_GPP_A 0x0200 +#define GPIO_SKL_LP_GROUP_GPP_B 0x0201 +#define GPIO_SKL_LP_GROUP_GPP_C 0x0202 +#define GPIO_SKL_LP_GROUP_GPP_D 0x0203 +#define GPIO_SKL_LP_GROUP_GPP_E 0x0204 +#define GPIO_SKL_LP_GROUP_GPP_F 0x0205 +#define GPIO_SKL_LP_GROUP_GPP_G 0x0206 +#define GPIO_SKL_LP_GROUP_GPD 0x0207 + +/// +/// Use below for functions from PCH GPIO Lib which +/// require GpioPad as argument. Encoding used here +/// has all information required by library functions +/// +#define GPIO_SKL_LP_GPP_A0 0x02000000 +#define GPIO_SKL_LP_GPP_A1 0x02000001 +#define GPIO_SKL_LP_GPP_A2 0x02000002 +#define GPIO_SKL_LP_GPP_A3 0x02000003 +#define GPIO_SKL_LP_GPP_A4 0x02000004 +#define GPIO_SKL_LP_GPP_A5 0x02000005 +#define GPIO_SKL_LP_GPP_A6 0x02000006 +#define GPIO_SKL_LP_GPP_A7 0x02000007 +#define GPIO_SKL_LP_GPP_A8 0x02000008 +#define GPIO_SKL_LP_GPP_A9 0x02000009 +#define GPIO_SKL_LP_GPP_A10 0x0200000A +#define GPIO_SKL_LP_GPP_A11 0x0200000B +#define GPIO_SKL_LP_GPP_A12 0x0200000C +#define GPIO_SKL_LP_GPP_A13 0x0200000D +#define GPIO_SKL_LP_GPP_A14 0x0200000E +#define GPIO_SKL_LP_GPP_A15 0x0200000F +#define GPIO_SKL_LP_GPP_A16 0x02000010 +#define GPIO_SKL_LP_GPP_A17 0x02000011 +#define GPIO_SKL_LP_GPP_A18 0x02000012 +#define GPIO_SKL_LP_GPP_A19 0x02000013 +#define GPIO_SKL_LP_GPP_A20 0x02000014 +#define GPIO_SKL_LP_GPP_A21 0x02000015 +#define GPIO_SKL_LP_GPP_A22 0x02000016 +#define GPIO_SKL_LP_GPP_A23 0x02000017 +#define GPIO_SKL_LP_GPP_B0 0x02010000 +#define GPIO_SKL_LP_GPP_B1 0x02010001 +#define GPIO_SKL_LP_GPP_B2 0x02010002 +#define GPIO_SKL_LP_GPP_B3 0x02010003 +#define GPIO_SKL_LP_GPP_B4 0x02010004 +#define GPIO_SKL_LP_GPP_B5 0x02010005 +#define GPIO_SKL_LP_GPP_B6 0x02010006 +#define GPIO_SKL_LP_GPP_B7 0x02010007 +#define GPIO_SKL_LP_GPP_B8 0x02010008 +#define GPIO_SKL_LP_GPP_B9 0x02010009 +#define GPIO_SKL_LP_GPP_B10 0x0201000A +#define GPIO_SKL_LP_GPP_B11 0x0201000B +#define GPIO_SKL_LP_GPP_B12 0x0201000C +#define GPIO_SKL_LP_GPP_B13 0x0201000D +#define GPIO_SKL_LP_GPP_B14 0x0201000E +#define GPIO_SKL_LP_GPP_B15 0x0201000F +#define GPIO_SKL_LP_GPP_B16 0x02010010 +#define GPIO_SKL_LP_GPP_B17 0x02010011 +#define GPIO_SKL_LP_GPP_B18 0x02010012 +#define GPIO_SKL_LP_GPP_B19 0x02010013 +#define GPIO_SKL_LP_GPP_B20 0x02010014 +#define GPIO_SKL_LP_GPP_B21 0x02010015 +#define GPIO_SKL_LP_GPP_B22 0x02010016 +#define GPIO_SKL_LP_GPP_B23 0x02010017 +#define GPIO_SKL_LP_GPP_C0 0x02020000 +#define GPIO_SKL_LP_GPP_C1 0x02020001 +#define GPIO_SKL_LP_GPP_C2 0x02020002 +#define GPIO_SKL_LP_GPP_C3 0x02020003 +#define GPIO_SKL_LP_GPP_C4 0x02020004 +#define GPIO_SKL_LP_GPP_C5 0x02020005 +#define GPIO_SKL_LP_GPP_C6 0x02020006 +#define GPIO_SKL_LP_GPP_C7 0x02020007 +#define GPIO_SKL_LP_GPP_C8 0x02020008 +#define GPIO_SKL_LP_GPP_C9 0x02020009 +#define GPIO_SKL_LP_GPP_C10 0x0202000A +#define GPIO_SKL_LP_GPP_C11 0x0202000B +#define GPIO_SKL_LP_GPP_C12 0x0202000C +#define GPIO_SKL_LP_GPP_C13 0x0202000D +#define GPIO_SKL_LP_GPP_C14 0x0202000E +#define GPIO_SKL_LP_GPP_C15 0x0202000F +#define GPIO_SKL_LP_GPP_C16 0x02020010 +#define GPIO_SKL_LP_GPP_C17 0x02020011 +#define GPIO_SKL_LP_GPP_C18 0x02020012 +#define GPIO_SKL_LP_GPP_C19 0x02020013 +#define GPIO_SKL_LP_GPP_C20 0x02020014 +#define GPIO_SKL_LP_GPP_C21 0x02020015 +#define GPIO_SKL_LP_GPP_C22 0x02020016 +#define GPIO_SKL_LP_GPP_C23 0x02020017 +#define GPIO_SKL_LP_GPP_D0 0x02030000 +#define GPIO_SKL_LP_GPP_D1 0x02030001 +#define GPIO_SKL_LP_GPP_D2 0x02030002 +#define GPIO_SKL_LP_GPP_D3 0x02030003 +#define GPIO_SKL_LP_GPP_D4 0x02030004 +#define GPIO_SKL_LP_GPP_D5 0x02030005 +#define GPIO_SKL_LP_GPP_D6 0x02030006 +#define GPIO_SKL_LP_GPP_D7 0x02030007 +#define GPIO_SKL_LP_GPP_D8 0x02030008 +#define GPIO_SKL_LP_GPP_D9 0x02030009 +#define GPIO_SKL_LP_GPP_D10 0x0203000A +#define GPIO_SKL_LP_GPP_D11 0x0203000B +#define GPIO_SKL_LP_GPP_D12 0x0203000C +#define GPIO_SKL_LP_GPP_D13 0x0203000D +#define GPIO_SKL_LP_GPP_D14 0x0203000E +#define GPIO_SKL_LP_GPP_D15 0x0203000F +#define GPIO_SKL_LP_GPP_D16 0x02030010 +#define GPIO_SKL_LP_GPP_D17 0x02030011 +#define GPIO_SKL_LP_GPP_D18 0x02030012 +#define GPIO_SKL_LP_GPP_D19 0x02030013 +#define GPIO_SKL_LP_GPP_D20 0x02030014 +#define GPIO_SKL_LP_GPP_D21 0x02030015 +#define GPIO_SKL_LP_GPP_D22 0x02030016 +#define GPIO_SKL_LP_GPP_D23 0x02030017 +#define GPIO_SKL_LP_GPP_E0 0x02040000 +#define GPIO_SKL_LP_GPP_E1 0x02040001 +#define GPIO_SKL_LP_GPP_E2 0x02040002 +#define GPIO_SKL_LP_GPP_E3 0x02040003 +#define GPIO_SKL_LP_GPP_E4 0x02040004 +#define GPIO_SKL_LP_GPP_E5 0x02040005 +#define GPIO_SKL_LP_GPP_E6 0x02040006 +#define GPIO_SKL_LP_GPP_E7 0x02040007 +#define GPIO_SKL_LP_GPP_E8 0x02040008 +#define GPIO_SKL_LP_GPP_E9 0x02040009 +#define GPIO_SKL_LP_GPP_E10 0x0204000A +#define GPIO_SKL_LP_GPP_E11 0x0204000B +#define GPIO_SKL_LP_GPP_E12 0x0204000C +#define GPIO_SKL_LP_GPP_E13 0x0204000D +#define GPIO_SKL_LP_GPP_E14 0x0204000E +#define GPIO_SKL_LP_GPP_E15 0x0204000F +#define GPIO_SKL_LP_GPP_E16 0x02040010 +#define GPIO_SKL_LP_GPP_E17 0x02040011 +#define GPIO_SKL_LP_GPP_E18 0x02040012 +#define GPIO_SKL_LP_GPP_E19 0x02040013 +#define GPIO_SKL_LP_GPP_E20 0x02040014 +#define GPIO_SKL_LP_GPP_E21 0x02040015 +#define GPIO_SKL_LP_GPP_E22 0x02040016 +#define GPIO_SKL_LP_GPP_E23 0x02040017 +#define GPIO_SKL_LP_GPP_F0 0x02050000 +#define GPIO_SKL_LP_GPP_F1 0x02050001 +#define GPIO_SKL_LP_GPP_F2 0x02050002 +#define GPIO_SKL_LP_GPP_F3 0x02050003 +#define GPIO_SKL_LP_GPP_F4 0x02050004 +#define GPIO_SKL_LP_GPP_F5 0x02050005 +#define GPIO_SKL_LP_GPP_F6 0x02050006 +#define GPIO_SKL_LP_GPP_F7 0x02050007 +#define GPIO_SKL_LP_GPP_F8 0x02050008 +#define GPIO_SKL_LP_GPP_F9 0x02050009 +#define GPIO_SKL_LP_GPP_F10 0x0205000A +#define GPIO_SKL_LP_GPP_F11 0x0205000B +#define GPIO_SKL_LP_GPP_F12 0x0205000C +#define GPIO_SKL_LP_GPP_F13 0x0205000D +#define GPIO_SKL_LP_GPP_F14 0x0205000E +#define GPIO_SKL_LP_GPP_F15 0x0205000F +#define GPIO_SKL_LP_GPP_F16 0x02050010 +#define GPIO_SKL_LP_GPP_F17 0x02050011 +#define GPIO_SKL_LP_GPP_F18 0x02050012 +#define GPIO_SKL_LP_GPP_F19 0x02050013 +#define GPIO_SKL_LP_GPP_F20 0x02050014 +#define GPIO_SKL_LP_GPP_F21 0x02050015 +#define GPIO_SKL_LP_GPP_F22 0x02050016 +#define GPIO_SKL_LP_GPP_F23 0x02050017 +#define GPIO_SKL_LP_GPP_G0 0x02060000 +#define GPIO_SKL_LP_GPP_G1 0x02060001 +#define GPIO_SKL_LP_GPP_G2 0x02060002 +#define GPIO_SKL_LP_GPP_G3 0x02060003 +#define GPIO_SKL_LP_GPP_G4 0x02060004 +#define GPIO_SKL_LP_GPP_G5 0x02060005 +#define GPIO_SKL_LP_GPP_G6 0x02060006 +#define GPIO_SKL_LP_GPP_G7 0x02060007 +#define GPIO_SKL_LP_GPD0 0x02070000 +#define GPIO_SKL_LP_GPD1 0x02070001 +#define GPIO_SKL_LP_GPD2 0x02070002 +#define GPIO_SKL_LP_GPD3 0x02070003 +#define GPIO_SKL_LP_GPD4 0x02070004 +#define GPIO_SKL_LP_GPD5 0x02070005 +#define GPIO_SKL_LP_GPD6 0x02070006 +#define GPIO_SKL_LP_GPD7 0x02070007 +#define GPIO_SKL_LP_GPD8 0x02070008 +#define GPIO_SKL_LP_GPD9 0x02070009 +#define GPIO_SKL_LP_GPD10 0x0207000A +#define GPIO_SKL_LP_GPD11 0x0207000B + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h b/S= ilicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h new file mode 100644 index 0000000000..6730b3baf9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchAccess.h @@ -0,0 +1,54 @@ +/** @file + Macros that simplify accessing PCH devices's PCI registers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_ACCESS_H_ +#define _PCH_ACCESS_H_ + +#include "PchLimits.h" +#include "PchReservedResources.h" + +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_SECOND +#define STALL_ONE_SECOND 1000000 +#endif + +// +// Include device register definitions +// +#include "PcieRegs.h" +#include "Register/PchRegs.h" +#include "Register/PchRegsPcr.h" +#include "Register/PchRegsP2sb.h" +#include "Register/PchRegsHda.h" +#include "Register/PchRegsHsio.h" +#include "Register/PchRegsLan.h" +#include "Register/PchRegsLpc.h" +#include "Register/PchRegsPmc.h" +#include "Register/PchRegsPcie.h" +#include "Register/PchRegsSata.h" +#include "Register/PchRegsSmbus.h" +#include "Register/PchRegsSpi.h" +#include +#include "Register/PchRegsGpio.h" +#include "Register/PchRegsThermalCnl.h" +#include "Register/PchRegsGpioCnl.h" +#include "Register/PchRegsSerialIoCnl.h" +#include "Register/PchRegsSerialIo.h" +#include "Register/PchRegsTraceHub.h" +#include "Register/PchRegsScsCnl.h" +#include "Register/PchRegsIsh.h" +#include "Register/PchRegsDmi.h" +#include "Register/PchRegsItss.h" +#include "Register/PchRegsPsth.h" +#include "Register/PchRegsFia.h" +#include "Register/PchRegsDci.h" + +#endif + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h b/Sili= con/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h new file mode 100644 index 0000000000..3b8e5147db --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchHda.h @@ -0,0 +1,38 @@ +/** @file + Header file for HD Audio configuration. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_H_ +#define _PCH_HDA_H_ + + +enum PCH_HDAUDIO_DMIC_TYPE { + PchHdaDmicDisabled =3D 0, + PchHdaDmic2chArray =3D 1, + PchHdaDmic4chArray =3D 2, + PchHdaDmic1chArray =3D 3 +}; + +typedef enum { + PchHdaLinkFreq6MHz =3D 0, + PchHdaLinkFreq12MHz =3D 1, + PchHdaLinkFreq24MHz =3D 2, + PchHdaLinkFreq48MHz =3D 3, + PchHdaLinkFreq96MHz =3D 4, + PchHdaLinkFreqInvalid +} PCH_HDAUDIO_LINK_FREQUENCY; + +typedef enum { + PchHdaIDispMode2T =3D 0, + PchHdaIDispMode1T =3D 1, + PchHdaIDispMode4T =3D 2, + PchHdaIDispMode8T =3D 3, + PchHdaIDispMode16T =3D 4, + PchHdaIDispTModeInvalid +} PCH_HDAUDIO_IDISP_TMODE; + +#endif // _PCH_HDA_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h b/= Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h new file mode 100644 index 0000000000..743dd84b2b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchInfoHob.h @@ -0,0 +1,80 @@ +/** @file + This file contains definitions of PCH Info HOB. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_INFO_HOB_H_ +#define _PCH_INFO_HOB_H_ + +extern EFI_GUID gPchInfoHobGuid; + +#define PCH_INFO_HOB_REVISION 2 + +#pragma pack (push,1) +/** + This structure is used to provide the information of PCH controller. + + Revision 1: + - Initial version. + Revision 2: + - Add CridSupport, CridOrgRid, and CridNewRid. + Revision 3: + - Added LaneReversal Field +**/ +typedef struct { + /** + This member specifies the revision of the PCH Info HOB. This field is = used + to indicate backwards compatible changes to the protocol. Platform cod= e that + consumes this protocol must read the correct revision value to correct= ly interpret + the content of the protocol fields. + **/ + UINT8 Revision; + UINT8 PcieControllerCfg[6]; + + /** + GbE over PCIe port number when GbE is enabled + >0 - Root port number (1-based) + 0 - GbE over PCIe disabled + This information needs to be passed through HOB as FIA registers + are not accessible with POSTBOOT_SAI + **/ + UINT8 GbePciePortNumber; + UINT32 PciePortFuses; + /** + Bit map for PCIe Root Port Lane setting. If bit is set it means that + corresponding Root Port has its lane enabled. + BIT0 - RP0, BIT1 - RP1, ... + This information needs to be passed through HOB as FIA registers + are not accessible with POSTBOOT_SAI + **/ + UINT32 PciePortLaneEnabled; + /** + Publish Hpet BDF and IoApic BDF information for VTD. + **/ + UINT32 HpetBusNum : 8; + UINT32 HpetDevNum : 5; + UINT32 HpetFuncNum : 3; + UINT32 IoApicBusNum : 8; + UINT32 IoApicDevNum : 5; + UINT32 IoApicFuncNum : 3; + /** + Publish the CRID information. + **/ + UINT32 CridOrgRid : 8; + UINT32 CridNewRid : 8; + UINT32 CridSupport : 1; + UINT32 Rsvdbits : 15; + /** + This member specifies if lane reversal is enabled on the specific + Pcie Root port controller. + **/ + UINT8 PcieControllerLaneReversal[6]; +} PCH_INFO_HOB; + +#pragma pack (pop) + +#endif // _PCH_INFO_HOB_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h b/S= ilicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h new file mode 100644 index 0000000000..929f9f02d4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchLimits.h @@ -0,0 +1,53 @@ +/** @file + Build time limits of PCH resources. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_LIMITS_H_ +#define _PCH_LIMITS_H_ + +// +// PCIe limits +// +#define PCH_MAX_PCIE_ROOT_PORTS 24 +#define PCH_MAX_PCIE_CONTROLLERS 6 + +// +// PCIe clocks limits +// +#define PCH_MAX_PCIE_CLOCKS 16 +// +// RST PCIe Storage Cycle Router limits +// +#define PCH_MAX_RST_PCIE_STORAGE_CR 3 + +// +// SATA limits +// +#define PCH_MAX_SATA_CONTROLLERS 3 +#define PCH_MAX_SATA_PORTS 8 + +// +// USB limits +// +#define PCH_MAX_USB2_PORTS 16 +#define PCH_MAX_USB3_PORTS 10 + +// +// SerialIo limits +// +#define PCH_MAX_SERIALIO_CONTROLLERS 12 +#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 6 +#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 3 +#define PCH_MAX_SERIALIO_UART_CONTROLLERS 3 + +// +// Number of eSPI slaves +// +#define PCH_MAX_ESPI_SLAVES 2 + +#endif // _PCH_LIMITS_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageD= etectHob.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageD= etectHob.h new file mode 100644 index 0000000000..1097e58332 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPcieStorageDetectHo= b.h @@ -0,0 +1,47 @@ +/** @file + Definitions required to create PcieStorageInfoHob + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIE_STORAGE_DETECT_HOB_ +#define _PCH_PCIE_STORAGE_DETECT_HOB_ + +#include "PchLimits.h" + +#define PCIE_STORAGE_INFO_HOB_REVISION 1 + +extern EFI_GUID gPchPcieStorageDetectHobGuid; + +typedef enum { + RstLinkWidthX1 =3D 1, + RstLinkWidthX2 =3D 2, + RstLinkWidthX4 =3D 4 +} RST_LINK_WIDTH; + +// +// Stores information about connected PCIe storage devices used later by = BIOS setup and RST remapping +// +#pragma pack(1) +typedef struct { + UINT8 Revision; + + // + // Stores the number of root ports occupied by a connected storage devic= e, values from RST_LINK_WIDTH are supported + // + UINT8 PcieStorageLinkWidth[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // Programming interface value for a given device, 0x02 - NVMe or RAID, = 0x1 - AHCI storage, 0x0 - no device connected + // + UINT8 PcieStorageProgrammingInterface[PCH_MAX_PCIE_ROOT_PORTS]; + + // + // Stores information about cycle router number under a given PCIe contr= oller + // + UINT8 RstCycleRouterMap[PCH_MAX_PCIE_CONTROLLERS]; +} PCIE_STORAGE_INFO_HOB; +#pragma pack() +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h new file mode 100644 index 0000000000..213ca91d2d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPolicyCommon.h @@ -0,0 +1,47 @@ +/** @file + PCH configuration based on PCH policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_POLICY_COMMON_H_ +#define _PCH_POLICY_COMMON_H_ + +#include +#include + +#include "PchLimits.h" +#include "ConfigBlock/PchGeneralConfig.h" +#include "ConfigBlock/PcieRpConfig.h" +#include "ConfigBlock/SataConfig.h" +#include "ConfigBlock/IoApicConfig.h" +#include "ConfigBlock/DmiConfig.h" +#include "ConfigBlock/FlashProtectionConfig.h" +#include "ConfigBlock/HdAudioConfig.h" +#include "ConfigBlock/InterruptConfig.h" +#include "ConfigBlock/IshConfig.h" +#include "ConfigBlock/LanConfig.h" +#include "ConfigBlock/LockDownConfig.h" +#include "ConfigBlock/P2sbConfig.h" +#include "ConfigBlock/PmConfig.h" +#include "ConfigBlock/ScsConfig.h" +#include "ConfigBlock/SerialIoConfig.h" +#include "ConfigBlock/SerialIrqConfig.h" +#include "ConfigBlock/ThermalConfig.h" +#include "ConfigBlock/EspiConfig.h" +#include "ConfigBlock/CnviConfig.h" + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + + +#endif // _PCH_POLICY_COMMON_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicy= Common.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCo= mmon.h new file mode 100644 index 0000000000..37b2301770 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h @@ -0,0 +1,59 @@ +/** @file + PCH configuration based on PCH policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PREMEM_POLICY_COMMON_H_ +#define _PCH_PREMEM_POLICY_COMMON_H_ + +#include + +#include "PchLimits.h" +#include "ConfigBlock/PchGeneralConfig.h" +#include "ConfigBlock/DciConfig.h" +#include "ConfigBlock/WatchDogConfig.h" +#include "ConfigBlock/PchTraceHubConfig.h" +#include "ConfigBlock/SmbusConfig.h" +#include "ConfigBlock/LpcConfig.h" +#include "ConfigBlock/HsioPcieConfig.h" +#include "ConfigBlock/HsioSataConfig.h" +#include "ConfigBlock/HsioConfig.h" + +#pragma pack (push,1) + +#ifndef FORCE_ENABLE +#define FORCE_ENABLE 1 +#endif +#ifndef FORCE_DISABLE +#define FORCE_DISABLE 2 +#endif +#ifndef PLATFORM_POR +#define PLATFORM_POR 0 +#endif + +/** + PCH Policy revision number + Any backwards compatible changes to this structure will result in an upd= ate in the revision number +**/ +#define PCH_PREMEM_POLICY_REVISION 1 + +/** + PCH Policy PPI\n + All PCH config block change history will be listed here\n\n + + - Revision 1: + - Initial version.\n +**/ +typedef struct _PCH_PREMEM_POLICY { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +} PCH_PREMEM_POLICY; + +#pragma pack (pop) + +#endif // _PCH_PREMEM_POLICY_COMMON_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedReso= urces.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResourc= es.h new file mode 100644 index 0000000000..f5106ffebb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchReservedResources.h @@ -0,0 +1,53 @@ +/** @file + PCH preserved MMIO resource definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PRESERVED_RESOURCES_H_ +#define _PCH_PRESERVED_RESOURCES_H_ + +/** + + Detailed recommended static allocation + +-----------------------------------------------------------------------= --+ + | = | + | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF = | + +-----------------------------------------------------------------------= --+ + | Size | Start | End | Usage = | + | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR = | + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = | + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = | + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = | + | 88 KB | 0xFE020000 | 0xFE035FFF | SerialIo BAR in ACPI mode = | + | 488 KB | 0xFE036000 | 0xFE0AFFFF | Unused = | + | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR = | + | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR = | + | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused = | + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR = | + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR = | + | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused = | + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = | + +-----------------------------------------------------------------------= --+ +**/ +#define PCH_PRESERVED_BASE_ADDRESS 0xFC800000 ///< Pch preserved = MMIO base address +#define PCH_PRESERVED_MMIO_SIZE 0x02000000 ///< 28MB +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO bas= e address +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO = base address +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO = base address +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB +#define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo MMIO = base address +#define PCH_SERIAL_IO_MMIO_SIZE 0x00016000 ///< 88KB +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB M= MIO base address +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE200000 ///< TraceHub FW MM= IO base address +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00200000 ///< 2MB +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp= address for misc usage, +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB + +#endif // _PCH_PRESERVED_RESOURCES_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatfor= mSpecific.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatfo= rmSpecific.h new file mode 100644 index 0000000000..8e1495d16f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/PchResetPlatformSpecif= ic.h @@ -0,0 +1,23 @@ +/** @file + PCH Reset Platform Specific definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_PLATFORM_SPECIFIC_H_ +#define _PCH_RESET_PLATFORM_SPECIFIC_H_ + +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET" +#define PCH_RESET_DATA_STRING_MAX_LENGTH (sizeof (PCH_PLATFORM_SPECIFI= C_RESET_STRING) / sizeof (UINT16)) + +extern EFI_GUID gPchGlobalResetGuid; + +typedef struct _RESET_DATA { + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH]; + EFI_GUID Guid; +} PCH_RESET_DATA; + +#endif // _PCH_RESET_PLATFORM_SPECIFIC_H_ + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45886): https://edk2.groups.io/g/devel/message/45886 Mute This Topic: https://groups.io/mt/32918178/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45884+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45884+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001013; cv=none; d=zoho.com; s=zohoarc; b=ZpmHcyfC+o3G+yP5dV+VlX62cv1ObRNE8TWoxv8x/Fhgt8WCdVHHtW1eKOSYUpXgpbLAtx4xxFrUXjiVZpSAqpt4bwMisH4I4QtBvoW9d6yWdjv68B/un2cp0/yCz7uQVKKtmgkXmhZ2jivNpe74UM+JkGxkez93hLiu3X16oEs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001013; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=SiAZh9JbaPnCHt+4zZ1bE3CHkPxCSQasSZay5OaHyzo=; b=ANpprIoiYsWUeV75iL1rsU24XU/oQZmbUsWTTVTqc+IaYWj0F8iv6arcoBE7f8gfMvm5y7+E4mz00eLoUr1PIQAAC/JsKqrzXQ5f0WeJB0kp2oLIbaXY7et5ddCfC90RXxBPjmCib770mIFKfjB2Sw3igRR3RqdhYBW9puKcLj8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45884+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156600101370910.359445705700864; Fri, 16 Aug 2019 17:16:53 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:51 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319238" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:49 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 05/37] CoffeelakeSiliconPkg/Pch: Add ConfigBlock headers Date: Fri, 16 Aug 2019 17:15:31 -0700 Message-Id: <20190817001603.30632-6-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001013; bh=9gVsezPF2YLRcLLqJGq9MMqD7fAdNg99XX+46KkvoKE=; h=Cc:Date:From:Reply-To:Subject:To; b=L+cIYQPOaJrt4Hcd2evnghLYP+8hlbhz9O7Z7bHZYkGRxX1aFUQDnRP2vKmgTmsWvys 4vsxkmXTcC9dhNcXLD9Zu/xRScK8px1zvO4Oe7HWb4v37n5mpvCR8/ySSclNnmd5SHkkA y+WwlqXbEdDWpeJVt5Bk1s3zU2PmGUr50Dk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds header files to Pch/Include/ConfigBlock. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha Reviewed-by: Nate DeSimone --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig.h = | 69 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h = | 56 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h = | 43 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig.h = | 40 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtection= Config.h | 54 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevConfig.h= | 39 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h= | 178 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h = | 57 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.= h | 58 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.= h | 66 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptConfig= .h | 58 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConfig.h = | 68 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h = | 57 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h = | 35 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.= h | 70 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h = | 34 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig.h = | 49 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfi= g.h | 71 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHubConf= ig.h | 36 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConfig.h = | 429 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h = | 311 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig.h = | 230 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h = | 63 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoConfig.= h | 96 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqConfig= .h | 43 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfig.h = | 52 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalConfig.h= | 139 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogConfig.= h | 33 ++ 28 files changed, 2534 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Cnv= iConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Cnvi= Config.h new file mode 100644 index 0000000000..35fa125ba3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/CnviConfig= .h @@ -0,0 +1,69 @@ +/** @file + CNVI policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CNVI_CONFIG_H_ +#define _CNVI_CONFIG_H_ + +#define CNVI_CONFIG_REVISION 2 +extern EFI_GUID gCnviConfigGuid; + +#pragma pack (push,1) + +/** + CNVi Mode options +**/ +typedef enum { + CnviModeDisabled =3D 0, + CnviModeAuto +} CNVI_MODE; + +/** + CNVi MfUart1 connection options +**/ +typedef enum { + CnviMfUart1Ish =3D 0, + CnviMfUart1SerialIo, + CnviBtUart1ExtPads, + CnviBtUart1NotConnected +} CNVI_MFUART1_TYPE; + + +/** + Revision 1: + - Initial version. + Revision 2: + - Remove BtInterface and BtUartType. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This option allows for automatic detection of Connectivity Solution. + Auto Detection assumes that CNVi will be enabled when available; + Disable allows for disabling CNVi. + CnviModeDisabled =3D Disabled, + CnviModeAuto =3D Auto Detection + **/ + UINT32 Mode : 1; + /** + (Test) This option configures Uart type which connects to MfUar= t1 + For production configuration ISH is the default, for tests SerialIO Ua= rt0 or external pads can be used + Use CNVI_MFUART1_TYPE enum for selection + CnviMfUart1Ish =3D MfUart1 over ISH Uart0, + CnviMfUart1SerialIo =3D MfUart1 over SerialIO Uart2, + CnviBtUart1ExtPads =3D MfUart1 over exteranl pads, + CnviBtUart1NotConnected =3D MfUart1 not connected + **/ + UINT32 MfUart1Type : 2; + UINT32 RsvdBits : 29; +} PCH_CNVI_CONFIG; + +#pragma pack (pop) + +#endif // _CNVI_CONFIG_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Dci= Config.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciCo= nfig.h new file mode 100644 index 0000000000..791546bdfe --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DciConfig.h @@ -0,0 +1,56 @@ +/** @file + Dci policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DCI_CONFIG_H_ +#define _DCI_CONFIG_H_ + +#define DCI_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gDciPreMemConfigGuid; + +#pragma pack (push,1) + +typedef enum { + ProbeTypeDisabled =3D 0x0, + ProbeTypeDciOobDbc =3D 0x1, + ProbeTypeDciOob =3D 0x2, + ProbeTypeUsb3Dbc =3D 0x3, + ProbeTypeXdp3 =3D 0x4, + ProbeTypeUsb2Dbc =3D 0x5, + ProbeTypeMax +} PLATFORM_DEBUG_CONSENT_PROBE_TYPE; + +/** + The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Con= nection Interface (DCI) + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Platform Debug Consent + As a master switch to enable platform debug capability and relevant se= ttings with specified probe type. + Note: DCI OOB (aka BSSB) uses CCA probe; [DCI OOB+DbC] and [USB2 DbC] = have the same setting. + Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE + 0:Disabled; 1:DCI OOB+DbC; 2:DCI OOB; 3:USB3 DbC; 4:XDP3/MIPI60= 5:USB2 DbC; + **/ + UINT32 PlatformDebugConsent : 3; + /** + USB3 Type-C UFP2DFP kenel / platform debug support. No change will do = nothing to UFP2DFP configuration. + When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP= (downstream-facing port) for first connection. + It must be enabled for USB3 kernel(kernel mode debug) and platform deb= ug(DFx, DMA, Trace) over UFP Type-C receptacle. + Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported setting= s. + 0:Disabled; 1:Enabled; 2:No Change + **/ + UINT32 DciUsb3TypecUfpDbg : 2; + UINT32 RsvdBits : 27; ///< Reserved bits +} PCH_DCI_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _DCI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Dmi= Config.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiCo= nfig.h new file mode 100644 index 0000000000..03f83d9bf8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/DmiConfig.h @@ -0,0 +1,43 @@ +/** @file + DMI policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DMI_CONFIG_H_ +#define _DMI_CONFIG_H_ + +#define DMI_CONFIG_REVISION 3 +extern EFI_GUID gDmiConfigGuid; + + +#pragma pack (push,1) + + +/** + The PCH_DMI_CONFIG block describes the expected configuration of the PCH= for DMI. + Revision 1: + - Initial version. + Revision 2: + - Deprecate DmiAspm and add DmiAspmCtrl + Revision 3 + - Added policy to enable/disable Central Write Buffer feature +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + @deprecated since revision 2 + **/ + + UINT32 DmiAspm : 1; + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable = DMI Power Optimizer on PCH side. + UINT32 DmiAspmCtrl : 8; ///< ASPM configuration (PCH_PCIE_= ASPM_CONTROL) on the PCH side of the DMI/OPI Link. Default is PchPcieAsp= mAutoConfig + UINT32 CwbEnable : 1; ///< 0: Disable; Central Wr= ite Buffer feature configurable and disabled by default + UINT32 Rsvdbits : 21; ///< Reserved bits +} PCH_DMI_CONFIG; + +#pragma pack (pop) + +#endif // _DMI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Esp= iConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Espi= Config.h new file mode 100644 index 0000000000..5de9b73397 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/EspiConfig= .h @@ -0,0 +1,40 @@ +/** @file + Espi policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ESPI_CONFIG_H_ +#define _ESPI_CONFIG_H_ + +#define ESPI_CONFIG_REVISION 1 +extern EFI_GUID gEspiConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to ESPI. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range + specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI). + 0: FALSE, 1: TRUE + **/ + UINT32 LgmrEnable : 1; + /** + eSPI Master and Slave BME settings. + When TRUE, then the BME bit enabled in eSPI Master and Slave. + 0: FALSE, 1: TRUE + **/ + UINT32 BmeMasterSlaveEnabled : 1; + UINT32 RsvdBits : 30; ///< Reserved bits +} PCH_ESPI_CONFIG; + +#pragma pack (pop) + +#endif // _ESPI_CONFIG_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Fla= shProtectionConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Confi= gBlock/FlashProtectionConfig.h new file mode 100644 index 0000000000..2a6c19de7e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/FlashProte= ctionConfig.h @@ -0,0 +1,54 @@ +/** @file + FlashProtection policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FLASH_PROTECTION_CONFIG_H_ +#define _FLASH_PROTECTION_CONFIG_H_ + +#define FLASH_PROTECTION_CONFIG_REVISION 1 +extern EFI_GUID gFlashProtectionConfigGuid; + +#pragma pack (push,1) + +// +// Flash Protection Range Register +// +#define PCH_FLASH_PROTECTED_RANGES 5 + +/** + The PCH provides a method for blocking writes and reads to specific rang= es + in the SPI flash when the Protected Ranges are enabled. + PROTECTED_RANGE is used to specify if flash protection are enabled, + the write protection enable bit and the read protection enable bit, + and to specify the upper limit and lower base for each register + Platform code is responsible to get the range base by PchGetSpiRegionAdd= resses routine, + and set the limit and base accordingly. +**/ +typedef struct { + UINT32 WriteProtectionEnable : 1; ///< Write or = erase is blocked by hardware. 0: Disable; 1: Enable. + UINT32 ReadProtectionEnable : 1; ///< Read is b= locked by hardware. 0: Disable; 1: Enable. + UINT32 RsvdBits : 30; ///< Reserved + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be FFFh for limit comparison + **/ + UINT16 ProtectedRangeLimit; + /** + The address of the upper limit of protection + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be 0 + **/ + UINT16 ProtectedRangeBase; +} PROTECTED_RANGE; + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; +} PCH_FLASH_PROTECTION_CONFIG; + +#pragma pack (pop) + +#endif // _FLASH_PROTECTION_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Gpi= oDevConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/G= pioDevConfig.h new file mode 100644 index 0000000000..2b32a21f54 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/GpioDevCon= fig.h @@ -0,0 +1,39 @@ +/** @file + GPIO device policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_DEV_CONFIG_H_ +#define _GPIO_DEV_CONFIG_H_ + +extern EFI_GUID gGpioDxeConfigGuid; + +#define GPIO_DXE_CONFIG_REVISION 1 + +#pragma pack (push,1) + +/** + This structure contains the DXE policies which are related to GPIO devic= e. + + Revision 1: + - Inital version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + If GPIO ACPI device is not used by OS it can be hidden. In such case + no other device exposed to the system can reference GPIO device in one + of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors. + 0: Disable; 1: Enable + **/ + UINT32 HideGpioAcpiDevice : 1; + UINT32 RsvdBits : 31; ///< Reserved bits + +} PCH_GPIO_DXE_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_GPIO_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdA= udioConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/H= dAudioConfig.h new file mode 100644 index 0000000000..a810d4f1fc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioCon= fig.h @@ -0,0 +1,178 @@ +/** @file + HDAUDIO policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _HDAUDIO_CONFIG_H_ +#define _HDAUDIO_CONFIG_H_ + +#include + +#define HDAUDIO_PREMEM_CONFIG_REVISION 1 +#define HDAUDIO_CONFIG_REVISION 2 +#define HDAUDIO_DXE_CONFIG_REVISION 2 + +extern EFI_GUID gHdAudioPreMemConfigGuid; +extern EFI_GUID gHdAudioConfigGuid; +extern EFI_GUID gHdAudioDxeConfigGuid; + +#pragma pack (push,1) + +/// +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of t= he Intel HD Audio feature. +/// + +#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((= UINT16)Vid | ((UINT16)Did << 16)) +#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((= UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16)) +#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (= VerbTable) - sizeof (PCH_HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32))) + +/// +/// Use this macro to create HDAUDIO_VERB_TABLE and populate size automati= cally +/// +#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \ +{ \ + { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }= , \ + { __VA_ARGS__ } \ +} + + +/** + Azalia verb table header + Every verb table should contain this defined header and followed by azal= ia verb commands. +**/ +typedef struct { + UINT16 VendorId; ///< Codec Vendor ID + UINT16 DeviceId; ///< Codec Device ID + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matche= s any revision. + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI. + UINT16 DataDwords; ///< Number of data DWORDs following the h= eader. +} PCH_HDA_VERB_TABLE_HEADER; + +#ifdef _MSC_VER +// +// Disable "zero-sized array in struct/union" extension warning. +// Used for neater verb table definitions. +// +#pragma warning (push) +#pragma warning (disable: 4200) +#endif +typedef struct { + PCH_HDA_VERB_TABLE_HEADER Header; + UINT32 Data[]; +} HDAUDIO_VERB_TABLE; +#ifdef _MSC_VER +#pragma warning (pop) +#endif + +/** + This structure contains the policies which are related to HD Audio devic= e (cAVS). + + Revision 1: + - Inital version. + Revision 2: + - Move DspEndpointDmic, DspEndpointBluetooth, DspEndpointI2s and DspFeat= ureMask to PCH_HDAUDIO_DXE_CONFIG +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; = 1: Enable + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: D= isable; 1: Enable + UINT32 VcType : 1; ///< Virtual Channel Type Select:= 0: VC0, 1: VC1 + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAU= DIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HD= AUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz + UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode (PCH_HDAUD= IO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T + /** + Universal Audio Architecture compliance for DSP enabled system: + 0: Not-UAA Compliant (Intel SST driver supported only), + 1: UAA Compliant (HDA Inbox driver or SST driver supported) + **/ + UINT32 DspUaaCompliance : 1; + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconn= ection, 0: Not disconnected, enumerable; 1: Disconnected SDI, not en= umerable + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake in= itiated by a codec in Sx (eg by modem codec), 0: Disable; 1: Enable + /** + Audio Link Mode configuration bitmask. + Allows to configure enablement of the following interfaces: HDA-Link, = DMIC, SSP, SoundWire. + **/ + UINT32 AudioLinkHda : 1; ///< HDA-Link enablement: 0: Disa= ble; 1: Enable. Muxed with SSP0/SSP1/SNDW1 + UINT32 AudioLinkDmic0 : 1; ///< DMIC0 link enablement: 0: Di= sable; 1: Enable. Muxed with SNDW4 + UINT32 AudioLinkDmic1 : 1; ///< DMIC1 link enablement: 0: Di= sable; 1: Enable. Muxed with SNDW3 + UINT32 AudioLinkSsp0 : 1; ///< I2S/SSP0 link enablement: 0: Disable; 1: Enable. Muxed with HDA SDI0 + UINT32 AudioLinkSsp1 : 1; ///< I2S/SSP1 link enablement: 0: Disable; 1: Enable. Muxed with HDA SDI1/SNDW2 + /** + I2S/SSP2 link enablement: 0: Disable; 1: Enable. + @note Since the I2S/SSP2 pin set contains pads which are also used for= CNVi purpose, enabling AudioLinkSsp2 + is exclusive with CNVi is present. + **/ + UINT32 AudioLinkSsp2 : 1; + UINT32 AudioLinkSndw1 : 1; ///< SoundWire1 link enablement: = 0: Disable; 1: Enable. Muxed with HDA + UINT32 AudioLinkSndw2 : 1; ///< SoundWire2 link enablement: = 0: Disable; 1: Enable. Muxed with SSP1 + UINT32 AudioLinkSndw3 : 1; ///< SoundWire3 link enablement: = 0: Disable; 1: Enable. Muxed with DMIC1 + UINT32 AudioLinkSndw4 : 1; ///< SoundWire4 link enablement: = 0: Disable; 1: Enable. Muxed with DMIC0 + /** + Soundwire Clock Buffer GPIO RCOMP adjustments based on bus topology: + 0: non-ACT - 50 Ohm driver impedance when bus topology does not= have the external AC termination; + 1: ACT - 8 Ohm driver impedance when bus topology has the external = AC termination. + **/ + UINT32 SndwBufferRcomp : 1; + UINT32 RsvdBits0 : 4; ///< Reserved bits 0 + UINT16 ResetWaitTimer; ///< (Test) The delay timer= after Azalia reset, the value is number of microseconds. Default is 600= . + UINT8 Rsvd0; ///< Reserved bytes, align to mult= iple 4 + /** + Number of the verb table entry defined in VerbTablePtr. + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE st= ructure and verb command blocks. + **/ + UINT8 VerbTableEntryNum; + /** + Pointer to a verb table array. + This pointer points to 32bits address, and is only eligible and consum= ed in post mem phase. + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE st= ructure and verb command blocks. + The prototype of this is: + HDAUDIO_VERB_TABLE **VerbTablePtr; + **/ + UINT32 VerbTablePtr; +} PCH_HDAUDIO_CONFIG; + +/** + This structure contains the premem policies which are related to HD Audi= o device (cAVS). + + Revision 1: + - Inital version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enab= lement: 0: Disable, 1: Enable + UINT32 RsvdBits : 31; ///< Reserved bits 0 +} PCH_HDAUDIO_PREMEM_CONFIG; + +/** + This structure contains the DXE policies which are related to HD Audio d= evice (cAVS). + + Revision 1: + - Inital version. + Revision 2: + - Add NhltDefaultFlow option for disabling NHLT flow from Si code. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + AudioDSP/iSST endpoints configuration exposed via NHLT ACPI table: + **/ + UINT32 DspEndpointDmic : 2; ///< DMIC Select (PCH_HDAUDIO_DMI= C_TYPE enum): 0: Disable; 1: 2ch array; 2: 4ch array; 3: 1ch array + UINT32 DspEndpointBluetooth : 1; ///< Bluetooth enablement: 0: = Disable; 1: Enable + UINT32 DspEndpointI2s : 1; ///< I2S enablement: 0: Disabl= e; 1: Enable + UINT32 NhltDefaultFlow : 1; ///< Default Nhlt flow: 0: Disabl= e, 1: Enable + UINT32 RsvdBits1 : 27; ///< Reserved bits 1 + /** + Bitmask of supported DSP features: + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT In= tel HFP; [BIT6] - BT Intel A2DP + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel W= oV, 1: Windows Voice Activation + Default is zero. + **/ + UINT32 DspFeatureMask; +} PCH_HDAUDIO_DXE_CONFIG; + +#pragma pack (pop) + +#endif // _HDAUDIO_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Hsi= oConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Hsio= Config.h new file mode 100644 index 0000000000..8c3186153c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig= .h @@ -0,0 +1,57 @@ +/** @file + HSIO policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _HSIO_CONFIG_H_ +#define _HSIO_CONFIG_H_ + +#define HSIO_PREMEM_CONFIG_REVISION 1 //@deprecated +#define HSIO_CONFIG_REVISION 1 +extern EFI_GUID gHsioPreMemConfigGuid; //@deprecated +extern EFI_GUID gHsioConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.= //@deprecated +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header //@deprec= ated + + /** + (Test) + 0- Disable, disable will prevent the HSIO version check and ChipsetInit = HECI message from being sent + 1- Enable ChipsetInit HECI message //@deprecated + **/ + UINT32 ChipsetInitMessage : 1; + /** + (Test) + 0- Disable + 1- Enable When enabled, this is used to bypass the reset after ChipsetIn= it HECI message. //@deprecated + **/ + UINT32 BypassPhySyncReset : 1; + UINT32 RsvdBits : 30; +} PCH_HSIO_PREMEM_CONFIG; + +/** + The PCH_HSIO_CONFIG block provides HSIO message related settings. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync= between BIOS and CSME + **/ + UINT32 ChipsetInitBinPtr; + /** + Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary = used to sync between BIOS and CSME + **/ + UINT32 ChipsetInitBinLen; +} PCH_HSIO_CONFIG; + +#pragma pack (pop) + +#endif // _HSIO_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Hsi= oPcieConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/= HsioPcieConfig.h new file mode 100644 index 0000000000..93131ea07a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieCo= nfig.h @@ -0,0 +1,58 @@ +/** @file + HSIO pcie policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _HSIO_PCIE_CONFIG_H_ +#define _HSIO_PCIE_CONFIG_H_ + +#define HSIO_PCIE_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gHsioPciePreMemConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane +**/ +typedef struct { + // + // HSIO Rx Eq + // Refer to the EDS for recommended values. + // Note that these setting are per-lane and not per-port + // + UINT32 HsioRxSetCtleEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 3 Set CTLE Value + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set = CTLE Value + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX O= utput Downscale Amplitude Adjustment value + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX O= utput Downscale Amplitude Adjustment value + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value ove= rride + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX O= utput Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved Bits + + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value ove= rride + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX O= utput De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setti= ng value override + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX O= utput -3.5dB Mode De-Emphasis Adjustment Setting + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setti= ng value override + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX O= utput -6.0dB Mode De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 11; ///< Reserved Bits +} PCH_HSIO_PCIE_LANE_CONFIG; + +/// +/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO= for PCIe lanes +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// These members describe the configuration of HSIO for PCIe lanes. + /// + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS]; +} PCH_HSIO_PCIE_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _HSIO_PCIE_LANE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Hsi= oSataConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/= HsioSataConfig.h new file mode 100644 index 0000000000..a79542d657 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataCo= nfig.h @@ -0,0 +1,66 @@ +/** @file + Hsio Sata policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _HSIO_SATA_CONFIG_H_ +#define _HSIO_SATA_CONFIG_H_ + +#define HSIO_SATA_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gHsioSataPreMemConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane +**/ +typedef struct { + // + // HSIO Rx Eq + // + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value + // + // HSIO Tx Eq + // + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Ou= tput Downscale Amplitude Adjustment value + UINT32 RsvdBits0 : 4; ///< Reserved bits + + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Ou= tput Downscale Amplitude Adjustment + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value over= ride + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Ou= tput Downscale Amplitude Adjustment + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Ou= tput De-Emphasis Adjustment Setting + + UINT32 HsioTxGen2DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Ou= tput De-Emphasis Adjustment Setting + UINT32 RsvdBits1 : 4; ///< Reserved bits + + UINT32 HsioTxGen3DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Ou= tput De-Emphasis Adjustment Setting value override + UINT32 RsvdBits2 : 25; ///< Reserved bits +} PCH_HSIO_SATA_PORT_LANE; + +/// +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the= SATA controller. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// These members describe the configuration of HSIO for SATA lanes. + /// + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS]; +} PCH_HSIO_SATA_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _HSIO_SATA_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Int= erruptConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock= /InterruptConfig.h new file mode 100644 index 0000000000..788931b83d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/InterruptC= onfig.h @@ -0,0 +1,58 @@ +/** @file + Interrupt policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _INTERRUPT_CONFIG_H_ +#define _INTERRUPT_CONFIG_H_ + +#define INTERRUPT_CONFIG_REVISION 1 +extern EFI_GUID gInterruptConfigGuid; + +#pragma pack (push,1) + +// +// --------------------- Interrupts Config ------------------------------ +// +typedef enum { + PchNoInt, ///< No Interrupt Pin + PchIntA, + PchIntB, + PchIntC, + PchIntD +} PCH_INT_PIN; + +/// +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and= interrupt mode for PCH device. +/// +typedef struct { + UINT8 Device; ///< Device number + UINT8 Function; ///< Device function + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see= PCH_INT_PIN) + UINT8 Irq; ///< IRQ to be set for device. +} PCH_DEVICE_INTERRUPT_CONFIG; + +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH d= evices +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC regi= sters in ITSS + +/// +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header + UINT8 NumOfDevIntConfig; = ///< Number of entries in DevIntConfig table + UINT8 Rsvd0[3]; = ///< Reserved bytes, align to multiple 4. + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFI= G]; ///< Array which stores PCH devices interrupts settings + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; = ///< Array which stores interrupt routing for 8259 controller + UINT8 GpioIrqRoute; = ///< Interrupt routing for GPIO. Default is 14. + UINT8 SciIrqSelect; = ///< Interrupt select for SCI. Default is 9. + UINT8 TcoIrqSelect; = ///< Interrupt select for TCO. Default is 9. + UINT8 TcoIrqEnable; = ///< Enable IRQ generation for TCO. 0: Disable; 1: Enable. +} PCH_INTERRUPT_CONFIG; + +#pragma pack (pop) + +#endif // _INTERRUPT_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoA= picConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Io= ApicConfig.h new file mode 100644 index 0000000000..ce1d8f746d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IoApicConf= ig.h @@ -0,0 +1,68 @@ +/** @file + IoApic policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IOAPIC_CONFIG_H_ +#define _IOAPIC_CONFIG_H_ + +#define IOAPIC_CONFIG_REVISION 2 +extern EFI_GUID gIoApicConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_IOAPIC_CONFIG block describes the expected configuration of the = PCH + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit = is + not TRUE. Bus:device:function fields will be programmed to the register + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpos= e: + As the Requester ID when initiating Interrupt Messages to the processor. + As the Completer ID when responding to the reads targeting the IOxAPI's + Memory-Mapped I/O registers. + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS can + program this field to provide a unique Bus:Device:Function number for the + internal IOxAPIC. + The address resource range of IOAPIC must be reserved in E820 and ACPI as + system resource. + + Revision 1: + - Initial version. + Revision 2: + - Add Enable8254ClockGatingOnS3. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable = IOAPIC Entry 24-119 + /** + Enable 8254 Static Clock Gating during early POST time. 0: Disable, 1: Enable + Setting 8254CGE is required to support SLP_S0. + Enable this if 8254 timer is not used. + However, set 8254CGE=3D1 in POST time might fail to boot legacy OS usi= ng 8254 timer. + Make sure it is disabled to support legacy OS using 8254 timer. + @note: + For some OS environment that it needs to set 8254CGE in late state it = should + set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in SM= M later. + This is also required during S3 resume. + To avoid SMI requirement in S3 reusme path, it can enable the Enable82= 54ClockGatingOnS3 + and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_= SAI. + **/ + UINT32 Enable8254ClockGating : 1; + /** + Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, 1: E= nable + This is only applicable when Enable8254ClockGating is disabled. + If Enable8254ClockGating is enabled, RC will do the 8254 CGE programmi= ng on + S3 resume path as well. + **/ + UINT32 Enable8254ClockGatingOnS3 : 1; + UINT32 RsvdBits1 : 29; ///< Reserved bits + UINT8 IoApicId; ///< This member determines IOAPIC= ID. Default is 0x02. + UINT8 Rsvd0[3]; ///< Reserved bytes +} PCH_IOAPIC_CONFIG; + +#pragma pack (pop) + +#endif // _IOAPIC_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Ish= Config.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshCo= nfig.h new file mode 100644 index 0000000000..d03ef377ce --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/IshConfig.h @@ -0,0 +1,57 @@ +/** @file + ISH policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ISH_CONFIG_H_ +#define _ISH_CONFIG_H_ + +#define ISH_PREMEM_CONFIG_REVISION 1 +#define ISH_CONFIG_REVISION 1 +extern EFI_GUID gIshPreMemConfigGuid; +extern EFI_GUID gIshConfigGuid; + +#pragma pack (push,1) + +/// +/// The PCH_ISH_CONFIG block describes Integrated Sensor Hub device. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 SpiGpioAssign : 1; ///< ISH SPI GPIO pins assigned: 0:= False 1: True + UINT32 Uart0GpioAssign : 1; ///< ISH UART0 GPIO pins assigned: = 0: False 1: True + UINT32 Uart1GpioAssign : 1; ///< ISH UART1 GPIO pins assigned: = 0: False 1: True + UINT32 I2c0GpioAssign : 1; ///< ISH I2C0 GPIO pins assigned: 0= : False 1: True + UINT32 I2c1GpioAssign : 1; ///< ISH I2C1 GPIO pins assigned: 0= : False 1: True + UINT32 I2c2GpioAssign : 1; ///< ISH I2C2 GPIO pins assigned: 0= : False 1: True + UINT32 Gp0GpioAssign : 1; ///< ISH GP_0 GPIO pin assigned: 0:= False 1: True + UINT32 Gp1GpioAssign : 1; ///< ISH GP_1 GPIO pin assigned: 0:= False 1: True + UINT32 Gp2GpioAssign : 1; ///< ISH GP_2 GPIO pin assigned: 0:= False 1: True + UINT32 Gp3GpioAssign : 1; ///< ISH GP_3 GPIO pin assigned: 0:= False 1: True + UINT32 Gp4GpioAssign : 1; ///< ISH GP_4 GPIO pin assigned: 0:= False 1: True + UINT32 Gp5GpioAssign : 1; ///< ISH GP_5 GPIO pin assigned: 0:= False 1: True + UINT32 Gp6GpioAssign : 1; ///< ISH GP_6 GPIO pin assigned: 0:= False 1: True + UINT32 Gp7GpioAssign : 1; ///< ISH GP_7 GPIO pin assigned: 0:= False 1: True + UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: 0: False 1: True + UINT32 RsvdBits0 : 17; ///< Reserved Bits +} PCH_ISH_CONFIG; + +/// +/// Premem Policy for Integrated Sensor Hub device. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + ISH Controler 0: Disable; 1: Enable. + For Desktop sku, the ISH POR should be disabled. 0:Disable . + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; ///< Reserved Bits +} PCH_ISH_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _ISH_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Lan= Config.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanCo= nfig.h new file mode 100644 index 0000000000..6bf34f8fe7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LanConfig.h @@ -0,0 +1,35 @@ +/** @file + Lan policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _LAN_CONFIG_H_ +#define _LAN_CONFIG_H_ + +#define LAN_CONFIG_REVISION 1 +extern EFI_GUID gLanConfigGuid; + +#pragma pack (push,1) + +/** + PCH intergrated LAN controller configuration settings. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Determines if enable PCH internal LAN, 0: Disable; 1: Enable. + When Enable is changed (from disabled to enabled or from enabled to di= sabled), + it needs to set LAN Disable register, which might be locked by FDSWL r= egister. + So it's recommendated to issue a global reset when changing the status= for PCH Internal LAN. + **/ + UINT32 Enable : 1; + UINT32 LtrEnable : 1; ///< 0: Disable; 1: Enable LTR cap= abilty of PCH internal LAN. + UINT32 RsvdBits0 : 30; ///< Reserved bits +} PCH_LAN_CONFIG; + +#pragma pack (pop) + +#endif // _LAN_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Loc= kDownConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/= LockDownConfig.h new file mode 100644 index 0000000000..a3a08c3cf6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LockDownCo= nfig.h @@ -0,0 +1,70 @@ +/** @file + Lock down policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _LOCK_DOWN_CONFIG_H_ +#define _LOCK_DOWN_CONFIG_H_ + +#define LOCK_DOWN_CONFIG_REVISION 1 +extern EFI_GUID gLockDownConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of t= he PCH + for security requirement. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + (Test) Enable SMI_LOCK bit to prevent writes to the Global SMI = Enable bit. 0: Disable; 1: Enable. + **/ + UINT32 GlobalSmi : 1; + /** + (Test) Enable BIOS Interface Lock Down bit to prevent writes to= the Backup Control Register + Top Swap bit and the General Control and Status Registers Boot BIOS St= raps. + Intel strongly recommends that BIOS sets the BIOS Interface Lock Down = bit. Enabling this bit + will mitigate malicious software attempts to replace the system BIOS w= ith its own code. + 0: Disable; 1: Enable. + **/ + UINT32 BiosInterface : 1; + /** + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in= the upper + and lower 128-byte bank of RTC RAM. 0: Disable; 1: Enable. + **/ + UINT32 RtcMemoryLock : 1; + /** + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:Reg= DCh[5]) + for the BIOS region protection. When it is enabled, the BIOS Region ca= n only be + modified from SMM after EndOfDxe protocol is installed. + Note: When BiosLock is enabled, platform code also needs to update to = take care + of BIOS modification (including SetVariable) in DXE or runtime phase a= fter + EndOfDxe protocol is installed. + Enable InSMM.STS (EISS) in SPI + If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be = '1' also + in order to write to BIOS regions of SPI Flash. If this EISS bit is cl= ear, + then the InSMM.STS is a don't care. + The BIOS must set the EISS bit while BIOS Guard support is enabled. + In recovery path, platform can temporary disable EISS for SPI programm= ing in + PEI phase or early DXE phase. + 0: Disable; 1: Enable. + **/ + UINT32 BiosLock : 1; + /** + (Test) This test option when set will force all GPIO pads to be= unlocked + before BIOS transitions to POSTBOOT_SAI. This option should not be ena= bled in production + configuration and used only for debug purpose when free runtime reconf= iguration of + GPIO pads is needed. + 0: Disable; 1: Enable. + **/ + UINT32 UnlockGpioPads : 1; + UINT32 RsvdBits0 : 27; ///< Reserved bits +} PCH_LOCK_DOWN_CONFIG; + +#pragma pack (pop) + +#endif // _LOCK_DOWN_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Lpc= Config.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcCo= nfig.h new file mode 100644 index 0000000000..6ee9fe2d75 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h @@ -0,0 +1,34 @@ +/** @file + Lpc policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _LPC_CONFIG_H_ +#define _LPC_CONFIG_H_ + +#define LPC_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gLpcPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to LPC. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Enhance the port 8xh decoding. + Original LPC only decodes one byte of port 80h, with this enhancement = LPC can decode word or dword of port 80h-83h. + @note: this will occupy one LPC generic IO range register. While this = is enabled, read from port 80h always return 0x00. + 0: Disable, 1: Enable + **/ + UINT32 EnhancePort8xhDecoding : 1; + UINT32 RsvdBits : 31; ///< Reserved bits +} PCH_LPC_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _LPC_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2s= bConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sb= Config.h new file mode 100644 index 0000000000..5e1971cb9c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/P2sbConfig= .h @@ -0,0 +1,49 @@ +/** @file + P2sb policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _P2SB_CONFIG_H_ +#define _P2SB_CONFIG_H_ + +#define P2SB_CONFIG_REVISION 2 +extern EFI_GUID gP2sbConfigGuid; + +#pragma pack (push,1) + +/** + This structure contains the policies which are related to P2SB device. + + Revision 1: + - Initial version. + Revision 2: + - Deprecate SbiUnlock policy. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + @deprecated from REVISION 2. + (Test) + This unlock the SBI lock bit to allow SBI after post time. + For CFL: 0: Lock SBI; 1: Unlock SBI. + NOTE: Do not change this policy "SbiUnlock" unless its necessary. + **/ + UINT32 SbiUnlock : 1; + /** + (Test) + The sideband MMIO register access to specific ports will be locked + before 3rd party code execution. Currently it disables PSFx access. + This policy unlocks the sideband MMIO space for those IPs. + 0: Lock sideband access ; 1: Unlock sideband access. + NOTE: Do not set this policy "SbAccessUnlock" unless its necessary. + **/ + UINT32 SbAccessUnlock : 1; + UINT32 Rsvdbits : 30; ///< Reserved bits +} PCH_P2SB_CONFIG; + +#pragma pack (pop) + +#endif // _P2SB_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Pch= GeneralConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBloc= k/PchGeneralConfig.h new file mode 100644 index 0000000000..67f9a121ca --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneral= Config.h @@ -0,0 +1,71 @@ +/** @file + PCH General policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_GENERAL_CONFIG_H_ +#define _PCH_GENERAL_CONFIG_H_ + +#define PCH_GENERAL_CONFIG_REVISION 3 +#define PCH_GENERAL_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gPchGeneralConfigGuid; +extern EFI_GUID gPchGeneralPreMemConfigGuid; + +#pragma pack (push,1) + +enum PCH_RESERVED_PAGE_ROUTE { + PchReservedPageToLpc, ///< Port 80h cycles are sent to= LPC. + PchReservedPageToPcie ///< Port 80h cycles are sent to= PCIe. +}; + +/** + PCH postmem general config block. + + Revision 1: + - Initial version. + Revision 2: + - Remove SubSystemVendorId and SubSystemId. + Revision 3: + - Add LegacyIoLowLatency support. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This member describes whether or not the Compatibility Revision ID (CR= ID) feature + of PCH should be enabled. 0: Disable; 1: Enable + **/ + UINT32 Crid : 1; + /** + Set to enable low latency of legacy IO. + Some systems require lower IO latency irrespective of power. + This is a tradeoff between power and IO latency. + @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent + and ITSS Clock Gating are forced to disabled. + 0: Disable, 1: Enable + **/ + UINT32 LegacyIoLowLatency : 1; + UINT32 RsvdBits0 : 30; ///< Reserved bits +} PCH_GENERAL_CONFIG; + +/** + PCH premem general config block. + + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. + **/ + UINT32 Port80Route : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits +} PCH_GENERAL_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_GENERAL_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Pch= TraceHubConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlo= ck/PchTraceHubConfig.h new file mode 100644 index 0000000000..36527a5af3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PchTraceHu= bConfig.h @@ -0,0 +1,36 @@ +/** @file + PCH Trace Hub policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_TRACEHUB_CONFIG_H_ +#define _PCH_TRACEHUB_CONFIG_H_ + +#define PCH_TRACEHUB_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gPchTraceHubPreMemConfigGuid; + +#pragma pack (push,1) + +/// +/// The PCH_TRACE_HUB_CONFIG block describes TraceHub settings for PCH. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 EnableMode : 2; ///< 0 =3D Disable; 1 =3D = Target Debugger mode; 2 =3D Host Debugger mode + /** + Pch Trace hub memory buffer region size policy. + The avaliable memory size options are: 0:0MB (none), 1:1MB, 2:8MB= , 3:64MB, 4:128MB, 5:256MB, 6:512MB. + Refer to TRACE_BUFFER_SIZE in TraceHubCommon.h for supported settings. + Note : Limitation of total buffer size (CPU + PCH) is 512MB. + **/ + UINT32 MemReg0Size : 8; + UINT32 MemReg1Size : 8; + UINT32 RsvdBits0 : 14; ///< Reserved bits +} PCH_TRACE_HUB_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _TRACEHUB_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Pci= eRpConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Pc= ieRpConfig.h new file mode 100644 index 0000000000..7d23fcd15f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PcieRpConf= ig.h @@ -0,0 +1,429 @@ +/** @file + Pcie root port policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIE_CONFIG_H_ +#define _PCH_PCIE_CONFIG_H_ + +#include + +#define PCIE_RP_CONFIG_REVISION 3 +#define PCIE_RP_PREMEM_CONFIG_REVISION 1 + +extern EFI_GUID gPcieRpConfigGuid; +extern EFI_GUID gPcieRpPreMemConfigGuid; + +#pragma pack (push,1) + +#define PCH_PCIE_SWEQ_COEFFS_MAX 5 + +typedef enum { + PchPcieOverrideDisabled =3D 0, + PchPcieL1L2Override =3D 0x01, + PchPcieL1SubstatesOverride =3D 0x02, + PchPcieL1L2AndL1SubstatesOverride =3D 0x03, + PchPcieLtrOverride =3D 0x04 +} PCH_PCIE_OVERRIDE_CONFIG; + +/** + PCIe device table entry entry + + The PCIe device table is being used to override PCIe device ASPM setting= s. + To take effect table consisting of such entries must be instelled as PPI + on gPchPcieDeviceTablePpiGuid. + Last entry VendorId must be 0. +**/ +typedef struct { + UINT16 VendorId; ///< The vendor Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Vendor ID + UINT16 DeviceId; ///< The Device Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Device ID + UINT8 RevId; ///< The Rev Id of Pci Express card= ASPM setting override, 0xFF means all steppings + UINT8 BaseClassCode; ///< The Base Class Code of Pci Exp= ress card ASPM setting override, 0xFF means all base class + UINT8 SubClassCode; ///< The Sub Class Code of Pci Expr= ess card ASPM setting override, 0xFF means all sub class + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH= _PCIE_ASPM_CONTROL) + ///< Bit 1 must be set in OverrideC= onfig for this field to take effect + UINT16 OverrideConfig; ///< The override config bitmap (se= e: PCH_PCIE_OVERRIDE_CONFIG). + /** + The L1Substates Capability Offset Override. (applicable if bit 2 is se= t in OverrideConfig) + This field can be zero if only the L1 Substate value is going to be ov= erride. + **/ + UINT16 L1SubstatesCapOffset; + /** + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideCo= nfig) + Set to zero then the L1 Substate Capability [3:0] is ignored, and only= L1s values are override. + Only bit [3:0] are applicable. Other bits are ignored. + **/ + UINT8 L1SubstatesCapMask; + /** + L1 Substate Port Common Mode Restore Time Override. (applicable if bit= 2 is set in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sCommonModeRestoreTime; + /** + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnScale; + /** + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set= in OverrideConfig) + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue. + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored, + and only L1SubstatesCapOffset is override. + **/ + UINT8 L1sTpowerOnValue; + + /** + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 SnoopLatency; + /** + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid + When clear values in bits 9:0 will be ignored + BITS[14:13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be= multiplied with + the scale in bits 12:10 + + This field takes effect only if bit 3 is set in OverrideConfig. + **/ + UINT16 NonSnoopLatency; + + /** + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected d= evice sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled,= then: + rootport will use LTR override values provided by BIOS forever; LTR = messages sent from connected device will be ignored + **/ + UINT8 ForceLtrOverride; + UINT8 Reserved[3]; +} PCH_PCIE_DEVICE_OVERRIDE; + +enum PCH_PCIE_SPEED { + PchPcieAuto, + PchPcieGen1, + PchPcieGen2, + PchPcieGen3 +}; + +/// +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature +/// +typedef enum { + PchPcieAspmDisabled, + PchPcieAspmL0s, + PchPcieAspmL1, + PchPcieAspmL0sL1, + PchPcieAspmAutoConfig, + PchPcieAspmMax +} PCH_PCIE_ASPM_CONTROL; + +/** + Refer to PCH EDS for the PCH implementation values corresponding + to below PCI-E spec defined ranges +**/ +typedef enum { + PchPcieL1SubstatesDisabled, + PchPcieL1SubstatesL1_1, + PchPcieL1SubstatesL1_1_2, + PchPcieL1SubstatesMax +} PCH_PCIE_L1SUBSTATES_CONTROL; + +enum PCH_PCIE_MAX_PAYLOAD { + PchPcieMaxPayload128 =3D 0, + PchPcieMaxPayload256, + PchPcieMaxPayloadMax +}; + +enum PCH_PCIE_COMPLETION_TIMEOUT { + PchPcieCompletionTO_Default, + PchPcieCompletionTO_50_100us, + PchPcieCompletionTO_1_10ms, + PchPcieCompletionTO_16_55ms, + PchPcieCompletionTO_65_210ms, + PchPcieCompletionTO_260_900ms, + PchPcieCompletionTO_1_3P5s, + PchPcieCompletionTO_4_13s, + PchPcieCompletionTO_17_64s, + PchPcieCompletionTO_Disabled +}; + +typedef enum { + PchPcieEqDefault =3D 0, ///< @deprecated since revision 3. Behaves= as PchPcieEqHardware. + PchPcieEqHardware =3D 1, ///< Hardware equalization + PchPcieEqStaticCoeff =3D 4 ///< Fixed equalization (requires Coeffici= ent settings per lane) +} PCH_PCIE_EQ_METHOD; + +/** + Represent lane specific PCIe Gen3 equalization parameters. +**/ +typedef struct { + UINT8 Cm; ///< Coefficient C-1 + UINT8 Cp; ///< Coefficient C+1 + UINT8 Rsvd0[2]; ///< Reserved bytes +} PCH_PCIE_EQ_LANE_PARAM, PCH_PCIE_EQ_PARAM; + + +/** + PCH_PCIE_CLOCK describes PCIe source clock generated by PCH. +**/ +typedef struct { + UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_US= AGE). Default: Unused, 0xFF + UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping= with Clock numbers + UINT8 RsvdBytes[2]; ///< Reserved byte +} PCH_PCIE_CLOCK; + +/** + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability= of each PCH PCIe root port. +**/ +typedef struct { + UINT32 HotPlug : 1; ///< Indicate whether th= e root port is hot plug available. 0: Disable; 1: Enable. + UINT32 PmSci : 1; ///< Indicate whether th= e root port power manager SCI is enabled. 0: Disable; 1: Enable. + UINT32 ExtSync : 1; ///< Indicate whether th= e extended synch is enabled. 0: Disable; 1: Enable. + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether th= e Transmitter Half Swing is enabled. 0: Disable; 1: Enable. + UINT32 AcsEnabled : 1; ///< Indicate whether th= e ACS is enabled. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 11; ///< Reserved bits. + /** + Probe CLKREQ# signal before enabling CLKREQ# based power management. + Conforming device shall hold CLKREQ# low until CPM is enabled. This fe= ature attempts + to verify CLKREQ# signal is connected by testing pad state before enab= ling CPM. + In particular this helps to avoid issues with open-ended PCIe slots. + This is only applicable to non hot-plug ports. + 0: Disable; 1: Enable. + **/ + UINT32 ClkReqDetect : 1; + // + // Error handlings + // + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether th= e Advanced Error Reporting is enabled. 0: Disable; 1: Enable. + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether th= e Unsupported Request Report is enabled. 0: Disable; 1: Enable. + UINT32 FatalErrorReport : 1; ///< Indicate whether th= e Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 NoFatalErrorReport : 1; ///< Indicate whether th= e No Fatal Error Report is enabled. 0: Disable; 1: Enable. + UINT32 CorrectableErrorReport : 1; ///< Indicate whether th= e Correctable Error Report is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether th= e System Error on Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether th= e System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable. + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether th= e System Error on Correctable Error is enabled. 0: Disable; 1: Enabl= e. + /** + Max Payload Size supported, Default 128B, see enum PCH_PCIE_MAX= _PAYLOAD + Changes Max Payload Size Supported field in Device Capabilities of the= root port. + **/ + UINT32 MaxPayload : 2; + UINT32 RsvdBits1 : 1; ///< Reserved fields for= future expansion w/o protocol change + UINT32 DpcEnabled : 1; ///< Downstream Port Con= tainment. 0: Disable; 1: Enable + UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for D= ownstream Port Containment. 0: Disable; 1: Enable + /** + Indicates how this root port is connected to endpoint. 0: built-in dev= ice; 1: slot + Built-in is incompatible with hotplug-capable ports. + **/ + UINT32 SlotImplemented : 1; + UINT32 RsvdBits3 : 1; ///< Placeholder for del= eted field + /** + Determines each PCIE Port speed capability. + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3 (see: PCH_PCIE_SPEED) + **/ + UINT8 PcieSpeed; + /** + PCIe Gen3 Equalization Phase 3 Method (see PCH_PCIE_EQ_METHOD). + 0: DEPRECATED, hardware equalization; 1: hardware equalization;= 4: Fixed Coefficients + **/ + UINT8 Gen3EqPh3Method; + + UINT8 PhysicalSlotNumber; ///< Indicates the slot = number for the root port. Default is the value as root port index. + UINT8 CompletionTimeout; ///< The completion time= out configuration of the root port (see: PCH_PCIE_COMPLETION_TIMEOUT). Defa= ult is PchPcieCompletionTO_Default. + /** + The PCH pin assigned to device PERST# signal if available, zero otherw= ise. + This entry is used mainly in Gen3 software equalization flow. It is ne= cessary for some devices + (mainly some graphic adapters) to successfully complete the software e= qualization flow. + See also DeviceResetPadActiveHigh + **/ + UINT32 RsvdBytes0[2]; ///< Reserved bytes + // + // Power Management + // + UINT8 Aspm; ///< The ASPM configurat= ion of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is PchPcieAsp= mAutoConfig for CNP-LP B1 it is limited to PchPcieAspmL1. + UINT8 L1Substates; ///< The L1 Substates co= nfiguration of the root port (see: PCH_PCIE_L1SUBSTATES_CONTROL). Default i= s PchPcieL1SubstatesL1_1_2. + UINT8 LtrEnable; ///< Latency Tolerance R= eporting Mechanism. 0: Disable; 1: Enable. + UINT8 LtrConfigLock; ///< 0: Disable; = 1: Enable. + UINT16 LtrMaxSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Snoop Latency. + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Non-Snoop Latency. + UINT8 SnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Mode. + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Multiplier. + UINT16 SnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Value. + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Mode. + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Multiplier. + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Value. + UINT32 SlotPowerLimitScale : 2; ///< (Test) Speci= fies scale used for slot power limit value. Leave as 0 to set to default. D= efault is zero. + UINT32 SlotPowerLimitValue : 12; ///< (Test) Speci= fies upper limit on power supplies by slot. Leave as 0 to set to default. D= efault is zero. + // + // Gen3 Equalization settings + // + UINT32 Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen3 Link Equalization. Used for al= l lanes. Default is 5. + UINT32 Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen3 Link Equalization. Used for a= ll lanes. Default is 7. + /** + (Test) + Forces LTR override to be permanent + The default way LTR override works is: + rootport uses LTR override values provided by BIOS until connected d= evice sends an LTR message, then it will use values from the message + This settings allows force override of LTR mechanism. If it's enabled,= then: + rootport will use LTR override values provided by BIOS forever; LTR = messages sent from connected device will be ignored + **/ + UINT32 ForceLtrOverride : 1; + UINT32 EnableCpm : 1; ///< Enables= Clock Power Management; even if disabled, CLKREQ# signal can still be cont= rolled by L1 PM substates mechanism + UINT32 PtmEnabled : 1; ///< Enables= PTM capability + UINT32 PcieRootPortGen2PllL1CgDisable : 1; ///< Disable= s Gen2PLL shutdown and L1 state controller power gating + UINT32 RsvdBits2 : 6; ///< Reserve= d Bits + /** + The number of milliseconds reference code will wait for link to exit D= etect state for enabled ports + before assuming there is no device and potentially disabling the port. + It's assumed that the link will exit detect state before root port ini= tialization (sufficient time + elapsed since PLTRST de-assertion) therefore default timeout is zero. = However this might be useful + if device power-up seqence is controlled by BIOS or a specific device = requires more time to detect. + In case of non-common clock enabled the default timout is 15ms. + Default: 0 + **/ + UINT16 DetectTimeoutMs; + UINT16 RsvdBytes1[3]; ///< Reserved bytes +} PCH_PCIE_ROOT_PORT_CONFIG; + +/** + The PCH_PCIE_CONFIG block describes the expected configuration of the PC= H PCI Express controllers + + Revision 1: + - Init version + Revision 2: + - Add policy PcieRootPortGen2PllL1CgDisable in PCH_PCIE_ROOT_PORT_CONFIG. + Revision 3: + - Deleted all items related to PCIe Gen3 software equalization: + DeviceResetPad, DeviceResetPadActiveHigh policies and two values fro= m PCH_PCIE_EQ_METHOD enum used for Gen3EqPh3Method field +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + /// + /// Configuration of PCIe source clocks + /// + PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS]; + /// + /// Gen3 Equalization settings for physical PCIe lane, index 0 represent= s PCIe lane 1, etc. + /// Corresponding entries are used when root port EqPh3Method is PchPcie= EqStaticCoeff (default). + /// + PCH_PCIE_EQ_LANE_PARAM EqPh3LaneParam[PCH_MAX_PCIE_ROOT_PORTS= ]; + /// + /// List of coefficients used during equalization (applicable to both so= ftware and hardware EQ) + /// + PCH_PCIE_EQ_PARAM SwEqCoeffList[PCH_PCIE_SWEQ_COEFFS_MAX= ]; + PCH_PCIE_EQ_PARAM Rsvd0[3]; + /// + /// (Test) This member describes whether PCIE root port Port 8xh = Decode is enabled. 0: Disable; 1: Enable. + /// + UINT32 EnablePort8xhDecode : 1; + /// + /// (Test) The Index of PCIe Port that is selected for Port8xh De= code (0 Based) + /// + UINT32 PchPciePort8xhDecodePortIndex : 5; + /// + /// This member describes whether the PCI Express Clock Gating for each = root port + /// is enabled by platform modules. 0: Disable; 1: Enable. + /// + UINT32 DisableRootPortClockGating : 1; + /// + /// This member describes whether Peer Memory Writes are enabled on the = platform. 0: Disable; 1: Enable. + /// + UINT32 EnablePeerMemoryWrite : 1; + /** + Compliance Test Mode shall be enabled when using Compliance Load Board. + 0: Disable, 1: Enable + **/ + UINT32 ComplianceTestMode : 1; + /** + RpFunctionSwap allows BIOS to use root port function number swapping w= hen root port of function 0 is disabled. + A PCIE device can have higher functions only when Function0 exists. To= satisfy this requirement, + BIOS will always enable Function0 of a device that contains more than = 0 enabled root ports. + - Enabled: One of enabled root ports get assigned to Function0. + This offers no guarantee that any particular root port will be avail= able at a specific DevNr:FuncNr location + - Disabled: Root port that corresponds to Function0 will be kept visib= le even though it might be not used. + That way rootport - to - DevNr:FuncNr assignment is constant. This o= ption will impact ports 1, 9, 17. + NOTE: This option will not work if ports 1, 9, 17 are fused or confi= gured for RST PCIe storage or disabled through policy + In other words, it only affects ports that would become hidden= because they have no device connected. + NOTE: Disabling function swap may have adverse impact on power manag= ement. This option should ONLY + be used when each one of root ports 1, 9, 17: + - is configured as PCIe and has correctly configured ClkReq signal= , or + - does not own any mPhy lanes (they are configured as SATA or USB) + **/ + UINT32 RpFunctionSwap : 1; + + UINT32 RsvdBits0 : 22; + /** + PCIe device override table + The PCIe device table is being used to override PCIe device ASPM setti= ngs. + This is a pointer points to a 32bit address. And it's only used in Pos= tMem phase. + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table. + Last entry VendorId must be 0. + The prototype of this policy is: + PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr; + **/ + UINT32 PcieDeviceOverrideTablePtr; + +} PCH_PCIE_CONFIG; + +/** + The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the= PCH PCI Express controllers + Revision 1: + - Init version + - Add RpEnable in premem phase. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config= Block Header + /** + Root Port enabling mask. + Bit0 presents RP1, Bit1 presents RP2, and so on. + 0: Disable; 1: Enable. + **/ + UINT32 RpEnabledMask; + UINT16 PcieImrSize; ///< PCIe I= MR size in megabytes + UINT8 PcieImrEnabled; ///< PCIe I= MR. 0: Disable; 1: Enable. + UINT8 ImrRpSelection; ///< Index = of PCIe root port that is selected for IMR (0 based) +} PCH_PCIE_RP_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _PCH_PCIE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmC= onfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConf= ig.h new file mode 100644 index 0000000000..8748db5e1a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/PmConfig.h @@ -0,0 +1,311 @@ +/** @file + Power Management policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PM_CONFIG_H_ +#define _PM_CONFIG_H_ + +#define PM_CONFIG_REVISION 5 +extern EFI_GUID gPmConfigGuid; + +#pragma pack (push,1) + +/** + This structure allows to customize PCH wake up capability from S5 or Dee= pSx by WOL, LAN, PCIE wake events. +**/ +typedef struct { + /** + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B= (GEN_PMCON_B) register. + When set to 1, this bit blocks wake events from PME_B0_STS in S5, rega= rdless of the state of PME_B0_EN. + When cleared (default), wake events from PME_B0_STS are allowed in S5 = if PME_B0_EN =3D 1. 0: Disable; 1: Enable. + **/ + UINT32 PmeB0S5Dis : 1; + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enabl= e Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0= : Disable; 1: Enable. + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to w= ake from deep Sx. 0: Disable; 1: Enable. + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from S= x, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0= : Disable; 1: Enable. + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from D= eepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <= b>0: Disable; 1: Enable. + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wa= ke from deep Sx. 0: Disable; 1: Enable. + UINT32 RsvdBits0 : 26; +} PCH_WAKE_CONFIG; + +typedef enum { + PchDeepSxPolDisable, + PchDpS5BatteryEn, + PchDpS5AlwaysEn, + PchDpS4S5BatteryEn, + PchDpS4S5AlwaysEn, +} PCH_DEEP_SX_CONFIG; + +typedef enum { + PchSlpS360us =3D 1, + PchSlpS31ms, + PchSlpS350ms, + PchSlpS32s +} PCH_SLP_S3_MIN_ASSERT; + +typedef enum { + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing a= nd Reset Signal Timings table + PchSlpS41s, + PchSlpS42s, + PchSlpS43s, + PchSlpS44s +} PCH_SLP_S4_MIN_ASSERT; + +typedef enum { + PchSlpSus0ms =3D 1, + PchSlpSus500ms, + PchSlpSus1s, + PchSlpSus4s, +} PCH_SLP_SUS_MIN_ASSERT; + +typedef enum { + PchSlpA0ms =3D 1, + PchSlpA4s, + PchSlpA98ms, + PchSlpA2s, +} PCH_SLP_A_MIN_ASSERT; + +typedef enum { + S0ixDisQNoChange, + S0ixDisQDciOob, + S0ixDisQUsb2Dbc, + S0ixDisQAuto, + S0ixDisQMax, +} S0IX_DISQ_PROBE_TYPE; + +typedef enum { + SlpS0OverrideDisabled =3D 0x0, + SlpS0OverrideEnabled =3D 0x1, + SlpS0OverrideAuto =3D 0x2, + SlpS0OverrideMax +} SLP_S0_OVERRIDE; + +/** + The PCH_PM_CONFIG block describes expected miscellaneous power managemen= t settings. + The PowerResetStatusClear field would clear the Power/Reset status bits,= please + set the bits if you want PCH Init driver to clear it, if you want to che= ck the + status later then clear the bits. + + Revision 1: + - Initial version. + Revision 2: + - Add PsOnEnable and PowerButtonDebounce. + Revision 3: + - Add CpuC10GatePinEnable in PCH_PM_CONFIG. + Revision 4: + - Add PmcDbgMsgEn. + - Removed PmcReadDisable in PCH_PM_CONFIG. + Revision 5: + - Add ModPhySusPgEnable + Revision 6: + - Add SlpS0WithGbeSupport +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header + + PCH_WAKE_CONFIG WakeConfig; ///< Specify W= ake Policy + UINT32 PchDeepSxPol : 4; ///< Deep Sx P= olicy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxP= olDisable. + UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Mi= nimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value= . Default is PchSlpS350ms. + UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Mi= nimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value= . Default is PchSlpS44s. + UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS M= inimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each val= ue. Default is PchSlpSus4s. + UINT32 PchSlpAMinAssert : 4; ///< SLP_A Min= imum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. = Default is PchSlpA2s. + UINT32 RsvdBits0 : 12; + /** + This member describes whether or not the LPC ClockRun feature of PCH s= hould + be enabled. 0: Disable; 1: Enable + **/ + UINT32 LpcClockRun : 1; /// 0: Disabl= e; 1: Enable + UINT32 SlpStrchSusUp : 1; ///< 0: Dis= able; 1: Enable SLP_X Stretching After SUS Well Power Up + /** + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; 1: Enable. + Configure On DC PHY Power Diable according to policy SlpLanLowDc. + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is lo= w. + This indicates that LAN PHY should be powered off on battery mode. + This will override the DC_PP_DIS setting by WolEnableOverride. + **/ + UINT32 SlpLanLowDc : 1; + /** + PCH power button override period. + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s + Default is 0: 4s + **/ + UINT32 PwrBtnOverridePeriod : 3; + /** + (Test) + Disable/Enable PCH to CPU enery report feature. 0: Disable; 1: = Enable. + Enery Report is must have feature. Wihtout Energy Report, the performa= nce report + by workloads/benchmarks will be unrealistic because PCH's energy is no= t being accounted + in power/performance management algorithm. + If for some reason PCH energy report is too high, which forces CPU to = try to reduce + its power by throttling, then it could try to disable Energy Report to= do first debug. + This might be due to energy scaling factors are not correct or the LPM= settings are not + kicking in. + **/ + UINT32 DisableEnergyReport : 1; + /** + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX= and during G3 exit. + When set to Enable, PCH will not pull down AC_PRESENT. + This setting is ignored when DeepSx is not supported. + Default is 0:Disable + **/ + UINT32 DisableDsxAcPresentPulldown : 1; + /** + Power button native mode disable. + While FALSE, the PMC's power button logic will act upon the input valu= e from the GPIO unit, as normal. + While TRUE, this will result in the PMC logic constantly seeing the po= wer button as de-asserted. + Default is FALSE. + **/ + UINT32 DisableNativePowerButton : 1; + /** + Indicates whether SLP_S0# is to be asserted when PCH reaches idle stat= e. + When set to one SLP_S0# will be asserted in idle state. + When set to zero SLP_S0# will not toggle and is always drivern high. + 0:Disable, 1:Enable + + If a platform is using SLP_S0 to lower PCH voltage the below policy mu= st be disabled. + **/ + UINT32 SlpS0Enable : 1; + /** + SLP_S0 Voltage Margining Runtime Control. + PCH VCCPRIM_CORE Voltage Margining is under ACPI control. Software in = runtime + may change VCCPRIM_CORE supply voltage based on conditions like HDAudi= o power state + after SLP_S0# assertion. Enable VM runtime control requires ACPI VMON = method + which will allow configuring VCCPRIM_CORE supply voltage. If this conf= iguration is used + ACPI VMON method needs to be provided as it is not implemented in RC. + This setting is dependent on PMIC/VR type used on the platform. + 0: Disable; 1: Enable. + **/ + UINT32 SlpS0VmRuntimeControl : 1; + /** + SLP_S0 0.70V Voltage Margining Support. + Indicates whether SLP_S0# Voltage Margining supports setting PCH VCCPR= IM_CORE down to 0.70V. + This setting is dependent on PMIC/VR type used on the platform. + 0: Disable; 1: Enable. + **/ + UINT32 SlpS0Vm070VSupport : 1; + /** + SLP_S0 0.75V Voltage Margining Support. + Indicates whether SLP_S0# Voltage Margining supports setting PCH VCCPR= IM_CORE down to 0.75V. + This setting is dependent on PMIC/VR type used on the platform. + 0: Disable; 1: Enable. + **/ + UINT32 SlpS0Vm075VSupport : 1; + /** + Decide if SLP_S0# needs to be overriden (de-asserted) when system is i= n debug mode. This is available since CNP-B0. + Select 'Auto', it will be auto-configured according to probe type. Sel= ect 'Enabled' will disable SLP_S0# assertion whereas 'Disabled' will enable= SLP_S0# assertion when debug is enabled. + This policy should keep 'Auto', other options are intended for advance= d configuration only. + please refer to SLP_S0_OVERRIDE + 0: Disable; 1: Enable; 2:Auto + **/ + UINT32 SlpS0Override : 2; + /** + SLP_S0# disqualify for debug prode + used to configure power management setting per debug probe to be disqu= alified from S0ix. + Reminder: USB3 DbC supports S0 only. DCI OOB (aka BSSB) uses CCA probe + Select 'Auto', it will be auto-configured according to probe type. 'No= Change' will keep PMC default settings. Or select the desired debug probe = type for S0ix Override settings.\nReminder: USB3 DbC supports S0 only. DCI = OOB (aka BSSB) uses CCA probe. + Note: This policy should keep 'Auto', other options are intended for a= dvanced configuration only. + please refer to S0IX_DISQ_PROBE_TYPE + 0: No Probe; 1: DCI OOB; 2: USB2 DbC; 3:Auto + **/ + UINT32 SlpS0DisQForDebug : 3; + UINT32 MeWakeSts : 1; ///< Clea= r the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Di= sable; 1: Enable. + UINT32 WolOvrWkSts : 1; ///< Clea= r the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0:= Disable; 1: Enable. + /* + Set true to enable TCO timer. + When FALSE, it disables PCH ACPI timer, and stops TCO timer. + @note: This will have significant power impact when it's enabled. + If TCO timer is disabled, uCode ACPI timer emulation must be enabled, + and WDAT table must not be exposed to the OS. + 0: Disable, 1: Enable + */ + UINT32 EnableTcoTimer : 1; + /* + When VRAlert# feature pin is enabled and its state is '0', + the PMC requests throttling to a T3 Tstate to the PCH throttling unit. + 0: Disable; 1: Enable. + */ + UINT32 VrAlert : 1; + /** + Decide if PS_ON is to be enabled. This is available on desktop only. + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a + lower power target that will be required by the California Energy + Commission (CEC). When FALSE, PS_ON is to be disabled.} + 0: Disable; 1: Enable. + **/ + UINT32 PsOnEnable : 1; + /** + Enable/Disable platform support for CPU_C10_GATE# pin to control gating + of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy needs + to be set if board design includes support for CPU_C10_GATE# pin. + 0: Disable; 1: Enable + **/ + UINT32 CpuC10GatePinEnable : 1; + /** + Control whether to enable PMC debug messages to Trace Hub. + When Enabled, PMC HW will send debug messages to trace hub; + When Disabled, PMC HW will never send debug meesages to trace hub. + @note: When enabled, system may not enter S0ix + 0: Disable; 1: Enable. + **/ + UINT32 PmcDbgMsgEn : 1; + /** + Enable/Disable ModPHY SUS Power Domain Dynamic Gating. + EXT_PWR_GATE# signal (if supported on platform) can be used to + control external FET for power gating ModPHY + @note: This setting is not supported and ignored on PCH-H + 0: Disable; 1: Enable. + **/ + UINT32 ModPhySusPgEnable : 1; + /** + Enable/Disable SLP_S0 with GBE Support. This policy is ignored when Gb= E is not present. + 0: Disable; 1: Enable. + Default is 0 when paired with WHL V0 stepping CPU and 1 for all other = CPUs. + **/ + UINT32 SlpS0WithGbeSupport : 1; + + UINT32 RsvdBits1 : 5; + /* + Power button debounce configuration + Debounce time can be specified in microseconds. Only certain values ac= cording + to below formula are supported: + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock perio= d). + RTC clock with f =3D 32 KHz is used for glitch filter. + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us). + Supported DebounceTime values are following: + DebounceTime =3D 0 -> Debounce feature disabled + DebounceTime > 0 && < 250us -> Not supported + DebounceTime =3D 250us - 1024000us -> Supported range (DebounceTime = =3D 250us * 2^n) + For values not supported by HW, they will be rounded down to closest s= upported one + Default is 0 + */ + UINT32 PowerButtonDebounce; + /** + Reset Power Cycle Duration could be customized in the unit of second. = Please refer to EDS + for all support settings. PCH HW default is 4 seconds, and range is 1~= 4 seconds, where + 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds. + And make sure the setting correct, which never less than the following= register. + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH + - PWRM_CFG.SLP_A_MIN_ASST_WDTH + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH + **/ + UINT8 PchPwrCycDur; + /** + Specifies the Pcie Pll Spread Spectrum Percentage + The value of this policy is in 1/10th percent units. + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO. + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0% + The default is 0xFF: AUTO - No BIOS override. + **/ + UINT8 PciePllSsc; + UINT8 Rsvd0[2]; ///< Reser= ved bytes + +} PCH_PM_CONFIG; + +#pragma pack (pop) + +#endif // _PM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Sat= aConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Sata= Config.h new file mode 100644 index 0000000000..ce1013b05e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SataConfig= .h @@ -0,0 +1,230 @@ +/** @file + Sata policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SATA_CONFIG_H_ +#define _SATA_CONFIG_H_ + +#include + +#define SATA_CONFIG_REVISION 2 +extern EFI_GUID gSataConfigGuid; + +#pragma pack (push,1) + +typedef enum { + PchSataModeAhci, + PchSataModeRaid, + PchSataModeMax +} PCH_SATA_MODE; + +typedef enum { + PchSataOromDelay2sec, + PchSataOromDelay4sec, + PchSataOromDelay6sec, + PchSataOromDelay8sec +} PCH_SATA_OROM_DELAY; + +typedef enum { + PchSataSpeedDefault, + PchSataSpeedGen1, + PchSataSpeedGen2, + PchSataSpeedGen3 +} PCH_SATA_SPEED; + +typedef enum { + PchSataRstMsix, + PchSataRstMsi, + PchSataRstLegacy +} PCH_SATA_RST_INTERRUPT; + +typedef enum { + PchSataRaidClient, + PchSataRaidAlternate, + PchSataRaidServer +} PCH_SATA_RAID_DEV_ID; + +/** + This structure configures the features, property, and capability for eac= h SATA port. +**/ +typedef struct { + /** + Enable SATA port. + It is highly recommended to disable unused ports for power savings + **/ + UINT32 Enable : 1; ///< 0: Disable; 1: E= nable + UINT32 HotPlug : 1; ///< 0: Disable; = 1: Enable + UINT32 InterlockSw : 1; ///< 0: Disable; = 1: Enable + UINT32 External : 1; ///< 0: Disable; = 1: Enable + UINT32 SpinUp : 1; ///< 0: Disable; = 1: Enable the COMRESET initialization Sequence to the device + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1: S= SD + UINT32 DevSlp : 1; ///< 0: Disable; = 1: Enable DEVSLP on the port + UINT32 EnableDitoConfig : 1; ///< 0: Disable; = 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal) + UINT32 DmVal : 4; ///< DITO multiplier. De= fault is 15. + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout= (DITO), Default is 625. + /** + Support zero power ODD 0: Disable, 1: Enable. + This is also used to disable ModPHY dynamic power gate. + **/ + UINT32 ZpOdd : 1; + UINT32 RsvdBits0 : 9; ///< Reserved fields for= future expansion w/o protocol change +} PCH_SATA_PORT_CONFIG; + +/** + Rapid Storage Technology settings. +**/ +typedef struct { + UINT32 Raid0 : 1; ///< 0 : Disable; 1 : Enab= le RAID0 + UINT32 Raid1 : 1; ///< 0 : Disable; 1 : Enab= le RAID1 + UINT32 Raid10 : 1; ///< 0 : Disable; 1 : Enab= le RAID10 + UINT32 Raid5 : 1; ///< 0 : Disable; 1 : Enab= le RAID5 + UINT32 Irrt : 1; ///< 0 : Disable; 1 : Enab= le Intel Rapid Recovery Technology + UINT32 OromUiBanner : 1; ///< 0 : Disable; 1 : Enab= le OROM UI and BANNER + UINT32 OromUiDelay : 2; ///< 00b : 2 secs; 01b = : 4 secs; 10b : 6 secs; 11 : 8 secs (see : PCH_SATA_OROM_DELAY) + UINT32 HddUnlock : 1; ///< 0 : Disable; 1 : Enab= le. Indicates that the HDD password unlock in the OS is enabled + UINT32 LedLocate : 1; ///< 0 : Disable; 1 : Enab= le. Indicates that the LED/SGPIO hardware is attached and ping to locat= e feature is enabled on the OS + UINT32 IrrtOnly : 1; ///< 0 : Disable; 1 : Enab= le. Allow only IRRT drives to span internal and external ports + UINT32 SmartStorage : 1; ///< 0 : Disable; 1 : Enab= le RST Smart Storage caching Bit + UINT32 LegacyOrom : 1; ///< 0 : Disable; 1 : = Enable RST Legacy OROM + UINT32 OptaneMemory : 1; ///< 0: Disable; 1: Enable RST Optane(TM) Memory + UINT32 CpuAttachedStorage : 1; ///< 0: Disable; 1: Enable CPU Attached Storage + /** + This option allows to configure SATA controller device ID while in RAI= D mode. + Refer to PCH_SATA_RAID_DEV_ID enumeration for supported options. + Choosing Client will allow RST driver loading, RSTe driver will not be= able to load + Choosing Alternate will not allow RST inbox driver loading in Windows + Choosing Server will allow RSTe driver loading, RST driver will not lo= ad + 0: Client; 1: Alternate; 2: Server + **/ + UINT32 RaidDeviceId : 2; + /** + Controlls which interrupts will be linked to SATA controller CAP list + This option will take effect only if SATA controller is in RAID mode + Default: PchSataMsix + **/ + UINT32 SataRstInterrupt : 2; + UINT32 RsvdBits0 : 13; ///< Reserved Bits +} PCH_SATA_RST_CONFIG; + +/** + This structure lists PCH supported SATA thermal throttling register sett= ing for customization. + The settings is programmed through SATA Index/Data registers. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch + + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch + + UINT32 P0Tinact : 2; ///< Port 0 Tinactive + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Td= ispatch + UINT32 P1Tinact : 2; ///< Port 1 Tinactive + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Td= ispatch + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values + UINT32 RsvdBits0 : 9; ///< Reserved bits +} SATA_THERMAL_THROTTLING; + +/** + This structure describes the details of Intel RST for PCIe Storage remap= ping + Note: In order to use this feature, Intel RST Driver is required +**/ +typedef struct { + /** + This member describes whether or not the Intel RST for PCIe Storage re= mapping should be enabled. 0: Disable; 1: Enable. + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should = be disabled as well + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI = controllers Class Code is configured as RAID + **/ + UINT32 Enable : 1; + /** + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <= b>0 =3D autodetect) + The supported ports for PCIe Storage remapping is different depend on = the platform and cycle router, the assignments are as below: + i.) RST PCIe Storage Cycle Router 2 -> RP5 - RP8 + ii.) RST PCIe Storage Cycle Router 3 -> RP9 - RP12 + + i.) RST PCIe Storage Cycle Router 1 -> RP9 - RP12 + ii.) RST PCIe Storage Cycle Router 2 -> RP13 - RP16 + iii.) RST PCIe Storage Cycle Router 3 -> RP17 - RP20 + **/ + UINT32 RstPcieStoragePort : 5; + UINT32 RsvdBits0 : 2; ///< Reserved bit + /** + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarant= ees such delay gap is fulfilled + before PCIe Storage Device configuration space is accessed after an re= set caused by the link disable and enable step. + Default value is 100ms. + **/ + UINT32 DeviceResetDelay : 8; + UINT32 RsvdBits1 : 16; ///< Reserved bits + + UINT32 Rsvd0[2]; ///< Reserved bytes +} PCH_RST_PCIE_STORAGE_CONFIG; + +/** + The PCH_SATA_CONFIG block describes the expected configuration of the SA= TA controllers. + + Revision 1: + - Initial version. + Revision 2: + - Add CpuAttachedStorage in PCH_SATA_RST_CONFIG. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header + /// + /// This member describes whether or not the SATA controllers should be = enabled. 0: Disable; 1: Enable. + /// + UINT32 Enable : 1; + UINT32 TestMode : 1; ///< (Test)= 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT32 SalpSupport : 1; ///< 0: Disabl= e; 1: Enable Aggressive Link Power Management + UINT32 PwrOptEnable : 1; ///< 0: Disabl= e; 1: Enable SATA Power Optimizer on PCH side. + /** + EsataSpeedLimit + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSA= TA port speed. + Please be noted, this setting could be cleared by HBA reset, which mig= ht be issued + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver = after POST. + To support the Speed Limitation when POST, the EFI AHCI driver should = preserve the + setting before and after initialization. For support it after POST, it= 's dependent on + driver's behavior. + 0: Disable; 1: Enable + **/ + UINT32 EsataSpeedLimit : 1; + UINT32 LedEnable : 1; ///< SATA LED = indicates SATA controller activity. 0: Disable; 1: Enable SATA LED. + UINT32 RsvdBits0 : 26; ///< Reserved = bits + + /** + Determines the system will be configured to which SATA mode (PCH_SATA_= MODE). Default is PchSataModeAhci. + **/ + PCH_SATA_MODE SataMode; + /** + Indicates the maximum speed the SATA controller can support + 0h: PchSataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2= ); 3h: 6 Gb/s (Gen 1) + **/ + PCH_SATA_SPEED SpeedLimit; + /** + This member configures the features, property, and capability for each= SATA port. + **/ + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; + PCH_SATA_RST_CONFIG Rst; ///< Setting a= pplicable to Rapid Storage Technology + /** + This member describes the details of implementation of Intel RST for P= CIe Storage remapping (Intel RST Driver is required) + Note: RST for PCIe Sorage remapping is supported only for first SATA c= ontroller if more controllers are available + **/ + PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORA= GE_CR]; + /** + This field decides the settings of Sata thermal throttling. When the S= uggested Setting + is enabled, PCH RC will use the suggested representative values. + **/ + SATA_THERMAL_THROTTLING ThermalThrottling; +} PCH_SATA_CONFIG; + +#pragma pack (pop) + +#endif // _SATA_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Scs= Config.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsCo= nfig.h new file mode 100644 index 0000000000..1e91143b93 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ScsConfig.h @@ -0,0 +1,63 @@ +/** @file + Scs policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SCS_CONFIG_H_ +#define _SCS_CONFIG_H_ + +#include + +#define SCS_CONFIG_REVISION 2 +extern EFI_GUID gScsConfigGuid; + +#pragma pack (push,1) + +typedef enum { + DriverStrength33Ohm =3D 0, + DriverStrength40Ohm, + DriverStrength50Ohm +} PCH_SCS_EMMC_DRIVER_STRENGTH; + +/** + The PCH_SCS_CONFIG block describes Storage and Communication Subsystem (= SCS) settings for PCH. + + Revision 1: + - Initial version + Revision 2: + - Add policy SdCardPowerEnableActiveHigh +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + + UINT32 ScsEmmcEnabled : 2; ///< Determine if eMMC i= s enabled - 0: Disabled, 1: Enabled. + UINT32 ScsEmmcHs400Enabled : 1; ///< Determine eMMC HS40= 0 Mode if ScsEmmcEnabled - 0: Disabled, 1: Enabled + /** + Determine if HS400 Training is required, set to FALSE if Hs400 Data is= valid. 0: Disabled, 1: Enabled. + First Boot or CMOS clear, system boot with Default settings, set tunin= g required. + Subsequent Boots, Get Variable 'Hs400TuningData' + - if failed to get variable, set tuning required + - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxD= ataDll from variable. Set tuning not required. + **/ + UINT32 ScsEmmcHs400TuningRequired : 1; + UINT32 ScsEmmcHs400DllDataValid : 1; ///< Set if HS400 Tuning= Data Valid + UINT32 ScsEmmcHs400RxStrobeDll1 : 7; ///< Rx Strobe Delay Con= trol - Rx Strobe Delay DLL 1 (HS400 Mode) + UINT32 ScsEmmcHs400TxDataDll : 7; ///< Tx Data Delay Contr= ol 1 - Tx Data Delay (HS400 Mode) + UINT32 ScsEmmcHs400DriverStrength : 3; ///< I/O driver strength= : 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm + /** + Sd Card Controler 0: Disable; 1: Enable. + For Desktop sku, the SD Card Controller POR should be disabled. 0:= Disable . + **/ + UINT32 ScsSdcardEnabled : 1; + UINT32 ScsUfsEnabled : 1; ///< Determine if Ufs is= enabled 0: Disabled 1: Enabled + UINT32 SdCardPowerEnableActiveHigh : 1; ///< Determine SD_PWREN#= polarity 0: Active low, 1: Active high + UINT32 RsvdBits : 7; + UINT32 Rsvd0; ///< Reserved bytes +} PCH_SCS_CONFIG; + +#pragma pack (pop) + +#endif // _SCS_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Ser= ialIoConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/= SerialIoConfig.h new file mode 100644 index 0000000000..73dfd17c47 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIoCo= nfig.h @@ -0,0 +1,96 @@ +/** @file + Serial IO policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SERIAL_IO_CONFIG_H_ +#define _SERIAL_IO_CONFIG_H_ + +#define SERIAL_IO_CONFIG_REVISION 2 +extern EFI_GUID gSerialIoConfigGuid; + +#pragma pack (push,1) + +/** + The PCH_SERIAL_IO_CONFIG block provides the configurations to set the Se= rial IO controllers + + Revision 1: + - Initial version. + Revision 2: + - Add I2cPadsTermination +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header + /** + 0: Disabled; + - Device is placed in D3 + - Gpio configuration is skipped + - Device will be disabled in PSF + - !important! If given device is Function 0 and not all other LP= SS functions on given device + are disabled, then PSF disabling is skipped. + PSF default will remain and device PCI CFG Space w= ill still be visible. + This is needed to allow PCI enumerator access func= tions above 0 in a multifunction device. + 1: Pci; + - Gpio pin configuration in native mode for each assigned pin + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl + - Device will be enabled in PSF + - Only Bar 0 will be enabled + 2: Acpi; + - Gpio pin configuration in native mode for each assigned pin + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl + - Device will be hidden in PSF and not available to PCI enumerat= or + - Both BARs are enabled, BAR1 becomes devices Pci config Space + @note Intel does not provide Windows SerialIo drivers for this mode + 3: Hidden; + Designated for Kernel Debug and Legacy UART configuartion, might= also be used for IO Expander on I2C + - Device is placed in D0 + - Gpio pin configuration in native mode for each assigned pin + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl + - Device will be hidden in PSF and not available to PCI enumerat= or + - Both BARs are enabled, BAR1 becomes devices Pci config Space + - !important! In this mode UART will work in 16550 Legacy 8BIT M= ode, it's resources will be assigned to mother board through ACPI (PNP0C02) + @note Considering the PcdSerialIoUartDebugEnable and PcdSerialIoUartNu= mber for all SerialIo UARTx, + the PCD is more meaningful to represent the board design. It mea= ns, if PcdSerialIoUartDebugEnable is not 0, + the board is designed to use the SerialIo UART for debug message= and the PcdSerialIoUartNumber is dedicated + to be Debug UART usage. Therefore, it should grayout the option = from setup menu since no other options + available for this UART controller on this board, and also overr= ide the policy default accordingly. + While PcdSerialIoUartDebugEnable is 0, then it's allowed to conf= igure the UART controller by policy. + **/ + UINT8 DevMode[PCH_MAX_SERIALIO_CONTROLLERS]; + UINT8 SpiCsPolarity[PCH_MAX_SERIALIO_SPI_CONTROLLERS]; ///< Selects S= PI ChipSelect signal polarity, 0=3Dactive low. + UINT8 UartHwFlowCtrl[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< Enables U= ART hardware flow control, CTS and RTS lines, 0:disabled, 1:enabled + /** + I2C Pads Internal Termination. + For more information please see Platform Design Guide. + Supported values (check GPIO_ELECTRICAL_CONFIG for reference): + GpioTermNone: No termination, + GpioTermWpu1K: 1kOhm weak pull-up, + GpioTermWpu5K: 5kOhm weak pull-up, + GpioTermWpu20K: 20kOhm weak pull-up + **/ + UINT8 I2cPadsTermination[PCH_MAX_SERIALIO_I2C_CONTROLLERS]; + /** + UART device for debug purpose. 0:UART0, 1: UART1, 2:UART2 + @note If CNVi solution is on the platform and UART0 is selected as BT = Core interface, + UART0 cannot be used for debug purpose. + **/ + UINT32 DebugUartNumber : 2; + UINT32 EnableDebugUartAfterPost : 1; ///< Enable de= bug UART controller after post. 0: diabled, 1: enabled + /** + 0: default pins; 1: pins muxed with CNV_BRI/RGI + UART0 can be configured to use two different sets of pins: + This setting gives flexibility to use UART0 functionality on other pin= s when + default ones are used for a different purpose. + @note Since the second pin set contains pads which are also used for C= NVi purpose, setting Uart0PinMuxing + is exclusive with CNVi being enabled. + **/ + UINT32 Uart0PinMuxing : 1; + UINT32 RsvdBits0 : 28; +} PCH_SERIAL_IO_CONFIG; + +#pragma pack (pop) + +#endif // _SERIAL_IO_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Ser= ialIrqConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock= /SerialIrqConfig.h new file mode 100644 index 0000000000..7ccfe65428 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SerialIrqC= onfig.h @@ -0,0 +1,43 @@ +/** @file + Serial IRQ policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SERIAL_IRQ_CONFIG_H_ +#define _SERIAL_IRQ_CONFIG_H_ + +#define SERIAL_IRQ_CONFIG_REVISION 1 +extern EFI_GUID gSerialIrqConfigGuid; + +#pragma pack (push,1) + +typedef enum { + PchQuietMode, + PchContinuousMode +} PCH_SIRQ_MODE; +/// +/// Refer to PCH EDS for the details of Start Frame Pulse Width in Continu= ous and Quiet mode +/// +typedef enum { + PchSfpw4Clk, + PchSfpw6Clk, + PchSfpw8Clk +} PCH_START_FRAME_PULSE; + +/// +/// The PCH_LPC_SIRQ_CONFIG block describes the expected configuration of = the PCH for Serial IRQ. +/// +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 SirqEnable : 1; ///< Determines if enabl= e Serial IRQ. 0: Disable; 1: Enable. + UINT32 SirqMode : 2; ///< Serial IRQ Mode Sel= ect. Refer to PCH_SIRQ_MODE for each value. 0: quiet mode 1: continu= ous mode. + UINT32 StartFramePulse : 3; ///< Start Frame Pulse W= idth. Refer to PCH_START_FRAME_PULSE for each value. Default is PchSfpw4= Clk. + UINT32 RsvdBits0 : 26; ///< Reserved bits +} PCH_LPC_SIRQ_CONFIG; + +#pragma pack (pop) + +#endif // _SERIAL_IRQ_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Smb= usConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Smb= usConfig.h new file mode 100644 index 0000000000..d96cf9f6cd --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/SmbusConfi= g.h @@ -0,0 +1,52 @@ +/** @file + Smbus policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SMBUS_CONFIG_H_ +#define _SMBUS_CONFIG_H_ + +#define SMBUS_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gSmbusPreMemConfigGuid; + +#pragma pack (push,1) + +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128 + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capabl= e devices in the platform. +/// +typedef struct { + /** + Revision 1: Init version + **/ + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This member describes whether or not the SMBus controller of PCH shoul= d be enabled. + 0: Disable; 1: Enable. + **/ + UINT32 Enable : 1; + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, = 0: Disable; 1: Enable. + UINT32 DynamicPowerGating : 1; ///< (Test) Disable = or Enable Smbus dynamic power gating. + /// + /// (Test) SPD Write Disable, 0: leave SPD Write Disable bit; = 1: set SPD Write Disable bit. + /// For security recommendations, SPD write disable bit must be set. + /// + UINT32 SpdWriteDisable : 1; + UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBAL= ERT#). 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 27; ///< Reserved bits + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space)= . Default is 0xEFA0. + UINT8 Rsvd0; ///< Reserved bytes + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the= RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} PCH_SMBUS_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _SMBUS_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/The= rmalConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/T= hermalConfig.h new file mode 100644 index 0000000000..d3ea563f95 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/ThermalCon= fig.h @@ -0,0 +1,139 @@ +/** @file + Thermal policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _THERMAL_CONFIG_H_ +#define _THERMAL_CONFIG_H_ + +#define THERMAL_CONFIG_REVISION 1 +extern EFI_GUID gThermalConfigGuid; + +#pragma pack (push,1) + +/** + This structure lists PCH supported throttling register setting for custi= mization. + When the SuggestedSetting is enabled, the customized values are ignored. +**/ +typedef struct { + UINT32 T0Level : 9; ///< Custimized T0Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 T1Level : 9; ///< Custimized T1Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 T2Level : 9; ///< Custimized T2Level value. If = SuggestedSetting is used, this setting is ignored. + UINT32 TTEnable : 1; ///< Enable the thermal throttle f= unction. If SuggestedSetting is used, this settings is ignored. + /** + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13= will force at least T2 state. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTState13Enable : 1; + /** + When set to 1, this entire register (TL) is locked and remains locked = until the next platform reset. + If SuggestedSetting is used, this setting is ignored. + **/ + UINT32 TTLock : 1; + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values. + /** + ULT processors support thermal management and cross thermal throttling= between the processor package + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit f= ields to update the PCH + thermal status to the processor which is factored into the processor t= hrottling. + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled. + **/ + UINT32 PchCrossThrottling : 1; + UINT32 Rsvd0; ///< Reserved bytes +} THERMAL_THROTTLE_LEVELS; + +/** + This structure allows to customize DMI HW Autonomous Width Control for T= hermal and Mechanical spec design. + When the SuggestedSetting is enabled, the customized values are ignored. + Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values +**/ +typedef struct { + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous= Width Enable + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values + UINT32 RsvdBits0 : 6; ///< Reserved bits + UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width= (DmiThermSensWidthx8) + UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width= (DmiThermSensWidthx4) + UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width= (DmiThermSensWidthx2) + UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width= (DmiThermSensWidthx1) + UINT32 RsvdBits1 : 12; ///< Reserved bits +} DMI_HW_WIDTH_CONTROL; + +/** + This structure configures PCH memory throttling thermal sensor GPIO PIN = settings +**/ +typedef struct { + /** + GPIO PM_SYNC enable, 0:Diabled, 1:Enabled + When enabled, RC will overrides the selected GPIO native mode. + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1 + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2 + **/ + UINT32 PmsyncEnable : 1; + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 st= ate, 0:Disabled, 1:Enabled + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection= , 0: default, 1: secondary + UINT32 RsvdBits0 : 29; +} TS_GPIO_PIN_SETTING; + +enum PCH_PMSYNC_GPIO_X_SELECTION { + TsGpioC, + TsGpioD, + MaxTsGpioPin +}; + +/** + This structure supports an external memory thermal sensor (TS-on-DIMM or= TS-on-Board). +**/ +typedef struct { + /** + This will enable PCH memory throttling. + While this policy is enabled, must also enable EnableExtts in SA policy. + 0: Disable; 1: Enable + **/ + UINT32 Enable : 1; + UINT32 RsvdBits0 : 31; + /** + GPIO_C and GPIO_D selection for memory throttling. + It's strongly recommended to choose GPIO_C and GPIO_D for memory throt= tling feature, + and route EXTTS# accordingly. + **/ + TS_GPIO_PIN_SETTING TsGpioPinSetting[2]; +} PCH_MEMORY_THROTTLING; + +/** + The PCH_THERMAL_CONFIG block describes the expected configuration of the= PCH for Thermal. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + /** + This locks down "SMI Enable on Alert Thermal Sensor Trip". 0: Disabled= , 1: Enabled. + **/ + UINT32 TsmicLock : 1; + UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion = when temperature is higher than PchHotLevel. 0: Disabled, 1: Enabled. + UINT32 RsvdBits0 : 30; + /** + This field decides the settings of Thermal throttling. When the Sugges= ted Setting + is enabled, PCH RC will use the suggested representative values. + **/ + THERMAL_THROTTLE_LEVELS TTLevels; + /** + This field decides the settings of DMI throttling. When the Suggested = Setting + is enabled, PCH RC will use the suggested representative values. + **/ + DMI_HW_WIDTH_CONTROL DmiHaAWC; + /** + Memory Thermal Management settings + **/ + PCH_MEMORY_THROTTLING MemoryThrottling; + /** + This field decides the temperature, default is 0x154. + The recommendation is the same as Cat Trip point. + **/ + UINT16 PchHotLevel; + UINT8 Rsvd0[6]; +} PCH_THERMAL_CONFIG; + +#pragma pack (pop) + +#endif // _THERMAL_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/Wat= chDogConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/= WatchDogConfig.h new file mode 100644 index 0000000000..78e4497d90 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/WatchDogCo= nfig.h @@ -0,0 +1,33 @@ +/** @file + WatchDog policy + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _WATCH_DOG_CONFIG_H_ +#define _WATCH_DOG_CONFIG_H_ + +#define WATCH_DOG_PREMEM_CONFIG_REVISION 1 +extern EFI_GUID gWatchDogPreMemConfigGuid; + +#pragma pack (push,1) + +/** + This policy clears status bits and disable watchdog, then lock the + WDT registers. + while WDT is designed to be disabled and locked by Policy, + bios should not enable WDT by WDT PPI. In such case, bios shows the + warning message but not disable and lock WDT register to make sure + WDT event trigger correctly. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Config Block Header + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clear = WDT status, then disable and lock WDT registers. 0: Disable; 1: Enab= le. + UINT32 RsvdBits : 31; +} PCH_WDT_PREMEM_CONFIG; + +#pragma pack (pop) + +#endif // _WATCH_DOG_CONFIG_H_ --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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16 Aug 2019 17:16:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319241" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:49 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 06/37] CoffeelakeSiliconPkg/Pch: Add Library include headers Date: Fri, 16 Aug 2019 17:15:32 -0700 Message-Id: <20190817001603.30632-7-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001012; bh=sLWEtV1jiPhy/X9jkntDmCyrIGaePLCZtADzdByHfko=; h=Cc:Date:From:Reply-To:Subject:To; b=qeekBrqa+gVftXQ4oNudst6zPAZLmH+ZA6Kq55gQpusmxYf5y4IHCyfgUcs9lhSDggd wEsa/9ZZHn777NXo7ZS4y0RHnkNqBFar3VnAqBHe0gFmX/K9hGpFpiV2PJQbQtEKPQ5c7 pxG6MBxnnuVU7/Gk5EMUt2XyijMufmtHQFU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds the following header files: * Pch/Include/library Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha Reviewed-by: Nate DeSimone --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h = | 27 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h = | 24 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLib.h = | 58 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h = | 265 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h = | 788 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h = | 166 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h = | 33 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib= .h | 371 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h = | 141 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h = | 36 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h = | 109 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h = | 407 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h = | 105 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h = | 226 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h = | 45 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h = | 114 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h = | 24 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLib.h = | 116 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib.h = | 240 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUartLib.= h | 111 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlLib.h = | 23 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLib.h = | 121 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h = | 207 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h = | 76 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h = | 22 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommonLib.h= | 98 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h = | 23 + 27 files changed, 3976 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLoc= kLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib= .h new file mode 100644 index 0000000000..ee77334ecb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/BiosLockLib.h @@ -0,0 +1,27 @@ +/** @file + Header file for BiosLockLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BIOSLOCK_LIB_H_ +#define _BIOSLOCK_LIB_H_ + +/** + Enable BIOS lock. This will set the LE (Lock Enable) and EISS (Enable In= SMM.STS). + When this is set, attempts to write the WPD (Write Protect Disable) bit = in PCH + will cause a SMI which will allow the BIOS to verify that the write is f= rom a valid source. + + Bios should always enable LockDownConfig.BiosLock policy to set Bios Loc= k bit in FRC. + If capsule udpate is enabled, it's expected to not do BiosLock by settin= g BiosLock policy disable + so it can udpate BIOS region. + After flash update, it should utilize this lib to do BiosLock for securi= ty. +**/ +VOID +BiosLockEnable ( + VOID + ); + +#endif // _BIOSLOCK_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h new file mode 100644 index 0000000000..f406e0d929 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/CnviLib.h @@ -0,0 +1,24 @@ +/** @file + Header file for CnviLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CNVI_LIB_H_ +#define _CNVI_LIB_H_ + +/** + Check if CNVi is present. + + @retval TRUE CNVi is enabled + @retval FALSE CNVi is disabled + +**/ +BOOLEAN +CnviIsPresent ( + VOID + ); + +#endif // _CNVI_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchP= olicyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchP= olicyLib.h new file mode 100644 index 0000000000..4d1ed91f7e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/DxePchPolicyLi= b.h @@ -0,0 +1,58 @@ +/** @file + Prototype of the DxePchPolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_PCH_POLICY_LIB_H_ +#define _DXE_PCH_POLICY_LIB_H_ + +#include + +/** + This function prints the DXE phase policy. + + @param[in] PchPolicy - PCH DXE Policy protocol +**/ +VOID +PchPrintPolicyProtocol ( + IN PCH_POLICY_PROTOCOL *PchPolicy + ); + +/** + CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] PchPolicy The pointer to get PCH Policy Prot= ocol instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CreatePchDxeConfigBlocks( + IN OUT PCH_POLICY_PROTOCOL **PchPolicy + ); + +/** + PchInstallPolicyProtocol installs PCH Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] PchPolicy The pointer to PCH Policy Protocol= instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +PchInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN PCH_POLICY_PROTOCOL *PchPolicy + ); + +#endif // _DXE_PCH_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiL= ib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h new file mode 100644 index 0000000000..a6ce032eba --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GbeMdiLib.h @@ -0,0 +1,265 @@ +/** @file + Header file for GbeMdiLib. + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denote= d by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in regist= er/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regi= ster/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be= just named + as "_PCH_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GBE_MDI_LIB_H_ +#define _GBE_MDI_LIB_H_ + +// +// +// PHY GENERAL registers +// Registers 0 to 15 are defined by the specification +// Registers 16 to 31 are left available to the vendor +// +#define B_PHY_MDI_PHY_ADDRESS_01 BIT21 +#define B_PHY_MDI_PHY_ADDRESS_MASK (BIT25 | BIT24 | BIT23 | BIT22 | BIT= 21) +#define MDI_REG_SHIFT(x) (x << 16) +#define R_PHY_MDI_PHY_REG_DATA_READ_WRITE 0x00120000 +// LAN PHY MDI registers and bits +// + +// +// Page 769 Port Control Registers +// 6020h (769 * 32) +// +#define PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS 769 + +// +// Port General Configuration PHY Address 01, Page 769, Register 17 +// +#define R_PHY_MDI_PAGE_769_REGISETER_17_PGC 0x0011 +// +// Page 769, Register 17, BIT 4 +// Enables host wake up +// +#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_HOST_WAKE_UP BIT4 +// +// Page 769, Register 17, BIT 2 +// Globally enable the MAC power down feature while the +// GbE supports WoL. When set to 1b, +// pages 800 and 801 are enabled for +// configuration and Host_WU_Active is not blocked for writes. +// +#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_MACPD_ENABLE BIT2 + +// +// Page 800 Wake Up Registers +// 6400h (800 * 32) +// +#define PHY_MDI_PAGE_800_WAKE_UP_REGISTERS 800 +// +// Wake Up Control - WUC PHY Address 01, Page 800, Register 1 +// 1h (Register 1) +// +#define R_PHY_MDI_PAGE_800_REGISETER_1_WUC 0x0001 +// +// Wake Up Control - (WUC) +// Page 800, Register 1, BIT 0 +// Advance Power Management Enable (APME) +// If set to 1b, APM wake up is enabled. +// +#define B_PHY_MDI_PAGE_800_REGISETER_1_WUC_APME BIT0 +// +// Receive Address Low - RAL PHY Address 01, Page 800, Register 16 +// 10h (Register 16) +// +#define R_PHY_MDI_PAGE_800_REGISETER_16_RAL0 0x0010 +// +// Receive Address Low - RAL PHY Address 01, Page 800, Register 17 +// 11h (Register 17) +// +#define R_PHY_MDI_PAGE_800_REGISETER_17_RAL1 0x0011 +// +// Receive Address High - RAH PHY Address 01, Page 800, Register 18 +// 12h (Register 18) +// +#define R_PHY_MDI_PAGE_800_REGISETER_18_RAH0 0x0012 +// +// Receive Address High - RAH PHY Address 01, Page 800, Register 19 +// 13h (Register 19) +// +#define R_PHY_MDI_PAGE_800_REGISETER_19_RAH1 0x0013 +// +// Setting AV (BIT15 RAH is divided on two registers) +// RAH Register 19, Page 800, BIT 31 +// +// Address valid (AV) +// When this bit is set, the relevant RAL and RAH are valid +// +#define B_PHY_MDI_PAGE_800_REGISETER_19_RAH1_ADDRESS_VALID BIT15 +// +// Page 803 Host WoL Packet +// 6460h (803 * 32) +// +#define PHY_MDI_PAGE_803_HOST_WOL_PACKET 803 +// +// Host WoL Packet Clear - HWPC PHY Address 01, Page 803, Register 66 +// +#define R_PHY_MDI_PAGE_803_REGISETER_66_HWPC 0x0042 + + +/** + Change Extended Device Control Register BIT 11 to 1 which + forces the interface between the MAC and the Phy to be on SMBus. + Cleared on the assertion of PCI reset. + + @param [in] GbeBar GbE MMIO space + +**/ +VOID +GbeMdiForceMACtoSMB ( + IN UINT32 GbeBar + ); + +/** + Test for MDIO operation complete. + + @param [in] GbeBar GbE MMIO space + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT +**/ +EFI_STATUS +GbeMdiWaitReady ( + IN UINT32 GbeBar + ); + +/** + Acquire MDIO software semaphore. + + 1. Ensure that MBARA offset F00h [5] =3D 1b + 2. Poll MBARA offset F00h [5] up to 200ms + + @param [in] GbeBar GbE MMIO space + + @retval EFI_SUCCESS + @retval EFI_TIMEOUT +**/ +EFI_STATUS +GbeMdiAcquireMdio ( + IN UINT32 GbeBar + ); + +/** + Release MDIO software semaphore by clearing MBARA offset F00h [5] + + @param [in] GbeBar GbE MMIO space +**/ +VOID +GbeMdiReleaseMdio ( + IN UINT32 GbeBar + ); + +/** + Sets page on MDI + Page setting is attempted twice. + If first attempt failes MAC and the Phy are force to be on SMBus + + @param [in] GbeBar GbE MMIO space + @param [in] Data Value to write in lower 16bits. + + @retval EFI_SUCCESS Page setting was successfull + @retval EFI_DEVICE_ERROR Returned if both attermps of setting page fail= ed +**/ +EFI_STATUS +GbeMdiSetPage ( + IN UINT32 GbeBar, + IN UINT32 Page + ); + +/** + Sets Register in current page. + + @param [in] GbeBar GbE MMIO space + @param [in] register Register number + + @return EFI_STATUS +**/ +EFI_STATUS +GbeMdiSetRegister ( + IN UINT32 GbeBar, + IN UINT32 Register + ); + + +/** + Perform MDI read. + + @param [in] GbeBar GbE MMIO space + @param [in] PhyAddress Phy Address General - 02 or Specific - 01 + @param [in] PhyRegister Phy Register + @param [out] ReadData Return Value + + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton fail= ed +**/ +EFI_STATUS +GbeMdiRead ( + IN UINT32 GbeBar, + IN UINT32 PhyAddress, + IN UINT32 PhyRegister, + OUT UINT16 *ReadData + ); + +/** + Perform MDI write. + + @param [in] GbeBar GbE MMIO space + @param [in] PhyAddress Phy Address General - 02 or Specific - 01 + @param [in] PhyRegister Phy Register + @param [in] WriteData Value to write in lower 16bits. + + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton fail= ed +**/ +EFI_STATUS +GbeMdiWrite ( + IN UINT32 GbeBar, + IN UINT32 PhyAddress, + IN UINT32 PhyRegister, + IN UINT32 WriteData + ); + +/** + Gets Phy Revision and Model Number + from PHY IDENTIFIER register 2 (offset 3) + + @param [in] GbeBar GbE MMIO space + @param [out] LanPhyRevision Return Value + + @return EFI_STATUS + @return EFI_INVALID_PARAMETER When GbeBar is incorrect +**/ +EFI_STATUS +GbeMdiGetLanPhyRevision ( + IN UINT32 GbeBar, + OUT UINT16 *LanPhyRevision + ); + +#endif // _GBE_MDI_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h new file mode 100644 index 0000000000..25def24fca --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h @@ -0,0 +1,788 @@ +/** @file + Header file for GpioLib. + All function in this library is available for PEI, DXE, and SMM + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_LIB_H_ +#define _GPIO_LIB_H_ + +#include + +#define GPIO_NAME_LENGTH_MAX 32 + +typedef struct { + GPIO_PAD GpioPad; + GPIO_CONFIG GpioConfig; +} GPIO_INIT_CONFIG; + +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG = structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware def= ault values. + Separate fields could be set to hardware default if it does not matter, = except + GpioPad and PadMode. + Function will work in most efficient way if pads which belong to the sam= e group are + placed in adjacent records of the table. + Although function can enable pads for Native mode, such programming is d= one + by reference code when enabling related silicon feature. + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ); + +// +// Functions for setting/getting multiple GpioPad settings +// + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ); + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ); + +// +// Functions for setting/getting single GpioPad properties +// + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ); + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ); + +/** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ); + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ); + +/** + This procedure will get GPIO pad input inversion value + + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ); + +/** + This procedure will set GPIO interrupt settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ); + +/** + This procedure will set GPIO electrical settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ); + +/** + This procedure will set GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ); + +/** + This procedure will get GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ); + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ); + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ); + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ); + +/// +/// Possible values of Pad Ownership +/// If Pad is not under Host ownership then GPIO registers +/// are not accessible by host (e.g. BIOS) and reading them +/// will return 0xFFs. +/// +typedef enum { + GpioPadOwnHost =3D 0x0, + GpioPadOwnCsme =3D 0x1, + GpioPadOwnIsh =3D 0x2, +} GPIO_PAD_OWN; + +/** + This procedure will get Gpio Pad Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ); + +/** + This procedure will check state of Pad Config Lock for pads within one g= roup + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ); + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ); + +/** + This procedure will check state of Pad Config Tx Lock for pads within on= e group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ); + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ); + +/** + This procedure will clear PadCfgLock for selected pads within one group. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ); + +/** + This procedure will clear PadCfgLock for selected pad. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ); + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioLockPadCfg ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will clear PadCfgLockTx for selected pads within one grou= p. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ); + +/** + This procedure will clear PadCfgLockTx for selected pad. + Unlocking a pad will cause an SMI (if enabled) + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ); + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get Group to GPE mapping. + It will assume that only first 32 pads can be mapped to GPE. + To handle cases where groups have more than 32 pads and higher part of g= roup + can be mapped please refer to GpioGetGroupDwToGpeDwX() + + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ); + +/** + This procedure will get Group to GPE mapping. If group has more than 32 = bits + it is possible to map only single DW of pins (e.g. 0-31, 32-63) because + ACPI GPE_DWx register is 32 bits large. + + @param[out] GroupToGpeDw0 GPIO group mapped to GPE_DW0 + @param[out] GroupDwForGpeDw0 DW of pins mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group mapped to GPE_DW1 + @param[out] GroupDwForGpeDw1 DW of pins mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group mapped to GPE_DW2 + @param[out] GroupDwForGpeDw2 DW of pins mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupDwToGpeDwX ( + OUT GPIO_GROUP *GroupToGpeDw0, + OUT UINT32 *GroupDwForGpeDw0, + OUT GPIO_GROUP *GroupToGpeDw1, + OUT UINT32 *GroupDwForGpeDw1, + OUT GPIO_GROUP *GroupToGpeDw2, + OUT UINT32 *GroupDwForGpeDw2 + ); + +/** + This procedure will set Group to GPE mapping. + It will assume that only first 32 pads can be mapped to GPE. + To handle cases where groups have more than 32 pads and higher part of g= roup + can be mapped please refer to GpioSetGroupDwToGpeDwX() + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ); + +/** + This procedure will set Group to GPE mapping. If group has more than 32 = bits + it is possible to map only single DW of pins (e.g. 0-31, 32-63) because + ACPI GPE_DWx register is 32 bits large. + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupDwForGpeDw0 DW of pins to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupDwForGpeDw1 DW of pins to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + @param[in] GroupDwForGpeDw2 DW of pins to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupDwToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN UINT32 GroupDwForGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN UINT32 GroupDwForGpeDw1, + IN GPIO_GROUP GroupToGpeDw2, + IN UINT32 GroupDwForGpeDw2 + ); + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (Gpi= oSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Pu= rpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others group= s will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected = GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to = 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If= it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_= GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ); + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used by Smi Dispatcher and will clear + all GPI SMI Status bits + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + VOID + ); + +/** + This procedure is used to disable all GPI SMI + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + VOID + ); + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ); + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier = architecture + + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN GPIO_PAD GpioPad, + OUT UINT32* Data + ); + +/** + This procedure is used to lock all GPIO pads except the ones + which were requested during their configuration to be left unlocked. + This function must be called before BIOS_DONE - before POSTBOOT_SAI is e= nabled. + FSP - call this function from wrapper before transition to FSP-S + UEFI/EDK - call this function before EndOfPei event + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPads ( + VOID + ); + +/** + Generates GPIO name from GpioPad + + @param[in] GpioPad GpioPad + @param[out] GpioNameBuffer Caller allocated buffer for GPIO name of= GPIO_NAME_LENGTH_MAX size + @param[in] GpioNameBufferSize Size of the buffer + + @retval CHAR8* Pointer to the GPIO name +**/ +CHAR8* +GpioGetPadName ( + IN GPIO_PAD GpioPad, + OUT CHAR8* GpioNameBuffer, + IN UINT32 GpioNameBufferSize + ); + +#endif // _GPIO_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNat= iveLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativ= eLib.h new file mode 100644 index 0000000000..9956c60dd5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioNativeLib.h @@ -0,0 +1,166 @@ +/** @file + Header file for GpioLib for native and Si specific usage. + All function in this library is available for PEI, DXE, and SMM, + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_NATIVE_LIB_H_ +#define _GPIO_NATIVE_LIB_H_ + +#include + +/** + This procedure will get number of pads for certain GPIO group + + @param[in] Group GPIO group number + + @retval Value Pad number for group + If illegal group number then return 0 +**/ +UINT32 +GpioGetPadPerGroup ( + IN GPIO_GROUP Group + ); + +/** + This procedure will get number of groups + + @param[in] none + + @retval Value Group number +**/ +UINT32 +GpioGetNumberOfGroups ( + VOID + ); +/** + This procedure will get lowest group + + @param[in] none + + @retval Value Lowest Group +**/ +GPIO_GROUP +GpioGetLowestGroup ( + VOID + ); + +/** + This procedure will get highest group + + @param[in] none + + @retval Value Highest Group +**/ +GPIO_GROUP +GpioGetHighestGroup ( + VOID + ); + +/** + This procedure will get group + + @param[in] GpioPad Gpio Pad + + @retval Value Group +**/ +GPIO_GROUP +GpioGetGroupFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from GpioPad + + @param[in] GpioPad Gpio Pad + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get group index (0 based) from group + + @param[in] GpioGroup Gpio Group + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGroup ( + IN GPIO_GROUP GpioGroup + ); + +/** + This procedure will get group from group index (0 based) + + @param[in] GroupIndex Group Index + + @retval GpioGroup Gpio Group +**/ +GPIO_GROUP +GpioGetGroupFromGroupIndex ( + IN UINT32 GroupIndex + ); + +/** + This procedure will get pad number (0 based) from Gpio Pad + + @param[in] GpioPad Gpio Pad + + @retval Value Pad Number +**/ +UINT32 +GpioGetPadNumberFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will return GpioPad from Group and PadNumber + + @param[in] Group GPIO group + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupAndPadNumber ( + IN GPIO_GROUP Group, + IN UINT32 PadNumber + ); + +/** + This procedure will return GpioPad from GroupIndex and PadNumber + + @param[in] GroupIndex GPIO GroupIndex + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupIndexAndPadNumber ( + IN UINT32 GroupIndex, + IN UINT32 PadNumber + ); + +/** + This function checks if SATA GP pin is enabled + + @param[in] SataCtrlIndex SATA Controller Index + @param[in] SataPort SATA port number + + @retval TRUE SATA GPx is enabled (pad is in required = native mode) + FALSE SATA GPx is not enabled +**/ +BOOLEAN +GpioIsSataGpEnabled ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort + ); + +#endif // _GPIO_NATIVE_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLi= b.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h new file mode 100644 index 0000000000..6ef0d08774 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/OcWdtLib.h @@ -0,0 +1,33 @@ +/** @file + Header file for OC WDT Library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _OC_WDT_LIB_H_ +#define _OC_WDT_LIB_H_ + +/** + Check for unexpected reset. + If there was an unexpected reset, enforces WDT expiration. + Stops watchdog. +**/ +VOID +OcWdtResetCheck ( + VOID + ); + +/** + This function install WDT PPI + + @retval EFI_STATUS Results of the installation of the WDT PPI +**/ +EFI_STATUS +EFIAPI +OcWdtInit ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycl= eDecodingLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/Pch= CycleDecodingLib.h new file mode 100644 index 0000000000..7b6c82d390 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchCycleDecodi= ngLib.h @@ -0,0 +1,371 @@ +/** @file + Header file for PchCycleDecodingLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_CYCLE_DECODING_LIB_H_ +#define _PCH_CYCLE_DECODING_LIB_H_ + +/** + Set PCH TCO base address. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. set Smbus PCI offset 54h [8] to enable TCO base address. + 2. program Smbus PCI offset 50h [15:5] to TCO base address. + 3. set Smbus PCI offset 54h [8] to enable TCO base address. + 4. program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [Smbus PCI of= fset 50h[15:5], 1]. + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +PchTcoBaseSet ( + IN UINT16 Address + ); + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +PchTcoBaseGet ( + OUT UINT16 *Address + ); + +/// +/// structure of LPC general IO range register +/// It contains base address, address mask, and enable status. +/// +typedef struct { + UINT32 BaseAddr :16; + UINT32 Length :15; + UINT32 Enable : 1; +} PCH_LPC_GEN_IO_RANGE; + +#define PCH_LPC_GEN_IO_RANGE_MAX 4 +#define ESPI_CS1_GEN_IO_RANGE_MAX 1 +#define PCH_H_ESPI_GEN_IO_RANGE_MAX PCH_LPC_GEN_IO_RANGE_MAX // @depr= ecated. Keep it here for backward compatibility. + +/// +/// structure of LPC general IO range register list +/// It lists all LPC general IO ran registers supported by PCH. +/// +typedef struct { + PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX]; +} PCH_LPC_GEN_IO_RANGE_LIST; + +/** + Set PCH LPC/eSPI generic IO range. + For generic IO range, the base address must align to 4 and less than 0xF= FFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length alig= ned. + This function basically checks the address and length, which should not = overlap with all other generic ranges. + If no more generic range register available, it returns out of resource = error. + This cycle decoding is also required on DMI side + Some IO ranges below 0x100 have fixed target. The target might be ITSS,R= TC,LPC,PMC or terminated inside P2SB + but all predefined and can't be changed. IO range below 0x100 will be re= jected in this function except below ranges: + 0x00-0x1F, + 0x44-0x4B, + 0x54-0x5F, + 0x68-0x6F, + 0x80-0x8F, + 0xC0-0xFF + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range in DMI + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + ); + +/** + Set PCH eSPI CS1# generic IO range decoding. + For generic IO range, the base address must align to 4 and less than 0xF= FFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length alig= ned. + This function basically checks the address and length, which should not = overlap with all other generic ranges. + If no more generic range register available, it returns out of resource = error. + This cycle decoding is also required on DMI side + Some IO ranges below 0x100 have fixed target. The target might be ITSS,R= TC,LPC,PMC or terminated inside P2SB + but all predefined and can't be changed. IO range below 0x100 will be re= jected in this function except below ranges: + 0x00-0x1F, + 0x44-0x4B, + 0x54-0x5F, + 0x68-0x6F, + 0x80-0x8F, + 0xC0-0xFF + Steps of programming generic IO range: + 1. Program eSPI PCI Offset A4h (eSPI CS1#) of Mask, Address, and Enable. + 2. Program eSPI Generic IO Range in DMI + + @param[in] Address Address for generic IO range decod= ing. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +PchEspiCs1GenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + ); + +/** + Get PCH LPC/eSPI generic IO range list. + This function returns a list of base address, length, and enable for all= LPC/eSPI generic IO range registers. + + @param[out] LpcGenIoRangeList Return all LPC/eSPI generic IO ran= ge register status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +PchLpcGenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + ); + +/** + Get PCH eSPI CS1# generic IO range list. + This function returns a list of base address, length, and enable for all= eSPI CS1# generic IO range registers. + + @param[out] GenIoRangeList eSPI generic IO range registers. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +PchEspiCs1GenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList + ); + +/** + Set PCH LPC/eSPI memory range decoding. + This cycle decoding is required to be set on DMI side + Programming steps: + 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding firs= t before changing base address. + 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1]. + 3. Program LPC Memory Range in DMI + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcMemRangeSet ( + IN UINT32 Address + ); + +/** + Set PCH eSPI CS1# memory range decoding. + This cycle decoding is required to be set on DMI side + Programming steps: + 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory = decoding first before changing base address. + 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1]. + 3. Program eSPI Memory Range in DMI + + @param[in] Address Address for memory for decoding. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +PchEspiCs1MemRangeSet ( + IN UINT32 Address + ); + +/** + @deprecated. Keep this for backward compatibility. + It's replaced by PchEspiCs1MemRangeSet. +**/ +EFI_STATUS +PchEspiMemRange2Set ( + IN UINT32 Address + ); + +/** + Get PCH LPC/eSPI memory range decoding address. + + @param[out] Address Address of LPC/eSPI memory decodin= g base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +PchLpcMemRangeGet ( + OUT UINT32 *Address + ); + +/** + Get PCH eSPI CS1# memory range decoding address. + + @param[out] Address Address of eSPI CS1# memory decodi= ng base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +PchEspiCs1MemRangeGet ( + OUT UINT32 *Address + ); + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify = SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDe= codeEnable. + 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same= value programmed in LPC/eSPI or SPI PCI Offset D8h. + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ); + +/** + Set PCH LPC IO decode ranges. + Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value = programmed in LPC offset 80h. + Please check EDS for detail of Lpc IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ); + +/** + Set PCH LPC and eSPI CS0# IO enable decoding. + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offse= t 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtract= ive agent for handling. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit setting= s. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + ); + +/** + Set PCH eSPI CS1# IO enable decoding. + Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0= h (eSPI CS1#). + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field + in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive = agent for handling. + Please check EDS for detail of eSPI IO decode ranges bit definition. + + @param[in] IoEnableDecoding eSPI IO enable decoding bit settin= gs. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMI configuration is locked +**/ +EFI_STATUS +PchEspiCs1IoEnableDecodingSet ( + IN UINT16 IoEnableDecoding + ); + +/** + Set PCH IO port 80h cycle decoding to PCIE root port. + System BIOS is likely to do this very soon after reset before PCI bus en= umeration, it must ensure that + the IO Base Address field (PCIe:1Ch[7:4]) contains a value greater than = the IO Limit field (PCIe:1Ch[15:12]) + before setting the IOSE bit. Otherwise the bridge will positively decode= IO range 000h - FFFh by its default + IO range values. + This cycle decoding is allowed to set when DMIC.SRL is 0. + Programming steps: + 1. Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID = of RP. + 2. Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. Use byte = write on GCS+1 and leave the BILD bit which is RWO. + 3. Program IOSE bit of PCIE:Reg04h[0] to '1' for PCH to send such IO cy= cles to PCIe bus for subtractive decoding. + + @param[in] RpPhyNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoPort80DecodeSet ( + IN UINTN RpPhyNumber + ); + +/** + Get IO APIC registers base address. + + @param[out] IoApicBase Buffer of IO APIC register address + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoApicBaseGet ( + OUT UINT32 *IoApicBase + ); + +/** + Get HPET base address. + This function will be unavailable after P2SB is hidden by PSF. + + @param[out] HpetBase Buffer of HPET base address + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchHpetBaseGet ( + OUT UINT32 *HpetBase + ); + +#endif // _PCH_CYCLE_DECODING_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspi= Lib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h new file mode 100644 index 0000000000..c1d3c50ead --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchEspiLib.h @@ -0,0 +1,141 @@ +/** @file + Header file for PchEspiLib. + All function in this library is available for PEI, DXE, and SMM, + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_ESPI_LIB_H_ +#define _PCH_ESPI_LIB_H_ + +/** + Checks if there's second slave connected under CS#1 + + @retval TRUE There's second slave + @retval FALSE There's no second slave +**/ +BOOLEAN +IsEspiSecondSlaveSupported ( + VOID + ); + +/** + Checks in slave General Capabilities register if it supports channel wit= h requested number + + @param[in] SlaveId Id of slave to check + @param[in] ChannelNumber Number of channel of which to check + + @retval TRUE Channel with requested number is supported by slave de= vice + @retval FALSE Channel with requested number is not supported by slav= e device +**/ +BOOLEAN +IsEspiSlaveChannelSupported ( + UINT8 SlaveId, + UINT8 ChannelNumber + ); + +/** + Is eSPI enabled in strap. + + @retval TRUE Espi is enabled in strap + @retval FALSE Espi is disabled in strap +**/ +BOOLEAN +IsEspiEnabled ( + VOID + ); + +/** + Get configuration from eSPI slave + + @param[in] SlaveId eSPI slave ID + @param[in] SlaveAddress Slave Configuration Register Address + @param[out] OutData Configuration data read + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PchLp + @retval EFI_INVALID_PARAMETER Slave configuration register address excee= d maximum allowed + @retval EFI_INVALID_PARAMETER Slave configuration register address is no= t DWord aligned + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +EFI_STATUS +PchEspiSlaveGetConfig ( + IN UINT32 SlaveId, + IN UINT32 SlaveAddress, + OUT UINT32 *OutData + ); + +/** + Set eSPI slave configuration + + Note: A Set_Configuration must always be followed by a Get_Configuration= in order to ensure + that the internal state of the eSPI-MC is consistent with the Slave's re= gister settings. + + @param[in] SlaveId eSPI slave ID + @param[in] SlaveAddress Slave Configuration Register Address + @param[in] InData Configuration data to write + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PchLp + @retval EFI_INVALID_PARAMETER Slave configuration register address excee= d maximum allowed + @retval EFI_INVALID_PARAMETER Slave configuration register address is no= t DWord aligned + @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to 0x7= FF has been locked + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +EFI_STATUS +PchEspiSlaveSetConfig ( + IN UINT32 SlaveId, + IN UINT32 SlaveAddress, + IN UINT32 InData + ); + +/** + Get status from eSPI slave + + @param[in] SlaveId eSPI slave ID + @param[out] OutData Configuration data read + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PchLp + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +EFI_STATUS +PchEspiSlaveGetStatus ( + IN UINT32 SlaveId, + OUT UINT16 *OutData + ); + +/** + eSPI slave in-band reset + + @param[in] SlaveId eSPI slave ID + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PchLp + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +EFI_STATUS +PchEspiSlaveInBandReset ( + IN UINT32 SlaveId + ); + +/** + eSPI Slave channel reset helper function + + @param[in] SlaveId eSPI slave ID + @param[in] ChannelNumber Number of channel to reset + + @retval EFI_SUCCESS Operation succeeded + @retval EFI_UNSUPPORTED Slave doesn't support that channel or inva= lid number specified + @retval EFI_TIMEOUT Operation has timeouted +**/ +EFI_STATUS +PchEspiSlaveChannelReset ( + IN UINT8 SlaveId, + IN UINT8 ChannelNumber + ); + +#endif // _PEI_DXE_SMM_PCH_ESPI_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeL= ib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h new file mode 100644 index 0000000000..2a4dc986f4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchGbeLib.h @@ -0,0 +1,36 @@ +/** @file + Header file for PchGbeLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_GBE_LIB_H_ +#define _PCH_GBE_LIB_H_ + +/** + Check whether GbE region is valid + Check SPI region directly since GBE might be disabled in SW. + + @retval TRUE Gbe Region is valid + @retval FALSE Gbe Region is invalid +**/ +BOOLEAN +PchIsGbeRegionValid ( + VOID + ); + + +/** + Check whether LAN controller is enabled in the platform. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbePresent ( + VOID + ); + +#endif // _PCH_GBE_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsio= Lib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h new file mode 100644 index 0000000000..4f93f44120 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchHsioLib.h @@ -0,0 +1,109 @@ +/** @file + Header file for PchHsioLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HSIO_LIB_H_ +#define _PCH_HSIO_LIB_H_ + +/** + Represents HSIO lane +**/ +typedef struct { + UINT8 Index; ///< Lane index + UINT8 Pid; ///< Sideband ID + UINT16 Base; ///< Sideband base address +} HSIO_LANE; + +/** + The function returns the Port Id and lane owner for the specified lane + + @param[in] PhyMode Phymode that needs to be checked + @param[out] Pid Common Lane End Point ID + @param[out] LaneOwner Lane Owner + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid lane number +**/ +EFI_STATUS +EFIAPI +PchGetLaneInfo ( + IN UINT32 LaneNum, + OUT UINT8 *PortId, + OUT UINT8 *LaneOwner + ); + +/** + Get HSIO lane representation needed to perform any operation on the lane. + + @param[in] LaneIndex Number of the HSIO lane + @param[out] HsioLane HSIO lane representation +**/ +VOID +HsioGetLane ( + IN UINT8 LaneIndex, + OUT HSIO_LANE *HsioLane + ); + +/** + Determine the lane number of a specified port + + @param[in] PcieLaneIndex PCIE Root Port Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetPcieLaneNum ( + UINT32 PcieLaneIndex, + UINT8 *LaneNum + ); + +/** + Determine the lane number of a specified port + + @param[in] SataLaneIndex Sata Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetSataLaneNum ( + UINT32 SataLaneIndex, + UINT8 *LaneNum + ); + +/** + Determine the lane number of a specified port + + @param[in] Usb3LaneIndex USB3 Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetUsb3LaneNum ( + UINT32 Usb3LaneIndex, + UINT8 *LaneNum + ); + +/** + Determine the lane number of a specified port + + @param[out] LaneNum GBE Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetGbeLaneNum ( + UINT8 *LaneNum + ); + +#endif // _PCH_HSIO_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfo= Lib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h new file mode 100644 index 0000000000..94a8204fa5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchInfoLib.h @@ -0,0 +1,407 @@ +/** @file + Header file for PchInfoLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_INFO_LIB_H_ +#define _PCH_INFO_LIB_H_ + +#include + +typedef UINT8 PCH_STEPPING; +#define PCH_A0 0x00 +#define PCH_A1 0x01 +#define PCH_B0 0x10 +#define PCH_B1 0x11 +#define PCH_C0 0x20 +#define PCH_C1 0x21 +#define PCH_D0 0x30 +#define PCH_D1 0x31 +#define PCH_STEPPING_MAX 0xFF + +typedef UINT8 PCH_SERIES; +#define PCH_H 1 +#define PCH_LP 2 +#define PCH_SERVER 0x80 +#define PCH_UNKNOWN_SERIES 0xFF + +typedef UINT8 PCH_GENERATION; +#define CNL_PCH 3 +#define CDF_PCH 0x80 +#define PCH_UNKNOWN_GENERATION 0xFF + +typedef enum { + RstUnsupported =3D 0, + RstPremium, + RstOptane, + RstMaxMode +} RST_MODE; + +/** + Return LPC Device Id + + @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID +**/ +UINT16 +PchGetLpcDid ( + VOID + ); + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +PchStepping ( + VOID + ); + +/** + Determine if PCH is supported + + @retval TRUE PCH is supported + @retval FALSE PCH is not supported +**/ +BOOLEAN +IsPchSupported ( + VOID + ); + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeries ( + VOID + ); + +/** + Check if this is PCH LP series + + @retval TRUE It's PCH LP series + @retval FALSE It's not PCH LP series +**/ +BOOLEAN +IsPchLp ( + VOID + ); + +/** + Check if this is PCH H series + + @retval TRUE It's PCH H series + @retval FALSE It's not PCH H series +**/ +BOOLEAN +IsPchH ( + VOID + ); + +/** + Check if this is Server PCH + + @retval TRUE It's a Server PCH + @retval FALSE It's not a Server PCH +**/ +BOOLEAN +IsPchServer ( + VOID + ); + +/** + Return Pch Generation + + @retval PCH_GENERATION Pch Generation +**/ +PCH_GENERATION +PchGeneration ( + VOID + ); + +/** + Check if this is CDF PCH generation + + @retval TRUE It's CDF PCH + @retval FALSE It's not CDF PCH +**/ +BOOLEAN +IsCdfPch ( + VOID + ); + +/** + @retval TRUE It's CNL PCH + @retval FALSE It's not CNL PCH +**/ +BOOLEAN +IsCnlPch ( + VOID + ); + +/** + Check if this is Server SKU + + @retval TRUE It's PCH Server SKU + @retval FALSE It's not PCH Server SKU +**/ +BOOLEAN +IsPchServerSku ( + VOID + ); + +/** + Get Pch Maximum Pcie Root Port Number + + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number +**/ +UINT8 +GetPchMaxPciePortNum ( + VOID + ); + +/** + Get Pch Maximum Pcie Controller Number + + @retval Pch Maximum Pcie Controller Number +**/ +UINT8 +GetPchMaxPcieControllerNum ( + VOID + ); + +/** + Get Pch Maximum Pcie Clock Number + + @retval Pch Maximum Pcie Clock Number +**/ +UINT8 +GetPchMaxPcieClockNum ( + VOID + ); + +/** + Get Pch Usb2 Maximum Physical Port Number + + @retval Pch Usb2 Maximum Physical Port Number +**/ +UINT8 +GetPchUsb2MaxPhysicalPortNum ( + VOID + ); + +/** + Get Pch Maximum Usb2 Port Number of XHCI Controller + + @retval Pch Maximum Usb2 Port Number of XHCI Controller +**/ +UINT8 +GetPchXhciMaxUsb2PortNum ( + VOID + ); + +/** + Get Pch Maximum Usb3 Port Number of XHCI Controller + + @retval Pch Maximum Usb3 Port Number of XHCI Controller +**/ +UINT8 +GetPchXhciMaxUsb3PortNum ( + VOID + ); + +/** + Get Pch Maximum Serial IO controllers number + + @retval Pch Maximum Serial IO controllers number +**/ +UINT8 +GetPchMaxSerialIoControllersNum ( + VOID + ); + +/** + Get Pch Maximum Serial IO I2C controllers number + + @retval Pch Maximum Serial IO I2C controllers number +**/ +UINT8 +GetPchMaxSerialIoI2cControllersNum ( + VOID + ); + +/** + Get Pch Maximum Serial IO SPI controllers number + + @retval Pch Maximum Serial IO SPI controllers number +**/ +UINT8 +GetPchMaxSerialIoSpiControllersNum ( + VOID + ); + +/** + Get Pch Maximum Serial IO UART controllers number + + @retval Pch Maximum Serial IO UART controllers number +**/ +UINT8 +GetPchMaxSerialIoUartControllersNum ( + VOID + ); + +#define PCH_STEPPING_STR_LENGTH_MAX 3 + +/** + Get PCH stepping ASCII string. + Function determines major and minor stepping versions and writes them in= to a buffer. + The return string is zero terminated + + @param [out] Buffer Output buffer of string + @param [in] BufferSize Buffer size. + Must not be less then PCH_STEPPING= _STR_LENGTH_MAX + + @retval EFI_SUCCESS String copied successfully + @retval EFI_INVALID_PARAMETER The stepping is not supported, or = parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSteppingStr ( + OUT CHAR8 *Buffer, + IN UINT32 BufferSize + ); + +/** + Get PCH series ASCII string. + The return string is zero terminated. + + @retval Static ASCII string of PCH Series +**/ +CHAR8* +PchGetSeriesStr ( + ); + +/** + Get PCH Sku ASCII string + The return string is zero terminated. + + @retval Static ASCII string of PCH Sku +**/ +CHAR8* +PchGetSkuStr ( + VOID + ); + +/** + Check if this chipset supports eMMC controller + + @retval BOOLEAN TRUE if supported, FALSE otherwise +**/ +BOOLEAN +IsPchEmmcSupported ( + VOID + ); + +/** + Check if this chipset supports SD controller + + @retval BOOLEAN TRUE if supported, FALSE otherwise +**/ +BOOLEAN +IsPchSdCardSupported ( + VOID + ); + +/** + Check if this chipset supports UFS controller + + @retval BOOLEAN TRUE if supported, FALSE otherwise +**/ +BOOLEAN +IsPchUfsSupported ( + VOID + ); + +/** + Gets the maximum number of UFS controller supported by this chipset. + + @return Number of supported UFS controllers +**/ +UINT8 +PchGetMaxUfsNum ( + VOID + ); + +/** + Get RST mode supported by the silicon + + @retval RST_MODE RST mode supported by silicon +**/ +RST_MODE +PchGetSupportedRstMode ( + VOID + ); + +/** + Check whether integrated LAN controller is supported. + + @retval TRUE GbE is supported in PCH + @retval FALSE GbE is not supported by PCH +**/ +BOOLEAN +PchIsGbeSupported ( + VOID + ); + +/** + Check if given Display Audio Link T-Mode is supported + + @param[in] Tmode T-mode support to be checked + + @retval TRUE T-mode supported + @retval FALSE T-mode not supported +**/ +BOOLEAN +IsAudioIDispTmodeSupported ( + IN PCH_HDAUDIO_IDISP_TMODE Tmode + ); + +/** + Check if link between PCH and CPU is an P-DMI + + @retval TRUE P-DMI link + @retval FALSE Not an P-DMI link +**/ +BOOLEAN +IsPchWithPdmi ( + VOID + ); + +/** + Check if link between PCH and CPU is an OP-DMI + + @retval TRUE OP-DMI link + @retval FALSE Not an OP-DMI link +**/ +BOOLEAN +IsPchWithOpdmi ( + VOID + ); + +/** + Check if link between PCH and CPU is an F-DMI + + @retval TRUE F-DMI link + @retval FALSE Not an F-DMI link +**/ +BOOLEAN +IsPchWithFdmi ( + VOID + ); + +#endif // _PCH_INFO_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcie= RpLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpL= ib.h new file mode 100644 index 0000000000..7c26f6939e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcieRpLib.h @@ -0,0 +1,105 @@ +/** @file + Header file for PchPcieRpLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIERP_LIB_H_ +#define _PCH_PCIERP_LIB_H_ + +#define RST_PCIE_STORAGE_CR_1 0 +#define RST_PCIE_STORAGE_CR_2 1 +#define RST_PCIE_STORAGE_CR_3 2 +#define RST_PCIE_STORAGE_CR_INVALID 99 + +typedef struct { + UINT8 DevNum; + UINT8 Pid; + UINT8 RpNumBase; +} PCH_PCIE_CONTROLLER_INFO; + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port physical = Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device nu= mber. + @param[out] RpFun Return corresponding root port function = number. + + @retval EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ); + +/** + Get Root Port physical Number by Pch Pcie Root Port Device and Function = Number + + @param[in] RpDev Root port device number. + @param[in] RpFun Root port function number. + @param[out] RpNumber Return corresponding physical Root Por= t index (0-based) + + @retval EFI_SUCCESS Physical root port is retrieved + @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid + @retval EFI_UNSUPPORTED Root port device and function is not a= ssigned to any physical root port +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpNumber ( + IN UINTN RpDev, + IN UINTN RpFun, + OUT UINTN *RpNumber + ); + +/** + Gets pci segment base address of PCIe root port. + + @param RpIndex Root Port Index (0 based) + @return PCIe port base address. +**/ +UINT64 +PchPcieBase ( + IN UINT32 RpIndex + ); + +/** + Determines whether L0s is supported on current stepping. + + @return TRUE if L0s is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieL0sSupported ( + VOID + ); + +/** + Some early PCH steppings require Native ASPM to be disabled due to hardw= are issues: + - RxL0s exit causes recovery + - Disabling PCIe L0s capability disables L1 + Use this function to determine affected steppings. + + @return TRUE if Native ASPM is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieNativeAspmSupported ( + VOID + ); + +/** + Check the RST PCIe Storage Cycle Router number according to the root por= t number and PCH type + + @param[in] RootPortNum Root Port Number + + @return The RST PCIe Storage Cycle Router Number +**/ +UINT8 +RstGetCycleRouterNumber ( + IN UINT32 RootPortNum + ); + +#endif // _PCH_PCIERP_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrL= ib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h new file mode 100644 index 0000000000..2d57087c6b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPcrLib.h @@ -0,0 +1,226 @@ +/** @file + Header file for PchPcrLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCR_LIB_H_ +#define _PCH_PCR_LIB_H_ + +#include + +/// +/// Definition for PCR base address (defined in PchReservedResources.h) +/// +//#define PCH_PCR_BASE_ADDRESS 0xFD000000 +//#define PCH_PCR_MMIO_SIZE 0x01000000 +/** + Definition for PCR address + The PCR address is used to the PCR MMIO programming +**/ +#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | ((UINT8)(P= id) << 16) | (UINT16)(Offset)) + +/** + PCH PCR boot script accessing macro + Those macros are only available for DXE phase. +**/ +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \ + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), = Count, Buffer); \ + +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd= ) \ + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offse= t), DataOr, DataAnd); \ + +#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \ + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), B= itMask, BitValue, 1, 1); + +typedef UINT8 PCH_SBI_PID; + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT32 PCR register value. +**/ +UINT32 +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ); + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT16 PCR register value. +**/ +UINT16 +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ); + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT8 PCR register value +**/ +UINT8 +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter. + + @retval UINT32 Value written to register +**/ +UINT32 +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter. + + @retval UINT16 Value written to register +**/ +UINT16 +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT16 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter. + + @retval UINT8 Value written to register +**/ +UINT8 +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT8 InData + ); + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT32 Value written to register + +**/ +UINT32 +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Write PCR register and read back. + The read back ensures the PCR cycle is completed before next operation. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT32 Value read back from the register +**/ +UINT32 +PchPcrAndThenOr32WithReadback ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT16 Value written to register + +**/ +UINT16 +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ); + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT8 Value written to register + +**/ +UINT8 +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ); + +#endif // _PCH_PCR_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcL= ib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h new file mode 100644 index 0000000000..36a0adb56f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPmcLib.h @@ -0,0 +1,45 @@ +/** @file + Header file for PchPmcLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PMC_LIB_H_ +#define _PCH_PMC_LIB_H_ + +typedef enum { + WarmBoot =3D 1, + ColdBoot, + PwrFlr, + PwrFlrSys, + PwrFlrPch, + PchPmStatusMax +} PCH_PM_STATUS; + +/** + Query PCH to determine the Pm Status + + @param[in] PmStatus - The Pch Pm Status to be probed + + @retval Status TRUE if Status querried is Valid or FALSE if otherwise +**/ +BOOLEAN +GetPchPmStatus ( + PCH_PM_STATUS PmStatus + ); + +/** + Funtion to check if Battery lost or CMOS cleared. + + @reval TRUE Battery is always present. + @reval FALSE CMOS is cleared. +**/ +BOOLEAN +EFIAPI +PchIsRtcBatteryGood ( + VOID + ); + +#endif // _PCH_PMC_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPoli= cyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyL= ib.h new file mode 100644 index 0000000000..acd7a16e48 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchPolicyLib.h @@ -0,0 +1,114 @@ +/** @file + Prototype of the PeiPchPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PCH_POLICY_LIB_H_ +#define _PEI_PCH_POLICY_LIB_H_ + +#include + +/** + Print whole PCH_PREMEM_POLICY_PPI and serial out. + + @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance +**/ +VOID +EFIAPI +PchPreMemPrintPolicyPpi ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + Print whole SI_POLICY_PPI and serial out. + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +PchPrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Get PCH PREMEM config block table total size. + + @retval Size of PCH PREMEM config block ta= ble +**/ +UINT16 +EFIAPI +PchGetPreMemConfigBlockTotalSize ( + VOID + ); + +/** + Get PCH config block table total size. + + @retval Size of PCH config block table +**/ +UINT16 +EFIAPI +PchGetConfigBlockTotalSize ( + VOID + ); + +/** + PchAddPreMemConfigBlocks add all PCH config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add PCH config bloc= ks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +PchAddPreMemConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +/** + PchAddConfigBlocks add all PCH config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add PCH config bloc= ks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +PchAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +/** + Get Sata Config Policy + + @param[in] SiPolicy The RC Policy PPI instance + @param[in] SataCtrlIndex SATA controller index + + @retval SataConfig Pointer to Sata Config Policy +**/ +PCH_SATA_CONFIG * +GetPchSataConfig ( + IN SI_POLICY_PPI *SiPolicy, + IN UINT32 SataCtrlIndex + ); + +/** + Get Hsio Sata Pre Mem Config Policy + + @param[in] SiPolicy The RC Policy PPI instance + @param[in] SataCtrlIndex SATA controller index + + @retval Pointer to Hsio Sata Pre Mem Config Policy +**/ +PCH_HSIO_SATA_PREMEM_CONFIG * +GetPchHsioSataPreMemConfig ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy, + IN UINT32 SataCtrlIndex + ); + +#endif // _PEI_PCH_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchRese= tLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib= .h new file mode 100644 index 0000000000..ca2da4cfc1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchResetLib.h @@ -0,0 +1,24 @@ +/** @file + Header file for PCH RESET Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_LIB_H_ +#define _PCH_RESET_LIB_H_ + +/** + Initialize PCH Reset APIs + + @retval EFI_SUCCESS APIs are installed successfully + @retval EFI_OUT_OF_RESOURCES Can't allocate pool +**/ +EFI_STATUS +EFIAPI +PchInitializeReset ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiA= ccessLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiA= ccessLib.h new file mode 100644 index 0000000000..779aac2d2a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSbiAccessLi= b.h @@ -0,0 +1,116 @@ +/** @file + Header file for PchSbiAccessLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SBI_ACCESS_LIB_H_ +#define _PCH_SBI_ACCESS_LIB_H_ + +#include + +/** + PCH SBI opcode definitions +**/ +typedef enum { + MemoryRead =3D 0x0, + MemoryWrite =3D 0x1, + PciConfigRead =3D 0x4, + PciConfigWrite =3D 0x5, + PrivateControlRead =3D 0x6, + PrivateControlWrite =3D 0x7, + GpioLockUnlock =3D 0x13 +} PCH_SBI_OPCODE; + +/** + PCH SBI response status definitions +**/ +typedef enum { + SBI_SUCCESSFUL =3D 0, + SBI_UNSUCCESSFUL =3D 1, + SBI_POWERDOWN =3D 2, + SBI_MIXED =3D 3, + SBI_INVALID_RESPONSE +} PCH_SBI_RESPONSE; + +/** + Execute PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiE= xecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. = If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be= checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would = provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + @retval EFI_TIMEOUT Timeout while waiting for response +**/ +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiE= xecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. = If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be= checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would = provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + @retval EFI_TIMEOUT Timeout while waiting for response +**/ +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ); + +#endif // _PCH_SBI_ACCESS_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSeri= alIoLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSeria= lIoLib.h new file mode 100644 index 0000000000..4962c67a7c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoLib= .h @@ -0,0 +1,240 @@ +/** @file + Header file for PCH Serial IO Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SERIAL_IO_LIB_H_ +#define _PCH_SERIAL_IO_LIB_H_ + +typedef enum { + PchSerialIoIndexI2C0, + PchSerialIoIndexI2C1, + PchSerialIoIndexI2C2, + PchSerialIoIndexI2C3, + PchSerialIoIndexI2C4, + PchSerialIoIndexI2C5, + PchSerialIoIndexSpi0, + PchSerialIoIndexSpi1, + PchSerialIoIndexSpi2, + PchSerialIoIndexUart0, + PchSerialIoIndexUart1, + PchSerialIoIndexUart2, + PchSerialIoIndexMax +} PCH_SERIAL_IO_CONTROLLER; + +typedef enum { + PchSerialIoDisabled, + PchSerialIoPci, + PchSerialIoAcpi, + PchSerialIoHidden +} PCH_SERIAL_IO_MODE; + +typedef enum { + SERIAL_IO_UNKNOWN =3D 0, + SERIAL_IO_I2C, + SERIAL_IO_SPI, + SERIAL_IO_UART +} PCH_SERIAL_IO_CONTROLLER_TYPE; + +enum PCH_LP_SERIAL_IO_CS_POLARITY { + PchSerialIoCsActiveLow =3D 0, + PchSerialIoCsActiveHigh =3D 1 +}; +enum PCH_LP_SERIAL_IO_HW_FLOW_CTRL { + PchSerialIoHwFlowCtrlDisabled =3D 0, + PchSerialIoHwFlowControlEnabled =3D 1 +}; + +#define SERIALIO_HID_LENGTH 8 // including null terminator +#define SERIALIO_UID_LENGTH 1 +#define SERIALIO_CID_LENGTH 1 +#define SERIALIO_TOTAL_ID_LENGTH SERIALIO_HID_LENGTH+SERIALIO_UID_LENGTH+S= ERIALIO_CID_LENGTH + +/** + Returns index of the last i2c controller + + @param[in] Number Number of SerialIo controller + + @retval Index of I2C controller +**/ +PCH_SERIAL_IO_CONTROLLER +GetMaxI2cNumber ( + VOID + ); + +/** + Returns string with AcpiHID assigned to selected SerialIo controller + + @param[in] Number Number of SerialIo controller + + @retval pointer to 8-byte string +**/ +CHAR8* +GetSerialIoAcpiHid ( + IN PCH_SERIAL_IO_CONTROLLER Number + ); + +/** + Checks if given Serial IO Controller Function equals 0 + + @param[in] SerialIoNumber Serial IO device + + @retval TRUE if SerialIO Function is equal= to 0 + FALSE if Function is higher then 0 +**/ +BOOLEAN +IsSerialIoFunctionZero ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Checks if Device with given PciDeviceId is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Numbe= r is not updated + + @param[in] PciDevId Device ID + @param[out] Number Number of SerialIo controller + + @retval TRUE Yes it is a SerialIo controller + @retval FALSE No it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoPciDevId ( + IN UINT16 PciDevId, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ); + +/** + Checks if Device with given AcpiHID string is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Numbe= r is not updated + + @param[in] AcpiHid String + @param[out] Number Number of SerialIo controller + + @retval TRUE yes it is a SerialIo controller + @retval FALSE no it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoAcpiHid ( + IN CHAR8 *AcpiHid, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ); + +/** + Configures Serial IO Controller + + @param[in] Controller Serial IO controller number + @param[in] DeviceMode Device operation mode + @param[in] PsfDisable Disable device at PSF level + + @retval None +**/ +VOID +ConfigureSerialIoController ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN BOOLEAN PsfDisable + ); + +/** + Returns Serial IO Controller Type I2C, SPI or UART + + @param[in] Number Number of SerialIo controller + + @retval I2C, SPI or UART + @retval UNKNOWN - in case if undefined controller +**/ +PCH_SERIAL_IO_CONTROLLER_TYPE +GetSerialIoControllerType ( + IN PCH_SERIAL_IO_CONTROLLER Controller + ); + +/** + Finds PCI Device Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoNumber Serial IO device + + @retval SerialIo device number +**/ +UINT8 +GetSerialIoDeviceNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds PCI Function Number of SerialIo devices. + SerialIo devices' BDF is configurable + + @param[in] SerialIoNumber Serial IO device + + @retval SerialIo funciton number +**/ +UINT8 +GetSerialIoFunctionNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ); + +/** + Finds BAR values of SerialIo devices. + SerialIo devices can be configured to not appear on PCI so traditional m= ethod of reading BAR might not work. + + @param[in] SerialIoDevice Serial IO device + @param[in] BarNumber 0=3DBAR0, 1=3DBAR1 + + @retval SerialIo Bar value +**/ +UINTN +FindSerialIoBar ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice, + IN UINT8 BarNumber + ); + +/** + Checks if given device corresponds to any of LPSS Devices + + @param[in] DeviceNumber device number + @param[in] FunctionNumber function number + + @retval TRUE if SerialIO Device/Function N= umber is equal to any of LPSS devices + FALSE Device/Function is not in Se= rial IO scope +**/ +BOOLEAN +IsSerialIoDevice ( + IN UINT8 DeviceNumber, + IN UINT8 FunctionNumber + ); + +/** + Checks if given Serial IO Controller is enabled or not + + @param[in] DeviceNumber device number + @param[in] FunctionNumber function number + + @retval TRUE TRUE if given serial io device is = enabled. + @retval FALSE FALSE if given serial io device is= disabled. +**/ +BOOLEAN +IsSerialIoDeviceEnabled ( + IN UINT8 DeviceNumber, + IN UINT8 FunctionNumber + ); + +/** + Gets Pci Config control offset + + @param[in] DeviceNumber device number + @param[in] FunctionNumber function number + + @retval CfgCtrAddr Offset of Pci config control + 0 if Device and Function do not co= rrespond to Serial IO +**/ +UINT16 +GetSerialIoConfigControlOffset ( + IN UINT8 DeviceNumber, + IN UINT8 FunctionNumber + ); + +#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSeri= alIoUartLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchS= erialIoUartLib.h new file mode 100644 index 0000000000..f97051e97c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSerialIoUar= tLib.h @@ -0,0 +1,111 @@ +/** @file + Header file for PCH Serial IO UART Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SERIAL_IO_UART_LIB_H_ +#define _PCH_SERIAL_IO_UART_LIB_H_ + +typedef enum { + AccessMode8bit, + AccessMode32bit +} UART_ACCESS_MODE; + +/** + Returns UART's currently active access mode, 8 or 32 bit + + @param[in] MmioBase Base address of UART MMIO space + + @retval AccessMode8bit + @retval AccessMode32bit +**/ +UART_ACCESS_MODE +DetectAccessMode ( + IN UINTN MmioBase + ); + +/** + Initialize selected SerialIo UART. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] FifoEnable When TRUE, enables 64-byte FIFOs. + @param[in] BaudRate Baud rate. + @param[in] LineControl Data length, parity, stop bits. + @param[in] HardwareFlowControl Automated hardware flow control. If TRU= E, hardware automatically checks CTS when sending data, and sets RTS when r= eceiving data. +**/ +VOID +EFIAPI +PchSerialIoUartInit ( + IN UINT8 UartNumber, + IN BOOLEAN FifoEnable, + IN UINT32 BaudRate, + IN UINT8 LineControl, + IN BOOLEAN HardwareFlowControl + ); + + +/** + Write data to serial device. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[in] Buffer Point of data buffer which need to be write= d. + @param[in] NumberOfBytes Number of output bytes which are cached in = Buffer. + + @retval Actual number of bytes writed to serial device. +**/ +UINTN +EFIAPI +PchSerialIoUartOut ( + IN UINT8 UartNumber, + IN UINT8 *Buffer, + IN UINTN NumberOfBytes +); + +/* + Read data from serial device and save the datas in buffer. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + @param[out] Buffer Point of data buffer which need to be = writed. + @param[in] NumberOfBytes Number of output bytes which are cache= d in Buffer. + @param[in] WaitUntilBufferFull When TRUE, function waits until whole = buffer is filled. When FALSE, function returns as soon as no new characters= are available. + + @retval Actual number of bytes raed from serial dev= ice. + +**/ +UINTN +EFIAPI +PchSerialIoUartIn ( + IN UINT8 UartNumber, + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes, + IN BOOLEAN WaitUntilBufferFull +); + +/** + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is= returned. + If there is no data waiting to be read from the serial device, then FALS= E is returned. + + @param[in] UartNumber Selects Serial IO UART device (0-2) + + @retval TRUE Data is waiting to be read from the serial devi= ce. + @retval FALSE There is no data waiting to be read from the se= rial device. + +**/ +BOOLEAN +EFIAPI +PchSerialIoUartPoll ( + IN UINT8 UartNumber + ); + + +#endif // _PEI_DXE_SMM_PCH_SERIAL_IO_UART_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmC= ontrolLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmm= ControlLib.h new file mode 100644 index 0000000000..34b9867c34 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchSmmControlL= ib.h @@ -0,0 +1,23 @@ +/** @file + Header file for SMM Control PEI Library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SMM_CONTROL_LIB_H_ +#define _PCH_SMM_CONTROL_LIB_H_ + +/** + This function install PEI SMM Control PPI + + @retval EFI_STATUS Results of the installation of the SMM Control PPI +**/ +EFI_STATUS +EFIAPI +PchSmmControlInit ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtC= ommonLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtC= ommonLib.h new file mode 100644 index 0000000000..69b9c1cdb7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PchWdtCommonLi= b.h @@ -0,0 +1,121 @@ +/** @file + Library that contains common parts of WdtPei and WdtDxe. Not a standalon= e module. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_WDT_COMMON_LIB_H_ +#define _PCH_WDT_COMMON_LIB_H_ + +extern UINT8 mAllowExpectedReset; + +/** + Reads LPC bridge to get Watchdog Timer address + + + @retval UINT32 Watchdog's address +**/ +UINT32 +WdtGetAddress ( + VOID + ); + +/** + Reloads WDT with new timeout value and starts it. Also sets Unexpected R= eset bit, which + causes the next reset to be treated as watchdog expiration - unless Allo= wKnownReset() + function was called too. + + @param[in] TimeoutValue Time in seconds before WDT times out. Su= pported range =3D 1 - 1024. + + @retval EFI_SUCCESS if everything's OK + @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong +**/ +EFI_STATUS +EFIAPI +WdtReloadAndStart ( + IN UINT32 TimeoutValue + ); + +/** + Disables WDT timer. + + +**/ +VOID +EFIAPI +WdtDisable ( + VOID + ); + +/** + Returns WDT failure status. + + + @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or= unexpected reset + @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise +**/ +UINT8 +EFIAPI +WdtCheckStatus ( + VOID + ); + +/** + Normally, each reboot performed while watchdog runs is considered a fail= ure. + This function allows platform to perform expected reboots with WDT runni= ng, + without being interpreted as failures. + In DXE phase, it is enough to call this function any time before reset. + In PEI phase, between calling this function and performing reset, Reload= AndStart() + must not be called. + + +**/ +VOID +EFIAPI +WdtAllowKnownReset ( + VOID + ); + +/** + Returns information if WDT coverage for the duration of BIOS execution + was requested by an OS application + + + @retval TRUE if WDT was requested + @retval FALSE if WDT was not requested +**/ +UINT8 +EFIAPI +IsWdtRequired ( + VOID + ); + +/** + Returns WDT enabled/disabled status. + + + @retval TRUE if WDT is enabled + @retval FALSE if WDT is disabled +**/ +UINT8 +EFIAPI +IsWdtEnabled ( + VOID + ); + +/** + Returns WDT locked status. + + + @retval TRUE if WDT is locked + @retval FALSE if WDT is unlocked +**/ +UINT8 +EFIAPI +IsWdtLocked ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.= h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h new file mode 100644 index 0000000000..f1a2600216 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/PmcLib.h @@ -0,0 +1,207 @@ +/** @file + Header file for PmcLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PMC_LIB_H_ +#define _PMC_LIB_H_ + +#pragma pack(1) + +typedef enum { + PmcNotASleepState, + PmcInS0State, + PmcS1SleepState, + PmcS2SleepState, + PmcS3SleepState, + PmcS4SleepState, + PmcS5SleepState, + PmcUndefinedState, +} PMC_SLEEP_STATE; + +typedef struct { + UINT32 Buf0; + UINT32 Buf1; + UINT32 Buf2; + UINT32 Buf3; +} PMC_IPC_COMMAND_BUFFER; + +#pragma pack() + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +PmcGetAcpiBase ( + VOID + ); + +/** + Get PCH PWRM base address. + + @retval Address Address of PWRM base address. +**/ +UINT32 +PmcGetPwrmBase ( + VOID + ); + +/** + This function checks if RTC Power Failure occurred by + reading RTC_PWR_FLR bit + + @retval RTC Power Failure state: TRUE - Battery is always present. + FALSE - CMOS is cleared. +**/ +BOOLEAN +PmcIsRtcBatteryGood ( + VOID + ); + +/** + This function checks if Power Failure occurred by + reading PWR_FLR bit + + @retval Power Failure state +**/ +BOOLEAN +PmcIsPowerFailureDetected ( + VOID + ); + +/** + This function checks if RTC Power Failure occurred by + reading SUS_PWR_FLR bit + + @retval SUS Power Failure state +**/ +BOOLEAN +PmcIsSusPowerFailureDetected ( + VOID + ); + +/** + This function clears Power Failure status (PWR_FLR) +**/ +VOID +PmcClearPowerFailureStatus ( + VOID + ); + +/** + This function clears Global Reset status (GBL_RST_STS) +**/ +VOID +PmcClearGlobalResetStatus ( + VOID + ); + +/** + This function clears Host Reset status (HOST_RST_STS) +**/ +VOID +PmcClearHostResetStatus ( + VOID + ); + +/** + This function clears SUS Power Failure status (SUS_PWR_FLR) +**/ +VOID +PmcClearSusPowerFailureStatus ( + VOID + ); + +/** + This function sets state to which platform will get after power is reapp= lied + + @param[in] PowerStateAfterG3 0: S0 state (boot) + 1: S5/S4 State +**/ +VOID +PmcSetPlatformStateAfterPowerFailure ( + IN UINT8 PowerStateAfterG3 + ); + +/** + This function enables Power Button SMI +**/ +VOID +PmcEnablePowerButtonSmi ( + VOID + ); + +/** + This function disables Power Button SMI +**/ +VOID +PmcDisablePowerButtonSmi ( + VOID + ); + +/** + This function reads PM Timer Count driven by 3.579545 MHz clock + + @retval PM Timer Count +**/ +UINT32 +PmcGetTimerCount ( + VOID + ); + +/** + Get Sleep Type that platform has waken from + + @retval SleepType Sleep Type +**/ +PMC_SLEEP_STATE +PmcGetSleepTypeAfterWake ( + VOID + ); + +/** + Clear PMC Wake Status +**/ +VOID +PmcClearWakeStatus ( + VOID + ); + +/** + Check if platform boots after shutdown caused by power button override e= vent + + @retval TRUE Power Button Override occurred in last system boot + @retval FALSE Power Button Override didn't occur +**/ +BOOLEAN +PmcIsPowerButtonOverrideDetected ( + VOID + ); + +/** + This function checks if SMI Lock is set + + @retval SMI Lock state +**/ +BOOLEAN +PmcIsSmiLockSet ( + VOID + ); + +/** + Check global SMI enable is set + + @retval TRUE Global SMI enable is set + FALSE Global SMI enable is not set +**/ +BOOLEAN +PmcIsGblSmiEn ( + VOID + ); + +#endif // _PMC_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h new file mode 100644 index 0000000000..047d543009 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SataLib.h @@ -0,0 +1,76 @@ +/** @file + Header file for PchSataLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SATA_LIB_H_ +#define _PCH_SATA_LIB_H_ + +#define SATA_1_CONTROLLER_INDEX 0 +#define SATA_2_CONTROLLER_INDEX 1 +#define SATA_3_CONTROLLER_INDEX 2 + +/** + Get Pch Maximum Sata Port Number + + @param[in] SataCtrlIndex SATA controller index + + @retval Pch Maximum Sata Port Number +**/ +UINT8 +GetPchMaxSataPortNum ( + IN UINT32 SataCtrlIndex + ); + +/** + Gets Maximum Sata Controller Number + + @param[in] None + + @retval Maximum Sata Controller Number +**/ +UINT8 +GetPchMaxSataControllerNum ( + VOID + ); + +/** + Gets SATA controller PCIe Device Number + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA controller PCIe Device Number +**/ +UINT8 +GetSataPcieDeviceNum ( + IN UINT32 SataCtrlIndex + ); + +/** + Gets SATA controller PCIe Function Number + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA controller PCIe Function Number +**/ +UINT8 +GetSataPcieFunctionNum ( + IN UINT32 SataCtrlIndex + ); + +/** + Gets SATA controller PCIe config space base address + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA controller PCIe config space base address +**/ +UINT64 +GetSataRegBase ( + IN UINT32 SataCtrlIndex + ); + +#endif // _PCH_SATA_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchL= ib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h new file mode 100644 index 0000000000..53283597e7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SecPchLib.h @@ -0,0 +1,22 @@ +/** @file + Header file for SEC PCH Lib. + All function in this library is available for SEC + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SEC_PCH_LIB_H_ +#define _SEC_PCH_LIB_H_ + +/** + This function do the PCH cycle decoding initialization. +**/ +VOID +EFIAPI +EarlyCycleDecoding ( + VOID + ); + +#endif // _SEC_PCH_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlas= hCommonLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFl= ashCommonLib.h new file mode 100644 index 0000000000..53c11bb59a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiFlashCommon= Lib.h @@ -0,0 +1,98 @@ +/** @file + The header file includes the common header files, defines + internal structure and functions used by SpiFlashCommonLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SPI_FLASH_COMMON_LIB_H__ +#define __SPI_FLASH_COMMON_LIB_H__ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SECTOR_SIZE_4KB 0x1000 // Common 4kBytes sector size +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ); + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ); + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ); + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.= h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h new file mode 100644 index 0000000000..e56f3139d7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/SpiLib.h @@ -0,0 +1,23 @@ +/** @file + Header file for Spi Library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SPI_LIB_H_ +#define _SPI_LIB_H_ + +/** + This function Initial SPI services + + @retval EFI_STATUS Results of the installation of the SPI services +**/ +EFI_STATUS +EFIAPI +SpiServiceInit ( + VOID + ); + +#endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45882): https://edk2.groups.io/g/devel/message/45882 Mute This Topic: https://groups.io/mt/32918173/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45880+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45880+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001012; cv=none; d=zoho.com; s=zohoarc; b=ZOI8+f762svOhQGZEieFDtaNfzVwpVPCqKTGdujfHLYQ1n/e7QEi7Pf9pBVe1uIVqnS+sO8wClvoVxuiGbFJ+cjBUVDZ6lhYhy1cnvQfRrGuSCunLyESxTH7VEs22Ja6T/xIjEMElhPoQpOVUNMrJnoqh28iYUYih/61XY73K5c= ARC-Message-Signature: i=1; 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16 Aug 2019 17:16:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319245" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:50 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 07/37] CoffeelakeSiliconPkg/Pch: Add PPI and Protocol include headers Date: Fri, 16 Aug 2019 17:15:33 -0700 Message-Id: <20190817001603.30632-8-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001011; bh=d+3DSyrIY8Hr4AHycUDiyWBIDRSz2h1NMT7Tb1/+UDA=; h=Cc:Date:From:Reply-To:Subject:To; b=oc3C45X0qHYMseDlV6yU04RcKg2LUPtpag5jSfm/yRlxBDVT5xMjtmYjgFo/ted+Snj dRlwD66BDuLWH4yK9+vI74kUEBBN61DnlcAN7U31Y0jehplMzqCJoZbE97TX3jUSjY83m XheC8KPgRjmO6Qk8U9Ti6PFxKKpnGM/0J6A= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds the following header files: * Pch/Include/Ppi * Pch/Include/Protocol Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h = | 42 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h = | 27 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h = | 28 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h= | 186 ++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch= .h | 136 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning.h = | 68 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch= .h | 146 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch= .h | 132 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h = | 42 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h = | 42 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h = | 134 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapContro= l.h | 67 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTime= rControl.h | 67 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.= h | 152 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h = | 15 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h = | 295 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h = | 113 ++++++++ 17 files changed, 1692 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h new file mode 100644 index 0000000000..840a2355f1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/PchReset.h @@ -0,0 +1,42 @@ +/** @file + PCH Reset PPI + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_PPI_H_ +#define _PCH_RESET_PPI_H_ + +// +// Member functions +// +/** + Execute call back function for Pch Reset. + + @param[in] ResetType Reset Types which includes GlobalReset. + @param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the Res= et Type Guid. + + @retval EFI_SUCCESS The callback function has been done succ= essfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback ppi. O= r, none of + callback ppi is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN EFI_RESET_TYPE ResetType, + IN EFI_GUID *ResetTypeGuid + ); + +/** + This ppi is used to execute PCH Reset from the host controller. + If drivers need to run their callback function right before issuing the = PCH Reset, + they can install PCH Reset Callback PPI before PCH Reset PEI driver to a= chieve that. +**/ +typedef struct { + PCH_RESET_CALLBACK ResetCallback; +} PCH_RESET_CALLBACK_PPI; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h new file mode 100644 index 0000000000..d3ff152742 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Spi.h @@ -0,0 +1,27 @@ +/** @file + This file defines the PCH SPI PPI which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_PPI_H_ +#define _PCH_SPI_PPI_H_ + +#include + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gPchSpiPpiGuid; + +/** + Reuse the PCH_SPI_PROTOCOL definitions + This is possible becaues the PPI implementation does not rely on a PeiSe= rvice pointer, + as it uses EDKII Glue Lib to do IO accesses +**/ +typedef PCH_SPI_PROTOCOL PCH_SPI_PPI; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h b/Sil= icon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h new file mode 100644 index 0000000000..59a9f0f251 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Ppi/Wdt.h @@ -0,0 +1,28 @@ +/** @file + Watchdog Timer PPI + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_WDT_H_ +#define _PEI_WDT_H_ + +#include +// +// MRC takes a lot of time to execute in debug mode +// +#define WDT_TIMEOUT_BETWEEN_PEI_DXE 60 + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gWdtPpiGuid; + +/// +/// Reuse WDT_PROTOCOL definition +/// +typedef WDT_PROTOCOL WDT_PPI; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrap= ExDispatch.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTr= apExDispatch.h new file mode 100644 index 0000000000..4f14065bd1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispa= tch.h @@ -0,0 +1,186 @@ +/** @file + PCH IO TrapEx Dispatch Protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IO_TRAP_EX_DISPATCH_H_ +#define _IO_TRAP_EX_DISPATCH_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gIoTrapExDispatchPro= tocolGuid; + +typedef struct _IO_TRAP_EX_DISPATCH_PROTOCOL IO_TRAP_EX_DISPATCH_= PROTOCOL; + +/** + IO Trap Ex valid types +**/ +typedef enum { + IoTrapExTypeWrite, + IoTrapExTypeRead, + IoTrapExTypeReadWrite, + IoTrapExTypeMaximum +} IO_TRAP_EX_DISPATCH_TYPE; + +/** + IO Trap Ex context structure containing information about the + IO trap Ex event that should invoke the handler. + ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b for = any byte access. + + Here are some examples for the usage. + 1. To trigger the TRAP for the IO address from 0x2000 to 0x20FF with BY= TE/WORD/DWORD read/write access: + Address =3D 0x2000 + Length =3D 0x100 + Type =3D IoTrapExTypeReadWrite + ByteEnable =3D 0x00 (BE is not matter) + ByteEnableMask =3D 0x0F (BEM 0xF for any BYTE/WORD/DWORD access) + 2. To trigger the TRAP for port 0x61 with BYTE read access: + Address =3D 0x60 + Length =3D 4 + Type =3D IoTrapExTypeRead + ByteEnable =3D 0x02 (BE is 0010b to trap only second byte of eve= ry DWORD) + ByteEnableMask =3D 0x00 (BEM doesn't mask any BE bit) + 3. To trigger the TRAP for port 0x60 and 0x64 with BYTE write access: + Address =3D 0x60 + Length =3D 8 + Type =3D IoTrapExTypeWrite + ByteEnable =3D 0x01 (BE is 0001b to trap only first byte of ever= y DWORD) + ByteEnableMask =3D 0x00 (BEM doesn't mask any BE bit) +**/ +typedef struct { + /** + The Address must be dword alignment. + **/ + UINT16 Address; + UINT16 Length; + IO_TRAP_EX_DISPATCH_TYPE Type; + /** + Bitmap to enable trap for each byte of every dword alignment address. + The Io Trap Address must be dword alignment for ByteEnable. + E.g. 0001b for first byte, 0010b for second byte, 1100b for third and = fourth byte. + **/ + UINT8 ByteEnable; + /** + ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b fo= r any byte access. + The Io Trap Address must be dword alignment for ByteEnableMask. + **/ + UINT8 ByteEnableMask; +} IO_TRAP_EX_REGISTER_CONTEXT; + +/** + Callback function for an PCH IO TRAP EX handler dispatch. + + @param[in] Address DWord-aligned address of the trapp= ed cycle. + @param[in] ByteEnable This is the DWord-aligned byte ena= bles associated with the trapped cycle. + A 1 in any bit location indicates = that the corresponding byte is enabled in the cycle. + @param[in] WriteCycle TRUE =3D Write cycle; FALSE =3D Re= ad cycle + @param[in] WriteData DWord of I/O write data. This fiel= d is undefined after trapping a read cycle. + The byte of WriteData is only vali= d if the corresponding bits in ByteEnable is 1. + E.g. + If ByteEnable is 0001b, then only = first byte of WriteData is valid. + If ByteEnable is 0010b, then only = second byte of WriteData is valid. +**/ +typedef +VOID +(EFIAPI *IO_TRAP_EX_DISPATCH_CALLBACK) ( + IN UINT16 Address, + IN UINT8 ByteEnable, + IN BOOLEAN WriteCycle, + IN UINT32 WriteData + ); + +/** + Register a new IO Trap Ex SMI dispatch function. + The caller will provide information of IO trap setting via the context. + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. + This is the function to extend the IoTrap capability, and it's expected + to handle the special ByteEnable and ByteEnableMask setting. + This register function will occupy one IoTrap register if possible. + And it only support one handler for one IoTrap event. + The Address of context MUST NOT be 0, and MUST be dword alignment. + The Length of context MUST not less than 4, and MUST be power of 2. + The ByteEnable and ByteEnableMask MUST not be zero at the same time. + if the IO Trap handler is not used. It also enable the IO Trap Range to = generate + SMI. + Caller must take care of reserving the IO addresses in ACPI. + + @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTO= COL instance. + @param[in] DispatchFunction Pointer to dispatch function to be invok= ed for + this SMI source. + @param[in] RegisterContext Pointer to the dispatch function's conte= xt. + The caller fills this context in before = calling + the register function to indicate to the= register + function the IO trap Ex SMI source for w= hich the dispatch + function should be invoked. This MUST n= ot be NULL. + @param[out] DispatchHandle Handle of dispatch function. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + registered and the SMI source has been e= nabled. + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available + @retval EFI_INVALID_PARAMETER Address requested is already in use. + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLo= ck event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *IO_TRAP_EX_DISPATCH_REGISTER) ( + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, + IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction, + IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a SMI source dispatch function. + This function is unsupported. + + @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTO= COL instance. + @param[in] DispatchHandle Handle of dispatch function to deregiste= r. + + @retval EFI_UNSUPPORTED The function is unsupported. +**/ +typedef +EFI_STATUS +(EFIAPI *IO_TRAP_EX_DISPATCH_UNREGISTER) ( + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for the IO trap Extention protocol. + This protocol exposes full IO TRAP capability for ByteEnable and ByteEna= bleMask setting. + Platform code should fully control the ByteEnable and ByteEnableMake whi= le using this protocol. + + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. + This is the function to extend the IoTrap capability, and it's expected + to handle the special ByteEnable and ByteEnableMask setting. + + The protocol is low level, It returns PSTH trapped cycle. This might not= be safe for multithread + if more than one thread triggers the same IOTRAP at the same time. +**/ +struct _IO_TRAP_EX_DISPATCH_PROTOCOL { + /** + Register function for PCH IO TRAP EX DISPATCH PROTOCOL. + The caller will provide information of IO trap setting via the context. + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible. + This is the function to extend the IoTrap capability, and it's expected + to handle the special ByteEnable and ByteEnableMask setting. + This register function will occupy one IoTrap register if possible. + And it only support one handler for one IoTrap event. + The Address of context MUST NOT be 0, and MUST be dword alignment. + The Length of context MUST not less than 4, and MUST be power of 2. + The ByteEnable and ByteEnableMask MUST not be zero at the same time. + if the IO Trap handler is not used. It also enable the IO Trap Range to + generate SMI. + **/ + IO_TRAP_EX_DISPATCH_REGISTER Register; + /** + Unregister function for PCH IO TRAP EX DISPATCH PROTOCOL. + **/ + IO_TRAP_EX_DISPATCH_UNREGISTER UnRegister; +}; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcp= iSmiDispatch.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Pc= hAcpiSmiDispatch.h new file mode 100644 index 0000000000..f3e788a2e1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDis= patch.h @@ -0,0 +1,136 @@ +/** @file + APIs of PCH ACPI SMI Dispatch Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchAcpiSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL PCH_ACPI_SMI_DISPATCH_PR= OTOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH ACPI SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this= handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_ACPI_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for PCH ACPI SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for w= hen interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + registered and the SMI source has = been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable th= e SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) = to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_ACPI_SMI_DISPATCH_REGISTER) ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent ACPI SMM d= river + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_ACPI_SMI_DISPATCH_UNREGISTER) ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH ACPI SMIs Dispatch Protocol + The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch func= tion for PCH ACPI related SMIs. + It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow. +**/ +struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is us= ed to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL. + **/ + PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister; + /** + Pme + The event is triggered by hardware when the PME# signal goes active. + Additionally, the event is only triggered when SCI_EN is not set. + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister; + /** + PmeB0 + The event is triggered PCH when any internal device with PCI Power Man= agement + capabilities on bus 0 asserts the equivalent of the PME# signal. + Additionally, the event is only triggered when SCI_EN is not set. + The following are internal devices which can set this bit: + Intel HD Audio, Intel Management Engine "maskable" wake events, Integr= ated LAN, + SATA, xHCI, Intel SST + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register; + /** + RtcAlarm + The event is triggered by hardware when the RTC generates an alarm + (assertion of the IRQ8# signal). + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister; + /** + TmrOverflow + The event is triggered any time bit 22 of the 24-bit timer goes high + (bits are numbered from 0 to 23). + This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + 0= 2h, bit 0) is set, + then the setting of the TMROF_STS bit will additionally generate an SM= I# + Additionally, the event is only triggered when SCI_EN is not set. + **/ + PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister; +}; + +/** + PCH ACPI SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_ACPI_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmm= cTuning.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmc= Tuning.h new file mode 100644 index 0000000000..45fae6e2d5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEmmcTuning= .h @@ -0,0 +1,68 @@ +/** @file + PCH eMMC HS400 Tuning Protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_EMMC_TUNING_PROTOCOL_H_ +#define _PCH_EMMC_TUNING_PROTOCOL_H_ + +#define PCH_EMMC_TUNING_PROTOCOL_REVISION 1 +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchEmmcTuningProtocolGuid; + +// +// Forward declaration for PCH_EMMC_TUNING_PROTOCOL +// +typedef struct _PCH_EMMC_TUNING_PROTOCOL PCH_EMMC_TUNING_PROTOCOL; + +/** + This structure decribes the required Emmc info for HS400 tuning +**/ +typedef struct { + EFI_HANDLE PartitionHandle; ///< eMMC partition handle= for block read/write + EFI_LBA Lba; ///< Logical Block Address= for HS400 Tuning block read/write + UINT32 RelativeDevAddress; ///< Device system address= , dynamically assigned by the host during initialization. + UINT8 HS200BusWidth; ///< The value to be progr= ammed for BUS_WIDTH[183] byte +} EMMC_INFO; + +/// +/// This structure describes the return value after HS400 tuning +/// +typedef struct { + UINT8 Hs400DataValid; ///< Set if Hs400 Tuning Data is valid a= fter tuning + UINT8 Hs400RxStrobe1Dll; ///< Rx Strobe Delay Control - Rx Strobe= Delay DLL 1 (HS400 Mode) + UINT8 Hs400TxDataDll; ///< Tx Data Delay Control 1 - Tx Data D= elay (HS400 Mode) +} EMMC_TUNING_DATA; + +/// +/// EMMC HS400 TUNING INTERFACE +/// +typedef EFI_STATUS (EFIAPI *EMMC_TUNE) ( + IN PCH_EMMC_TUNING_PROTOCOL *This, ///< This poin= ter to PCH_EMMC_TUNING_PROTOCOL + /** + Revision parameter is used to verify the layout of EMMC_INFO and TUNIN= GDATA. + If the revision is not matched, means the revision of EMMC_INFO and TU= NINGDATA is not matched. + And function will return immediately. + **/ + IN UINT8 Revision, + IN EMMC_INFO *EmmcInfo, ///< Pointer t= o EMMC_INFO + OUT EMMC_TUNING_DATA *EmmcTuningData ///< Pointer t= o EMMC_TUNING_DATA +); + +/** + PCH EMMC TUNING PROTOCOL INTERFACE + Platform code uses this protocol to configure Emmc Hs400 mode, by passin= g the EMMC_INFO information. + PCH will setting EMMC controller based on EMMC_INFO and return EMMC_TUNI= NG_DATA to platform code. + Platform should keep values of EMMC_TUNING_DATA and uses to configure EM= MC through policies, to + prevent from doing EMMC tuning every boot. +**/ +struct _PCH_EMMC_TUNING_PROTOCOL { + EMMC_TUNE EmmcTune; ///< Emmc Hs400 Tuning Interface +}; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEsp= iSmiDispatch.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Pc= hEspiSmiDispatch.h new file mode 100644 index 0000000000..9a180b4285 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDis= patch.h @@ -0,0 +1,146 @@ +/** @file + SmmEspiDispatch Protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchEspiSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL PCH_ESPI_SMI_DISPATCH_PROTO= COL; + +// +// Member functions +// + +/** + Callback function for an PCH eSPI SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this= handler by register function. +**/ +typedef +VOID +(EFIAPI *PCH_ESPI_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Generic function to register different types of eSPI SMI types + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration successful + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event= has been triggered + @retval others Registration failed +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_ESPI_SMI_REGISTER) ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to unregister a callback based on ha= ndle + + @param[in] This Not used + @param[in] DispatchHandle Handle acquired during registration + + @retval EFI_SUCCESS Unregister successful + @retval EFI_INVALID_PARAMETER DispatchHandle is null + @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has ba= d pointer + @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in dat= abase + @retval EFI_ACCESS_DENIED Unregistration is done after end of = DXE +**/ + +typedef +EFI_STATUS +(EFIAPI *PCH_ESPI_SMI_UNREGISTER) ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH eSPI SMIs Dispatch Protocol + The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch func= tion for PCH eSPI related SMIs. + It contains SMI types of BiosWr, EcAssertedVw, and eSPI Master asserted = SMIs +**/ +struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is us= ed to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Unregister eSPI SMI events + **/ + PCH_ESPI_SMI_UNREGISTER UnRegister; + /** + Register a BIOS Write Protect event + **/ + PCH_ESPI_SMI_REGISTER BiosWrProtectRegister; + /** + Register a BIOS Write Report event + **/ + PCH_ESPI_SMI_REGISTER BiosWrReportRegister; + /** + Register a Peripheral Channel Non Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister; + /** + Register a Peripheral Channel Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER PcErrFatalRegister; + /** + Register a Virtual Wire Non Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister; + /** + Register a Virtual Wire Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER VwErrFatalRegister; + /** + Register a Flash Channel Non Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister; + /** + Register a Flash Channel Fatal Error event + **/ + PCH_ESPI_SMI_REGISTER FlashErrFatalRegister; + /** + Register a Link Error event + **/ + PCH_ESPI_SMI_REGISTER LnkErrType1Register; + /** + Register a SMI handler for Espi slaver + This routine will also lock down ESPI_SMI_LOCK bit after registration = and prevent + this handler from unregistration. + On platform that supports more than 1 device through another chip sele= ct (SPT-H), + the SMI handler itself needs to inspect both the eSPI devices' interru= pt status registers + (implementation specific for each Slave) in order to identify and serv= ice the cause. + After servicing it, it has to clear the Slaves' internal SMI# status r= egisters + **/ + PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister; +}; + +/** + PCH ESPI SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_ESPI_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPci= eSmiDispatch.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Pc= hPcieSmiDispatch.h new file mode 100644 index 0000000000..c5e8bc3f28 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDis= patch.h @@ -0,0 +1,132 @@ +/** @file + APIs of PCH PCIE SMI Dispatch Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchPcieSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PR= OTOCOL; + +// +// Member functions +// + +typedef struct { + UINT8 RpIndex; ///< Root port index (0-b= ased), 0: RP1, 1: RP2, n: RP(N+1) + UINT8 BusNum; ///< Root port pci bus nu= mber + UINT8 DevNum; ///< Root port pci device= number + UINT8 FuncNum; ///< Root port pci functi= on number +} PCH_PCIE_SMI_RP_CONTEXT; + +/** + Callback function for an PCH PCIE RP SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this= handler by register function. + @param[in] RpContext Pointer of PCH PCIE Root Port cont= ext. + +**/ +typedef +VOID +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ); + +/** + Register a child SMI source dispatch function for PCH PCIERP SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for + this SMI source + @param[in] RpIndex Refer to PCH PCIE Root Port index. + 0: RP1, 1: RP2, n: RP(N+1) + @param[out] DispatchHandle Handle of dispatch function, for w= hen interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + registered and the SMI source has = been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable th= e SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) = to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, + IN UINTN RpIndex, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent PCIE SMM d= river + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH PCIE SMIs Dispatch Protocol + The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch func= tion for PCH PCIE related SMIs. + It contains SMI types of HotPlug, LinkActive, and Link EQ. +**/ +struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is us= ed to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL. + **/ + PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister; + /** + PcieRpXHotPlug + The event is triggered when PCIE root port Hot-Plug Presence Detect. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister; + /** + PcieRpXLinkActive + The event is triggered when Hot-Plug Link Active State Changed. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister; + /** + PcieRpXLinkEq + The event is triggered when Device Requests Software Link Equalization. + **/ + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister; +}; + +/** + PCH PCIE SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_PCIE_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPol= icy.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h new file mode 100644 index 0000000000..ff35b43b61 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h @@ -0,0 +1,42 @@ +/** @file + Interface definition details between Pch and platform drivers during DXE= phase. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_POLICY_H_ +#define _PCH_POLICY_H_ + +#include +#include +#include +#include + +extern EFI_GUID gPchPolicyProtocolGuid; + +#define PCH_POLICY_PROTOCOL_REVISION 1 + + +/** + PCH DXE Policy + + The PCH_POLICY_PROTOCOL producer drvier is recommended to + set all the PCH_POLICY_PROTOCOL size buffer zero before init any member = parameter, + this clear step can make sure no random value for those unknown new vers= ion parameters. + + Make sure to update the Revision if any change to the protocol, includin= g the existing + internal structure definations.\n + Note: Here revision will be bumped up when adding/removing any config bl= ock under this structure.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_TABLE_HEADER TableHeader; +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +} PCH_POLICY_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchRes= et.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h new file mode 100644 index 0000000000..4c49d082fc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchReset.h @@ -0,0 +1,42 @@ +/** @file + PCH Reset Protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RESET_PROTOCOL_H_ +#define _PCH_RESET_PROTOCOL_H_ + +// +// Member functions +// +/** + Execute call back function for Pch Reset. + + @param[in] ResetType Reset Types which includes GlobalReset. + @param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the Res= et Type Guid. + + @retval EFI_SUCCESS The callback function has been done succ= essfully + @retval EFI_NOT_FOUND Failed to find Pch Reset Callback protoc= ol. Or, none of + callback protocol is installed. + @retval Others Do not do any reset from PCH +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_RESET_CALLBACK) ( + IN EFI_RESET_TYPE ResetType, + IN EFI_GUID *ResetTypeGuid + ); + +/** + This protocol is used to execute PCH Reset from the host controller. + If drivers need to run their callback function right before issuing the = PCH Reset, + they can install PCH Reset Callback Protocol before PCH Reset DXE driver= to achieve that. +**/ +typedef struct { + PCH_RESET_CALLBACK ResetCallback; +} PCH_RESET_CALLBACK_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmi= Dispatch.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmi= Dispatch.h new file mode 100644 index 0000000000..6fdfed1de7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatc= h.h @@ -0,0 +1,134 @@ +/** @file + APIs of PCH SMI Dispatch Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCO= L; + +// +// Member functions +// + +/** + Callback function for an PCH SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this= handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for specific PCH SMI dispa= tch event. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for w= hen interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + registered and the SMI source has = been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable th= e SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) = to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMI_DISPATCH_REGISTER) ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMI_DISPATCH_UNREGISTER) ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH specific SMIs Dispatch Protocol + The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function = for PCH misc SMIs. + It contains legacy SMIs and new PCH SMI types like: + SerialIrq, McSmi, Smbus, ... +**/ +struct _PCH_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is us= ed to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH SMI DISPATCH PROTOCOL. + **/ + PCH_SMI_DISPATCH_UNREGISTER UnRegister; + /** + SerialIrq + The event is triggered while the SMI# was caused by the SERIRQ decoder. + **/ + PCH_SMI_DISPATCH_REGISTER SerialIrqRegister; + /** + McSmi + The event is triggered if there has been an access to the power manage= ment + microcontroller range (62h or 66h) and the Microcontroller Decode Enab= le #1 bit + in the LPC Bridge I/O Enables configuration register is 1 . + **/ + PCH_SMI_DISPATCH_REGISTER McSmiRegister; + /** + SmBus + The event is triggered while the SMI# was caused by: + 1. The SMBus Slave receiving a message that an SMI# should be caused, = or + 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and = the + SMBALERT_DIS bit is cleared, or + 3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY= _INTREN and + the SMB_SMI_EN bits are set, or + 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 stat= e. + **/ + PCH_SMI_DISPATCH_REGISTER SmbusRegister; + /** + SPI Asynchronous + When registered, the flash controller will generate an SMI when it blo= cks a BIOS write or erase. + **/ + PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister; +}; + +/** + PCH SMI dispatch revision number + + Revision 1: Initial version +**/ +#define PCH_SMI_DISPATCH_REVISION 1 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmm= IoTrapControl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/P= chSmmIoTrapControl.h new file mode 100644 index 0000000000..73386a570e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapC= ontrol.h @@ -0,0 +1,67 @@ +/** @file + PCH SMM IO Trap Control Protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SMM_IO_TRAP_CONTROL_H_ +#define _PCH_SMM_IO_TRAP_CONTROL_H_ + + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmmIoTrapControlGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_= PROTOCOL; + +// +// Related Definitions +// + +// +// Member functions +// + +/** + The Prototype of Pause and Resume IoTrap callback function. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_P= ROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change st= ate. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) ( + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for the SMM IO trap pause and resume protocol + This protocol provides the functions to runtime control the IoTrap SMI e= nabled/disable. + This applys the capability to the DispatchHandle which returned by IoTra= p callback + registration, and the DispatchHandle which must be MergeDisable =3D TRUE= and Address !=3D 0. + Besides, when S3 resuem, it only restores the state of IoTrap callback r= egistration. + The Paused/Resume state won't be restored after S3 resume. +**/ +struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL { + /** + This runtime pauses a registered IoTrap handler. + **/ + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause; + /** + This runtime resumes a registered IoTrap handler. + **/ + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume; +}; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmm= PeriodicTimerControl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Pro= tocol/PchSmmPeriodicTimerControl.h new file mode 100644 index 0000000000..06ddc3e1cd --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodi= cTimerControl.h @@ -0,0 +1,67 @@ +/** @file + PCH SMM Periodic Timer Control Protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ +#define _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ + + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSmmPeriodi= cTimerControlGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL PCH_SMM_PERIOD= IC_TIMER_CONTROL_PROTOCOL; + +// +// Related Definitions +// + +// +// Member functions +// + +/** + The Prototype of Pause and Resume SMM PERIODIC TIMER function. + + @param[in] This Pointer to the PCH_SMM_PERIODIC_TI= MER_CONTROL_PROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to cha= nge state. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RE= SUMED. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) ( + IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for the SMM PERIODIC TIMER pause and resume protocol + This protocol provides the functions to runtime control the SM periodic = timer enabled/disable. + This applies the capability to the DispatchHandle which returned by SMM = periodic timer callback + registration. + Besides, when S3 resume, it only restores the state of callback registra= tion. + The Paused/Resume state won't be restored after S3 resume. +**/ +struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL { + /** + This runtime pauses the registered periodic timer handler. + **/ + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause; + /** + This runtime resumes the registered periodic timer handler. + **/ + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume; +}; + +#endif // _PCH_SMM_PERIODIC_TIMER_CONTROL_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTco= SmiDispatch.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Pch= TcoSmiDispatch.h new file mode 100644 index 0000000000..d397712092 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDisp= atch.h @@ -0,0 +1,152 @@ +/** @file + APIs of PCH TCO SMI Dispatch Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ +#define _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchTcoSmiDispatchProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PRO= TOCOL; + +// +// Member functions +// + +/** + Callback function for an PCH TCO SMI handler dispatch. + + @param[in] DispatchHandle The unique handle assigned to this= handler by register function. + +**/ +typedef +VOID +(EFIAPI *PCH_TCO_SMI_DISPATCH_CALLBACK) ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register a child SMI source dispatch function for PCH TCO SMI events. + + @param[in] This Protocol instance pointer. + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for + this SMI source + @param[out] DispatchHandle Handle of dispatch function, for w= hen interfacing + with the parent SMM driver. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + registered and the SMI source has = been enabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable th= e SMI source. + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) = to manage this child. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_TCO_SMI_DISPATCH_REGISTER) ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent TCO SMM dr= iver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_TCO_SMI_DISPATCH_UNREGISTER) ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Interface structure for PCH TCO SMIs Dispatch Protocol + The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch funct= ion for PCH TCO related SMIs. + It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect, a= nd BiowWp. +**/ +struct _PCH_TCO_SMI_DISPATCH_PROTOCOL { + /** + This member specifies the revision of this structure. This field is us= ed to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + /** + Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL. + **/ + PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister; + /** + Mch + The event is triggered when PCH received a DMI special cycle message u= sing DMI indicating that + it wants to cause an SMI. + The software must read the processor to determine the reason for the S= MI. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER MchRegister; + /** + TcoTimeout + The event is triggered by PCH to indicate that the SMI was caused by t= he TCO timer reaching 0. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister; + /** + OsTco + The event is triggered when software caused an SMI# by writing to the = TCO_DAT_IN register (TCOBASE + 02h). + **/ + PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister; + /** + Nmi + The event is triggered by the PCH when an SMI# occurs because an event= occurred that would otherwise have + caused an NMI (because NMI2SMI_EN is set) + **/ + PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister; + /** + IntruderDectect + The event is triggered by PCH to indicate that an intrusion was detect= ed. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister; + /** + SpiBiosWp + This event is triggered when SMI# was caused by the TCO logic and + SPI flash controller asserted Synchronous SMI by BIOS lock enable set. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister; + /** + LpcBiosWp + This event is triggered when SMI# was caused by the TCO logic and + LPC/eSPI BIOS lock enable set. + **/ + PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister; + /** + NewCentury + This event is triggered when SMI# was caused by the TCO logic and + year of RTC date rolls over a century (99 to 00). + **/ + PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister; +}; + +/** + PCH TCO SMI dispatch revision number + + Revision 1: Initial version + Revision 2: Add NEWCENTURY support +**/ +#define PCH_TCO_SMI_DISPATCH_REVISION 2 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmb= us.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h new file mode 100644 index 0000000000..ece65cd729 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/SmmSmbus.h @@ -0,0 +1,15 @@ +/** @file + SmmSmbus Protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __EFI_SMM_SMBUS_PROTOCOL_H__ +#define __EFI_SMM_SMBUS_PROTOCOL_H__ + +extern EFI_GUID gEfiSmmSmbusProtocolGuid; + +#endif + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h new file mode 100644 index 0000000000..22df7fe351 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Spi.h @@ -0,0 +1,295 @@ +/** @file + This file defines the PCH SPI Protocol which implements the + Intel(R) PCH SPI Host Controller Compatibility Interface. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_PROTOCOL_H_ +#define _PCH_SPI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchSpiProtocolGuid; +extern EFI_GUID gPchSmmSpiProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL; + +// +// SPI protocol data structures and definitions +// + +/** + Flash Region Type +**/ +typedef enum { + FlashRegionDescriptor, + FlashRegionBios, + FlashRegionMe, + FlashRegionGbE, + FlashRegionPlatformData, + FlashRegionDer, + FlashRegionEC =3D 8, + FlashRegionAll, + FlashRegionMax +} FLASH_REGION_TYPE; + +// +// Protocol member functions +// + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. Remark: Erase may be needed before write t= o the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_ERASE) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data = read. + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +typedef +EFI_STATUS +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + These protocols/PPI allows a platform module to perform SPI operations t= hrough the + Intel PCH SPI Host Controller Interface. +**/ +struct _PCH_SPI_PROTOCOL { + /** + This member specifies the revision of this structure. This field is us= ed to + indicate backwards compatible changes to the protocol. + **/ + UINT8 Revision; + PCH_SPI_FLASH_READ FlashRead; ///< Read data fro= m the flash part. + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to= the flash part. Remark: Erase may be needed before write to the flash part. + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some ar= ea on the flash part. + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP dat= a from the flash part. + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id= from the flash part. + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the sta= tus register in the flash part. + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status r= egister in the flash part. + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI r= egion base and size + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft= Strap Values + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft= Strap Values +}; + +/** + PCH SPI PPI/PROTOCOL revision number + + Revision 1: Initial version +**/ +#define PCH_SPI_SERVICES_REVISION 1 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h = b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h new file mode 100644 index 0000000000..67554e526f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Protocol/Wdt.h @@ -0,0 +1,113 @@ +/** @file + Watchdog Timer protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_WDT_H_ +#define _DXE_WDT_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gWdtProtocolGuid; +// +// Forward reference for ANSI C compatibility +// +typedef struct _WDT_PROTOCOL WDT_PROTOCOL; + +/** + Reloads WDT with new timeout value and starts it. Also sets Unexpected R= eset bit, which + causes the next reset to be treated as watchdog expiration - unless Allo= wKnownReset() + function was called too. + + @param[in] TimeoutValue Time in seconds before WDT times out. Su= pported range =3D 1 - 1024. + + @retval EFI_SUCCESS if everything's OK + @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong +**/ +typedef +EFI_STATUS +(EFIAPI *WDT_RELOAD_AND_START) ( + UINT32 TimeoutValue + ); + +/** + Returns WDT failure status. + + @retval V_PCH_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiration or= unexpected reset + @retval V_PCH_OC_WDT_CTL_STATUS_OK Otherwise +**/ +typedef +UINT8 +(EFIAPI *WDT_CHECK_STATUS) ( + VOID + ); + +/** + Returns information if WDT coverage for the duration of BIOS execution + was requested by an OS application. + + @retval TRUE if WDT was requested + @retval FALSE if WDT was not requested +**/ +typedef +UINT8 +(EFIAPI *IS_WDT_REQUIRED) ( + VOID + ); + +/** + Returns WDT enabled/disabled status. + + @retval TRUE if WDT is enabled + @retval FALSE if WDT is disabled +**/ +typedef +UINT8 +(EFIAPI *IS_WDT_ENABLED) ( + VOID + ); + +/** + Disables WDT timer. +**/ +typedef +VOID +(EFIAPI *WDT_DISABLE) ( + VOID + ); + +/** + Normally, each reboot performed while watchdog runs is considered a fail= ure. + This function allows platform to perform expected reboots with WDT runni= ng, + without being interpreted as failures. + In DXE phase, it is enough to call this function any time before reset. + In PEI phase, between calling this function and performing reset, Reload= AndStart() + must not be called. +**/ +typedef +VOID +(EFIAPI *WDT_ALLOW_KNOWN_RESET) ( + VOID + ); + +/** + These protocols and PPI allow a platform module to perform watch dog tim= er operations + through the Intel PCH LPC Host Controller Interface. The WDT protocol an= d WDT PPI + implement the Intel (R) Watch Dog timer for DXE, and PEI environments, r= espectively. + WDT_PROTOCOL referenced hereafter represents both WDT_PROTOCOL and WDT_P= PI, as they + share the identical data structure. +**/ +struct _WDT_PROTOCOL { + WDT_RELOAD_AND_START ReloadAndStart; ///< Reloads WDT with new timeou= t value and starts it. + WDT_CHECK_STATUS CheckStatus; ///< Returns WDT failure status. + WDT_DISABLE Disable; ///< Disables WDT timer. + WDT_ALLOW_KNOWN_RESET AllowKnownReset; ///< Perform expected reboots wi= th WDT running, without being interpreted as failures. + IS_WDT_REQUIRED IsWdtRequired; ///< Returns information if WDT = coverage for the duration of BIOS execution was requested by an OS applicat= ion. + IS_WDT_ENABLED IsWdtEnabled; ///< Returns WDT enabled/disable= d status. +}; + +#endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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1566001013215107.52113080252332; Fri, 16 Aug 2019 17:16:53 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:51 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319248" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:50 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 08/37] CoffeelakeSiliconPkg/Pch: Add Register include headers Date: Fri, 16 Aug 2019 17:15:34 -0700 Message-Id: <20190817001603.30632-9-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001012; bh=vWROTgTk4rKDs9ccFdVFIIFxHUCJJp8tpDDSe4gW7fg=; h=Cc:Date:From:Reply-To:Subject:To; b=Oli1bET1Ova1MRMLd5dQ+SaggUqQqZoqR+odV2IGtS6dSIPnX3ZmOH0y9qX8FGPzyZz WEMf/rZ9wqjInFbXkwwWKfBk+2trFGG+Ikop2chp6IujgOSR55eK/XITpQsalOTl2YeHg xOP63X+Fm97KR1+hqrm3w9lC2Vuycq0AKEw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds the following header files: * Pch/Include/Register Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs.h = | 54 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDci.h = | 57 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h = | 122 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi14.h = | 54 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi15.h = | 62 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsFia.h = | 90 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h = | 273 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpioCnl.h = | 694 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHda.h = | 204 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h = | 170 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h = | 79 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsItss.h = | 103 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan.h = | 58 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h = | 360 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl.h = | 61 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h = | 116 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h = | 484 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h = | 73 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h = | 670 +++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmcCnl.h = | 72 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h = | 104 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsfCnl.h = | 113 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h = | 77 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSata.h = | 668 +++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScs.h = | 52 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScsCnl.h = | 48 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIo.h = | 232 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerialIoCnl= .h | 138 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h = | 151 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h = | 295 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsThermalCnl.= h | 49 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsTraceHub.h = | 134 ++++ 32 files changed, 5917 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= s.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs.h new file mode 100644 index 0000000000..10fcb316fc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs.h @@ -0,0 +1,54 @@ +/** @file + Generic register definitions for PCH. + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_H_ +#define _PCH_REGS_H_ + +/// +/// The default PCH PCI segment and bus number +/// +#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0 +#define DEFAULT_PCI_BUS_NUMBER_PCH 0 + +// +// Default Vendor ID and Subsystem ID +// +#define V_PCH_INTEL_VENDOR_ID 0x8086 ///< Default Intel PCH Vendor = ID +#define V_PCH_DEFAULT_SID 0x7270 ///< Default Intel PCH Subsyst= em ID +#define V_PCH_DEFAULT_SVID_SID (V_INTEL_VENDOR_ID + (V_PCH_DEFAULT_SID <<= 16)) ///< Default INTEL PCH Vendor ID and Subsystem ID + +#endif //_PCH_REGS_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sDci.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDci= .h new file mode 100644 index 0000000000..47dd73215e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDci.h @@ -0,0 +1,57 @@ +/** @file + Register names for PCH DCI device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_DCI_H_ +#define _PCH_REGS_DCI_H_ + +// +// DCI PCR Registers +// + +#define R_DCI_PCR_ECTRL 0x04 ///< DCI Con= trol Register + +#define B_DCI_PCR_ECTRL_HDCIEN_LOCK BIT0 ///< Host DC= I Enable Lock +#define B_DCI_PCR_ECTRL_HDCIEN BIT4 ///< Host DC= I Enable + +#define R_DCI_PCR_ECKPWRCTL 0x08 ///< DCI Pow= er Control +// CNP-A0 (DCI Gen2) and backwards +#define R_DCI_PCR_PCE 0x30 ///< DCI Pow= er Control Enable Register +#define B_DCI_PCR_PCE_HAE BIT5 ///< Hardwar= e Autonomous Enable +#define B_DCI_PCR_PCE_D3HE BIT2 ///< D3-Hot = Enable +#define B_DCI_PCR_PCE_I3E BIT1 ///< I3 Enab= le +#define B_DCI_PCR_PCE_PMCRE BIT0 ///< PMC Req= uest Enable +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sDmi.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi= .h new file mode 100644 index 0000000000..44f708dd92 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi.h @@ -0,0 +1,122 @@ +/** @file + Register names for DMI and OP-DMI + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_DMI_H_ +#define _PCH_REGS_DMI_H_ + +// +// DMI Chipset Configuration Registers (PID:DMI) +// + +// +// VC Configuration (Common) +// +#define B_PCH_DMI_PCR_V0CTL_EN BIT31 +#define B_PCH_DMI_PCR_V0CTL_ID (7 << 24) /= //< Bit[26:24] +#define N_PCH_DMI_PCR_V0CTL_ID 24 +#define V_PCH_DMI_PCR_V0CTL_ETVM_MASK 0xFC00 +#define V_PCH_DMI_PCR_V0CTL_TVM_MASK 0x7E +#define B_PCH_DMI_PCR_V0STS_NP BIT1 +#define B_PCH_DMI_PCR_V1CTL_EN BIT31 +#define B_PCH_DMI_PCR_V1CTL_ID (0x0F << 24) /= //< Bit[27:24] +#define N_PCH_DMI_PCR_V1CTL_ID 24 +#define V_PCH_DMI_PCR_V1CTL_ETVM_MASK 0xFC00 +#define V_PCH_DMI_PCR_V1CTL_TVM_MASK 0xFE +#define B_PCH_DMI_PCR_V1STS_NP BIT1 + + +// +// DMI Source Decode PCRs (Common) +// +#define R_PCH_DMI_PCR_PCIEPAR1E 0x2700 ///< PCIE Po= rt IOxAPIC Range 1 Enable +#define R_PCH_DMI_PCR_PCIEPAR2E 0x2704 ///< PCIE Po= rt IOxAPIC Range 2 Enable +#define R_PCH_DMI_PCR_PCIEPAR3E 0x2708 ///< PCIE Po= rt IOxAPIC Range 3 Enable +#define R_PCH_DMI_PCR_PCIEPAR4E 0x270C ///< PCIE Po= rt IOxAPIC Range 4 Enable +#define R_PCH_DMI_PCR_PCIEPAR1DID 0x2710 ///< PCIE Po= rt IOxAPIC Range 1 Destination ID +#define R_PCH_DMI_PCR_PCIEPAR2DID 0x2714 ///< PCIE Po= rt IOxAPIC Range 2 Destination ID +#define R_PCH_DMI_PCR_PCIEPAR3DID 0x2718 ///< PCIE Po= rt IOxAPIC Range 3 Destination ID +#define R_PCH_DMI_PCR_PCIEPAR4DID 0x271C ///< PCIE Po= rt IOxAPIC Range 4 Destination ID +#define R_PCH_DMI_PCR_P2SBIOR 0x2720 ///< P2SB IO= Range +#define R_PCH_DMI_PCR_TTTBARB 0x2724 ///< Thermal= Throttling BIOS Assigned Thermal Base Address +#define R_PCH_DMI_PCR_TTTBARBH 0x2728 ///< Thermal= Throttling BIOS Assigned Thermal Base High Address +#define R_PCH_DMI_PCR_LPCLGIR1 0x2730 ///< LPC Gen= eric I/O Range 1 +#define R_PCH_DMI_PCR_LPCLGIR2 0x2734 ///< LPC Gen= eric I/O Range 2 +#define R_PCH_DMI_PCR_LPCLGIR3 0x2738 ///< LPC Gen= eric I/O Range 3 +#define R_PCH_DMI_PCR_LPCLGIR4 0x273C ///< LPC Gen= eric I/O Range 4 +#define R_PCH_DMI_PCR_LPCGMR 0x2740 ///< LPC Gen= eric Memory Range +#define R_PCH_DMI_PCR_SEGIR 0x27BC ///< Second = ESPI Generic I/O Range +#define R_PCH_DMI_PCR_SEGMR 0x27C0 ///< Second = ESPI Generic Memory Range +#define R_PCH_DMI_PCR_LPCBDE 0x2744 ///< LPC BIO= S Decode Enable +#define R_PCH_DMI_PCR_UCPR 0x2748 ///< uCode P= atch Region +#define B_PCH_DMI_PCR_UCPR_UPRE BIT0 ///< uCode P= atch Region Enable +#define R_PCH_DMI_PCR_GCS 0x274C ///< Generic= Control and Status +#define B_PCH_DMI_PCR_RPRDID 0xFFFF0000 ///< RPR Des= tination ID +#define B_PCH_DMI_PCR_BBS BIT10 ///< Boot BI= OS Strap +#define B_PCH_DMI_PCR_RPR BIT11 ///< Reserve= d Page Route +#define B_PCH_DMI_PCR_BILD BIT0 ///< BIOS In= terface Lock-Down +#define R_PCH_DMI_PCR_IOT1 0x2750 ///< I/O Tra= p Register 1 +#define R_PCH_DMI_PCR_IOT2 0x2758 ///< I/O Tra= p Register 2 +#define R_PCH_DMI_PCR_IOT3 0x2760 ///< I/O Tra= p Register 3 +#define R_PCH_DMI_PCR_IOT4 0x2768 ///< I/O Tra= p Register 4 +#define R_PCH_DMI_PCR_LPCIOD 0x2770 ///< LPC I/O= Decode Ranges +#define R_PCH_DMI_PCR_LPCIOE 0x2774 ///< LPC I/O= Enables +#define R_PCH_DMI_PCR_TCOBASE 0x2778 ///< TCO Bas= e Address +#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 ///< TCO Bas= e Address Mask +#define R_PCH_DMI_PCR_GPMR1 0x277C ///< General= Purpose Memory Range 1 +#define R_PCH_DMI_PCR_GPMR1DID 0x2780 ///< General= Purpose Memory Range 1 Destination ID +#define R_PCH_DMI_PCR_GPMR2 0x2784 ///< General= Purpose Memory Range 2 +#define R_PCH_DMI_PCR_GPMR2DID 0x2788 ///< General= Purpose Memory Range 2 Destination ID +#define R_PCH_DMI_PCR_GPMR3 0x278C ///< General= Purpose Memory Range 3 +#define R_PCH_DMI_PCR_GPMR3DID 0x2790 ///< General= Purpose Memory Range 3 Destination ID +#define R_PCH_DMI_PCR_GPIOR1 0x2794 ///< General= Purpose I/O Range 1 +#define R_PCH_DMI_PCR_GPIOR1DID 0x2798 ///< General= Purpose I/O Range 1 Destination ID +#define R_PCH_DMI_PCR_GPIOR2 0x279C ///< General= Purpose I/O Range 2 +#define R_PCH_DMI_PCR_GPIOR2DID 0x27A0 ///< General= Purpose I/O Range 2 Destination ID +#define R_PCH_DMI_PCR_GPIOR3 0x27A4 ///< General= Purpose I/O Range 3 +#define R_PCH_DMI_PCR_GPIOR3DID 0x27A8 ///< General= Purpose I/O Range 3 Destination ID + +// +// Opi PHY registers +// +#define R_PCH_OPIPHY_PCR_0110 0x0110 +#define R_PCH_OPIPHY_PCR_0118 0x0118 +#define R_PCH_OPIPHY_PCR_011C 0x011C +#define R_PCH_OPIPHY_PCR_0354 0x0354 +#define R_PCH_OPIPHY_PCR_B104 0xB104 +#define R_PCH_OPIPHY_PCR_B10C 0xB10C + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sDmi14.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsD= mi14.h new file mode 100644 index 0000000000..36c0054d63 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi14.h @@ -0,0 +1,54 @@ +/** @file + Register names for DMI SIP14 + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_DMI14_H_ +#define _PCH_REGS_DMI14_H_ + +// +// DMI Chipset Configuration Registers (PID:DMI) +// + +// +// DMI Control +// +#define R_PCH_DMI14_PCR_DMIC 0x2234 = ///< DMI Control +#define B_PCH_DMI14_PCR_DMIC_SRL BIT31 = ///< Secured register lock +#define B_PCH_DMI14_PCR_DMIC_DMICGEN (BIT4 | BIT3 | BIT2 | BIT1 = | BIT0) ///< DMI Clock Gate Enable + +#define R_PCH_DMI14_PCR_2314 0x2314 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sDmi15.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsD= mi15.h new file mode 100644 index 0000000000..c885fdd34d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsDmi15.h @@ -0,0 +1,62 @@ +/** @file + Register names for DMI and OP-DMI + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_DMI15_H_ +#define _PCH_REGS_DMI15_H_ + +#define R_PCH_DMI15_PCR_MPC 0x20D8 /= //< Miscellaneous Port Configuration +#define B_PCH_DMI15_PCR_MPC_SRL BIT23 /= //< Secured register lock +#define R_PCH_DMI15_PCR_V0CTL 0x2284 /= //< Virtual channel 0 resource control +#define R_PCH_DMI15_PCR_V0STS 0x228A /= //< Virtual channel 0 status + +#define R_PCH_DMI15_PCR_V1CTL 0x2290 /= //< Virtual channel 1 resource control +#define R_PCH_DMI15_PCR_V1STS 0x2296 /= //< Virtual channel 1 status + +#define R_PCH_DMI15_PCR_VMCTL 0x22B0 /= //< ME Virtual Channel (VCm) resource control + +#define R_PCH_DMI15_PCR_UPHWAWC 0x249C /= //< Upstream Port HW Autonomous Width Control +#define B_PCH_DMI15_PCR_UPHWAWC_TS3TW (BIT15 | BIT14 | BIT13) /= //< Thermal Sensor 3 Target Width +#define N_PCH_DMI15_PCR_UPHWAWC_TS3TW 13 /= //< Thermal Sensor 3 Target Width +#define B_PCH_DMI15_PCR_UPHWAWC_TS2TW (BIT12 | BIT11 | BIT10) /= //< Thermal Sensor 2 Target Width +#define N_PCH_DMI15_PCR_UPHWAWC_TS2TW 10 /= //< Thermal Sensor 2 Target Width +#define B_PCH_DMI15_PCR_UPHWAWC_TS1TW (BIT9 | BIT8 | BIT7) /= //< Thermal Sensor 1 Target Width +#define N_PCH_DMI15_PCR_UPHWAWC_TS1TW 7 /= //< Thermal Sensor 1 Target Width +#define B_PCH_DMI15_PCR_UPHWAWC_TS0TW (BIT6 | BIT5 | BIT4) /= //< Thermal Sensor 0 Target Width +#define N_PCH_DMI15_PCR_UPHWAWC_TS0TW 4 /= //< Thermal Sensor 0 Target Width +#define B_PCH_DMI15_PCR_UPHWAWC_TSAWEN BIT0 /= //< Thermal Sensor Autonomous Width Enable + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sFia.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsFia= .h new file mode 100644 index 0000000000..837fdc5609 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsFia.h @@ -0,0 +1,90 @@ +/** @file + Register definition for FIA component + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_FIA_H_ +#define _PCH_REGS_FIA_H_ + + +// +// Private chipset register (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PCH FIA lane owner encoding +// +#define V_PCH_FIA_PCR_LANE_OWN_PCIEDMI 0x0 +#define V_PCH_FIA_PCR_LANE_OWN_USB3 0x1 +#define V_PCH_FIA_PCR_LANE_OWN_SATA 0x2 +#define V_PCH_FIA_PCR_LANE_OWN_GBE 0x3 +#define V_PCH_FIA_PCR_LANE_OWN_MOBEXP 0x4 +#define V_PCH_FIA_PCR_LANE_OWN_SSIC 0x5 +#define V_PCH_FIA_PCR_LANE_OWN_CSI3 0x6 +#define V_PCH_FIA_PCR_LANE_OWN_UFS 0x7 + +#define B_PCH_FIA_PCR_L0O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_FIA_PCR_L1O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_FIA_PCR_L2O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_FIA_PCR_L3O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_FIA_PCR_L4O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_FIA_PCR_L5O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_FIA_PCR_L6O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_FIA_PCR_L7O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_FIA_PCR_L8O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_FIA_PCR_L9O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_FIA_PCR_L10O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_FIA_PCR_L11O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_FIA_PCR_L12O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_FIA_PCR_L13O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_FIA_PCR_L14O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_FIA_PCR_L15O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_FIA_PCR_L16O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_FIA_PCR_L17O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_FIA_PCR_L18O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_FIA_PCR_L19O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_FIA_PCR_L20O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_FIA_PCR_L21O (BIT23 | BIT22 |= BIT21 | BIT20) +#define B_PCH_FIA_PCR_L22O (BIT27 | BIT26 |= BIT25 | BIT24) +#define B_PCH_FIA_PCR_L23O (BIT31 | BIT30 |= BIT29 | BIT28) +#define B_PCH_FIA_PCR_L24O (BIT3 | BIT2 | B= IT1 | BIT0) +#define B_PCH_FIA_PCR_L25O (BIT7 | BIT6 | B= IT5 | BIT4) +#define B_PCH_FIA_PCR_L26O (BIT11 | BIT10 |= BIT9 | BIT8) +#define B_PCH_FIA_PCR_L27O (BIT15 | BIT14 |= BIT13 | BIT12) +#define B_PCH_FIA_PCR_L28O (BIT19 | BIT18 |= BIT17 | BIT16) +#define B_PCH_FIA_PCR_L29O (BIT23 | BIT22 |= BIT21 | BIT20) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sGpio.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGp= io.h new file mode 100644 index 0000000000..3f614ba002 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpio.h @@ -0,0 +1,273 @@ +/** @file + Register names for PCH GPIO + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_GPIO_H_ +#define _PCH_REGS_GPIO_H_ + +// +// GPIO Common Private Configuration Registers +// +#define R_GPIO_PCR_REV_ID 0x00 +#define R_GPIO_PCR_CAP_LIST 0x04 +#define R_GPIO_PCR_FAMBAR 0x08 +#define R_GPIO_PCR_PADBAR 0x0C +#define B_GPIO_PCR_PADBAR 0x0000FFFF +#define R_GPIO_PCR_MISCCFG 0x10 +#define B_GPIO_PCR_MISCCFG_IRQ_ROUTE 0xFF000000 +#define N_GPIO_PCR_MISCCFG_IRQ_ROUTE 24 +#define B_GPIO_PCR_MISCCFG_GPE0_DW2 (BIT19 | BIT18 | BIT17 | BIT16) +#define N_GPIO_PCR_MISCCFG_GPE0_DW2 16 +#define B_GPIO_PCR_MISCCFG_GPE0_DW1 (BIT15 | BIT14 | BIT13 | BIT12) +#define N_GPIO_PCR_MISCCFG_GPE0_DW1 12 +#define B_GPIO_PCR_MISCCFG_GPE0_DW0 (BIT11 | BIT10 | BIT9 | BIT8) +#define N_GPIO_PCR_MISCCFG_GPE0_DW0 8 +#define B_GPIO_PCR_MISCCFG_GPSIDEDPCGEN BIT5 +#define B_GPIO_PCR_MISCCFG_GPRCOMPCDLCGEN BIT4 +#define B_GPIO_PCR_MISCCFG_GPRTCDLCGEN BIT3 +#define B_GPIO_PCR_MISCCFG_GPDPCGEN BIT1 +#define B_GPIO_PCR_MISCCFG_GPDLCGEN BIT0 + +// +// GPIO SerialBlink/PWM registers +// +#define R_GPIO_PCR_CAP_LIST_1_PWM 0x0200 +#define R_GPIO_PCR_PWMC 0x0204 +#define R_GPIO_PCR_CAP_LIST_2_SER_BLINK 0x0208 +#define R_GPIO_PCR_GP_SER_BLINK 0x020C +#define B_GPIO_PCR_GP_SER_BLINK 0x1F +#define R_GPIO_PCR_GP_SER_CMDSTS 0x0210 +#define B_GPIO_PCR_GP_SER_CMDSTS_DLS (BIT23 | BIT22) +#define N_GPIO_PCR_GP_SER_CMDSTS_DLS 22 +#define B_GPIO_PCR_GP_SER_CMDSTS_DRS 0x003F0000 +#define N_GPIO_PCR_GP_SER_CMDSTS_DRS 16 +#define B_GPIO_PCR_GP_SER_CMDSTS_BUSY BIT8 +#define B_GPIO_PCR_GP_SER_CMDSTS_GO BIT0 +#define R_GPIO_PCR_GP_SER_DATA 0x0210 + +// +// PADCFG register is split into multiple DW registers +// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers= for one pad +// +#define S_GPIO_PCR_PADCFG 0x10 + +// +// Pad Configuration Register DW0 +// + +//Pad Reset Config +#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30) +#define N_GPIO_PCR_RST_CONF 30 +#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00 +#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01 +#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02 +#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group + +//RX Pad State Select +#define B_GPIO_PCR_RX_PAD_STATE BIT29 +#define N_GPIO_PCR_RX_PAD_STATE 29 +#define V_GPIO_PCR_RX_PAD_STATE_RAW 0x00 +#define V_GPIO_PCR_RX_PAD_STATE_INT 0x01 + +//RX Raw Overrride to 1 +#define B_GPIO_PCR_RX_RAW1 BIT28 +#define N_GPIO_PCR_RX_RAW1 28 +#define V_GPIO_PCR_RX_RAW1_DIS 0x00 +#define V_GPIO_PCR_RX_RAW1_EN 0x01 + +//RX Level/Edge Configuration +#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25) +#define N_GPIO_PCR_RX_LVL_EDG 25 +#define V_GPIO_PCR_RX_LVL_EDG_LVL 0x00 +#define V_GPIO_PCR_RX_LVL_EDG_EDG 0x01 +#define V_GPIO_PCR_RX_LVL_EDG_0 0x02 +#define V_GPIO_PCR_RX_LVL_EDG_RIS_FAL 0x03 + +//RX Invert +#define B_GPIO_PCR_RXINV BIT23 +#define N_GPIO_PCR_RXINV 23 +#define V_GPIO_PCR_RXINV_NO 0x00 +#define V_GPIO_PCR_RXINV_YES 0x01 + +//GPIO Input Route IOxAPIC +#define B_GPIO_PCR_RX_APIC_ROUTE BIT20 +#define N_GPIO_PCR_RX_APIC_ROUTE 20 +#define V_GPIO_PCR_RX_APIC_ROUTE_DIS 0x00 +#define V_GPIO_PCR_RX_APIC_ROUTE_EN 0x01 + +//GPIO Input Route SCI +#define B_GPIO_PCR_RX_SCI_ROUTE BIT19 +#define N_GPIO_PCR_RX_SCI_ROUTE 19 +#define V_GPIO_PCR_RX_SCI_ROUTE_DIS 0x00 +#define V_GPIO_PCR_RX_SCI_ROUTE_EN 0x01 + +//GPIO Input Route SMI +#define B_GPIO_PCR_RX_SMI_ROUTE BIT18 +#define N_GPIO_PCR_RX_SMI_ROUTE 18 +#define V_GPIO_PCR_RX_SMI_ROUTE_DIS 0x00 +#define V_GPIO_PCR_RX_SMI_ROUTE_EN 0x01 + +//GPIO Input Route NMI +#define B_GPIO_PCR_RX_NMI_ROUTE BIT17 +#define N_GPIO_PCR_RX_NMI_ROUTE 17 +#define V_GPIO_PCR_RX_NMI_ROUTE_DIS 0x00 +#define V_GPIO_PCR_RX_NMI_ROUTE_EN 0x01 + +//GPIO Pad Mode +#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10) +#define N_GPIO_PCR_PAD_MODE 10 +#define V_GPIO_PCR_PAD_MODE_GPIO 0 +#define V_GPIO_PCR_PAD_MODE_NAT_1 1 +#define V_GPIO_PCR_PAD_MODE_NAT_2 2 +#define V_GPIO_PCR_PAD_MODE_NAT_3 3 +#define V_GPIO_PCR_PAD_MODE_NAT_4 4 // SPT-H only + +//GPIO RX Disable +#define B_GPIO_PCR_RXDIS BIT9 +#define N_GPIO_PCR_RXDIS 9 +#define V_GPIO_PCR_RXDIS_EN 0x00 +#define V_GPIO_PCR_RXDIS_DIS 0x01 + +//GPIO TX Disable +#define B_GPIO_PCR_TXDIS BIT8 +#define N_GPIO_PCR_TXDIS 8 +#define V_GPIO_PCR_TXDIS_EN 0x00 +#define V_GPIO_PCR_TXDIS_DIS 0x01 + +//GPIO RX State +#define B_GPIO_PCR_RX_STATE BIT1 +#define N_GPIO_PCR_RX_STATE 1 +#define V_GPIO_PCR_RX_STATE_LOW 0x00 +#define V_GPIO_PCR_RX_STATE_HIGH 0x01 + +//GPIO TX State +#define B_GPIO_PCR_TX_STATE BIT0 +#define N_GPIO_PCR_TX_STATE 0 +#define V_GPIO_PCR_TX_STATE_LOW 0x00 +#define V_GPIO_PCR_TX_STATE_HIGH 0x01 + +// +// Pad Configuration Register DW1 +// + +//Padtol +#define B_GPIO_PCR_PADTOL BIT25 +#define N_GPIO_PCR_PADTOL 25 +#define V_GPIO_PCR_PADTOL_NONE 0x00 +#define V_GPIO_PCR_PADTOL_CLEAR 0x00 +#define V_GPIO_PCR_PADTOL_SET 0x01 + +//Termination +#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10) +#define N_GPIO_PCR_TERM 10 +#define V_GPIO_PCR_TERM_WPD_NONE 0x00 +#define V_GPIO_PCR_TERM_WPD_5K 0x02 +#define V_GPIO_PCR_TERM_WPD_20K 0x04 +#define V_GPIO_PCR_TERM_WPU_NONE 0x08 +#define V_GPIO_PCR_TERM_WPU_1K 0x09 +#define V_GPIO_PCR_TERM_WPU_2K 0x0B +#define V_GPIO_PCR_TERM_WPU_5K 0x0A +#define V_GPIO_PCR_TERM_WPU_20K 0x0C +#define V_GPIO_PCR_TERM_WPU_1K_2K 0x0D +#define V_GPIO_PCR_TERM_NATIVE 0x0F + +//Interrupt number +#define B_GPIO_PCR_INTSEL 0x7F +#define N_GPIO_PCR_INTSEL 0 + +// +//Debounce +#define B_GPIO_PCR_DEBOUNCE (BIT4 | BIT3 | BIT2 | BIT1) +#define N_GPIO_PCR_DEBOUNCE 1 + +//Debounce Enable +#define B_GPIO_PCR_DEBEN BIT0 +#define N_GPIO_PCR_DEBEN 0 + +// +// Ownership +// +#define V_GPIO_PCR_OWN_GPIO 0x01 +#define V_GPIO_PCR_OWN_ACPI 0x00 + +// +// GPE +// +#define V_GPIO_PCR_GPE_EN 0x01 +#define V_GPIO_PCR_GPE_DIS 0x00 +// +// SMI +// +#define V_GPIO_PCR_SMI_EN 0x01 +#define V_GPIO_PCR_SMI_DIS 0x00 +// +// NMI +// +#define V_GPIO_PCR_NMI_EN 0x01 +#define V_GPIO_PCR_NMI_DIS 0x00 + +// +// GPIO native features pins data +// +#define PCH_GPIO_HDA_LINK_NUMBER_OF_PINS 6 +#define PCH_GPIO_HDA_DMIC_NUMBER_OF_PINS 2 +#define PCH_GPIO_HDA_SSP_NUMBER_OF_PINS 4 +#define PCH_GPIO_HDA_SNDW_NUMBER_OF_PINS 2 +#define PCH_GPIO_SMBUS_NUMBER_OF_PINS 2 +#define PCH_GPIO_CPU_GP_NUMBER_OF_PINS 4 +#define PCH_GPIO_EDP_NUMBER_OF_PINS 4 +#define PCH_GPIO_DDSP_HPD_NUMBER_OF_PINS 4 +#define PCH_GPIO_DDP_NUMBER_OF_INTERFACES 4 +#define PCH_GPIO_DDP_NUMBER_OF_PINS 2 +#define PCH_GPIO_CNVI_UART_NUMBER_OF_PINS 4 +#define PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS 4 +#define PCH_GPIO_CNVI_BRI_RGI_NUMBER_OF_PINS 4 + + +/// +/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL +/// Below defines are to be used internally by PCH SMI dispatcher only +/// +#define PCH_GPIO_NUM_SUPPORTED_GPIS 512 +#define S_GPIO_PCR_GP_SMI_EN 4 +#define S_GPIO_PCR_GP_SMI_STS 4 + +/// +/// Groups mapped to 2-tier General Purpose Event will all be under +/// one master GPE_111 (0x6F) +/// +#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sGpioCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sGpioCnl.h new file mode 100644 index 0000000000..140c758730 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsGpioCn= l.h @@ -0,0 +1,694 @@ +/** @file + Register names for GPIO + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_GPIO_CNL_H_ +#define _PCH_REGS_GPIO_CNL_H_ + +// +// PCH-LP GPIO +// +#define CNL_PCH_LP_GPIO_GROUP_MAX 15 + +#define CNL_PCH_LP_GPIO_GPP_A_PAD_MAX 25 +#define CNL_PCH_LP_GPIO_GPP_B_PAD_MAX 26 +#define CNL_PCH_LP_GPIO_GPP_C_PAD_MAX 24 +#define CNL_PCH_LP_GPIO_GPP_D_PAD_MAX 24 +#define CNL_PCH_LP_GPIO_GPP_E_PAD_MAX 24 +#define CNL_PCH_LP_GPIO_GPP_F_PAD_MAX 24 +#define CNL_PCH_LP_GPIO_GPP_G_PAD_MAX 8 +#define CNL_PCH_LP_GPIO_GPP_H_PAD_MAX 24 +#define CNL_PCH_LP_GPIO_GPD_PAD_MAX 16 +#define CNL_PCH_LP_GPIO_VGPIO_PAD_MAX 40 +#define CNL_PCH_LP_GPIO_SPI_PAD_MAX 9 +#define CNL_PCH_LP_GPIO_AZA_PAD_MAX 8 +#define CNL_PCH_LP_GPIO_CPU_PAD_MAX 11 +#define CNL_PCH_LP_GPIO_JTAG_PAD_MAX 9 +#define CNL_PCH_LP_GPIO_HVMOS_PAD_MAX 6 + +// +// PCH-H GPIO +// +#define CNL_PCH_H_GPIO_GROUP_MAX 17 + +#define CNL_PCH_H_GPIO_GPP_A_PAD_MAX 25 +#define CNL_PCH_H_GPIO_GPP_B_PAD_MAX 26 +#define CNL_PCH_H_GPIO_GPP_C_PAD_MAX 24 +#define CNL_PCH_H_GPIO_GPP_D_PAD_MAX 24 +#define CNL_PCH_H_GPIO_GPP_E_PAD_MAX 13 +#define CNL_PCH_H_GPIO_GPP_F_PAD_MAX 24 +#define CNL_PCH_H_GPIO_GPP_G_PAD_MAX 8 +#define CNL_PCH_H_GPIO_GPP_H_PAD_MAX 24 +#define CNL_PCH_H_GPIO_GPP_I_PAD_MAX 18 +#define CNL_PCH_H_GPIO_GPP_J_PAD_MAX 12 +#define CNL_PCH_H_GPIO_GPP_K_PAD_MAX 24 +#define CNL_PCH_H_GPIO_GPD_PAD_MAX 16 +#define CNL_PCH_H_GPIO_VGPIO_PAD_MAX 40 +#define CNL_PCH_H_GPIO_SPI_PAD_MAX 9 +#define CNL_PCH_H_GPIO_AZA_PAD_MAX 8 +#define CNL_PCH_H_GPIO_CPU_PAD_MAX 11 +#define CNL_PCH_H_GPIO_JTAG_PAD_MAX 9 + +// +// PCH-LP GPIO registers +// +// +// GPIO Community Common Private Configuration Registers +// +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_A 0x0 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_B 0x1 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_C 0xC +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_D 0x4 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_E 0xD +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_F 0x5 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_G 0x2 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_H 0x6 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPD 0x9 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_VGPIO 0x7 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_SPI 0x3 +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_AZA 0xA +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_CPU 0xB +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_JTAG 0xE +#define V_CNL_PCH_LP_GPIO_PCR_MISCCFG_GPE0_HVMOS 0xF + +// +// GPIO Community 0 Private Configuration Registers +// +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x20 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x30 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_PAD_OWN 0x40 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_PAD_OWN 0x44 + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x80 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x84 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x88 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x8C +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_PADCFGLOCK 0x90 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_PADCFGLOCKTX 0x94 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_PADCFGLOCK 0x98 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_PADCFGLOCKTX 0x9C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB0 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB4 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_HOSTSW_OWN 0xB8 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_HOSTSW_OWN 0xBC + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0100 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0104 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_IS 0x0108 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_IS 0x010C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0120 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0124 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_IE 0x0128 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_IE 0x012C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0140 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0144 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_GPE_STS 0x0148 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_GPE_STS 0x014C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0160 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0164 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_GPE_EN 0x0168 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_GPE_EN 0x016C + +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_SMI_STS 0x0180 // Not suppor= ted setting for this group +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0184 +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_SMI_STS 0x0188 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_SPI_SMI_STS 0x018C // Not suppor= ted setting for this group + +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_SMI_EN 0x01A0 // Not suppor= ted setting for this group +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A4 +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_SMI_EN 0x01A8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_SPI_SMI_EN 0x01AC // Not suppor= ted setting for this group + +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_NMI_STS 0x01C0 // Not suppor= ted setting for this group +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C4 +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_NMI_STS 0x01C8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_SPI_NMI_STS 0x01CC // Not suppor= ted setting for this group + +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_NMI_EN 0x01E0 // Not suppor= ted setting for this group +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E4 +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_NMI_EN 0x01E8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_SPI_NMI_EN 0x01EC // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x600 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x790 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_G_PADCFG_OFFSET 0x930 +#define R_CNL_PCH_LP_GPIO_PCR_SPI_PADCFG_OFFSET 0x9B0 + +// +// GPIO Community 1 Private Configuration Registers +// +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x20 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x30 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x3C +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_PAD_OWN 0x48 + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x80 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x84 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x90 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x94 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_0_PADCFGLOCK 0x98 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_0_PADCFGLOCKTX 0x9C +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_1_PADCFGLOCK 0xA0 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_1_PADCFGLOCKTX 0xA4 + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB0 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB8 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_HOSTSW_OWN 0xBC + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0100 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0108 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_IS 0x010C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0120 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0128 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_IE 0x012C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0140 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0148 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_GPE_STS 0x014C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0160 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0168 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_GPE_EN 0x016C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0180 +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_SMI_STS 0x0184 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_SMI_STS 0x0188 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_SMI_STS 0x018C // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A0 +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_SMI_EN 0x01A4 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_SMI_EN 0x01A8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_SMI_EN 0x01AC // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C0 +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_NMI_STS 0x01C4 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_NMI_STS 0x01C8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_NMI_STS 0x01CC // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E0 +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_NMI_EN 0x01E4 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_NMI_EN 0x01E8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_NMI_EN 0x01EC // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x600 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x790 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x910 +#define R_CNL_PCH_LP_GPIO_PCR_VGPIO_PADCFG_OFFSET 0xA90 + +// +// GPIO Community 2 Private Configuration Registers +// +#define R_CNL_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20 + +#define R_CNL_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80 +#define R_CNL_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84 + +#define R_CNL_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0 + +#define R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100 +#define R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120 + +#define R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140 +#define R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160 + +//#define R_CNL_PCH_LP_GPIO_PCR_GPD_SMI_STS 0x0180 // Not supporte= d setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_GPD_SMI_EN 0x01A0 // Not supporte= d setting for this group + +//#define R_CNL_PCH_LP_GPIO_PCR_GPD_NMI_STS 0x01C0 // Not supporte= d setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_GPD_NMI_EN 0x01E0 // Not supporte= d setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x600 + +// +// GPIO Community 3 Private Configuration Registers +// +#define R_CNL_PCH_LP_GPIO_PCR_AZA_PAD_OWN 0x20 +#define R_CNL_PCH_LP_GPIO_PCR_CPU_PAD_OWN 0x24 + +#define R_CNL_PCH_LP_GPIO_PCR_AZA_PADCFGLOCK 0x80 +#define R_CNL_PCH_LP_GPIO_PCR_AZA_PADCFGLOCKTX 0x84 +#define R_CNL_PCH_LP_GPIO_PCR_CPU_PADCFGLOCK 0x88 +#define R_CNL_PCH_LP_GPIO_PCR_CPU_PADCFGLOCKTX 0x8C + +#define R_CNL_PCH_LP_GPIO_PCR_AZA_HOSTSW_OWN 0xB0 +#define R_CNL_PCH_LP_GPIO_PCR_CPU_HOSTSW_OWN 0xB4 + +#define R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_IS 0x0100 +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_GPI_IS 0x0104 // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_IE 0x0120 +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_GPI_IE 0x0124 // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_GPE_STS 0x0140 +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_GPI_GPE_STS 0x0144 // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_GPE_EN 0x0160 +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_GPI_GPE_EN 0x0164 // Not suppor= ted setting for this group + +//#define R_CNL_PCH_LP_GPIO_PCR_AZA_SMI_STS 0x0180 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_SMI_STS 0x0184 // Not suppor= ted setting for this group + +//#define R_CNL_PCH_LP_GPIO_PCR_AZA_SMI_EN 0x01A0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_SMI_EN 0x01A4 // Not suppor= ted setting for this group + +//#define R_CNL_PCH_LP_GPIO_PCR_AZA_NMI_STS 0x01C0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_NMI_STS 0x01C4 // Not suppor= ted setting for this group + +//#define R_CNL_PCH_LP_GPIO_PCR_AZA_NMI_EN 0x01E0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_CPU_NMI_EN 0x01E4 // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_AZA_PADCFG_OFFSET 0x600 +#define R_CNL_PCH_LP_GPIO_PCR_CPU_PADCFG_OFFSET 0x680 + +// +// GPIO Community 4 Private Configuration Registers +// +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x2C +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_PAD_OWN 0x38 +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_PAD_OWN 0x40 + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x88 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x8C +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_PADCFGLOCK 0x90 +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_PADCFGLOCKTX 0x94 +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_PADCFGLOCK 0x98 +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_PADCFGLOCKTX 0x9C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xB4 +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_HOSTSW_OWN 0xB8 +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_HOSTSW_OWN 0xBC + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x0104 +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_GPI_IS 0x0108 // Not suppor= ted setting for this group +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_IS 0x010C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x0124 +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_GPI_IE 0x0128 // Not suppor= ted setting for this group +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_IE 0x012C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x0144 +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_GPI_GPE_STS 0x0148 // Not suppor= ted setting for this group +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_GPE_STS 0x014C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x0164 +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_GPI_GPE_EN 0x0168 // Not suppor= ted setting for this group +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_GPE_EN 0x016C + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x0184 +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_SMI_STS 0x0188 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_SMI_STS 0x018C // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01A4 +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_SMI_EN 0x01A8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_SMI_EN 0x01AC // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01C4 +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_NMI_STS 0x01C8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_NMI_STS 0x01CC // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01E4 +//#define R_CNL_PCH_LP_GPIO_PCR_JTAG_NMI_EN 0x01E8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_NMI_EN 0x01EC // Not suppor= ted setting for this group + +#define R_CNL_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x600 +#define R_CNL_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0x780 +#define R_CNL_PCH_LP_GPIO_PCR_JTAG_PADCFG_OFFSET 0x900 +#define R_CNL_PCH_LP_GPIO_PCR_HVMOS_PADCFG_OFFSET 0x990 + +// +// PCH-H GPIO registers +// +// +// GPIO Community Common Private Configuration Registers +// +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_A 0x0 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_B 0x1 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_C 0x2 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_D 0x3 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_E 0x6 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_F 0x7 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_G 0x4 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_H 0x8 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_K 0x9 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_I 0xA +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_J 0xB +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_GPD 0x5 +#define V_CNL_PCH_H_GPIO_PCR_MISCCFG_GPE0_VGPIO 0xD + +// +// GPIO Community 0 Private Configuration Registers +// +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_PAD_OWN 0x20 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_PAD_OWN 0x30 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_PADCFGLOCK 0x80 +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x84 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_PADCFGLOCK 0x88 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x8C + +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_HOSTSW_OWN 0xC0 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_HOSTSW_OWN 0xC4 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_IS 0x0100 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_IS 0x0104 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_IE 0x0120 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_IE 0x0124 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0140 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0144 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0160 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0164 + +//#define R_CNL_PCH_H_GPIO_PCR_GPP_A_SMI_STS 0x0180 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_SMI_STS 0x0184 + +//#define R_CNL_PCH_H_GPIO_PCR_GPP_A_SMI_EN 0x01A0 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_SMI_EN 0x01A4 + +//#define R_CNL_PCH_H_GPIO_PCR_GPP_A_NMI_STS 0x01C0 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_NMI_STS 0x01C4 + +//#define R_CNL_PCH_H_GPIO_PCR_GPP_A_NMI_EN 0x01E0 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_NMI_EN 0x01E4 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x600 +#define R_CNL_PCH_H_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x790 + +// +// GPIO Community 1 Private Configuration Registers +// +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_PAD_OWN 0x20 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_PAD_OWN 0x2C +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_PAD_OWN 0x38 +#define R_CNL_PCH_H_GPIO_PCR_AZA_PAD_OWN 0x3C +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_PAD_OWN 0x40 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_PADCFGLOCK 0x80 +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_PADCFGLOCK 0x88 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x8C +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_PADCFGLOCK 0x90 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_PADCFGLOCKTX 0x94 +#define R_CNL_PCH_H_GPIO_PCR_AZA_PADCFGLOCK 0x98 +#define R_CNL_PCH_H_GPIO_PCR_AZA_PADCFGLOCKTX 0x9C +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_0_PADCFGLOCK 0xA0 +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_0_PADCFGLOCKTX 0xA4 +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_1_PADCFGLOCK 0xA8 +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_1_PADCFGLOCKTX 0xAC + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_HOSTSW_OWN 0xC0 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_HOSTSW_OWN 0xC4 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_HOSTSW_OWN 0xC8 +#define R_CNL_PCH_H_GPIO_PCR_AZA_HOSTSW_OWN 0xCC +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_HOSTSW_OWN 0xD0 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_IS 0x0100 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_IS 0x0104 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_IS 0x0108 +//#define R_CNL_PCH_H_GPIO_PCR_AZA_GPI_IS 0x010C // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_IS 0x0110 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_IE 0x0120 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_IE 0x0124 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_IE 0x0128 +//#define R_CNL_PCH_H_GPIO_PCR_AZA_GPI_IE 0x012C // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_IE 0x0130 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0144 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_GPE_STS 0x0148 +//#define R_CNL_PCH_H_GPIO_PCR_AZA_GPI_GPE_STS 0x014C // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_GPE_STS 0x0150 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0164 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_GPE_EN 0x0168 +//#define R_CNL_PCH_H_GPIO_PCR_AZA_GPI_GPE_EN 0x016C // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_GPE_EN 0x0170 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_SMI_STS 0x0180 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_SMI_STS 0x0184 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_SMI_STS 0x0188 +//#define R_CNL_PCH_H_GPIO_PCR_AZA_SMI_STS 0x018C // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_VGPIO_SMI_STS 0x0190 // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_SMI_EN 0x01A0 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_SMI_EN 0x01A4 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_SMI_EN 0x01A8 +//#define R_CNL_PCH_H_GPIO_PCR_AZA_SMI_EN 0x01AC // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_VGPIO_SMI_EN 0x01B0 // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_NMI_STS 0x01C0 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_NMI_STS 0x01C4 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_G_NMI_STS 0x01C8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_AZA_NMI_STS 0x01CC // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_VGPIO_NMI_STS 0x01D0 // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_NMI_EN 0x01E0 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_NMI_EN 0x01E4 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_G_NMI_EN 0x01E8 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_AZA_NMI_EN 0x01EC // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_VGPIO_NMI_EN 0x01F0 // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x600 +#define R_CNL_PCH_H_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x780 +#define R_CNL_PCH_H_GPIO_PCR_GPP_G_PADCFG_OFFSET 0x900 +#define R_CNL_PCH_H_GPIO_PCR_AZA_PADCFG_OFFSET 0x980 +#define R_CNL_PCH_H_GPIO_PCR_VGPIO_PADCFG_OFFSET 0xA00 + +// +// GPIO Community 2 Private Configuration Registers +// + +#define R_CNL_PCH_H_GPIO_PCR_GPD_PAD_OWN 0x20 + +#define R_CNL_PCH_H_GPIO_PCR_GPD_PADCFGLOCK 0x80 +#define R_CNL_PCH_H_GPIO_PCR_GPD_PADCFGLOCKTX 0x84 + +#define R_CNL_PCH_H_GPIO_PCR_GPD_HOSTSW_OWN 0xB0 + +#define R_CNL_PCH_H_GPIO_PCR_GPD_GPI_IS 0x0100 + +#define R_CNL_PCH_H_GPIO_PCR_GPD_GPI_IE 0x0120 + +#define R_CNL_PCH_H_GPIO_PCR_GPD_GPI_GPE_STS 0x0140 + +#define R_CNL_PCH_H_GPIO_PCR_GPD_GPI_GPE_EN 0x0160 + +//#define R_CNL_PCH_H_GPIO_PCR_GPD_SMI_STS 0x0180 // Not supporte= d setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_GPD_SMI_EN 0x01A0 // Not supporte= d setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_GPD_NMI_STS 0x01C0 // Not supporte= d setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_GPD_NMI_EN 0x01E0 // Not supporte= d setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPD_PADCFG_OFFSET 0x600 + +// +// GPIO Community 3 Private Configuration Registers +// +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_PAD_OWN 0x20 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_PAD_OWN 0x2C +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_PAD_OWN 0x38 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_PAD_OWN 0x40 +#define R_CNL_PCH_H_GPIO_PCR_SPI_PAD_OWN 0x4C + +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_PADCFGLOCK 0x80 +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_PADCFGLOCKTX 0x84 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_PADCFGLOCK 0x88 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_PADCFGLOCK 0x90 +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x94 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_PADCFGLOCK 0x98 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x9C +#define R_CNL_PCH_H_GPIO_PCR_SPI_PADCFGLOCK 0xA0 +#define R_CNL_PCH_H_GPIO_PCR_SPI_PADCFGLOCKTX 0xA4 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_HOSTSW_OWN 0xC0 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_HOSTSW_OWN 0xC4 +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_HOSTSW_OWN 0xC8 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_HOSTSW_OWN 0xCC +#define R_CNL_PCH_H_GPIO_PCR_SPI_HOSTSW_OWN 0xD0 + +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_IS 0x0100 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_IS 0x0104 +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_IS 0x0108 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_IS 0x010C +//#define R_CNL_PCH_H_GPIO_PCR_SPI_GPI_IS 0x0110 // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_IE 0x0120 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_IE 0x0124 +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_IE 0x0128 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_IE 0x012C +//#define R_CNL_PCH_H_GPIO_PCR_SPI_GPI_IE 0x0130 // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_GPE_STS 0x0140 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144 +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_GPE_STS 0x0148 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_GPE_STS 0x014C +//#define R_CNL_PCH_H_GPIO_PCR_SPI_GPI_GPE_STS 0x0150 // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_GPE_EN 0x0160 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164 +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_GPE_EN 0x0168 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_GPE_EN 0x016C +//#define R_CNL_PCH_H_GPIO_PCR_SPI_GPI_GPE_EN 0x0170 // Not suppor= ted setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_GPP_K_SMI_STS 0x0180 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_GPP_H_SMI_STS 0x0184 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_SMI_STS 0x0188 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_F_SMI_STS 0x018C // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_SPI_SMI_STS 0x0190 // Not suppor= ted setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_GPP_K_SMI_EN 0x01A0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_GPP_H_SMI_EN 0x01A4 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_SMI_EN 0x01A8 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_F_SMI_EN 0x01AC // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_SPI_SMI_EN 0x01B0 // Not suppor= ted setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_GPP_K_NMI_STS 0x01C0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_GPP_H_NMI_STS 0x01C4 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_NMI_STS 0x01C8 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_F_NMI_STS 0x01CC // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_SPI_NMI_STS 0x01D0 // Not suppor= ted setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_GPP_K_NMI_EN 0x01E0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_GPP_H_NMI_EN 0x01E4 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_NMI_EN 0x01E8 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_F_NMI_EN 0x01EC // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_SPI_NMI_EN 0x01F0 // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_GPP_K_PADCFG_OFFSET 0x600 +#define R_CNL_PCH_H_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780 +#define R_CNL_PCH_H_GPIO_PCR_GPP_E_PADCFG_OFFSET 0x900 +#define R_CNL_PCH_H_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x9D0 +#define R_CNL_PCH_H_GPIO_PCR_SPI_PADCFG_OFFSET 0xB50 + +// +// GPIO Community 4 Private Configuration Registers +// +#define R_CNL_PCH_H_GPIO_PCR_CPU_PAD_OWN 0x20 +#define R_CNL_PCH_H_GPIO_PCR_JTAG_PAD_OWN 0x28 +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_PAD_OWN 0x30 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_PAD_OWN 0x3C + +#define R_CNL_PCH_H_GPIO_PCR_CPU_PADCFGLOCK 0x80 +#define R_CNL_PCH_H_GPIO_PCR_CPU_PADCFGLOCKTX 0x84 +#define R_CNL_PCH_H_GPIO_PCR_JTAG_PADCFGLOCK 0x88 +#define R_CNL_PCH_H_GPIO_PCR_JTAG_PADCFGLOCKTX 0x8C +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_PADCFGLOCK 0x90 +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_PADCFGLOCKTX 0x94 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_PADCFGLOCK 0x98 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_PADCFGLOCKTX 0x9C + +#define R_CNL_PCH_H_GPIO_PCR_CPU_HOSTSW_OWN 0xC0 +#define R_CNL_PCH_H_GPIO_PCR_JTAG_HOSTSW_OWN 0xC4 +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_HOSTSW_OWN 0xC8 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_HOSTSW_OWN 0xCC + +//#define R_CNL_PCH_H_GPIO_PCR_CPU_GPI_IS 0x0100 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_GPI_IS 0x0104 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_IS 0x0108 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_IS 0x010C + +//#define R_CNL_PCH_H_GPIO_PCR_CPU_GPI_IE 0x0120 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_GPI_IE 0x0124 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_IE 0x0128 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_IE 0x012C + +//#define R_CNL_PCH_H_GPIO_PCR_CPU_GPI_GPE_STS 0x0140 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_GPI_GPE_STS 0x0144 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_GPE_STS 0x0148 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_GPE_STS 0x014C + +//#define R_CNL_PCH_H_GPIO_PCR_CPU_GPI_GPE_EN 0x0160 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_GPI_GPE_EN 0x0164 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_GPE_EN 0x0168 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_GPE_EN 0x016C + +//#define R_CNL_PCH_H_GPIO_PCR_CPU_SMI_STS 0x0180 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_SMI_STS 0x0184 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_SMI_STS 0x0188 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_J_SMI_STS 0x018C // Not suppor= ted setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_CPU_SMI_EN 0x01A0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_SMI_EN 0x01A4 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_SMI_EN 0x01A8 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_J_SMI_EN 0x01AC // Not suppor= ted setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_CPU_NMI_STS 0x01C0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_NMI_STS 0x01C4 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_NMI_STS 0x01C8 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_J_NMI_STS 0x01CC // Not suppor= ted setting for this group + +//#define R_CNL_PCH_H_GPIO_PCR_CPU_NMI_EN 0x01E0 // Not suppor= ted setting for this group +//#define R_CNL_PCH_H_GPIO_PCR_JTAG_NMI_EN 0x01E4 // Not suppor= ted setting for this group +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_NMI_EN 0x01E8 +//#define R_CNL_PCH_H_GPIO_PCR_GPP_J_NMI_EN 0x01EC // Not suppor= ted setting for this group + +#define R_CNL_PCH_H_GPIO_PCR_CPU_PADCFG_OFFSET 0x600 +#define R_CNL_PCH_H_GPIO_PCR_JTAG_PADCFG_OFFSET 0x6B0 +#define R_CNL_PCH_H_GPIO_PCR_GPP_I_PADCFG_OFFSET 0x740 +#define R_CNL_PCH_H_GPIO_PCR_GPP_J_PADCFG_OFFSET 0x860 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sHda.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHda= .h new file mode 100644 index 0000000000..bc099d9662 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHda.h @@ -0,0 +1,204 @@ +/** @file + Register names for PCH High Definition Audio device. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_HDA_H_ +#define _PCH_REGS_HDA_H_ + +// +// HD-A Controller Registers (D31:F3) +// +// PCI Configuration Space Registers +// +#define PCI_DEVICE_NUMBER_PCH_HDA 31 +#define PCI_FUNCTION_NUMBER_PCH_HDA 3 + +#define R_HDA_CFG_PI 0x09 +#define V_HDA_CFG_PI_ADSP_UAA 0x80 +#define R_HDA_CFG_SCC 0x0A +#define V_HDA_CFG_SCC_ADSP 0x01 +#define R_HDA_CFG_HDALBA 0x10 +#define B_HDA_CFG_HDALBA_LBA 0xFFFFC000 +#define V_HDA_CFG_HDBAR_SIZE (1 << 14) +#define R_HDA_CFG_HDAUBA 0x14 +#define B_HDA_CFG_HDAUBA_UBA 0xFFFFFFFF +#define R_HDA_CFG_CGCTL 0x48 +#define B_HDA_CFG_CGCTL_RSMTCGE BIT18 +#define B_HDA_CFG_CGCTL_MISCBDCGE BIT6 +#define R_HDA_CFG_PC 0x52 +#define V_HDA_CFG_PC_PMES 0x18 +#define N_HDA_CFG_PC_PMES 11 +#define R_HDA_CFG_PCS 0x54 +#define B_HDA_CFG_PCS_PMEE BIT8 +#define B_HDA_CFG_PCS_PS (BIT1 | BIT0) +#define R_HDA_CFG_MMC 0x62 +#define B_HDA_CFG_MMC_ME BIT0 +#define R_HDA_CFG_DEVC 0x78 +#define B_HDA_CFG_DEVC_NSNPEN BIT11 +#define R_HDA_CFG_SEM1 0xC0 +#define B_HDA_CFG_SEM1_LFLCS BIT24 +#define B_HDA_CFG_SEM1_BLKC3DIS BIT17 +#define B_HDA_CFG_SEM1_TMODE BIT12 +#define B_HDA_CFG_SEM1_FIFORDYSEL (BIT10 | BIT9) +#define R_HDA_CFG_SEM2 0xC4 +#define B_HDA_CFG_SEM2_BSMT (BIT27 | BIT26) +#define V_HDA_CFG_SEM2_BSMT 0x1 +#define N_HDA_CFG_SEM2_BSMT 26 +#define B_HDA_CFG_SEM2_VC0SNR BIT24 +#define B_HDA_CFG_SEM2_DUM BIT23 +#define R_HDA_CFG_SEM3L 0xC8 +#define B_HDA_CFG_SEM3L_ISL1EXT2 (BIT21 | BIT20) +#define V_HDA_CFG_SEM3L_ISL1EXT2 0x2 +#define N_HDA_CFG_SEM3L_ISL1EXT2 20 +#define R_HDA_CFG_SEM4L 0xD0 +#define B_HDA_CFG_SEM4L_OSL1EXT2 (BIT21 | BIT20) +#define V_HDA_CFG_SEM4L_OSL1EXT2 0x3 +#define N_HDA_CFG_SEM4L_OSL1EXT2 20 + +// +// Memory Space Registers +// +// +// Resides in 'HD Audio Global Registers' (0000h) +// +#define R_HDA_MEM_GCAP 0x00 +#define R_HDA_MEM_GCTL 0x08 +#define B_HDA_MEM_GCTL_CRST BIT0 + +#define R_HDA_MEM_OUTPAY 0x04 +#define R_HDA_MEM_INPAY 0x06 +#define V_HDA_MEM_INPAY_DEFAULT 0x1C + +#define R_HDA_MEM_WAKEEN 0x0C +#define B_HDA_MEM_WAKEEN_SDI_3 BIT3 +#define B_HDA_MEM_WAKEEN_SDI_2 BIT2 +#define B_HDA_MEM_WAKEEN_SDI_1 BIT1 +#define B_HDA_MEM_WAKEEN_SDI_0 BIT0 + +#define R_HDA_MEM_WAKESTS 0x0E +#define B_HDA_MEM_WAKESTS_SDIN3 BIT3 +#define B_HDA_MEM_WAKESTS_SDIN2 BIT2 +#define B_HDA_MEM_WAKESTS_SDIN1 BIT1 +#define B_HDA_MEM_WAKESTS_SDIN0 BIT0 + +// +// Resides in 'HD Audio Controller Registers' (0030h) +// +#define R_HDA_MEM_IC 0x60 +#define R_HDA_MEM_IR 0x64 +#define R_HDA_MEM_ICS 0x68 +#define B_HDA_MEM_ICS_IRV BIT1 +#define B_HDA_MEM_ICS_ICB BIT0 + +// +// Resides in 'HD Audio Processing Pipe Capability Structure' (0800h) +// +#define R_HDA_MEM_PPC 0x0800 // Processing Pipe Ca= pability Structure (Memory Space, offset 0800h) +#define R_HDA_MEM_PPCTL (R_HDA_MEM_PPC + 0x04) +#define B_HDA_MEM_PPCTL_GPROCEN BIT30 + +// +// Resides in 'HD Audio Multiple Links Capability Structure' (0C00h) +// +#define HDA_HDALINK_INDEX 0 +#define HDA_IDISPLINK_INDEX 1 + +#define R_HDA_MEM_MLC 0x0C00 // Multiple Links Cap= ability Structure (Memory Space, offset 0C00h) +#define R_HDA_MEM_LCTLX(x) (R_HDA_MEM_MLC + (0x40 + (0x= 40 * (x)) + 0x04)) // x - Link index: 0 - HDA Link, 1 - iDisp Link +#define B_HDA_MEM_LCTLX_CPA BIT23 +#define B_HDA_MEM_LCTLX_SPA BIT16 +#define N_HDA_MEM_LCTLX_SCF 0 +#define V_HDA_MEM_LCTLX_SCF_6MHZ 0x0 +#define V_HDA_MEM_LCTLX_SCF_12MHZ 0x1 +#define V_HDA_MEM_LCTLX_SCF_24MHZ 0x2 +#define V_HDA_MEM_LCTLX_SCF_48MHZ 0x3 +#define V_HDA_MEM_LCTLX_SCF_96MHZ 0x4 + +// +// Resides in 'HD Audio Vendor Specific Registers' (1000h) +// +#define R_HDA_MEM_LTRC 0x1048 +#define V_HDA_MEM_LTRC_GB 0x29 +#define N_HDA_MEM_LTRC_GB 0 +#define R_HDA_MEM_PCE 0x104B +#define B_HDA_MEM_PCE_D3HE BIT2 + +// +// Private Configuration Space Registers +// +// +// Resides in IOSF & Fabric Configuration Registers (000h) +// +#define R_HDA_PCR_TTCCFG 0xE4 +#define B_HDA_PCR_TTCCFG_HCDT BIT1 + +// +// Resides in PCI & Codec Configuration Registers (500h) +// +#define R_HDA_PCR_PCICDCCFG 0x500 // PCI & Codec Configura= tion Registers (PCR, offset 500h) +#define B_HDA_PCR_PCICDCCFG_ACPIIN 0x0000FF00 +#define N_HDA_PCR_PCICDCCFG_ACPIIN 8 +#define R_HDA_PCR_FNCFG (R_HDA_PCR_PCICDCCFG + 0x30) +#define B_HDA_PCR_FNCFG_PGD BIT5 +#define B_HDA_PCR_FNCFG_BCLD BIT4 +#define B_HDA_PCR_FNCFG_CGD BIT3 +#define B_HDA_PCR_FNCFG_ADSPD BIT2 +#define B_HDA_PCR_FNCFG_HDASD BIT0 +#define R_HDA_PCR_CDCCFG (R_HDA_PCR_PCICDCCFG + 0x34) +#define B_HDA_PCR_CDCCFG_DIS_SDIN2 BIT2 + +// +// Resides in Power Management & EBB Configuration Registers (600h) +// +#define R_HDA_PCR_PWRMANCFG 0x600 // Power Management & EB= B Configuration Registers (PCR, offset 600h) +#define R_HDA_PCR_APLLP0 (R_HDA_PCR_PWRMANCFG + 0x10) +#define V_HDA_PCR_APLLP0 0xFC1E0000 +#define R_HDA_PCR_APLLP1 (R_HDA_PCR_PWRMANCFG + 0x14) +#define V_HDA_PCR_APLLP1 0x00003F00 +#define R_HDA_PCR_APLLP2 (R_HDA_PCR_PWRMANCFG + 0x18) +#define V_HDA_PCR_APLLP2 0x0000011D +#define R_HDA_PCR_IOBCTL (R_HDA_PCR_PWRMANCFG + 0x1C) +#define B_HDA_PCR_IOBCTL_OSEL (BIT9 | BIT8) +#define V_HDA_PCR_IOBCTL_OSEL_HDALINK 0 +#define V_HDA_PCR_IOBCTL_OSEL_HDALINK_I2S 1 +#define V_HDA_PCR_IOBCTL_OSEL_I2S 3 +#define N_HDA_PCR_IOBCTL_OSEL 8 +#define B_HDA_PCR_IOBCTL_VSEL BIT1 +#define R_HDA_PCR_PTDC (R_HDA_PCR_PWRMANCFG + 0x28) +#define B_HDA_PCR_PTDC_SRMIW (BIT6 | BIT5 | BIT4) + + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sHsio.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHs= io.h new file mode 100644 index 0000000000..0cd69eb299 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsHsio.h @@ -0,0 +1,170 @@ +/** @file + Register definition for HSIO + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_HSIO_H_ +#define _PCH_REGS_HSIO_H_ + +#define B_HSIO_PCR_ACCESS_TYPE (BIT15 | BIT14) +#define N_HSIO_PCR_ACCESS_TYPE 14 +#define V_HSIO_PCR_ACCESS_TYPE_BDCAST (BIT15 | BIT14) +#define V_HSIO_PCR_ACCESS_TYPE_MULCAST BIT15 +#define B_HSIO_PCR_LANE_GROUP_NO (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9) +#define B_HSIO_PCR_FUNCTION_NO (BIT8 | BIT7) +#define N_HSIO_PCR_FUNCTION_NO 7 +#define B_HSIO_PCR_REG_OFFSET (BIT6 | BIT5 | B= IT4 | BIT3 | BIT2 | BIT1 | BIT0) + +#define V_HSIO_PCR_ACCESS_TYPE_BCAST 0x03 +#define V_HSIO_PCR_ACCESS_TYPE_MCAST 0x02 +#define V_HSIO_PCR_ACCESS_TYPE_UCAST 0x00 + +#define V_HSIO_PCR_LANE_GROUP_NO_CMN_LANE 0x00 + +#define V_HSIO_PCR_FUNCTION_NO_PCS 0x00 +#define V_HSIO_PCR_FUNCTION_NO_TX 0x01 +#define V_HSIO_PCR_FUNCTION_NO_RX 0x02 + +#define V_HSIO_PCR_FUNCTION_NO_CMNDIG 0x00 +#define V_HSIO_PCR_FUNCTION_NO_CMNANA 0x01 +#define V_HSIO_PCR_FUNCTION_NO_PLL 0x02 + +#define R_HSIO_PCR_PCS_DWORD4 0x10 + +#define R_HSIO_PCR_PCS_DWORD8 0x20 +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_PTR_INIT_4_0 0x1F000000 +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 0x001F0000 +#define N_HSIO_PCR_PCS_DWORD8_CRI_RXEB_LOWATER_4_0 16 +#define B_HSIO_PCR_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 0x00001F00 +#define N_HSIO_PCR_PCS_DWORD8_CRI_RXEB_HIWATER_4_0 8 + +#define R_HSIO_PCR_PCS_DWORD9 0x24 +#define B_HSIO_PCR_PCS_DWORD9_REG_ENABLE_PWR_GATING BIT29 + +#define R_HSIO_PCR_RX_DWORD8 0x220 +#define B_HSIO_PCR_RX_DWORD8_ICFGDFETAP3_EN BIT10 + +#define R_HSIO_PCR_RX_DWORD9 0x224 +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP4_OVERRIDE_EN BIT24 +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP3_OVERRIDE_EN BIT26 +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP2_OVERRIDE_EN BIT28 +#define B_HSIO_PCR_RX_DWORD9_CFGDFETAP1_OVERRIDE_EN BIT30 + +#define R_HSIO_PCR_RX_DWORD12 0x230 +#define B_HSIO_PCR_RX_DWORD12_O_CFGEWMARGINSEL BIT14 + +#define R_HSIO_PCR_RX_DWORD20 0x250 +#define B_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 (BIT29 | BIT28= | BIT27 | BIT26 | BIT25 | BIT24) +#define N_HSIO_PCR_RX_DWORD20_ICFGCTLEDATATAP_FULLRATE_5_0 24 + +#define R_HSIO_PCR_RX_DWORD21 0x254 +#define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 (BIT13 | BIT12= | BIT11 | BIT10 | BIT9 | BIT8) +#define N_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_QUATRATE_5_0 8 +#define B_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 (BIT5 | BIT4 |= BIT3 | BIT2 | BIT1 | BIT0) +#define N_HSIO_PCR_RX_DWORD21_ICFGCTLEDATATAP_HALFRATE_5_0 0 + +#define R_HSIO_PCR_RX_DWORD23 0x25C +#define B_HSIO_PCR_RX_DWORD23_ICFGVGABLWTAP_OVERRIDE_EN BIT2 +#define B_HSIO_PCR_RX_DWORD23_CFGVGATAP_ADAPT_OVERRIDE_EN BIT4 + +#define R_HSIO_PCR_RX_DWORD25 0x264 +#define B_HSIO_PCR_RX_DWORD25_RX_TAP_CFG_CTRL BIT3 +#define B_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 0x1F0000 +#define N_HSIO_PCR_RX_DWORD25_CTLE_ADAPT_OFFSET_CFG_4_0 16 + +#define R_HSIO_PCR_RX_DWORD26 0x268 +#define B_HSIO_PCR_RX_DWORD26_SATA_EQ_DIS BIT16 + +#define R_HSIO_PCR_RX_DWORD34 0x288 +#define B_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 (BIT14 | BIT13 | B= IT12) +#define N_HSIO_PCR_RX_DWORD34_MM_PH_OFC_SCALE_2_0 12 + +#define R_HSIO_PCR_RX_DWORD44 0x2B0 +#define B_HSIO_PCR_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 0xFF0000 +#define N_HSIO_PCR_RX_DWORD44_0_DFE_DATASUMCAL0_7_0 16 + +#define R_HSIO_PCR_RX_DWORD56 0x2E0 +#define B_HSIO_PCR_RX_DWORD56_ICFGPIDACCFGVALID BIT16 + +#define R_HSIO_PCR_RX_DWORD57 0x2E4 +#define B_HSIO_PCR_RX_DWORD57_JIM_COURSE BIT30 +#define B_HSIO_PCR_RX_DWORD57_JIM_ENABLE BIT29 +#define B_HSIO_PCR_RX_DWORD57_JIMMODE BIT28 +#define B_HSIO_PCR_RX_DWORD57_JIMNUMCYCLES_3_0 0x0F000000 +#define N_HSIO_PCR_RX_DWORD57_JIMNUMCYCLES_3_0 24 +#define B_HSIO_PCR_RX_DWORD57_ICFGMARGINEN BIT0 + +#define R_HSIO_PCR_RX_DWORD59 0x2EC +#define R_HSIO_PCR_RX_DWORD60 0x2F0 + +#define R_HSIO_PCR_TX_DWORD5 0x154 +#define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_HSIO_PCR_TX_DWORD5_OW2TAPGEN2DEEMPH3P5_5_0 16 +#define B_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_HSIO_PCR_TX_DWORD5_OW2TAPGEN1DEEMPH3P5_5_0 8 + +#define R_HSIO_PCR_TX_DWORD6 0x158 +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_HSIO_PCR_TX_DWORD6_OW2TAPGEN3DEEMPH6P0_5_0 16 +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_HSIO_PCR_TX_DWORD6_OW2TAPGEN2DEEMPH6P0_5_0 8 +#define B_HSIO_PCR_TX_DWORD6_OW2TAPGEN1DEEMPH6P0_5_0 (BIT5 | BIT4 | BIT= 3 | BIT2 | BIT1 | BIT0) + +#define R_HSIO_PCR_TX_DWORD8 0x160 +#define B_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 (BIT29 | BIT28 | B= IT27 | BIT26 | BIT25 | BIT24) +#define N_HSIO_PCR_TX_DWORD8_ORATE10MARGIN_5_0 24 +#define B_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 (BIT21 | BIT20 | B= IT19 | BIT18 | BIT17 | BIT16) +#define N_HSIO_PCR_TX_DWORD8_ORATE01MARGIN_5_0 16 +#define B_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 (BIT13 | BIT12 | B= IT11 | BIT10 | BIT9 | BIT8) +#define N_HSIO_PCR_TX_DWORD8_ORATE00MARGIN_5_0 8 + +#define R_HSIO_PCR_TX_DWORD19 0x18C + +#define R_HSIO_PCR_CLANE0_CMN_ANA_DWORD2 0x80C8 +#define B_HSIO_PCR_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_PLLEN_H_OVRDEN = BIT5 +#define B_HSIO_PCR_CLANE0_CMN_ANA_DWORD2_O_DTPLL1_lC_FULLCALRESET_L_OVERDE= N BIT3 + +#define R_HSIO_PCR_PLL_SSC_DWORD2 0x8188 +#define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 (BIT23 | BIT22 | B= IT21 | BIT20 | BIT19 | BIT18 | BIT17 | BIT16) +#define N_HSIO_PCR_PLL_SSC_DWORD2_SSCSTEPSIZE_7_0 16 +#define B_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN BIT10 +#define N_HSIO_PCR_PLL_SSC_DWORD2_SSCSEN 10 + +#define R_HSIO_PCR_PLL_SSC_DWORD3 0x818C +#define B_HSIO_PCR_PLL_SSC_DWORD3_SSC_PROPAGATE BIT0 + + +#endif //_PCH_REGS_HSIO_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sIsh.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsIsh= .h new file mode 100644 index 0000000000..5b4e23c43f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsIsh.h @@ -0,0 +1,79 @@ +/** @file + Register names for PCH Integrated Sensor Hub (ISH3.0) + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_ISH_H_ +#define _PCH_REGS_ISH_H_ + +// +// ISH Controller Registers +// +// D19:F0 +#define PCI_DEVICE_NUMBER_PCH_ISH 19 +#define PCI_FUNCTION_NUMBER_PCH_ISH 0 + +// PCI Configuration Space Registers +#define R_ISH_CFG_BAR0_LOW 0x10 +#define R_ISH_CFG_BAR0_HIGH 0x14 +#define V_ISH_CFG_BAR0_SIZE 0x100000 +#define N_ISH_CFG_BAR0_ALIGNMENT 20 +#define R_ISH_CFG_BAR1_LOW 0x18 +#define R_ISH_CFG_BAR1_HIGH 0x1C +#define V_ISH_CFG_BAR1_SIZE 0x1000 +#define N_ISH_CFG_BAR1_ALIGNMENT 12 + +// +// ISH Private Configuration Space Registers (IOSF2OCP) +// (PID:ISH) +// +#define R_ISH_PCR_PMCTL 0x1D0 //= /< Power Management +#define R_ISH_PCR_PCICFGCTRL 0x200 //= /< PCI Configuration Control +#define B_ISH_PCR_PCICFGCTR_PCI_IRQ 0x0FF00000 //= /< PCI IRQ number +#define N_ISH_PCR_PCICFGCTR_PCI_IRQ 20 +#define B_ISH_PCR_PCICFGCTR_ACPI_IRQ 0x000FF000 //= /< ACPI IRQ number +#define N_ISH_PCR_PCICFGCTR_ACPI_IRQ 12 +#define B_ISH_PCR_PCICFGCTR_IPIN1 (BIT11 | BIT10 | BIT9 | BIT8) //= /< Interrupt Pin +#define N_ISH_PCR_PCICFGCTR_IPIN1 8 +#define B_ISH_PCR_PCICFGCTRL_BAR1DIS BIT7 //= /< BAR1 Disable + +// +// Number of pins used by ISH controllers +// +#define PCH_ISH_PINS_PER_I2C_CONTROLLER 2 +#define PCH_ISH_PINS_PER_UART_CONTROLLER 4 +#define PCH_ISH_PINS_PER_SPI_CONTROLLER 4 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sItss.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsIt= ss.h new file mode 100644 index 0000000000..8d7c3f9015 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsItss.h @@ -0,0 +1,103 @@ +/** @file + Register names for ITSS + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_ITSS_H_ +#define _PCH_REGS_ITSS_H_ + +// +// ITSS PCRs (PID:ITSS) +// +#define R_ITSS_PCR_PIRQA_ROUT 0x3100 ///< PIRQA Routi= ng Control register +#define R_ITSS_PCR_PIRQB_ROUT 0x3101 ///< PIRQB Routi= ng Control register +#define R_ITSS_PCR_PIRQC_ROUT 0x3102 ///< PIRQC Routi= ng Control register +#define R_ITSS_PCR_PIRQD_ROUT 0x3103 ///< PIRQD Routi= ng Control register +#define R_ITSS_PCR_PIRQE_ROUT 0x3104 ///< PIRQE Routi= ng Control register +#define R_ITSS_PCR_PIRQF_ROUT 0x3105 ///< PIRQF Routi= ng Control register +#define R_ITSS_PCR_PIRQG_ROUT 0x3106 ///< PIRQG Routi= ng Control register +#define R_ITSS_PCR_PIRQH_ROUT 0x3107 ///< PIRQH Routi= ng Control register +#define B_ITSS_PCR_PIRQX_ROUT_REN 0x80 ///< Interrupt R= outing Enable +#define B_ITSS_PCR_PIRQX_ROUT_IR 0x0F ///< IRQ Routng +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_3 0x03 ///< Route PIRQx= to IRQ3 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_4 0x04 ///< Route PIRQx= to IRQ4 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_5 0x05 ///< Route PIRQx= to IRQ5 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_6 0x06 ///< Route PIRQx= to IRQ6 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_7 0x07 ///< Route PIRQx= to IRQ7 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_9 0x09 ///< Route PIRQx= to IRQ9 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_10 0x0A ///< Route PIRQx= to IRQ10 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_11 0x0B ///< Route PIRQx= to IRQ11 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_12 0x0C ///< Route PIRQx= to IRQ12 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_14 0x0E ///< Route PIRQx= to IRQ14 +#define V_ITSS_PCR_PIRQX_ROUT_IRQ_15 0x0F ///< Route PIRQx= to IRQ15 + +#define R_ITSS_PCR_PIR0 0x3140 ///< PCI Interru= pt Route 0 +#define R_ITSS_PCR_PIR1 0x3142 ///< PCI Interru= pt Route 1 +#define R_ITSS_PCR_PIR2 0x3144 ///< PCI Interru= pt Route 2 +#define R_ITSS_PCR_PIR3 0x3146 ///< PCI Interru= pt Route 3 +#define R_ITSS_PCR_PIR4 0x3148 ///< PCI Interru= pt Route 4 +#define R_ITSS_PCR_PIR5 0x314A ///< PCI Interru= pt Route 5 +#define R_ITSS_PCR_PIR6 0x314C ///< PCI Interru= pt Route 6 +#define R_ITSS_PCR_PIR7 0x314E ///< PCI Interru= pt Route 7 +#define R_ITSS_PCR_PIR8 0x3150 ///< PCI Interru= pt Route 8 +#define R_ITSS_PCR_PIR9 0x3152 ///< PCI Interru= pt Route 9 +#define R_ITSS_PCR_PIR10 0x3154 ///< PCI Interru= pt Route 10 +#define R_ITSS_PCR_PIR11 0x3156 ///< PCI Interru= pt Route 11 +#define R_ITSS_PCR_PIR12 0x3158 ///< PCI Interru= pt Route 12 + +#define R_ITSS_PCR_GIC 0x31FC ///< General Int= errupt Control +#define B_ITSS_PCR_GIC_MAX_IRQ_24 BIT9 ///< Max IRQ ent= ry size, 1 =3D 24 entry size, 0 =3D 120 entry size +#define B_ITSS_PCR_GIC_AME BIT17 ///< Alternate A= ccess Mode Enable +#define B_ITSS_PCR_GIC_SPS BIT16 ///< Shutdown Po= licy Select +#define R_ITSS_PCR_IPC0 0x3200 ///< Interrupt P= olarity Control 0 +#define R_ITSS_PCR_IPC1 0x3204 ///< Interrupt P= olarity Control 1 +#define R_ITSS_PCR_IPC2 0x3208 ///< Interrupt P= olarity Control 2 +#define R_ITSS_PCR_IPC3 0x320C ///< Interrupt P= olarity Control 3 +#define R_ITSS_PCR_ITSSPRC 0x3300 ///< ITSS Power = Reduction Control +#define B_ITSS_PCR_ITSSPRC_PGCBDCGE BIT4 ///< PGCB Dynami= c Clock Gating Enable +#define B_ITSS_PCR_ITSSPRC_HPETDCGE BIT3 ///< HPET Dynami= c Clock Gating Enable +#define B_ITSS_PCR_ITSSPRC_8254CGE BIT2 ///< 8254 Static= Clock Gating Enable +#define B_ITSS_PCR_ITSSPRC_IOSFICGE BIT1 ///< IOSF-Sideba= nd Interface Clock Gating Enable +#define B_ITSS_PCR_ITSSPRC_ITSSCGE BIT0 ///< ITSS Clock = Gate Enable +#define R_ITSS_PCR_NMI 0x3330 ///< NMI Control +#define N_ITSS_PCR_NMI_NMI2SMI_STS 3 ///< NMI2SMI Sta= tus +#define N_ITSS_PCR_NMI_NMI2SMI_EN 2 ///< NMI2SMI Ena= ble +#define B_ITSS_PCR_NMI_NMI2SMI_EN BIT2 ///< NMI2SMI Ena= ble +#define B_ITSS_PCR_NMI_NMI_NOW_STS BIT1 ///< NMI_NOW_STS +#define B_ITSS_PCR_NMI_NMI_NOW BIT0 ///< NMI_NOW +#define R_ITSS_PCR_MMC 0x3334 ///< Master Mess= age Control +#define B_ITSS_PCR_MMC_MSTRMSG_EN BIT0 ///< Master Mess= age Enable + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sLan.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan= .h new file mode 100644 index 0000000000..f649873f67 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLan.h @@ -0,0 +1,58 @@ +/** @file + Register names for PCH LAN device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_LAN_H_ +#define _PCH_REGS_LAN_H_ + +// +// Gigabit LAN Controller configuration registers (D31:F6) +// +#define PCI_DEVICE_NUMBER_PCH_LAN 31 +#define PCI_FUNCTION_NUMBER_PCH_LAN 6 + +#define R_LAN_CFG_MBARA 0x10 +#define N_LAN_CFG_MBARA_ALIGN 17 +#define R_LAN_CFG_PMCS 0xCC +#define B_LAN_CFG_PMCS_PS (BIT1 | BIT0) +#define V_LAN_CFG_PMCS_PS0 0x00 +#define R_LAN_MEM_CSR_RAL 0x5400 +#define R_LAN_MEM_CSR_RAH 0x5404 +#define B_LAN_MEM_CSR_RAH_RAH 0x0000FFFF +#define R_LAN_MEM_CSR_WUC 0x5800 +#define B_LAN_MEM_CSR_WUC_APME BIT0 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sLpc.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc= .h new file mode 100644 index 0000000000..34fc3c4dd2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h @@ -0,0 +1,360 @@ +/** @file + Register names for PCH LPC/eSPI device + +Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_LPC_H_ +#define _PCH_REGS_LPC_H_ + +#define B_LPC_CFG_DID 0xFFE0 + +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_PCH_LPC 31 +#define PCI_FUNCTION_NUMBER_PCH_LPC 0 + +#define V_LPC_CFG_VENDOR_ID V_PCH_INTEL_VENDOR_ID + + +#define R_LPC_CFG_SERIRQ_CNT 0x64 +#define B_LPC_CFG_SERIRQ_CNT_SIRQEN BIT7 +#define B_LPC_CFG_SERIRQ_CNT_SIRQMD BIT6 +#define B_LPC_CFG_SERIRQ_CNT_SIRQSZ (BIT5 | BIT4 | BIT3 | BI= T2) +#define N_LPC_CFG_SERIRQ_CNT_SIRQSZ 2 +#define B_LPC_CFG_SERIRQ_CNT_SFPW (BIT1 | BIT0) +#define N_LPC_CFG_SERIRQ_CNT_SFPW 0 +#define V_LPC_CFG_SERIRQ_CNT_SFPW_4CLK 0x00 +#define V_LPC_CFG_SERIRQ_CNT_SFPW_6CLK 0x01 +#define V_LPC_CFG_SERIRQ_CNT_SFPW_8CLK 0x02 + +#define R_LPC_CFG_IOD 0x80 +#define B_LPC_CFG_IOD_FDD BIT12 +#define N_LPC_CFG_IOD_FDD 12 +#define V_LPC_CFG_IOD_FDD_3F0 0 +#define V_LPC_CFG_IOD_FDD_370 1 +#define B_LPC_CFG_IOD_LPT (BIT9 | BIT8) +#define N_LPC_CFG_IOD_LPT 8 +#define V_LPC_CFG_IOD_LPT_378 0 +#define V_LPC_CFG_IOD_LPT_278 1 +#define V_LPC_CFG_IOD_LPT_3BC 2 +#define B_LPC_CFG_IOD_COMB (BIT6 | BIT5 |BIT4) +#define N_LPC_CFG_IOD_COMB 4 +#define V_LPC_CFG_IOD_COMB_3F8 0 +#define V_LPC_CFG_IOD_COMB_2F8 1 +#define V_LPC_CFG_IOD_COMB_220 2 +#define V_LPC_CFG_IOD_COMB_228 3 +#define V_LPC_CFG_IOD_COMB_238 4 +#define V_LPC_CFG_IOD_COMB_2E8 5 +#define V_LPC_CFG_IOD_COMB_338 6 +#define V_LPC_CFG_IOD_COMB_3E8 7 +#define B_LPC_CFG_IOD_COMA (BIT2 | BIT1 | BIT0) +#define N_LPC_CFG_IOD_COMA 0 +#define V_LPC_CFG_IOD_COMA_3F8 0 +#define V_LPC_CFG_IOD_COMA_2F8 1 +#define V_LPC_CFG_IOD_COMA_220 2 +#define V_LPC_CFG_IOD_COMA_228 3 +#define V_LPC_CFG_IOD_COMA_238 4 +#define V_LPC_CFG_IOD_COMA_2E8 5 +#define V_LPC_CFG_IOD_COMA_338 6 +#define V_LPC_CFG_IOD_COMA_3E8 7 +#define R_LPC_CFG_IOE 0x82 +#define B_LPC_CFG_IOE_ME2 BIT13 ///< Mic= rocontroller Enable #2, Enables decoding of I/O locations 4Eh and 4Fh to LPC +#define B_LPC_CFG_IOE_SE BIT12 ///< Sup= er I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC. +#define B_LPC_CFG_IOE_ME1 BIT11 ///< Mic= rocontroller Enable #1, Enables decoding of I/O locations 62h and 66h to LP= C. +#define B_LPC_CFG_IOE_KE BIT10 ///< Key= board Enable, Enables decoding of the keyboard I/O locations 60h and 64h to= LPC. +#define B_LPC_CFG_IOE_HGE BIT9 ///< Hig= h Gameport Enable, Enables decoding of the I/O locations 208h to 20Fh to LP= C. +#define B_LPC_CFG_IOE_LGE BIT8 ///< Low= Gameport Enable, Enables decoding of the I/O locations 200h to 207h to LPC. +#define B_LPC_CFG_IOE_FDE BIT3 ///< Flo= ppy Drive Enable, Enables decoding of the FDD range to LPC. Range is select= ed by LIOD.FDE +#define B_LPC_CFG_IOE_PPE BIT2 ///< Par= allel Port Enable, Enables decoding of the LPT range to LPC. Range is selec= ted by LIOD.LPT. +#define B_LPC_CFG_IOE_CBE BIT1 ///< Com= Port B Enable, Enables decoding of the COMB range to LPC. Range is selecte= d LIOD.CB. +#define B_LPC_CFG_IOE_CAE BIT0 ///< Com= Port A Enable, Enables decoding of the COMA range to LPC. Range is selecte= d LIOD.CA. +#define R_LPC_CFG_GEN1_DEC 0x84 +#define R_LPC_CFG_GEN2_DEC 0x88 +#define R_LPC_CFG_GEN3_DEC 0x8C +#define R_LPC_CFG_GEN4_DEC 0x90 +#define B_LPC_CFG_GENX_DEC_IODRA 0x00FC0000 +#define B_LPC_CFG_GENX_DEC_IOBAR 0x0000FFFC +#define B_LPC_CFG_GENX_DEC_EN 0x00000001 +#define R_LPC_CFG_ULKMC 0x94 +#define B_LPC_CFG_ULKMC_SMIBYENDPS BIT15 +#define B_LPC_CFG_ULKMC_TRAPBY64W BIT11 +#define B_LPC_CFG_ULKMC_TRAPBY64R BIT10 +#define B_LPC_CFG_ULKMC_TRAPBY60W BIT9 +#define B_LPC_CFG_ULKMC_TRAPBY60R BIT8 +#define B_LPC_CFG_ULKMC_SMIATENDPS BIT7 +#define B_LPC_CFG_ULKMC_PSTATE BIT6 +#define B_LPC_CFG_ULKMC_A20PASSEN BIT5 +#define B_LPC_CFG_ULKMC_USBSMIEN BIT4 +#define B_LPC_CFG_ULKMC_64WEN BIT3 +#define B_LPC_CFG_ULKMC_64REN BIT2 +#define B_LPC_CFG_ULKMC_60WEN BIT1 +#define B_LPC_CFG_ULKMC_60REN BIT0 +#define R_LPC_CFG_LGMR 0x98 +#define B_LPC_CFG_LGMR_MA 0xFFFF0000 +#define B_LPC_CFG_LGMR_LMRD_EN BIT0 +#define R_ESPI_CFG_CS1IORE 0xA0 +#define R_ESPI_CFG_CS1IORE_DPCS1RE BIT14 +#define R_ESPI_CFG_CS1GIR1 0xA4 +#define R_ESPI_CFG_CS1GMR1 0xA8 + +#define R_LPC_CFG_FWH_BIOS_SEL 0xD0 +#define B_LPC_CFG_FWH_BIOS_SEL_F8 0xF0000000 +#define B_LPC_CFG_FWH_BIOS_SEL_F0 0x0F000000 +#define B_LPC_CFG_FWH_BIOS_SEL_E8 0x00F00000 +#define B_LPC_CFG_FWH_BIOS_SEL_E0 0x000F0000 +#define B_LPC_CFG_FWH_BIOS_SEL_D8 0x0000F000 +#define B_LPC_CFG_FWH_BIOS_SEL_D0 0x00000F00 +#define B_LPC_CFG_FWH_BIOS_SEL_C8 0x000000F0 +#define B_LPC_CFG_FWH_BIOS_SEL_C0 0x0000000F +#define R_LPC_CFG_FWH_BIOS_SEL2 0xD4 +#define B_LPC_CFG_FWH_BIOS_SEL2_70 0xF000 +#define B_LPC_CFG_FWH_BIOS_SEL2_60 0x0F00 +#define B_LPC_CFG_FWH_BIOS_SEL2_50 0x00F0 +#define B_LPC_CFG_FWH_BIOS_SEL2_40 0x000F +#define R_LPC_CFG_BDE 0xD8 = ///< BIOS decode enable +#define B_LPC_CFG_BDE_F8 BIT15 +#define B_LPC_CFG_BDE_F0 BIT14 +#define B_LPC_CFG_BDE_E8 BIT13 +#define B_LPC_CFG_BDE_E0 BIT12 +#define B_LPC_CFG_BDE_D8 BIT11 +#define B_LPC_CFG_BDE_D0 BIT10 +#define B_LPC_CFG_BDE_C8 BIT9 +#define B_LPC_CFG_BDE_C0 BIT8 +#define B_LPC_CFG_BDE_LEG_F BIT7 +#define B_LPC_CFG_BDE_LEG_E BIT6 +#define B_LPC_CFG_BDE_70 BIT3 +#define B_LPC_CFG_BDE_60 BIT2 +#define B_LPC_CFG_BDE_50 BIT1 +#define B_LPC_CFG_BDE_40 BIT0 +#define R_LPC_CFG_PCC 0xE0 +#define B_LPC_CFG_PCC_CLKRUN_EN BIT0 + +#define B_LPC_CFG_FVEC0_USB_PORT_CAP (BIT11 | BIT10) +#define V_LPC_CFG_FVEC0_USB_14_PORT 0x00000000 +#define V_LPC_CFG_FVEC0_USB_12_PORT 0x00000400 +#define V_LPC_CFG_FVEC0_USB_10_PORT 0x00000800 +#define B_LPC_CFG_FVEC0_SATA_RAID_CAP BIT7 +#define B_LPC_CFG_FVEC0_SATA_PORT23_CAP BIT6 +#define B_LPC_CFG_FVEC0_SATA_PORT1_6GB_CAP BIT3 +#define B_LPC_CFG_FVEC0_SATA_PORT0_6GB_CAP BIT2 +#define B_LPC_CFG_FVEC0_PCI_CAP BIT1 +#define R_LPC_CFG_FVEC1 0x01 +#define B_LPC_CFG_FVEC1_USB_R_CAP BIT22 +#define R_LPC_CFG_FVEC2 0x02 +#define V_LPC_CFG_FVEC2_PCIE_PORT78_CAP 0x00200000 +#define V_LPC_CFG_FVEC2_PCH_IG_SUPPORT_CAP 0x00020000 ///< PCH Inte= grated Graphics Support Capability +#define R_LPC_CFG_FVEC3 0x03 +#define B_LPC_CFG_FVEC3_DCMI_CAP BIT13 ///< Data Cen= ter Manageability Interface (DCMI) Capability +#define B_LPC_CFG_FVEC3_NM_CAP BIT12 ///< Node Man= ager Capability + +#define R_LPC_CFG_MDAP 0xC0 +#define B_LPC_CFG_MDAP_POLICY_EN BIT31 +#define B_LPC_CFG_MDAP_PDMA_EN BIT30 +#define B_LPC_CFG_MDAP_VALUE 0x0001FFFF + +// +// APM Registers +// +#define R_PCH_IO_APM_CNT 0xB2 +#define R_PCH_IO_APM_STS 0xB3 + +#define R_LPC_CFG_BC 0xDC ///< Bio= s Control +#define S_LPC_CFG_BC 1 +#define B_LPC_CFG_BC_BILD BIT7 ///< BIO= S Interface Lock-Down +#define B_LPC_CFG_BC_BBS BIT6 ///< Boo= t BIOS strap +#define N_LPC_CFG_BC_BBS 6 +#define V_LPC_CFG_BC_BBS_SPI 0 ///< Boo= t BIOS strapped to SPI +#define V_LPC_CFG_BC_BBS_LPC 1 ///< Boo= t BIOS strapped to LPC +#define B_LPC_CFG_BC_EISS BIT5 ///< Ena= ble InSMM.STS +#define B_LPC_CFG_BC_TS BIT4 ///< Top= Swap +#define B_LPC_CFG_BC_LE BIT1 ///< Loc= k Enable +#define N_LPC_CFG_BC_LE 1 +#define B_LPC_CFG_BC_WPD BIT0 ///< Wri= te Protect Disable + +#define R_ESPI_CFG_PCBC 0xDC ///< Per= ipheral Channel BIOS Control +#define S_ESPI_CFG_PCBC 4 ///< Per= ipheral Channel BIOS Control register size +#define B_ESPI_CFG_PCBC_BWRE BIT11 ///< BIO= S Write Report Enable +#define N_ESPI_CFG_PCBC_BWRE 11 ///< BIO= S Write Report Enable bit position +#define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIO= S Write Report Status +#define N_ESPI_CFG_PCBC_BWRS 10 ///< BIO= S Write Report Status bit position +#define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< BIO= S Write Protect Disable Status +#define N_ESPI_CFG_PCBC_BWPDS 8 ///< BIO= S Write Protect Disable Status bit position +#define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSP= I Enable Pin Strap +#define B_ESPI_CFG_PCBC_LE BIT1 ///< Loc= k Enable +#define N_ESPI_CFG_PCBC_LE 1 + +// +// eSPI slave registers +// +#define R_ESPI_SLAVE_CHA_0_CAP_AND_CONF 0x10 ///< Cha= nnel 0 Capabilities and Configurations +#define B_ESPI_SLAVE_BME BIT2 ///< Bus= Master Enable + +// +// Processor interface registers +// +#define R_PCH_IO_NMI_SC 0x61 +#define B_PCH_IO_NMI_SC_SERR_NMI_STS BIT7 +#define B_PCH_IO_NMI_SC_IOCHK_NMI_STS BIT6 +#define B_PCH_IO_NMI_SC_TMR2_OUT_STS BIT5 +#define B_PCH_IO_NMI_SC_REF_TOGGLE BIT4 +#define B_PCH_IO_NMI_SC_IOCHK_NMI_EN BIT3 +#define B_PCH_IO_NMI_SC_PCI_SERR_EN BIT2 +#define B_PCH_IO_NMI_SC_SPKR_DAT_EN BIT1 +#define B_PCH_IO_NMI_SC_TIM_CNT2_EN BIT0 +#define R_PCH_IO_NMI_EN 0x70 +#define B_PCH_IO_NMI_EN_NMI_EN BIT7 + +// +// Reset Generator I/O Port +// +#define R_PCH_IO_RST_CNT 0xCF9 +#define B_PCH_IO_RST_CNT_FULL_RST BIT3 +#define B_PCH_IO_RST_CNT_RST_CPU BIT2 +#define B_PCH_IO_RST_CNT_SYS_RST BIT1 +#define V_PCH_IO_RST_CNT_FULLRESET 0x0E +#define V_PCH_IO_RST_CNT_HARDRESET 0x06 +#define V_PCH_IO_RST_CNT_SOFTRESET 0x04 +#define V_PCH_IO_RST_CNT_HARDSTARTSTATE 0x02 +#define V_PCH_IO_RST_CNT_SOFTSTARTSTATE 0x00 + +// +// RTC register +// +#define R_RTC_IO_INDEX 0x70 +#define R_RTC_IO_TARGET 0x71 +#define R_RTC_IO_EXT_INDEX 0x72 +#define R_RTC_IO_EXT_TARGET 0x73 +#define R_RTC_IO_INDEX_ALT 0x74 +#define R_RTC_IO_TARGET_ALT 0x75 +#define R_RTC_IO_EXT_INDEX_ALT 0x76 +#define R_RTC_IO_EXT_TARGET_ALT 0x77 +#define R_RTC_IO_REGA 0x0A +#define B_RTC_IO_REGA_UIP BIT7 +#define R_RTC_IO_REGB 0x0B +#define B_RTC_IO_REGB_SET 0x80 +#define B_RTC_IO_REGB_PIE 0x40 +#define B_RTC_IO_REGB_AIE 0x20 +#define B_RTC_IO_REGB_UIE 0x10 +#define B_RTC_IO_REGB_DM 0x04 +#define B_RTC_IO_REGB_HOURFORM 0x02 +#define R_RTC_IO_REGC 0x0C +#define R_RTC_IO_REGD 0x0D + +// +// Private Configuration Register +// RTC PCRs (PID:RTC) +// +#define R_RTC_PCR_CONF 0x3400 ///< RT= C Configuration register +#define B_RTC_PCR_CONF_BILD BIT31 ///< BI= OS Interface Lock-Down +#define B_RTC_PCR_CONF_HPM_HW_DIS BIT6 ///< RT= C High Power Mode HW Disable +#define B_RTC_PCR_CONF_UCMOS_LOCK BIT4 ///< Up= per 128 Byte Lock +#define B_RTC_PCR_CONF_LCMOS_LOCK BIT3 ///< Lo= wer 128 Byte Lock +#define B_RTC_PCR_CONF_UCMOS_EN BIT2 ///< Up= per CMOS bank enable +#define R_RTC_PCR_BUC 0x3414 ///< Ba= cked Up Control +#define B_RTC_PCR_BUC_DSO BIT4 ///< Da= ylight Savings Override +#define B_RTC_PCR_BUC_TS BIT0 ///< To= p Swap +#define R_RTC_PCR_RTCDCG 0x3418 ///< RT= C Dynamic Clock Gating Control +#define R_RTC_PCR_RTCDCG_RTCPGCBDCGEN BIT2 ///< pg= cb_clk (12Mhz) Dynamic Clock Gate Enable +#define R_RTC_PCR_RTCDCG_RTCPCICLKDCGEN BIT1 ///< ip= ciclk_clk (24 MHz) Dynamic Clock Gate Enable +#define R_RTC_PCR_RTCDCG_RTCROSIDEDCGEN BIT0 ///< ro= sc_side_clk (120 MHz) Dynamic Clock Gate Enable +#define R_RTC_PCR_PG1_CP_LO 0x3428 +#define R_RTC_PCR_PG1_AC_LO 0x3438 +#define R_RTC_PCR_3F00 0x3F00 +#define R_RTC_PCR_UIPSMI 0x3F04 ///< RT= C Update In Progress SMI Control + +// +// LPC PCR Registers +// +#define R_LPC_PCR_HVMTCTL 0x3410 +#define R_LPC_PCR_GCFD 0x3418 +#define B_LPC_PCR_GCFD_SRVR_CLKRUN_EN BIT2 ///< En= ables the CLKRUN# logic to stop the PCI clocks +#define R_LPC_PCR_PRC 0x341C +#define R_LPC_PCR_PCT 0x3420 +#define R_LPC_PCR_SCT 0x3424 +#define R_LPC_PCR_LPCCT 0x3428 +#define R_LPC_PCR_ULTOR 0x3500 + +// +// eSPI PCR Registers +// +#define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 ///<= Slave Configuration Register and Link Control +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 ///<= Slave Configuration Register Access Enable +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///<= Slave Configuration Register Access Status +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 ///<= Slave Configuration Register Access Status bit position +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 ///<= IOSF-SB eSPI Link Configuration Lock +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///<= No errors (transaction completed successfully) +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///<= Slave ID +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 ///<= Slave ID bit position +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///<= Slave Configuration Register Access Type +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 ///<= Slave Configuration Register Access Type bit position +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RD 0 ///<= Slave Configuration register read from address SCRA[11:0] +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_WR 1 ///<= Slave Configuration register write to address SCRA[11:0] +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_STS 2 ///<= Slave Status register read +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRT_RS 3 ///<= In-Band reset +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///<= Slave Configuration Register Address +#define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 ///<= Slave Configuration Register Data + +#define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Periphe= ral Channel Error for Slave 0 +#define B_ESPI_PCR_PCERR_PCURD BIT24 ///< Periphe= ral Channel Unsupported Request Detected +#define R_ESPI_PCR_PCERR_SLV1 0x4024 ///< Periphe= ral Channel Error for Slave 1 +#define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtual= Wire Channel Error for Slave 0 +#define R_ESPI_PCR_VWERR_SLV1 0x4034 ///< Virtual= Wire Channel Error for Slave 1 +#define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash A= ccess Channel Error for Slave 0 +#define B_ESPI_PCR_FCERR_SAFBLK BIT17 ///< SAF Blo= cked (SAFBLK) +#define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fat= al Error Reporting Enable bits +#define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-Fat= al Error Reporting Enable bit position +#define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enable = Non-Fatal Error Reporting as SMI +#define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal E= rror Status +#define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal E= rror Reporting Enable bits +#define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal E= rror Reporting Enable bit position +#define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enable = Fatal Error Reporting as SMI +#define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal E= rror Status +#define S_ESPI_PCR_XERR 4 ///< Channel= register sizes +#define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///< Periphe= ral Channel Unsupported Request Detected +#define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link Er= ror for Slave 0 +#define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link Er= ror for Slave 0 register size +#define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Li= nk and Slave Channel Recovery Required +#define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal E= rror Type 1 Reporting Enable +#define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal E= rror Type 1 Reporting Enable bit position +#define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable = Fatal Error Type 1 Reporting as SMI +#define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link Fa= tal Error Type 1 Status +#define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link Er= ror for Slave 1 +#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI En= abled Strap +#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI En= abled Strap bit position +#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI So= fstraps Register 0 +#define R_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# En= able + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sLpcCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs= LpcCnl.h new file mode 100644 index 0000000000..74789a87ce --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsLpcCnl= .h @@ -0,0 +1,61 @@ +/** @file + Register names for PCH LPC/eSPI device + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denote= d by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in regist= er/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regi= ster/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be= just named + as "_PCH_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_LPC_CNL_H_ +#define _PCH_REGS_LPC_CNL_H_ + +#define V_LPC_CFG_DID_CNL_H 0xA300 +#define V_LPC_CFG_DID_CNL_LP 0x9D80 + +// +// PCH-LP Device IDs +// +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_SUPER_SKU 0x9D80 ///<= PCH LP Mobile +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_0 0x9D81 ///<= PCH LP Mobile (U) +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_1 0x9D82 ///<= PCH LP Mobile Locked +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_2 0x9D83 ///<= PCH LP Mobile (Y) +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_3 0x9D84 ///<= PCH LP Mobile (U) +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_4 0x9D85 ///<= PCH LP Mobile (U) +#define V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_5 0x9D86 ///<= PCH LP Mobile (Y) + +// +// PCH-H Desktop LPC Device IDs +// +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A300_SKU 0xA300 ///<= LPC/eSPI Controller +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A303_SKU 0xA303 ///<= PCH H Mobile H310 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A304_SKU 0xA304 ///<= PCH H Mobile H370 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A305_SKU 0xA305 ///<= PCH H Mobile Z390 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A306_SKU 0xA306 ///<= PCH H Mobile Q370 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A309_SKU 0xA309 ///<= PCH H Mobile C246 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30A_SKU 0xA30A ///<= PCH H Mobile C242 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30B_SKU 0xA30B ///<= PCH H Mobile X399 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30C_SKU 0xA30C ///<= PCH H Mobile QM370 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30D_SKU 0xA30D ///<= PCH H Mobile HM370 +#define V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30E_SKU 0xA30E ///<= PCH H Mobile CM246 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sP2sb.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsP2= sb.h new file mode 100644 index 0000000000..db6a8c4e95 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsP2sb.h @@ -0,0 +1,116 @@ +/** @file + Register names for PCH P2SB device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_P2SB_H_ +#define _PCH_REGS_P2SB_H_ + +// +// PCI to P2SB Bridge Registers (D31:F1) +// +#define PCI_DEVICE_NUMBER_PCH_P2SB 31 +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1 + +#define V_P2SB_CFG_VENDOR_ID V_PCH_INTEL_VENDOR_ID +#define R_P2SB_CFG_SBREG_BAR 0x10 +#define B_P2SB_CFG_SBREG_RBA 0xFF000000 +#define R_P2SB_CFG_SBREG_BARH 0x14 +#define B_P2SB_CFG_SBREG_RBAH 0xFFFFFFFF +#define R_P2SB_CFG_VBDF 0x50 +#define B_P2SB_CFG_VBDF_BUS 0xFF00 +#define B_P2SB_CFG_VBDF_DEV 0x00F8 +#define B_P2SB_CFG_VBDF_FUNC 0x0007 +#define R_P2SB_CFG_ESMBDF 0x52 +#define B_P2SB_CFG_ESMBDF_BUS 0xFF00 +#define B_P2SB_CFG_ESMBDF_DEV 0x00F8 +#define B_P2SB_CFG_ESMBDF_FUNC 0x0007 +#define R_P2SB_CFG_RCFG 0x54 +#define B_P2SB_CFG_RCFG_RPRID 0x0000FF00 +#define B_P2SB_CFG_RCFG_RSE BIT0 +#define R_P2SB_CFG_HPTC 0x60 +#define B_P2SB_CFG_HPTC_AE BIT7 +#define B_P2SB_CFG_HPTC_AS 0x0003 +#define N_HPET_ADDR_ASEL 12 +#define R_P2SB_CFG_IOAC 0x64 +#define B_P2SB_CFG_IOAC_AE BIT8 +#define B_P2SB_CFG_IOAC_ASEL 0x00FF +#define N_IO_APIC_ASEL 12 +#define R_IO_APIC_INDEX_OFFSET 0x00 +#define R_IO_APIC_DATA_OFFSET 0x10 +#define R_IO_APIC_EOI_OFFSET 0x40 +#define R_P2SB_CFG_IBDF 0x6C +#define B_P2SB_CFG_IBDF_BUS 0xFF00 +#define B_P2SB_CFG_IBDF_DEV 0x00F8 +#define B_P2SB_CFG_IBDF_FUNC 0x0007 +#define V_P2SB_CFG_IBDF_BUS 0 +#define V_P2SB_CFG_IBDF_DEV 30 +#define V_P2SB_CFG_IBDF_FUNC 7 +#define V_P2SB_CFG_HBDF_BUS 0 +#define V_P2SB_CFG_HBDF_DEV 30 +#define V_P2SB_CFG_HBDF_FUNC 6 + +// +// Definition for SBI +// +#define R_P2SB_CFG_SBIADDR 0xD0 +#define B_P2SB_CFG_SBIADDR_DESTID 0xFF000000 +#define B_P2SB_CFG_SBIADDR_RS 0x000F0000 +#define B_P2SB_CFG_SBIADDR_OFFSET 0x0000FFFF +#define R_P2SB_CFG_SBIDATA 0xD4 +#define B_P2SB_CFG_SBIDATA_DATA 0xFFFFFFFF +#define R_P2SB_CFG_SBISTAT 0xD8 +#define B_P2SB_CFG_SBISTAT_OPCODE 0xFF00 +#define B_P2SB_CFG_SBISTAT_POSTED BIT7 +#define B_P2SB_CFG_SBISTAT_RESPONSE 0x0006 +#define N_P2SB_CFG_SBISTAT_RESPONSE 1 +#define B_P2SB_CFG_SBISTAT_INITRDY BIT0 +#define R_P2SB_CFG_SBIRID 0xDA +#define B_P2SB_CFG_SBIRID_FBE 0xF000 +#define B_P2SB_CFG_SBIRID_BAR 0x0700 +#define B_P2SB_CFG_SBIRID_FID 0x00FF +#define R_P2SB_CFG_SBIEXTADDR 0xDC +#define B_P2SB_CFG_SBIEXTADDR_ADDR 0xFFFFFFFF + +// +// Others +// +#define R_P2SB_CFG_E0 0xE0 +#define R_P2SB_CFG_E4 0xE4 +#define R_P2SB_CFG_E8 0xE8 +#define R_P2SB_CFG_EA 0xEA +#define R_P2SB_CFG_F4 0xF4 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sPcie.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPc= ie.h new file mode 100644 index 0000000000..af19b93e2d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcie.h @@ -0,0 +1,484 @@ +/** @file + Register names for PCH PCI-E root port devices + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PCIE_H_ +#define _PCH_REGS_PCIE_H_ + +// +// Number of PCIe ports per PCIe controller +// +#define PCH_PCIE_CONTROLLER_PORTS 4u + +// +// PCH PCI Express Root Ports (D28:F0..7, D29:F0..7, D27:F0..7) +// +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1 28 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2 29 +#define PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3 27 +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORTS 28 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16 7 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17 0 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18 1 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19 2 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20 3 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21 4 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22 5 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23 6 +#define PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24 7 + +#define V_PCH_PCIE_CFG_VENDOR_ID V_PCH_INTEL_VENDOR_ID + + +#define R_PCH_PCIE_CFG_CLIST 0x40 +#define R_PCH_PCIE_CFG_XCAP (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_XCAP_OFFSET) +#define R_PCH_PCIE_CFG_DCAP (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_DCAP_OFFSET) +#define R_PCH_PCIE_CFG_DCTL (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_DCTL_OFFSET) +#define R_PCH_PCIE_CFG_DSTS (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_DSTS_OFFSET) +#define R_PCH_PCIE_CFG_LCAP (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_LCAP_OFFSET) +#define B_PCH_PCIE_CFG_LCAP_PN 0xFF000000 +#define N_PCH_PCIE_CFG_LCAP_PN 24 +#define R_PCH_PCIE_CFG_LCTL (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_LCTL_OFFSET) +#define R_PCH_PCIE_CFG_LSTS (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_LSTS_OFFSET) +#define R_PCH_PCIE_CFG_SLCAP (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_SLCAP_OFFSET) +#define R_PCH_PCIE_CFG_SLCTL (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_SLCTL_OFFSET) +#define R_PCH_PCIE_CFG_SLSTS (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_SLSTS_OFFSET) +#define R_PCH_PCIE_CFG_RCTL (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_RCTL_OFFSET) +#define R_PCH_PCIE_CFG_RSTS (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_RSTS_OFFSET) +#define R_PCH_PCIE_CFG_DCAP2 (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_DCAP2_OFFSET) +#define R_PCH_PCIE_CFG_DCTL2 (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_DCTL2_OFFSET) +#define R_PCH_PCIE_CFG_LCTL2 (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_LCTL2_OFFSET) +#define R_PCH_PCIE_CFG_LSTS2 (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_LSTS2_OFFSET) + +#define R_PCH_PCIE_CFG_MID 0x80 +#define S_PCH_PCIE_CFG_MID 2 +#define R_PCH_PCIE_CFG_MC 0x82 +#define S_PCH_PCIE_CFG_MC 2 +#define R_PCH_PCIE_CFG_MA 0x84 +#define S_PCH_PCIE_CFG_MA 4 +#define R_PCH_PCIE_CFG_MD 0x88 +#define S_PCH_PCIE_CFG_MD 2 + +#define R_PCH_PCIE_CFG_SVCAP 0x90 +#define S_PCH_PCIE_CFG_SVCAP 2 +#define R_PCH_PCIE_CFG_SVID 0x94 +#define S_PCH_PCIE_CFG_SVID 4 + +#define R_PCH_PCIE_CFG_PMCAP 0xA0 +#define R_PCH_PCIE_CFG_PMCS (R_PCH_PCIE_CFG_PMCA= P + R_PCIE_PMCS_OFFST) + +#define R_PCH_PCIE_CFG_CCFG 0xD0 +#define B_PCH_PCIE_CFG_CCFG_UNRS (BIT6 | BIT5 | BIT4) +#define N_PCH_PCIE_CFG_CCFG_UNRS 4 + +#define R_PCH_PCIE_CFG_MPC2 0xD4 +#define S_PCH_PCIE_CFG_MPC2 4 +#define B_PCH_PCIE_CFG_MPC2_PTNFAE BIT12 +#define B_PCH_PCIE_CFG_MPC2_LSTP BIT6 +#define B_PCH_PCIE_CFG_MPC2_IEIME BIT5 +#define B_PCH_PCIE_CFG_MPC2_ASPMCOEN BIT4 +#define B_PCH_PCIE_CFG_MPC2_ASPMCO (BIT3 | BIT2) +#define V_PCH_PCIE_CFG_MPC2_ASPMCO_DISABLED 0 +#define V_PCH_PCIE_CFG_MPC2_ASPMCO_L0S (1 << 2) +#define V_PCH_PCIE_CFG_MPC2_ASPMCO_L1 (2 << 2) +#define V_PCH_PCIE_CFG_MPC2_ASPMCO_L0S_L1 (3 << 2) +#define B_PCH_PCIE_CFG_MPC2_EOIFD BIT1 + +#define R_PCH_PCIE_CFG_MPC 0xD8 +#define S_PCH_PCIE_CFG_MPC 4 +#define B_PCH_PCIE_CFG_MPC_PMCE BIT31 +#define B_PCH_PCIE_CFG_MPC_HPCE BIT30 +#define B_PCH_PCIE_CFG_MPC_MMBNCE BIT27 +#define B_PCH_PCIE_CFG_MPC_P8XDE BIT26 +#define B_PCH_PCIE_CFG_MPC_IRRCE BIT25 +#define B_PCH_PCIE_CFG_MPC_SRL BIT23 +#define B_PCH_PCIE_CFG_MPC_UCEL (BIT20 | BIT19 | BIT= 18) +#define N_PCH_PCIE_CFG_MPC_UCEL 18 +#define B_PCH_PCIE_CFG_MPC_CCEL (BIT17 | BIT16 | BIT= 15) +#define N_PCH_PCIE_CFG_MPC_CCEL 15 +#define B_PCH_PCIE_CFG_MPC_PCIESD (BIT14 | BIT13) +#define N_PCH_PCIE_CFG_MPC_PCIESD 13 +#define V_PCH_PCIE_CFG_MPC_PCIESD_GEN1 1 +#define V_PCH_PCIE_CFG_MPC_PCIESD_GEN2 2 +#define B_PCH_PCIE_CFG_MPC_MCTPSE BIT3 +#define B_PCH_PCIE_CFG_MPC_HPME BIT1 +#define N_PCH_PCIE_CFG_MPC_HPME 1 +#define B_PCH_PCIE_CFG_MPC_PMME BIT0 + +#define R_PCH_PCIE_CFG_SMSCS 0xDC +#define S_PCH_PCIE_CFG_SMSCS 4 +#define B_PCH_PCIE_CFG_SMSCS_PMCS BIT31 +#define N_PCH_PCIE_CFG_SMSCS_LERSMIS 5 +#define N_PCH_PCIE_CFG_SMSCS_HPLAS 4 +#define N_PCH_PCIE_CFG_SMSCS_HPPDM 1 + +#define R_PCH_PCIE_CFG_RPDCGEN 0xE1 +#define S_PCH_PCIE_CFG_RPDCGEN 1 +#define B_PCH_PCIE_CFG_RPDCGEN_RPSCGEN BIT7 +#define B_PCH_PCIE_CFG_RPDCGEN_PTOCGE BIT6 +#define B_PCH_PCIE_CFG_RPDCGEN_LCLKREQEN BIT5 +#define B_PCH_PCIE_CFG_RPDCGEN_BBCLKREQEN BIT4 +#define B_PCH_PCIE_CFG_RPDCGEN_SRDBCGEN BIT2 +#define B_PCH_PCIE_CFG_RPDCGEN_RPDLCGEN BIT1 +#define B_PCH_PCIE_CFG_RPDCGEN_RPDBCGEN BIT0 + + +#define R_PCH_PCIE_CFG_PWRCTL 0xE8 +#define B_PCH_PCIE_CFG_PWRCTL_LTSSMRTC BIT20 +#define B_PCH_PCIE_CFG_PWRCTL_WPDMPGEP BIT17 +#define B_PCH_PCIE_CFG_PWRCTL_DBUPI BIT15 +#define B_PCH_PCIE_CFG_PWRCTL_TXSWING BIT13 +#define B_PCH_PCIE_CFG_PWRCTL_RPL1SQPOL BIT1 +#define B_PCH_PCIE_CFG_PWRCTL_RPDTSQPOL BIT0 + +#define R_PCH_PCIE_CFG_DC 0xEC +#define B_PCH_PCIE_CFG_DC_PCIBEM BIT2 + +#define R_PCH_PCIE_CFG_PHYCTL2 0xF5 +#define B_PCH_PCIE_CFG_PHYCTL2_TDFT (BIT7 | BIT6) +#define B_PCH_PCIE_CFG_PHYCTL2_TXCFGCHGWAIT (BIT5 | BIT4) +#define N_PCH_PCIE_CFG_PHYCTL2_TXCFGCHGWAIT 4 +#define B_PCH_PCIE_CFG_PHYCTL2_PXPG3PLLOFFEN BIT1 +#define B_PCH_PCIE_CFG_PHYCTL2_PXPG2PLLOFFEN BIT0 + +#define R_PCH_PCIE_CFG_IOSFSBCS 0xF7 +#define B_PCH_PCIE_CFG_IOSFSBCS_SCPTCGE BIT6 +#define B_PCH_PCIE_CFG_IOSFSBCS_SIID (BIT3 | BIT2) + +#define R_PCH_PCIE_CFG_STRPFUSECFG 0xFC +#define B_PCH_PCIE_CFG_STRPFUSECFG_PXIP (BIT27 | BIT26 | BIT= 25 | BIT24) +#define N_PCH_PCIE_CFG_STRPFUSECFG_PXIP 24 +#define B_PCH_PCIE_CFG_STRPFUSECFG_RPC (BIT15 | BIT14) +#define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_1_1_1_1 0 +#define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_2_1_1 1 +#define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_2_2 2 +#define V_PCH_PCIE_CFG_STRPFUSECFG_RPC_4 3 +#define N_PCH_PCIE_CFG_STRPFUSECFG_RPC 14 +#define B_PCH_PCIE_CFG_STRPFUSECFG_MODPHYIOPMDIS BIT9 +#define B_PCH_PCIE_CFG_STRPFUSECFG_PLLSHTDWNDIS BIT8 +#define B_PCH_PCIE_CFG_STRPFUSECFG_STPGATEDIS BIT7 +#define B_PCH_PCIE_CFG_STRPFUSECFG_ASPMDIS BIT6 +#define B_PCH_PCIE_CFG_STRPFUSECFG_LDCGDIS BIT5 +#define B_PCH_PCIE_CFG_STRPFUSECFG_LTCGDIS BIT4 +#define B_PCH_PCIE_CFG_STRPFUSECFG_CDCGDIS BIT3 +#define B_PCH_PCIE_CFG_STRPFUSECFG_DESKTOPMOB BIT2 + +// +//PCI Express Extended Capability Registers +// + +#define R_PCH_PCIE_CFG_EXCAP_OFFSET 0x100 + +#define R_PCH_PCIE_CFG_EX_AECH 0x100 ///< Advanced = Error Reporting Capability Header +#define V_PCH_PCIE_CFG_EX_AEC_CV 0x1 +#define R_PCH_PCIE_CFG_EX_UEM (R_PCH_PCIE_CFG_EX_A= ECH + R_PCIE_EX_UEM_OFFSET) // Uncorrectable Error Mask + +#define R_PCH_PCIE_CFG_EX_CES 0x110 ///< Correctab= le Error Status +#define B_PCH_PCIE_CFG_EX_CES_BD BIT7 ///< Bad DLLP = Status +#define B_PCH_PCIE_CFG_EX_CES_BT BIT6 ///< Bad TLP S= tatus +#define B_PCH_PCIE_CFG_EX_CES_RE BIT0 ///< Receiver = Error Status + + +//CES.RE, CES.BT, CES.BD + +#define R_PCH_PCIE_CFG_EX_ACSECH 0x140 ///< ACS Exten= ded Capability Header +#define V_PCH_PCIE_CFG_EX_ACS_CV 0x1 +#define R_PCH_PCIE_CFG_EX_ACSCAPR (R_PCH_PCIE_CFG_EX_A= CSECH + R_PCIE_EX_ACSCAPR_OFFSET) + +#define R_PCH_PCIE_CFG_EX_L1SECH 0x200 ///< L1 Sub-St= ates Extended Capability Header +#define V_PCH_PCIE_CFG_EX_L1S_CV 0x1 +#define R_PCH_PCIE_CFG_EX_L1SCAP (R_PCH_PCIE_CFG_EX_L= 1SECH + R_PCIE_EX_L1SCAP_OFFSET) +#define R_PCH_PCIE_CFG_EX_L1SCTL1 (R_PCH_PCIE_CFG_EX_L= 1SECH + R_PCIE_EX_L1SCTL1_OFFSET) +#define R_PCH_PCIE_CFG_EX_L1SCTL2 (R_PCH_PCIE_CFG_EX_L= 1SECH + R_PCIE_EX_L1SCTL2_OFFSET) + +#define R_PCH_PCIE_CFG_EX_SPEECH 0x220 ///< Secondary= PCI Express Extended Capability Header +#define V_PCH_PCIE_CFG_EX_SPEECH_CV 0x1 +#define R_PCH_PCIE_CFG_EX_LCTL3 (R_PCH_PCIE_CFG_EX_S= PEECH + R_PCIE_EX_LCTL3_OFFSET) +#define R_PCH_PCIE_CFG_EX_LES (R_PCH_PCIE_CFG_EX_S= PEECH + R_PCIE_EX_LES_OFFSET) +#define R_PCH_PCIE_CFG_EX_LECTL (R_PCH_PCIE_CFG_EX_S= PEECH + R_PCIE_EX_L01EC_OFFSET) +#define B_PCH_PCIE_CFG_EX_LECTL_UPTPH (BIT14 | BIT13 | BIT= 12) +#define N_PCH_PCIE_CFG_EX_LECTL_UPTPH 12 +#define B_PCH_PCIE_CFG_EX_LECTL_UPTP 0x0F00 +#define N_PCH_PCIE_CFG_EX_LECTL_UPTP 8 +#define B_PCH_PCIE_CFG_EX_LECTL_DPTPH (BIT6 | BIT5 | BIT4) +#define N_PCH_PCIE_CFG_EX_LECTL_DPTPH 4 +#define B_PCH_PCIE_CFG_EX_LECTL_DPTP 0x000F +#define N_PCH_PCIE_CFG_EX_LECTL_DPTP 0 + +#define R_PCH_PCIE_CFG_EX_L01EC (R_PCH_PCIE_CFG_EX_S= PEECH + R_PCIE_EX_L01EC_OFFSET) +#define R_PCH_PCIE_CFG_EX_L23EC (R_PCH_PCIE_CFG_EX_S= PEECH + R_PCIE_EX_L23EC_OFFSET) + +#define R_PCH_PCIE_CFG_PCIERTP1 0x300 +#define R_PCH_PCIE_CFG_PCIERTP2 0x304 +#define R_PCH_PCIE_CFG_PCIENFTS 0x314 +#define R_PCH_PCIE_CFG_PCIEL0SC 0x318 + +#define R_PCH_PCIE_CFG_PCIECFG2 0x320 +#define B_PCH_PCIE_CFG_PCIECFG2_LBWSSTE BIT30 +#define B_PCH_PCIE_CFG_PCIECFG2_RLLG3R BIT27 +#define B_PCH_PCIE_CFG_PCIECFG2_CROAOV BIT24 +#define B_PCH_PCIE_CFG_PCIECFG2_CROAOE BIT23 +#define B_PCH_PCIE_CFG_PCIECFG2_CRSREN BIT22 +#define B_PCH_PCIE_CFG_PCIECFG2_PMET (BIT21 | BIT20) +#define V_PCH_PCIE_CFG_PCIECFG2_PMET 1 +#define N_PCH_PCIE_CFG_PCIECFG2_PMET 20 + +#define R_PCH_PCIE_CFG_PCIEDBG 0x324 +#define B_PCH_PCIE_CFG_PCIEDBG_LBWSSTE BIT30 +#define B_PCH_PCIE_CFG_PCIEDBG_USSP (BIT27 | BIT26) +#define B_PCH_PCIE_CFG_PCIEDBG_LGCLKSQEXITDBTIMERS (BIT25 | BIT24) +#define B_PCH_PCIE_CFG_PCIEDBG_CTONFAE BIT14 +#define B_PCH_PCIE_CFG_PCIEDBG_SQOL0 BIT7 +#define B_PCH_PCIE_CFG_PCIEDBG_SPCE BIT5 +#define B_PCH_PCIE_CFG_PCIEDBG_LR BIT4 + +#define R_PCH_PCIE_CFG_PCIESTS1 0x328 +#define B_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE 0xFF000000 +#define N_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE 24 +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DETRDY 0x01 +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DETRDYECINP1CG 0x0E +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_L0 0x33 +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DISWAIT 0x5E +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_DISWAITPG 0x60 +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_RECOVERYSPEEDREADY 0x6C +#define V_PCH_PCIE_CFG_PCIESTS1_LTSMSTATE_RECOVERYLNK2DETECT 0x6F + + +#define B_PCH_PCIE_CFG_PCIESTS1_LNKSTAT (BIT22 | BIT21 | BIT= 20 | BIT19) +#define N_PCH_PCIE_CFG_PCIESTS1_LNKSTAT 19 +#define V_PCH_PCIE_CFG_PCIESTS1_LNKSTAT_L0 0x7 + +#define R_PCH_PCIE_CFG_PCIESTS2 0x32C +#define B_PCH_PCIE_CFG_PCIESTS2_P4PNCCWSSCMES BIT31 +#define B_PCH_PCIE_CFG_PCIESTS2_P3PNCCWSSCMES BIT30 +#define B_PCH_PCIE_CFG_PCIESTS2_P2PNCCWSSCMES BIT29 +#define B_PCH_PCIE_CFG_PCIESTS2_P1PNCCWSSCMES BIT28 +#define B_PCH_PCIE_CFG_PCIESTS2_CLRE 0x0000F000 +#define N_PCH_PCIE_CFG_PCIESTS2_CLRE 12 + +#define R_PCH_PCIE_CFG_PCIEALC 0x338 +#define B_PCH_PCIE_CFG_PCIEALC_ITLRCLD BIT29 +#define B_PCH_PCIE_CFG_PCIEALC_ILLRCLD BIT28 +#define B_PCH_PCIE_CFG_PCIEALC_BLKDQDA BIT26 + + +#define R_PCH_PCIE_CFG_LTROVR 0x400 +#define B_PCH_PCIE_CFG_LTROVR_LTRNSROVR BIT31 ///< LTR Non-S= noop Requirement Bit Override +#define B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15 ///< LTR Snoop= Requirement Bit Override + +#define R_PCH_PCIE_CFG_LTROVR2 0x404 +#define B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE BIT3 ///< LTR Force = Override Enable +#define B_PCH_PCIE_CFG_LTROVR2_LOCK BIT2 ///< LTR Overri= de Lock +#define B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN BIT1 ///< LTR Non-Sn= oop Override Enable +#define B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN BIT0 ///< LTR Snoop = Override Enable + +#define R_PCH_PCIE_CFG_PHYCTL4 0x408 +#define B_PCH_PCIE_CFG_PHYCTL4_SQDIS BIT27 + +#define R_PCH_PCIE_CFG_PCIEPMECTL 0x420 +#define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE BIT30 +#define B_PCH_PCIE_CFG_PCIEPMECTL_L1LE BIT17 +#define B_PCH_PCIE_CFG_PCIEPMECTL_L1FSOE BIT0 + +#define R_PCH_PCIE_CFG_PCIEPMECTL2 0x424 +#define B_PCH_PCIE_CFG_PCIEPMECTL2_PHYCLPGE BIT11 +#define B_PCH_PCIE_CFG_PCIEPMECTL2_FDCPGE BIT8 +#define B_PCH_PCIE_CFG_PCIEPMECTL2_DETSCPGE BIT7 +#define B_PCH_PCIE_CFG_PCIEPMECTL2_L23RDYSCPGE BIT6 +#define B_PCH_PCIE_CFG_PCIEPMECTL2_DISSCPGE BIT5 +#define B_PCH_PCIE_CFG_PCIEPMECTL2_L1SCPGE BIT4 + +#define R_PCH_PCIE_CFG_PCE 0x428 +#define B_PCH_PCIE_CFG_PCE_HAE BIT5 +#define B_PCH_PCIE_CFG_PCE_PMCRE BIT0 + +#define R_PCH_PCIE_CFG_EQCFG1 0x450 +#define S_PCH_PCIE_CFG_EQCFG1 4 +#define B_PCH_PCIE_CFG_EQCFG1_REC 0xFF000000 +#define N_PCH_PCIE_CFG_EQCFG1_REC 24 +#define B_PCH_PCIE_CFG_EQCFG1_REIFECE BIT23 +#define N_PCH_PCIE_CFG_EQCFG1_LERSMIE 21 +#define B_PCH_PCIE_CFG_EQCFG1_LEP23B BIT18 +#define B_PCH_PCIE_CFG_EQCFG1_LEP3B BIT17 +#define B_PCH_PCIE_CFG_EQCFG1_RTLEPCEB BIT16 +#define B_PCH_PCIE_CFG_EQCFG1_RTPCOE BIT15 +#define B_PCH_PCIE_CFG_EQCFG1_HPCMQE BIT13 +#define B_PCH_PCIE_CFG_EQCFG1_HAED BIT12 +#define B_PCH_PCIE_CFG_EQCFG1_EQTS2IRRC BIT7 +#define B_PCH_PCIE_CFG_EQCFG1_TUPP BIT1 + +#define R_PCH_PCIE_CFG_RTPCL1 0x454 +#define B_PCH_PCIE_CFG_RTPCL1_PCM BIT31 +#define B_PCH_PCIE_CFG_RTPCL1_RTPRECL2PL4 0x3F000000 +#define B_PCH_PCIE_CFG_RTPCL1_RTPOSTCL1PL3 0xFC0000 +#define B_PCH_PCIE_CFG_RTPCL1_RTPRECL1PL2 0x3F000 +#define B_PCH_PCIE_CFG_RTPCL1_RTPOSTCL0PL1 0xFC0 +#define B_PCH_PCIE_CFG_RTPCL1_RTPRECL0PL0 0x3F + +#define R_PCH_PCIE_CFG_RTPCL2 0x458 +#define B_PCH_PCIE_CFG_RTPCL2_RTPOSTCL3PL 0x3F000 +#define B_PCH_PCIE_CFG_RTPCL2_RTPRECL3PL6 0xFC0 +#define B_PCH_PCIE_CFG_RTPCL2_RTPOSTCL2PL5 0x3F + +#define R_PCH_PCIE_CFG_RTPCL3 0x45C +#define B_PCH_PCIE_CFG_RTPCL3_RTPRECL7 0x3F000000 +#define B_PCH_PCIE_CFG_RTPCL3_RTPOSTCL6 0xFC0000 +#define B_PCH_PCIE_CFG_RTPCL3_RTPRECL6 0x3F000 +#define B_PCH_PCIE_CFG_RTPCL3_RTPOSTCL5 0xFC0 +#define B_PCH_PCIE_CFG_RTPCL3_RTPRECL5PL10 0x3F + +#define R_PCH_PCIE_CFG_RTPCL4 0x460 +#define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL9 0x3F000000 +#define B_PCH_PCIE_CFG_RTPCL4_RTPRECL9 0xFC0000 +#define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL8 0x3F000 +#define B_PCH_PCIE_CFG_RTPCL4_RTPRECL8 0xFC0 +#define B_PCH_PCIE_CFG_RTPCL4_RTPOSTCL7 0x3F + +#define R_PCH_PCIE_CFG_FOMS 0x464 +#define B_PCH_PCIE_CFG_FOMS_I (BIT30 | BIT29) +#define N_PCH_PCIE_CFG_FOMS_I 29 +#define B_PCH_PCIE_CFG_FOMS_LN 0x1F000000 +#define N_PCH_PCIE_CFG_FOMS_LN 24 +#define B_PCH_PCIE_CFG_FOMS_FOMSV 0x00FFFFFF +#define B_PCH_PCIE_CFG_FOMS_FOMSV0 0x000000FF +#define N_PCH_PCIE_CFG_FOMS_FOMSV0 0 +#define B_PCH_PCIE_CFG_FOMS_FOMSV1 0x0000FF00 +#define N_PCH_PCIE_CFG_FOMS_FOMSV1 8 +#define B_PCH_PCIE_CFG_FOMS_FOMSV2 0x00FF0000 +#define N_PCH_PCIE_CFG_FOMS_FOMSV2 16 + +#define R_PCH_PCIE_CFG_HAEQ 0x468 +#define B_PCH_PCIE_CFG_HAEQ_HAPCCPI (BIT31 | BIT30 | BIT= 29 | BIT28) +#define N_PCH_PCIE_CFG_HAEQ_HAPCCPI 28 +#define B_PCH_PCIE_CFG_HAEQ_MACFOMC BIT19 + +#define R_PCH_PCIE_CFG_LTCO1 0x470 +#define B_PCH_PCIE_CFG_LTCO1_L1TCOE BIT25 +#define B_PCH_PCIE_CFG_LTCO1_L0TCOE BIT24 +#define B_PCH_PCIE_CFG_LTCO1_L1TPOSTCO 0xFC0000 +#define N_PCH_PCIE_CFG_LTCO1_L1TPOSTCO 18 +#define B_PCH_PCIE_CFG_LTCO1_L1TPRECO 0x3F000 +#define N_PCH_PCIE_CFG_LTCO1_L1TPRECO 12 +#define B_PCH_PCIE_CFG_LTCO1_L0TPOSTCO 0xFC0 +#define N_PCH_PCIE_CFG_LTCO1_L0TPOSTCO 6 +#define B_PCH_PCIE_CFG_LTCO1_L0TPRECO 0x3F +#define N_PCH_PCIE_CFG_LTCO1_L0TPRECO 0 + +#define R_PCH_PCIE_CFG_LTCO2 0x474 +#define B_PCH_PCIE_CFG_LTCO2_L3TCOE BIT25 +#define B_PCH_PCIE_CFG_LTCO2_L2TCOE BIT24 +#define B_PCH_PCIE_CFG_LTCO2_L3TPOSTCO 0xFC0000 +#define B_PCH_PCIE_CFG_LTCO2_L3TPRECO 0x3F000 +#define B_PCH_PCIE_CFG_LTCO2_L2TPOSTCO 0xFC0 +#define B_PCH_PCIE_CFG_LTCO2_L2TPRECO 0x3F + +#define R_PCH_PCIE_CFG_G3L0SCTL 0x478 +#define B_PCH_PCIE_CFG_G3L0SCTL_G3UCNFTS 0x0000FF00 +#define B_PCH_PCIE_CFG_G3L0SCTL_G3CCNFTS 0x000000FF + +#define R_PCH_PCIE_CFG_EQCFG2 0x47C +#define B_PCH_PCIE_CFG_EQCFG2_NTIC 0xFF000000 +#define B_PCH_PCIE_CFG_EQCFG2_EMD BIT23 +#define B_PCH_PCIE_CFG_EQCFG2_NTSS (BIT22 | BIT21 | BIT= 20) +#define B_PCH_PCIE_CFG_EQCFG2_PCET (BIT19 | BIT18 | BIT= 17 | BIT16) +#define N_PCH_PCIE_CFG_EQCFG2_PCET 16 +#define B_PCH_PCIE_CFG_EQCFG2_HAPCSB (BIT15 | BIT14 | BIT= 13 | BIT12) +#define N_PCH_PCIE_CFG_EQCFG2_HAPCSB 12 +#define B_PCH_PCIE_CFG_EQCFG2_NTEME BIT11 +#define B_PCH_PCIE_CFG_EQCFG2_MPEME BIT10 +#define B_PCH_PCIE_CFG_EQCFG2_REWMETM (BIT9 | BIT8) +#define B_PCH_PCIE_CFG_EQCFG2_REWMET 0xFF + +#define R_PCH_PCIE_CFG_MM 0x480 +#define B_PCH_PCIE_CFG_MM_MSST 0xFFFFFF00 +#define N_PCH_PCIE_CFG_MM_MSST 8 +#define B_PCH_PCIE_CFG_MM_MSS 0xFF + +// +// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF) +// +#define R_SPX_PCR_PCD 0 ///<= Port configuration and disable +#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///<= Port 1 Function Number +#define B_SPX_PCR_PCD_RP1CH BIT3 ///<= Port 1 config hide +#define B_SPX_PCR_PCD_RP2FN (BIT6 | BIT5 | BIT4) ///<= Port 2 Function Number +#define B_SPX_PCR_PCD_RP2CH BIT7 ///<= Port 2 config hide +#define B_SPX_PCR_PCD_RP3FN (BIT10 | BIT9 | BIT8) ///<= Port 3 Function Number +#define B_SPX_PCR_PCD_RP3CH BIT11 ///<= Port 3 config hide +#define B_SPX_PCR_PCD_RP4FN (BIT14 | BIT13 | BIT12) ///<= Port 4 Function Number +#define B_SPX_PCR_PCD_RP4CH BIT15 ///<= Port 4 config hide +#define S_SPX_PCR_PCD_RP_FIELD 4 ///<= 4 bits for each RP FN +#define B_SPX_PCR_PCD_P1D BIT16 ///<= Port 1 disable +#define B_SPX_PCR_PCD_P2D BIT17 ///<= Port 2 disable +#define B_SPX_PCR_PCD_P3D BIT18 ///<= Port 3 disable +#define B_SPX_PCR_PCD_P4D BIT19 ///<= Port 4 disable +#define B_SPX_PCR_PCD_SRL BIT31 ///<= Secured Register Lock + +#define R_SPX_PCR_PCIEHBP 0x0004 ///<= PCI Express high-speed bypass +#define B_SPX_PCR_PCIEHBP_PCIEHBPME BIT0 ///<= PCIe HBP mode enable +#define B_SPX_PCR_PCIEHBP_PCIEGMO (BIT2 | BIT1) ///<= PCIe gen mode override +#define B_SPX_PCR_PCIEHBP_PCIETIL0O BIT3 ///<= PCIe transmitter-in-L0 override +#define B_SPX_PCR_PCIEHBP_PCIERIL0O BIT4 ///<= PCIe receiver-in-L0 override +#define B_SPX_PCR_PCIEHBP_PCIELRO BIT5 ///<= PCIe link recovery override +#define B_SPX_PCR_PCIEHBP_PCIELDO BIT6 ///<= PCIe link down override +#define B_SPX_PCR_PCIEHBP_PCIESSM BIT7 ///<= PCIe SKP suppression mode +#define B_SPX_PCR_PCIEHBP_PCIESST BIT8 ///<= PCIe suppress SKP transmission +#define B_SPX_PCR_PCIEHBP_PCIEHBPPS (BIT13 | BIT12) ///<= PCIe HBP port select +#define B_SPX_PCR_PCIEHBP_CRCSEL (BIT15 | BIT14) ///<= CRC select +#define B_SPX_PCR_PCIEHBP_PCIEHBPCRC 0xFFFF0000 ///<= PCIe HBP CRC + +// +// ICC PCR (PID: ICC) +// +#define R_ICC_PCR_TMCSRCCLK 0x1000 ///<= Timing Control SRC Clock Register +#define R_ICC_PCR_TMCSRCCLK2 0x1004 ///<= Timing Control SRC Clock Register 2 +#define R_ICC_PCR_MSKCKRQ 0x100C ///<= Mask Control CLKREQ + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sPcr.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcr= .h new file mode 100644 index 0000000000..ed1668300a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPcr.h @@ -0,0 +1,73 @@ +/** @file + Register names for PCH private chipset register + + Conventions: + + - Prefixes: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register sizes + Definitions beginning with "N_" are the bit position + - In general, PCH registers are denoted by "_PCH_" in register names + - Registers / bits that are different between PCH generations are denote= d by + "_PCH_[generation_name]_" in register/bit names. + - Registers / bits that are specific to PCH-H denoted by "_H_" in regist= er/bit names. + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regi= ster/bit names. + e.g., "_PCH_H_", "_PCH_LP_" + Registers / bits names without _H_ or _LP_ apply for both H and LP. + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a PCH generation will be= just named + as "_PCH_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PCR_H_ +#define _PCH_REGS_PCR_H_ + +/** + Definition for SBI PID + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI pro= gramming as well. +**/ +#define PID_OPIPHY 0xAC +#define PID_MODPHY0 0xAB +#define PID_MODPHY1 0xAA +#define PID_USB2 0xCA +#define PID_DMI 0x88 +#define PID_PSTH 0x89 +#define PID_DSP 0xD7 +#define PID_ESPISPI 0x72 +#define PID_FIA 0xCF +#define PID_SPF 0x85 +#define PID_SPE 0x84 +#define PID_SPD 0x83 +#define PID_SPC 0x82 +#define PID_SPB 0x81 +#define PID_SPA 0x80 +#define PID_SERIALIO 0xCB +#define PID_LPC 0xC7 +#define PID_SMB 0xC6 +#define PID_ITSS 0xC4 +#define PID_RTC_HOST 0xC3 +#define PID_PSF6 0x7F +#define PID_PSF7 0x7E +#define PID_PSF8 0x7D +#define PID_PSF4 0xBD +#define PID_PSF3 0xBC +#define PID_PSF2 0xBB +#define PID_PSF1 0xBA +#define PID_GPIOCOM0 0x6E +#define PID_GPIOCOM1 0x6D +#define PID_GPIOCOM2 0x6C +#define PID_GPIOCOM3 0x6B +#define PID_GPIOCOM4 0x6A +#define PID_CSME12 0x9C + +#define PID_CSME0 0x90 +#define PID_CSME_PSF 0x8F + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sPmc.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmc= .h new file mode 100644 index 0000000000..dcecc633a1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmc.h @@ -0,0 +1,670 @@ +/** @file + Register names for PCH PMC device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PMC_H_ +#define _PCH_REGS_PMC_H_ + +// +// PMC Registers (D31:F2) +// +#define PCI_DEVICE_NUMBER_PCH_PMC 31 +#define PCI_FUNCTION_NUMBER_PCH_PMC 2 + +#define R_PMC_CFG_BASE 0x10 +#define B_PMC_CFG_PWRM_BASE_MASK 0xFFFF0000 = ///< PWRM must be 64KB alignment to align the source decode. + +// +// ACPI and legacy I/O register offsets from ACPIBASE +// +#define R_ACPI_IO_PM1_STS 0x00 +#define S_ACPI_IO_PM1_STS 2 +#define B_ACPI_IO_PM1_STS_WAK BIT15 +#define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14 +#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11 +#define B_ACPI_IO_PM1_STS_RTC BIT10 +#define B_ACPI_IO_PM1_STS_PWRBTN BIT8 +#define B_ACPI_IO_PM1_STS_GBL BIT5 +#define B_ACPI_IO_PM1_STS_BM BIT4 +#define B_ACPI_IO_PM1_STS_TMROF BIT0 +#define N_ACPI_IO_PM1_STS_WAK 15 +#define N_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS 14 +#define N_ACPI_IO_PM1_STS_PRBTNOR 11 +#define N_ACPI_IO_PM1_STS_RTC 10 +#define N_ACPI_IO_PM1_STS_PWRBTN 8 +#define N_ACPI_IO_PM1_STS_GBL 5 +#define N_ACPI_IO_PM1_STS_BM 4 +#define N_ACPI_IO_PM1_STS_TMROF 0 + +#define R_ACPI_IO_PM1_EN 0x02 +#define S_ACPI_IO_PM1_EN 2 +#define B_ACPI_IO_PM1_EN_RTC BIT10 +#define B_ACPI_IO_PM1_EN_PWRBTN BIT8 +#define B_ACPI_IO_PM1_EN_GBL BIT5 +#define B_ACPI_IO_PM1_EN_TMROF BIT0 +#define N_ACPI_IO_PM1_EN_RTC 10 +#define N_ACPI_IO_PM1_EN_PWRBTN 8 +#define N_ACPI_IO_PM1_EN_GBL 5 +#define N_ACPI_IO_PM1_EN_TMROF 0 + +#define R_ACPI_IO_PM1_CNT 0x04 +#define S_ACPI_IO_PM1_CNT 4 +#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13 +#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10) +#define V_ACPI_IO_PM1_CNT_S0 0 +#define V_ACPI_IO_PM1_CNT_S1 BIT10 +#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10) +#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11) +#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10) +#define B_ACPI_IO_PM1_CNT_GBL_RLS BIT2 +#define B_ACPI_IO_PM1_CNT_BM_RLD BIT1 +#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0 + +#define R_ACPI_IO_PM1_TMR 0x08 +#define V_ACPI_IO_PM1_TMR_FREQUENCY 3579545 +#define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF +#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The = timer is 24 bit overflow + +#define R_ACPI_IO_SMI_EN 0x30 +#define S_ACPI_IO_SMI_EN 4 +#define B_ACPI_IO_SMI_EN_LEGACY_USB3 BIT31 +#define B_ACPI_IO_SMI_EN_GPIO_UNLOCK_SMI BIT27 +#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17 +#define B_ACPI_IO_SMI_EN_PERIODIC BIT14 +#define B_ACPI_IO_SMI_EN_TCO BIT13 +#define B_ACPI_IO_SMI_EN_MCSMI BIT11 +#define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7 +#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6 +#define B_ACPI_IO_SMI_EN_APMC BIT5 +#define B_ACPI_IO_SMI_EN_ON_SLP_EN BIT4 +#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3 +#define B_ACPI_IO_SMI_EN_BIOS BIT2 +#define B_ACPI_IO_SMI_EN_EOS BIT1 +#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0 +#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31 +#define N_ACPI_IO_SMI_EN_ESPI 28 +#define N_ACPI_IO_SMI_EN_GPIO_UNLOCK 27 +#define N_ACPI_IO_SMI_EN_INTEL_USB2 18 +#define N_ACPI_IO_SMI_EN_LEGACY_USB2 17 +#define N_ACPI_IO_SMI_EN_PERIODIC 14 +#define N_ACPI_IO_SMI_EN_TCO 13 +#define N_ACPI_IO_SMI_EN_MCSMI 11 +#define N_ACPI_IO_SMI_EN_BIOS_RLS 7 +#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6 +#define N_ACPI_IO_SMI_EN_APMC 5 +#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4 +#define N_ACPI_IO_SMI_EN_LEGACY_USB 3 +#define N_ACPI_IO_SMI_EN_BIOS 2 +#define N_ACPI_IO_SMI_EN_EOS 1 +#define N_ACPI_IO_SMI_EN_GBL_SMI 0 + +#define R_ACPI_IO_SMI_STS 0x34 +#define S_ACPI_IO_SMI_STS 4 +#define B_ACPI_IO_SMI_STS_LEGACY_USB3 BIT31 +#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27 +#define B_ACPI_IO_SMI_STS_SPI BIT26 +#define B_ACPI_IO_SMI_STS_MONITOR BIT21 +#define B_ACPI_IO_SMI_STS_PCI_EXP BIT20 +#define B_ACPI_IO_SMI_STS_PATCH BIT19 +#define B_ACPI_IO_SMI_STS_INTEL_USB2 BIT18 +#define B_ACPI_IO_SMI_STS_LEGACY_USB2 BIT17 +#define B_ACPI_IO_SMI_STS_SMBUS BIT16 +#define B_ACPI_IO_SMI_STS_SERIRQ BIT15 +#define B_ACPI_IO_SMI_STS_PERIODIC BIT14 +#define B_ACPI_IO_SMI_STS_TCO BIT13 +#define B_ACPI_IO_SMI_STS_DEVMON BIT12 +#define B_ACPI_IO_SMI_STS_MCSMI BIT11 +#define B_ACPI_IO_SMI_STS_GPIO_SMI BIT10 +#define B_ACPI_IO_SMI_STS_GPE0 BIT9 +#define B_ACPI_IO_SMI_STS_PM1_STS_REG BIT8 +#define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6 +#define B_ACPI_IO_SMI_STS_APM BIT5 +#define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4 +#define B_ACPI_IO_SMI_STS_LEGACY_USB BIT3 +#define B_ACPI_IO_SMI_STS_BIOS BIT2 +#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31 +#define N_ACPI_IO_SMI_STS_ESPI 28 +#define N_ACPI_IO_SMI_STS_GPIO_UNLOCK 27 +#define N_ACPI_IO_SMI_STS_SPI 26 +#define N_ACPI_IO_SMI_STS_MONITOR 21 +#define N_ACPI_IO_SMI_STS_PCI_EXP 20 +#define N_ACPI_IO_SMI_STS_PATCH 19 +#define N_ACPI_IO_SMI_STS_INTEL_USB2 18 +#define N_ACPI_IO_SMI_STS_LEGACY_USB2 17 +#define N_ACPI_IO_SMI_STS_SMBUS 16 +#define N_ACPI_IO_SMI_STS_SERIRQ 15 +#define N_ACPI_IO_SMI_STS_PERIODIC 14 +#define N_ACPI_IO_SMI_STS_TCO 13 +#define N_ACPI_IO_SMI_STS_DEVMON 12 +#define N_ACPI_IO_SMI_STS_MCSMI 11 +#define N_ACPI_IO_SMI_STS_GPIO_SMI 10 +#define N_ACPI_IO_SMI_STS_GPE0 9 +#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8 +#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6 +#define N_ACPI_IO_SMI_STS_APM 5 +#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4 +#define N_ACPI_IO_SMI_STS_LEGACY_USB 3 +#define N_ACPI_IO_SMI_STS_BIOS 2 + +#define R_ACPI_IO_GPE_CNTL 0x40 +#define B_ACPI_IO_GPE_CNTL_SWGPE_CTRL BIT17 + +#define R_ACPI_IO_DEVACT_STS 0x44 +#define S_ACPI_IO_DEVACT_STS 2 +#define B_ACPI_IO_DEVACT_STS_MASK 0x13E1 +#define B_ACPI_IO_DEVACT_STS_KBC BIT12 +#define B_ACPI_IO_DEVACT_STS_PIRQDH BIT9 +#define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8 +#define B_ACPI_IO_DEVACT_STS_PIRQBF BIT7 +#define B_ACPI_IO_DEVACT_STS_PIRQAE BIT6 +#define B_ACPI_IO_DEVACT_STS_D0_TRP BIT0 +#define N_ACPI_IO_DEVACT_STS_KBC 12 +#define N_ACPI_IO_DEVACT_STS_PIRQDH 9 +#define N_ACPI_IO_DEVACT_STS_PIRQCG 8 +#define N_ACPI_IO_DEVACT_STS_PIRQBF 7 +#define N_ACPI_IO_DEVACT_STS_PIRQAE 6 + +#define R_ACPI_IO_PM2_CNT 0x50 +#define B_ACPI_IO_PM2_CNT_ARB_DIS BIT0 + +#define R_ACPI_IO_OC_WDT_CTL 0x54 +#define B_ACPI_IO_OC_WDT_CTL_RLD BIT31 +#define B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS BIT25 +#define B_ACPI_IO_OC_WDT_CTL_NO_ICCSURV_STS BIT24 +#define B_ACPI_IO_OC_WDT_CTL_FORCE_ALL BIT15 +#define B_ACPI_IO_OC_WDT_CTL_EN BIT14 +#define B_ACPI_IO_OC_WDT_CTL_ICCSURV BIT13 +#define B_ACPI_IO_OC_WDT_CTL_LCK BIT12 +#define B_ACPI_IO_OC_WDT_CTL_TOV_MASK 0x3FF +#define B_ACPI_IO_OC_WDT_CTL_FAILURE_STS BIT23 +#define B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS BIT22 +#define B_ACPI_IO_OC_WDT_CTL_AFTER_POST 0x3F0000 +#define V_ACPI_IO_OC_WDT_CTL_STATUS_FAILURE 1 +#define V_ACPI_IO_OC_WDT_CTL_STATUS_OK 0 + +#define R_ACPI_IO_GPE0_STS_31_0 0x60 +#define R_ACPI_IO_GPE0_STS_63_32 0x64 +#define R_ACPI_IO_GPE0_STS_95_64 0x68 +#define R_ACPI_IO_GPE0_STS_127_96 0x6C +#define S_ACPI_IO_GPE0_STS_127_96 4 +#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18 +#define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17 +#define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16 +#define B_ACPI_IO_GPE0_STS_127_96_GPIO_TIER_2 BIT15 +#define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13 +#define B_ACPI_IO_GPE0_STS_127_96_ME_SCI BIT12 +#define B_ACPI_IO_GPE0_STS_127_96_PME BIT11 +#define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10 +#define B_ACPI_IO_GPE0_STS_127_96_PCI_EXP BIT9 +#define B_ACPI_IO_GPE0_STS_127_96_RI BIT8 +#define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7 +#define B_ACPI_IO_GPE0_STS_127_96_TC0SCI BIT6 +#define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2 +#define B_ACPI_IO_GPE0_STS_127_96_HOT_PLUG BIT1 +#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13 +#define N_ACPI_IO_GPE0_STS_127_96_PME 11 +#define N_ACPI_IO_GPE0_STS_127_96_BATLOW 10 +#define N_ACPI_IO_GPE0_STS_127_96_PCI_EXP 9 +#define N_ACPI_IO_GPE0_STS_127_96_RI 8 +#define N_ACPI_IO_GPE0_STS_127_96_SMB_WAK 7 +#define N_ACPI_IO_GPE0_STS_127_96_TC0SCI 6 +#define N_ACPI_IO_GPE0_STS_127_96_SWGPE 2 +#define N_ACPI_IO_GPE0_STS_127_96_HOT_PLUG 1 + +#define R_ACPI_IO_GPE0_EN_31_0 0x70 +#define R_ACPI_IO_GPE0_EN_63_32 0x74 +#define R_ACPI_IO_GPE0_EN_95_64 0x78 +#define R_ACPI_IO_GPE0_EN_127_96 0x7C +#define S_ACPI_IO_GPE0_EN_127_96 4 +#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18 +#define B_ACPI_IO_GPE0_EN_127_96_USB_CON_DSX_EN BIT17 +#define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16 +#define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13 +#define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12 +#define B_ACPI_IO_GPE0_EN_127_96_PME BIT11 +#define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10 +#define B_ACPI_IO_GPE0_EN_127_96_PCI_EXP BIT9 +#define B_ACPI_IO_GPE0_EN_127_96_RI BIT8 +#define B_ACPI_IO_GPE0_EN_127_96_TC0SCI BIT6 +#define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2 +#define B_ACPI_IO_GPE0_EN_127_96_HOT_PLUG BIT1 +#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13 +#define N_ACPI_IO_GPE0_EN_127_96_USB3 12 +#define N_ACPI_IO_GPE0_EN_127_96_PME 11 +#define N_ACPI_IO_GPE0_EN_127_96_BATLOW 10 +#define N_ACPI_IO_GPE0_EN_127_96_PCI_EXP 9 +#define N_ACPI_IO_GPE0_EN_127_96_RI 8 +#define N_ACPI_IO_GPE0_EN_127_96_TC0SCI 6 +#define N_ACPI_IO_GPE0_EN_127_96_SWGPE 2 +#define N_ACPI_IO_GPE0_EN_127_96_HOT_PLUG 1 + + +// +// TCO register I/O map +// +#define R_TCO_IO_RLD 0x0 +#define R_TCO_IO_DAT_IN 0x2 +#define R_TCO_IO_DAT_OUT 0x3 +#define R_TCO_IO_TCO1_STS 0x04 +#define S_TCO_IO_TCO1_STS 2 +#define B_TCO_IO_TCO1_STS_DMISERR BIT12 +#define B_TCO_IO_TCO1_STS_DMISMI BIT10 +#define B_TCO_IO_TCO1_STS_DMISCI BIT9 +#define B_TCO_IO_TCO1_STS_BIOSWR BIT8 +#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7 +#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3 +#define B_TCO_IO_TCO1_STS_TCO_INT BIT2 +#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1 +#define N_TCO_IO_TCO1_STS_DMISMI 10 +#define N_TCO_IO_TCO1_STS_BIOSWR 8 +#define N_TCO_IO_TCO1_STS_NEWCENTURY 7 +#define N_TCO_IO_TCO1_STS_TIMEOUT 3 +#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1 + +#define R_TCO_IO_TCO2_STS 0x06 +#define S_TCO_IO_TCO2_STS 2 +#define B_TCO_IO_TCO2_STS_SMLINK_SLV_SMI BIT4 +#define B_TCO_IO_TCO2_STS_BAD_BIOS BIT3 +#define B_TCO_IO_TCO2_STS_BOOT BIT2 +#define B_TCO_IO_TCO2_STS_SECOND_TO BIT1 +#define B_TCO_IO_TCO2_STS_INTRD_DET BIT0 +#define N_TCO_IO_TCO2_STS_INTRD_DET 0 + +#define R_TCO_IO_TCO1_CNT 0x08 +#define S_TCO_IO_TCO1_CNT 2 +#define B_TCO_IO_TCO1_CNT_LOCK BIT12 +#define B_TCO_IO_TCO1_CNT_TMR_HLT BIT11 +#define B_TCO_IO_TCO1_CNT_NR_MSUS BIT0 //NO_REBOOT + +#define R_TCO_IO_TCO2_CNT 0x0A +#define S_TCO_IO_TCO2_CNT 2 +#define B_TCO_IO_TCO2_CNT_OS_POLICY 0x0030 +#define B_TCO_IO_TCO2_CNT_GPI11_ALERT_DISABLE 0x0008 +#define B_TCO_IO_TCO2_CNT_INTRD_SEL 0x0006 +#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2 + +#define R_TCO_IO_MESSAGE1 0x0C +#define R_TCO_IO_MESSAGE2 0x0D +#define R_TCO_IO_TWDS 0x0E ///< T= CO_WDSTATUS register. +#define R_TCO_IO_LE 0x10 ///< L= EGACY_ELIM register +#define B_TCO_IO_LE_IRQ12_CAUSE BIT1 +#define B_TCO_IO_LE_IRQ1_CAUSE BIT0 +#define R_TCO_IO_TMR 0x12 + +// +// PWRM Registers for IPC interface +// +#define R_PMC_PWRM_IPC_CMD 0x00 = ///< IPC command +#define N_PMC_PWRM_IPC_CMD_CMD_ID 12 = ///< IPC command.cmd.ID +#define N_PMC_PWRM_IPC_CMD_SIZE 16 = ///< IPC command.size +#define B_PMC_PWRM_IPC_CMD_SIZE_MASK 0x00FF0000 = ///< IPC command.size mask Bits[23:16] +#define N_PMC_PWRM_IPC_CMD_COMMAND 0 = ///< IPC command.cmd.Command +#define B_PMC_PWRM_IPC_CMD_COMMAND_MASK 0x000000FF = ///< IPC command.size mask Bits[07:00] +#define V_PMC_PWRM_IPC_CMD_COMMAND_SLP_CTRL 0xA1 = ///< IPC commmand to control S0ix policies RCOMP +#define V_PMC_PWRM_IPC_CMD_COMMAND_NPK_STATE 0xA4 = ///< IPC commmand to control NPK Power State +#define V_PMC_PWRM_IPC_CMD_COMMAND_PROXY 0xAA = ///< Proxy access to SOC registers +#define V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_READ 0 = ///< Read command +#define V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_WRITE 1 = ///< Write command +#define V_PMC_PWRM_IPC_CMD_WBUF0_PROXY_NMI 2 = ///< parameter to access NMI control register +#define R_PMC_PWRM_IPC_STS 0x04 = ///< IPC Status +#define B_PMC_PWRM_IPC_STS_BUSY BIT0 = ///< IPC Status Busy Bit +#define B_PMC_PWRM_IPC_STS_ERROR BIT1 = ///< IPC Status Error Bit +#define N_PMC_PWRM_IPC_STS_ERR_CODE BIT16 = ///< IPC Status Error status +#define B_PMC_PWRM_IPC_STS_ERR_CODE_MASK 0x00FF0000 = ///< IPC Status Error status mask[23:16] +#define R_PMC_PWRM_IPC_SPTR 0x08 = ///< IPC Source Pointer +#define R_PMC_PWRM_IPC_DPTR 0x0C = ///< IPC Destination Pointer +#define R_PMC_PWRM_IPC_WBUF0 0x80 = ///< IPC Write Buffer +#define R_PMC_PWRM_IPC_WBUF1 0x84 = ///< IPC Write Buffer +#define R_PMC_PWRM_IPC_WBUF2 0x88 = ///< IPC Write Buffer +#define R_PMC_PWRM_IPC_WBUF3 0x8C = ///< IPC Write Buffer +#define R_PMC_PWRM_IPC_RBUF0 0x90 = ///< IPC Read Buffer +#define R_PMC_PWRM_IPC_RBUF1 0x94 = ///< IPC Read Buffer +#define R_PMC_PWRM_IPC_RBUF2 0x98 = ///< IPC Read Buffer +#define R_PMC_PWRM_IPC_RBUF3 0x9C = ///< IPC Read Buffer +// +// PWRM Registers +// +#define R_PMC_PWRM_GEN_PMCON_A 0x1020 +#define B_PMC_PWRM_GEN_PMCON_A_DC_PP_DIS BIT30 +#define B_PMC_PWRM_GEN_PMCON_A_DSX_PP_DIS BIT29 +#define B_PMC_PWRM_GEN_PMCON_A_AG3_PP_EN BIT28 +#define B_PMC_PWRM_GEN_PMCON_A_SX_PP_EN BIT27 +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_ICLK_PLL BIT26 +#define B_PMC_PWRM_GEN_PMCON_A_MPHY_CRICLK_GATE_OVR BIT25 +#define B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24 +#define B_PMC_PWRM_GEN_PMCON_A_DISB BIT23 +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_OPI_PLL_SD_INC0 BIT22 +#define B_PMC_PWRM_GEN_PMCON_A_MEM_SR BIT21 +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_SPXB_CG_INC0 BIT20 +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19 +#define B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18 +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_OPI_ON BIT17 +#define B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16 +#define B_PMC_PWRM_GEN_PMCON_A_PME_B0_S5_DIS BIT15 +#define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14 +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_BCLKREQ_ON BIT13 +#define B_PMC_PWRM_GEN_PMCON_A_DISABLE_SX_STRETCH BIT12 +#define B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9 +#define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8 +#define B_PMC_PWRM_GEN_PMCON_A_SLP_S4_ASE BIT3 +#define B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN BIT0 +#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0 +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0 +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80 +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40 +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00 +#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL 0x6 +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000 +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002 +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004 +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006 + +#define R_PMC_PWRM_GEN_PMCON_B 0x1024 +#define B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 = ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width +#define B_PMC_PWRM_GEN_PMCON_B_WOL_EN_OVRD BIT13 +#define B_PMC_PWRM_GEN_PMCON_B_BIOS_PCI_EXP_EN BIT10 +#define B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9 +#define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4 +#define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2 + +#define R_PMC_PWRM_CRID 0x1030 = ///< Configured Revision ID +#define B_PMC_PWRM_CRID_RID_SEL (BIT0 | BIT1) = ///< RID Select +#define V_PMC_PWRM_CRID_RID_SEL_REVISIONID 0 +#define V_PMC_PWRM_CRID_RID_SEL_CRID0 1 +#define B_PMC_PWRM_CRID_CRID_LK BIT31 = ///< CRID Lock + +#define R_PMC_PWRM_ETR3 0x1048 = ///< this is PWRM register +#define B_PMC_PWRM_ETR3_CF9LOCK BIT31 = ///< CF9h Lockdown +#define B_PMC_PWRM_ETR3_LATCH_EVENTS_C10_EXIT BIT30 +#define B_PMC_PWRM_ETR3_USB_CACHE_DIS BIT21 +#define B_PMC_PWRM_ETR3_CF9GR BIT20 = ///< CF9h Global Reset +#define B_PMC_PWRM_ETR3_SKIP_HOST_RST_HS BIT19 +#define B_PMC_PWRM_ETR3_CWORWRE BIT18 +#define B_PMC_PWRM_THROT_1_VR_ALERT BIT0 + +#define R_PMC_PWRM_SSML 0x104C = ///< Set Strap Msg Lock +#define B_PMC_PWRM_SSML_SSL BIT0 = ///< Set_Strap Lock +#define R_PMC_PWRM_SSMC 0x1050 = ///< Set Strap Msg Control +#define B_PMC_PWRM_SSMC_SSMS BIT0 = ///< Set_Strap Mux Select +#define R_PMC_PWRM_SSMD 0x1054 = ///< Set Strap Msg Data + +#define R_PMC_PWRM_MODPHY_PM_CFG5 0x10D0 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS2 BIT26 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_DMI BIT25 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_E3 BIT24 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_E2 BIT23 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_E1 BIT22 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_E0 BIT21 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D3 BIT20 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D2 BIT19 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D1 BIT18 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_D0 BIT17 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_UFS BIT16 ///< = UFS ModPHY SPD RT Request +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XDCI BIT15 ///< = xDCI ModPHY SPD RT Request +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_XHCI BIT14 ///< = xHCI ModPHY SPD RT Request +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_GBE BIT13 ///< = GbE ModPHY SPD RT Request +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_SATA BIT12 ///< = SATA ModPHY SPD RT Request +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C3 BIT11 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C2 BIT10 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C1 BIT9 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_C0 BIT8 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B3 BIT7 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B2 BIT6 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B1 BIT5 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_B0 BIT4 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A3 BIT3 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A2 BIT2 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A1 BIT1 +#define B_PMC_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_A0 BIT0 +#define R_PMC_PWRM_WADT_AC 0x1800 +#define R_PMC_PWRM_PRSTS 0x1810 = ///< Power and Reset Status +#define B_PMC_PWRM_PRSTS_VE_WD_TMR_STS BIT7 = ///< VE Watchdog Timer Status +#define B_PMC_PWRM_PRSTS_WOL_OVR_WK_STS BIT5 +#define B_PMC_PWRM_PRSTS_FIELD_1 BIT4 +#define B_PMC_PWRM_PRSTS_ME_WAKE_STS BIT0 + +#define R_PMC_PWRM_1814 0x1814 +#define R_PMC_PWRM_CFG 0x1818 = ///< Power Management Configuration +#define B_PMC_PWRM_CFG_ALLOW_24_OSC_SD BIT29 = ///< Allow 24MHz Crystal Oscillator Shutdown +#define B_PMC_PWRM_CFG_DBG_MODE_LOCK BIT27 = ///< Debug Mode Lock +#define B_PMC_PWRM_CFG_ALLOW_USB2_CORE_PG BIT25 = ///< Allow USB2 Core Power Gating +#define B_PMC_PWRM_CFG_ER_LOCK BIT24 = ///< Energy Reporting Lock +#define B_PMC_PWRM_CFG_EN_PMC_UNC_ERR BIT23 = ///< Enable Global Reset on Uncorrectable Parity Error on PMC= SRAM Interface +#define B_PMC_PWRM_CFG_PMCREAD_DISABLE BIT22 = ///< Disable Reads to PMC +#define B_PMC_PWRM_CFG_RTC_DS_WAKE_DIS BIT21 = ///< RTC Wake from Deep S4/S5 Disable +#define B_PMC_PWRM_CFG_SSMAW_MASK (BIT19 | BIT18= ) ///< SLP_SUS# Min Assertion Width +#define V_PMC_PWRM_CFG_SSMAW_4S (BIT19 | BIT18= ) ///< 4 seconds +#define V_PMC_PWRM_CFG_SSMAW_1S BIT19 = ///< 1 second +#define V_PMC_PWRM_CFG_SSMAW_0_5S BIT18 = ///< 0.5 second (500ms) +#define V_PMC_PWRM_CFG_SSMAW_0S 0 = ///< 0 second +#define B_PMC_PWRM_CFG_SAMAW_MASK (BIT17 | BIT16= ) ///< SLP_A# Min Assertion Width +#define V_PMC_PWRM_CFG_SAMAW_2S (BIT17 | BIT16= ) ///< 2 seconds +#define V_PMC_PWRM_CFG_SAMAW_98ms BIT17 = ///< 98ms +#define V_PMC_PWRM_CFG_SAMAW_4S BIT16 = ///< 4 seconds +#define V_PMC_PWRM_CFG_SAMAW_0S 0 = ///< 0 second +#define B_PMC_PWRM_CFG_RPCD_MASK (BIT9 | BIT8) = ///< Reset Power Cycle Duration +#define V_PMC_PWRM_CFG_RPCD_1S (BIT9 | BIT8) = ///< 1-2 seconds +#define V_PMC_PWRM_CFG_RPCD_2S BIT9 = ///< 2-3 seconds +#define V_PMC_PWRM_CFG_RPCD_3S BIT8 = ///< 3-4 seconds +#define V_PMC_PWRM_CFG_RPCD_4S 0 = ///< 4-5 seconds (Default) +#define B_PMC_PWRM_CFG_COCS BIT5 = ///< CPU OC Strap +#define B_PMC_PWRM_CFG_ER_EN BIT2 = ///< Energy Reporting Enable +#define B_PMC_PWRM_CFG_TIMING_TPCH25 (BIT1 | BIT0) = ///< tPCH25 timing + +#define R_PMC_PWRM_S3_PWRGATE_POL 0x1828 = ///< S3 Power Gating Policies +#define B_PMC_PWRM_S3_PWRGATE_POL_S3DC_GATE_SUS BIT1 = ///< Deep S3 Enable in DC Mode +#define B_PMC_PWRM_S3_PWRGATE_POL_S3AC_GATE_SUS BIT0 = ///< Deep S3 Enable in AC Mode + +#define R_PMC_PWRM_S4_PWRGATE_POL 0x182C = ///< Deep S4 Power Policies +#define B_PMC_PWRM_S4_PWRGATE_POL_S4DC_GATE_SUS BIT1 = ///< Deep S4 Enable in DC Mode +#define B_PMC_PWRM_S4_PWRGATE_POL_S4AC_GATE_SUS BIT0 = ///< Deep S4 Enable in AC Mode + +#define R_PMC_PWRM_S5_PWRGATE_POL 0x1830 = ///< Deep S5 Power Policies +#define B_PMC_PWRM_S5_PWRGATE_POL_S5DC_GATE_SUS BIT15 = ///< Deep S5 Enable in DC Mode +#define B_PMC_PWRM_S5_PWRGATE_POL_S5AC_GATE_SUS BIT14 = ///< Deep S5 Enable in AC Mode + +#define R_PMC_PWRM_DSX_CFG 0x1834 = ///< Deep SX Configuration +#define B_PMC_PWRM_DSX_CFG_WAKE_PIN_DSX_EN BIT2 = ///< WAKE# Pin DeepSx Enable +#define B_PMC_PWRM_DSX_CFG_ACPRES_PD_DSX_DIS BIT1 = ///< AC_PRESENT pin pulldown in DeepSx disable +#define B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 = ///< LAN_WAKE Pin DeepSx Enable + +#define R_PMC_PWRM_CFG2 0x183C = ///< Power Management Configuration Reg 2 +#define B_PMC_PWRM_CFG2_PBOP (BIT31 | BIT30= | BIT29) ///< Power Button Override Period (PBOP) +#define N_PMC_PWRM_CFG2_PBOP 29 = ///< Power Button Override Period (PBOP) +#define B_PMC_PWRM_CFG2_PB_DIS BIT28 = ///< Power Button Native Mode Disable (PB_DIS) +#define B_PMC_PWRM_CFG2_EN_DBG_MSG BIT27 = ///< Enable PMC Debug Messages +#define B_PMC_PWRM_CFG2_DRAM_RESET_CTL BIT26 = ///< DRAM RESET# control +#define N_PMC_PWRM_CFG2_DRAM_RESET_CTL 26 + +#define R_PMC_PWRM_EN_SN_SLOW_RING 0x1848 = ///< Enable Snoop Request to SLOW_RING +#define R_PMC_PWRM_EN_SN_SLOW_RING2 0x184C = ///< Enable Snoop Request to SLOW_RING 2nd Reg +#define R_PMC_PWRM_EN_SN_SA 0x1850 = ///< Enable Snoop Request to SA +#define R_PMC_PWRM_EN_SN_SA2 0x1854 = ///< Enable Snoop Request to SA 2nd Reg +#define R_PMC_PWRM_EN_SN_SLOW_RING_CF 0x1858 = ///< Enable Snoop Request to SLOW_RING_CF +#define R_PMC_PWRM_EN_NS_SA 0x1868 = ///< Enable Non-Snoop Request to SA +#define R_PMC_PWRM_EN_CW_SLOW_RING 0x1880 = ///< Enable Clock Wake to SLOW_RING +#define R_PMC_PWRM_EN_CW_SLOW_RING2 0x1884 = ///< Enable Clock Wake to SLOW_RING 2nd Reg +#define R_PMC_PWRM_EN_CW_SA 0x1888 = ///< Enable Clock Wake to SA +#define R_PMC_PWRM_EN_CW_SA2 0x188C = ///< Enable Clock Wake to SA 2nd Reg +#define R_PMC_PWRM_EN_CW_SLOW_RING_CF 0x1898 = ///< Enable Clock Wake to SLOW_RING_CF +#define R_PMC_PWRM_EN_PA_SLOW_RING 0x18A8 = ///< Enable Pegged Active to SLOW_RING +#define R_PMC_PWRM_EN_PA_SLOW_RING2 0x18AC = ///< Enable Pegged Active to SLOW_RING 2nd Reg +#define R_PMC_PWRM_EN_PA_SA 0x18B0 = ///< Enable Pegged Active to SA +#define R_PMC_PWRM_EN_PA_SA2 0x18B4 = ///< Enable Pegged Active to SA 2nd Reg +#define R_PMC_PWRM_EN_MISC_EVENT 0x18C0 = ///< Enable Misc PM_SYNC Events +#define R_PMC_PWRM_PMSYNC_TPR_CONFIG 0x18C4 +#define B_PMC_PWRM_PMSYNC_TPR_CONFIG_LOCK BIT31 +#define B_PMC_PWRM_PMSYNC_PCH2CPU_TT_EN BIT26 +#define B_PMC_PWRM_PMSYNC_PCH2CPU_TT_STATE (BIT25 | BIT24) +#define N_PMC_PWRM_PMSYNC_PCH2CPU_TT_STATE 24 +#define V_PMC_PWRM_PMSYNC_PCH2CPU_TT_STATE_1 1 +#define B_PMC_PWRM_PMSYNC_PM_SYNC_LOCK BIT15 = ///< PM_SYNC Configuration Lock +#define B_PMC_PWRM_PMSYNC_GPIO_D_SEL BIT11 +#define B_PMC_PWRM_PMSYNC_GPIO_C_SEL BIT10 + +#define R_PMC_PWRM_PM_SYNC_STATE_HYS 0x18D0 = ///< PM_SYNC State Hysteresis +#define R_PMC_PWRM_PM_SYNC_MODE 0x18D4 = ///< PM_SYNC Pin Mode + +#define R_PMC_PWRM_CFG3 0x18E0 = ///< Power Management Configuration Reg 3 +#define B_PMC_PWRM_CFG3_HOST_WLAN_PP_EN BIT17 = ///< Host Wireless LAN Phy Power Enable +#define B_PMC_PWRM_CFG3_DSX_WLAN_PP_EN BIT16 = ///< Deep-Sx WLAN Phy Power Enable + +#define R_PMC_PWRM_PM_DOWN_PPB_CFG 0x18E4 = ///< PM_DOWN PCH_POWER_BUDGET CONFIGURATION + +#define R_PMC_PWRM_CFG4 0x18E8 = ///< Power Management Configuration Reg 4 +#define B_PMC_PWRM_CFG4_U2_PHY_PG_EN BIT30 = ///< USB2 PHY SUS Well Power Gating Enable +#define B_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR (0x000001FF) = ///< CPU I/O VR Ramp Duration, [8:0] +#define N_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR 0 +#define V_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR_70US 0x007 +#define V_PMC_PWRM_CFG4_CPU_IOVR_RAMP_DUR_240US 0x018 + +#define R_PMC_PWRM_CPU_EPOC 0x18EC + +#define R_PMC_PWRM_GPIO_CFG 0x1920 +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10= | BIT9 | BIT8) +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW2 8 +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 |= BIT5 | BIT4) +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW1 4 +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 |= BIT1 | BIT0) +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW0 0 + + +#define R_PMC_PWRM_CS_SD_CTL1 0x1BE8 = ///< Clock Source Shutdown Control Reg 1 +#define B_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG (BIT22 | BIT21= | BIT20) ///< Clock Source 5 Control Configuration +#define N_PMC_PWRM_CS_SD_CTL1_CS5_CTL_CFG 20 +#define B_PMC_PWRM_CS_SD_CTL1_CS1_CTL_CFG (BIT2 | BIT1 |= BIT0) ///< Clock Source 1 Control Configuration +#define N_PMC_PWRM_CS_SD_CTL1_CS1_CTL_CFG 0 + +#define R_PMC_PWRM_CS_SD_CTL2 0x1BEC ///< Cl= ock Source Shutdown Control Reg 2 + +#define R_PMC_PWRM_HSWPGCR1 0x1DD0 +#define B_PMC_PWRM_SW_PG_CTRL_LOCK BIT31 +#define B_PMC_PWRM_NPK_VNN_SW_PG_CTRL BIT0 + +#define R_PMC_PWRM_1E00 0x1E00 +#define R_PMC_PWRM_1E04 0x1E04 + +#define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20 ///< St= atic PG Related Function Disable Register 1 +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_CNVI_FDIS_PMC BIT1 ///< CN= Vi Function Disable (PMC Version) (CNVI_FDIS_PMC) +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Sta= tic Function Disable Lock (ST_FDIS_LK) +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_CAM_FDIS_PMC BIT6 ///< Cam= era Function Disable (PMC Version) (CAM_FDIS_PMC) +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC BIT5 ///< SH = Function Disable (PMC Version) (ISH_FDIS_PMC) +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC BIT0 ///< GBE= Function Disable (PMC Version) (GBE_FDIS_PMC) + +#define R_PMC_PWRM_ST_PG_FDIS_PMC_2 0x1E24 ///< St= atic Function Disable Control Register 2 +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI2_FDIS_PMC BIT11 ///< Ser= ialIo Controller GSPI Device 2 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI1_FDIS_PMC BIT10 ///< Ser= ialIo Controller GSPI Device 1 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_GSPI0_FDIS_PMC BIT9 ///< Ser= ialIo Controller GSPI Device 0 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART2_FDIS_PMC BIT8 ///< Ser= ialIo Controller UART Device 2 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART1_FDIS_PMC BIT7 ///< Ser= ialIo Controller UART Device 1 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_UART0_FDIS_PMC BIT6 ///< Ser= ialIo Controller UART Device 0 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C5_FDIS_PMC BIT5 ///< Ser= ialIo Controller I2C Device 5 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C4_FDIS_PMC BIT4 ///< Ser= ialIo Controller I2C Device 4 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C3_FDIS_PMC BIT3 ///< Ser= ialIo Controller I2C Device 3 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C2_FDIS_PMC BIT2 ///< Ser= ialIo Controller I2C Device 2 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C1_FDIS_PMC BIT1 ///< Ser= ialIo Controller I2C Device 1 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO_I2C0_FDIS_PMC BIT0 ///< Ser= ialIo Controller I2C Device 0 Function Disable +#define B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO 0xFFF ///< Se= rialIo Devices Disable Mask + +#define R_PMC_PWRM_NST_PG_FDIS_1 0x1E28 +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F3_FDIS_PMC BIT31 ///< PC= Ie Controller F Port 3 Function Disable +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F2_FDIS_PMC BIT30 ///< PC= Ie Controller F Port 2 Function Disable +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F1_FDIS_PMC BIT29 ///< PC= Ie Controller F Port 1 Function Disable +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F0_FDIS_PMC BIT28 ///< PC= Ie Controller F Port 0 Function Disable +#define B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC BIT29 ///< SD= Card Function Disable +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC BIT27 ///< SD= Card Function Disable +#define B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_EMMC_FDIS_PMC BIT28 ///< eM= MC Function Disable +#define B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_UFS_FDIS_PMC BIT27 ///< UF= S Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_XDCI_FDIS_PMC BIT26 ///< XD= CI Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_SMBUS_FDIS_PMC BIT25 ///< Sm= bus Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_ADSP_FDIS_PMC BIT23 ///< AD= SP Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_SATA_FDIS_PMC BIT22 ///< SA= TA Function Disable +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E3_FDIS_PMC BIT21 ///< PC= Ie Controller E Port 3 Function Disable +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E2_FDIS_PMC BIT20 ///< PC= Ie Controller E Port 2 Function Disable +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E1_FDIS_PMC BIT19 ///< PC= Ie Controller E Port 1 Function Disable +#define B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_E0_FDIS_PMC BIT18 ///< PC= Ie Controller E Port 0 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D3_FDIS_PMC BIT17 ///< PC= Ie Controller D Port 3 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D2_FDIS_PMC BIT16 ///< PC= Ie Controller D Port 2 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D1_FDIS_PMC BIT15 ///< PC= Ie Controller D Port 1 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_D0_FDIS_PMC BIT14 ///< PC= Ie Controller D Port 0 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C3_FDIS_PMC BIT13 ///< PC= Ie Controller C Port 3 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C2_FDIS_PMC BIT12 ///< PC= Ie Controller C Port 2 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C1_FDIS_PMC BIT11 ///< PC= Ie Controller C Port 1 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_C0_FDIS_PMC BIT10 ///< PC= Ie Controller C Port 0 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_B3_FDIS_PMC BIT9 ///< PC= Ie Controller B Port 3 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_B2_FDIS_PMC BIT8 ///< PC= Ie Controller B Port 2 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_B1_FDIS_PMC BIT7 ///< PC= Ie Controller B Port 1 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_B0_FDIS_PMC BIT6 ///< PC= Ie Controller B Port 0 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A3_FDIS_PMC BIT5 ///< PC= Ie Controller A Port 3 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A2_FDIS_PMC BIT4 ///< PC= Ie Controller A Port 2 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A1_FDIS_PMC BIT3 ///< PC= Ie Controller A Port 1 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC BIT2 ///< PC= Ie Controller A Port 0 Function Disable +#define B_PMC_PWRM_NST_PG_FDIS_1_XHCI_FDIS_PMC BIT0 ///< XH= CI Function Disable + +#define R_PMC_PWRM_FUSE_DIS_RD_2 0x1E44 ///< Fu= se Disable Read 2 Register +#define B_PMC_PWRM_FUSE_DIS_RD_2_SPC_SS_DIS BIT25 ///< SPC= Fuse Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_SPB_SS_DIS BIT24 ///< SPB= Fuse Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_SPA_SS_DIS BIT23 ///< SPA= Fuse Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_PSTH_FUSE_SS_DIS BIT21 ///< PST= H Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_DMI_FUSE_SS_DIS BIT20 ///< DMI= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS BIT19 ///< OTG= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_XHCI_SS_DIS BIT18 ///< XHC= I Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_FIA_FUSE_SS_DIS BIT17 ///< FIA= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_DSP_FUSE_SS_DIS BIT16 ///< DSP= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS BIT15 ///< SAT= A Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_ICC_FUSE_SS_DIS BIT14 ///< ICC= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_LPC_FUSE_SS_DIS BIT13 ///< LPC= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_RTC_FUSE_SS_DIS BIT12 ///< RTC= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_P2S_FUSE_SS_DIS BIT11 ///< P2S= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_TRSB_FUSE_SS_DIS BIT10 ///< TRS= B Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_SMB_FUSE_SS_DIS BIT9 ///< SMB= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_ITSS_FUSE_SS_DIS BIT8 ///< ITS= S Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_UFSX2_FUSE_SS_DIS BIT7 ///< UF= SX2 Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS BIT6 ///< Ser= ialIo Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_EMMC_FUSE_SS_DIS BIT5 ///< EM= MC Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_CNVI_FUSE_SS_DIS BIT4 ///< CN= Vi Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_P2D_FUSE_SS_DIS BIT3 ///< P2D= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_SDX_FUSE_SS_DIS BIT2 ///< SD= Conroller Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS BIT1 ///< ISH= Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE= Fuse or Soft Strap Disable + +#define R_PMC_PWRM_FUSE_DIS_RD_3 0x1E48 ///< St= atic PG Fuse and Soft Strap Disable Read Register 3 +#define B_PMC_PWRM_FUSE_DIS_RD_3_PNCRA3_FUSE_SS_DIS BIT3 ///< PNC= RA3 Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_3_PNCRA2_FUSE_SS_DIS BIT2 ///< PNC= RA2 Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_3_PNCRA1_FUSE_SS_DIS BIT1 ///< PNC= RA1 Fuse or Soft Strap Disable +#define B_PMC_PWRM_FUSE_DIS_RD_3_PNCRA_FUSE_SS_DIS BIT0 ///< PNC= RA Fuse or Soft Strap Disable + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sPmcCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs= PmcCnl.h new file mode 100644 index 0000000000..bd0c2574f2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPmcCnl= .h @@ -0,0 +1,72 @@ +/** @file + Register names for PCH PMC device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PMC_CNL_H_ +#define _PCH_REGS_PMC_CNL_H_ + +// +// PWRM Registers +// +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_A 0x0 +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_B 0x1 +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_C 0xD +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_D 0x4 +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_E 0xE +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_F 0x5 +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_G 0x2 +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_H 0x6 +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPD 0xA +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_VGPIO 0x7 +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_SPI 0x3 +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_AZA 0xB +#define V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_JTAG 0xF + +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_A 0x0 +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_B 0x1 +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_C 0x2 +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_D 0x3 +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_E 0xA +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_F 0xB +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_G 0x4 +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_H 0x9 +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_I 0xC +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_J 0xD +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_K 0x8 +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPD 0x7 +#define V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_VGPIO 0x5 + +#endif // _PCH_REGS_PMC_CNL_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sPsf.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsf= .h new file mode 100644 index 0000000000..5c4d583904 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h @@ -0,0 +1,104 @@ +/** @file + Register definition for PSF component + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PSF_H_ +#define _PCH_REGS_PSF_H_ + +// +// Private chipset register (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PSFx segment registers +// +#define R_PCH_PSF_PCR_GLOBAL_CONFIG 0x4000 = ///< PSF Segment Global Configuration Register +#define B_PCH_PSF_PCR_ROOTSPACE_CONFIG_RSX_ENADDRP2P BIT1 +#define B_PCH_PSF_PCR_ROOTSPACE_CONFIG_RSX_VTDEN BIT0 + +#define S_PCH_PSFX_PCR_DEV_GNTCNT_RELOAD_DGCR 4 +#define S_PCH_PSFX_PCR_TARGET_GNTCNT_RELOAD 4 +#define B_PCH_PSFX_PCR_DEV_GNTCNT_RELOAD_DGCR_GNT_CNT_RELOAD 0x1F +#define B_PCH_PSFX_PCR_TARGET_GNTCNT_RELOAD_GNT_CNT_RELOAD 0x1F + +#define N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC 1 +#define B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN BIT0 + +// +// PSFx PCRs definitions +// +#define R_PCH_PSFX_PCR_T0_SHDW_BAR0 0 = ///< PCI BAR0 +#define R_PCH_PSFX_PCR_T0_SHDW_BAR1 0x04 = ///< PCI BAR1 +#define R_PCH_PSFX_PCR_T0_SHDW_BAR2 0x08 = ///< PCI BAR2 +#define R_PCH_PSFX_PCR_T0_SHDW_BAR3 0x0C = ///< PCI BAR3 +#define R_PCH_PSFX_PCR_T0_SHDW_BAR4 0x10 = ///< PCI BAR4 +#define R_PCH_PSFX_PCR_T0_SHDW_PCIEN 0x1C = ///< PCI configuration space enable bits +#define N_PCH_PSFX_PCR_T0_SHDW_PCIEN_BARXDIS 16 +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR0DIS BIT16 = ///< Disable BAR0 +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR1DIS BIT17 = ///< Disable BAR1 +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR2DIS BIT18 = ///< Disable BAR2 +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR3DIS BIT19 = ///< Disable BAR3 +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR4DIS BIT20 = ///< Disable BAR4 +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_BAR5DIS BIT21 = ///< Disable BAR5 +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS BIT8 = ///< Function disable +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_MEMEN BIT1 = ///< Memory decoding enable +#define B_PCH_PSFX_PCR_T0_SHDW_PCIEN_IOEN BIT0 = ///< IO decoding enable +#define R_PCH_PSFX_PCR_T0_SHDW_PMCSR 0x20 = ///< PCI power management configuration +#define B_PCH_PSFX_PCR_T0_SHDW_PMCSR_PWRST (BIT1 | BIT0) = ///< Power status +#define R_PCH_PSFX_PCR_T0_SHDW_CFG_DIS 0x38 = ///< PCI configuration disable +#define B_PCH_PSFX_PCR_T0_SHDW_CFG_DIS_CFGDIS BIT0 = ///< config disable + +#define R_PCH_PSFX_PCR_T1_SHDW_PCIEN 0x3C = ///< PCI configuration space enable bits +#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_FUNDIS BIT8 = ///< Function disable +#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_MEMEN BIT1 = ///< Memory decoding enable +#define B_PCH_PSFX_PCR_T1_SHDW_PCIEN_IOEN BIT0 = ///< IO decoding enable + +#define B_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_DEVICE 0x01F0 = ///< device number +#define N_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_DEVICE 4 +#define B_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_FUNCTION (BIT3 | BIT2 | B= IT1) ///< function number +#define N_PCH_PSFX_PCR_TX_AGENT_FUNCTION_CONFIG_FUNCTION 1 + +#define B_PCH_PSFX_PCR_TARGET_CHANNELID 0xFF +#define B_PCH_PSFX_PCR_TARGET_PORTID 0x7F00 +#define N_PCH_PSFX_PCR_TARGET_PORTID 8 +#define B_PCH_PSFX_PCR_TARGET_PORTGROUPID BIT15 +#define N_PCH_PSFX_PCR_TARGET_PORTGROUPID 15 +#define B_PCH_PSFX_PCR_TARGET_PSFID 0xFF0000 +#define N_PCH_PSFX_PCR_TARGET_PSFID 16 +#define B_PCH_PSFX_PCR_TARGET_CHANMAP BIT31 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sPsfCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs= PsfCnl.h new file mode 100644 index 0000000000..9a5e536f18 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsfCnl= .h @@ -0,0 +1,113 @@ +/** @file + Register definition for PSF component + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PSF_CNL_H_ +#define _PCH_REGS_PSF_CNL_H_ + +//PSF 1 Multicast Message Configuration +#define R_CNL_PCH_LP_PSF1_PCR_PSF_MC_CONTROL_MCAST0_EOI 0x= 404C ///< Multicast Control Register +#define R_CNL_PCH_LP_PSF1_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x= 4064 ///< Destination ID +#define R_CNL_PCH_H_PSF1_PCR_PSF_MC_CONTROL_MCAST0_EOI 0x= 403C ///< Multicast Control Register +#define R_CNL_PCH_H_PSF1_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x= 4054 ///< Destination ID + +// +// PSF3 PCRs (PID:PSF3) +// +// PSF3 PCH-LP Specific Base Address +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI2_REG_BASE 0x0100 = ///< D18F6 PSF base address (SerialIo: SPI2) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_ISH_REG_BASE 0x0200 = ///< D19F0 PSF base address (ISH) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_CNVI_REG_BASE 0x0400 = ///< D20F3 PSF base address (CNVi) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SDCARD_REG_BASE 0x0500 = ///< D20F5 PSF base address (SCC: SDCard) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C0_REG_BASE 0x0600 = ///< D21F0 PSF base address (SerialIo: I2C0) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C1_REG_BASE 0x0700 = ///< D21F1 PSF base address (SerialIo: I2C1) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C2_REG_BASE 0x0800 = ///< D21F2 PSF base address (SerialIo: I2C2) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C3_REG_BASE 0x0900 = ///< D21F3 PSF base address (SerialIo: I2C3) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C4_REG_BASE 0x0A00 = ///< D25F0 PSF base address (SerialIo: I2C4) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C5_REG_BASE 0x0B00 = ///< D25F1 PSF base address (SerialIo: I2C5) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART2_REG_BASE 0x0C00 = ///< D25F2 PSF base address (SerialIo: UART2) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART0_REG_BASE 0x0D00 = ///< D30F0 PSF base address (SerialIo: UART0) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART1_REG_BASE 0x0E00 = ///< D30F1 PSF base address (SerialIo: UART1) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI0_REG_BASE 0x0F00 = ///< D30F2 PSF base address (SerialIo: SPI0) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI1_REG_BASE 0x1000 = ///< D30F3 PSF base address (SerialIo: SPI1) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_LPC_REG_BASE 0x1100 = ///< D31F0 PSF base address (LPC) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_P2SB_REG_BASE 0x1300 = ///< D31F1 PSF base address (P2SB) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_PMC_REG_BASE 0x1400 = ///< D31F2 PSF base address (PMC) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_AUD_REG_BASE 0x1500 = ///< D31F3 PSF base address (HDA, ADSP) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SMBUS_REG_BASE 0x1600 = ///< D31F4 PSF base address (SMBUS) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI_SPI_REG_BASE 0x1700 = ///< D31F5 PSF base address (SPI SPI) +#define R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_GBE_REG_BASE 0x1800 = ///< D31F6 PSF base address (GBE) +// PSF3 PCH-H Specific Base Address +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI2_REG_BASE 0x0100 = ///< D18F6 PSF base address (SerialIo: SPI2) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_ISH_REG_BASE 0x0180 = ///< D19F0 PSF base address (ISH) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_CNVI_REG_BASE 0x0280 = ///< D20F3 PSF base address (CNVi) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SDCARD_REG_BASE 0x0300 = ///< D20F5 PSF base address (SCC: SDCard) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C0_REG_BASE 0x0380 = ///< D21F0 PSF base address (SerialIo: I2C0) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C1_REG_BASE 0x0400 = ///< D21F1 PSF base address (SerialIo: I2C1) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C2_REG_BASE 0x0480 = ///< D21F2 PSF base address (SerialIo: I2C2) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C3_REG_BASE 0x0500 = ///< D21F3 PSF base address (SerialIo: I2C3) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART2_REG_BASE 0x0580 = ///< D25F2 PSF base address (SerialIo: UART2) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART0_REG_BASE 0x0600 = ///< D30F0 PSF base address (SerialIo: UART0) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART1_REG_BASE 0x0680 = ///< D30F1 PSF base address (SerialIo: UART1) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI0_REG_BASE 0x0700 = ///< D30F2 PSF base address (SerialIo: SPI0) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI1_REG_BASE 0x0780 = ///< D30F3 PSF base address (SerialIo: SPI1) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_LPC_REG_BASE 0x0800 = ///< D31F0 PSF base address (LPC) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_P2SB_REG_BASE 0x0900 = ///< D31F1 PSF base address (P2SB) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_PMC_REG_BASE 0x0980 = ///< D31F2 PSF base address (PMC) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_AUD_REG_BASE 0x0A00 = ///< D31F3 PSF base address (HDA, ADSP)H +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SMBUS_REG_BASE 0x0A80 = ///< D31F4 PSF base address (SMBUS) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI_SPI_REG_BASE 0x0B00 = ///< D31F5 PSF base address (SPI SPI) +#define R_CNL_PCH_H_PSF3_PCR_T0_SHDW_GBE_REG_BASE 0x0B80 = ///< D31F6 PSF base address (GBE) + +// Other PSF3 PCRs definition +#define R_CNL_PCH_PSF3_PCR_PSF_MC_CONTROL_MCAST0_EOI 0x4058 = ///< Multicast Control Register // LP&H +#define R_CNL_PCH_PSF3_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4064 = ///< Destination ID // LP&H + +#define R_CNL_PCH_H_PSF6_PCR_PSF_MC_CONTROL_MCAST0_EOI 0x4030= ///< Multicast Control Register +#define R_CNL_PCH_H_PSF6_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4048= ///< Destination ID +#define R_CNL_PCH_H_PSF6_PCR_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x403C= ///< Multicast Control Register +#define R_CNL_PCH_H_PSF6_PCR_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 0x4070= ///< Destination ID + +#define R_CNL_PCH_H_PSF7_PCR_PSF_MC_CONTROL_MCAST0_EOI 0x4030= ///< Multicast Control Register +#define R_CNL_PCH_H_PSF7_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4048= ///< Destination ID +#define R_CNL_PCH_H_PSF7_PCR_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x403C= ///< Multicast Control Register +#define R_CNL_PCH_H_PSF7_PCR_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 0x4070= ///< Destination ID + +#define R_CNL_PCH_H_PSF8_PCR_PSF_MC_CONTROL_MCAST0_EOI 0x4030= ///< Multicast Control Register +#define R_CNL_PCH_H_PSF8_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI 0x4048= ///< Destination ID +#define R_CNL_PCH_H_PSF8_PCR_PSF_MC_CONTROL_MCAST1_RS0_MCTP1 0x403C= ///< Multicast Control Register +#define R_CNL_PCH_H_PSF8_PCR_PSF_MC_AGENT_MCAST1_RS0_TGT0_MCTP1 0x4070= ///< Destination ID +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sPsth.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPs= th.h new file mode 100644 index 0000000000..d6030ed10d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h @@ -0,0 +1,77 @@ +/** @file + Register definition for PSTH component + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_PSTH_H_ +#define _PCH_REGS_PSTH_H_ + +// +// Private chipset register (Memory space) offset definition +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well. +// + +// +// PSTH and IO Trap PCRs (PID:PSTH) +// +#define R_PSTH_PCR_PSTHCTL 0x1D00 ///< PSTH contro= l register +#define B_PSTH_PCR_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF p= rimary trunk clock gating enable +#define B_PSTH_PCR_PSTHIOSFSTCGE BIT1 ///< PSTH IOSF s= ideband trunk clock gating enable +#define B_PSTH_PCR_PSTHDCGE BIT0 ///< PSTH dynami= c clock gating enable +#define R_PSTH_PCR_TRPST 0x1E00 ///< Trap status= register +#define B_PSTH_PCR_TRPST_CTSS 0x0000000F ///< Cycle Trap = SMI# Status mask +#define R_PSTH_PCR_TRPC 0x1E10 ///< Trapped cyc= le +#define B_PSTH_PCR_TRPC_RW BIT24 ///< Read/Write#= : 1=3DRead, 0=3DWrite +#define B_PSTH_PCR_TRPC_AHBE 0x00000000000F0000 ///< Active high= byte enables +#define B_PSTH_PCR_TRPC_IOA 0x000000000000FFFC ///< Trap cycle = I/O address +#define R_PSTH_PCR_TRPD 0x1E18 ///< Trapped wri= te data +#define B_PSTH_PCR_TRPD_IOD 0x00000000FFFFFFFF ///< Trap cycle = I/O data +#define R_PSTH_PCR_TRPREG0 0x1E80 ///< IO Tarp 0 r= egister +#define R_PSTH_PCR_TRPREG1 0x1E88 ///< IO Tarp 1 r= egister +#define R_PSTH_PCR_TRPREG2 0x1E90 ///< IO Tarp 2 r= egister +#define R_PSTH_PCR_TRPREG3 0x1E98 ///< IO Tarp 3 r= egister +#define B_PSTH_PCR_TRPREG_RWM BIT17 ///< 49 - 32 for= 32 bit access, Read/Write mask +#define B_PSTH_PCR_TRPREG_RWIO BIT16 ///< 48 - 32 for= 32 bit access, Read/Write#, 1=3DRead, 0=3DWrite +#define N_PSTH_PCR_TRPREG_RWIO 16 ///< 48 - 32 for= 32 bit access, 16bit shift for Read/Write field +#define N_PSTH_PCR_TRPREG_BEM 36 +#define B_PSTH_PCR_TRPREG_BEM 0x000000F000000000 ///< Byte enable= mask +#define N_PSTH_PCR_TRPREG_BE 32 +#define B_PSTH_PCR_TRPREG_BE 0x0000000F00000000 ///< Byte enable +#define B_PSTH_PCR_TRPREG_AM 0x0000000000FC0000 ///< IO Address = mask +#define B_PSTH_PCR_TRPREG_AD 0x000000000000FFFC ///< IO Address +#define B_PSTH_PCR_TRPREG_TSE BIT0 ///< Trap and SM= I# Enable + + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sSata.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSa= ta.h new file mode 100644 index 0000000000..d98ce39df6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSata.h @@ -0,0 +1,668 @@ +/** @file + Register names for PCH SATA controllers + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SATA_H_ +#define _PCH_REGS_SATA_H_ + +// +// SATA Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SATA 23 +#define PCI_FUNCTION_NUMBER_PCH_SATA 0 + +#define PCI_DEVICE_NUMBER_CDF_PCH_SATA_1 7 +#define PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1 0 + +#define PCI_DEVICE_NUMBER_CDF_PCH_SATA_2 8 +#define PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2 0 + +#define PCI_DEVICE_NUMBER_CDF_PCH_SATA_3 14 +#define PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3 0 + +// +// PCH-LP SATA Device ID's +// +#define V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_AHCI 0x9DD3 ///< SATA C= ontroller (AHCI) - Mobile +#define V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID 0x9DD5 ///< SATA C= ontroller (RAID 0/1/5/10) - NOT premium - Mobile +#define V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID_PREM 0x9DD7 ///< SATA C= ontroller (RAID 0/1/5/10) - premium - Mobile +#define V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID_IBC 0x282A ///< SATA C= ontroller (RAID 0/1/5/10) - In-box compatible - Mobile + +// +// PCH-H SATA Device ID's +// +#define V_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_ALTDIS 0x2822 ///< SATA Contr= oller (RAID 0/1/5/10) - premium - Alternate ID +#define V_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_RSTE 0x2826 ///< SATA Contr= oller (RAID 0/1/5/10) - RSTe of Server SKU + +// +// PCH-H SATA Device ID's +// +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_AHCI 0xA352 ///< SATA Co= ntroller (AHCI) Desktop/Server +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_AHCI 0xA353 ///< SATA Co= ntroller (AHCI) Mobile Halo +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID 0xA354 ///< SATA Co= ntroller (RAID 0/1/5/10) - NOT premium Desktop/Server +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_RAID 0xA355 ///< SATA Co= ntroller (RAID 0/1/5/10) - NOT premium Mobile Halo +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_PREM 0xA356 ///< SATA Co= ntroller (RAID 0/1/5/10) - premium Desktop/Server +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_RAID_PREM 0xA357 ///< SATA Co= ntroller (RAID 0/1/5/10) - premium Mobile Halo +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_OP_AHCI 0xA35E ///< SATA Co= ntroller (AHCI) Optane Caching - Desktop +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC 0x2822 ///< SATA Co= ntroller (RAID 0/1/5/10) - In-box compatible +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC_RST 0x2826 ///< SATA Co= ntroller (RAID 0/1/5/10) - In-box compatible (RSTe) +#define V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC_2 0x282A ///< SATA Co= ntroller (RAID 0/1/5/10) - In-box compatible (Alternate) + + +// +// SATA Controller common Registers +// +#define V_SATA_CFG_SUB_CLASS_CODE_AHCI 0x06 +#define V_SATA_CFG_SUB_CLASS_CODE_RAID 0x04 +#define R_SATA_CFG_AHCI_BAR 0x24 +#define B_SATA_CFG_AHCI_BAR_BA 0xFFFFF800 +#define V_SATA_CFG_AHCI_BAR_LENGTH 0x800 +#define N_SATA_CFG_AHCI_BAR_ALIGNMENT 11 +#define V_SATA_CFG_AHCI_BAR_LENGTH_512K 0x80000 +#define N_SATA_CFG_AHCI_BAR_ALIGNMENT_512K 19 +#define B_SATA_CFG_AHCI_BAR_PF BIT3 +#define B_SATA_CFG_AHCI_BAR_TP (BIT2 | BIT1) +#define B_SATA_CFG_AHCI_BAR_RTE BIT0 +#define R_SATA_CFG_PID 0x70 +#define B_SATA_CFG_PID_NEXT 0xFF00 +#define V_SATA_CFG_PID_NEXT_0 0xB000 +#define V_SATA_CFG_PID_NEXT_1 0xA800 +#define B_SATA_CFG_PID_CID 0x00FF +#define R_SATA_CFG_PC 0x72 +#define S_SATA_CFG_PC 2 +#define B_SATA_CFG_PC_PME (BIT15 | BIT14 | BIT13 | BIT12= | BIT11) +#define V_SATA_CFG_PC_PME_0 0x0000 +#define V_SATA_CFG_PC_PME_1 0x4000 +#define B_SATA_CFG_PC_D2_SUP BIT10 +#define B_SATA_CFG_PC_D1_SUP BIT9 +#define B_SATA_CFG_PC_AUX_CUR (BIT8 | BIT7 | BIT6) +#define B_SATA_CFG_PC_DSI BIT5 +#define B_SATA_CFG_PC_PME_CLK BIT3 +#define B_SATA_CFG_PC_VER (BIT2 | BIT1 | BIT0) +#define R_SATA_CFG_PMCS 0x74 +#define B_SATA_CFG_PMCS_PMES BIT15 +#define B_SATA_CFG_PMCS_PMEE BIT8 +#define B_SATA_CFG_PMCS_NSFRST BIT3 +#define V_SATA_CFG_PMCS_NSFRST_1 0x01 +#define V_SATA_CFG_PMCS_NSFRST_0 0x00 +#define B_SATA_CFG_PMCS_PS (BIT1 | BIT0) +#define V_SATA_CFG_PMCS_PS_3 0x03 +#define V_SATA_CFG_PMCS_PS_0 0x00 +#define R_SATA_CFG_MID 0x80 +#define B_SATA_CFG_MID_NEXT 0xFF00 +#define B_SATA_CFG_MID_CID 0x00FF +#define R_SATA_CFG_MC 0x82 +#define B_SATA_CFG_MC_C64 BIT7 +#define B_SATA_CFG_MC_MME (BIT6 | BIT5 | BIT4) +#define V_SATA_CFG_MC_MME_4 0x04 +#define V_SATA_CFG_MC_MME_2 0x02 +#define V_SATA_CFG_MC_MME_1 0x01 +#define V_SATA_CFG_MC_MME_0 0x00 +#define B_SATA_CFG_MC_MMC (BIT3 | BIT2 | BIT1) +#define V_SATA_CFG_MC_MMC_4 0x04 +#define V_SATA_CFG_MC_MMC_0 0x00 +#define B_SATA_CFG_MC_MSIE BIT0 +#define V_SATA_CFG_MC_MSIE_1 0x01 +#define V_SATA_CFG_MC_MSIE_0 0x00 +#define R_SATA_CFG_MA 0x84 +#define B_SATA_CFG_MA 0xFFFFFFFC +#define R_SATA_CFG_MD 0x88 +#define B_SATA_CFG_MD_MSIMD 0xFFFF + +#define R_SATA_CFG_MAP 0x90 +#define B_SATA_CFG_MAP_PCD 0xFF +#define N_SATA_CFG_MAP_SPD 16 +#define B_SATA_CFG_MAP_SPD7 BIT23 +#define B_SATA_CFG_MAP_SPD6 BIT22 +#define B_SATA_CFG_MAP_SPD5 BIT21 +#define B_SATA_CFG_MAP_SPD4 BIT20 +#define B_SATA_CFG_MAP_SPD3 BIT19 +#define B_SATA_CFG_MAP_SPD2 BIT18 +#define B_SATA_CFG_MAP_SPD1 BIT17 +#define B_SATA_CFG_MAP_SPD0 BIT16 +#define B_SATA_CFG_MAP_PORT7_PCD BIT7 +#define B_SATA_CFG_MAP_PORT6_PCD BIT6 +#define B_SATA_CFG_MAP_PORT5_PCD BIT5 +#define B_SATA_CFG_MAP_PORT4_PCD BIT4 +#define B_SATA_CFG_MAP_PORT3_PCD BIT3 +#define B_SATA_CFG_MAP_PORT2_PCD BIT2 +#define B_SATA_CFG_MAP_PORT1_PCD BIT1 +#define B_SATA_CFG_MAP_PORT0_PCD BIT0 +#define R_SATA_CFG_PCS 0x94 +#define B_SATA_CFG_PCS_P7P BIT23 +#define B_SATA_CFG_PCS_P6P BIT22 +#define B_SATA_CFG_PCS_P5P BIT21 +#define B_SATA_CFG_PCS_P4P BIT20 +#define B_SATA_CFG_PCS_P3P BIT19 +#define B_SATA_CFG_PCS_P2P BIT18 +#define B_SATA_CFG_PCS_P1P BIT17 +#define B_SATA_CFG_PCS_P0P BIT16 +#define B_SATA_CFG_PCS_P7E BIT7 +#define B_SATA_CFG_PCS_P6E BIT6 +#define B_SATA_CFG_PCS_P5E BIT5 +#define B_SATA_CFG_PCS_P4E BIT4 +#define B_SATA_CFG_PCS_P3E BIT3 +#define B_SATA_CFG_PCS_P2E BIT2 +#define B_SATA_CFG_PCS_P1E BIT1 +#define B_SATA_CFG_PCS_P0E BIT0 +#define R_SATA_CFG_SATAGC 0x9C +#define B_SATA_CFG_SATAGC_SMS_MASK BIT16 +#define N_SATA_CFG_SATAGC_SMS_MASK 16 +#define V_SATA_CFG_SATAGC_SMS_AHCI 0x0 +#define V_SATA_CFG_SATAGC_SMS_RAID 0x1 +#define B_SATA_CFG_SATAGC_AIE BIT7 +#define B_SATA_CFG_SATAGC_AIES BIT6 +#define B_SATA_CFG_SATAGC_MSS (BIT4 | BIT3) +#define V_SATA_CFG_SATAGC_MSS_8K 0x2 +#define N_SATA_CFG_SATAGC_MSS 3 +#define B_SATA_CFG_SATAGC_ASSEL (BIT2 | BIT1 | BIT0) + +#define V_SATA_CFG_SATAGC_ASSEL_2K 0x0 +#define V_SATA_CFG_SATAGC_ASSEL_16K 0x1 +#define V_SATA_CFG_SATAGC_ASSEL_32K 0x2 +#define V_SATA_CFG_SATAGC_ASSEL_64K 0x3 +#define V_SATA_CFG_SATAGC_ASSEL_128K 0x4 +#define V_SATA_CFG_SATAGC_ASSEL_256K 0x5 +#define V_SATA_CFG_SATAGC_ASSEL_512K 0x6 + +#define R_SATA_CFG_SIRI 0xA0 +#define R_SATA_CFG_STRD 0xA4 +#define R_SATA_CFG_SIR_0C 0x0C +#define R_SATA_CFG_SIR_50 0x50 +#define R_SATA_CFG_SIR_54 0x54 +#define R_SATA_CFG_SIR_58 0x58 +#define R_SATA_CFG_SIR_5C 0x5C +#define R_SATA_CFG_SIR_60 0x60 +#define R_SATA_CFG_SIR_64 0x64 +#define R_SATA_CFG_SIR_68 0x68 +#define R_SATA_CFG_SIR_6C 0x6C +#define R_SATA_CFG_SIR_70 0x70 +#define R_SATA_CFG_SIR_80 0x80 +#define R_SATA_CFG_SIR_84 0x84 +#define R_SATA_CFG_SIR_8C 0x8C +#define R_SATA_CFG_SIR_90 0x90 +#define R_SATA_CFG_SIR_98 0x98 +#define R_SATA_CFG_SIR_9C 0x9C +#define R_SATA_CFG_SIR_A0 0xA0 +#define R_SATA_CFG_SIR_A4 0xA4 +#define R_SATA_CFG_SIR_A8 0xA8 +#define R_SATA_CFG_SIR_C8 0xC8 +#define R_SATA_CFG_SIR_CC 0xCC +#define R_SATA_CFG_SIR_D0 0xD0 +#define R_SATA_CFG_SIR_D4 0xD4 +#define B_SATA_CFG_STRD_DTA 0xFFFFFFFF +#define R_SATA_CFG_CR0 0xA8 +#define B_SATA_CFG_CR0_MAJREV 0x00F00000 +#define B_SATA_CFG_CR0_MINREV 0x000F0000 +#define B_SATA_CFG_CR0_NEXT 0x0000FF00 +#define B_SATA_CFG_CR0_CAP 0x000000FF +#define R_SATA_CFG_CR1 0xAC +#define B_SATA_CFG_CR1_BAROFST 0xFFF0 +#define B_SATA_CFG_CR1_BARLOC 0x000F +#define R_SATA_CFG_FLR_CID 0xB0 +#define B_SATA_CFG_FLR_CID_NEXT 0xFF00 +#define B_SATA_CFG_FLR_CID 0x00FF +#define V_SATA_CFG_FLR_CID_1 0x0009 +#define V_SATA_CFG_FLR_CID_0 0x0013 +#define R_SATA_CFG_FLR_CLV 0xB2 +#define B_SATA_CFG_FLR_CLV_FLRC_FLRCSSEL_0 BIT9 +#define B_SATA_CFG_FLR_CLV_TXPC_FLRCSSEL_0 BIT8 +#define B_SATA_CFG_FLR_CLV_VSCID_FLRCSSEL_0 0x00FF +#define B_SATA_CFG_FLR_CLV_VSCID_FLRCSSEL_1 0x00FF +#define V_SATA_CFG_FLR_CLV_VSCID_FLRCSSEL 0x0006 +#define R_SATA_CFG_FLRC 0xB4 +#define B_SATA_CFG_FLRC_TXP BIT8 +#define B_SATA_CFG_FLRC_INITFLR BIT0 +#define R_SATA_CFG_SP 0xC0 +#define B_SATA_CFG_SP 0xFFFFFFFF +#define R_SATA_CFG_MXID 0xD0 +#define N_SATA_CFG_MXID_NEXT 8 + +#define R_SATA_CFG_BFCS 0xE0 +#define B_SATA_CFG_BFCS_P7BFI BIT17 +#define B_SATA_CFG_BFCS_P6BFI BIT16 +#define B_SATA_CFG_BFCS_P5BFI BIT15 +#define B_SATA_CFG_BFCS_P4BFI BIT14 +#define B_SATA_CFG_BFCS_P3BFI BIT13 +#define B_SATA_CFG_BFCS_P2BFI BIT12 +#define B_SATA_CFG_BFCS_P2BFS BIT11 +#define B_SATA_CFG_BFCS_P2BFF BIT10 +#define B_SATA_CFG_BFCS_P1BFI BIT9 +#define B_SATA_CFG_BFCS_P0BFI BIT8 +#define B_SATA_CFG_BFCS_BIST_FIS_T BIT7 +#define B_SATA_CFG_BFCS_BIST_FIS_A BIT6 +#define B_SATA_CFG_BFCS_BIST_FIS_S BIT5 +#define B_SATA_CFG_BFCS_BIST_FIS_L BIT4 +#define B_SATA_CFG_BFCS_BIST_FIS_F BIT3 +#define B_SATA_CFG_BFCS_BIST_FIS_P BIT2 +#define R_SATA_CFG_BFTD1 0xE4 +#define B_SATA_CFG_BFTD1 0xFFFFFFFF +#define R_SATA_CFG_BFTD2 0xE8 +#define B_SATA_CFG_BFTD2 0xFFFFFFFF + +#define R_SATA_CFG_VS_CAP 0xA4 +#define B_SATA_CFG_VS_CAP_NRMBE BIT0 = ///< NVM Remap Memory BAR Enable +#define B_SATA_CFG_VS_CAP_MSL 0x1FFE = ///< Memory Space Limit +#define N_SATA_CFG_VS_CAP_MSL 1 +#define V_SATA_CFG_VS_CAP_MSL 0x1EF = ///< Memory Space Limit Field Value +#define B_SATA_CFG_VS_CAP_NRMO 0xFFF0000 = ///< NVM Remapped Memory Offset +#define N_SATA_CFG_VS_CAP_NRMO 16 +#define V_SATA_CFG_VS_CAP_NRMO 0x10 = ///< NVM Remapped Memory Offset Field Value + +// +// RST PCIe Storage Remapping Registers +// +#define R_SATA_CFG_RST_PCIE_STORAGE_RCR 0x800 = ///< Remap Capability Register +#define B_SATA_CFG_RST_PCIE_STORAGE_RCR_NRS (BIT2|BIT1|BIT0) = ///< Number of Remapping Supported +#define B_SATA_CFG_RST_PCIE_STORAGE_RCR_NRS_CR1 BIT0 = ///< Number of Remapping Supported (RST PCIe Storage Cycle Ro= uter #1) +#define R_SATA_CFG_RST_PCIE_STORAGE_SPR 0x80C = ///< Scratch Pad Register +#define R_SATA_CFG_RST_PCIE_STORAGE_CR1_DCC 0x880 = ///< CR#1 Device Class Code +#define N_SATA_CFG_RST_PCIE_STORAGE_CR1_DCC_SCC 8 +#define N_SATA_CFG_RST_PCIE_STORAGE_CR1_DCC_BCC 16 +#define B_SATA_CFG_RST_PCIE_STORAGE_CR1_DCC_DT BIT31 = ///< Device Type +#define V_SATA_CFG_RST_PCIE_STORAGE_REMAP_CONFIG_CR 0x80 = ///< Remapped Configuration for RST PCIe Storage Cycle Router= #n +#define V_SATA_CFG_RST_PCIE_STORAGE_REMAP_RP_OFFSET 0x100 = ///< Remapped Root Port Offset Value +#define R_SATA_CFG_RST_PCIE_STORAGE_CCFG 0x1D0 = ///< Port Configuration Register +// +// AHCI BAR Area related Registers +// +#define R_SATA_MEM_AHCI_CAP 0x0 +#define B_SATA_MEM_AHCI_CAP_S64A BIT31 +#define B_SATA_MEM_AHCI_CAP_SCQA BIT30 +#define B_SATA_MEM_AHCI_CAP_SSNTF BIT29 +#define B_SATA_MEM_AHCI_CAP_SMPS BIT28 ///< Supports Interlock = Switch +#define B_SATA_MEM_AHCI_CAP_SSS BIT27 ///< Supports Stagger Sp= in-up +#define B_SATA_MEM_AHCI_CAP_SALP BIT26 +#define B_SATA_MEM_AHCI_CAP_SAL BIT25 +#define B_SATA_MEM_AHCI_CAP_SCLO BIT24 ///< Supports Command Li= st Override +#define B_SATA_MEM_AHCI_CAP_ISS_MASK (BIT23 | BIT22 | BIT21 | BIT20) +#define N_SATA_MEM_AHCI_CAP_ISS 20 ///< Interface Speed Sup= port +#define V_SATA_MEM_AHCI_CAP_ISS_1_5_G 0x01 +#define V_SATA_MEM_AHCI_CAP_ISS_3_0_G 0x02 +#define V_SATA_MEM_AHCI_CAP_ISS_6_0_G 0x03 +#define B_SATA_MEM_AHCI_CAP_SNZO BIT19 +#define B_SATA_MEM_AHCI_CAP_SAM BIT18 +#define B_SATA_MEM_AHCI_CAP_SPM BIT17 ///< Supports Port Multi= plier +#define B_SATA_MEM_AHCI_CAP_PMD BIT15 ///< PIO Multiple DRQ Bl= ock +#define B_SATA_MEM_AHCI_CAP_SSC BIT14 +#define B_SATA_MEM_AHCI_CAP_PSC BIT13 +#define B_SATA_MEM_AHCI_CAP_NCS 0x1F00 +#define B_SATA_MEM_AHCI_CAP_CCCS BIT7 +#define B_SATA_MEM_AHCI_CAP_EMS BIT6 +#define B_SATA_MEM_AHCI_CAP_SXS BIT5 ///< External SATA is su= pported +#define B_SATA_MEM_AHCI_CAP_NPS 0x001F + +#define R_SATA_MEM_AHCI_GHC 0x04 +#define B_SATA_MEM_AHCI_GHC_AE BIT31 +#define B_SATA_MEM_AHCI_GHC_MRSM BIT2 +#define B_SATA_MEM_AHCI_GHC_IE BIT1 +#define B_SATA_MEM_AHCI_GHC_HR BIT0 + +#define R_SATA_MEM_AHCI_IS 0x08 +#define B_SATA_MEM_AHCI_IS_PORT7 BIT7 +#define B_SATA_MEM_AHCI_IS_PORT6 BIT6 +#define B_SATA_MEM_AHCI_IS_PORT5 BIT5 +#define B_SATA_MEM_AHCI_IS_PORT4 BIT4 +#define B_SATA_MEM_AHCI_IS_PORT3 BIT3 +#define B_SATA_MEM_AHCI_IS_PORT2 BIT2 +#define B_SATA_MEM_AHCI_IS_PORT1 BIT1 +#define B_SATA_MEM_AHCI_IS_PORT0 BIT0 +#define R_SATA_MEM_AHCI_PI 0x0C +#define B_SATA_MEM_AHCI_PI_PORT_MASK 0xFF +#define B_SATA_MEM_PORT7_IMPLEMENTED BIT7 +#define B_SATA_MEM_PORT6_IMPLEMENTED BIT6 +#define B_SATA_MEM_PORT5_IMPLEMENTED BIT5 +#define B_SATA_MEM_PORT4_IMPLEMENTED BIT4 +#define B_SATA_MEM_PORT3_IMPLEMENTED BIT3 +#define B_SATA_MEM_PORT2_IMPLEMENTED BIT2 +#define B_SATA_MEM_PORT1_IMPLEMENTED BIT1 +#define B_SATA_MEM_PORT0_IMPLEMENTED BIT0 +#define R_SATA_MEM_AHCI_VS 0x10 +#define B_SATA_MEM_AHCI_VS_MJR 0xFFFF0000 +#define B_SATA_MEM_AHCI_VS_MNR 0x0000FFFF +#define R_SATA_MEM_AHCI_EM_LOC 0x1C +#define B_SATA_MEM_AHCI_EM_LOC_OFST 0xFFFF0000 +#define B_SATA_MEM_AHCI_EM_LOC_SZ 0x0000FFFF +#define R_SATA_MEM_AHCI_EM_CTRL 0x20 +#define B_SATA_MEM_AHCI_EM_CTRL_ATTR_ALHD BIT26 +#define B_SATA_MEM_AHCI_EM_CTRL_ATTR_XMT BIT25 +#define B_SATA_MEM_AHCI_EM_CTRL_ATTR_SMB BIT24 +#define B_SATA_MEM_AHCI_EM_CTRL_SUPP_SGPIO BIT19 +#define B_SATA_MEM_AHCI_EM_CTRL_SUPP_SES2 BIT18 +#define B_SATA_MEM_AHCI_EM_CTRL_SUPP_SAFTE BIT17 +#define B_SATA_MEM_AHCI_EM_CTRL_SUPP_LED BIT16 +#define B_SATA_MEM_AHCI_EM_CTRL_RST BIT9 +#define B_SATA_MEM_AHCI_EM_CTRL_CTL_TM BIT8 +#define B_SATA_MEM_AHCI_EM_CTRL_STS_MR BIT0 +#define R_SATA_MEM_AHCI_CAP2 0x24 +#define B_SATA_MEM_AHCI_CAP2_DESO BIT5 +#define B_SATA_MEM_AHCI_CAP2_SADM BIT4 +#define B_SATA_MEM_AHCI_CAP2_SDS BIT3 +#define B_SATA_MEM_AHCI_CAP2_APST BIT2 ///< Automatic Partial t= o Slumber Transitions +#define R_SATA_MEM_AHCI_VSP 0xA0 +#define B_SATA_MEM_AHCI_VSP_SLPD BIT0 +#define R_SATA_MEM_AHCI_SFM 0xC8 ///< RST Feature Capabil= ities +#define B_SATA_MEM_AHCI_SFM_LEGACY BIT12 +#define B_SATA_MEM_AHCI_SFM_OUD (BIT11 | BIT10) +#define N_SATA_MEM_AHCI_SFM_OUD 10 +#define B_SATA_MEM_AHCI_SFM_SEREQ BIT9 +#define B_SATA_MEM_AHCI_SFM_IROES BIT8 +#define B_SATA_MEM_AHCI_SFM_LEDL BIT7 +#define B_SATA_MEM_AHCI_SFM_HDDLK BIT6 +#define B_SATA_MEM_AHCI_SFM_IRSTOROM BIT5 +#define B_SATA_MEM_AHCI_SFM_RSTE BIT4 +#define B_SATA_MEM_AHCI_SFM_R5E BIT3 +#define B_SATA_MEM_AHCI_SFM_R10E BIT2 +#define B_SATA_MEM_AHCI_SFM_R1E BIT1 +#define B_SATA_MEM_AHCI_SFM_R0E BIT0 +#define B_SATA_MEM_AHCI_SFM_LOWBYTES 0x1FF +#define R_SATA_MEM_AHCI_P0CLB 0x100 +#define R_SATA_MEM_AHCI_P1CLB 0x180 +#define R_SATA_MEM_AHCI_P2CLB 0x200 +#define R_SATA_MEM_AHCI_P3CLB 0x280 +#define R_SATA_MEM_AHCI_P4CLB 0x300 +#define R_SATA_MEM_AHCI_P5CLB 0x380 +#define R_SATA_MEM_AHCI_P6CLB 0x400 +#define R_SATA_MEM_AHCI_P7CLB 0x480 +#define B_SATA_MEM_AHCI_PXCLB 0xFFFFFC00 +#define R_SATA_MEM_AHCI_P0CLBU 0x104 +#define R_SATA_MEM_AHCI_P1CLBU 0x184 +#define R_SATA_MEM_AHCI_P2CLBU 0x204 +#define R_SATA_MEM_AHCI_P3CLBU 0x284 +#define R_SATA_MEM_AHCI_P4CLBU 0x304 +#define R_SATA_MEM_AHCI_P5CLBU 0x384 +#define R_SATA_MEM_AHCI_P6CLBU 0x404 +#define R_SATA_MEM_AHCI_P7CLBU 0x484 +#define B_SATA_MEM_AHCI_PXCLBU 0xFFFFFFFF +#define R_SATA_MEM_AHCI_P0FB 0x108 +#define R_SATA_MEM_AHCI_P1FB 0x188 +#define R_SATA_MEM_AHCI_P2FB 0x208 +#define R_SATA_MEM_AHCI_P3FB 0x288 +#define R_SATA_MEM_AHCI_P4FB 0x308 +#define R_SATA_MEM_AHCI_P5FB 0x388 +#define R_SATA_MEM_AHCI_P6FB 0x408 +#define R_SATA_MEM_AHCI_P7FB 0x488 +#define B_SATA_MEM_AHCI_PXFB 0xFFFFFF00 +#define R_SATA_MEM_AHCI_P0FBU 0x10C +#define R_SATA_MEM_AHCI_P1FBU 0x18C +#define R_SATA_MEM_AHCI_P2FBU 0x20C +#define R_SATA_MEM_AHCI_P3FBU 0x28C +#define R_SATA_MEM_AHCI_P4FBU 0x30C +#define R_SATA_MEM_AHCI_P5FBU 0x38C +#define R_SATA_MEM_AHCI_P6FBU 0x40C +#define R_SATA_MEM_AHCI_P7FBU 0x48C +#define B_SATA_MEM_AHCI_PXFBU 0xFFFFFFFF +#define R_SATA_MEM_AHCI_P0IS 0x110 +#define R_SATA_MEM_AHCI_P1IS 0x190 +#define R_SATA_MEM_AHCI_P2IS 0x210 +#define R_SATA_MEM_AHCI_P3IS 0x290 +#define R_SATA_MEM_AHCI_P4IS 0x310 +#define R_SATA_MEM_AHCI_P5IS 0x390 +#define R_SATA_MEM_AHCI_P6IS 0x410 +#define R_SATA_MEM_AHCI_P7IS 0x490 +#define B_SATA_MEM_AHCI_PXIS_CPDS BIT31 +#define B_SATA_MEM_AHCI_PXIS_TFES BIT30 +#define B_SATA_MEM_AHCI_PXIS_HBFS BIT29 +#define B_SATA_MEM_AHCI_PXIS_HBDS BIT28 +#define B_SATA_MEM_AHCI_PXIS_IFS BIT27 +#define B_SATA_MEM_AHCI_PXIS_INFS BIT26 +#define B_SATA_MEM_AHCI_PXIS_OFS BIT24 +#define B_SATA_MEM_AHCI_PXIS_IPMS BIT23 +#define B_SATA_MEM_AHCI_PXIS_PRCS BIT22 +#define B_SATA_MEM_AHCI_PXIS_DIS BIT7 +#define B_SATA_MEM_AHCI_PXIS_PCS BIT6 +#define B_SATA_MEM_AHCI_PXIS_DPS BIT5 +#define B_SATA_MEM_AHCI_PXIS_UFS BIT4 +#define B_SATA_MEM_AHCI_PXIS_SDBS BIT3 +#define B_SATA_MEM_AHCI_PXIS_DSS BIT2 +#define B_SATA_MEM_AHCI_PXIS_PSS BIT1 +#define B_SATA_MEM_AHCI_PXIS_DHRS BIT0 +#define R_SATA_MEM_AHCI_P0IE 0x114 +#define R_SATA_MEM_AHCI_P1IE 0x194 +#define R_SATA_MEM_AHCI_P2IE 0x214 +#define R_SATA_MEM_AHCI_P3IE 0x294 +#define R_SATA_MEM_AHCI_P4IE 0x314 +#define R_SATA_MEM_AHCI_P5IE 0x394 +#define R_SATA_MEM_AHCI_P6IE 0x414 +#define R_SATA_MEM_AHCI_P7IE 0x494 +#define B_SATA_MEM_AHCI_PXIE_CPDE BIT31 +#define B_SATA_MEM_AHCI_PXIE_TFEE BIT30 +#define B_SATA_MEM_AHCI_PXIE_HBFE BIT29 +#define B_SATA_MEM_AHCI_PXIE_HBDE BIT28 +#define B_SATA_MEM_AHCI_PXIE_IFE BIT27 +#define B_SATA_MEM_AHCI_PXIE_INFE BIT26 +#define B_SATA_MEM_AHCI_PXIE_OFE BIT24 +#define B_SATA_MEM_AHCI_PXIE_IPME BIT23 +#define B_SATA_MEM_AHCI_PXIE_PRCE BIT22 +#define B_SATA_MEM_AHCI_PXIE_DIE BIT7 +#define B_SATA_MEM_AHCI_PXIE_PCE BIT6 +#define B_SATA_MEM_AHCI_PXIE_DPE BIT5 +#define B_SATA_MEM_AHCI_PXIE_UFIE BIT4 +#define B_SATA_MEM_AHCI_PXIE_SDBE BIT3 +#define B_SATA_MEM_AHCI_PXIE_DSE BIT2 +#define B_SATA_MEM_AHCI_PXIE_PSE BIT1 +#define B_SATA_MEM_AHCI_PXIE_DHRE BIT0 +#define R_SATA_MEM_AHCI_P0CMD 0x118 +#define R_SATA_MEM_AHCI_P1CMD 0x198 +#define R_SATA_MEM_AHCI_P2CMD 0x218 +#define R_SATA_MEM_AHCI_P3CMD 0x298 +#define R_SATA_MEM_AHCI_P4CMD 0x318 +#define R_SATA_MEM_AHCI_P5CMD 0x398 +#define R_SATA_MEM_AHCI_P6CMD 0x418 +#define R_SATA_MEM_AHCI_P7CMD 0x498 +#define B_SATA_MEM_AHCI_PxCMD_ESP BIT21 ///< Used with an extern= al SATA device +#define B_SATA_MEM_AHCI_PxCMD_MPSP BIT19 ///< Mechanical Switch A= ttached to Port +#define B_SATA_MEM_AHCI_PxCMD_HPCP BIT18 ///< Hotplug capable +#define B_SATA_MEM_AHCI_PxCMD_CR BIT15 +#define B_SATA_MEM_AHCI_PxCMD_FR BIT14 +#define B_SATA_MEM_AHCI_PxCMD_ISS BIT13 +#define B_SATA_MEM_AHCI_PxCMD_CCS 0x00001F00 +#define B_SATA_MEM_AHCI_PxCMD_FRE BIT4 +#define B_SATA_MEM_AHCI_PxCMD_CLO BIT3 +#define B_SATA_MEM_AHCI_PxCMD_POD BIT2 +#define B_SATA_MEM_AHCI_PxCMD_SUD BIT1 +#define B_SATA_MEM_AHCI_PxCMD_ST BIT0 +#define R_SATA_MEM_AHCI_P0TFD 0x120 +#define R_SATA_MEM_AHCI_P1TFD 0x1A0 +#define R_SATA_MEM_AHCI_P2TFD 0x220 +#define R_SATA_MEM_AHCI_P3TFD 0x2A0 +#define R_SATA_MEM_AHCI_P4TFD 0x320 +#define R_SATA_MEM_AHCI_P5TFD 0x3A0 +#define R_SATA_MEM_AHCI_P6TFD 0x420 +#define B_SATA_MEM_AHCI_PXTFD_ERR 0x0000FF00 +#define B_SATA_MEM_AHCI_PXTFD_STS 0x000000FF +#define R_SATA_MEM_AHCI_P0SIG 0x124 +#define R_SATA_MEM_AHCI_P1SIG 0x1A4 +#define R_SATA_MEM_AHCI_P2SIG 0x224 +#define R_SATA_MEM_AHCI_P3SIG 0x2A4 +#define R_SATA_MEM_AHCI_P4SIG 0x324 +#define R_SATA_MEM_AHCI_P5SIG 0x3A4 +#define R_SATA_MEM_AHCI_P6SIG 0x424 +#define B_SATA_MEM_AHCI_PXSIG_LBA_HR 0xFF000000 +#define B_SATA_MEM_AHCI_PXSIG_LBA_MR 0x00FF0000 +#define B_SATA_MEM_AHCI_PXSIG_LBA_LR 0x0000FF00 +#define B_SATA_MEM_AHCI_PXSIG_SCR 0x000000FF +#define R_SATA_MEM_AHCI_P0SSTS 0x128 +#define R_SATA_MEM_AHCI_P1SSTS 0x1A8 +#define R_SATA_MEM_AHCI_P2SSTS 0x228 +#define R_SATA_MEM_AHCI_P3SSTS 0x2A8 +#define R_SATA_MEM_AHCI_P4SSTS 0x328 +#define R_SATA_MEM_AHCI_P5SSTS 0x3A8 +#define R_SATA_MEM_AHCI_P6SSTS 0x428 +#define B_SATA_MEM_AHCI_PXSSTS_IPM_0 0x00000000 +#define B_SATA_MEM_AHCI_PXSSTS_IPM_1 0x00000100 +#define B_SATA_MEM_AHCI_PXSSTS_IPM_2 0x00000200 +#define B_SATA_MEM_AHCI_PXSSTS_IPM_6 0x00000600 +#define B_SATA_MEM_AHCI_PXSSTS_SPD_0 0x00000000 +#define B_SATA_MEM_AHCI_PXSSTS_SPD_1 0x00000010 +#define B_SATA_MEM_AHCI_PXSSTS_SPD_2 0x00000020 +#define B_SATA_MEM_AHCI_PXSSTS_SPD_3 0x00000030 +#define B_SATA_MEM_AHCI_PXSSTS_DET_0 0x00000000 +#define B_SATA_MEM_AHCI_PXSSTS_DET_1 0x00000001 +#define B_SATA_MEM_AHCI_PXSSTS_DET_3 0x00000003 +#define B_SATA_MEM_AHCI_PXSSTS_DET_4 0x00000004 +#define R_SATA_MEM_AHCI_P0SCTL 0x12C +#define R_SATA_MEM_AHCI_P1SCTL 0x1AC +#define R_SATA_MEM_AHCI_P2SCTL 0x22C +#define R_SATA_MEM_AHCI_P3SCTL 0x2AC +#define R_SATA_MEM_AHCI_P4SCTL 0x32C +#define R_SATA_MEM_AHCI_P5SCTL 0x3AC +#define R_SATA_MEM_AHCI_P6SCTL 0x42C +#define B_SATA_MEM_AHCI_PXSCTL_IPM 0x00000F00 +#define V_SATA_MEM_AHCI_PXSCTL_IPM_0 0x00000000 +#define V_SATA_MEM_AHCI_PXSCTL_IPM_1 0x00000100 +#define V_SATA_MEM_AHCI_PXSCTL_IPM_2 0x00000200 +#define V_SATA_MEM_AHCI_PXSCTL_IPM_3 0x00000300 +#define B_SATA_MEM_AHCI_PXSCTL_SPD 0x000000F0 +#define V_SATA_MEM_AHCI_PXSCTL_SPD_0 0x00000000 +#define V_SATA_MEM_AHCI_PXSCTL_SPD_1 0x00000010 +#define V_SATA_MEM_AHCI_PXSCTL_SPD_2 0x00000020 +#define V_SATA_MEM_AHCI_PXSCTL_SPD_3 0x00000030 +#define B_SATA_MEM_AHCI_PXSCTL_DET 0x0000000F +#define V_SATA_MEM_AHCI_PXSCTL_DET_0 0x00000000 +#define V_SATA_MEM_AHCI_PXSCTL_DET_1 0x00000001 +#define V_SATA_MEM_AHCI_PXSCTL_DET_4 0x00000004 +#define R_SATA_MEM_AHCI_P0SERR 0x130 +#define R_SATA_MEM_AHCI_P1SERR 0x1B0 +#define R_SATA_MEM_AHCI_P2SERR 0x230 +#define R_SATA_MEM_AHCI_P3SERR 0x2B0 +#define R_SATA_MEM_AHCI_P4SERR 0x330 +#define R_SATA_MEM_AHCI_P5SERR 0x3B0 +#define R_SATA_MEM_AHCI_P6SERR 0x430 +#define B_SATA_MEM_AHCI_PXSERR_EXCHG BIT26 +#define B_SATA_MEM_AHCI_PXSERR_UN_FIS_TYPE BIT25 +#define B_SATA_MEM_AHCI_PXSERR_TRSTE_24 BIT24 +#define B_SATA_MEM_AHCI_PXSERR_TRSTE_23 BIT23 +#define B_SATA_MEM_AHCI_PXSERR_HANDSHAKE BIT22 +#define B_SATA_MEM_AHCI_PXSERR_CRC_ERROR BIT21 +#define B_SATA_MEM_AHCI_PXSERR_10B8B_DECERR BIT19 +#define B_SATA_MEM_AHCI_PXSERR_COMM_WAKE BIT18 +#define B_SATA_MEM_AHCI_PXSERR_PHY_ERROR BIT17 +#define B_SATA_MEM_AHCI_PXSERR_PHY_RDY_CHG BIT16 +#define B_SATA_MEM_AHCI_PXSERR_INTRNAL_ERR BIT11 +#define B_SATA_MEM_AHCI_PXSERR_PROTOCOL_ERR BIT10 +#define B_SATA_MEM_AHCI_PXSERR_PCDIE BIT9 +#define B_SATA_MEM_AHCI_PXSERR_TDIE BIT8 +#define B_SATA_MEM_AHCI_PXSERR_RCE BIT1 +#define B_SATA_MEM_AHCI_PXSERR_RDIE BIT0 +#define R_SATA_MEM_AHCI_P0SACT 0x134 +#define R_SATA_MEM_AHCI_P1SACT 0x1B4 +#define R_SATA_MEM_AHCI_P2SACT 0x234 +#define R_SATA_MEM_AHCI_P3SACT 0x2B4 +#define R_SATA_MEM_AHCI_P4SACT 0x334 +#define R_SATA_MEM_AHCI_P5SACT 0x3B4 +#define R_SATA_MEM_AHCI_P6SACT 0x434 +#define B_SATA_MEM_AHCI_PXSACT_DS 0xFFFFFFFF +#define R_SATA_MEM_AHCI_P0CI 0x138 +#define R_SATA_MEM_AHCI_P1CI 0x1B8 +#define R_SATA_MEM_AHCI_P2CI 0x238 +#define R_SATA_MEM_AHCI_P3CI 0x2B8 +#define R_SATA_MEM_AHCI_P4CI 0x338 +#define R_SATA_MEM_AHCI_P5CI 0x3B8 +#define R_SATA_MEM_AHCI_P6CI 0x438 +#define B_SATA_MEM_AHCI_PXCI 0xFFFFFFFF + +// +// SATA AHCI Device ID macros +// +#define IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_AHCI) || \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_AHCI) || \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_OP_AHCI) \ + ) + +#define IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_AHCI) \ + ) + +#define IS_PCH_SATA_AHCI_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) \ + ) + +// +// SATA RAID Device ID macros +// +#define IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID) || \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_RAID) || \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_PREM) || \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_MH_RAID_PREM) || \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC) || \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC_RST) || \ + (DeviceId =3D=3D V_CNL_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_IBC_2) || \ + (DeviceId =3D=3D V_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_ALTDIS) || \ + (DeviceId =3D=3D V_PCH_H_SATA_CFG_DEVICE_ID_D_RAID_RSTE) \ + ) + +#define IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + (DeviceId =3D=3D V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID) || \ + (DeviceId =3D=3D V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID_PREM) || \ + (DeviceId =3D=3D V_CNL_PCH_LP_SATA_CFG_DEVICE_ID_M_RAID_IBC) \ + ) + +#define IS_PCH_SATA_RAID_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ) + +// +// Combined SATA IDE/AHCI/RAID Device ID macros +// +#define IS_PCH_H_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_AHCI_DEVICE_ID(DeviceId) || \ + IS_PCH_H_SATA_RAID_DEVICE_ID(DeviceId) \ + ) + +#define IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_LP_SATA_AHCI_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SATA_RAID_DEVICE_ID(DeviceId) \ + ) +#define IS_PCH_SATA_DEVICE_ID(DeviceId) \ + ( \ + IS_PCH_H_SATA_DEVICE_ID(DeviceId) || \ + IS_PCH_LP_SATA_DEVICE_ID(DeviceId) \ + ) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sScs.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScs= .h new file mode 100644 index 0000000000..00e7881408 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScs.h @@ -0,0 +1,52 @@ +/** @file + Register names for PCH Storage and Communication Subsystem + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SCS_H_ +#define _PCH_REGS_SCS_H_ + +// +// SCS Devices proprietary PCI Config Space Registers +// +#define R_SCS_CFG_PCS 0x84 //= /< PME Control Status +#define B_SCS_CFG_PCS_PMESTS BIT15 //= /< PME Status +#define B_SCS_CFG_PCS_PMEEN BIT8 //= /< PME Enable +#define B_SCS_CFG_PCS_NSS BIT3 //= /< No Soft Reset +#define B_SCS_CFG_PCS_PS (BIT1 | BIT0) //= /< Power State +#define B_SCS_CFG_PCS_PS_D3HOT (BIT1 | BIT0) //= /< Power State: D3Hot State +#define R_SCS_CFG_PG_CONFIG 0xA2 //= /< PG Config + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sScsCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegs= ScsCnl.h new file mode 100644 index 0000000000..c18e1ef38c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsScsCnl= .h @@ -0,0 +1,48 @@ +/** @file + Project specific SCS register definitions. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SCS_CNL_H_ +#define _PCH_REGS_SCS_CNL_H_ + +// +// SCS SDCARD Controller PCI config +// +#define PCI_DEVICE_NUMBER_PCH_CNL_SCS_SDCARD 20 +#define PCI_FUNCTION_NUMBER_PCH_CNL_SCS_SDCARD 5 + +#endif + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sSerialIo.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRe= gsSerialIo.h new file mode 100644 index 0000000000..449335b073 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerial= Io.h @@ -0,0 +1,232 @@ +/** @file + Register names for PCH Serial IO Controllers + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SERIAL_IO_ +#define _PCH_REGS_SERIAL_IO_ + +// +// Serial IO Controllers General PCI Configuration Registers +// registers accessed using PciD21FxRegBase + offset +// +#define R_SERIAL_IO_CFG_BAR0_LOW 0x10 +#define B_SERIAL_IO_CFG_BAR0_LOW_BAR 0xFFFFF000 +#define R_SERIAL_IO_CFG_BAR0_HIGH 0x14 +#define R_SERIAL_IO_CFG_BAR1_LOW 0x18 +#define B_SERIAL_IO_CFG_BAR1_LOW_BAR 0xFFFFF000 +#define R_SERIAL_IO_CFG_BAR1_HIGH 0x1C +#define V_SERIAL_IO_CFG_BAR_SIZE (4 * 1024) +#define N_SERIAL_IO_CFG_BAR_ALIGNMENT 12 + +#define R_SERIAL_IO_CFG_PME_CTRL_STS 0x84 +#define B_SERIAL_IO_CFG_PME_CTRL_STS_PWR_ST (BIT1| BIT0) + +#define R_SERIAL_IO_CFG_D0I3MAXDEVPG 0xA0 +#define B_SERIAL_IO_CFG_D0I3MAXDEVPG_PMCRE BIT16 +#define B_SERIAL_IO_CFG_D0I3MAXDEVPG_I3E BIT17 +#define B_SERIAL_IO_CFG_D0I3MAXDEVPG_PGE BIT18 + +#define R_SERIAL_IO_CFG_INTERRUPTREG 0x3C +#define B_SERIAL_IO_CFG_INTERRUPTREG_INTLINE 0x000000FF + +// +// Serial IO Controllers MMIO Registers +// registers accessed : BAR0 + offset +// +#define R_SERIAL_IO_MEM_SSCR1 0x4 +#define B_SERIAL_IO_MEM_SSCR1_IFS BIT16 + +#define R_SERIAL_IO_MEM_PPR_CLK 0x200 +#define B_SERIAL_IO_MEM_PPR_CLK_EN BIT0 +#define B_SERIAL_IO_MEM_PPR_CLK_UPDATE BIT31 +#define V_SERIAL_IO_MEM_PPR_CLK_M_DIV 0x30 +#define V_SERIAL_IO_MEM_PPR_CLK_N_DIV 0xC35 + +#define R_SERIAL_IO_MEM_PPR_RESETS 0x204 +#define B_SERIAL_IO_MEM_PPR_RESETS_FUNC BIT0 +#define B_SERIAL_IO_MEM_PPR_RESETS_APB BIT1 +#define B_SERIAL_IO_MEM_PPR_RESETS_IDMA BIT2 + +#define R_SERIAL_IO_MEM_ACTIVE_LTR 0x210 +#define R_SERIAL_IO_MEM_IDLE_LTR 0x214 +#define B_SERIAL_IO_MEM_LTR_SNOOP_VALUE 0x000003FF +#define B_SERIAL_IO_MEM_LTR_SNOOP_SCALE 0x00001C00 +#define B_SERIAL_IO_MEM_LTR_SNOOP_REQUIREMENT BIT15 + +#define R_SERIAL_IO_MEM_SPI_CS_CONTROL 0x224 +#define B_SERIAL_IO_MEM_SPI_CS_CONTROL_STATE BIT1 +#define B_SERIAL_IO_MEM_SPI_CS_CONTROL_MODE BIT0 + +#define R_SERIAL_IO_MEM_REMAP_ADR_LOW 0x240 +#define R_SERIAL_IO_MEM_REMAP_ADR_HIGH 0x244 + +#define R_SERIAL_IO_MEM_I2C_SDA_HOLD 0x7C +#define V_SERIAL_IO_MEM_I2C_SDA_HOLD_VALUE 0x002C002C + +// +// I2C Controller +// Registers accessed through BAR0 + offset +// +#define R_IC_CON 0x00 // I2c Control +#define B_IC_MASTER_MODE BIT0 +#define B_IC_RESTART_EN BIT5 +#define B_IC_SLAVE_DISABLE BIT6 +#define V_IC_SPEED_STANDARD 0x02 +#define V_IC_SPEED_FAST 0x04 +#define V_IC_SPEED_HIGH 0x06 + +#define R_IC_TAR 0x04 // I2c Target Address +#define B_IC_TAR_10BITADDR_MASTER BIT12 + +#define R_IC_DATA_CMD 0x10 // I2c Rx/Tx Data Buf= fer and Command +#define B_IC_CMD_READ BIT8 // 1 =3D read, 0 = =3D write +#define B_IC_CMD_STOP BIT9 // 1 =3D STOP +#define B_IC_CMD_RESTART BIT10 // 1 =3D IC_RESTART= _EN +#define V_IC_WRITE_CMD_MASK 0xFF + +#define R_IC_SS_SCL_HCNT 0x14 // Standard Speed I2c = Clock SCL High Count +#define R_IC_SS_SCL_LCNT 0x18 // Standard Speed I2c = Clock SCL Low Count +#define R_IC_FS_SCL_HCNT 0x1C // Full Speed I2c Cloc= k SCL High Count +#define R_IC_FS_SCL_LCNT 0x20 // Full Speed I2c Cloc= k SCL Low Count +#define R_IC_HS_SCL_HCNT 0x24 // High Speed I2c Cloc= k SCL High Count +#define R_IC_HS_SCL_LCNT 0x28 // High Speed I2c Cloc= k SCL Low Count +#define R_IC_INTR_STAT 0x2C // I2c Inetrrupt Status +#define R_IC_INTR_MASK 0x30 // I2c Interrupt Mask +#define B_IC_INTR_GEN_CALL BIT11 // General call rece= ived +#define B_IC_INTR_START_DET BIT10 +#define B_IC_INTR_STOP_DET BIT9 +#define B_IC_INTR_ACTIVITY BIT8 +#define B_IC_INTR_TX_ABRT BIT6 // Set on NACK +#define B_IC_INTR_TX_EMPTY BIT4 +#define B_IC_INTR_TX_OVER BIT3 +#define B_IC_INTR_RX_FULL BIT2 // Data bytes in RX = FIFO over threshold +#define B_IC_INTR_RX_OVER BIT1 +#define B_IC_INTR_RX_UNDER BIT0 +#define R_IC_RAW_INTR_STAT ( 0x34) // I2c Raw Interrupt = Status +#define R_IC_RX_TL ( 0x38) // I2c Receive FIFO T= hreshold +#define R_IC_TX_TL ( 0x3C) // I2c Transmit FIFO = Threshold +#define R_IC_CLR_INTR ( 0x40) // Clear Combined and= Individual Interrupts +#define R_IC_CLR_RX_UNDER ( 0x44) // Clear RX_UNDER Int= errupt +#define R_IC_CLR_RX_OVER ( 0x48) // Clear RX_OVERinter= rupt +#define R_IC_CLR_TX_OVER ( 0x4C) // Clear TX_OVER inte= rrupt +#define R_IC_CLR_RD_REQ ( 0x50) // Clear RD_REQ inter= rupt +#define R_IC_CLR_TX_ABRT ( 0x54) // Clear TX_ABRT inte= rrupt +#define R_IC_CLR_RX_DONE ( 0x58) // Clear RX_DONE inte= rrupt +#define R_IC_CLR_ACTIVITY ( 0x5C) // Clear ACTIVITY int= errupt +#define R_IC_CLR_STOP_DET ( 0x60) // Clear STOP_DET int= errupt +#define R_IC_CLR_START_DET ( 0x64) // Clear START_DET in= terrupt +#define R_IC_CLR_GEN_CALL ( 0x68) // Clear GEN_CALL int= errupt +#define R_IC_ENABLE ( 0x6C) // I2c Enable + +#define R_IC_STATUS 0x70 // I2c Status +#define B_IC_STATUS_RFF BIT4 // RX FIFO is comple= tely full +#define B_IC_STATUS_RFNE BIT3 // RX FIFO is not em= pty +#define B_IC_STATUS_TFE BIT2 // TX FIFO is comple= tely empty +#define B_IC_STATUS_TFNF BIT1 // TX FIFO is not fu= ll +#define B_IC_STATUS_ACTIVITY BIT0 // Controller Activi= ty Status. + +#define R_IC_TXFL R ( 0x74) // Transmit FIFO Leve= l Register +#define R_IC_RXFLR ( 0x78) // Receive FIFO Level= Register +#define R_IC_SDA_HOLD ( 0x7C) +#define R_IC_TX_ABRT_SOURCE ( 0x80) // I2c Transmit Abort= Status Register +#define B_IC_TX_ABRT_7B_ADDR_NACK BIT0 // NACK on 7-bit address + +#define R_IC_SDA_SETUP ( 0x94) // I2c SDA Setup Regi= ster +#define R_IC_ACK_GENERAL_CALL ( 0x98) // I2c ACK General Ca= ll Register +#define R_IC_ENABLE_STATUS ( 0x9C) // I2c Enable Status = Register +#define B_IC_EN BIT0 // I2c enable status + +#define R_IC_CLK_GATE ( 0xC0) +#define R_IC_COMP_PARAM ( 0xF4) // Component Paramete= r Register +#define R_IC_COMP_VERSION ( 0xF8) // Component Version = ID +#define R_IC_COMP_TYPE ( 0xFC) // Component Type + +// +// Bridge Private Configuration Registers +// accessed only through SB messaging. SB access =3D SerialIo IOSF2OCP Bri= dge Port ID + offset +// +#define R_SERIAL_IO_PCR_PMCTL 0x1D0 +#define V_SERIAL_IO_PCR_PMCTL_PWR_GATING 0x3F + +#define R_SERIAL_IO_PCR_PCICFGCTRLx 0x200 +#define V_SERIAL_IO_PCR_PCICFGCTRL_N_OFFS 0x04 +#define R_SERIAL_IO_PCR_PCICFGCTRL1 0x200 //I2C0 +#define R_SERIAL_IO_PCR_PCICFGCTRL2 0x204 //I2C1 +#define R_SERIAL_IO_PCR_PCICFGCTRL3 0x208 //I2C2 +#define R_SERIAL_IO_PCR_PCICFGCTRL4 0x20C //I2C3 +#define R_SERIAL_IO_PCR_PCICFGCTRL5 0x210 //I2C4 +#define R_SERIAL_IO_PCR_PCICFGCTRL6 0x214 //I2C5 +#define R_SERIAL_IO_PCR_PCICFGCTRL9 0x218 //UA00 +#define R_SERIAL_IO_PCR_PCICFGCTRL10 0x21C //UA01 +#define R_SERIAL_IO_PCR_PCICFGCTRL11 0x220 //UA02 +#define R_SERIAL_IO_PCR_PCICFGCTRL13 0x224 //SPI0 +#define R_SERIAL_IO_PCR_PCICFGCTRL14 0x228 //SPI1 + +#define B_SERIAL_IO_PCR_PCICFGCTRL_PCI_CFG_DIS BIT0 +#define B_SERIAL_IO_PCR_PCICFGCTRL_ACPI_INTR_EN BIT1 +#define B_SERIAL_IO_PCR_PCICFGCTRL_BAR1_DIS BIT7 +#define B_SERIAL_IO_PCR_PCICFGCTRL_INT_PIN (BIT11 | BIT10 | BIT9 = | BIT8) +#define N_SERIAL_IO_PCR_PCICFGCTRL_INT_PIN 8 +#define V_SERIAL_IO_PCR_PCICFGCTRL_INTA 0x01 +#define V_SERIAL_IO_PCR_PCICFGCTRL_INTB 0x02 +#define V_SERIAL_IO_PCR_PCICFGCTRL_INTC 0x03 +#define V_SERIAL_IO_PCR_PCICFGCTRL_INTD 0x04 +#define B_SERIAL_IO_PCR_PCICFGCTRL_ACPI_IRQ 0x000FF000 +#define N_SERIAL_IO_PCR_PCICFGCTRL_ACPI_IRQ 12 +#define B_SERIAL_IO_PCR_PCICFGCTRL_PCI_IRQ 0x0FF00000 +#define N_SERIAL_IO_PCR_PCICFGCTRL_PCI_IRQ 20 + +#define R_SERIAL_IO_PCR_GPPRVRW2 0x604 +#define B_SERIAL_IO_PCR_GPPRVRW2_PGCB_FRC_CLK_CP_EN BIT1 +#define B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CG_EN BIT5 +#define B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CLKREQ_CTL_EN BIT11 +#define V_SERIAL_IO_PCR_GPPRVRW2_CLK_GATING (B_SERIAL_IO_P= CR_GPPRVRW2_PGCB_FRC_CLK_CP_EN | B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CG_E= N | B_SERIAL_IO_PCR_GPPRVRW2_CDC_SIDE_CFG_CLKREQ_CTL_EN) + + +#define R_SERIAL_IO_PCR_GPPRVRW7 0x618 +#define B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN BIT0 +#define B_SERIAL_IO_PCR_GPPRVRW7_UART1_BYTE_ADDR_EN BIT1 +#define B_SERIAL_IO_PCR_GPPRVRW7_UART2_BYTE_ADDR_EN BIT2 + +// +// Number of pins used by SerialIo controllers +// +#define PCH_SERIAL_IO_PINS_PER_I2C_CONTROLLER 2 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 +#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 +#define PCH_SERIAL_IO_PINS_PER_SPI_CONTROLLER 4 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sSerialIoCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/Pc= hRegsSerialIoCnl.h new file mode 100644 index 0000000000..62b859dc99 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSerial= IoCnl.h @@ -0,0 +1,138 @@ +/** @file + Device IDs for PCH Serial IO Controllers for PCH + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SERIAL_IO_CNL_ +#define _PCH_REGS_SERIAL_IO_CNL_ + +// +// Serial IO I2C0 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C0_DEVICE_ID 0x9DE8 +#define V_CNL_PCH_H_SERIAL_IO_CFG_I2C0_DEVICE_ID 0xA368 + +// +// Serial IO I2C1 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C1_DEVICE_ID 0x9DE9 +#define V_CNL_PCH_H_SERIAL_IO_CFG_I2C1_DEVICE_ID 0xA369 + +// +// Serial IO I2C2 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C2_DEVICE_ID 0x9DEA +#define V_CNL_PCH_H_SERIAL_IO_CFG_I2C2_DEVICE_ID 0xA36A + +// +// Serial IO I2C3 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C3_DEVICE_ID 0x9DEB +#define V_CNL_PCH_H_SERIAL_IO_CFG_I2C3_DEVICE_ID 0xA36B + +// +// Serial IO I2C4 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 0 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C4_DEVICE_ID 0x9DC5 + +// +// Serial IO I2C5 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_I2C5_DEVICE_ID 0x9DC6 + +// +// Serial IO SPI0 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_SPI0_DEVICE_ID 0x9DAA +#define V_CNL_PCH_H_SERIAL_IO_CFG_SPI0_DEVICE_ID 0xA32A + +// +// Serial IO SPI1 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_SPI1_DEVICE_ID 0x9DAB +#define V_CNL_PCH_H_SERIAL_IO_CFG_SPI1_DEVICE_ID 0xA32B + +// +// Serial IO UART0 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_UART0_DEVICE_ID 0x9DA8 +#define V_CNL_PCH_H_SERIAL_IO_CFG_UART0_DEVICE_ID 0xA328 + +// +// Serial IO UART1 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_UART1_DEVICE_ID 0x9DA9 +#define V_CNL_PCH_H_SERIAL_IO_CFG_UART1_DEVICE_ID 0xA329 + +// +// Serial IO UART2 Controller Registers +// +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2 25 +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2 2 + +#define V_CNL_PCH_LP_SERIAL_IO_CFG_UART2_DEVICE_ID 0x9DC7 +#define V_CNL_PCH_H_SERIAL_IO_CFG_UART2_DEVICE_ID 0xA347 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sSmbus.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsS= mbus.h new file mode 100644 index 0000000000..e571a6a127 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSmbus.h @@ -0,0 +1,151 @@ +/** @file + Register names for PCH Smbus Device. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used . + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SMBUS_H_ +#define _PCH_REGS_SMBUS_H_ + +// +// SMBus Controller Registers (D31:F4) +// +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31 +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4 +#define R_SMBUS_CFG_BASE 0x20 +#define V_SMBUS_CFG_BASE_SIZE (1 << 5) +#define B_SMBUS_CFG_BASE_BAR 0x0000FFE0 +#define R_SMBUS_CFG_HOSTC 0x40 +#define B_SMBUS_CFG_HOSTC_SPDWD BIT4 +#define B_SMBUS_CFG_HOSTC_SSRESET BIT3 +#define B_SMBUS_CFG_HOSTC_I2C_EN BIT2 +#define B_SMBUS_CFG_HOSTC_SMI_EN BIT1 +#define B_SMBUS_CFG_HOSTC_HST_EN BIT0 +#define R_SMBUS_CFG_TCOBASE 0x50 +#define B_SMBUS_CFG_TCOBASE_BAR 0x0000FFE0 +#define R_SMBUS_CFG_TCOCTL 0x54 +#define B_SMBUS_CFG_TCOCTL_TCO_BASE_EN BIT8 +#define B_SMBUS_CFG_TCOCTL_TCO_BASE_LOCK BIT0 +#define R_SMBUS_CFG_64 0x64 +#define R_SMBUS_CFG_80 0x80 + +// +// SMBus I/O Registers +// +#define R_SMBUS_IO_HSTS 0x00 ///< Host Status Register R= /W +#define B_SMBUS_IO_HBSY 0x01 +#define B_SMBUS_IO_INTR 0x02 +#define B_SMBUS_IO_DERR 0x04 +#define B_SMBUS_IO_BERR 0x08 +#define B_SMBUS_IO_FAIL 0x10 +#define B_SMBUS_IO_SMBALERT_STS 0x20 +#define B_SMBUS_IO_IUS 0x40 +#define B_SMBUS_IO_BYTE_DONE_STS 0x80 +#define B_SMBUS_IO_ERROR (B_SMBUS_IO_DERR | B_SMBUS_IO_BER= R | B_SMBUS_IO_FAIL) +#define B_SMBUS_IO_HSTS_ALL 0xFF +#define R_SMBUS_IO_HCTL 0x02 ///< Host Control Register = R/W +#define B_SMBUS_IO_INTREN 0x01 +#define B_SMBUS_IO_KILL 0x02 +#define B_SMBUS_IO_SMB_CMD 0x1C +#define V_SMBUS_IO_SMB_CMD_QUICK 0x00 +#define V_SMBUS_IO_SMB_CMD_BYTE 0x04 +#define V_SMBUS_IO_SMB_CMD_BYTE_DATA 0x08 +#define V_SMBUS_IO_SMB_CMD_WORD_DATA 0x0C +#define V_SMBUS_IO_SMB_CMD_PROCESS_CALL 0x10 +#define V_SMBUS_IO_SMB_CMD_BLOCK 0x14 +#define V_SMBUS_IO_SMB_CMD_IIC_READ 0x18 +#define V_SMBUS_IO_SMB_CMD_BLOCK_PROCESS 0x1C +#define B_SMBUS_IO_LAST_BYTE 0x20 +#define B_SMBUS_IO_START 0x40 +#define B_SMBUS_IO_PEC_EN 0x80 +#define R_SMBUS_IO_HCMD 0x03 ///< Host Command Register = R/W +#define R_SMBUS_IO_TSA 0x04 ///< Transmit Slave Address= Register R/W +#define B_SMBUS_IO_RW_SEL 0x01 +#define B_SMBUS_IO_READ 0x01 // RW +#define B_SMBUS_IO_WRITE 0x00 // RW +#define B_SMBUS_IO_ADDRESS 0xFE +#define R_SMBUS_IO_HD0 0x05 ///< Data 0 Register R/W +#define R_SMBUS_IO_HD1 0x06 ///< Data 1 Register R/W +#define R_SMBUS_IO_HBD 0x07 ///< Host Block Data Regist= er R/W +#define R_SMBUS_IO_PEC 0x08 ///< Packet Error Check Dat= a Register R/W +#define R_SMBUS_IO_RSA 0x09 ///< Receive Slave Address = Register R/W +#define B_SMBUS_IO_SLAVE_ADDR 0x7F +#define R_SMBUS_IO_SD 0x0A ///< Receive Slave Data Reg= ister R/W +#define R_SMBUS_IO_AUXS 0x0C ///< Auxiliary Status Regis= ter R/WC +#define B_SMBUS_IO_CRCE 0x01 +#define B_SMBUS_IO_STCO 0x02 ///< SMBus TCO Mode +#define R_SMBUS_IO_AUXC 0x0D ///< Auxiliary Control Regi= ster R/W +#define B_SMBUS_IO_AAC 0x01 +#define B_SMBUS_IO_E32B 0x02 +#define R_SMBUS_IO_SMLC 0x0E ///< SMLINK Pin Control Reg= ister R/W +#define B_SMBUS_IO_SMLINK0_CUR_STS 0x01 +#define B_SMBUS_IO_SMLINK1_CUR_STS 0x02 +#define B_SMBUS_IO_SMLINK_CLK_CTL 0x04 +#define R_SMBUS_IO_SMBC 0x0F ///< SMBus Pin Control Regi= ster R/W +#define B_SMBUS_IO_SMBCLK_CUR_STS 0x01 +#define B_SMBUS_IO_SMBDATA_CUR_STS 0x02 +#define B_SMBUS_IO_SMBCLK_CTL 0x04 +#define R_SMBUS_IO_SSTS 0x10 ///< Slave Status Register = R/WC +#define B_SMBUS_IO_HOST_NOTIFY_STS 0x01 +#define R_SMBUS_IO_SCMD 0x11 ///< Slave Command Register= R/W +#define B_SMBUS_IO_HOST_NOTIFY_INTREN 0x01 +#define B_SMBUS_IO_HOST_NOTIFY_WKEN 0x02 +#define B_SMBUS_IO_SMBALERT_DIS 0x04 +#define R_SMBUS_IO_NDA 0x14 ///< Notify Device Address = Register RO +#define B_SMBUS_IO_DEVICE_ADDRESS 0xFE +#define R_SMBUS_IO_NDLB 0x16 ///< Notify Data Low Byte R= egister RO +#define R_SMBUS_IO_NDHB 0x17 ///< Notify Data High Byte = Register RO + +// +// SMBus Private Config Registers +// (PID:SMB) +// +#define R_SMBUS_PCR_TCOCFG 0x00 ///<= TCO Configuration register +#define B_SMBUS_PCR_TCOCFG_IE BIT7 ///<= TCO IRQ Enable +#define B_SMBUS_PCR_TCOCFG_IS (BIT2 | BIT1 | BIT0) ///<= TCO IRQ Select +#define V_SMBUS_PCR_TCOCFG_IRQ_9 0x00 +#define V_SMBUS_PCR_TCOCFG_IRQ_10 0x01 +#define V_SMBUS_PCR_TCOCFG_IRQ_11 0x02 +#define V_SMBUS_PCR_TCOCFG_IRQ_20 0x04 ///<= only if APIC enabled +#define V_SMBUS_PCR_TCOCFG_IRQ_21 0x05 ///<= only if APIC enabled +#define V_SMBUS_PCR_TCOCFG_IRQ_22 0x06 ///<= only if APIC enabled +#define V_SMBUS_PCR_TCOCFG_IRQ_23 0x07 ///<= only if APIC enabled +#define R_SMBUS_PCR_SMBTM 0x04 ///<= SMBus Test Mode +#define B_SMBUS_PCR_SMBTM_SMBCT BIT1 ///<= SMBus Counter +#define B_SMBUS_PCR_SMBTM_SMBDG BIT0 ///<= SMBus Deglitch +#define R_SMBUS_PCR_SCTM 0x08 ///<= Short Counter Test Mode +#define B_SMBUS_PCR_SCTM_SSU BIT31 ///<= Simulation Speed-Up +#define R_SMBUS_PCR_GC 0x0C ///<= General Control +#define B_SMBUS_PCR_GC_FD BIT0 ///<= Function Disable +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sSpi.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSpi= .h new file mode 100644 index 0000000000..013603ca25 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsSpi.h @@ -0,0 +1,295 @@ +/** @file + Register names for PCH SPI device. + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_SPI_H_ +#define _PCH_REGS_SPI_H_ + +// +// SPI Registers (D31:F5) +// + +#define PCI_DEVICE_NUMBER_PCH_SPI 31 +#define PCI_FUNCTION_NUMBER_PCH_SPI 5 + +#define R_SPI_CFG_BAR0 0x10 +#define B_SPI_CFG_BAR0_MASK 0x0FFF + +#define R_SPI_CFG_BDE 0xD8 +#define B_SPI_CFG_BDE_F8 0x8000 +#define B_SPI_CFG_BDE_F0 0x4000 +#define B_SPI_CFG_BDE_E8 0x2000 +#define B_SPI_CFG_BDE_E0 0x1000 +#define B_SPI_CFG_BDE_D8 0x0800 +#define B_SPI_CFG_BDE_D0 0x0400 +#define B_SPI_CFG_BDE_C8 0x0200 +#define B_SPI_CFG_BDE_C0 0x0100 +#define B_SPI_CFG_BDE_LEG_F 0x0080 +#define B_SPI_CFG_BDE_LEG_E 0x0040 +#define B_SPI_CFG_BDE_70 0x0008 +#define B_SPI_CFG_BDE_60 0x0004 +#define B_SPI_CFG_BDE_50 0x0002 +#define B_SPI_CFG_BDE_40 0x0001 + +#define R_SPI_CFG_BC 0xDC +#define S_SPI_CFG_BC 4 +#define N_SPI_CFG_BC_ASE_BWP 11 +#define B_SPI_CFG_BC_ASE_BWP BIT11 +#define N_SPI_CFG_BC_ASYNC_SS 10 +#define B_SPI_CFG_BC_ASYNC_SS BIT10 +#define B_SPI_CFG_BC_OSFH BIT9 ///< OS Functi= on Hide +#define N_SPI_CFG_BC_SYNC_SS 8 +#define B_SPI_CFG_BC_SYNC_SS BIT8 +#define B_SPI_CFG_BC_BILD BIT7 +#define B_SPI_CFG_BC_BBS BIT6 ///< Boot BIOS= strap +#define N_SPI_CFG_BC_BBS 6 +#define V_SPI_CFG_BC_BBS_SPI 0 ///< Boot BIOS= strapped to SPI +#define V_SPI_CFG_BC_BBS_LPC 1 ///< Boot BIOS= strapped to LPC +#define B_SPI_CFG_BC_EISS BIT5 ///< Enable In= SMM.STS +#define B_SPI_CFG_BC_TSS BIT4 +#define B_SPI_CFG_BC_SRC (BIT3 | BIT2) +#define N_SPI_CFG_BC_SRC 2 +#define V_SPI_CFG_BC_SRC_PREF_EN_CACHE_EN 0x02 ///< Prefetchi= ng and Caching enabled +#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS 0x01 ///< No prefet= ching and no caching +#define V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_EN 0x00 ///< No prefet= ching, but caching enabled +#define B_SPI_CFG_BC_LE BIT1 ///< Lock Enab= le +#define N_SPI_CFG_BC_BLE 1 +#define B_SPI_CFG_BC_WPD BIT0 ///< Write Pro= tect Disable + +// +// BIOS Flash Program Registers (based on SPI_BAR0) +// +#define R_SPI_MEM_BFPR 0x00 = ///< BIOS Flash Primary Region Register(32bits), which is RO and contains t= he same value from FREG1 +#define B_SPI_MEM_BFPR_PRL 0x7FFF0000 = ///< BIOS Flash Primary Region Limit mask +#define N_SPI_MEM_BFPR_PRL 16 = ///< BIOS Flash Primary Region Limit bit position +#define B_SPI_MEM_BFPR_PRB 0x00007FFF = ///< BIOS Flash Primary Region Base mask +#define N_SPI_MEM_BFPR_PRB 0 = ///< BIOS Flash Primary Region Base bit position +#define R_SPI_MEM_HSFSC 0x04 = ///< Hardware Sequencing Flash Status and Control Register(32bits) +#define B_SPI_MEM_HSFSC_FSMIE BIT31 = ///< Flash SPI SMI# Enable +#define B_SPI_MEM_HSFSC_FDBC_MASK 0x3F000000 = ///< Flash Data Byte Count ( <=3D 64), Count =3D (Value in this field) + 1. +#define N_SPI_MEM_HSFSC_FDBC 24 +#define B_SPI_MEM_HSFSC_CYCLE_MASK 0x001E0000 = ///< Flash Cycle. +#define N_SPI_MEM_HSFSC_CYCLE 17 +#define V_SPI_MEM_HSFSC_CYCLE_READ 0 = ///< Flash Cycle Read +#define V_SPI_MEM_HSFSC_CYCLE_WRITE 2 = ///< Flash Cycle Write +#define V_SPI_MEM_HSFSC_CYCLE_4K_ERASE 3 = ///< Flash Cycle 4K Block Erase +#define V_SPI_MEM_HSFSC_CYCLE_64K_ERASE 4 = ///< Flash Cycle 64K Sector Erase +#define V_SPI_MEM_HSFSC_CYCLE_READ_SFDP 5 = ///< Flash Cycle Read SFDP +#define V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID 6 = ///< Flash Cycle Read JEDEC ID +#define V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS 7 = ///< Flash Cycle Write Status +#define V_SPI_MEM_HSFSC_CYCLE_READ_STATUS 8 = ///< Flash Cycle Read Status +#define B_SPI_MEM_HSFSC_CYCLE_FGO BIT16 = ///< Flash Cycle Go. +#define B_SPI_MEM_HSFSC_FLOCKDN BIT15 = ///< Flash Configuration Lock-Down +#define B_SPI_MEM_HSFSC_FDV BIT14 = ///< Flash Descriptor Valid, once valid software can use hareware sequencin= g regs +#define B_SPI_MEM_HSFSC_FDOPSS BIT13 = ///< Flash Descriptor Override Pin-Strap Status +#define B_SPI_MEM_HSFSC_PRR34_LOCKDN BIT12 = ///< PRR3 PRR4 Lock-Down +#define B_SPI_MEM_HSFSC_WRSDIS BIT11 = ///< Write Status Disable +#define B_SPI_MEM_HSFSC_SAF_CE BIT8 = ///< SAF ctype error +#define B_SPI_MEM_HSFSC_SAF_MODE_ACTIVE BIT7 = ///< Indicates flash is attached either directly to the PCH via the SPI bus= or EC/BMC +#define B_SPI_MEM_HSFSC_SAF_LE BIT6 = ///< SAF link error +#define B_SPI_MEM_HSFSC_SCIP BIT5 = ///< SPI cycle in progress +#define B_SPI_MEM_HSFSC_SAF_DLE BIT4 = ///< SAF Data length error +#define B_SPI_MEM_HSFSC_SAF_ERROR BIT3 = ///< SAF Error +#define B_SPI_MEM_HSFSC_AEL BIT2 = ///< Access Error Log +#define B_SPI_MEM_HSFSC_FCERR BIT1 = ///< Flash Cycle Error +#define B_SPI_MEM_HSFSC_FDONE BIT0 = ///< Flash Cycle Done +#define R_SPI_MEM_FADDR 0x08 = ///< SPI Flash Address +#define B_SPI_MEM_FADDR_MASK 0x07FFFFFF = ///< SPI Flash Address Mask (0~26bit) +#define R_SPI_MEM_DLOCK 0x0C = ///< Discrete Lock Bits +#define B_SPI_MEM_DLOCK_PR0LOCKDN BIT8 = ///< PR0LOCKDN +#define R_SPI_MEM_FDATA00 0x10 = ///< SPI Data 00 (32 bits) +#define R_SPI_MEM_FDATA01 0x14 = ///< SPI Data 01 +#define R_SPI_MEM_FDATA02 0x18 = ///< SPI Data 02 +#define R_SPI_MEM_FDATA03 0x1C = ///< SPI Data 03 +#define R_SPI_MEM_FDATA04 0x20 = ///< SPI Data 04 +#define R_SPI_MEM_FDATA05 0x24 = ///< SPI Data 05 +#define R_SPI_MEM_FDATA06 0x28 = ///< SPI Data 06 +#define R_SPI_MEM_FDATA07 0x2C = ///< SPI Data 07 +#define R_SPI_MEM_FDATA08 0x30 = ///< SPI Data 08 +#define R_SPI_MEM_FDATA09 0x34 = ///< SPI Data 09 +#define R_SPI_MEM_FDATA10 0x38 = ///< SPI Data 10 +#define R_SPI_MEM_FDATA11 0x3C = ///< SPI Data 11 +#define R_SPI_MEM_FDATA12 0x40 = ///< SPI Data 12 +#define R_SPI_MEM_FDATA13 0x44 = ///< SPI Data 13 +#define R_SPI_MEM_FDATA14 0x48 = ///< SPI Data 14 +#define R_SPI_MEM_FDATA15 0x4C = ///< SPI Data 15 +#define R_SPI_MEM_FRAP 0x50 = ///< Flash Region Access Permisions Register +#define B_SPI_MEM_FRAP_BRWA_MASK 0x0000FF00 = ///< BIOS Region Write Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIO= S; 2: ME; 3: GbE; 4: PlatformData +#define N_SPI_MEM_FRAP_BRWA 8 = ///< BIOS Region Write Access bit position +#define B_SPI_MEM_FRAP_BRRA_MASK 0x000000FF = ///< BIOS Region Read Access MASK, Region0~7 - 0: Flash Descriptor; 1: BIOS= ; 2: ME; 3: GbE; 4: PlatformData +#define B_SPI_MEM_FRAP_BMRAG_MASK 0x00FF0000 = ///< BIOS Master Read Access Grant +#define B_SPI_MEM_FRAP_BMWAG_MASK 0xFF000000 = ///< BIOS Master Write Access Grant +#define R_SPI_MEM_FREG0_FLASHD 0x54 = ///< Flash Region 0(Flash Descriptor)(32bits) +#define R_SPI_MEM_FREG1_BIOS 0x58 = ///< Flash Region 1(BIOS)(32bits) +#define R_SPI_MEM_FREG2_ME 0x5C = ///< Flash Region 2(ME)(32bits) +#define R_SPI_MEM_FREG3_GBE 0x60 = ///< Flash Region 3(GbE)(32bits) +#define R_SPI_MEM_FREG4_PLATFORM_DATA 0x64 = ///< Flash Region 4(Platform Data)(32bits) +#define R_SPI_MEM_FREG5_DER 0x68 = ///< Flash Region 5(Device Expansion Region)(32bits) +#define S_SPI_MEM_FREGX 4 = ///< Size of Flash Region register +#define B_SPI_MEM_FREGX_LIMIT_MASK 0x7FFF0000 = ///< Flash Region Limit [30:16] represents [26:12], [11:0] are assumed to b= e FFFh +#define N_SPI_MEM_FREGX_LIMIT 16 = ///< Region limit bit position +#define N_SPI_MEM_FREGX_LIMIT_REPR 12 = ///< Region limit bit represents position +#define B_SPI_MEM_FREGX_BASE_MASK 0x00007FFF = ///< Flash Region Base, [14:0] represents [26:12] +#define N_SPI_MEM_FREGX_BASE 0 = ///< Region base bit position +#define N_SPI_MEM_FREGX_BASE_REPR 12 = ///< Region base bit represents position +#define R_SPI_MEM_PR0 0x84 = ///< Protected Region 0 Register +#define R_SPI_MEM_PR1 0x88 = ///< Protected Region 1 Register +#define R_SPI_MEM_PR2 0x8C = ///< Protected Region 2 Register +#define R_SPI_MEM_PR3 0x90 = ///< Protected Region 3 Register +#define R_SPI_MEM_PR4 0x94 = ///< Protected Region 4 Register +#define S_SPI_MEM_PRX 4 = ///< Protected Region X Register size +#define B_SPI_MEM_PRX_WPE BIT31 = ///< Write Protection Enable +#define B_SPI_MEM_PRX_PRL_MASK 0x7FFF0000 = ///< Protected Range Limit Mask, [30:16] here represents upper limit of add= ress [26:12] +#define N_SPI_MEM_PRX_PRL 16 = ///< Protected Range Limit bit position +#define B_SPI_MEM_PRX_RPE BIT15 = ///< Read Protection Enable +#define B_SPI_MEM_PRX_PRB_MASK 0x00007FFF = ///< Protected Range Base Mask, [14:0] here represents base limit of addres= s [26:12] +#define N_SPI_MEM_PRX_PRB 0 = ///< Protected Range Base bit position +#define R_SPI_MEM_SFRAP 0xB0 = ///< Secondary Flash Regions Access Permisions Register +#define R_SPI_MEM_FDOC 0xB4 = ///< Flash Descriptor Observability Control Register(32 bits) +#define B_SPI_MEM_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) = ///< Flash Descritor Section Select +#define V_SPI_MEM_FDOC_FDSS_FSDM 0x0000 = ///< Flash Signature and Descriptor Map +#define V_SPI_MEM_FDOC_FDSS_COMP 0x1000 = ///< Component +#define V_SPI_MEM_FDOC_FDSS_REGN 0x2000 = ///< Region +#define V_SPI_MEM_FDOC_FDSS_MSTR 0x3000 = ///< Master +#define V_SPI_MEM_FDOC_FDSS_PCHS 0x4000 = ///< PCH soft straps +#define V_SPI_MEM_FDOC_FDSS_SFDP 0x5000 = ///< SFDP Parameter Table +#define B_SPI_MEM_FDOC_FDSI_MASK 0x0FFC = ///< Flash Descriptor Section Index +#define R_SPI_MEM_FDOD 0xB8 = ///< Flash Descriptor Observability Data Register(32 bits) +#define R_SPI_MEM_SFDP0_VSCC0 0xC4 = ///< Vendor Specific Component Capabilities Register(32 bits) +#define B_SPI_MEM_SFDPX_VSCCX_CPPTV BIT31 = ///< Component Property Parameter Table Valid +#define B_SPI_MEM_SFDP0_VSCC0_VCL BIT30 = ///< Vendor Component Lock +#define B_SPI_MEM_SFDPX_VSCCX_EO_64K BIT29 = ///< 64k Erase valid (EO_64k_valid) +#define B_SPI_MEM_SFDPX_VSCCX_EO_4K BIT28 = ///< 4k Erase valid (EO_4k_valid) +#define B_SPI_MEM_SFDPX_VSCCX_RPMC BIT27 = ///< RPMC Supported +#define B_SPI_MEM_SFDPX_VSCCX_DPD BIT26 = ///< Deep Powerdown Supported +#define B_SPI_MEM_SFDPX_VSCCX_SUSRES BIT25 = ///< Suspend/Resume Supported +#define B_SPI_MEM_SFDPX_VSCCX_SOFTRES BIT24 = ///< Soft Reset Supported +#define B_SPI_MEM_SFDPX_VSCCX_64k_EO_MASK 0x00FF0000 = ///< 64k Erase Opcode (EO_64k) +#define B_SPI_MEM_SFDPX_VSCCX_4k_EO_MASK 0x0000FF00 = ///< 4k Erase Opcode (EO_4k) +#define B_SPI_MEM_SFDPX_VSCCX_QER (BIT7 | BIT6 | BIT5) = ///< Quad Enable Requirements +#define B_SPI_MEM_SFDPX_VSCCX_WEWS BIT4 = ///< Write Enable on Write Status +#define B_SPI_MEM_SFDPX_VSCCX_WSR BIT3 = ///< Write Status Required +#define B_SPI_MEM_SFDPX_VSCCX_WG_64B BIT2 = ///< Write Granularity, 0: 1 Byte; 1: 64 Bytes +#define R_SPI_MEM_SFDP1_VSCC1 0xC8 = ///< Vendor Specific Component Capabilities Register(32 bits) +#define R_SPI_MEM_PINTX 0xCC = ///< Parameter Table Index +#define N_SPI_MEM_PINTX_SPT 14 +#define V_SPI_MEM_PINTX_SPT_CPT0 0x0 = ///< Component 0 Property Parameter Table +#define V_SPI_MEM_PINTX_SPT_CPT1 0x1 = ///< Component 1 Property Parameter Table +#define N_SPI_MEM_PINTX_HORD 12 +#define V_SPI_MEM_PINTX_HORD_SFDP 0x0 = ///< SFDP Header +#define V_SPI_MEM_PINTX_HORD_PT 0x1 = ///< Parameter Table Header +#define V_SPI_MEM_PINTX_HORD_DATA 0x2 = ///< Data +#define R_SPI_MEM_PTDATA 0xD0 = ///< Parameter Table Data +#define R_SPI_MEM_SBRS 0xD4 = ///< SPI Bus Requester Status + +// +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0 +// +#define R_SPI_FLASH_FDBAR_FLVALSIG 0x00 = ///< Flash Valid Signature +#define V_SPI_FLASH_FDBAR_FLVALSIG 0x0FF0A55A +#define R_SPI_FLASH_FDBAR_FLASH_MAP0 0x04 +#define B_SPI_FLASH_FDBAR_FCBA 0x000000FF = ///< Flash Component Base Address +#define B_SPI_FLASH_FDBAR_NC 0x00000300 = ///< Number Of Components +#define N_SPI_FLASH_FDBAR_NC 8 = ///< Number Of Components +#define V_SPI_FLASH_FDBAR_NC_1 0x00000000 +#define V_SPI_FLASH_FDBAR_NC_2 0x00000100 +#define B_SPI_FLASH_FDBAR_FRBA 0x00FF0000 = ///< Flash Region Base Address +#define B_SPI_FLASH_FDBAR_NR 0x07000000 = ///< Number Of Regions +#define R_SPI_FLASH_FDBAR_FLASH_MAP1 0x08 +#define B_SPI_FLASH_FDBAR_FMBA 0x000000FF = ///< Flash Master Base Address +#define B_SPI_FLASH_FDBAR_NM 0x00000700 = ///< Number Of Masters +#define B_SPI_FLASH_FDBAR_FPSBA 0x00FF0000 = ///< PCH Strap Base Address, [23:16] represents [11:4] +#define N_SPI_FLASH_FDBAR_FPSBA 16 = ///< PCH Strap base Address bit position +#define N_SPI_FLASH_FDBAR_FPSBA_REPR 4 = ///< PCH Strap base Address bit represents position +#define B_SPI_FLASH_FDBAR_PCHSL 0xFF000000 = ///< PCH Strap Length, [31:24] represents number of Dwords +#define N_SPI_FLASH_FDBAR_PCHSL 24 = ///< PCH Strap Length bit position +#define R_SPI_FLASH_FDBAR_FLASH_MAP2 0x0C +#define B_SPI_FLASH_FDBAR_FCPUSBA 0x000000FF = ///< CPU Strap Base Address, [7:0] represents [11:4] +#define N_SPI_FLASH_FDBAR_FCPUSBA 0 = ///< CPU Strap Base Address bit position +#define N_SPI_FLASH_FDBAR_FCPUSBA_REPR 4 = ///< CPU Strap Base Address bit represents position +#define B_SPI_FLASH_FDBAR_CPUSL 0x0000FF00 = ///< CPU Strap Length, [15:8] represents number of Dwords +#define N_SPI_FLASH_FDBAR_CPUSL 8 = ///< CPU Strap Length bit position +// +// Flash Component Base Address (FCBA) from Flash Region 0 +// +#define R_SPI_FLASH_FCBA_FLCOMP 0x00 = ///< Flash Components Register +#define B_SPI_FLASH_FLCOMP_RIDS_FREQ (BIT29 | BIT28 | BIT27) = ///< Read ID and Read Status Clock Frequency +#define B_SPI_FLASH_FLCOMP_WE_FREQ (BIT26 | BIT25 | BIT24) = ///< Write and Erase Clock Frequency +#define B_SPI_FLASH_FLCOMP_FRCF_FREQ (BIT23 | BIT22 | BIT21) = ///< Fast Read Clock Frequency +#define B_SPI_FLASH_FLCOMP_FR_SUP BIT20 = ///< Fast Read Support. +#define B_SPI_FLASH_FLCOMP_RC_FREQ (BIT19 | BIT18 | BIT17) = ///< Read Clock Frequency. +#define V_SPI_FLASH_FLCOMP_FREQ_48MHZ 0x02 +#define V_SPI_FLASH_FLCOMP_FREQ_30MHZ 0x04 +#define V_SPI_FLASH_FLCOMP_FREQ_17MHZ 0x06 +#define B_SPI_FLASH_FLCOMP_COMP1_MASK 0xF0 = ///< Flash Component 1 Size MASK +#define N_SPI_FLASH_FLCOMP_COMP1 4 = ///< Flash Component 1 Size bit position +#define B_SPI_FLASH_FLCOMP_COMP0_MASK 0x0F = ///< Flash Component 0 Size MASK +#define V_SPI_FLASH_FLCOMP_COMP_512KB 0x80000 +// +// Descriptor Upper Map Section from Flash Region 0 +// +#define R_SPI_FLASH_UMAP1 0xEFC = ///< Flash Upper Map 1 +#define B_SPI_FLASH_UMAP1_VTBA 0x000000FF = ///< VSCC Table Base Address +#define B_SPI_FLASH_UMAP1_VTL 0x0000FF00 = ///< VSCC Table Length + +// +// SPI Private Configuration Space Registers +// +#define R_SPI_PCR_CLK_CTL 0xC004 +#define R_SPI_PCR_PWR_CTL 0xC008 +#define R_SPI_PCR_ESPI_SOFTSTRAPS 0xC210 +#define B_SPI_PCR_ESPI_SLAVE BIT12 + +// +// MMP0 +// +#define R_PCH_SPI_STRP_MMP0 0xC4 ///< MMP0 Soft strap o= ffset +#define B_PCH_SPI_STRP_MMP0 0x10 ///< MMP0 Soft strap b= it + + +#define R_PCH_SPI_STRP_SFDP 0xF0 ///< PCH Soft Strap SF= DP +#define B_PCH_SPI_STRP_SFDP_QIORE BIT3 ///< Quad IO Read Enab= le +#define B_PCH_SPI_STRP_SFDP_QORE BIT2 ///< Quad Output Read = Enable +#define B_PCH_SPI_STRP_SFDP_DIORE BIT1 ///< Dual IO Read Enab= le +#define B_PCH_SPI_STRP_SFDP_DORE BIT0 ///< Dual Output Read = Enable + +// +// Descriptor Record 0 +// +#define R_PCH_SPI_STRP_DSCR_0 0x00 ///< PCH Soft Strap 0 +#define B_PCH_SPI_STRP_DSCR_0_PTT_SUPP BIT22 ///< PTT Supported + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sThermalCnl.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/Pch= RegsThermalCnl.h new file mode 100644 index 0000000000..fb93a62364 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsTherma= lCnl.h @@ -0,0 +1,49 @@ +/** @file + Register names for PCH Thermal Device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_THERMAL_H_ +#define _PCH_REGS_THERMAL_H_ + +// +// Thermal Device Registers (D18:0) +// +#define PCI_DEVICE_NUMBER_PCH_THERMAL 18 +#define PCI_FUNCTION_NUMBER_PCH_THERMAL 0 +#define R_THERMAL_CFG_MEM_TBAR 0x10 +#define B_THERMAL_CFG_MEM_TBAR_MASK 0xFFFFF000 +#define R_THERMAL_CFG_MEM_TBARH 0x14 +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchReg= sTraceHub.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRe= gsTraceHub.h new file mode 100644 index 0000000000..21f9839546 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Register/PchRegsTraceH= ub.h @@ -0,0 +1,134 @@ +/** @file + Register names for PCH TraceHub device + + Conventions: + + - Register definition format: + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName + - Prefix: + Definitions beginning with "R_" are registers + Definitions beginning with "B_" are bits within registers + Definitions beginning with "V_" are meaningful values within the bits + Definitions beginning with "S_" are register size + Definitions beginning with "N_" are the bit position + - [GenerationName]: + Three letter acronym of the generation is used + Register name without GenerationName applies to all generations. + - [ComponentName]: + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.) + Register name without ComponentName applies to all components. + Register that is specific to -H denoted by "_PCH_H_" in component name. + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me. + - SubsystemName: + This field indicates the subsystem name of the component that the regi= ster belongs to + (e.g. PCIE, USB, SATA, GPIO, PMC etc.). + - RegisterSpace: + MEM - MMIO space register of subsystem. + IO - IO space register of subsystem. + PCR - Private configuration register of subsystem. + CFG - PCI configuration space register of subsystem. + - RegisterName: + Full register name. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_REGS_TRACE_HUB_H_ +#define _PCH_REGS_TRACE_HUB_H_ + +// +// TraceHub Registers (D31:F7) +// +#define PCI_DEVICE_NUMBER_PCH_TRACE_HUB 31 +#define PCI_FUNCTION_NUMBER_PCH_TRACE_HUB 7 + +#define R_TRACE_HUB_CFG_CSR_MTB_LBAR 0x10 +#define B_TRACE_HUB_CFG_CSR_MTB_RBAL 0xFFF00000 +#define R_TRACE_HUB_CFG_CSR_MTB_UBAR 0x14 +#define B_TRACE_HUB_CFG_CSR_MTB_RBAU 0xFFFFFFFF +#define R_TRACE_HUB_CFG_SW_LBAR 0x18 +#define R_TRACE_HUB_CFG_SW_UBAR 0x1C +#define B_TRACE_HUB_CFG_SW_RBAU 0xFFFFFFFF +#define R_TRACE_HUB_CFG_RTIT_LBAR 0x20 +#define B_TRACE_HUB_CFG_RTIT_RBAL 0xFFFFFF00 +#define R_TRACE_HUB_CFG_RTIT_UBAR 0x24 +#define B_TRACE_HUB_CFG_RTIT_RBAU 0xFFFFFFFF +#define R_TRACE_HUB_CFG_MSICID 0x40 +#define R_TRACE_HUB_CFG_MSINCP 0x41 +#define R_TRACE_HUB_CFG_MSIMC 0x42 +#define R_TRACE_HUB_CFG_MSILMA 0x44 +#define R_TRACE_HUB_CFG_MSIUMA 0x48 +#define R_TRACE_HUB_CFG_MSIMD 0x4C +#define B_TRACE_HUB_CFG_FW_RBAU 0xFFFFFFFF +#define R_TRACE_HUB_CFG_DSC 0x80 +#define B_TRACE_HUB_CFG_BYP BIT0 //< TraceHub By= pass +#define R_TRACE_HUB_CFG_DSS 0x81 +#define R_TRACE_HUB_CFG_ISTOT 0x84 +#define R_TRACE_HUB_CFG_ICTOT 0x88 +#define R_TRACE_HUB_CFG_IPAD 0x8C +#define R_TRACE_HUB_CFG_DSD 0x90 + +// +// Offsets from CSR_MTB_BAR +// +#define R_TRACE_HUB_MEM_MTB_GTHOPT0 0x00 +#define B_TRACE_HUB_MEM_MTB_GTHOPT0_P0FLUSH BIT7 +#define B_TRACE_HUB_MEM_MTB_GTHOPT0_P1FLUSH BIT15 +#define V_TRACE_HUB_MEM_MTB_SWDEST_PTI 0x0A +#define V_TRACE_HUB_MEM_MTB_SWDEST_MEMEXI 0x08 +#define V_TRACE_HUB_MEM_MTB_SWDEST_DISABLE 0x00 +#define R_TRACE_HUB_MEM_MTB_SWDEST_1 0x0C +#define B_TRACE_HUB_MEM_MTB_SWDEST_CSE_1 0x0000000F +#define B_TRACE_HUB_MEM_MTB_SWDEST_CSE_2 0x000000F0 +#define B_TRACE_HUB_MEM_MTB_SWDEST_CSE_3 0x00000F00 +#define B_TRACE_HUB_MEM_MTB_SWDEST_ISH_1 0x0000F000 +#define B_TRACE_HUB_MEM_MTB_SWDEST_ISH_2 0x000F0000 +#define B_TRACE_HUB_MEM_MTB_SWDEST_ISH_3 0x00F00000 +#define B_TRACE_HUB_MEM_MTB_SWDEST_AUDIO 0x0F000000 +#define B_TRACE_HUB_MEM_MTB_SWDEST_PMC 0xF0000000 +#define R_TRACE_HUB_MEM_MTB_SWDEST_2 0x10 +#define B_TRACE_HUB_MEM_MTB_SWDEST_FTH 0x0000000F +#define R_TRACE_HUB_MEM_MTB_SWDEST_3 0x14 +#define B_TRACE_HUB_MEM_MTB_SWDEST_MAESTRO 0x00000F00 +#define B_TRACE_HUB_MEM_MTB_SWDEST_MIPICAM 0x0F000000 +#define B_TRACE_HUB_MEM_MTB_SWDEST_AET 0xF0000000 +#define R_TRACE_HUB_MEM_MTB_SWDEST_4 0x18 +#define R_TRACE_HUB_MEM_MTB_MSC0CTL 0xA0100 +#define R_TRACE_HUB_MEM_MTB_MSC1CTL 0xA0200 +#define V_TRACE_HUB_MEM_MTB_MSCNMODE_DCI 0x2 +#define V_TRACE_HUB_MEM_MTB_MSCNMODE_DEBUG 0x3 +#define B_TRACE_HUB_MEM_MTB_MSCNLEN (BIT10 | BIT9 | BIT8) +#define B_TRACE_HUB_MEM_MTB_MSCNMODE (BIT5 | BIT4) +#define N_TRACE_HUB_MEM_MTB_MSCNMODE 0x4 +#define B_TRACE_HUB_MEM_MTB_MSCN_RD_HDR_OVRD BIT2 +#define B_TRACE_HUB_MEM_MTB_WRAPENN BIT1 +#define B_TRACE_HUB_MEM_MTB_MSCNEN BIT0 +#define R_TRACE_HUB_MEM_MTB_GTHSTAT 0xD4 +#define R_TRACE_HUB_MEM_MTB_SCR2 0xD8 +#define B_TRACE_HUB_MEM_MTB_SCR2_FCD BIT0 +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF2 BIT2 +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF3 BIT3 +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF4 BIT4 +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF5 BIT5 +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF6 BIT6 +#define B_TRACE_HUB_MEM_MTB_SCR2_FSEOFF7 BIT7 +#define R_TRACE_HUB_MEM_MTB_MSC0BAR 0xA0108 +#define R_TRACE_HUB_MEM_MTB_MSC0SIZE 0xA010C +#define R_TRACE_HUB_MEM_MTB_MSC1BAR 0xA0208 +#define R_TRACE_HUB_MEM_MTB_MSC1SIZE 0xA020C +#define R_TRACE_HUB_MEM_MTB_STREAMCFG1 0xA1000 +#define R_TRACE_HUB_MEM_MTB_SCR 0xC8 +#define R_TRACE_HUB_MEM_MTB_GTH_FREQ 0xCC +#define V_TRACE_HUB_MEM_MTB_SCR 0x00130000 +#define R_TRACE_HUB_MEM_CSR_MTB_SCRATCHPAD0 0xE0 +#define R_TRACE_HUB_MEM_CSR_MTB_SCRATCHPAD1 0xE4 +#define R_TRACE_HUB_MEM_CSR_MTB_SCRATCHPAD10 0xE40 +#define R_TRACE_HUB_MEM_MTB_CTPGCS 0x1C14 +#define B_TRACE_HUB_MEM_MTB_CTPEN BIT0 +#define V_TRACE_HUB_MEM_MTB_CHLCNT 0x80 +#define R_TRACE_HUB_MEM_CSR_MTB_TSUCTRL 0x2000 +#define B_TRACE_HUB_MEM_CSR_MTB_TSUCTRL_CTCRESYNC BIT0 + +#endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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16 Aug 2019 17:16:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319251" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:50 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 09/37] CoffeelakeSiliconPkg/Pch: Add Private include headers Date: Fri, 16 Aug 2019 17:15:35 -0700 Message-Id: <20190817001603.30632-10-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001013; bh=FsD73FPN/VuHD194h+RHB87CnuzsxtB+afCwAYNdKd8=; h=Cc:Date:From:Reply-To:Subject:To; b=lTmA64XJF68iHyq2VGxMtCAiGvtf+1J8EXeY4AL39KIFzuZjA70w0HGBjW1xV8LZ0Of 0PL7l8jawpVWZSfWldi1qEsrfJzW5j5wn9fafbgQe5uVtswTNFCv5Jm9Y1urPPdSshQHn nsMNnsl5o39JdgYEmRsy8O2NvMn3Y3G529g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds the following header files: * Pch/Include/Private Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx.h = | 16 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h = | 273 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoints.h = | 115 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h = | 92 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h = | 269 +++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h = | 58 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleResetHob.= h | 25 ++ 7 files changed, 848 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchL= pHsioDx.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLp= HsioDx.h new file mode 100644 index 0000000000..6c9d10e928 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/CnlPchLpHsioDx= .h @@ -0,0 +1,16 @@ +/** @file + CnlPchLp Dx HSIO Header File + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CNL_PCH_LP_HSIO_DX_H_ +#define _CNL_PCH_LP_HSIO_DX_H_ + +#define CNL_PCH_LP_HSIO_VER_DX 0x7 + + +extern UINT8 CnlPchLpChipsetInitTable_Dx[5072]; +extern UINT8 CnlPchLpChipsetInitTable_eDBC_Dx[4612]; +#endif //_CNL_PCH_LP_HSIO_DX_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConf= igHob.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigH= ob.h new file mode 100644 index 0000000000..5569da670d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchConfigHob.h @@ -0,0 +1,273 @@ +/** @file + The GUID definition for PchConfigHob + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_CONFIG_HOB_H_ +#define _PCH_CONFIG_HOB_H_ + +#include +#include +#include +#include +#include +#include + +extern EFI_GUID gPchConfigHobGuid; + +#pragma pack (push,1) + +/// +/// This structure contains the HOB which are related to PCH general confi= g. +/// +typedef struct { + /** + This member describes whether or not the Compatibility Revision ID (CR= ID) feature + of PCH should be enabled. 0: Disable; 1: Enable + **/ + UINT32 Crid : 1; + UINT32 RsvdBits0 : 31; ///< Reserved bits + /// + /// +} GENERAL_HOB; + +/// +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capabl= e devices in the platform. +/// +typedef struct { + UINT8 RsvdBytes[3]; + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the= RsvdSmbusAddressTable. + /** + Array of addresses reserved for non-ARP-capable SMBus devices. + **/ + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS]; +} SMBUS_HOB; + +/// +/// The INTERRUPT describes interrupt settings for PCH HOB. +/// +typedef struct { + UINT8 NumOfDevIntConfig; = ///< Number of entries in DevIntConfig table + UINT8 GpioIrqRoute; = ///< Interrupt routing for GPIO. Default is 14. + UINT8 Rsvd0[2]; = ///< Reserved bytes, align to multiple 4. + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFI= G]; ///< Array which stores PCH devices interrupts settings + UINT8 PxRcConfig[PCH_MAX_PXRC_CONFIG]; = ///< PCI interrupt routing for 8259 PIC controller +} INTERRUPT_HOB; + +/// +/// The CNVI_HOB block describes CNVi device. +/// +typedef struct { + UINT32 Mode : 1; ///< 0: Disabled, 1: A= uto + UINT32 RsvdBits0 : 31; +} CNVI_HOB; + +/** + The SERIAL_IO block provides the configurations to set the Serial IO con= trollers +**/ +typedef struct { + /** + 0: Disabled; + - Device is placed in D3 + - Gpio configuration is skipped + - Device will be disabled in PSF + - !important! If given device is Function 0 and not all other LP= SS functions on given device + are disabled, then PSF disabling is skipped. + PSF default will remain and device PCI CFG Space w= ill still be visible. + This is needed to allow PCI enumerator access func= tions above 0 in a multifunction device. + 1: Pci; + - Gpio pin configuration in native mode for each assigned pin + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl + - Device will be enabled in PSF + - Only Bar 0 will be enabled + 2: Acpi; + - Gpio pin configuration in native mode for each assigned pin + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl + - Device will be hidden in PSF and not available to PCI enumerat= or + - Both BARs are enabled, BAR1 becomes devices Pci config Space + @note Intel does not provide Windows SerialIo drivers for this mode + 3: Hidden; + Designated for Kernel Debug and Legacy UART configuartion, might= also be used for IO Expander on I2C + - Device is placed in D0 + - Gpio pin configuration in native mode for each assigned pin + RX/TX or RX/TX/CTS/RTS in case of UART depending UartHwFlowCtrl + - Device will be hidden in PSF and not available to PCI enumerat= or + - Both BARs are enabled, BAR1 becomes devices Pci config Space + - !important! In this mode UART will work in 16550 Legacy 8BIT M= ode, it's resources will be assigned to mother board through ACPI (PNP0C02) + @note Considering the PcdSerialIoUartDebugEnable and PcdSerialIoUartNu= mber for all SerialIo UARTx, + the PCD is more meaningful to represent the board design. It mea= ns, if PcdSerialIoUartDebugEnable is not 0, + the board is designed to use the SerialIo UART for debug message= and the PcdSerialIoUartNumber is dedicated + to be Debug UART usage. Therefore, it should grayout the option = from setup menu since no other options + available for this UART controller on this board, and also overr= ide the policy default accordingly. + While PcdSerialIoUartDebugEnable is 0, then it's allowed to conf= igure the UART controller by policy. + **/ + UINT8 DevMode[PCH_MAX_SERIALIO_CONTROLLERS]; + UINT32 DebugUartNumber : 2; ///< UART numb= er for debug purpose. 0:UART0, 1: UART1, 2:UART2 + UINT32 EnableDebugUartAfterPost : 1; ///< Enable de= bug UART controller after post. 0: disabled, 1: enabled + UINT32 RsvdBits0 : 29; +} SERIAL_IO_HOB; + + +/// +/// The PCH_PCIE_CONFIG block describes the expected configuration of the = PCH PCI Express controllers +/// +typedef struct { + /// + /// These members describe the configuration of each PCH PCIe root port. + /// + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS]; + /** + This member allows BIOS to control ICC PLL Shutdown by determining PCI= e devices are LTR capable + or leaving untouched. + - 0: Disable, ICC PLL Shutdown is determined by PCIe device LTR cap= ablility. + - To allow ICC PLL shutdown if all present PCIe devices are LTR capa= ble or if no PCIe devices are + presented for maximum power savings where possible. + - To disable ICC PLL shutdown when BIOS detects any non-LTR capable = PCIe device for ensuring device + functionality. + - 1: Enable, To allow ICC PLL shutdown even if some devices do not sup= port LTR capability. + **/ + UINT32 AllowNoLtrIccPllShutdown : 1; + UINT32 RsvdBits0 : 31; +} PCIERP_HOB; + +typedef struct { + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; = 1: Enable + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake in= itiated by a codec in Sx, 0: Disable; 1: Enable + UINT32 AudioLinkSndw1 : 1; ///< SoundWire1 link enablement: = 0: Disable; 1: Enable. Muxed with HDA + UINT32 AudioLinkSndw2 : 1; ///< SoundWire2 link enablement: = 0: Disable; 1: Enable. Muxed with SSP1 + UINT32 AudioLinkSndw3 : 1; ///< SoundWire3 link enablement: = 0: Disable; 1: Enable. Muxed with DMIC1 + UINT32 AudioLinkSndw4 : 1; ///< SoundWire4 link enablement: = 0: Disable; 1: Enable. Muxed with DMIC0 + UINT32 RsvdBits0 : 26; ///< Reserved bits +} HDAUDIO_HOB; + +typedef struct { + /// + /// This member describes whether or not the SATA controllers should be = enabled. 0: Disable; 1: Enable. + /// + UINT32 Enable : 1; + UINT32 TestMode : 1; ///< (Test)= 0: Disable; 1: Allow entrance to the PCH SATA test modes + UINT32 RsvdBits0 : 30; ///< Reserved = bits + /** + This member configures the features, property, and capability for each= SATA port. + **/ + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS]; + /** + This member describes the details of implementation of Intel RST for P= CIe Storage remapping (Intel RST Driver is required) + **/ + PCH_RST_PCIE_STORAGE_CONFIG RstPcieStorageRemap[PCH_MAX_RST_PCIE_STORA= GE_CR]; +} SATA_HOB; + +/// +/// The SCS_HOB block describes Storage and Communication Subsystem (SCS) = settings for PCH. +/// +typedef struct { + UINT32 ScsEmmcEnabled : 2; ///< Determine if eMM= C is enabled - 0: Disabled, 1: Enabled. + UINT32 ScsEmmcHs400Enabled : 1; ///< Determine eMMC H= S400 Mode if ScsEmmcEnabled - 0: Disabled, 1: Enabled + /** + Determine if HS400 Training is required, set to FALSE if Hs400 Data is= valid. 0: Disabled, 1: Enabled. + First Boot or CMOS clear, system boot with Default settings, set tunin= g required. + Subsequent Boots, Get Variable 'Hs400TuningData' + - if failed to get variable, set tuning required + - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxD= ataDll from variable. Set tuning not required. + **/ + UINT32 ScsEmmcHs400TuningRequired : 1; + UINT32 ScsEmmcHs400DllDataValid : 1; ///< Set if HS400 Tun= ing Data Valid + UINT32 ScsEmmcHs400DriverStrength : 3; ///< I/O driver stren= gth: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm + UINT32 ScsSdPowerEnableActiveHigh : 1; ///< Sd PWREN# active= high + UINT32 ScsSdCardEnabled : 1; ///< Sd card enabled + UINT32 RsvdBits : 22; +} SCS_HOB; + +/** + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of t= he PCH + for security requirement. +**/ +typedef struct { + UINT32 GlobalSmi : 1; + /** + (Test) Enable BIOS Interface Lock Down bit to prevent writes to= the Backup Control Register + Top Swap bit and the General Control and Status Registers Boot BIOS St= raps. 0: Disable; 1: Enable. + **/ + UINT32 BiosInterface : 1; + /** + Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in= the upper + and lower 128-byte bank of RTC RAM. 0: Disable; 1: Enable. + **/ + UINT32 RtcMemoryLock : 1; + /** + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:Reg= DCh[5]) + for the BIOS region protection. When it is enabled, the BIOS Region ca= n only be + modified from SMM after EndOfDxe protocol is installed. + Note: When BiosLock is enabled, platform code also needs to update to = take care + of BIOS modification (including SetVariable) in DXE or runtime phase a= fter + EndOfDxe protocol is installed. + Enable InSMM.STS (EISS) in SPI + If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be = '1' also + in order to write to BIOS regions of SPI Flash. If this EISS bit is cl= ear, + then the InSMM.STS is a don't care. + The BIOS must set the EISS bit while BIOS Guard support is enabled. + In recovery path, platform can temporary disable EISS for SPI programm= ing in + PEI phase or early DXE phase. + 0: Disable; 1: Enable. + **/ + UINT32 BiosLock : 1; + UINT32 RsvdBits : 28; +} LOCK_DOWN_HOB; + +/** + The PM_HOB block describes expected miscellaneous power management setti= ngs. + The PowerResetStatusClear field would clear the Power/Reset status bits,= please + set the bits if you want PCH Init driver to clear it, if you want to che= ck the + status later then clear the bits. +**/ +typedef struct { + UINT32 SlpS0VmRuntimeControl : 1; /// < SLP= _S0 Voltage Margining Runtime Control. 0: Disable; 1: Enable. + UINT32 SlpS0Vm070VSupport : 1; /// < SLP= _S0 0.70V Voltage Margining Support. 0: Disable; 1: Enable. + UINT32 SlpS0Vm075VSupport : 1; /// < SLP= _S0 0.75V Voltage Margining Support. 0: Disable; 1: Enable. + UINT32 PsOnEnable : 1; /// < Ind= icates if PS_ON support has been enabled, 0: Disable; 1: Enable. + UINT32 RsvdBits1 : 28; +} PM_HOB; + +/** + PCH Trace Hub HOB settings. +**/ +typedef struct { + UINT32 PchTraceHubMode : 2; // 0 =3D Disable; 1 =3D Targe= t Debugger mode; 2 =3D Host Debugger mode + UINT32 Rsvd1 : 30; // Reserved bytes +} PCH_TRACEHUB_HOB; + +/** + PCH eSPI HOB settings. +**/ +typedef struct { + UINT32 BmeMasterSlaveEnabled : 1; // 0 =3D BME disable; 1 =3D B= ME enable + UINT32 RsvdBits : 31; +} PCH_ESPI_HOB; + + +/// +/// Pch Config Hob +/// +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure for = gPchConfigHobGuid + GENERAL_HOB General; ///< Pch general HOB definition + INTERRUPT_HOB Interrupt; ///< Interrupt HOB definition + SERIAL_IO_HOB SerialIo; ///< Serial io HOB definition + PCIERP_HOB PcieRp; ///< PCIE root port HOB definition + SCS_HOB Scs; ///< Scs HOB definition + CNVI_HOB Cnvi; ///< Cnvi Hob definition + LOCK_DOWN_HOB LockDown; ///< Lock down HOB definition + PM_HOB Pm; ///< PM HOB definition + HDAUDIO_HOB HdAudio; ///< HD audio definition + SATA_HOB Sata[PCH_MAX_SATA_CONTROLLERS]; ///< SATA definition + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; + SMBUS_HOB Smbus; + PCH_TRACEHUB_HOB PchTraceHub; ///< PCH Trace Hub definition + PCH_ESPI_HOB Espi; ///< PCH eSPI definition + +} PCH_CONFIG_HOB; +#pragma pack (pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaE= ndpoints.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaE= ndpoints.h new file mode 100644 index 0000000000..faaff9f497 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHdaEndpoint= s.h @@ -0,0 +1,115 @@ +/** @file + Header file for PchHdaLib Endpoint descriptors. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_ENDPOINTS_H_ +#define _PCH_HDA_ENDPOINTS_H_ + +#include + +typedef enum { + HdaDmicX1 =3D 0, + HdaDmicX2, + HdaDmicX4, + HdaBtRender, + HdaBtCapture, + HdaI2sRender1, + HdaI2sRender2, + HdaI2sCapture, + HdaEndpointMax +} NHLT_ENDPOINT; + +typedef struct { + NHLT_ENDPOINT EndpointType; + UINT32 EndpointFormatsBitmask; + UINT32 EndpointDevicesBitmask; + BOOLEAN Enable; +} PCH_HDA_NHLT_ENDPOINTS; + +#define PCH_HDA_NHLT_TABLE_SIZE 0x2000 + +// Format bitmask +#define B_HDA_DMIC_2CH_48KHZ_16BIT_FORMAT BIT0 +#define B_HDA_DMIC_2CH_48KHZ_32BIT_FORMAT BIT1 +#define B_HDA_DMIC_4CH_48KHZ_16BIT_FORMAT BIT2 +#define B_HDA_DMIC_4CH_48KHZ_32BIT_FORMAT BIT3 +#define B_HDA_DMIC_1CH_48KHZ_16BIT_FORMAT BIT4 +#define B_HDA_BT_NARROWBAND_FORMAT BIT5 +#define B_HDA_BT_WIDEBAND_FORMAT BIT6 +#define B_HDA_BT_A2DP_FORMAT BIT7 +#define B_HDA_I2S_RTK274_RENDER_4CH_48KHZ_24BIT_FORMAT BIT8 +#define B_HDA_I2S_RTK274_CAPTURE_4CH_48KHZ_24BIT_FORMAT BIT9 +#define V_HDA_FORMAT_MAX 10 + +// Formats +extern CONST WAVEFORMATEXTENSIBLE Ch1_48kHz16bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz16bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz24bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch2_48kHz32bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch4_48kHz16bitFormat; +extern CONST WAVEFORMATEXTENSIBLE Ch4_48kHz32bitFormat; +extern CONST WAVEFORMATEXTENSIBLE NarrowbandFormat; +extern CONST WAVEFORMATEXTENSIBLE WidebandFormat; +extern CONST WAVEFORMATEXTENSIBLE A2dpFormat; + +// Format Config +extern CONST UINT32 DmicStereo16BitFormatConfig[]; +extern CONST UINT32 DmicStereo16BitFormatConfigSize; +extern CONST UINT32 DmicStereo32BitFormatConfig[]; +extern CONST UINT32 DmicStereo32BitFormatConfigSize; +extern CONST UINT32 DmicQuad16BitFormatConfig[]; +extern CONST UINT32 DmicQuad16BitFormatConfigSize; +extern CONST UINT32 DmicQuad32BitFormatConfig[]; +extern CONST UINT32 DmicQuad32BitFormatConfigSize; +extern CONST UINT32 DmicMono16BitFormatConfig[]; +extern CONST UINT32 DmicMono16BitFormatConfigSize; + +extern CONST UINT32 I2sRtk274Render4ch48kHz24bitFormatConfig[]; +extern CONST UINT32 I2sRtk274Render4ch48kHz24bitFormatConfigSize; +extern CONST UINT32 I2sRtk274Capture4ch48kHz24bitFormatConfig[]; +extern CONST UINT32 I2sRtk274Capture4ch48kHz24bitFormatConfigSize; +extern CONST UINT32 BtFormatConfig[]; +extern CONST UINT32 BtFormatConfigSize; + +// Endpoints +extern ENDPOINT_DESCRIPTOR HdaEndpointDmicX1; +extern ENDPOINT_DESCRIPTOR HdaEndpointDmicX2; +extern ENDPOINT_DESCRIPTOR HdaEndpointDmicX4; +extern ENDPOINT_DESCRIPTOR HdaEndpointBtRender; +extern ENDPOINT_DESCRIPTOR HdaEndpointBtCapture; +extern ENDPOINT_DESCRIPTOR HdaEndpointI2sRender; +extern ENDPOINT_DESCRIPTOR HdaEndpointI2sCapture; + +// Endpoint Config +extern CONST UINT8 DmicX1Config[]; +extern CONST UINT32 DmicX1ConfigSize; +extern CONST UINT8 DmicX2Config[]; +extern CONST UINT32 DmicX2ConfigSize; +extern CONST UINT8 DmicX4Config[]; +extern CONST UINT32 DmicX4ConfigSize; +extern CONST UINT8 BtConfig[]; +extern CONST UINT32 BtConfigSize; +extern CONST UINT8 I2sRender1Config[]; +extern CONST UINT32 I2sRender1ConfigSize; +extern CONST UINT8 I2sRender2Config[]; +extern CONST UINT32 I2sRender2ConfigSize; +extern CONST UINT8 I2sCaptureConfig[]; +extern CONST UINT32 I2sCaptureConfigSize; + +// Device Info bitmask +#define B_HDA_I2S_RENDER_DEVICE_INFO BIT0 +#define B_HDA_I2S_CAPTURE_DEVICE_INFO BIT1 + +// Device Info +extern CONST DEVICE_INFO I2sRenderDeviceInfo; +extern CONST DEVICE_INFO I2sCaptureDeviceInfo; + +// Oed Configuration +extern CONST UINT32 NhltConfiguration[]; +extern CONST UINT32 NhltConfigurationSize; + +#endif // _PCH_HDA_ENDPOINTS_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio= .h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h new file mode 100644 index 0000000000..860ed89f0d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchHsio.h @@ -0,0 +1,92 @@ +/** @file + Header file with all common HSIO information + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HSIO_H_ +#define _PCH_HSIO_H_ + +#define PCH_LANE_OWN_COMMON 0x10 +#define PCH_LANE_BDCAST 0x11 +#define PCH_HSIO_LANE_GROUP_NO 0x09 +#define PCH_HSIO_LANE_GROUP_COMMON_LANE 0x00 +#define PCH_HSIO_LANE_GROUP_PCIE 0x01 +#define PCH_HSIO_LANE_GROUP_DMI 0x02 +#define PCH_HSIO_LANE_GROUP_GBE 0x03 +#define PCH_HSIO_LANE_GROUP_USB3 0x04 +#define PCH_HSIO_LANE_GROUP_SATA 0x05 +#define PCH_HSIO_LANE_GROUP_SSIC 0x06 + + +/** + PCH HSIO ChipsetInit Version Information +**/ +typedef struct { + UINT16 BaseCrc; + UINT16 SusCrc; + UINT16 OemCrc; + UINT8 Version; + UINT8 Product; + UINT8 MetalLayer : 4; + UINT8 BaseLayer : 4; + UINT8 OemVersion; + UINT16 DebugMode : 1; + UINT16 OemCrcValid : 1; + UINT16 SusCrcValid : 1; + UINT16 BaseCrcValid : 1; + UINT16 Reserved : 12; +} PCH_HSIO_VER_INFO; + +#define PMC_DATA_CMD_SIZE ((12/sizeof(UINT16))-1) +#define PMC_DATA_DELAY_CMD_SIZE ((4/sizeof(UINT16))-1) + +#define RECORD_OFFSET(X, Y) ((X << 4) | Y) +/** + PCH HSIO ChipsetInit Command Field +**/ +typedef struct { + UINT8 Command : 3; + UINT8 Size : 5; + UINT8 Pid; + UINT8 OpCode; //PrivateControlWrite + UINT8 Bar; //0 + UINT8 Fbe; //First Byte Enable : 0x0F + UINT8 Fid; //0 + UINT16 Offset; + UINT32 Value; +} PCH_HSIO_CMD_FIELD; + +/** +PCH HSIO Delay XRAM Data +**/ +typedef struct { + UINT8 Command : 3; + UINT8 Size : 5; + UINT8 DelayPeriod; //(00h =3D 1us, 01h =3D 10us, 02h =3D 100us, ..., 07h= =3D 10s; others reserved) + UINT8 DelayCount; //(0 - 255); total delay =3D Delay period * Delay count + UINT8 Padding; +} PCH_HSIO_DELAY_CMD_FIELD; + +typedef enum { + Delay1us =3D 0x0, + Delay10us, + Delay100us, + Delay1ms, + Delay10ms, + Delay100ms, + Delay1s, + Delay10s +} PCH_HSIO_DELAY; + +/** +PCH PCIE PLL SSC Data +**/ +#define MAX_PCIE_PLL_SSC_PERCENT 20 + +#include + +#endif //_PCH_HSIO_H_ + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsA= reaDef.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAre= aDef.h new file mode 100644 index 0000000000..4617a01c0b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchNvsAreaDef.h @@ -0,0 +1,269 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // + // Define PCH NVS Area operatino region. + // + +#ifndef _PCH_NVS_AREA_DEF_H_ +#define _PCH_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + UINT16 PchSeries; ///< Offset 0 PC= H Series + UINT16 PchGeneration; ///< Offset 2 PC= H Generation + UINT16 PchStepping; ///< Offset 4 PC= H Stepping + UINT32 RpAddress[24]; ///< Offset 6 Ro= ot Port address 1 + ///< Offset 10 Ro= ot Port address 2 + ///< Offset 14 Ro= ot Port address 3 + ///< Offset 18 Ro= ot Port address 4 + ///< Offset 22 Ro= ot Port address 5 + ///< Offset 26 Ro= ot Port address 6 + ///< Offset 30 Ro= ot Port address 7 + ///< Offset 34 Ro= ot Port address 8 + ///< Offset 38 Ro= ot Port address 9 + ///< Offset 42 Ro= ot Port address 10 + ///< Offset 46 Ro= ot Port address 11 + ///< Offset 50 Ro= ot Port address 12 + ///< Offset 54 Ro= ot Port address 13 + ///< Offset 58 Ro= ot Port address 14 + ///< Offset 62 Ro= ot Port address 15 + ///< Offset 66 Ro= ot Port address 16 + ///< Offset 70 Ro= ot Port address 17 + ///< Offset 74 Ro= ot Port address 18 + ///< Offset 78 Ro= ot Port address 19 + ///< Offset 82 Ro= ot Port address 20 + ///< Offset 86 Ro= ot Port address 21 + ///< Offset 90 Ro= ot Port address 22 + ///< Offset 94 Ro= ot Port address 23 + ///< Offset 98 Ro= ot Port address 24 + UINT64 NHLA; ///< Offset 102 HD= -Audio NHLT ACPI address + UINT32 NHLL; ///< Offset 110 HD= -Audio NHLT ACPI length + UINT32 ADFM; ///< Offset 114 HD= -Audio DSP Feature Mask + UINT8 SWQ0; ///< Offset 118 HD= -Audio SoundWire Link #1 quirk mask + UINT8 SWQ1; ///< Offset 119 HD= -Audio SoundWire Link #2 quirk mask + UINT8 SWQ2; ///< Offset 120 HD= -Audio SoundWire Link #3 quirk mask + UINT8 SWQ3; ///< Offset 121 HD= -Audio SoundWire Link #4 quirk mask + UINT32 DSPM; ///< Offset 122 HD= -Audio DSP Stolen Memory Base Address + UINT32 SBRG; ///< Offset 126 SB= REG_BAR + UINT8 GEI0; ///< Offset 130 GP= IO GroupIndex mapped to GPE_DW0 + UINT8 GEI1; ///< Offset 131 GP= IO GroupIndex mapped to GPE_DW1 + UINT8 GEI2; ///< Offset 132 GP= IO GroupIndex mapped to GPE_DW2 + UINT8 GED0; ///< Offset 133 GP= IO DW part of group mapped to GPE_DW0 + UINT8 GED1; ///< Offset 134 GP= IO DW part of group mapped to GPE_DW1 + UINT8 GED2; ///< Offset 135 GP= IO DW part of group mapped to GPE_DW2 + UINT16 PcieLtrMaxSnoopLatency[24]; ///< Offset 136 PC= IE LTR max snoop Latency 1 + ///< Offset 138 PC= IE LTR max snoop Latency 2 + ///< Offset 140 PC= IE LTR max snoop Latency 3 + ///< Offset 142 PC= IE LTR max snoop Latency 4 + ///< Offset 144 PC= IE LTR max snoop Latency 5 + ///< Offset 146 PC= IE LTR max snoop Latency 6 + ///< Offset 148 PC= IE LTR max snoop Latency 7 + ///< Offset 150 PC= IE LTR max snoop Latency 8 + ///< Offset 152 PC= IE LTR max snoop Latency 9 + ///< Offset 154 PC= IE LTR max snoop Latency 10 + ///< Offset 156 PC= IE LTR max snoop Latency 11 + ///< Offset 158 PC= IE LTR max snoop Latency 12 + ///< Offset 160 PC= IE LTR max snoop Latency 13 + ///< Offset 162 PC= IE LTR max snoop Latency 14 + ///< Offset 164 PC= IE LTR max snoop Latency 15 + ///< Offset 166 PC= IE LTR max snoop Latency 16 + ///< Offset 168 PC= IE LTR max snoop Latency 17 + ///< Offset 170 PC= IE LTR max snoop Latency 18 + ///< Offset 172 PC= IE LTR max snoop Latency 19 + ///< Offset 174 PC= IE LTR max snoop Latency 20 + ///< Offset 176 PC= IE LTR max snoop Latency 21 + ///< Offset 178 PC= IE LTR max snoop Latency 22 + ///< Offset 180 PC= IE LTR max snoop Latency 23 + ///< Offset 182 PC= IE LTR max snoop Latency 24 + UINT16 PcieLtrMaxNoSnoopLatency[24]; ///< Offset 184 PC= IE LTR max no snoop Latency 1 + ///< Offset 186 PC= IE LTR max no snoop Latency 2 + ///< Offset 188 PC= IE LTR max no snoop Latency 3 + ///< Offset 190 PC= IE LTR max no snoop Latency 4 + ///< Offset 192 PC= IE LTR max no snoop Latency 5 + ///< Offset 194 PC= IE LTR max no snoop Latency 6 + ///< Offset 196 PC= IE LTR max no snoop Latency 7 + ///< Offset 198 PC= IE LTR max no snoop Latency 8 + ///< Offset 200 PC= IE LTR max no snoop Latency 9 + ///< Offset 202 PC= IE LTR max no snoop Latency 10 + ///< Offset 204 PC= IE LTR max no snoop Latency 11 + ///< Offset 206 PC= IE LTR max no snoop Latency 12 + ///< Offset 208 PC= IE LTR max no snoop Latency 13 + ///< Offset 210 PC= IE LTR max no snoop Latency 14 + ///< Offset 212 PC= IE LTR max no snoop Latency 15 + ///< Offset 214 PC= IE LTR max no snoop Latency 16 + ///< Offset 216 PC= IE LTR max no snoop Latency 17 + ///< Offset 218 PC= IE LTR max no snoop Latency 18 + ///< Offset 220 PC= IE LTR max no snoop Latency 19 + ///< Offset 222 PC= IE LTR max no snoop Latency 20 + ///< Offset 224 PC= IE LTR max no snoop Latency 21 + ///< Offset 226 PC= IE LTR max no snoop Latency 22 + ///< Offset 228 PC= IE LTR max no snoop Latency 23 + ///< Offset 230 PC= IE LTR max no snoop Latency 24 + UINT8 XHPC; ///< Offset 232 Nu= mber of HighSpeed ports implemented in XHCI controller + UINT8 XRPC; ///< Offset 233 Nu= mber of USBR ports implemented in XHCI controller + UINT8 XSPC; ///< Offset 234 Nu= mber of SuperSpeed ports implemented in XHCI controller + UINT8 XSPA; ///< Offset 235 Ad= dress of 1st SuperSpeed port + UINT32 HPTB; ///< Offset 236 HP= ET base address + UINT8 HPTE; ///< Offset 240 HP= ET enable + //SerialIo block + UINT8 SMD[12]; ///< Offset 241 Se= rialIo controller 0 mode + ///< Offset 242 Se= rialIo controller 1 mode + ///< Offset 243 Se= rialIo controller 2 mode + ///< Offset 244 Se= rialIo controller 3 mode + ///< Offset 245 Se= rialIo controller 4 mode + ///< Offset 246 Se= rialIo controller 5 mode + ///< Offset 247 Se= rialIo controller 6 mode + ///< Offset 248 Se= rialIo controller 7 mode + ///< Offset 249 Se= rialIo controller 8 mode + ///< Offset 250 Se= rialIo controller 9 mode + ///< Offset 251 Se= rialIo controller A mode + ///< Offset 252 Se= rialIo controller B mode + UINT8 SIR[12]; ///< Offset 253 Se= rialIo controller 0 irq number + ///< Offset 254 Se= rialIo controller 1 irq number + ///< Offset 255 Se= rialIo controller 2 irq number + ///< Offset 256 Se= rialIo controller 3 irq number + ///< Offset 257 Se= rialIo controller 4 irq number + ///< Offset 258 Se= rialIo controller 5 irq number + ///< Offset 259 Se= rialIo controller 6 irq number + ///< Offset 260 Se= rialIo controller 7 irq number + ///< Offset 261 Se= rialIo controller 8 irq number + ///< Offset 262 Se= rialIo controller 9 irq number + ///< Offset 263 Se= rialIo controller A irq number + ///< Offset 264 Se= rialIo controller B irq number + UINT64 SB0[12]; ///< Offset 265 Se= rialIo controller 0 BAR0 + ///< Offset 273 Se= rialIo controller 1 BAR0 + ///< Offset 281 Se= rialIo controller 2 BAR0 + ///< Offset 289 Se= rialIo controller 3 BAR0 + ///< Offset 297 Se= rialIo controller 4 BAR0 + ///< Offset 305 Se= rialIo controller 5 BAR0 + ///< Offset 313 Se= rialIo controller 6 BAR0 + ///< Offset 321 Se= rialIo controller 7 BAR0 + ///< Offset 329 Se= rialIo controller 8 BAR0 + ///< Offset 337 Se= rialIo controller 9 BAR0 + ///< Offset 345 Se= rialIo controller A BAR0 + ///< Offset 353 Se= rialIo controller B BAR0 + UINT64 SB1[12]; ///< Offset 361 Se= rialIo controller 0 BAR1 + ///< Offset 369 Se= rialIo controller 1 BAR1 + ///< Offset 377 Se= rialIo controller 2 BAR1 + ///< Offset 385 Se= rialIo controller 3 BAR1 + ///< Offset 393 Se= rialIo controller 4 BAR1 + ///< Offset 401 Se= rialIo controller 5 BAR1 + ///< Offset 409 Se= rialIo controller 6 BAR1 + ///< Offset 417 Se= rialIo controller 7 BAR1 + ///< Offset 425 Se= rialIo controller 8 BAR1 + ///< Offset 433 Se= rialIo controller 9 BAR1 + ///< Offset 441 Se= rialIo controller A BAR1 + ///< Offset 449 Se= rialIo controller B BAR1 + //end of SerialIo block + UINT8 SGIR; ///< Offset 457 GP= IO IRQ + UINT8 GPHD; ///< Offset 458 Hi= de GPIO ACPI device + UINT8 RstPcieStorageInterfaceType[3]; ///< Offset 459 RS= T PCIe Storage Cycle Router#1 Interface Type + ///< Offset 460 RS= T PCIe Storage Cycle Router#2 Interface Type + ///< Offset 461 RS= T PCIe Storage Cycle Router#3 Interface Type + UINT8 RstPcieStoragePmCapPtr[3]; ///< Offset 462 RS= T PCIe Storage Cycle Router#1 Power Management Capability Pointer + ///< Offset 463 RS= T PCIe Storage Cycle Router#2 Power Management Capability Pointer + ///< Offset 464 RS= T PCIe Storage Cycle Router#3 Power Management Capability Pointer + UINT8 RstPcieStoragePcieCapPtr[3]; ///< Offset 465 RS= T PCIe Storage Cycle Router#1 PCIe Capabilities Pointer + ///< Offset 466 RS= T PCIe Storage Cycle Router#2 PCIe Capabilities Pointer + ///< Offset 467 RS= T PCIe Storage Cycle Router#3 PCIe Capabilities Pointer + UINT16 RstPcieStorageL1ssCapPtr[3]; ///< Offset 468 RS= T PCIe Storage Cycle Router#1 L1SS Capability Pointer + ///< Offset 470 RS= T PCIe Storage Cycle Router#2 L1SS Capability Pointer + ///< Offset 472 RS= T PCIe Storage Cycle Router#3 L1SS Capability Pointer + UINT8 RstPcieStorageEpL1ssControl2[3]; ///< Offset 474 RS= T PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2 + ///< Offset 475 RS= T PCIe Storage Cycle Router#2 Endpoint L1SS Control Data2 + ///< Offset 476 RS= T PCIe Storage Cycle Router#3 Endpoint L1SS Control Data2 + UINT32 RstPcieStorageEpL1ssControl1[3]; ///< Offset 477 RS= T PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1 + ///< Offset 481 RS= T PCIe Storage Cycle Router#2 Endpoint L1SS Control Data1 + ///< Offset 485 RS= T PCIe Storage Cycle Router#3 Endpoint L1SS Control Data1 + UINT16 RstPcieStorageLtrCapPtr[3]; ///< Offset 489 RS= T PCIe Storage Cycle Router#1 LTR Capability Pointer + ///< Offset 491 RS= T PCIe Storage Cycle Router#2 LTR Capability Pointer + ///< Offset 493 RS= T PCIe Storage Cycle Router#3 LTR Capability Pointer + UINT32 RstPcieStorageEpLtrData[3]; ///< Offset 495 RS= T PCIe Storage Cycle Router#1 Endpoint LTR Data + ///< Offset 499 RS= T PCIe Storage Cycle Router#2 Endpoint LTR Data + ///< Offset 503 RS= T PCIe Storage Cycle Router#3 Endpoint LTR Data + UINT16 RstPcieStorageEpLctlData16[3]; ///< Offset 507 RS= T PCIe Storage Cycle Router#1 Endpoint LCTL Data + ///< Offset 509 RS= T PCIe Storage Cycle Router#2 Endpoint LCTL Data + ///< Offset 511 RS= T PCIe Storage Cycle Router#3 Endpoint LCTL Data + UINT16 RstPcieStorageEpDctlData16[3]; ///< Offset 513 RS= T PCIe Storage Cycle Router#1 Endpoint DCTL Data + ///< Offset 515 RS= T PCIe Storage Cycle Router#2 Endpoint DCTL Data + ///< Offset 517 RS= T PCIe Storage Cycle Router#3 Endpoint DCTL Data + UINT16 RstPcieStorageEpDctl2Data16[3]; ///< Offset 519 RS= T PCIe Storage Cycle Router#1 Endpoint DCTL2 Data + ///< Offset 521 RS= T PCIe Storage Cycle Router#2 Endpoint DCTL2 Data + ///< Offset 523 RS= T PCIe Storage Cycle Router#3 Endpoint DCTL2 Data + UINT16 RstPcieStorageRpDctl2Data16[3]; ///< Offset 525 RS= T PCIe Storage Cycle Router#1 RootPort DCTL2 Data + ///< Offset 527 RS= T PCIe Storage Cycle Router#2 RootPort DCTL2 Data + ///< Offset 529 RS= T PCIe Storage Cycle Router#3 RootPort DCTL2 Data + UINT32 RstPcieStorageUniqueTableBar[3]; ///< Offset 531 RS= T PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR + ///< Offset 535 RS= T PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR + ///< Offset 539 RS= T PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR + UINT32 RstPcieStorageUniqueTableBarValue[3]; ///< Offset 543 RS= T PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value + ///< Offset 547 RS= T PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR value + ///< Offset 551 RS= T PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR value + UINT32 RstPcieStorageUniquePbaBar[3]; ///< Offset 555 RS= T PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR + ///< Offset 559 RS= T PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR + ///< Offset 563 RS= T PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR + UINT32 RstPcieStorageUniquePbaBarValue[3]; ///< Offset 567 RS= T PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value + ///< Offset 571 RS= T PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR value + ///< Offset 575 RS= T PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR value + UINT32 RstPcieStorageRootPortNum[3]; ///< Offset 579 RS= T PCIe Storage Cycle Router#1 Root Port number + ///< Offset 583 RS= T PCIe Storage Cycle Router#2 Root Port number + ///< Offset 587 RS= T PCIe Storage Cycle Router#3 Root Port number + UINT8 EMH4; ///< Offset 591 eM= MC HS400 mode enabled + UINT8 EMDS; ///< Offset 592 eM= MC Driver Strength + UINT8 CpuSku; ///< Offset 593 CP= U SKU + UINT16 IoTrapAddress[4]; ///< Offset 594 + UINT8 IoTrapStatus[4]; ///< Offset 602 + UINT16 PMBS; ///< Offset 606 AC= PI IO BASE address + UINT32 PWRM; ///< Offset 608 PW= RM MEM BASE address + // Cnvi specific + UINT8 CnviMode; ///< Offset 612 CN= Vi mode + UINT32 RmrrCsmeBaseAddress; ///< Offset 613 RM= RR CSME Base Address + //Voltage Margining + UINT8 SlpS0VmRuntimeControl; ///< Offset 617 SL= P_S0 Voltage Margining Runtime Control + UINT8 SlpS0Vm070VSupport; ///< Offset 618 SL= P_S0 0.70V Voltage Margining Support + UINT8 SlpS0Vm075VSupport; ///< Offset 619 SL= P_S0 0.75V Voltage Margining Support + // PCH Trace Hub + UINT8 PchTraceHubMode; ///< Offset 620 PC= H Trace Hub Mode + // PCH PS_ON support + UINT8 PsOnEnable; ///< Offset 621 PC= H PS_ON enable + UINT32 TempRsvdMemBase; ///< Offset 622 Re= served memory base address for Temp MBAR + // + // These are for PchApciTablesSelfTest use + // + UINT8 LtrEnable[24]; ///< Offset 626 La= tency Tolerance Reporting Enable + ///< Offset 627 La= tency Tolerance Reporting Enable + ///< Offset 628 La= tency Tolerance Reporting Enable + ///< Offset 629 La= tency Tolerance Reporting Enable + ///< Offset 630 La= tency Tolerance Reporting Enable + ///< Offset 631 La= tency Tolerance Reporting Enable + ///< Offset 632 La= tency Tolerance Reporting Enable + ///< Offset 633 La= tency Tolerance Reporting Enable + ///< Offset 634 La= tency Tolerance Reporting Enable + ///< Offset 635 La= tency Tolerance Reporting Enable + ///< Offset 636 La= tency Tolerance Reporting Enable + ///< Offset 637 La= tency Tolerance Reporting Enable + ///< Offset 638 La= tency Tolerance Reporting Enable + ///< Offset 639 La= tency Tolerance Reporting Enable + ///< Offset 640 La= tency Tolerance Reporting Enable + ///< Offset 641 La= tency Tolerance Reporting Enable + ///< Offset 642 La= tency Tolerance Reporting Enable + ///< Offset 643 La= tency Tolerance Reporting Enable + ///< Offset 644 La= tency Tolerance Reporting Enable + ///< Offset 645 La= tency Tolerance Reporting Enable + ///< Offset 646 La= tency Tolerance Reporting Enable + ///< Offset 647 La= tency Tolerance Reporting Enable + ///< Offset 648 La= tency Tolerance Reporting Enable + ///< Offset 649 La= tency Tolerance Reporting Enable + UINT8 GBES; ///< Offset 650 Gb= E Support + UINT8 SataPortPresence; ///< Offset 651 Ho= lds information from SATA PCS register about SATA ports which recieved COMI= NIT from connected devices. + UINT8 SdPowerEnableActiveHigh; ///< Offset 652 SD= PWREN# active high indication + UINT8 EmmcEnabled; ///< Offset 653 Se= t to indicate that eMMC is enabled + UINT8 SdCardEnabled; ///< Offset 654 Se= t to indicate that SD card is enabled +} PCH_NVS_AREA; + +#pragma pack(pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstH= ob.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h new file mode 100644 index 0000000000..94a5e0fad2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/PchRstHob.h @@ -0,0 +1,58 @@ +/** @file + Definitions required to create RstHob + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_RST_HOB_ +#define _PCH_RST_HOB_ + +extern EFI_GUID gPchRstHobGuid; + +// +// This struct is used to record the fields that should be restored during= device wake up +// +typedef struct { + UINT8 PmCapPtr; + UINT8 PcieCapPtr; + UINT16 L1ssCapPtr; + UINT8 EndpointL1ssControl2; + UINT32 EndpointL1ssControl1; + UINT16 LtrCapPtr; + UINT32 EndpointLtrData; + UINT16 EndpointLctlData16; + UINT16 EndpointDctlData16; + UINT16 EndpointDctl2Data16; + UINT16 RootPortDctl2Data16; +} SAVED_DEVICE_CONFIG_SPACE; + +// +// This structure is used to record the result of PCIe storageremapping fo= r each cycle router +// +typedef struct { + UINT8 RootPortNum; = // Indicates the root port number with RST PCIe Storage Remapping remapping= supported and PCIe storage device plugged on, numbering is 0-based + UINT8 DeviceInterface; = // Indicates the interface of the PCIe storage device (AHCI or NVMe) + UINT32 EndPointUniqueMsixTableBar; = // Records the PCIe storage device's MSI-X Table BAR if it supports unique = MSI-X Table BAR + UINT32 EndPointUniqueMsixTableBarValue; = // Records the PCIe storage device's MSI-X Table BAR value if it supports u= nique MSI-X Table BAR + UINT32 EndPointUniqueMsixPbaBar; = // Records the PCIe storage device's MSI-X PBA BAR if it supports unique MS= I-X PBA BAR + UINT32 EndPointUniqueMsixPbaBarValue; = // Records the PCIe storage device's MSI-X PBA BAR value if it supports uni= que MSI-X PBA BAR +} RST_CR_CONFIGURATION; + +// +// Passes to DXE results of PCIe storage remapping +// +typedef struct { + // + // Stores configuration information about cycle router + // + RST_CR_CONFIGURATION RstCrConfiguration[PCH_MAX_RST_PCIE_STORAGE_CR]; + + // + // Saved fields from hidden device config space to be used later by RST = driver + // + SAVED_DEVICE_CONFIG_SPACE SavedRemapedDeviceConfigSpace[PCH_MAX_RST_PCI= E_STORAGE_CR]; +} PCH_RST_HOB; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiSched= uleResetHob.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiSc= heduleResetHob.h new file mode 100644 index 0000000000..7a92a509b4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/SiScheduleRese= tHob.h @@ -0,0 +1,25 @@ +/** @file + This file contains definitions of Si Schedule Reset HOB. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_SCHEDULE_RESET_HOB_H_ +#define _SI_SCHEDULE_RESET_HOB_H_ + +#include + +/** + This structure is used to provide information about PCH Resets +**/ +typedef struct { + EFI_RESET_TYPE ResetType; + PCH_RESET_DATA ResetData; +} SI_SCHEDULE_RESET_HOB; + +extern EFI_GUID gSiScheduleResetHobGuid; + +#endif // _SI_SCHEDULE_RESET_HOB_H_ + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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16 Aug 2019 17:16:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319255" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:50 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 10/37] CoffeelakeSiliconPkg/Pch: Add Private/Library include headers Date: Fri, 16 Aug 2019 17:15:36 -0700 Message-Id: <20190817001603.30632-11-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001014; bh=HJSfT89jcflQ9PSw+ewHKU6HQsGoCocrlTv86fqe6/0=; h=Cc:Date:From:Reply-To:Subject:To; b=Zp2ocuhvH9qb8DpGE8p2l10u3dhkmaPWXPu26oyLU7J3nuZ94Zsxu4PwALG69l9mNhc nyTHQu8qD4xyInVZdTRbn9CPuVJnR/XCEJCPtYTOkBMw3niEh/EsXWKdMN9xcjCBjCpEs tg+0r5OcAGujCnlXsl078qneatUPkYTjpQM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds the following header files: * Pch/Include/Private/Library Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePchHdaNh= lt.h | 134 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHelpers= Lib.h | 97 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioNameBuf= ferLib.h | 25 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPrivate= Lib.h | 1061 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMasterCo= mmonLib.h | 288 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmiLib.h= | 344 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHdaLib.h= | 56 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchInitComm= onLib.h | 100 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPciExpre= ssHelpersLib.h | 371 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsfPriva= teLib.h | 578 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmbusCom= monLib.h | 98 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpiCommo= nLib.h | 366 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPchDmiLi= b.h | 25 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPrivateL= ib.h | 706 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiScheduleR= esetLib.h | 48 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPchPriva= teLib.h | 28 + 16 files changed, 4325 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /DxePchHdaNhlt.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/L= ibrary/DxePchHdaNhlt.h new file mode 100644 index 0000000000..9d8e34eb0d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/DxePch= HdaNhlt.h @@ -0,0 +1,134 @@ +/** @file + Header file for DxePchHdaLib - NHLT structure definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_PCH_HDA_NHLT_H_ +#define _DXE_PCH_HDA_NHLT_H_ + +#include + +// +// ACPI support protocol instance signature definition. +// +#define NHLT_ACPI_TABLE_SIGNATURE SIGNATURE_32 ('N', 'H', 'L', 'T') + +// MSFT defined structures +#define SPEAKER_FRONT_LEFT 0x1 +#define SPEAKER_FRONT_RIGHT 0x2 +#define SPEAKER_FRONT_CENTER 0x4 +#define SPEAKER_BACK_LEFT 0x10 +#define SPEAKER_BACK_RIGHT 0x20 + +#define KSAUDIO_SPEAKER_MONO (SPEAKER_FRONT_CENTER) +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT) +#define KSAUDIO_SPEAKER_QUAD (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT |= SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT) + +#define WAVE_FORMAT_EXTENSIBLE 0xFFFE /* Microsoft */ +#define KSDATAFORMAT_SUBTYPE_PCM \ + {0x00000001, 0x0000, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, = 0x9b, 0x71}} + +#pragma pack (push, 1) + +typedef struct { + UINT16 wFormatTag; + UINT16 nChannels; + UINT32 nSamplesPerSec; + UINT32 nAvgBytesPerSec; + UINT16 nBlockAlign; + UINT16 wBitsPerSample; + UINT16 cbSize; +} WAVEFORMATEX; + +typedef struct { + WAVEFORMATEX Format; + union { + UINT16 wValidBitsPerSample; + UINT16 wSamplesPerBlock; + UINT16 wReserved; + } Samples; + UINT32 dwChannelMask; + GUID SubFormat; +} WAVEFORMATEXTENSIBLE; + +// +// List of supported link type. +// +enum NHLT_LINK_TYPE +{ + HdaNhltLinkHd =3D 0, + HdaNhltLinkDsp =3D 1, + HdaNhltLinkDmic =3D 2, + HdaNhltLinkSsp =3D 3, + HdaNhltLinkInvalid +}; + +// +// List of supported device type. +// +enum NHLT_DEVICE_TYPE +{ + HdaNhltDeviceBt =3D 0, + HdaNhltDeviceDmic =3D 1, + HdaNhltDeviceI2s =3D 4, + HdaNhltDeviceInvalid +}; + +typedef struct { + UINT32 CapabilitiesSize; + UINT8 Capabilities[1]; +} SPECIFIC_CONFIG; + +typedef struct { + WAVEFORMATEXTENSIBLE Format; + SPECIFIC_CONFIG FormatConfiguration; +} FORMAT_CONFIG; + +typedef struct { + UINT8 FormatsCount; + FORMAT_CONFIG FormatsConfiguration[1]; +} FORMATS_CONFIG; + +typedef struct { + UINT8 DeviceId[16]; + UINT8 DeviceInstanceId; + UINT8 DevicePortId; +} DEVICE_INFO; + +typedef struct { + UINT8 DeviceInfoCount; + DEVICE_INFO DeviceInformation[1]; +} DEVICES_INFO; + +typedef struct { + UINT32 EndpointDescriptorLength; + UINT8 LinkType; + UINT8 InstanceId; + UINT16 HwVendorId; + UINT16 HwDeviceId; + UINT16 HwRevisionId; + UINT32 HwSubsystemId; + UINT8 DeviceType; + UINT8 Direction; + UINT8 VirtualBusId; + SPECIFIC_CONFIG EndpointConfig; + FORMATS_CONFIG FormatsConfig; + DEVICES_INFO DevicesInformation; +} ENDPOINT_DESCRIPTOR; + +// +// High Level Table structure +// +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'} + UINT8 EndpointCount; // Actual number of endpoin= ts + ENDPOINT_DESCRIPTOR EndpointDescriptors[1]; + SPECIFIC_CONFIG OedConfiguration; +} NHLT_ACPI_TABLE; + +#pragma pack (pop) + +#endif // _DXE_PCH_HDA_NHLT_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /GpioHelpersLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/= Library/GpioHelpersLib.h new file mode 100644 index 0000000000..9e0658331f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioHe= lpersLib.h @@ -0,0 +1,97 @@ +/** @file + Header file for GPIO Helpers Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_HELPERS_LIB_H_ +#define _GPIO_HELPERS_LIB_H_ + +#include + +/** + This procedure stores GPIO pad unlock information + + @param[in] GpioPad GPIO pad + @param[in] GpioLockConfig GPIO Lock Configuration + + @retval Status +**/ +EFI_STATUS +GpioStoreUnlockData ( + IN GPIO_PAD GpioPad, + IN GPIO_LOCK_CONFIG GpioLockConfig + ); + +/** + This procedure stores GPIO group data about pads which PadConfig needs t= o be unlocked. + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLock DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: Skip, 1: Leave unlocked + + @retval Status +**/ +EFI_STATUS +GpioStoreGroupDwUnlockPadConfigData ( + IN UINT32 GroupIndex, + IN UINT32 DwNum, + IN UINT32 UnlockedPads + ); + +/** + This procedure stores GPIO group data about pads which Output state need= s to be unlocked. + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLock DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: Skip, 1: Leave unlocked + + @retval Status +**/ +EFI_STATUS +GpioStoreGroupDwUnlockOutputData ( + IN UINT32 GroupIndex, + IN UINT32 DwNum, + IN UINT32 UnlockedPads + ); + +/** + This procedure will get GPIO group data with pads, which PadConfig is su= pposed to be left unlock + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @retval UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: to be locked, 1: Leave un= locked +**/ +UINT32 +GpioGetGroupDwUnlockPadConfigMask ( + IN UINT32 GroupIndex, + IN UINT32 DwNum + ); + +/** + This procedure will get GPIO group data with pads, which Output is suppo= sed to be left unlock + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @retval UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: to be locked, 1: Leave un= locked +**/ +UINT32 +GpioGetGroupDwUnlockOutputMask ( + IN UINT32 GroupIndex, + IN UINT32 DwNum + ); +#endif // _GPIO_HELPERS_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /GpioNameBufferLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Priva= te/Library/GpioNameBufferLib.h new file mode 100644 index 0000000000..a6ab42e4d5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioNa= meBufferLib.h @@ -0,0 +1,25 @@ +/** @file + Header file for GpioMemLib. This library provides GpioLib with static me= mory to hold GpioName. + Static memory is handled differently in PEI and DXE phase. For PEI pre m= em we use private HOB to store + gpio name since .data section is read only. For PEI post mem and DXE sim= ple static buffer is used. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_NAME_BUFFER_LIB_H_ +#define _GPIO_NAME_BUFFER_LIB_H_ + +#define GPIO_NAME_LENGTH_MAX 32 + +/** + Returns pointer to the global buffer to be used by GpioNamesLib + + @retval CHAR8* Pointer to the buffer +**/ +CHAR8* +GpioGetStaticNameBuffer ( + VOID + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /GpioPrivateLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/= Library/GpioPrivateLib.h new file mode 100644 index 0000000000..245618ff6d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/GpioPr= ivateLib.h @@ -0,0 +1,1061 @@ +/** @file + Header file for GpioPrivateLib. + All function in this library is available for PEI, DXE, and SMM, + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_PRIVATE_LIB_H_ +#define _GPIO_PRIVATE_LIB_H_ + +#include +#include + +// +// Structure for native pin data +// +typedef struct { + GPIO_PAD Pad; + GPIO_PAD_MODE Mode; +} GPIO_PAD_NATIVE_FUNCTION; + +// +// Below defines are based on GPIO_CONFIG structure fields +// +#define B_GPIO_PAD_MODE_MASK 0xF +#define N_GPIO_PAD_MODE_BIT_POS 0 +#define B_GPIO_HOSTSW_OWN_MASK 0x3 +#define N_GPIO_HOSTSW_OWN_BIT_POS 0 +#define B_GPIO_DIRECTION_MASK 0x1F +#define B_GPIO_DIRECTION_DIR_MASK 0x7 +#define N_GPIO_DIRECTION_DIR_BIT_POS 0 +#define B_GPIO_DIRECTION_INV_MASK 0x18 +#define N_GPIO_DIRECTION_INV_BIT_POS 3 +#define B_GPIO_OUTPUT_MASK 0x3 +#define N_GPIO_OUTPUT_BIT_POS 0 +#define N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS 0 +#define N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS 5 +#define B_GPIO_RESET_CONFIG_RESET_MASK 0x3F +#define N_GPIO_RESET_CONFIG_OLD_RESET_TYPE BIT1 +#define B_GPIO_RESET_CONFIG_OLD_RESET_MASK 0xF +#define N_GPIO_RESET_CONFIG_RESET_BIT_POS 0 +#define B_GPIO_RESET_CONFIG_GPD_RESET_MASK (BIT5 | BIT4) +#define B_GPIO_RESET_CONFIG_GPP_RESET_MASK (BIT3 | BIT2) +#define N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS 0 +#define N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS 0 + +// +// Structure for storing information about registers offset, community, +// maximal pad number for available groups +// +typedef struct { + PCH_SBI_PID Community; + UINT16 PadOwnOffset; + UINT16 HostOwnOffset; + UINT16 GpiIsOffset; + UINT16 GpiIeOffset; + UINT16 GpiGpeStsOffset; + UINT16 GpiGpeEnOffset; + UINT16 SmiStsOffset; + UINT16 SmiEnOffset; + UINT16 NmiStsOffset; + UINT16 NmiEnOffset; + UINT16 PadCfgLockOffset; + UINT16 PadCfgLockTxOffset; + UINT16 PadCfgOffset; + UINT16 PadPerGroup; +} GPIO_GROUP_INFO; + +// +// If in GPIO_GROUP_INFO structure certain register doesn't exist +// it will have value equal to NO_REGISTER_FOR_PROPERTY +// +#define NO_REGISTER_FOR_PROPERTY 0xFFFF + +/** + This procedure will retrieve address and length of GPIO info table + + @param[out] GpioGroupInfoTableLength Length of GPIO group table + + @retval Pointer to GPIO group table +**/ +CONST GPIO_GROUP_INFO* +GpioGetGroupInfoTable ( + OUT UINT32 *GpioGroupInfoTableLength + ); + +typedef struct { + CONST CHAR8* GpioGroupPrefix; + CONST GPIO_PAD FirstUniqueGpio; + CONST CHAR8** GroupUniqueNames; + CONST UINT32 UniqueNamesTableSize; +} GPIO_GROUP_NAME_INFO; + +// +// Helper macros for initializing GPIO_GROUP_NAME_INFO structures +// +#define GPIO_GROUP_NAME(GroupName,FirstUniqueGpio,GroupUniqueNamesTable) \ + {GroupName, FirstUniqueGpio, GroupUniqueNamesTable, ARRAY_SIZE (GroupUni= queNamesTable)} + +#define GPIO_GROUP_NAME_BASIC(GroupName) \ + {GroupName, 0, NULL, 0} + +/** + Returns GPIO_GROUP_NAME_INFO corresponding to the give GpioPad + + @param[in] GroupIndex Group index + + @retval GPIO_GROUP_NAME_INFO* Pointer to the GPIO_GROUP_NAME_INFO + @retval NULL If no group descriptor was found +**/ +CONST +GPIO_GROUP_NAME_INFO* +GpioGetGroupNameInfo ( + IN UINT32 GroupIndex + ); + +/** + Get GPIO Chipset ID specific to PCH generation and series +**/ +UINT32 +GpioGetThisChipsetId ( + VOID + ); + +/** + This procedure is used to check if GpioPad is valid for certain chipset + + @param[in] GpioPad GPIO pad + + @retval TRUE This pin is valid on this chipset + FALSE Incorrect pin +**/ +BOOLEAN +GpioIsCorrectPadForThisChipset ( + IN GPIO_PAD GpioPad + ); + +/** + Generates GPIO name from GpioPad + This function returns pointer to the static buffer. + + @param[in] GpioPad GpioPad + + @retval CHAR8* Pointer to the GPIO name +**/ +CHAR8* +GpioName ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will get value of selected gpio register + + @param[in] Group GPIO group number + @param[in] Offset GPIO register offset + @param[out] RegVal Value of gpio register + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetReg ( + IN GPIO_GROUP Group, + IN UINT32 Offset, + OUT UINT32 *RegVal + ); + +/** + This procedure will set value of selected gpio register + + @param[in] Group GPIO group number + @param[in] Offset GPIO register offset + @param[in] RegVal Value of gpio register + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetReg ( + IN GPIO_GROUP Group, + IN UINT32 Offset, + IN UINT32 RegVal + ); + +/** + This procedure is used by PchSmiDispatcher and will return information + needed to register GPI SMI. + + @param[in] Index GPI SMI number + @param[out] GpioPin GPIO pin + @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi R= egisters + @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register + @param[out] GpiSmiStsRegAddress Address of GPI SMI status register + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadAndSmiRegs ( + IN UINT32 Index, + OUT GPIO_PAD *GpioPin, + OUT UINT8 *GpiSmiBitOffset, + OUT UINT32 *GpiHostSwOwnRegAddress, + OUT UINT32 *GpiSmiStsRegAddress + ); + +/** + This procedure will set GPIO Driver IRQ number + + @param[in] Irq Irq number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid IRQ number +**/ +EFI_STATUS +GpioSetIrq ( + IN UINT8 Irq + ); + +/** + This function provides GPIO Community PortIDs + + @param[out] NativePinsTable Table with GPIO COMMx SBI Por= tIDs + + @retval Number of communities +**/ +UINT32 +GpioGetComSbiPortIds ( + OUT PCH_SBI_PID **GpioComSbiIds + ); + +/** + This procedure will perform special handling of GPP_A_12. + + @param[in] None + + @retval None +**/ +VOID +GpioA12SpecialHandling ( + VOID + ); + +// +// Structure which stores information needed to map GPIO Group +// to 1-Tier GPE. Configuration is needed both in PMC and GPIO IP. +// Because GPE_DWx can handle only 32 pins only single double word can +// be mapped at a time. Each DW for a group has different configuration in= PMC and GPIO +// +typedef struct { + GPIO_GROUP Group; + UINT8 GroupDw; + UINT8 PmcGpeDwxVal; + UINT8 GpioGpeDwxVal; +} GPIO_GROUP_TO_GPE_MAPPING; + +/** + Get information for GPIO Group required to program GPIO and PMC for desi= red 1-Tier GPE mapping + + @param[out] GpioGroupToGpeMapping Table with GPIO Group to GPE ma= pping + @param[out] GpioGroupToGpeMappingLength GPIO Group to GPE mapping table= length +**/ +VOID +GpioGetGroupToGpeMapping ( + OUT GPIO_GROUP_TO_GPE_MAPPING **GpioGroupToGpeMapping, + OUT UINT32 *GpioGroupToGpeMappingLength + ); + +/** + This procedure will return Port ID of GPIO Community from GpioPad + + @param[in] GpioPad GpioPad + + @retval GpioCommunityPortId Port ID of GPIO Community +**/ +UINT8 +GpioGetGpioCommunityPortIdFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will return PadCfg address from GpioPad + + @param[in] GpioPad GpioPad + + @retval GpioPadCfgAddress PadCfg Address of GpioPad +**/ +UINT32 +GpioGetGpioPadCfgAddressFromGpioPad ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure is used to unlock all GPIO pads. + This function can only be called when platform is still in HOSTIA_BOOT_S= AI. +**/ +VOID +GpioUnlockAllPads ( + VOID + ); + +/** + This procedure will check if GpioPad is owned by host. + + @param[in] GpioPad GPIO pad + + @retval TRUE GPIO pad is owned by host + @retval FALSE GPIO pad is not owned by host and should not be= used with GPIO lib API +**/ +BOOLEAN +GpioIsPadHostOwned ( + IN GPIO_PAD GpioPad + ); + + +/** + This procedure will check if GpioPad argument is valid. + Function will check below conditions: + - GpioPad represents a pad for current PCH + - GpioPad belongs to valid GpioGroup + - GPIO PadNumber is not greater than number of pads for this group + + @param[in] GpioPad GPIO pad + + @retval TRUE GPIO pad is valid and can be used with GPIO lib= API + @retval FALSE GPIO pad is invalid and cannot be used with GPI= O lib API +**/ +BOOLEAN +GpioIsPadValid ( + IN GPIO_PAD GpioPad + ); + +/** + This procedure will read GPIO Pad Configuration register + + @param[in] GpioPad GPIO pad + @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1 + + @retval PadCfgRegValue PADCFG_DWx value +**/ +UINT32 +GpioReadPadCfgReg ( + IN GPIO_PAD GpioPad, + IN UINT8 DwReg + ); + +/** + This procedure will write or read GPIO Pad Configuration register + + @param[in] GpioPad GPIO pad + @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1 + @param[in] PadCfgAndMask Mask to be AND'ed with PADCFG reg value + @param[in] PadCfgOrMask Mask to be OR'ed with PADCFG reg value + + @retval none +**/ +VOID +GpioWritePadCfgReg ( + IN GPIO_PAD GpioPad, + IN UINT8 DwReg, + IN UINT32 PadCfgAndMask, + IN UINT32 PadCfgOrMask + ); + +/** + This procedure will set GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadMode ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadModeValue + ); + +/** + This procedure will get GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadMode ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_MODE *PadModeValue + ); + +/** + This procedure will check if group is within DeepSleepWell. + + @param[in] Group GPIO Group + + @retval GroupWell TRUE: This is DSW Group + FALSE: This is not DSW Group +**/ +BOOLEAN +GpioIsDswGroup ( + IN GPIO_GROUP Group + ); + +/** + The function performs GPIO Power Management programming. +**/ +VOID +GpioConfigurePm ( + VOID + ); + +/** + This function sets SerialIo I2C controller pins into native mode + + @param[in] SerialIoI2cControllerNumber I2C controller + @param[in] GpioTermination GPIO termination type + + @retval Status +**/ +EFI_STATUS +GpioEnableSerialIoI2c ( + IN UINT32 SerialIoI2cControllerNumber, + IN GPIO_ELECTRICAL_CONFIG GpioTermination + ); + +/** + This function sets SerialIo UART controller pins into native mode + + @param[in] SerialIoUartControllerNumber UART controller + @param[in] HardwareFlowControl Hardware Flow control + @param[in] PinMuxing UART controller pin muxing + + @retval Status +**/ +EFI_STATUS +GpioEnableSerialIoUart ( + IN UINT32 SerialIoUartControllerNumber, + IN BOOLEAN HardwareFlowControl, + IN UINT32 PinMuxing + ); + +/** + This function sets SerialIo SPI controller pins into native mode + + @param[in] SerialIoSpiControllerNumber SPI controller + + @retval Status +**/ +EFI_STATUS +GpioEnableSerialIoSpi ( + IN UINT32 SerialIoSpiControllerNumber + ); + +/** + This function sets ISH I2C controller pins into native mode + + @param[in] IshI2cControllerNumber I2C controller + + @retval Status +**/ +EFI_STATUS +GpioEnableIshI2c ( + IN UINT32 IshI2cControllerNumber + ); + +/** + This function sets ISH UART controller pins into native mode + + @param[in] IshUartControllerNumber UART controller + + @retval Status +**/ +EFI_STATUS +GpioEnableIshUart ( + IN UINT32 IshUartControllerNumber + ); + +/** + This function sets ISH SPI controller pins into native mode + + @param[in] IshSpiControllerNumber SPI controller + + @retval Status +**/ +EFI_STATUS +GpioEnableIshSpi ( + IN UINT32 IshSpiControllerNumber + ); + +/** + This function sets ISH GP pin into native mode + + @param[in] IshGpPinNumber ISH GP pin number + + @retval Status +**/ +EFI_STATUS +GpioEnableIshGpPin ( + IN UINT32 IshGpPinNumber + ); + +/** + This function sets SCS SD card controller pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableScsSdCard ( + VOID + ); + +/** + This function enables SCS SD Card controller card detect pin + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableScsSdCardDetect ( + VOID + ); + +/** + This function sets SCS eMMC controller pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableScsEmmc ( + VOID + ); + +/** + This function sets HDA Link pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaLink ( + VOID + ); + +/** + This function sets HDA DMIC pins into native mode + + @param[in] DmicNumber DMIC number + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaDmic ( + IN UINT32 DmicNumber + ); + +/** + This function sets HDA SSP interface pins into native mode + + @param[in] SspInterfaceNumber SSPx interface number + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaSsp ( + IN UINT32 SspInterfaceNumber + ); + +/** + This function sets HDA SSP Master Clock into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaSspMasterClock ( + VOID + ); + +/** + This function sets HDA SoundWire interface pins into native mode + + @param[in] SndwInterfaceNumber SNDWx interface number + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaSndw ( + IN UINT32 SndwInterfaceNumber + ); + +/** + This function sets SMBUS controller pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableSmbus ( + VOID + ); + +/** + This function sets SMBUS ALERT pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableSmbusAlert ( + VOID + ); + +/** + This function enables USB OverCurrent pins by setting + USB2 OCB pins into native mode + + @param[in] OcPinNumber USB OC pin number + + @retval Status +**/ +EFI_STATUS +GpioEnableUsbOverCurrent ( + IN UINTN OcPinNumber + ); + +/** + This function sets SATA DevSlp pins into native mode + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + + @retval Status +**/ +EFI_STATUS +GpioEnableSataDevSlpPin ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort + ); + +/** + This function checks if SataDevSlp pin is in native mode + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port + @param[out] DevSlpPad DevSlpPad + This is an optional parameter and may be= NULL. + + @retval TRUE DevSlp is in native mode + FALSE DevSlp is not in native mode +**/ +BOOLEAN +GpioIsSataDevSlpPinEnabled ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort, + OUT GPIO_PAD *DevSlpPad OPTIONAL + ); + +/** + This function sets SATAGPx pin into native mode + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + + @retval Status +**/ +EFI_STATUS +GpioEnableSataGpPin ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort + ); + +/** + This function provides SATA GP pin data + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + @param[out] NativePin SATA GP pin +**/ +VOID +GpioGetSataGpPin ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort, + OUT GPIO_PAD_NATIVE_FUNCTION *NativePin + ); + +/** + This function sets SATA LED pin into native mode. SATA LED indicates + SATA controller activity + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableSataLed ( + VOID + ); + +/** + Returns pad for given CLKREQ# index. + + @param[in] ClkreqIndex CLKREQ# number + + @return CLKREQ# pad. +**/ +GPIO_PAD +GpioGetClkreqPad ( + IN UINT32 ClkreqIndex + ); + +/** + Enables CLKREQ# pad in native mode. + + @param[in] ClkreqIndex CLKREQ# number + + @return none +**/ +VOID +GpioEnableClkreq ( + IN UINT32 ClkreqIndex + ); + +/** + This function sets PCHHOT pin into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnablePchHot ( + VOID + ); + +/** + This function sets VRALERTB pin into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableVrAlert ( + VOID + ); + +/** + This function sets CPU GP pins into native mode + + @param[in] CpuGpPinNum CPU GP pin number + + @retval Status +**/ +EFI_STATUS +GpioEnableCpuGpPin ( + IN UINT32 CpuGpPinNum + ); + +/** +This function sets CPU C10 Gate pins into native mode + +@retval Status +**/ +EFI_STATUS +GpioEnableCpuC10GatePin ( + VOID + ); + +// +// DDSP_HPD pins +// +typedef enum { + GpioDdspHpd0 =3D 0x00, + GpioDdspHpd1 =3D 0x01, + GpioDdspHpd2 =3D 0x02, + GpioDdspHpd3 =3D 0x03, + GpioDdspHpd4 =3D 0x04, + GpioDdspHpdA =3D 0x10, + GpioDdspHpdB =3D 0x11, + GpioDdspHpdC =3D 0x12 +} GPIO_DDSP_HPD; + +/** + This function sets DDSP_HPDx pin into native mode + + @param[in] DdspHpdPin DDSP_HPDx pin + + @retval Status +**/ +EFI_STATUS +GpioEnableDpHotPlugDetect ( + IN GPIO_DDSP_HPD DdspHpdPin + ); + +/** + This function sets HPD, VDDEN, BKLTEN and BKLTCTL pins into native mode = for eDP Panel + + @retval Status +**/ +EFI_STATUS +GpioEnableEdpPins ( + VOID + ); + +// +// DDPx pins +// +typedef enum { + GpioDdp1 =3D 0x01, + GpioDdp2 =3D 0x02, + GpioDdp3 =3D 0x03, + GpioDdp4 =3D 0x04, + GpioDdpA =3D 0x10, + GpioDdpB =3D 0x11, + GpioDdpC =3D 0x12, + GpioDdpD =3D 0x13, + GpioDdpF =3D 0x15, +} GPIO_DDP; + +/** + This function sets DDP pins into native mode + + @param[in] DdpInterface DDPx interface + + @retval Status +**/ +EFI_STATUS +GpioEnableDpInterface ( + IN GPIO_DDP DdpInterface + ); + +/** + This function configures GPIO connection between CNVi and CRF + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviCrfConnection ( + VOID + ); + +/** + This function enables CNVi RF Reset pin +**/ +VOID +GpioEnableCnviRfResetPin ( + VOID + ); + +/** + This function enables CNVi MODEM CLKREQ pin +**/ +VOID +GpioEnableCnviModemClkReqPin ( + VOID + ); + +/** + CNVi Bluetooth UART connection options +**/ +typedef enum { + GpioCnviBtUartNotConnected, + GpioCnviBtUartToSerialIoUart0, + GpioCnviBtUartToIshUart0, + GpioCnviBtUartToExternalPads +} VGPIO_CNVI_BT_UART_CONNECTION_TYPE; + +/** + This function configures virtual GPIO connection for CNVi Bluetooth UART + + @param[in] ConnectionType + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviBtUartConnection ( + IN VGPIO_CNVI_BT_UART_CONNECTION_TYPE ConnectionType + ); + +/** + CNVi Bluetooth I2S connection options +**/ +typedef enum { + GpioCnviBtI2sNotConnected, + GpioCnviBtI2sToSsp0, + GpioCnviBtI2sToSsp1, + GpioCnviBtI2sToSsp2, + GpioCnviBtI2sToExternalPads +} VGPIO_CNVI_BT_I2S_CONNECTION_TYPE; + +/** + This function configures virtual GPIO connection for CNVi Bluetooth I2S + + @param[in] ConnectionType + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviBtI2sConnection ( + IN VGPIO_CNVI_BT_I2S_CONNECTION_TYPE ConnectionType + ); + +/** + CNVi MultiFunction UART connection options +**/ +typedef enum { + GpioCnviMfUart1NotConnected, + GpioCnviMfUart1ToSerialIoUart2, + GpioCnviMfUart1ToIshUart0, + GpioCnviMfUart1ToExternalPads +} VGPIO_CNVI_MF_UART1_CONNECTION_TYPE; + +/** + This function configures virtual GPIO connection for CNVi MFUART1 + + @param[in] ConnectionType + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviMfUart1Connection ( + IN VGPIO_CNVI_MF_UART1_CONNECTION_TYPE ConnectionType + ); + + +/** + This function sets CNVi Bluetooth Enable value + + @param[in] Value CNVi BT enable value + 0: Disable, 1: Enable + @retval Status +**/ +EFI_STATUS +GpioSetCnviBtEnState ( + IN UINT32 Value + ); + +/** + CNVi Bluetooth UART connection options +**/ +typedef enum { + GpioCnviBtIfUart =3D 0, + GpioCnviBtIfUsb, +} VGPIO_CNVI_BT_INTERFACE; + +/** + This function sets CNVi Bluetooth main host interface + + @param[in] BtInterface CNVi BT Interface Select value + GpioCnviBtIfUart: UART, GpioCnviBtIfUsb:= USB + @retval Status +**/ +EFI_STATUS +GpioSetCnviBtInterface ( + IN VGPIO_CNVI_BT_INTERFACE BtInterface + ); + +/** + This function sets CNVi Bluetooth Wireless Charging support + + @param[in] BtWirelessCharging CNVi BT Wireless Charging support + 0: Normal BT operation (no Wireless Char= ging support) + 1: Enable BT Wireless Charging + @retval Status +**/ +EFI_STATUS +GpioSetCnviBtWirelessCharging ( + IN UINT32 BtWirelessCharging + ); + +/** + This function enables and configures CNVi Bluetooth Host wake-up interru= pt + + @param[in] None + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviBtHostWakeInt ( + VOID + ); + +/** + CNVi WiFi mode +**/ +typedef enum { + GpioCnviWiFiEnabled, + GpioCnviWiFiAuto +} VGPIO_CNVI_WIFI_MODE; + +/** + This function sets CNVi WiFi mode + + @param[in] Value CNVi WiFi Mode value + GpioCnviWiFiAuto: WiFi is automatically = enabled/disabled by WiFi core + GpioCnviWiFiEnabled: WiFi is enabled reg= ardless of WiFi core decision + @retval Status +**/ +EFI_STATUS +GpioSetCnviWifiMode ( + IN VGPIO_CNVI_WIFI_MODE WiFiMode + ); + +/** + This function enables IMGU CLKOUT native pin + + @param[in] None + + @retval Status +**/ +EFI_STATUS +GpioEnableImguClkOut ( + VOID + ); + +/** + Power button debounce configuration + Debounce time can be specified in microseconds. Only certain values acco= rding + to below formula are supported: + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period). + RTC clock with f =3D 32 KHz is used for glitch filter. + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us). + Supported DebounceTime values are following: + DebounceTime =3D 0 -> Debounce feature disabled + DebounceTime > 0 && < 250us -> Not supported + DebounceTime =3D 250us - 1024000us -> Supported range (DebounceTime =3D= 250us * 2^n) + For values not supported by HW, they will be rounded down to closest sup= ported one + + @param[in] DebounceTime Debounce Time in microseconds + If Debounce Time =3D 0, Debouncer feature wil= l be disabled + Function will set DebounceTime argument to ro= unded supported value +**/ +VOID +GpioSetPwrBtnDebounceTimer ( + IN UINT32 DebounceTime + ); + +/** + Configure LPC GPIO +**/ +VOID +LpcConfigureGpio ( + VOID + ); + +#endif // _GPIO_PRIVATE_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /I2cMasterCommonLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Priv= ate/Library/I2cMasterCommonLib.h new file mode 100644 index 0000000000..a4bd42f420 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/I2cMas= terCommonLib.h @@ -0,0 +1,288 @@ +/** @file + Implement the I2C port control. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _I2C_MASTER_COMMON_LIB_H_ +#define _I2C_MASTER_COMMON_LIB_H_ + +/// +/// Each I2C port instance uses an I2C_MASTER_CONTEXT structure +/// to maintain its context. +/// +typedef struct { + EFI_I2C_CONTROLLER_CAPABILITIES Capabilities; + // + // I2C master's mmio addresses cached to speed up operation + // + UINTN MmioAddress; + UINTN ConfigAddress; + // + // copy of all pointers and data provided in StartRequest call + // if transfer didn't finish in one go, those will be needed to continue= it + // + EFI_I2C_REQUEST_PACKET *Request; + // + // Internal copy of Transfer status, to be returned from StartRequest() + // + EFI_STATUS TransferStatus; + // + // Index (Operation:Postition in Buffer) of next operation to be perform= ed + // Write is for both R/W operations as both need to be put in fifo + // Read is for Read only, for filling buffer with data retrieved from bus + // + UINTN WriteOp; + UINTN WritePos; + UINTN ReadOp; + UINTN ReadPos; + BOOLEAN TransferInProgress; +} I2C_MASTER_CONTEXT; + +/** + Prepare I2c controller for use: enable its mmio range, put in D0, get ou= t of reset + Verifies I2C Line SDA and SCL states + + @param[in] Context - driver context + + @retval EFI_SUCCESS Controller prepared + @retval EFI_DEVICE_ERROR SCL and/or SDA lines are not pulled up +**/ +EFI_STATUS +PrepareController ( + I2C_MASTER_CONTEXT *Context + ); + +/** + Determine the state of the I2C controller + + @param[in] Context - driver context + + @retval TRUE The I2C controller is active + @retval FALSE The I2C controller is idle +**/ +BOOLEAN +IsHardwareActive ( + I2C_MASTER_CONTEXT *Context + ); + +/** + Updates WriteOperation and WritePosition, two variables that determine + which part of Request is being committed to I2C bus. + This iterates over both Read and Write operations from a request, because + things that need to be written to WriteFifo are both I2c bus writes + and I2c bus reads (the command to perform bus read needs to be put into = Write Fifo) + + @param[in] Context - driver context +**/ +VOID +UpdateWritePosition ( + I2C_MASTER_CONTEXT *Context + ); + +/** + FindReadOp checks if current Operation is of Read type. If so, returns. + If not, increases ReadOp until it finds one or goes beyond Request's Ope= rationCount + + @param[in] Context - driver context +**/ +VOID +FindReadOp ( + I2C_MASTER_CONTEXT *Context + ); + +/** + Updates ReadOperation and ReadPosition, two variables that determine + which part of Request is being filled with data incoming from I2C reads. + This iterates only over Read operations from a request. + + @param[in] Context - driver context +**/ +VOID +UpdateReadPosition ( + I2C_MASTER_CONTEXT *Context + ); + +/** + ValidateRequest checks if Request is valid and can be started + + @param[in] Context driver context + @param[in] RequestPacket content of I2C request package + + @retval EFI_SUCCESS Request is valid and can be started + @retval EFI_ALREADY_STARTED The controller is busy with another transf= er + @retval EFI_BAD_BUFFER_SIZE Transfer size too big + @retval EFI_INVALID_PARAMETER RequestPacket is NULL, invalid Operation f= lags + @retval EFI_UNSUPPORTED 10bit I2C address or "ping" operation atte= mpted (0-byte transfer, address byte not followed by any data) +**/ +EFI_STATUS +ValidateRequest ( + I2C_MASTER_CONTEXT *Context, + CONST EFI_I2C_REQUEST_PACKET *RequestPacket + ); + +/** + IsLastFromRequest checks if WritePos and WriteOp point to the last byte = of the request + + @param[in] Context - driver context +**/ +BOOLEAN +IsLastFromRequest ( + I2C_MASTER_CONTEXT *Context + ); + +/** + IsLastFromRequest checks if WritePos and WriteOp point to the first byte= of an operation + + @param[in] Context - driver context + + @retval Boolean +**/ +BOOLEAN +IsFirstFromOperation ( + I2C_MASTER_CONTEXT *Context + ); + +/** + InitializeTransfer checks if HW is ready to accept new transfer. + If so, sets up slave address + + @param[in] Context - driver context + + @retval Status +**/ +EFI_STATUS +InitializeTransfer ( + I2C_MASTER_CONTEXT *Context, + UINTN SlaveAddress, + CONST EFI_I2C_REQUEST_PACKET *RequestPacket + ); + +/** + WriteFifo writes to I2c controller's transmit Fifo. Data written to Fifo= could be + - data bytes to be written to an I2C slave + - read requests that trigger I2C bus reads + First transfer from each operation adds Restart bit which triggers Resta= rt condition on bus + Last transfer from the whole Request adds Stop bit which triggers Stop c= ondtion on bus + Driver keeps track of which parts of Request were already committed to h= ardware using + pointer consisting of WritePosition and WriteOperation variables. This p= ointer is updated + every time data byte/read request is committed to FIFO + WriteFifo executes while there's anything more to write and the write fi= fo isn't full + + @param[in] Context - driver context +**/ +VOID +WriteFifo ( + I2C_MASTER_CONTEXT *Context + ); + +/** + ReadFifo reads from I2c controller's receive Fifo. It contains data retr= ieved + from slave device as a result of executing read transfers, which were + triggered by putting read requests into Write Fifo. Retrieved data is co= pied into buffers + pointed to by Request structure. + Driver keeps track where to copy incoming data using pointer consisting = of + ReadPosition and ReadOperation variables. This pointer is updated + every time data was retrieved from hardware + ReadFifo executes while there's data available and receive buffers were = not filled + + @param[in] Context - driver context +**/ +VOID +ReadFifo ( + I2C_MASTER_CONTEXT *Context + ); + +/** + CheckErrors checks if there were any transfer errors. + + @param[in] Context - driver context +**/ +VOID +CheckErrors ( + I2C_MASTER_CONTEXT *Context + ); + +/** + Transfer is finished when all requested operations were placed in fifo, + all read requests were filled and hardware is inactive + The last part is necessary for write-only transfers where after + placing all writes in fifo sw needs to wait until they flush down the bus + + @param[in] Context - driver context + + @retval Boolean +**/ +BOOLEAN +IsTransferFinished ( + I2C_MASTER_CONTEXT *Context + ); + +/** + Clean up Hw activity and errors + Return status to Request's submitter and signal the event that tells + it that the request is complete + Clear up Sw context to allow new request to start + + @param[in] Context - driver context +**/ +VOID +FinishTransfer ( + I2C_MASTER_CONTEXT *Context + ); + +/** + PerformTransfer. For synchronous transfer this function is called in a l= oop + and for asynchronous transfers, as a timer callback. It writes data and/= or + read requests to hadrware, copies read data to destination buffers. When + transfer completes, it cleans up Sw context and Hw registers in preparat= ion + for new transfer + + @param[in] Context - driver context +**/ +VOID +PerformTransfer ( + IN I2C_MASTER_CONTEXT *Context + ); + +/** + Set the I2C controller bus clock frequency. + + This routine must be called at or below TPL_NOTIFY. + + The software and controller do a best case effort of using the specified + frequency for the I2C bus. If the frequency does not match exactly then + the controller will use lower frequency for the I2C to avoid exceeding + the operating conditions for any of the I2C devices on the bus. + For example if 400 KHz was specified and the controller's divide network + only supports 402 KHz or 398 KHz then the controller would be set to 398 + KHz. + + @param[in] MmioAddress Address of I2C controller + @param[in] BusClockHertz New I2C bus clock frequency in Hertz + + @retval EFI_SUCCESS The bus frequency was set successfully. + @retval EFI_UNSUPPORTED The controller does not support this frequency. +**/ + +EFI_STATUS +FrequencySet ( + IN UINTN MmioAddress, + IN OUT UINTN *BusClockHertz + ); + +/** + Reset the I2C controller + + @param[in] MmioAddress Address of I2C controller + + @retval Status +**/ +EFI_STATUS +I2cReset ( + IN UINTN MmioAddress + ); + +#endif // _I2C_MASTER_COMMON_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PchDmiLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Libra= ry/PchDmiLib.h new file mode 100644 index 0000000000..d17b65c598 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchDmi= Lib.h @@ -0,0 +1,344 @@ +/** @file + Header file for PchDmiLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_DMI_LIB_H_ +#define _PCH_DMI_LIB_H_ + +/** + This function checks if DMI Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmiLocked ( + VOID + ); + +/** + Set ACPI base address decoding in DMI + + @param[in] Address Address for ACPI base. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetAcpiBase ( + IN UINT16 Address + ); + +/** + Set PWRM base address decoding in DMI + + @param[in] Address Address for PWRM base. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetPwrmBase ( + IN UINT32 Address + ); + +/** + Set PCH TCO base address decoding in DMI + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetTcoBase ( + IN UINT16 Address + ); + +/** + Get PCH TCO base address. + + @retval Address Address of TCO base address. +**/ +UINT16 +PchDmiGetTcoBase ( + VOID + ); + +/** + Set PCH LPC/eSPI generic IO range decoding in DMI + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + @param[in] RangeIndex Index of choosen range + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcGenIoRange ( + IN UINT32 Address, + IN UINT32 Length, + IN UINT32 RangeIndex + ); + +/** + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1GenIoRange ( + IN UINT32 Address, + IN UINT32 Length + ); + +/** + Clear PCH LPC/eSPI generic IO range decoding in DMI + + @param[in] RangeIndex Index of chosen range + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiClearLpcGenIoRange ( + IN UINTN RangeIndex + ); + +/** + Clear PCH eSPI CS1# generic IO range decoding in DMI + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiClearEspiCs1GenIoRange ( + VOID + ); + +/** + Set PCH LPC/eSPI memory range decoding in DMI + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcMemRange ( + IN UINT32 Address + ); + +/** + Set PCH eSPI CS1# memory range decoding in DMI + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1MemRange ( + IN UINT32 Address + ); + +/** + Check if Boot BIOS Strap is set for SPI. + + @retval TRUE Boot BIOS Strap set for SPI + @retval FALSE Boot BIOS Strap set for LPC/eSPI +**/ +BOOLEAN +PchDmiIsBootBiosStrapSetForSpi ( + VOID + ); + +/** + Set PCH BIOS range decoding in DMI + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetBiosDecodeEnable ( + IN UINT16 BiosDecodeEnable + ); + +/** + Set PCH LPC/eSPI IO decode ranges in DMI + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcIoDecodeRanges ( + IN UINT16 LpcIoDecodeRanges + ); + +/** + Set PCH LPC/eSPI IO enable decoding in DMI + + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcIoEnable ( + IN UINT16 LpcIoEnableDecoding + ); + +/** + Set PCH IO port 80h cycle decoding to PCIE root port in DMI + + @param[in] RpNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchDmiSetIoPort80Decode ( + IN UINTN RpNumber + ); + +/** + Set DMI thermal throttling to recommended configuration +**/ +VOID +PchDmiSetRecommendedThermalThrottling ( + VOID + ); + +// +// Thermal Sensor Target Width structure +// Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values +// +typedef struct { + UINT32 ThermalSensor0TargetWidth :3; + UINT32 ThermalSensor1TargetWidth :3; + UINT32 ThermalSensor2TargetWidth :3; + UINT32 ThermalSensor3TargetWidth :3; + UINT32 Rsvd :20; +} DMI_THERMAL_THROTTLING; + +/** + Set DMI thermal throttling to custom configuration. + This function will configure Thermal Sensor 0/1/2/3 TargetWidth and set + DMI Thermal Sensor Autonomous Width Enable. + + @param[in] DmiThermalThrottling DMI Thermal Throttling structure. +**/ +VOID +PchDmiSetCustomThermalThrottling ( + IN DMI_THERMAL_THROTTLING DmiThermalThrottling + ); + +/** + Determines where to send the reserved page registers + Accesses to the I/O ranges 80h - 8Fh will be forwarded to PCIe Root Port + with the destination ID specified in GCS.RPRDID using DMI source decode. +**/ +VOID +PchDmiSetReservedPageRegToPcieRootPort ( + VOID + ); + +/** + Determines where to send the reserved page registers + DMI will not perform source decode on the I/O ranges 80h - 8Fh. The cycl= es hitting these ranges will + end up in P2SB which will then forward the cycle to LPC or eSPI through = IOSF Sideband. +**/ +VOID +PchDmiSetReservedPageRegToLpc ( + VOID + ); + +/** + uCode Patch Region Enable (UPRE). Enables memory access targeting the uC= ode patch region (0xFEF00000 to 0xFEFFFFFF) + to be forwarded to SPI Flash. This can only be set if the boot flash is = on SPI. +**/ +VOID +PchDmiEnableUCodePatchRegion ( + VOID + ); + +/** + Enable PCIe Relaxed Order +**/ +VOID +PchDmiEnablePcieRelaxedOrder ( + VOID + ); + +/** + This function will switch SAI value to be driven to IOSF Primary Fabric + for cycles with Core BDF from HOSTIA_BOOT_SAI to HOSTIA_POSTBOOT_SAI. + To be used when PCH is paired with CFL CPU. +**/ +VOID +PchDmiEnablePostBootSai ( + VOID + ); + +/** + This function will do necessary configuration after platform + should have switched to POSTBOOT_SAI. It needs to be called even if + POSTBOOT_SAI was not set. +**/ +VOID +PchDmiConfigAfterPostBootSai ( + VOID + ); + +/** + Configure PCH DMI Lock +**/ +VOID +PchDmiSetLockWithS3BootScript ( + VOID + ); + +/** + Set BIOS interface Lock-Down +**/ +VOID +PchDmiSetBiosLockDownWithS3BootScript ( + VOID + ); +#endif // _PCH_DMI_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PchHdaLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Libra= ry/PchHdaLib.h new file mode 100644 index 0000000000..e53ed881df --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchHda= Lib.h @@ -0,0 +1,56 @@ +/** @file + This library provides PCH HD Audio functions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_LIB_H_ +#define _PCH_HDA_LIB_H_ + +#include +#include + +/** + Prints NHLT (Non HDA-Link Table) to be exposed via ACPI (aka. OED (Offlo= ad Engine Driver) Configuration Table). + + @param[in] *NhltAcpiTable The NHLT table to print +**/ +VOID +NhltAcpiTableDump( + IN NHLT_ACPI_TABLE *NhltTable + ); + +/** + Constructs EFI_ACPI_DESCRIPTION_HEADER structure for NHLT table. + + @param[in][out] *NhltTable NHLT table for which header will b= e created + @param[in] NhltTableSize Size of NHLT table + + @retval None +**/ +VOID +NhltAcpiHeaderConstructor ( + IN OUT NHLT_ACPI_TABLE *NhltTable, + IN UINT32 NhltTableSize + ); + +/** + Constructs NHLT_ACPI_TABLE structure based on given Endpoints list. + + @param[in] *EndpointTable List of endpoints for NHLT + @param[in][out] **NhltTable NHLT table to be created + @param[in][out] *NhltTableSize Size of created NHLT table + + @retval EFI_SUCCESS NHLT created successfully + @retval EFI_BAD_BUFFER_SIZE Not enough resources to allocate NHLT +**/ +EFI_STATUS +NhltConstructor( + IN PCH_HDA_NHLT_ENDPOINTS *EndpointTable, + IN OUT NHLT_ACPI_TABLE **NhltTable, + IN OUT UINT32 *NhltTableSize + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PchInitCommonLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Privat= e/Library/PchInitCommonLib.h new file mode 100644 index 0000000000..6d71504772 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchIni= tCommonLib.h @@ -0,0 +1,100 @@ +/** @file + Header file for PCH Init Common Lib + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_INIT_COMMON_LIB_H_ +#define _PCH_INIT_COMMON_LIB_H_ + +#include + +/** + This function returns PID according to PCIe controller index + + @param[in] ControllerIndex PCIe controller index + + @retval PCH_SBI_PID Returns PID for SBI Access +**/ +PCH_SBI_PID +PchGetPcieControllerSbiPid ( + IN UINT32 ControllerIndex + ); + +/** + This function returns PID according to Root Port Number + + @param[in] RpPort Root Port Number + + @retval PCH_SBI_PID Returns PID for SBI Access +**/ +PCH_SBI_PID +GetRpSbiPid ( + IN UINTN RpPort + ); + +/** + Calculate root port device number based on physical port index. + + @param[in] RpIndex Root port index (0-based). + + @retval Root port device number. +**/ +UINT32 +PchGetPcieRpDevice ( + IN UINT32 RpIndex + ); + +/** + This function reads Pci Config register via SBI Access + + @param[in] RpIndex Root Port Index (0-based) + @param[in] Offset Offset of Config register + @param[out] *Data32 Value of Config register + + @retval EFI_SUCCESS SBI Read successful. +**/ +EFI_STATUS +PchSbiRpPciRead32 ( + IN UINT32 RpIndex, + IN UINT32 Offset, + OUT UINT32 *Data32 + ); + +/** + This function And then Or Pci Config register via SBI Access + + @param[in] RpIndex Root Port Index (0-based) + @param[in] Offset Offset of Config register + @param[in] Data32And Value of Config register to be And-ed + @param[in] Data32AOr Value of Config register to be Or-ed + + @retval EFI_SUCCESS SBI Read and Write successful. +**/ +EFI_STATUS +PchSbiRpPciAndThenOr32 ( + IN UINT32 RpIndex, + IN UINT32 Offset, + IN UINT32 Data32And, + IN UINT32 Data32Or + ); + +/** + Print registers value + + @param[in] PrintMmioBase Mmio base address + @param[in] PrintSize Number of registers + @param[in] OffsetFromBase Offset from mmio base address + + @retval None +**/ +VOID +PrintRegisters ( + IN UINTN PrintMmioBase, + IN UINT32 PrintSize, + IN UINT32 OffsetFromBase + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PchPciExpressHelpersLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include= /Private/Library/PchPciExpressHelpersLib.h new file mode 100644 index 0000000000..b0e4eb64c2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPci= ExpressHelpersLib.h @@ -0,0 +1,371 @@ +/** @file + Header file for PCH PCI Express helpers library + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCI_EXPRESS_HELPERS_LIB_H_ +#define _PCH_PCI_EXPRESS_HELPERS_LIB_H_ + +#include + +typedef enum { + TpoScale2us, + TpoScale10us, + TpoScale100us, + TpoScaleMax +} T_PO_SCALE; + +typedef struct { + UINT32 Value; + T_PO_SCALE Scale; +} T_POWER_ON; + +// +// Function prototypes +// + +/** + Get PCIe port number for enabled port. + @param[in] RpBase Root Port pci segment base address + @return Root Port number (1 based) +**/ +UINT32 +PciePortNum ( + IN UINT64 RpBase + ); + +/** + Get PCIe root port index + @param[in] RpBase Root Port pci segment base address + @return Root Port index (0 based) +**/ +UINT32 +PciePortIndex ( + IN UINT64 RpBase + ); + +/** + Translate PCIe Port/Lane pair to 0-based PCIe lane number. + + @param[in] RpIndex Root Port index + @param[in] RpLane Root Port Lane (0-3) + + @retval PCIe lane number (0-based) +**/ +UINT32 +PchPciePhysicalLane ( + UINT32 RpIndex, + UINT32 RpLane + ); + +/** + Checks if lane reversal is enabled on a given root port + + @param[in] RpIndex Root port index (0-based) + + @retval TRUE if lane reversal is enbabled, FALSE otherwise +**/ +BOOLEAN +IsPcieLaneReversalEnabled ( + IN UINT32 RpIndex + ); + +/** + Calculates the index of the first port on the same controller. + + @param[in] RpIndex Root Port Number (0-based) + + @retval Index of the first port on the first controller. +**/ +UINT32 +PchGetPcieFirstPortIndex ( + IN UINT32 RpIndex + ); + +/* + Returns Tpower_on capability of device + + @param[in] DeviceBase device's PCI segment base address + @param[in] L1ssCapOffset offset to L1substates capability in device's= extended config space + + @retval structure containing Tpoweron scale and value +*/ +T_POWER_ON +GetTpoCapability ( + UINT64 DeviceBase, + UINT32 L1ssCapOffset + ); + +/* + Converts Tpower_on from value:scale notation to microseconds + + @param[in] TpoScale T power on scale + @param[in] TpoValue T power on value + + @retval number of microseconds +*/ +UINT32 +TpoToUs ( + UINT32 TpoScale, + UINT32 TpoValue + ); + +/** + Find the Offset to a given Capabilities ID + CAPID list: + 0x01 =3D PCI Power Management Interface + 0x04 =3D Slot Identification + 0x05 =3D MSI Capability + 0x10 =3D PCI Express Capability + + @param[in] DeviceBase device's base address + @param[in] CapId CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT8 +PcieBaseFindCapId ( + IN UINT64 DeviceBase, + IN UINT8 CapId + ); + +/** + Find the Offset to a given Capabilities ID + CAPID list: + 0x01 =3D PCI Power Management Interface + 0x04 =3D Slot Identification + 0x05 =3D MSI Capability + 0x10 =3D PCI Express Capability + + @param[in] Segment Pci Segment Number + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT8 +PcieFindCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 CapId + ); + +/** + Search and return the offset of desired Pci Express Capability ID + CAPID list: + 0x0001 =3D Advanced Error Reporting Capability + 0x0002 =3D Virtual Channel Capability + 0x0003 =3D Device Serial Number Capability + 0x0004 =3D Power Budgeting Capability + + @param[in] DeviceBase device base address + @param[in] CapId Extended CAPID to search for + + @retval 0 CAPID not found, this includes situation= where device doesn't exist + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT16 +PcieBaseFindExtendedCapId ( + IN UINT64 DeviceBase, + IN UINT16 CapId + ); + +/** + Search and return the offset of desired Pci Express Capability ID + CAPID list: + 0x0001 =3D Advanced Error Rreporting Capability + 0x0002 =3D Virtual Channel Capability + 0x0003 =3D Device Serial Number Capability + 0x0004 =3D Power Budgeting Capability + + @param[in] Segment Pci Segment Number + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId Extended CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT16 +PcieFindExtendedCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT16 CapId + ); + +/* + Checks device's Slot Clock Configuration + + @param[in] Base device's base address + + @retval TRUE when device device uses slot clock, FALSE otherwise +*/ +BOOLEAN +GetScc ( + UINT64 Base, + UINT8 PcieCapOffset + ); + +/* + Sets Common Clock Configuration bit for given device. + + @param[in] Base device's base address +*/ +VOID +EnableCcc ( + UINT64 Base, + UINT8 PcieCapOffset + ); + +/* + Retrains link behind given device. + It only makes sense to call it for downstream ports. + If called for upstream port nothing will happen, it won't enter infinite= loop. + + @param[in] Base device's base address +*/ +VOID +RetrainLink ( + UINT64 Base, + UINT8 PcieCapOffset, + BOOLEAN WaitUntilDone + ); + +/* + Checks if device at given address exists + + @retval TRUE when device exists; FALSE otherwise +*/ +BOOLEAN +IsDevicePresent ( + UINT64 Base + ); + +/* + Checks if device is a multifunction device + + @param[in] Base device's base address + + @retval TRUE if multifunction; FALSE otherwise +*/ +BOOLEAN +IsMultifunctionDevice ( + UINT64 Base + ); + +/* + Initializes the following features in rootport and devices behind it: + Maximum Payload Size (generic) + Rootport packet split (proprietary) + EonOfInterrupt forwarding (proprietary) + Common Clock Configuration (generic) + + Generic: any code written according to PCIE Express base specification c= an do that. + Proprietary: code uses registers and features that are specific to Intel= silicon + and probably only this Reference Code knows how to handle that. + + If OEM implemented generic feature enabling in his platform code or trus= ts Operating System + to do it, then those features can be deleted from here. + + CCC requires link retrain, which takes a while. CCC must happen before L= 0s/L1 programming. + If there was guarantee no code would access PCI while links retrain, it = would be possible to skip this waiting + + @param[in] RpSegment address of rootport on PCIe + @param[in] RpBus address of rootport on PCIe + @param[in] RpDevice address of rootport on PCIe + @param[in] RpFunction address of rootport on PCIe + @param[in] BusMin minimum Bus number that can be assigned below this= rootport + @param[in] BusMax maximum Bus number that can be assigned below this= rootport +*/ +VOID +RootportDownstreamConfiguration ( + UINT8 RpSegment, + UINT8 RpBus, + UINT8 RpDevice, + UINT8 RpFunction, + UINT8 BusMin, + UINT8 BusMax + ); + +/* + Configures the following power-management related features in rootport a= nd devices behind it: + LTR limit (generic) + LTR override (proprietary) + Clock Power Management (generic) + L1 substates (generic except for the override table) + L1.LOW substate (proprietary) + L0s and L1 (generic) + + Generic: any code written according to PCIE Express base specification c= an do that. + Proprietary: code uses registers and features that are specific to Intel= silicon + and probably only this Reference Code knows how to handle that. + + If OEM implemented generic feature enabling in his platform code or trus= ts Operating System + to do it, then those features can be deleted from here. + + @param[in] RpSegment address of rootport on PCIe + @param[in] RpBus address of rootport on PCIe + @param[in] RpDevice address of rootport on PCIe + @param[in] RpFunction address of rootport on PCIe + @param[in] BusLimit maximum Bus number that can be assig= ned below this rootport + @param[in] AspmOverrideTableSize size of override array + @param[in] AspmOverrideTable array of device that need exceptions= in configuration +*/ +VOID +RootportDownstreamPmConfiguration ( + UINT8 RpSegment, + UINT8 RpBus, + UINT8 RpDevice, + UINT8 RpFunction, + UINT8 BusMin, + UINT8 BusMax, + PCH_PCIE_ROOT_PORT_CONFIG *RpConfig, + UINT32 AspmOverrideTableSize, + PCH_PCIE_DEVICE_OVERRIDE *AspmOverrideTable + ); + +/** + Get current PCIe link speed. + + @param[in] RpBase Root Port base address + @return Link speed +**/ +UINT32 +GetLinkSpeed ( + UINT64 RpBase + ); + +/** + Get max PCIe link speed supported by the root port. + + @param[in] RpBase Root Port pci segment base address + @return Max link speed +**/ +UINT32 +GetMaxLinkSpeed ( + UINT64 RpBase + ); + +/** + PCIe controller configuration. +**/ +typedef enum { + Pcie4x1 =3D 0, + Pcie1x2_2x1 =3D 1, + Pcie2x2 =3D 2, + Pcie1x4 =3D 3 +} PCIE_CONTROLLER_CONFIG; + +#endif // _PEI_DXE_SMM_PCH_PCI_EXPRESS_HELPERS_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PchPsfPrivateLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Privat= e/Library/PchPsfPrivateLib.h new file mode 100644 index 0000000000..9e68615717 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchPsf= PrivateLib.h @@ -0,0 +1,578 @@ +/** @file + Header file for PchPsfPrivateLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PSF_PRIVATE_LIB_H_ +#define _PCH_PSF_PRIVATE_LIB_H_ + +#include +#include + +// +// Structure for storing data on both PSF SideBand Port ID and +// PSF port register offset for specific device +// +typedef struct { + PCH_SBI_PID PsfPid; + UINT16 RegBase; +} PSF_PORT; + +/** + Disable device at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfDisableDevice ( + IN PSF_PORT PsfPort + ); + +/** + Enable device at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfEnableDevice ( + IN PSF_PORT PsfPort + ); + +/** + Hide PciCfgSpace of device at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfHideDevice ( + IN PSF_PORT PsfPort + ); + +/** + Unhide PciCfgSpace of device at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfUnhideDevice ( + IN PSF_PORT PsfPort + ); + +/** + Disable device BARs at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure + @param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,... + Mask corresponds to 32bit wide BARs +**/ +VOID +PsfDisableDeviceBar ( + IN PSF_PORT PsfPort, + IN UINT32 BarDisMask + ); + +/** + Enable device BARs at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure + @param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,... + Mask corresponds to 32bit wide BARs +**/ +VOID +PsfEnableDeviceBar ( + IN PSF_PORT PsfPort, + IN UINT32 BarEnMask + ); + +/** + Return PSF_PORT for SerialIO I2C device + + @param[in] I2cNum Serial IO I2C device (I2C0, I2C1, ....) + + @retval PsfPort PSF PORT structure for SerialIO I2C device +**/ +PSF_PORT +PsfSerialIoI2cPort ( + IN UINT32 I2cNum + ); + +/** + Return PSF_PORT for SerialIO SPI device + + @param[in] SpiNum Serial IO SPI device (SPI0, SPI1, ....) + + @retval PsfPort PSF PORT structure for SerialIO SPI device +**/ +PSF_PORT +PsfSerialIoSpiPort ( + IN UINT32 SpiNum + ); + +/** + Return PSF_PORT for SerialIO UART device + + @param[in] UartNum Serial IO UART device (UART0, UART1, ....) + + @retval PsfPort PSF PORT structure for SerialIO UART device +**/ +PSF_PORT +PsfSerialIoUartPort ( + IN UINT32 UartNum + ); + +/** + This procedure will set BARx value for TraceHub ACPI device at PSF level + + @param[in] BarNum BAR Number (0:BAR0, 1:BAR1) + @param[in] BarValue 32bit BAR value +**/ +VOID +PsfSetTraceHubAcpiDeviceBarValue ( + IN UINT8 BarNum, + IN UINT32 BarValue + ); + +/** + This procedure will enable MSE for TraceHub ACPI device at PSF level +**/ +VOID +PsfEnableTraceHubAcpiDeviceMemorySpace ( + VOID + ); + +/** + Enable HECI device at PSF level + + @param[in] HeciDevice HECIx Device (HECI1-4) +**/ +VOID +PsfEnableHeciDevice ( + IN UINT8 HeciDevice + ); + +/** + Disable HECI device at PSF level + + @param[in] HeciDevice HECIx Device (HECI1-4) +**/ +VOID +PsfDisableHeciDevice ( + IN UINT8 HeciDevice + ); + +/** + Disable IDER device at PSF level +**/ +VOID +PsfDisableIderDevice ( + VOID + ); + +/** + Enable SOL device at PSF level +**/ +VOID +PsfEnableSolDevice ( + VOID + ); + +/** + Disable SOL device at PSF level +**/ +VOID +PsfDisableSolDevice ( + VOID + ); + +/** + Set PMC ABASE value in PSF + + @param[in] Address Address for ACPI base. +**/ +VOID +PsfSetPmcAbase ( + IN UINT16 Address + ); + +/** + Get PMC ABASE value from PSF + + @retval Address Address for ACPI base. +**/ +UINT16 +PsfGetPmcAbase ( + VOID + ); + +/** + Get PMC PWRMBASE value from PSF + + @retval Address Address for PWRM base. +**/ +UINT32 +PsfGetPmcPwrmBase ( + VOID + ); + +/** + Hide Cnvi WiFi device's PciCfgSpace at PSF level +**/ +VOID +PsfHideCnviWifiDevice ( + VOID + ); + +/** + Disable Cnvi Wifi device at PSF level +**/ +VOID +PsfDisableCnviWifiDevice ( + VOID + ); + +/** + Disable HDAudio device at PSF level +**/ +VOID +PsfDisableHdaDevice ( + VOID + ); + +/** + Disable xDCI device at PSF level +**/ +VOID +PsfDisableXdciDevice ( + VOID + ); + +/** + Disable xHCI device at PSF level +**/ +VOID +PsfDisableXhciDevice ( + VOID + ); + +/** + Disable xHCI VTIO Phantom device at PSF level +**/ +VOID +PsfDisableXhciVtioDevice ( + VOID + ); + +/** + Disable SATA device at PSF level + + @param[in] SataCtrlIndex SATA controller index +**/ +VOID +PsfDisableSataDevice ( + IN UINT32 SataCtrlIndex + ); + +/** + Return PSF_PORT for SCS eMMC device + + @retval PsfPort PSF PORT structure for SCS eMMC device +**/ +PSF_PORT +PsfScsEmmcPort ( + VOID + ); + +/** + Return PSF_PORT for SCS SD Card device + + @retval PsfPort PSF PORT structure for SCS SD Card device +**/ +PSF_PORT +PsfScsSdCardPort ( + VOID + ); + +/** + Return PSF_PORT for SCS UFS device + + @param[in] UfsNum UFS Device + + @retval PsfPort PSF PORT structure for SCS UFS device +**/ +PSF_PORT +PsfScsUfsPort ( + IN UINT32 UfsNum + ); + +/** + Disable ISH device at PSF level +**/ +VOID +PsfDisableIshDevice ( + VOID + ); + +/** + Disable ISH BAR1 at PSF level +**/ +VOID +PsfDisableIshBar1 ( + VOID + ); + +/** + Disable GbE device at PSF level +**/ +VOID +PsfDisableGbeDevice ( + VOID + ); + +/** + Disable SMBUS device at PSF level +**/ +VOID +PsfDisableSmbusDevice ( + VOID + ); + +/** + Disable TraceHub ACPI devices at PSF level +**/ +VOID +PsfDisableTraceHubAcpiDevice ( + VOID + ); + +/** + Hide TraceHub ACPI devices PciCfgSpace at PSF level +**/ +VOID +PsfHideTraceHubAcpiDevice ( + VOID + ); + +/** + This procedure will hide TraceHub PciCfgSpace at PSF level +**/ +VOID +PsfHideTraceHubDevice ( + VOID + ); + +/** + This procedure will unhide TraceHub PciCfgSpace at PSF level +**/ +VOID +PsfUnhideTraceHubDevice ( + VOID + ); + +/** + This procedure will disable TraceHub device at PSF level +**/ +VOID +PsfDisableTraceHubDevice ( + VOID + ); + +/** + Configures rootspace 3 bus number for PCIe IMR use + + @param[in] Rs3Bus bus number +**/ +VOID +PsfSetRs3Bus ( + UINT8 Rs3Bus + ); + +/** + Disable PCIe Root Port at PSF level + + @param[in] RpIndex PCIe Root Port Index (0 based) +**/ +VOID +PsfDisablePcieRootPort ( + IN UINT32 RpIndex + ); + +/** + Program PSF grant counts for SATA + Call this before SATA ports are accessed for enumeration +**/ +VOID +PsfConfigureSataGrantCounts ( + VOID + ); + +typedef enum { + PsfPcieCtrl4x1, + PsfPcieCtrl1x2_2x1, + PsfPcieCtrl2x2, + PsfPcieCtrl1x4 +} PSF_PCIE_CTRL_CONFIG; + +/** + Program PSF grant counts for PCI express depending on controllers config= uration + + @param[in] PsfPcieCtrlConfigTable Table with PCIe controllers configur= ation + @param[in] NumberOfPcieControllers Number of PCIe controllers. This is = also the size of PsfPcieCtrlConfig table +**/ +VOID +PsfConfigurePcieGrantCounts ( + IN PSF_PCIE_CTRL_CONFIG *PsfPcieCtrlConfigTable, + IN UINT32 NumberOfPcieControllers + ); + +/** + Program PSF EOI Multicast configuration for ITSS +**/ +VOID +PsfConfigurEoiForItss ( + VOID + ); + +/** + This function enables EOI message forwarding in PSF for PCIe ports + for cases where IOAPIC is present behind this root port. + + @param[in] RpIndex Root port index (0 based) + + @retval Status +**/ +EFI_STATUS +PsfConfigurEoiForPciePort ( + IN UINT32 RpIndex + ); + +// +// Structure for PSF Port Destination ID +// +typedef union { + UINT32 RegVal; + struct { + UINT32 ChannelId : 8; // Channel ID + UINT32 PortId : 7; // Port ID + UINT32 PortGroupId : 1; // Port Group ID + UINT32 PsfId : 8; // PSF ID + UINT32 Rsvd : 7; // Reserved + UINT32 ChanMap : 1; // Channel map + } Fields; +} PSF_PORT_DEST_ID; + +/** + PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id) + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval Destination ID +**/ +PSF_PORT_DEST_ID +PsfPcieDestinationId ( + IN UINT32 RpIndex + ); + +/** + PSF early initialization. +**/ +VOID +PsfEarlyInit ( + VOID + ); + +/** + Assign new function number for PCIe Port Number. + + @param[in] RpIndex PCIe Root Port Index (0 based) + @param[in] NewFunction New Function number +**/ +VOID +PsfSetPcieFunction ( + IN UINT32 RpIndex, + IN UINT32 NewFunction + ); + +/** + This function enables PCIe Relaxed Order in PSF +**/ +VOID +PsfEnablePcieRelaxedOrder ( + VOID + ); + +/** + Configure PSF power management. + Must be called after all PSF configuration is completed. +**/ +VOID +PsfConfigurePowerManagement ( + VOID + ); + +/** + Enable VTd support in PSF. +**/ +VOID +PchPsfEnableVtd ( + VOID + ); + +/** + Disable PSF address-based peer-to-peer decoding. +**/ +VOID +PchPsfDisableP2pDecoding ( + VOID + ); + +/** + Perform registers programming required for + Management Component Transport Protocol Broadcast Cycle. + + Agent Destination Addresses are being programmed only when adequate + PCIe root port controllers are function enabled. + + Function sets CSME PMT as a message broadcaster and programs the targets + of the message in registers only if adequate PCIe root port controllers + are function enabled. Conditionally, if the CPU PEG exist and is function + enabled, DMI is also a target. +**/ +VOID +PsfConfigureMctpCycle ( + VOID + ); + +/** + This procedure will hide PMC device at PSF level +**/ +VOID +PsfHidePmcDevice ( + VOID + ); + +/** + This procedure will disable D3:F0 device at PSF level for PCH-LP +**/ +VOID +PsfDisableD3F0 ( + VOID + ); + +/** + This procedure will disable PSF upstream completion tracking for HDAudio= on PCH-LP +**/ +VOID +PsfDisableUpstreamCompletionTrackingForHda ( + VOID + ); + +#endif // _PCH_PSF_PRIVATE_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PchSmbusCommonLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Priva= te/Library/PchSmbusCommonLib.h new file mode 100644 index 0000000000..313b13060f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSmb= usCommonLib.h @@ -0,0 +1,98 @@ +/** @file + PCH Smbus Protocol + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SMBUS_COMMON_LIB_H +#define _PCH_SMBUS_COMMON_LIB_H + +// +// Definitions +// +#define SMBUS_NUM_RESERVED 38 ///< Number of device addresse= s that are reserved by the SMBus spec. +#define SMBUS_ADDRESS_ARP 0xC2 >> 1 +#define SMBUS_DATA_PREPARE_TO_ARP 0x01 +#define SMBUS_DATA_RESET_DEVICE 0x02 +#define SMBUS_DATA_GET_UDID_GENERAL 0x03 +#define SMBUS_DATA_ASSIGN_ADDRESS 0x04 +#define SMBUS_GET_UDID_LENGTH 17 ///< 16 byte UDID + 1 byte add= ress +// +// Private data and functions +// + +#define PCH_SMBUS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('p', 's', 'm', 'b') + +/** + This function provides a standard way to read PCH Smbus IO registers. + + @param[in] Offset Register offset from Smbus base IO addre= ss. + + @retval UINT8 Returns data read from IO. +**/ +UINT8 +SmbusIoRead ( + IN UINT8 Offset + ); + +/** + This function provides a standard way to write PCH Smbus IO registers. + + @param[in] Offset Register offset from Smbus base IO addre= ss. + @param[in] Data Data to write to register. + +**/ +VOID +SmbusIoWrite ( + IN UINT8 Offset, + IN UINT8 Data + ); + +/** + This function provides a standard way to execute Smbus protocols + as defined in the SMBus Specification. The data can either be of + the Length byte, word, or a block of data. The resulting transaction wil= l be + either the SMBus Slave Device accepts this transaction or this function + returns with an error + + @param[in] SlaveAddress Smbus Slave device the command is direct= ed at + @param[in] Command Slave Device dependent + @param[in] Operation Which SMBus protocol will be used + @param[in] PecCheck Defines if Packet Error Code Checking is= to be used + @param[in, out] Length How many bytes to read. Must be 0 <=3D L= ength <=3D 32 depending on Operation + It will contain the actual number of byt= es read/written. + @param[in, out] Buffer Contain the data read/written. + + @retval EFI_SUCCESS The operation completed successfully. + @exception EFI_UNSUPPORTED The operation is unsupported. + + @retval EFI_INVALID_PARAMETER Length or Buffer is NULL for any operati= on besides + quick read or quick write. + @retval EFI_TIMEOUT The transaction did not complete within = an internally + specified timeout period, or the control= ler is not + available for use. + @retval EFI_DEVICE_ERROR There was an Smbus error (NACK) during t= he operation. + This could indicate the slave device is = not present + or is in a hung condition. +**/ +EFI_STATUS +SmbusExec ( + IN EFI_SMBUS_DEVICE_ADDRESS SlaveAddress, + IN EFI_SMBUS_DEVICE_COMMAND Command, + IN EFI_SMBUS_OPERATION Operation, + IN BOOLEAN PecCheck, + IN OUT UINTN *Length, + IN OUT VOID *Buffer + ); + +/** + This function initializes the Smbus Registers. + +**/ +VOID +InitializeSmbusRegisters ( + VOID + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PchSpiCommonLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private= /Library/PchSpiCommonLib.h new file mode 100644 index 0000000000..0a973a77a3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PchSpi= CommonLib.h @@ -0,0 +1,366 @@ +/** @file + Header file for the PCH SPI Common Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SPI_COMMON_LIB_H_ +#define _PCH_SPI_COMMON_LIB_H_ + +#include + +// +// Maximum time allowed while waiting the SPI cycle to complete +// Wait Time =3D 6 seconds =3D 6000000 microseconds +// Wait Period =3D 10 microseconds +// +#define SPI_WAIT_TIME 6000000 ///< Wait Time =3D 6 seconds =3D 60000= 00 microseconds +#define SPI_WAIT_PERIOD 10 ///< Wait Period =3D 10 microseconds + +/// +/// Flash cycle Type +/// +typedef enum { + FlashCycleRead, + FlashCycleWrite, + FlashCycleErase, + FlashCycleReadSfdp, + FlashCycleReadJedecId, + FlashCycleWriteStatus, + FlashCycleReadStatus, + FlashCycleMax +} FLASH_CYCLE_TYPE; + +/// +/// Flash Component Number +/// +typedef enum { + FlashComponent0, + FlashComponent1, + FlashComponentMax +} FLASH_COMPONENT_NUM; + +/// +/// Private data structure definitions for the driver +/// +#define PCH_SPI_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('P', 'S', 'P', 'I') + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + PCH_SPI_PROTOCOL SpiProtocol; + UINT16 PchAcpiBase; + UINT64 PchSpiBase; + UINT8 ReadPermission; + UINT8 WritePermission; + UINT32 SfdpVscc0Value; + UINT32 SfdpVscc1Value; + UINT16 PchStrapBaseAddr; + UINT16 PchStrapSize; + UINT16 CpuStrapBaseAddr; + UINT16 CpuStrapSize; + UINT8 NumberOfComponents; + UINT32 Component1StartAddr; + UINT32 TotalFlashSize; +} SPI_INSTANCE; + +#define SPI_INSTANCE_FROM_SPIPROTOCOL(a) CR (a, SPI_INSTANCE, SpiProtocol= , PCH_SPI_PRIVATE_DATA_SIGNATURE) + +// +// Function prototypes used by the SPI protocol. +// + +/** + Initialize an SPI protocol instance. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +SpiProtocolConstructor ( + IN SPI_INSTANCE *SpiInstance + ); + +/** + This function is a hook for Spi to disable BIOS Write Protect + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in S= MM phase + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + VOID + ); + +/** + This function is a hook for Spi to enable BIOS Write Protect + + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + VOID + ); + +/** + Acquire pch spi mmio address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval PchSpiBar0 return SPI MMIO address +**/ +UINTN +AcquireSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ); + +/** + Release pch spi mmio address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval None +**/ +VOID +ReleaseSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ); + +/** + Check if it's granted to do flash write. + + @retval TRUE It's secure to do flash write. + @retval FALSE It's not secure to do flash write. +**/ +BOOLEAN +IsSpiFlashWriteGranted ( + VOID + ); + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashRead ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ); + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWrite ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ); + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashErase ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ); + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data = read. + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadSfdp ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ); + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadJedecId ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ); + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWriteStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ); + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ); + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +EFI_STATUS +EFIAPI +SpiProtocolGetRegionAddress ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ); + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadPchSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadCpuSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PeiPchDmiLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Li= brary/PeiPchDmiLib.h new file mode 100644 index 0000000000..301ec3dd48 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PeiPch= DmiLib.h @@ -0,0 +1,25 @@ +/** @file + This file contains PEI DMI methods + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PCH_DMI_LIB_H_ +#define _PEI_PCH_DMI_LIB_H_ + +#include + +// +// Data structure definitions +// +typedef enum { + DmiVcTypeVc0, + DmiVcTypeVc1, + DmiVcTypeVcm, + DmiVcTypeMax +} PCH_DMI_VC_TYPE; + + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /PmcPrivateLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/L= ibrary/PmcPrivateLib.h new file mode 100644 index 0000000000..44e7567e0f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/PmcPri= vateLib.h @@ -0,0 +1,706 @@ +/** @file + Header file for private PmcLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PMC_PRIVATE_LIB_H_ +#define _PMC_PRIVATE_LIB_H_ + +#include +#include + +/** + Send PMC IPC1 Normal Read/Write command + + @param[in] Command Command to be issued to PMC IPC 1 interface + @param[in] SubCmdId SUB_CMD_ID for provided Command + @param[in] CmdSize Total size in byte to be sent via PMC IPC = 1 interface + @param[in] WriteBufPtr Pointer to Structure of 4 DWORDs to be iss= ued to PMC IPC 1 interface + @param[out] ReadBufPtr Pointer to Structure of 4 DWORDs to be fil= led by PMC IPC 1 interface + + @retval EFI_SUCCESS Command was executed successfully + @retval EFI_INVALID_PARAMETER Invalid command size + @retval EFI_DEVICE_ERROR IPC command failed with an error + @retval EFI_TIMEOUT IPC command did not complete after 1s +**/ +EFI_STATUS +PmcSendCommand ( + IN UINT8 Command, + IN UINT8 SubCmdId, + IN UINT8 CmdSize, + IN PMC_IPC_COMMAND_BUFFER *WriteBufPtr, + OUT PMC_IPC_COMMAND_BUFFER *ReadBufPtr + ); + +/** + Set PCH ACPI base address. + The Address should not be 0 and should be 256 bytes alignment, and it is= IO space, so must not exceed 0xFFFF. + + @param[in] Address Address for ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +PmcSetAcpiBase ( + IN UINT16 Address + ); + +/** + Set PCH PWRM base address. + Only 0xFE000000 (PCH_PWRM_BASE_ADDRESS) is the acceptable value for PWRM= BASE + + @param[in] Address Address for PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PmcSetPwrmBase ( + IN UINT32 Address + ); + +/** + This function checks if function disable (static and non-static power ga= ting) + configuration is locked + + @retval lock state +**/ +BOOLEAN +PmcIsFunctionDisableConfigLocked ( + VOID + ); + +/** + This function locks static power gating configuration with S3 Boot Scrip= t programming +**/ +VOID +PmcLockFunctionDisableConfigWithS3BootScript ( + VOID + ); + +/** + This function checks if ISH is function disabled + by static power gating + + @retval ISH device state +**/ +BOOLEAN +PmcIsIshFunctionDisabled ( + VOID + ); + +/** + This function checks if ISH device is supported (not disabled by fuse) + + @retval ISH support state +**/ +BOOLEAN +PmcIsIshSupported ( + VOID + ); + +/** + This function disables ISH device by static power gating + For static power gating to take place Global Reset, G3 or DeepSx transit= ion must happen. +**/ +VOID +PmcStaticDisableIsh ( + VOID + ); + +/** + This function enables ISH device by disabling static power gating +**/ +VOID +PmcEnableIsh ( + VOID + ); + +/** + This function enables GBE ModPHY SPD gating. +**/ +VOID +PmcGbeModPhyPowerGating ( + VOID + ); + +/** + This function checks if GbE is function disabled + by static power gating + + @retval GbE device state +**/ +BOOLEAN +PmcIsGbeFunctionDisabled ( + VOID + ); + +/** + This function disables GbE device by static power gating + For static power gating to take place Global Reset, G3 or DeepSx transit= ion must happen. +**/ +VOID +PmcStaticDisableGbe ( + VOID + ); + +/** + This function enables GbE device by disabling static power gating + Static power gating disabling takes place after Global Reset, G3 or Deep= Sx transition. +**/ +VOID +PmcEnableGbe ( + VOID + ); + +/** + This function checks if GbE device is supported (not disabled by fuse) + + @retval GbE support state +**/ +BOOLEAN +PmcIsGbeSupported ( + VOID + ); + +/** + This function enables all SerailIo devices + Static power gating disabling takes place after Global Reset, G3 or Deep= Sx transition. +**/ +VOID +PmcEnableSerialIo ( + VOID + ); + +/** + This function disables (static power gating) all SerailIo devices. + For SerialIo controllers they can be power gated only if all of them are= to be disabled. + They cannot be statically power gated separately. + For static power gating to take place Global Reset, G3 or DeepSx transit= ion must happen. +**/ +VOID +PmcStaticDisableSerialIo ( + VOID + ); + +/** + This function checks if all SerialIo devices are statically disabled (st= atic power gating) + + @retval SerialIo disable state +**/ +BOOLEAN +PmcIsSerialIoStaticallyDisabled ( + VOID + ); + +/** + This function checks if SerialIo device is supported (not disabled by fu= se) + + @retval SerialIo support state +**/ +BOOLEAN +PmcIsSerialIoSupported ( + VOID + ); + +/** + This function disables (non-static power gating) HDA device +**/ +VOID +PmcDisableHda ( + VOID + ); + +/** + This function checks if Cnvi device is supported (not disabled by fuse) + + @retval Cnvi support state +**/ +BOOLEAN +PmcIsCnviSupported ( + VOID + ); + +/** + This function checks if CNVi is function disabled + by static power gating + + @retval GbE device state +**/ +BOOLEAN +PmcIsCnviFunctionDisabled ( + VOID + ); + +/** + This function enables CNVi device by disabling static power gating. + Static power gating disabling takes place after Global Reset, G3 or Deep= Sx transition. +**/ +VOID +PmcEnableCnvi ( + VOID + ); + +/** + This function disables CNVi device by static power gating + For static power gating to take place Global Reset, G3 or DeepSx transit= ion must happen. +**/ +VOID +PmcStaticDisableCnvi ( + VOID + ); + +/** + This function disables (non-static power gating) PCIe Root Port + + @param[in] RpIndex PCIe Root Port Index (0 based) +**/ +VOID +PmcDisablePcieRootPort ( + IN UINT32 RpIndex + ); + +/** + This function disables (non-static power gating) SATA + + @param[in] SataCtrlIndex SATA controller index +**/ +VOID +PmcDisableSata ( + IN UINT32 SataCtrlIndex + ); + +/** + This function checks if SATA device is supported (not disabled by fuse) + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA support state +**/ +BOOLEAN +PmcIsSataSupported ( + IN UINT32 SataCtrlIndex + ); + +/** + This function gets NMI regsiter. + + @retval NMI register setting +**/ +UINT32 +PmcGetNmiControl ( + VOID + ); + +/** + This function sets the NMI register + + @param[in] NmiRegister The whole NMI register +**/ +VOID +PmcSetNmiControl ( + UINT32 NmiRegister + ); + +/** + This function disables (non-static power gating) xHCI +**/ +VOID +PmcDisableXhci ( + VOID + ); + +/** + This function disables (non-static power gating) XDCI +**/ +VOID +PmcDisableXdci ( + VOID + ); + +/** + This function checks if XDCI device is supported (not disabled by fuse) + + @retval XDCI support state +**/ +BOOLEAN +PmcIsXdciSupported ( + VOID + ); + +/** + This function disables (non-static power gating) SCS eMMC controller and= enables ModPHY SPD gating (PCH-LP only). +**/ +VOID +PmcDisableScsEmmc ( + VOID + ); + +/** + This function disables (non-static power gating) SCS SD Card controller = and enables ModPHY SPD gating (PCH-LP only). +**/ +VOID +PmcDisableScsSdCard ( + VOID + ); + +/** + This function disables (non-static power gating) SCS UFS controller and = enables ModPHY SPD gating (PCH-LP only). + + @param[in] UfsNum SCS UFS Device +**/ +VOID +PmcDisableScsUfs ( + IN UINT32 UfsNum + ); + +/** + This function checks if SCS eMMC device is supported (not disabled by fu= se) + + @retval SCS device support state +**/ +BOOLEAN +PmcIsScsEmmcSupported ( + VOID + ); + +/** + This function checks if SCS SD Card device is supported (not disabled by= fuse) + + @retval SCS device support state +**/ +BOOLEAN +PmcIsScsSdCardSupported ( + VOID + ); + +/** + This function checks if SCS UFS device is supported (not disabled by fus= e) + + @param[in] UfsNum SCS UFS Device + + @retval SCS device support state +**/ +BOOLEAN +PmcIsScsUfsSupported ( + IN UINT32 UfsNum + ); + + +/** + This function locks HOST SW power gating control +**/ +VOID +PmcLockHostSwPgCtrl ( + VOID + ); + +/** + This function checks if HOST SW Power Gating Control is locked + + @retval lock state +**/ +BOOLEAN +PmcIsHostSwPgCtrlLocked ( + VOID + ); + +/** + This function disables Trace Hub by enabling power gating +**/ +VOID +PmcDisableTraceHub ( + VOID + ); + +/** + This function enables Trace Hub by disabling power gating +**/ +VOID +PmcEnableTraceHub ( + VOID + ); + +/** + This function checks if LAN wake from DeepSx is enabled + + @retval Lan Wake state +**/ +BOOLEAN +PmcIsLanDeepSxWakeEnabled ( + VOID + ); + +/** + This function locks down PMC (DebugModeLock) +**/ +VOID +PmcLockWithS3BootScript ( + VOID + ); + +/** + Checks if conditions for proper USB2 PHY AFE programming are met +**/ +VOID +PmcUsb2CorePhyPowerGatingDisable ( + VOID + ); + +/** + This function reads CPU Early Power-on Configuration (EPOC) + + @retval CPU EPOC value +**/ +UINT32 +PmcGetCpuEpoc ( + VOID + ); + +/** + This function sets CPU Early Power-on Configuration (EPOC) + + @param[in] CpuEpocValue CPU EPOC value +**/ +VOID +PmcSetCpuEpoc ( + IN UINT32 CpuEpocValue + ); + +/** + This function sets DRAM_RESET# Control Pin value + + @param[in] DramResetVal 0: Pin output is low + 1: Pin output is tri-stated +**/ +VOID +PmcSetDramResetCtlState ( + IN UINT32 DramResetVal + ); + +/** + This function enables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh +**/ +VOID +PmcEnableCf9GlobalReset ( + VOID + ); + +/** + This function disables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh. +**/ +VOID +PmcDisableCf9GlobalReset ( + VOID + ); + +/** + This function disables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh. + Global Reset configuration is locked after programming +**/ +VOID +PmcDisableCf9GlobalResetWithLock ( + VOID + ); + +/** + This S3 BootScript only function disables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh. +**/ +VOID +PmcDisableCf9GlobalResetInS3BootScript ( + VOID + ); + +/** + This S3 BootScript only function disables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh. + Global Reset configuration is locked after programming +**/ +VOID +PmcDisableCf9GlobalResetWithLockInS3BootScript ( + VOID + ); + +/** + This function disables CF9 reset without Resume Well reset. + Cf9 0x6/0xE reset will also reset resume well logic. +**/ +VOID +PmcDisableCf9ResetWithoutResumeWell ( + VOID + ); + +/** + This function locks PMC Set Strap Message interface with S3 Boot Script = programming +**/ +VOID +PmcLockSetStrapMsgInterfaceWithS3BootScript ( + VOID + ); + +/** + This function clears RTC Power Failure status (RTC_PWR_FLR) +**/ +VOID +PmcClearRtcPowerFailureStatus ( + VOID + ); + +/** + This function enables PCI Express* PME events +**/ +VOID +PmcEnablePciExpressPmeEvents ( + VOID + ); + +/** + This function sets SLP_SX Stretching Policy and adds + lock setting to S3 Boot Script +**/ +VOID +PmcLockSlpSxStretchingPolicyWithS3BootScript ( + VOID + ); + +/** + This function sets SMI Lock with S3 Boot Script programming +**/ +VOID +PmcLockSmiWithS3BootScript ( + VOID + ); + +/** + This function sets eSPI SMI Lock +**/ +VOID +PmcLockEspiSmi ( + VOID + ); + +/** + This function checks if eSPI SMI Lock is set + + @retval eSPI SMI Lock state +**/ +BOOLEAN +PmcIsEspiSmiLockSet ( + VOID + ); + +typedef enum { + PmcSwSmiRate1p5ms =3D 0, + PmcSwSmiRate16ms, + PmcSwSmiRate32ms, + PmcSwSmiRate64ms +} PMC_SWSMI_RATE; + +/** + This function sets SW SMI Rate. + + @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values +**/ +VOID +PmcSetSwSmiRate ( + IN PMC_SWSMI_RATE SwSmiRate + ); + +typedef enum { + PmcPeriodicSmiRate8s =3D 0, + PmcPeriodicSmiRate16s, + PmcPeriodicSmiRate32s, + PmcPeriodicSmiRate64s +} PMC_PERIODIC_SMI_RATE; + +/** + This function sets Periodic SMI Rate. + + @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for pos= sible values +**/ +VOID +PmcSetPeriodicSmiRate ( + IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate + ); + +/** + This function reads Power Button Level + + @retval State of PWRBTN# signal (0: Low, 1: High) +**/ +UINT8 +PmcGetPwrBtnLevel ( + VOID + ); + +/** + This function gets Group to GPE0 configuration + + @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment + @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment + @param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment +**/ +VOID +PmcGetGpioGpe ( + OUT UINT32 *GpeDw0Value, + OUT UINT32 *GpeDw1Value, + OUT UINT32 *GpeDw2Value + ); + +/** + This function sets Group to GPE0 configuration + + @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment + @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment + @param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment +**/ +VOID +PmcSetGpioGpe ( + IN UINT32 GpeDw0Value, + IN UINT32 GpeDw1Value, + IN UINT32 GpeDw2Value + ); + +/** + This function checks if SCI interrupt is enabled + + @retval SCI Enable state +**/ +BOOLEAN +PmcIsSciEnabled ( + VOID + ); + +/** + This function triggers Software GPE +**/ +VOID +PmcTriggerSwGpe ( + VOID + ); + +/** + Disable SLP_S0# assertion when system is in debug mode +**/ +VOID +PmcDisableSlpS0AssertionInDebugMode ( + VOID + ); + +/** + Enable SLP_S0# assertion even when system is in debug mode +**/ +VOID +PmcEnableSlpS0AssertionInDebugMode ( + VOID + ); + +#endif // _PMC_PRIVATE_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /SiScheduleResetLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Priv= ate/Library/SiScheduleResetLib.h new file mode 100644 index 0000000000..af5734b74b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SiSche= duleResetLib.h @@ -0,0 +1,48 @@ +/** @file + Reset scheduling library services + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_SCHEDULE_RESET_LIB_H_ +#define _SI_SCHEDULE_RESET_LIB_H_ + +#include +#include + +/** + This function updates the reset information in SiScheduleResetHob + @param[in] ResetType UEFI defined reset type. + @param[in] ResetData Optional element used to introduce a platfor= m specific reset. + The exact type of the reset is defined by t= he EFI_GUID that follows + the Null-terminated Unicode string. +**/ +VOID +SiScheduleResetSetType ( + IN EFI_RESET_TYPE ResetType, + IN PCH_RESET_DATA *ResetData OPTIONAL + ); + +/** + This function returns TRUE or FALSE depending on whether a reset is requ= ired based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is requ= ired +**/ +BOOLEAN +SiScheduleResetIsRequired ( + VOID + ); + +/** + This function performs reset based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is requ= ired +**/ +BOOLEAN +SiScheduleResetPerformReset ( + VOID + ); + +#endif //_SI_SCHEDULE_RESET_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library= /SmmPchPrivateLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Privat= e/Library/SmmPchPrivateLib.h new file mode 100644 index 0000000000..f074e0073a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Library/SmmPch= PrivateLib.h @@ -0,0 +1,28 @@ +/** @file + Header file for private PCH SMM Lib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SMM_PCH_PRIVATE_LIB_H_ +#define _SMM_PCH_PRIVATE_LIB_H_ + +/** + Set InSmm.Sts bit +**/ +VOID +PchSetInSmmSts ( + VOID + ); + +/** + Clear InSmm.Sts bit +**/ +VOID +PchClearInSmmSts ( + VOID + ); + +#endif // _SMM_PCH_PRIVATE_LIB_H_ --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45888): https://edk2.groups.io/g/devel/message/45888 Mute This Topic: https://groups.io/mt/32918180/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45887+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45887+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001014; cv=none; d=zoho.com; s=zohoarc; b=QHZ5d8xJEvAv8rTbdAYP41k0iniDi3EkB0G5hUfveMDE6Wi8XUfOx+eQlKHlJLkmZf30BbZpLFz3Wird0tAavpCLjpJqC7C1cVm+ZS4CeVIlfQLuCjPohR5uHyj7DkAPg89JXD31Y/6RO+aIJv6ZpOYzUweco4uOYOCkGMEc6bg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001014; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=Ltqi2LsP3dyLXXbgSRTB+F93FQznhjFXB/pfTqMRWaI=; b=ohl4IJhjaXFakTEyBHYWCFC+Qd5V2nInhSARF67cRvI2c5iPRjkQHMFkjf0PyCY+5AuSnQilS4lKzGrxlh0AKzZfjGKa6QLsS3N4QrbtzZGj48/G+0iwqwImm9D/2CevteU2IloxUBVL2GO5fp3i4xE3MU19YnJkQetHVV78pLs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45887+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001014332771.8350502601272; Fri, 16 Aug 2019 17:16:54 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:52 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319258" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:51 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 11/37] CoffeelakeSiliconPkg/Pch: Add Private/Protocol include headers Date: Fri, 16 Aug 2019 17:15:37 -0700 Message-Id: <20190817001603.30632-12-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001013; bh=KnMt4jvbyr3KnLDz0uNzjv2f5O3DDsXjKstZcmA9E3o=; h=Cc:Date:From:Reply-To:Subject:To; b=ASsbft2mm81Ik+W/51VgpHz2oqpbcyTVUtVW/0HCjpr5tRLk6FyG8eWOM5fzK47htEd PfI8DvbGTcHnJB4i6HbZOhnU6o8JQ92nnCUC9jgNyJS8NOSNixCfGJpCA+y/lMkmlQGl1 VQQDrEYJGyxRc2x7bcAY9corLHFmFIINXfM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds the following header files: * Pch/Include/Private/Protocol Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNvsArea= .h | 31 ++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieIoTrap= .h | 37 ++++++++++++++++++++ 2 files changed, 68 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protoco= l/PchNvsArea.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Pro= tocol/PchNvsArea.h new file mode 100644 index 0000000000..75003c82ad --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PchNv= sArea.h @@ -0,0 +1,31 @@ +/** @file + This file defines the PCH NVS Area Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_NVS_AREA_H_ +#define _PCH_NVS_AREA_H_ + +// +// PCH NVS Area definition +// +#include + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchNvsAreaProtocolGuid; + +/** + This protocol is used to sync PCH information from POST to runtime ASL. + This protocol exposes the pointer of PCH NVS Area only. Please refer to + ASL definition for PCH NVS AREA. +**/ +typedef struct { + PCH_NVS_AREA *Area; +} PCH_NVS_AREA_PROTOCOL; + +#endif // _PCH_NVS_AREA_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protoco= l/PcieIoTrap.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Pro= tocol/PcieIoTrap.h new file mode 100644 index 0000000000..2cd6b85d29 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Private/Protocol/PcieI= oTrap.h @@ -0,0 +1,37 @@ +/** @file + This file defines the PCH PCIE IoTrap Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCIE_IOTRAP_H_ +#define _PCH_PCIE_IOTRAP_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gPchPcieIoTrapProtocolGuid; + +// +// Forward reference for ANSI C compatibility +// +typedef struct _PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL; + +/// +/// Pcie Trap valid types +/// +typedef enum { + PciePmTrap, + PcieTrapTypeMaximum +} PCH_PCIE_TRAP_TYPE; + +/** + This protocol is used to provide the IoTrap address to trigger PCH PCIE c= all back events +**/ +struct _PCH_PCIE_IOTRAP_PROTOCOL { + UINT16 PcieTrapAddress; +}; + +#endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45887): https://edk2.groups.io/g/devel/message/45887 Mute This Topic: https://groups.io/mt/32918179/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45890+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45890+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001015; cv=none; d=zoho.com; s=zohoarc; b=OwbTIlLy1w+MlUGNJNHtnGFwR7AlDvL+3DQkcPSKc4lZuLrUFISjOSICLkWOOCW+VG5eJCLrpbtiRKE/DGTCATI+QLK+ABPMXHQSCPC3w01gD2c43k1wEZYelYMvEjR6g14FWFKQ8OkhN0LlAQ5RnbLIBqmaZB182r5M5kzTSos= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001015; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=UEJdMtz4ZwnWoVXSKkaAzHs5aGS1phc/h6Rg0QNXKqg=; b=PtX9lJEq0C/tfWPqLL5Vj+HbX1/h7HSQ4rJCr9hzfKjGT0xXay6ofGxa5bvqqo477CVlaDbloWYytTSKoNK+GkhOPP8lAB44yXnxmlB7zlpPzF5O9azpYZljYWNCj4dTe4qCxBm51SqUBnfN17kfKPzu6Khb3wYNc257dWw/XQI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45890+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001015288597.1255315868349; Fri, 16 Aug 2019 17:16:55 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:52 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319260" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:51 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 12/37] CoffeelakeSiliconPkg/SampleCode: Add Include headers Date: Fri, 16 Aug 2019 17:15:38 -0700 Message-Id: <20190817001603.30632-13-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001014; bh=gXu7KqK4I4KjGC5g7niskruAcXTE8hINpwg+wbD6XTY=; h=Cc:Date:From:Reply-To:Subject:To; b=mkZtWhobZ/QnkxIeSpBFAovc8znfkA0zTqXNnoeUi9LilP/fK+ziZ7s7/2hxDOVeNWL 9lu1uWk9joW3GkTQVj1sd2Xvn8ZckfPA/EO8Gxxqi2GW6QZM9RMM8E+6yiDXC5AnM8vxq 1xcsuw0h2VwkjtjbZGMBvmnpAPDAKxhEzAo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds header files common to silicon Sample Code. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha > Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlatformL= ib.h | 82 ++ Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Gu= id/SmramMemoryReserve.h | 51 + Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Pr= otocol/LegacyBios.h | 1513 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Include/Pr= otocol/LegacyInterrupt.h | 118 ++ Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/Ac= piS3Context.h | 65 + Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/Co= nsoleOutDevice.h | 17 + Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Guid/Me= moryTypeInformation.h | 30 + Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Library= /ResetSystemLib.h | 80 ++ Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/Smm= Access.h | 137 ++ Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Ppi/Smm= Control.h | 87 ++ Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Protoco= l/SmmVariable.h | 33 + 11 files changed, 2213 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/= SecPlatformLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Li= brary/SecPlatformLib.h new file mode 100644 index 0000000000..829d1190fc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/Include/Library/SecPlat= formLib.h @@ -0,0 +1,82 @@ +/** @file + Prototype of SEC Platform hook library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SEC_PLATFORM_LIB_H_ +#define _SEC_PLATFORM_LIB_H_ + +#include +#include + +/** + A developer supplied function to perform platform specific operations. + + It's a developer supplied function to perform any operations appropriate= to a + given platform. It's invoked just before passing control to PEI core by = SEC + core. Platform developer may modify the SecCoreData passed to PEI Core. + It returns a platform specific PPI list that platform wishes to pass to = PEI core. + The Generic SEC core module will merge this list to join the final list = passed to + PEI core. + + @param SecCoreData The same parameter as passing to PEI core.= It + could be overridden by this function. + + @return The platform specific PPI list to be passed to PEI core or + NULL if there is no need of such platform specific PPI list. + +**/ +EFI_PEI_PPI_DESCRIPTOR * +EFIAPI +SecPlatformMain ( + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData + ); + + +/** + This interface conveys state information out of the Security (SEC) phase= into PEI. + + @param PeiServices Pointer to the PEI Services Table. + @param StructureSize Pointer to the variable describing siz= e of the input buffer. + @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORM= ATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ); + +/** + This interface conveys performance information out of the Security (SEC)= phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an= optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the + PEI Foundation. As such, if the platform supports collecting performance= data in SEC, + this information is encapsulated into the data structure abstracted by t= his service. + This information is collected for the boot-strap processor (BSP) on IA-3= 2. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI. + @param[out] Performance The pointer to performance data collected in SE= C phase. + + @retval EFI_SUCCESS The data was successfully returned. +**/ +EFI_STATUS +EFIAPI +SecGetPerformance ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_SEC_PERFORMANCE_PPI *This, + OUT FIRMWARE_SEC_PERFORMANCE *Performance + ); + +#endif + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPk= g/Include/Guid/SmramMemoryReserve.h b/Silicon/Intel/CoffeelakeSiliconPkg/Sa= mpleCode/IntelFrameworkPkg/Include/Guid/SmramMemoryReserve.h new file mode 100644 index 0000000000..862a7c8aea --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Inclu= de/Guid/SmramMemoryReserve.h @@ -0,0 +1,51 @@ +/** @file + Definition of GUIDed HOB for reserving SMRAM regions. + + This file defines: + * the GUID used to identify the GUID HOB for reserving SMRAM regions. + * the data structure of SMRAM descriptor to describe SMRAM candidate reg= ions + * values of state of SMRAM candidate regions + * the GUID specific data structure of HOB for reserving SMRAM regions. + This GUIDed HOB can be used to convey the existence of the T-SEG reserva= tion and H-SEG usage + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_ +#define _EFI_SMM_PEI_SMRAM_MEMORY_RESERVE_H_ + +#define EFI_SMM_PEI_SMRAM_MEMORY_RESERVE \ + { \ + 0x6dadf1d1, 0xd4cc, 0x4910, {0xbb, 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff,= 0x3d } \ + } + +/** +* GUID specific data structure of HOB for reserving SMRAM regions. +* +* Inconsistent with specification here: +* EFI_HOB_SMRAM_DESCRIPTOR_BLOCK has been changed to EFI_SMRAM_HOB_DESCRIP= TOR_BLOCK. +* This inconsistency is kept in code in order for backward compatibility. +**/ +typedef struct { + /// + /// Designates the number of possible regions in the system + /// that can be usable for SMRAM. + /// + /// Inconsistent with specification here: + /// In Framework SMM CIS 0.91 specification, it defines the field type a= s UINTN. + /// However, HOBs are supposed to be CPU neutral, so UINT32 should be us= ed instead. + /// + UINT32 NumberOfSmmReservedRegions; + /// + /// Used throughout this protocol to describe the candidate + /// regions for SMRAM that are supported by this platform. + /// + EFI_SMRAM_DESCRIPTOR Descriptor[1]; +} EFI_SMRAM_HOB_DESCRIPTOR_BLOCK; + +extern EFI_GUID gEfiSmmPeiSmramMemoryReserveGuid; + +#endif + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPk= g/Include/Protocol/LegacyBios.h b/Silicon/Intel/CoffeelakeSiliconPkg/Sample= Code/IntelFrameworkPkg/Include/Protocol/LegacyBios.h new file mode 100644 index 0000000000..6ba23381b0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Inclu= de/Protocol/LegacyBios.h @@ -0,0 +1,1513 @@ +/** @file + The EFI Legacy BIOS Protocol is used to abstract legacy Option ROM usage + under EFI and Legacy OS boot. This file also includes all the related + COMPATIBILIY16 structures and defintions. + + Note: The names for EFI_IA32_REGISTER_SET elements were picked to follow + well known naming conventions. + + Thunk is the code that switches from 32-bit protected environment into t= he 16-bit real-mode + environment. Reverse thunk is the code that does the opposite. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_LEGACY_BIOS_H_ +#define _EFI_LEGACY_BIOS_H_ + +/// +/// +/// +#pragma pack(1) + +typedef UINT8 SERIAL_MODE; +typedef UINT8 PARALLEL_MODE; + +#define EFI_COMPATIBILITY16_TABLE_SIGNATURE SIGNATURE_32 ('I', 'F', 'E', '= $') + +/// +/// There is a table located within the traditional BIOS in either the 0xF= 000:xxxx or 0xE000:xxxx +/// physical address range. It is located on a 16-byte boundary and provid= es the physical address of the +/// entry point for the Compatibility16 functions. These functions provide= the platform-specific +/// information that is required by the generic EfiCompatibility code. The= functions are invoked via +/// thunking by using EFI_LEGACY_BIOS_PROTOCOL.FarCall86() with the 32-bit= physical +/// entry point. +/// +typedef struct { + /// + /// The string "$EFI" denotes the start of the EfiCompatibility table. B= yte 0 is "I," byte + /// 1 is "F," byte 2 is "E," and byte 3 is "$" and is normally accessed = as a DWORD or UINT32. + /// + UINT32 Signature; + + /// + /// The value required such that byte checksum of TableLength equals zer= o. + /// + UINT8 TableChecksum; + + /// + /// The length of this table. + /// + UINT8 TableLength; + + /// + /// The major EFI revision for which this table was generated. + /// + UINT8 EfiMajorRevision; + + /// + /// The minor EFI revision for which this table was generated. + /// + UINT8 EfiMinorRevision; + + /// + /// The major revision of this table. + /// + UINT8 TableMajorRevision; + + /// + /// The minor revision of this table. + /// + UINT8 TableMinorRevision; + + /// + /// Reserved for future usage. + /// + UINT16 Reserved; + + /// + /// The segment of the entry point within the traditional BIOS for Compa= tibility16 functions. + /// + UINT16 Compatibility16CallSegment; + + /// + /// The offset of the entry point within the traditional BIOS for Compat= ibility16 functions. + /// + UINT16 Compatibility16CallOffset; + + /// + /// The segment of the entry point within the traditional BIOS for EfiCo= mpatibility + /// to invoke the PnP installation check. + /// + UINT16 PnPInstallationCheckSegment; + + /// + /// The Offset of the entry point within the traditional BIOS for EfiCom= patibility + /// to invoke the PnP installation check. + /// + UINT16 PnPInstallationCheckOffset; + + /// + /// EFI system resources table. Type EFI_SYSTEM_TABLE is defined in the = IntelPlatform + ///Innovation Framework for EFI Driver Execution Environment Core Interf= ace Specification (DXE CIS). + /// + UINT32 EfiSystemTable; + + /// + /// The address of an OEM-provided identifier string. The string is null= terminated. + /// + UINT32 OemIdStringPointer; + + /// + /// The 32-bit physical address where ACPI RSD PTR is stored within the = traditional + /// BIOS. The remained of the ACPI tables are located at their EFI addre= sses. The size + /// reserved is the maximum for ACPI 2.0. The EfiCompatibility will fill= in the ACPI + /// RSD PTR with either the ACPI 1.0b or 2.0 values. + /// + UINT32 AcpiRsdPtrPointer; + + /// + /// The OEM revision number. Usage is undefined but provided for OEM mod= ule usage. + /// + UINT16 OemRevision; + + /// + /// The 32-bit physical address where INT15 E820 data is stored within t= he traditional + /// BIOS. The EfiCompatibility code will fill in the E820Pointer value a= nd copy the + /// data to the indicated area. + /// + UINT32 E820Pointer; + + /// + /// The length of the E820 data and is filled in by the EfiCompatibility= code. + /// + UINT32 E820Length; + + /// + /// The 32-bit physical address where the $PIR table is stored in the tr= aditional BIOS. + /// The EfiCompatibility code will fill in the IrqRoutingTablePointer va= lue and + /// copy the data to the indicated area. + /// + UINT32 IrqRoutingTablePointer; + + /// + /// The length of the $PIR table and is filled in by the EfiCompatibilit= y code. + /// + UINT32 IrqRoutingTableLength; + + /// + /// The 32-bit physical address where the MP table is stored in the trad= itional BIOS. + /// The EfiCompatibility code will fill in the MpTablePtr value and copy= the data + /// to the indicated area. + /// + UINT32 MpTablePtr; + + /// + /// The length of the MP table and is filled in by the EfiCompatibility = code. + /// + UINT32 MpTableLength; + + /// + /// The segment of the OEM-specific INT table/code. + /// + UINT16 OemIntSegment; + + /// + /// The offset of the OEM-specific INT table/code. + /// + UINT16 OemIntOffset; + + /// + /// The segment of the OEM-specific 32-bit table/code. + /// + UINT16 Oem32Segment; + + /// + /// The offset of the OEM-specific 32-bit table/code. + /// + UINT16 Oem32Offset; + + /// + /// The segment of the OEM-specific 16-bit table/code. + /// + UINT16 Oem16Segment; + + /// + /// The offset of the OEM-specific 16-bit table/code. + /// + UINT16 Oem16Offset; + + /// + /// The segment of the TPM binary passed to 16-bit CSM. + /// + UINT16 TpmSegment; + + /// + /// The offset of the TPM binary passed to 16-bit CSM. + /// + UINT16 TpmOffset; + + /// + /// A pointer to a string identifying the independent BIOS vendor. + /// + UINT32 IbvPointer; + + /// + /// This field is NULL for all systems not supporting PCI Express. This = field is the base + /// value of the start of the PCI Express memory-mapped configuration re= gisters and + /// must be filled in prior to EfiCompatibility code issuing the Compati= bility16 function + /// Compatibility16InitializeYourself(). + /// Compatibility16InitializeYourself() is defined in Compatability16 + /// Functions. + /// + UINT32 PciExpressBase; + + /// + /// Maximum PCI bus number assigned. + /// + UINT8 LastPciBus; + + /// + /// Start Address of Upper Memory Area (UMA) to be set as Read/Write. If + /// UmaAddress is a valid address in the shadow RAM, it also indicates t= hat the region + /// from 0xC0000 to (UmaAddress - 1) can be used for Option ROM. + /// + UINT32 UmaAddress; + + /// + /// Upper Memory Area size in bytes to be set as Read/Write. If zero, no= UMA region + /// will be set as Read/Write (i.e. all Shadow RAM is set as Read-Only). + /// + UINT32 UmaSize; + + /// + /// Start Address of high memory that can be used for permanent allocati= on. If zero, + /// high memory is not available for permanent allocation. + /// + UINT32 HiPermanentMemoryAddress; + + /// + /// Size of high memory that can be used for permanent allocation in byt= es. If zero, + /// high memory is not available for permanent allocation. + /// + UINT32 HiPermanentMemorySize; +} EFI_COMPATIBILITY16_TABLE; + +/// +/// Functions provided by the CSM binary which communicate between the Efi= Compatibility +/// and Compatability16 code. +/// +/// Inconsistent with the specification here: +/// The member's name started with "Compatibility16" [defined in Intel Fra= mework +/// Compatibility Support Module Specification / 0.97 version] +/// has been changed to "Legacy16" since keeping backward compatible. +/// +typedef enum { + /// + /// Causes the Compatibility16 code to do any internal initialization re= quired. + /// Input: + /// AX =3D Compatibility16InitializeYourself + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_INIT_TABLE + /// Return: + /// AX =3D Return Status codes + /// + Legacy16InitializeYourself =3D 0x0000, + + /// + /// Causes the Compatibility16 BIOS to perform any drive number translat= ions to match the boot sequence. + /// Input: + /// AX =3D Compatibility16UpdateBbs + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE + /// Return: + /// AX =3D Returned status codes + /// + Legacy16UpdateBbs =3D 0x0001, + + /// + /// Allows the Compatibility16 code to perform any final actions before = booting. The Compatibility16 + /// code is read/write. + /// Input: + /// AX =3D Compatibility16PrepareToBoot + /// ES:BX =3D Pointer to EFI_TO_COMPATIBILITY16_BOOT_TABLE structure + /// Return: + /// AX =3D Returned status codes + /// + Legacy16PrepareToBoot =3D 0x0002, + + /// + /// Causes the Compatibility16 BIOS to boot. The Compatibility16 code is= Read/Only. + /// Input: + /// AX =3D Compatibility16Boot + /// Output: + /// AX =3D Returned status codes + /// + Legacy16Boot =3D 0x0003, + + /// + /// Allows the Compatibility16 code to get the last device from which a = boot was attempted. This is + /// stored in CMOS and is the priority number of the last attempted boot= device. + /// Input: + /// AX =3D Compatibility16RetrieveLastBootDevice + /// Output: + /// AX =3D Returned status codes + /// BX =3D Priority number of the boot device. + /// + Legacy16RetrieveLastBootDevice =3D 0x0004, + + /// + /// Allows the Compatibility16 code rehook INT13, INT18, and/or INT19 af= ter dispatching a legacy OpROM. + /// Input: + /// AX =3D Compatibility16DispatchOprom + /// ES:BX =3D Pointer to EFI_DISPATCH_OPROM_TABLE + /// Output: + /// AX =3D Returned status codes + /// BX =3D Number of non-BBS-compliant devices found. Equals 0 if BBS = compliant. + /// + Legacy16DispatchOprom =3D 0x0005, + + /// + /// Finds a free area in the 0xFxxxx or 0xExxxx region of the specified = length and returns the address + /// of that region. + /// Input: + /// AX =3D Compatibility16GetTableAddress + /// BX =3D Allocation region + /// 00 =3D Allocate from either 0xE0000 or 0xF0000 64 KB blocks. + /// Bit 0 =3D 1 Allocate from 0xF0000 64 KB block + /// Bit 1 =3D 1 Allocate from 0xE0000 64 KB block + /// CX =3D Requested length in bytes. + /// DX =3D Required address alignment. Bit mapped. First non-zero bit = from the right is the alignment. + /// Output: + /// AX =3D Returned status codes + /// DS:BX =3D Address of the region + /// + Legacy16GetTableAddress =3D 0x0006, + + /// + /// Enables the EfiCompatibility module to do any nonstandard processing= of keyboard LEDs or state. + /// Input: + /// AX =3D Compatibility16SetKeyboardLeds + /// CL =3D LED status. + /// Bit 0 Scroll Lock 0 =3D Off + /// Bit 1 NumLock + /// Bit 2 Caps Lock + /// Output: + /// AX =3D Returned status codes + /// + Legacy16SetKeyboardLeds =3D 0x0007, + + /// + /// Enables the EfiCompatibility module to install an interrupt handler = for PCI mass media devices that + /// do not have an OpROM associated with them. An example is SATA. + /// Input: + /// AX =3D Compatibility16InstallPciHandler + /// ES:BX =3D Pointer to EFI_LEGACY_INSTALL_PCI_HANDLER structure + /// Output: + /// AX =3D Returned status codes + /// + Legacy16InstallPciHandler =3D 0x0008 +} EFI_COMPATIBILITY_FUNCTIONS; + + +/// +/// EFI_DISPATCH_OPROM_TABLE +/// +typedef struct { + UINT16 PnPInstallationCheckSegment; ///< A pointer to the PnpInstallat= ionCheck data structure. + UINT16 PnPInstallationCheckOffset; ///< A pointer to the PnpInstallat= ionCheck data structure. + UINT16 OpromSegment; ///< The segment where the OpROM w= as placed. Offset is assumed to be 3. + UINT8 PciBus; ///< The PCI bus. + UINT8 PciDeviceFunction; ///< The PCI device * 0x08 | PCI f= unction. + UINT8 NumberBbsEntries; ///< The number of valid BBS table= entries upon entry and exit. The IBV code may + ///< increase this number, if BBS-= compliant devices also hook INTs in order to force the + ///< OpROM BIOS Setup to be execut= ed. + UINT32 BbsTablePointer; ///< A pointer to the BBS table. + UINT16 RuntimeSegment; ///< The segment where the OpROM c= an be relocated to. If this value is 0x0000, this + ///< means that the relocation of = this run time code is not supported. + ///< Inconsistent with specificati= on here: + ///< The member's name "OpromDesti= nationSegment" [defined in Intel Framework Compatibility Support Module Spe= cification / 0.97 version] + ///< has been changed to "RuntimeS= egment" since keeping backward compatible. + +} EFI_DISPATCH_OPROM_TABLE; + +/// +/// EFI_TO_COMPATIBILITY16_INIT_TABLE +/// +typedef struct { + /// + /// Starting address of memory under 1 MB. The ending address is assumed= to be 640 KB or 0x9FFFF. + /// + UINT32 BiosLessThan1MB; + + /// + /// The starting address of the high memory block. + /// + UINT32 HiPmmMemory; + + /// + /// The length of high memory block. + /// + UINT32 HiPmmMemorySizeInBytes; + + /// + /// The segment of the reverse thunk call code. + /// + UINT16 ReverseThunkCallSegment; + + /// + /// The offset of the reverse thunk call code. + /// + UINT16 ReverseThunkCallOffset; + + /// + /// The number of E820 entries copied to the Compatibility16 BIOS. + /// + UINT32 NumberE820Entries; + + /// + /// The amount of usable memory above 1 MB, e.g., E820 type 1 memory. + /// + UINT32 OsMemoryAbove1Mb; + + /// + /// The start of thunk code in main memory. Memory cannot be used by BIO= S or PMM. + /// + UINT32 ThunkStart; + + /// + /// The size of the thunk code. + /// + UINT32 ThunkSizeInBytes; + + /// + /// Starting address of memory under 1 MB. + /// + UINT32 LowPmmMemory; + + /// + /// The length of low Memory block. + /// + UINT32 LowPmmMemorySizeInBytes; +} EFI_TO_COMPATIBILITY16_INIT_TABLE; + +/// +/// DEVICE_PRODUCER_SERIAL. +/// +typedef struct { + UINT16 Address; ///< I/O address assigned = to the serial port. + UINT8 Irq; ///< IRQ assigned to the s= erial port. + SERIAL_MODE Mode; ///< Mode of serial port. = Values are defined below. +} DEVICE_PRODUCER_SERIAL; + +/// +/// DEVICE_PRODUCER_SERIAL's modes. +///@{ +#define DEVICE_SERIAL_MODE_NORMAL 0x00 +#define DEVICE_SERIAL_MODE_IRDA 0x01 +#define DEVICE_SERIAL_MODE_ASK_IR 0x02 +#define DEVICE_SERIAL_MODE_DUPLEX_HALF 0x00 +#define DEVICE_SERIAL_MODE_DUPLEX_FULL 0x10 +///@) + +/// +/// DEVICE_PRODUCER_PARALLEL. +/// +typedef struct { + UINT16 Address; ///< I/O address assigned to= the parallel port. + UINT8 Irq; ///< IRQ assigned to the par= allel port. + UINT8 Dma; ///< DMA assigned to the par= allel port. + PARALLEL_MODE Mode; ///< Mode of the parallel po= rt. Values are defined below. +} DEVICE_PRODUCER_PARALLEL; + +/// +/// DEVICE_PRODUCER_PARALLEL's modes. +///@{ +#define DEVICE_PARALLEL_MODE_MODE_OUTPUT_ONLY 0x00 +#define DEVICE_PARALLEL_MODE_MODE_BIDIRECTIONAL 0x01 +#define DEVICE_PARALLEL_MODE_MODE_EPP 0x02 +#define DEVICE_PARALLEL_MODE_MODE_ECP 0x03 +///@} + +/// +/// DEVICE_PRODUCER_FLOPPY +/// +typedef struct { + UINT16 Address; ///< I/O address ass= igned to the floppy. + UINT8 Irq; ///< IRQ assigned to= the floppy. + UINT8 Dma; ///< DMA assigned to= the floppy. + UINT8 NumberOfFloppy; ///< Number of flopp= ies in the system. +} DEVICE_PRODUCER_FLOPPY; + +/// +/// LEGACY_DEVICE_FLAGS +/// +typedef struct { + UINT32 A20Kybd : 1; ///< A20 controller = by keyboard controller. + UINT32 A20Port90 : 1; ///< A20 controlled = by port 0x92. + UINT32 Reserved : 30; ///< Reserved for fu= ture usage. +} LEGACY_DEVICE_FLAGS; + +/// +/// DEVICE_PRODUCER_DATA_HEADER +/// +typedef struct { + DEVICE_PRODUCER_SERIAL Serial[4]; ///< Data for serial p= ort x. Type DEVICE_PRODUCER_SERIAL is defined below. + DEVICE_PRODUCER_PARALLEL Parallel[3]; ///< Data for parallel= port x. Type DEVICE_PRODUCER_PARALLEL is defined below. + DEVICE_PRODUCER_FLOPPY Floppy; ///< Data for floppy. = Type DEVICE_PRODUCER_FLOPPY is defined below. + UINT8 MousePresent; ///< Flag to indicate = if mouse is present. + LEGACY_DEVICE_FLAGS Flags; ///< Miscellaneous Boo= lean state information passed to CSM. +} DEVICE_PRODUCER_DATA_HEADER; + +/// +/// ATAPI_IDENTIFY +/// +typedef struct { + UINT16 Raw[256]; ///< Raw data from the I= DE IdentifyDrive command. +} ATAPI_IDENTIFY; + +/// +/// HDD_INFO +/// +typedef struct { + /// + /// Status of IDE device. Values are defined below. There is one HDD_INF= O structure + /// per IDE controller. The IdentifyDrive is per drive. Index 0 is maste= r and index + /// 1 is slave. + /// + UINT16 Status; + + /// + /// PCI bus of IDE controller. + /// + UINT32 Bus; + + /// + /// PCI device of IDE controller. + /// + UINT32 Device; + + /// + /// PCI function of IDE controller. + /// + UINT32 Function; + + /// + /// Command ports base address. + /// + UINT16 CommandBaseAddress; + + /// + /// Control ports base address. + /// + UINT16 ControlBaseAddress; + + /// + /// Bus master address. + /// + UINT16 BusMasterAddress; + + UINT8 HddIrq; + + /// + /// Data that identifies the drive data; one per possible attached drive. + /// + ATAPI_IDENTIFY IdentifyDrive[2]; +} HDD_INFO; + +/// +/// HDD_INFO status bits +/// +#define HDD_PRIMARY 0x01 +#define HDD_SECONDARY 0x02 +#define HDD_MASTER_ATAPI_CDROM 0x04 +#define HDD_SLAVE_ATAPI_CDROM 0x08 +#define HDD_MASTER_IDE 0x20 +#define HDD_SLAVE_IDE 0x40 +#define HDD_MASTER_ATAPI_ZIPDISK 0x10 +#define HDD_SLAVE_ATAPI_ZIPDISK 0x80 + +/// +/// BBS_STATUS_FLAGS;\. +/// +typedef struct { + UINT16 OldPosition : 4; ///< Prior priorit= y. + UINT16 Reserved1 : 4; ///< Reserved for = future use. + UINT16 Enabled : 1; ///< If 0, ignore = this entry. + UINT16 Failed : 1; ///< 0 =3D Not kno= wn if boot failure occurred. + ///< 1 =3D Boot at= tempted failed. + + /// + /// State of media present. + /// 00 =3D No bootable media is present in the device. + /// 01 =3D Unknown if a bootable media present. + /// 10 =3D Media is present and appears bootable. + /// 11 =3D Reserved. + /// + UINT16 MediaPresent : 2; + UINT16 Reserved2 : 4; ///< Reserved for = future use. +} BBS_STATUS_FLAGS; + +/// +/// BBS_TABLE, device type values & boot priority values. +/// +typedef struct { + /// + /// The boot priority for this boot device. Values are defined below. + /// + UINT16 BootPriority; + + /// + /// The PCI bus for this boot device. + /// + UINT32 Bus; + + /// + /// The PCI device for this boot device. + /// + UINT32 Device; + + /// + /// The PCI function for the boot device. + /// + UINT32 Function; + + /// + /// The PCI class for this boot device. + /// + UINT8 Class; + + /// + /// The PCI Subclass for this boot device. + /// + UINT8 SubClass; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= e manufacturer. + /// + UINT16 MfgStringOffset; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= e manufacturer. + /// + UINT16 MfgStringSegment; + + /// + /// BBS device type. BBS device types are defined below. + /// + UINT16 DeviceType; + + /// + /// Status of this boot device. Type BBS_STATUS_FLAGS is defined below. + /// + BBS_STATUS_FLAGS StatusFlags; + + /// + /// Segment:Offset address of boot loader for IPL devices or install INT= 13 handler for + /// BCV devices. + /// + UINT16 BootHandlerOffset; + + /// + /// Segment:Offset address of boot loader for IPL devices or install INT= 13 handler for + /// BCV devices. + /// + UINT16 BootHandlerSegment; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= is device. + /// + UINT16 DescStringOffset; + + /// + /// Segment:offset address of an ASCIIZ description string describing th= is device. + /// + UINT16 DescStringSegment; + + /// + /// Reserved. + /// + UINT32 InitPerReserved; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq13Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq18Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq19Handler; + + /// + /// The use of these fields is IBV dependent. They can be used to flag t= hat an OpROM + /// has hooked the specified IRQ. The OpROM may be BBS compliant as some= SCSI + /// BBS-compliant OpROMs also hook IRQ vectors in order to run their BIO= S Setup + /// + UINT32 AdditionalIrq40Handler; + UINT8 AssignedDriveNumber; + UINT32 AdditionalIrq41Handler; + UINT32 AdditionalIrq46Handler; + UINT32 IBV1; + UINT32 IBV2; +} BBS_TABLE; + +/// +/// BBS device type values +///@{ +#define BBS_FLOPPY 0x01 +#define BBS_HARDDISK 0x02 +#define BBS_CDROM 0x03 +#define BBS_PCMCIA 0x04 +#define BBS_USB 0x05 +#define BBS_EMBED_NETWORK 0x06 +#define BBS_BEV_DEVICE 0x80 +#define BBS_UNKNOWN 0xff +///@} + +/// +/// BBS boot priority values +///@{ +#define BBS_DO_NOT_BOOT_FROM 0xFFFC +#define BBS_LOWEST_PRIORITY 0xFFFD +#define BBS_UNPRIORITIZED_ENTRY 0xFFFE +#define BBS_IGNORE_ENTRY 0xFFFF +///@} + +/// +/// SMM_ATTRIBUTES +/// +typedef struct { + /// + /// Access mechanism used to generate the soft SMI. Defined types are be= low. The other + /// values are reserved for future usage. + /// + UINT16 Type : 3; + + /// + /// The size of "port" in bits. Defined values are below. + /// + UINT16 PortGranularity : 3; + + /// + /// The size of data in bits. Defined values are below. + /// + UINT16 DataGranularity : 3; + + /// + /// Reserved for future use. + /// + UINT16 Reserved : 7; +} SMM_ATTRIBUTES; + +/// +/// SMM_ATTRIBUTES type values. +///@{ +#define STANDARD_IO 0x00 +#define STANDARD_MEMORY 0x01 +///@} + +/// +/// SMM_ATTRIBUTES port size constants. +///@{ +#define PORT_SIZE_8 0x00 +#define PORT_SIZE_16 0x01 +#define PORT_SIZE_32 0x02 +#define PORT_SIZE_64 0x03 +///@} + +/// +/// SMM_ATTRIBUTES data size constants. +///@{ +#define DATA_SIZE_8 0x00 +#define DATA_SIZE_16 0x01 +#define DATA_SIZE_32 0x02 +#define DATA_SIZE_64 0x03 +///@} + +/// +/// SMM_FUNCTION & relating constants. +/// +typedef struct { + UINT16 Function : 15; + UINT16 Owner : 1; +} SMM_FUNCTION; + +/// +/// SMM_FUNCTION Function constants. +///@{ +#define INT15_D042 0x0000 +#define GET_USB_BOOT_INFO 0x0001 +#define DMI_PNP_50_57 0x0002 +///@} + +/// +/// SMM_FUNCTION Owner constants. +///@{ +#define STANDARD_OWNER 0x0 +#define OEM_OWNER 0x1 +///@} + +/// +/// This structure assumes both port and data sizes are 1. SmmAttribute mu= st be +/// properly to reflect that assumption. +/// +typedef struct { + /// + /// Describes the access mechanism, SmmPort, and SmmData sizes. Type + /// SMM_ATTRIBUTES is defined below. + /// + SMM_ATTRIBUTES SmmAttributes; + + /// + /// Function Soft SMI is to perform. Type SMM_FUNCTION is defined below. + /// + SMM_FUNCTION SmmFunction; + + /// + /// SmmPort size depends upon SmmAttributes and ranges from2 bytes to 16= bytes. + /// + UINT8 SmmPort; + + /// + /// SmmData size depends upon SmmAttributes and ranges from2 bytes to 16= bytes. + /// + UINT8 SmmData; +} SMM_ENTRY; + +/// +/// SMM_TABLE +/// +typedef struct { + UINT16 NumSmmEntries; ///< Number of entri= es represented by SmmEntry. + SMM_ENTRY SmmEntry; ///< One entry per f= unction. Type SMM_ENTRY is defined below. +} SMM_TABLE; + +/// +/// UDC_ATTRIBUTES +/// +typedef struct { + /// + /// This bit set indicates that the ServiceAreaData is valid. + /// + UINT8 DirectoryServiceValidity : 1; + + /// + /// This bit set indicates to use the Reserve Area Boot Code Address (RA= CBA) only if + /// DirectoryServiceValidity is 0. + /// + UINT8 RabcaUsedFlag : 1; + + /// + /// This bit set indicates to execute hard disk diagnostics. + /// + UINT8 ExecuteHddDiagnosticsFlag : 1; + + /// + /// Reserved for future use. Set to 0. + /// + UINT8 Reserved : 5; +} UDC_ATTRIBUTES; + +/// +/// UD_TABLE +/// +typedef struct { + /// + /// This field contains the bit-mapped attributes of the PARTIES informa= tion. Type + /// UDC_ATTRIBUTES is defined below. + /// + UDC_ATTRIBUTES Attributes; + + /// + /// This field contains the zero-based device on which the selected + /// ServiceDataArea is present. It is 0 for master and 1 for the slave d= evice. + /// + UINT8 DeviceNumber; + + /// + /// This field contains the zero-based index into the BbsTable for the p= arent device. + /// This index allows the user to reference the parent device informatio= n such as PCI + /// bus, device function. + /// + UINT8 BbsTableEntryNumberForParentDevice; + + /// + /// This field contains the zero-based index into the BbsTable for the b= oot entry. + /// + UINT8 BbsTableEntryNumberForBoot; + + /// + /// This field contains the zero-based index into the BbsTable for the H= DD diagnostics entry. + /// + UINT8 BbsTableEntryNumberForHddDiag; + + /// + /// The raw Beer data. + /// + UINT8 BeerData[128]; + + /// + /// The raw data of selected service area. + /// + UINT8 ServiceAreaData[64]; +} UD_TABLE; + +#define EFI_TO_LEGACY_MAJOR_VERSION 0x02 +#define EFI_TO_LEGACY_MINOR_VERSION 0x00 +#define MAX_IDE_CONTROLLER 8 + +/// +/// EFI_TO_COMPATIBILITY16_BOOT_TABLE +/// +typedef struct { + UINT16 MajorVersion; ///< The= EfiCompatibility major version number. + UINT16 MinorVersion; ///< The= EfiCompatibility minor version number. + UINT32 AcpiTable; ///< The= location of the RSDT ACPI table. < 4G range. + UINT32 SmbiosTable; ///< The= location of the SMBIOS table in EFI memory. < 4G range. + UINT32 SmbiosTableLength; + // + // Legacy SIO state + // + DEVICE_PRODUCER_DATA_HEADER SioData; ///< Sta= ndard traditional device information. + UINT16 DevicePathType; ///< The= default boot type. + UINT16 PciIrqMask; ///< Mas= k of which IRQs have been assigned to PCI. + UINT32 NumberE820Entries; ///< Num= ber of E820 entries. The number can change from the + ///< Com= patibility16InitializeYourself() function. + // + // Controller & Drive Identify[2] per controller information + // + HDD_INFO HddInfo[MAX_IDE_CONTROLLER]; ///< Har= d disk drive information, including raw Identify Drive data. + UINT32 NumberBbsEntries; ///< Num= ber of entries in the BBS table + UINT32 BbsTable; ///< A p= ointer to the BBS table. Type BBS_TABLE is defined below. + UINT32 SmmTable; ///< A p= ointer to the SMM table. Type SMM_TABLE is defined below. + UINT32 OsMemoryAbove1Mb; ///< The= amount of usable memory above 1 MB, i.e. E820 type 1 memory. This value can + ///< dif= fer from the value in EFI_TO_COMPATIBILITY16_INIT_TABLE as more + ///< mem= ory may have been discovered. + UINT32 UnconventionalDeviceTable; ///< Inf= ormation to boot off an unconventional device like a PARTIES partition. Type + ///< UD_= TABLE is defined below. +} EFI_TO_COMPATIBILITY16_BOOT_TABLE; + +/// +/// EFI_LEGACY_INSTALL_PCI_HANDLER +/// +typedef struct { + UINT8 PciBus; ///< The PCI bus o= f the device. + UINT8 PciDeviceFun; ///< The PCI devic= e in bits 7:3 and function in bits 2:0. + UINT8 PciSegment; ///< The PCI segme= nt of the device. + UINT8 PciClass; ///< The PCI class= code of the device. + UINT8 PciSubclass; ///< The PCI subcl= ass code of the device. + UINT8 PciInterface; ///< The PCI inter= face code of the device. + // + // Primary section + // + UINT8 PrimaryIrq; ///< The primary d= evice IRQ. + UINT8 PrimaryReserved; ///< Reserved. + UINT16 PrimaryControl; ///< The primary d= evice control I/O base. + UINT16 PrimaryBase; ///< The primary d= evice I/O base. + UINT16 PrimaryBusMaster; ///< The primary d= evice bus master I/O base. + // + // Secondary Section + // + UINT8 SecondaryIrq; ///< The secondary= device IRQ. + UINT8 SecondaryReserved; ///< Reserved. + UINT16 SecondaryControl; ///< The secondary= device control I/O base. + UINT16 SecondaryBase; ///< The secondary= device I/O base. + UINT16 SecondaryBusMaster; ///< The secondary= device bus master I/O base. +} EFI_LEGACY_INSTALL_PCI_HANDLER; + +// +// Restore default pack value +// +#pragma pack() + +#define EFI_LEGACY_BIOS_PROTOCOL_GUID \ + { \ + 0xdb9a1e3d, 0x45cb, 0x4abb, {0x85, 0x3b, 0xe5, 0x38, 0x7f, 0xdb, 0x2e,= 0x2d } \ + } + +typedef struct _EFI_LEGACY_BIOS_PROTOCOL EFI_LEGACY_BIOS_PROTOCOL; + +/// +/// Flags returned by CheckPciRom(). +/// +#define NO_ROM 0x00 +#define ROM_FOUND 0x01 +#define VALID_LEGACY_ROM 0x02 +#define ROM_WITH_CONFIG 0x04 ///< Not defined in the Framework CSM S= pecification. + +/// +/// The following macros do not appear in the Framework CSM Specification = and +/// are kept for backward compatibility only. They convert 32-bit address= (_Adr) +/// to Segment:Offset 16-bit form. +/// +///@{ +#define EFI_SEGMENT(_Adr) (UINT16) ((UINT16) (((UINTN) (_Adr)) >> 4) &= 0xf000) +#define EFI_OFFSET(_Adr) (UINT16) (((UINT16) ((UINTN) (_Adr))) & 0xff= ff) +///@} + +#define CARRY_FLAG 0x01 + +/// +/// EFI_EFLAGS_REG +/// +typedef struct { + UINT32 CF:1; + UINT32 Reserved1:1; + UINT32 PF:1; + UINT32 Reserved2:1; + UINT32 AF:1; + UINT32 Reserved3:1; + UINT32 ZF:1; + UINT32 SF:1; + UINT32 TF:1; + UINT32 IF:1; + UINT32 DF:1; + UINT32 OF:1; + UINT32 IOPL:2; + UINT32 NT:1; + UINT32 Reserved4:2; + UINT32 VM:1; + UINT32 Reserved5:14; +} EFI_EFLAGS_REG; + +/// +/// EFI_DWORD_REGS +/// +typedef struct { + UINT32 EAX; + UINT32 EBX; + UINT32 ECX; + UINT32 EDX; + UINT32 ESI; + UINT32 EDI; + EFI_EFLAGS_REG EFlags; + UINT16 ES; + UINT16 CS; + UINT16 SS; + UINT16 DS; + UINT16 FS; + UINT16 GS; + UINT32 EBP; + UINT32 ESP; +} EFI_DWORD_REGS; + +/// +/// EFI_FLAGS_REG +/// +typedef struct { + UINT16 CF:1; + UINT16 Reserved1:1; + UINT16 PF:1; + UINT16 Reserved2:1; + UINT16 AF:1; + UINT16 Reserved3:1; + UINT16 ZF:1; + UINT16 SF:1; + UINT16 TF:1; + UINT16 IF:1; + UINT16 DF:1; + UINT16 OF:1; + UINT16 IOPL:2; + UINT16 NT:1; + UINT16 Reserved4:1; +} EFI_FLAGS_REG; + +/// +/// EFI_WORD_REGS +/// +typedef struct { + UINT16 AX; + UINT16 ReservedAX; + UINT16 BX; + UINT16 ReservedBX; + UINT16 CX; + UINT16 ReservedCX; + UINT16 DX; + UINT16 ReservedDX; + UINT16 SI; + UINT16 ReservedSI; + UINT16 DI; + UINT16 ReservedDI; + EFI_FLAGS_REG Flags; + UINT16 ReservedFlags; + UINT16 ES; + UINT16 CS; + UINT16 SS; + UINT16 DS; + UINT16 FS; + UINT16 GS; + UINT16 BP; + UINT16 ReservedBP; + UINT16 SP; + UINT16 ReservedSP; +} EFI_WORD_REGS; + +/// +/// EFI_BYTE_REGS +/// +typedef struct { + UINT8 AL, AH; + UINT16 ReservedAX; + UINT8 BL, BH; + UINT16 ReservedBX; + UINT8 CL, CH; + UINT16 ReservedCX; + UINT8 DL, DH; + UINT16 ReservedDX; +} EFI_BYTE_REGS; + +/// +/// EFI_IA32_REGISTER_SET +/// +typedef union { + EFI_DWORD_REGS E; + EFI_WORD_REGS X; + EFI_BYTE_REGS H; +} EFI_IA32_REGISTER_SET; + +/** + Thunk to 16-bit real mode and execute a software interrupt with a vector + of BiosInt. Regs will contain the 16-bit register context on entry and + exit. + + @param[in] This The protocol instance pointer. + @param[in] BiosInt The processor interrupt vector to invoke. + @param[in,out] Reg Register contexted passed into (and returned) f= rom thunk to + 16-bit mode. + + @retval TRUE Thunk completed with no BIOS errors in the t= arget code. See Regs for status. + @retval FALSE There was a BIOS error in the target code. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_LEGACY_BIOS_INT86)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT8 BiosInt, + IN OUT EFI_IA32_REGISTER_SET *Regs + ); + +/** + Thunk to 16-bit real mode and call Segment:Offset. Regs will contain the + 16-bit register context on entry and exit. Arguments can be passed on + the Stack argument + + @param[in] This The protocol instance pointer. + @param[in] Segment The segemnt of 16-bit mode call. + @param[in] Offset The offset of 16-bit mdoe call. + @param[in] Reg Register contexted passed into (and returned) fro= m thunk to + 16-bit mode. + @param[in] Stack The caller allocated stack used to pass arguments. + @param[in] StackSize The size of Stack in bytes. + + @retval FALSE Thunk completed with no BIOS errors in the= target code. See Regs for status. @retval = TRUE There was a BIOS error in the target code. +**/ +typedef +BOOLEAN +(EFIAPI *EFI_LEGACY_BIOS_FARCALL86)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT16 Segment, + IN UINT16 Offset, + IN EFI_IA32_REGISTER_SET *Regs, + IN VOID *Stack, + IN UINTN StackSize + ); + +/** + Test to see if a legacy PCI ROM exists for this device. Optionally return + the Legacy ROM instance for this PCI device. + + @param[in] This The protocol instance pointer. + @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM BAR wi= ll be loaded + @param[out] RomImage Return the legacy PCI ROM for this device. + @param[out] RomSize The size of ROM Image. + @param[out] Flags Indicates if ROM found and if PC-AT. Multiple bi= ts can be set as follows: + - 00 =3D No ROM. + - 01 =3D ROM Found. + - 02 =3D ROM is a valid legacy ROM. + + @retval EFI_SUCCESS The Legacy Option ROM available for this device + @retval EFI_UNSUPPORTED The Legacy Option ROM is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_CHECK_ROM)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, OPTIONAL + OUT UINTN *RomSize, OPTIONAL + OUT UINTN *Flags + ); + +/** + Load a legacy PC-AT OPROM on the PciHandle device. Return information + about how many disks were added by the OPROM and the shadow address and + size. DiskStart & DiskEnd are INT 13h drive letters. Thus 0x80 is C: + + @param[in] This The protocol instance pointer. + @param[in] PciHandle The PCI PC-AT OPROM from this devices ROM= BAR will be loaded. + This value is NULL if RomImage is non-NUL= L. This is the normal + case. + @param[in] RomImage A PCI PC-AT ROM image. This argument is n= on-NULL if there is + no hardware associated with the ROM and t= hus no PciHandle, + otherwise is must be NULL. + Example is PXE base code. + @param[out] Flags The type of ROM discovered. Multiple bits= can be set, as follows: + - 00 =3D No ROM. + - 01 =3D ROM found. + - 02 =3D ROM is a valid legacy ROM. + @param[out] DiskStart The disk number of first device hooked by= the ROM. If DiskStart + is the same as DiskEnd no disked were hoo= ked. + @param[out] DiskEnd disk number of the last device hooked by = the ROM. + @param[out] RomShadowAddress Shadow address of PC-AT ROM. + @param[out] RomShadowSize Size of RomShadowAddress in bytes. + + @retval EFI_SUCCESS Thunk completed, see Regs for status. + @retval EFI_INVALID_PARAMETER PciHandle not found + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_INSTALL_ROM)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + IN VOID **RomImage, + OUT UINTN *Flags, + OUT UINT8 *DiskStart, OPTIONAL + OUT UINT8 *DiskEnd, OPTIONAL + OUT VOID **RomShadowAddress, OPTIONAL + OUT UINT32 *ShadowedRomSize OPTIONAL + ); + +/** + This function attempts to traditionally boot the specified BootOption. I= f the EFI context has + been compromised, this function will not return. This procedure is not u= sed for loading an EFI-aware + OS off a traditional device. The following actions occur: + - Get EFI SMBIOS data structures, convert them to a traditional format, = and copy to + Compatibility16. + - Get a pointer to ACPI data structures and copy the Compatibility16 RSD= PTR to F0000 block. + - Find the traditional SMI handler from a firmware volume and register t= he traditional SMI + handler with the EFI SMI handler. + - Build onboard IDE information and pass this information to the Compati= bility16 code. + - Make sure all PCI Interrupt Line registers are programmed to match 825= 9. + - Reconfigure SIO devices from EFI mode (polled) into traditional mode (= interrupt driven). + - Shadow all PCI ROMs. + - Set up BDA and EBDA standard areas before the legacy boot. + - Construct the Compatibility16 boot memory map and pass it to the Compa= tibility16 code. + - Invoke the Compatibility16 table function Compatibility16PrepareToBoot= (). This + invocation causes a thunk into the Compatibility16 code, which sets al= l appropriate internal + data structures. The boot device list is a parameter. + - Invoke the Compatibility16 Table function Compatibility16Boot(). This = invocation + causes a thunk into the Compatibility16 code, which does an INT19. + - If the Compatibility16Boot() function returns, then the boot failed in= a graceful + manner--meaning that the EFI code is still valid. An ungraceful boot f= ailure causes a reset because the state + of EFI code is unknown. + + @param[in] This The protocol instance pointer. + @param[in] BootOption The EFI Device Path from BootXXXX variable. + @param[in] LoadOptionSize The size of LoadOption in size. + @param[in] LoadOption LThe oadOption from BootXXXX variable. + + @retval EFI_DEVICE_ERROR Failed to boot from any boot device and me= mory is uncorrupted. Note: This function nor= mally does not returns. It will either boot the = OS or reset the system if memory has been "corrupted" by loading = a boot sector and passing control to it. +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_BOOT)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN BBS_BBS_DEVICE_PATH *BootOption, + IN UINT32 LoadOptionsSize, + IN VOID *LoadOptions + ); + +/** + This function takes the Leds input parameter and sets/resets the BDA acc= ordingly. + Leds is also passed to Compatibility16 code, in case any special process= ing is required. + This function is normally called from EFI Setup drivers that handle user= -selectable + keyboard options such as boot with NUM LOCK on/off. This function does n= ot + touch the keyboard or keyboard LEDs but only the BDA. + + @param[in] This The protocol instance pointer. + @param[in] Leds The status of current Scroll, Num & Cap lock LEDS: + - Bit 0 is Scroll Lock 0 =3D Not locked. + - Bit 1 is Num Lock. + - Bit 2 is Caps Lock. + + @retval EFI_SUCCESS The BDA was updated successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINT8 Leds + ); + +/** + Retrieve legacy BBS info and assign boot priority. + + @param[in] This The protocol instance pointer. + @param[out] HddCount The number of HDD_INFO structures. + @param[out] HddInfo Onboard IDE controller information. + @param[out] BbsCount The number of BBS_TABLE structures. + @param[in,out] BbsTable Points to List of BBS_TABLE. + + @retval EFI_SUCCESS Tables were returned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_GET_BBS_INFO)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + OUT UINT16 *HddCount, + OUT HDD_INFO **HddInfo, + OUT UINT16 *BbsCount, + IN OUT BBS_TABLE **BbsTable + ); + +/** + Assign drive number to legacy HDD drives prior to booting an EFI + aware OS so the OS can access drives without an EFI driver. + + @param[in] This The protocol instance pointer. + @param[out] BbsCount The number of BBS_TABLE structures + @param[out] BbsTable List of BBS entries + + @retval EFI_SUCCESS Drive numbers assigned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + OUT UINT16 *BbsCount, + OUT BBS_TABLE **BbsTable + ); + +/** + To boot from an unconventional device like parties and/or execute + HDD diagnostics. + + @param[in] This The protocol instance pointer. + @param[in] Attributes How to interpret the other input parameter= s. + @param[in] BbsEntry The 0-based index into the BbsTable for th= e parent + device. + @param[in] BeerData A pointer to the 128 bytes of ram BEER dat= a. + @param[in] ServiceAreaData A pointer to the 64 bytes of raw Service A= rea data. The + caller must provide a pointer to the speci= fic Service + Area and not the start all Service Areas. + + @retval EFI_INVALID_PARAMETER If error. Does NOT return if no error. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UDC_ATTRIBUTES Attributes, + IN UINTN BbsEntry, + IN VOID *BeerData, + IN VOID *ServiceAreaData + ); + +/** + Shadow all legacy16 OPROMs that haven't been shadowed. + Warning: Use this with caution. This routine disconnects all EFI + drivers. If used externally, then the caller must re-connect EFI + drivers. + + @param[in] This The protocol instance pointer. + + @retval EFI_SUCCESS OPROMs were shadowed. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS)( + IN EFI_LEGACY_BIOS_PROTOCOL *This + ); + +/** + Get a region from the LegacyBios for S3 usage. + + @param[in] This The protocol instance pointer. + @param[in] LegacyMemorySize The size of required region. + @param[in] Region The region to use. + 00 =3D Either 0xE0000 or 0xF0000 block. + - Bit0 =3D 1 0xF0000 block. + - Bit1 =3D 1 0xE0000 block. + @param[in] Alignment Address alignment. Bit mapped. The fir= st non-zero + bit from right is alignment. + @param[out] LegacyMemoryAddress The Region Assigned + + @retval EFI_SUCCESS The Region was assigned. + @retval EFI_ACCESS_DENIED The function was previously invoked. + @retval Other The Region was not assigned. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_GET_LEGACY_REGION)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINTN LegacyMemorySize, + IN UINTN Region, + IN UINTN Alignment, + OUT VOID **LegacyMemoryAddress + ); + +/** + Get a region from the LegacyBios for Tiano usage. Can only be invoked on= ce. + + @param[in] This The protocol instance pointer. + @param[in] LegacyMemorySize The size of data to copy. + @param[in] LegacyMemoryAddress The Legacy Region destination ad= dress. + Note: must be in region assigned= by + LegacyBiosGetLegacyRegion. + @param[in] LegacyMemorySourceAddress The source of the data to copy. + + @retval EFI_SUCCESS The Region assigned. + @retval EFI_ACCESS_DENIED Destination was outside an assigned region. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_BIOS_COPY_LEGACY_REGION)( + IN EFI_LEGACY_BIOS_PROTOCOL *This, + IN UINTN LegacyMemorySize, + IN VOID *LegacyMemoryAddress, + IN VOID *LegacyMemorySourceAddress + ); + +/// +/// Abstracts the traditional BIOS from the rest of EFI. The LegacyBoot() +/// member function allows the BDS to support booting a traditional OS. +/// EFI thunks drivers that make EFI bindings for BIOS INT services use +/// all the other member functions. +/// +struct _EFI_LEGACY_BIOS_PROTOCOL { + /// + /// Performs traditional software INT. See the Int86() function descript= ion. + /// + EFI_LEGACY_BIOS_INT86 Int86; + + /// + /// Performs a far call into Compatibility16 or traditional OpROM code. + /// + EFI_LEGACY_BIOS_FARCALL86 FarCall86; + + /// + /// Checks if a traditional OpROM exists for this device. + /// + EFI_LEGACY_BIOS_CHECK_ROM CheckPciRom; + + /// + /// Loads a traditional OpROM in traditional OpROM address space. + /// + EFI_LEGACY_BIOS_INSTALL_ROM InstallPciRom; + + /// + /// Boots a traditional OS. + /// + EFI_LEGACY_BIOS_BOOT LegacyBoot; + + /// + /// Updates BDA to reflect the current EFI keyboard LED status. + /// + EFI_LEGACY_BIOS_UPDATE_KEYBOARD_LED_STATUS UpdateKeyboardLedStatus; + + /// + /// Allows an external agent, such as BIOS Setup, to get the BBS data. + /// + EFI_LEGACY_BIOS_GET_BBS_INFO GetBbsInfo; + + /// + /// Causes all legacy OpROMs to be shadowed. + /// + EFI_LEGACY_BIOS_SHADOW_ALL_LEGACY_OPROMS ShadowAllLegacyOproms; + + /// + /// Performs all actions prior to boot. Used when booting an EFI-aware OS + /// rather than a legacy OS. + /// + EFI_LEGACY_BIOS_PREPARE_TO_BOOT_EFI PrepareToBootEfi; + + /// + /// Allows EFI to reserve an area in the 0xE0000 or 0xF0000 block. + /// + EFI_LEGACY_BIOS_GET_LEGACY_REGION GetLegacyRegion; + + /// + /// Allows EFI to copy data to the area specified by GetLegacyRegion. + /// + EFI_LEGACY_BIOS_COPY_LEGACY_REGION CopyLegacyRegion; + + /// + /// Allows the user to boot off an unconventional device such as a PARTI= ES partition. + /// + EFI_LEGACY_BIOS_BOOT_UNCONVENTIONAL_DEVICE BootUnconventionalDevice; +}; + +extern EFI_GUID gEfiLegacyBiosProtocolGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPk= g/Include/Protocol/LegacyInterrupt.h b/Silicon/Intel/CoffeelakeSiliconPkg/S= ampleCode/IntelFrameworkPkg/Include/Protocol/LegacyInterrupt.h new file mode 100644 index 0000000000..1d776793d2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/IntelFrameworkPkg/Inclu= de/Protocol/LegacyInterrupt.h @@ -0,0 +1,118 @@ +/** @file + This protocol abstracts the PIRQ programming from the generic EFI Compat= ibility Support Modules (CSMs). + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _EFI_LEGACY_INTERRUPT_H_ +#define _EFI_LEGACY_INTERRUPT_H_ + + +#define EFI_LEGACY_INTERRUPT_PROTOCOL_GUID \ + { \ + 0x31ce593d, 0x108a, 0x485d, {0xad, 0xb2, 0x78, 0xf2, 0x1f, 0x29, 0x66,= 0xbe } \ + } + +typedef struct _EFI_LEGACY_INTERRUPT_PROTOCOL EFI_LEGACY_INTERRUPT_PROTOCO= L; + +/** + Get the number of PIRQs this hardware supports. + + @param This The protocol instance pointer. + @param NumberPirsq The number of PIRQs that are supported. + + @retval EFI_SUCCESS The number of PIRQs was returned successfu= lly. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_INTERRUPT_GET_NUMBER_PIRQS)( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + OUT UINT8 *NumberPirqs + ); + +/** + Gets the PCI location associated with this protocol. + + @param This The Protocol instance pointer. + @param Bus The PCI Bus. + @param Device The PCI Device. + @param Function The PCI Function. + + @retval EFI_SUCCESS The Bus, Device, and Function were returne= d successfully. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_INTERRUPT_GET_LOCATION)( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + OUT UINT8 *Bus, + OUT UINT8 *Device, + OUT UINT8 *Function + ); + +/** + Read the PIRQ register and return the data + + @param This The protocol instance pointer. + @param PirqNumber The PIRQ register to read. + @param PirqData The data read. + + @retval EFI_SUCCESS The data was read. + @retval EFI_INVALID_PARAMETER Invalid PIRQ number. + @retval EFI_DEVICE_ERROR Operation was unsuccessful +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_INTERRUPT_READ_PIRQ)( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + IN UINT8 PirqNumber, + OUT UINT8 *PirqData + ); + +/** + Write the specified PIRQ register with the given data. + + @param This The protocol instance pointer. + @param PirqNumber A PIRQ register to read. + @param PirqData The data to write. + + @retval EFI_SUCCESS The PIRQ was programmed. + @retval EFI_INVALID_PARAMETER Invalid PIRQ number. + @retval EFI_DEVICE_ERROR Operation was unsuccessful +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_LEGACY_INTERRUPT_WRITE_PIRQ)( + IN EFI_LEGACY_INTERRUPT_PROTOCOL *This, + IN UINT8 PirqNumber, + IN UINT8 PirqData + ); + +struct _EFI_LEGACY_INTERRUPT_PROTOCOL { + /// + /// Gets the number of PIRQs supported. + /// + EFI_LEGACY_INTERRUPT_GET_NUMBER_PIRQS GetNumberPirqs; + + /// + /// Gets the PCI bus, device, and function that is associated with this = protocol. + /// + EFI_LEGACY_INTERRUPT_GET_LOCATION GetLocation; + + /// + /// Reads the indicated PIRQ register. + /// + EFI_LEGACY_INTERRUPT_READ_PIRQ ReadPirq; + + /// + /// Writes to the indicated PIRQ register. + /// + EFI_LEGACY_INTERRUPT_WRITE_PIRQ WritePirq; +}; + +extern EFI_GUID gEfiLegacyInterruptProtocolGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Inc= lude/Guid/AcpiS3Context.h b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/M= deModulePkg/Include/Guid/AcpiS3Context.h new file mode 100644 index 0000000000..c1d1fc89ec --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gu= id/AcpiS3Context.h @@ -0,0 +1,65 @@ +/** @file + Definitions for data structures used in S3 resume. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_S3_DATA_H_ +#define _ACPI_S3_DATA_H_ + +#include + +#define SMM_S3_RESUME_SMM_32 SIGNATURE_64 ('S','M','M','S','3','_','3','2') +#define SMM_S3_RESUME_SMM_64 SIGNATURE_64 ('S','M','M','S','3','_','6','4') + +#pragma pack(1) + +typedef struct { + UINT64 Signature; + EFI_PHYSICAL_ADDRESS SmmS3ResumeEntryPoint; + EFI_PHYSICAL_ADDRESS SmmS3StackBase; + UINT64 SmmS3StackSize; + UINT64 SmmS3Cr0; + UINT64 SmmS3Cr3; + UINT64 SmmS3Cr4; + UINT16 ReturnCs; + EFI_PHYSICAL_ADDRESS ReturnEntryPoint; + EFI_PHYSICAL_ADDRESS ReturnContext1; + EFI_PHYSICAL_ADDRESS ReturnContext2; + EFI_PHYSICAL_ADDRESS ReturnStackPointer; + EFI_PHYSICAL_ADDRESS Smst; +} SMM_S3_RESUME_STATE; + + +typedef struct { + EFI_PHYSICAL_ADDRESS AcpiFacsTable; + EFI_PHYSICAL_ADDRESS IdtrProfile; + EFI_PHYSICAL_ADDRESS S3NvsPageTableAddress; + EFI_PHYSICAL_ADDRESS BootScriptStackBase; + UINT64 BootScriptStackSize; + EFI_PHYSICAL_ADDRESS S3DebugBufferAddress; +} ACPI_S3_CONTEXT; + +typedef struct { + UINT16 ReturnCs; + UINT64 ReturnStatus; + EFI_PHYSICAL_ADDRESS ReturnEntryPoint; + EFI_PHYSICAL_ADDRESS ReturnStackPointer; + EFI_PHYSICAL_ADDRESS AsmTransferControl; + IA32_DESCRIPTOR Idtr; +} PEI_S3_RESUME_STATE; + +#pragma pack() + +#define EFI_ACPI_S3_CONTEXT_GUID \ + { \ + 0xef98d3a, 0x3e33, 0x497a, {0xa4, 0x1, 0x77, 0xbe, 0x3e, 0xb7, 0x4f, 0= x38} \ + } + +extern EFI_GUID gEfiAcpiS3ContextGuid; + +extern EFI_GUID gEfiAcpiVariableGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Inc= lude/Guid/ConsoleOutDevice.h b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCod= e/MdeModulePkg/Include/Guid/ConsoleOutDevice.h new file mode 100644 index 0000000000..c770101b38 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gu= id/ConsoleOutDevice.h @@ -0,0 +1,17 @@ +/** @file + This GUID can be installed to the device handle to specify that the devi= ce is the console-out device. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __CONSOLE_OUT_DEVICE_H__ +#define __CONSOLE_OUT_DEVICE_H__ + +#define EFI_CONSOLE_OUT_DEVICE_GUID \ + { 0xd3b36f2c, 0xd551, 0x11d4, {0x9a, 0x46, 0x0, 0x90, 0x27, 0x3f, 0xc1= , 0x4d } } + +extern EFI_GUID gEfiConsoleOutDeviceGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Inc= lude/Guid/MemoryTypeInformation.h b/Silicon/Intel/CoffeelakeSiliconPkg/Samp= leCode/MdeModulePkg/Include/Guid/MemoryTypeInformation.h new file mode 100644 index 0000000000..bf4b3cdeca --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Gu= id/MemoryTypeInformation.h @@ -0,0 +1,30 @@ +/** @file + This file defines: + * Memory Type Information GUID for HOB and Variable. + * Memory Type Information Variable Name. + * Memory Type Information GUID HOB data structure. + + The memory type information HOB and variable can + be used to store the information for each memory type in Variable or HOB. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __MEMORY_TYPE_INFORMATION_GUID_H__ +#define __MEMORY_TYPE_INFORMATION_GUID_H__ + +#define EFI_MEMORY_TYPE_INFORMATION_GUID \ + { 0x4c19049f,0x4137,0x4dd3, { 0x9c,0x10,0x8b,0x97,0xa8,0x3f,0xfd,0xfa } } + +#define EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME L"MemoryTypeInformation" + +extern EFI_GUID gEfiMemoryTypeInformationGuid; + +typedef struct { + UINT32 Type; ///< EFI memory type defined in UEFI specifica= tion. + UINT32 NumberOfPages; ///< The pages of this type memory. +} EFI_MEMORY_TYPE_INFORMATION; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Inc= lude/Library/ResetSystemLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCo= de/MdeModulePkg/Include/Library/ResetSystemLib.h new file mode 100644 index 0000000000..754865943e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Li= brary/ResetSystemLib.h @@ -0,0 +1,80 @@ +/** @file + System reset Library Services. This library class defines a set of + methods that reset the whole system. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __RESET_SYSTEM_LIB_H__ +#define __RESET_SYSTEM_LIB_H__ + +/** + This function causes a system-wide reset (cold reset), in which + all circuitry within the system returns to its initial state. This type = of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + If this function returns, it means that the system does not support cold= reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ); + +/** + This function causes a system-wide initialization (warm reset), in which= all processors + are set to their initial state. Pending cycles are not corrupted. + + If this function returns, it means that the system does not support warm= reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ); + +/** + This function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + If this function returns, it means that the system does not support shut= down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ); + +/** + This function causes the system to enter S3 and then wake up immediately. + + If this function returns, it means that the system does not support S3 f= eature. +**/ +VOID +EFIAPI +EnterS3WithImmediateWake ( + VOID + ); + +/** + This function causes a systemwide reset. The exact type of the reset is + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data + the platform must pick a supported reset type to perform.The platform may + optionally log the parameters from any non-normal reset that occurs. + + @param[in] DataSize The size, in bytes, of ResetData. + @param[in] ResetData The data buffer starts with a Null-terminated str= ing, + followed by the EFI_GUID. +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Inc= lude/Ppi/SmmAccess.h b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeMod= ulePkg/Include/Ppi/SmmAccess.h new file mode 100644 index 0000000000..565d35b654 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Pp= i/SmmAccess.h @@ -0,0 +1,137 @@ +/** @file + EFI SMM Access PPI definition. + + This PPI is used to control the visibility of the SMRAM on the platform. + It abstracts the location and characteristics of SMRAM. The expectation= is + that the north bridge or memory controller would publish this PPI. + + The principal functionality found in the memory controller includes the = following: + - Exposing the SMRAM to all non-SMM agents, or the "open" state + - Shrouding the SMRAM to all but the SMM agents, or the "closed" state + - Preserving the system integrity, or "locking" the SMRAM, such that the= settings cannot be + perturbed by either boot service or runtime agents + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SMM_ACCESS_PPI_H_ +#define _SMM_ACCESS_PPI_H_ + +#define PEI_SMM_ACCESS_PPI_GUID \ + { 0x268f33a9, 0xcccd, 0x48be, { 0x88, 0x17, 0x86, 0x5, 0x3a, 0xc3, 0x2e,= 0xd6 }} + +typedef struct _PEI_SMM_ACCESS_PPI PEI_SMM_ACCESS_PPI; + +/** + Opens the SMRAM area to be accessible by a PEIM driver. + + This function "opens" SMRAM so that it is visible while not inside of SM= M. The function should + return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM.= The function + should return EFI_DEVICE_ERROR if the SMRAM configuration is locked. + + @param PeiServices General purpose services available to eve= ry PEIM. + @param This The pointer to the SMM Access Interface. + @param DescriptorIndex The region of SMRAM to Open. + + @retval EFI_SUCCESS The region was successfully opened. + @retval EFI_DEVICE_ERROR The region could not be opened because lo= cked by chipset. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_OPEN)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + Inhibits access to the SMRAM. + + This function "closes" SMRAM so that it is not visible while outside of = SMM. The function should + return EFI_UNSUPPORTED if the hardware does not support hiding of SMRAM. + + @param PeiServices General purpose services available to e= very PEIM. + @param This The pointer to the SMM Access Interface. + @param DescriptorIndex The region of SMRAM to Close. + + @retval EFI_SUCCESS The region was successfully closed. + @retval EFI_DEVICE_ERROR The region could not be closed because = locked by chipset. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_CLOSE)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + Inhibits access to the SMRAM. + + This function prohibits access to the SMRAM region. This function is us= ually implemented such + that it is a write-once operation. + + @param PeiServices General purpose services available to e= very PEIM. + @param This The pointer to the SMM Access Interface. + @param DescriptorIndex The region of SMRAM to Close. + + @retval EFI_SUCCESS The region was successfully locked. + @retval EFI_DEVICE_ERROR The region could not be locked because at= least + one range is still open. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bounds. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_LOCK)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ); + +/** + Queries the memory controller for the possible regions that will support= SMRAM. + + @param PeiServices General purpose services available to ever= y PEIM. + @param This The pointer to the SmmAccessPpi Interface. + @param SmramMapSize The pointer to the variable containing siz= e of the + buffer to contain the description informat= ion. + @param SmramMap The buffer containing the data describing = the Smram + region descriptors. + + @retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient buff= er. + @retval EFI_SUCCESS The user provided a sufficiently-sized buf= fer. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_CAPABILITIES)( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap + ); + +/// +/// EFI SMM Access PPI is used to control the visibility of the SMRAM on = the platform. +/// It abstracts the location and characteristics of SMRAM. The expectat= ion is +/// that the north bridge or memory controller would publish this PPI. +/// +struct _PEI_SMM_ACCESS_PPI { + PEI_SMM_OPEN Open; + PEI_SMM_CLOSE Close; + PEI_SMM_LOCK Lock; + PEI_SMM_CAPABILITIES GetCapabilities; + BOOLEAN LockState; + BOOLEAN OpenState; +}; + +extern EFI_GUID gPeiSmmAccessPpiGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Inc= lude/Ppi/SmmControl.h b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeMo= dulePkg/Include/Ppi/SmmControl.h new file mode 100644 index 0000000000..e982c00bf4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Pp= i/SmmControl.h @@ -0,0 +1,87 @@ +/** @file + EFI SMM Control PPI definition. + + This PPI is used to initiate SMI/PMI activations. This protocol could be= published by either: + - A processor driver to abstract the SMI/PMI IPI + - The driver that abstracts the ASIC that is supporting the APM port, su= ch as the ICH in an + Intel chipset + Because of the possibility of performing SMI or PMI IPI transactions, th= e ability to generate this + event from a platform chipset agent is an optional capability for both I= A-32 and Itanium-based + systems. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SMM_CONTROL_PPI_H_ +#define _SMM_CONTROL_PPI_H_ + +#define PEI_SMM_CONTROL_PPI_GUID \ + { 0x61c68702, 0x4d7e, 0x4f43, 0x8d, 0xef, 0xa7, 0x43, 0x5, 0xce, 0x74, 0= xc5 } + +typedef struct _PEI_SMM_CONTROL_PPI PEI_SMM_CONTROL_PPI; + +/** + Invokes SMI activation from either the preboot or runtime environment. + + @param PeiServices General purpose services available to ever= y PEIM. + @param This The PEI_SMM_CONTROL_PPI instance. + @param ArgumentBuffer The optional sized data to pass into the p= rotocol activation. + @param ArgumentBufferSize The optional size of the data. + @param Periodic An optional mechanism to periodically repe= at activation. + @param ActivationInterval An optional parameter to repeat at this pe= riod one + time or, if the Periodic Boolean is set, p= eriodically. + + @retval EFI_SUCCESS The SMI/PMI has been engendered. + @retval EFI_DEVICE_ERROR The timing is unsupported. + @retval EFI_INVALID_PARAMETER The activation period is unsupported. + @retval EFI_NOT_STARTED The SMM base service has not been initiali= zed. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_ACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI * This, + IN OUT INT8 *ArgumentBuffer OPTIO= NAL, + IN OUT UINTN *ArgumentBufferSize O= PTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OP= TIONAL + ); + +/** + Clears any system state that was created in response to the Active call. + + @param PeiServices General purpose services available to ever= y PEIM. + @param This The PEI_SMM_CONTROL_PPI instance. + @param Periodic Optional parameter to repeat at this perio= d one + time or, if the Periodic Boolean is set, p= eriodically. + + @retval EFI_SUCCESS The SMI/PMI has been engendered. + @retval EFI_DEVICE_ERROR The source could not be cleared. + @retval EFI_INVALID_PARAMETER The service did not support the Periodic i= nput argument. + +**/ +typedef +EFI_STATUS +(EFIAPI *PEI_SMM_DEACTIVATE) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI * This, + IN BOOLEAN Periodic OPTIONAL + ); + +/// +/// PEI SMM Control PPI is used to initiate SMI/PMI activations. This pro= tocol could be published by either: +/// - A processor driver to abstract the SMI/PMI IPI +/// - The driver that abstracts the ASIC that is supporting the APM port,= such as the ICH in an +/// Intel chipset +/// +struct _PEI_SMM_CONTROL_PPI { + PEI_SMM_ACTIVATE Trigger; + PEI_SMM_DEACTIVATE Clear; +}; + +extern EFI_GUID gPeiSmmControlPpiGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Inc= lude/Protocol/SmmVariable.h b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode= /MdeModulePkg/Include/Protocol/SmmVariable.h new file mode 100644 index 0000000000..4aaa715d77 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SampleCode/MdeModulePkg/Include/Pr= otocol/SmmVariable.h @@ -0,0 +1,33 @@ +/** @file + EFI SMM Variable Protocol is related to EDK II-specific implementation o= f variables + and intended for use as a means to store data in the EFI SMM environment. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SMM_VARIABLE_H__ +#define __SMM_VARIABLE_H__ + +#define EFI_SMM_VARIABLE_PROTOCOL_GUID \ + { \ + 0xed32d533, 0x99e6, 0x4209, { 0x9c, 0xc0, 0x2d, 0x72, 0xcd, 0xd9, 0x98= , 0xa7 } \ + } + +typedef struct _EFI_SMM_VARIABLE_PROTOCOL EFI_SMM_VARIABLE_PROTOCOL; + +/// +/// EFI SMM Variable Protocol is intended for use as a means +/// to store data in the EFI SMM environment. +/// +struct _EFI_SMM_VARIABLE_PROTOCOL { + EFI_GET_VARIABLE SmmGetVariable; + EFI_GET_NEXT_VARIABLE_NAME SmmGetNextVariableName; + EFI_SET_VARIABLE SmmSetVariable; + EFI_QUERY_VARIABLE_INFO SmmQueryVariableInfo; +}; + +extern EFI_GUID gEfiSmmVariableProtocolGuid; + +#endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45890): https://edk2.groups.io/g/devel/message/45890 Mute This Topic: https://groups.io/mt/32918182/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45889+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45889+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001014; cv=none; d=zoho.com; s=zohoarc; b=HDEJaCDiaVZjGaBCVB2bIZRpTuTyC1/f3MDU3Zcod51fAulw00mqHKoUyPfq5e/l8IlNrCGCPZRr/sl5ulr3XACU4yGi2sJHLfpWrdij2XtJCJdhsobiZnKa6nK6Xwi/e5FN3ZZgtCb7XcffIXv4kyVKwbcE3hB9nEK43QU/R6k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001014; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=GmXgsm1JIghaLszYjNaKIm8HsLMGg3OqGtfSRiPk7TU=; b=MvbEh0u3hWN69j1WZ8Q27Zf/6wQe1eW9qOHSVK6g5SG+j2ykDtbSy0BLxiEfaU9hQZfujIFrVRYudDFJhhawcmb/wcPQUIKrYrhypsOlMPd+AbZyKQqtv0oqTkatjeZG1N4EXmTQcSIdmB58WJUhVfuNXRF2bURZmEQ79SolOjo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45889+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156600101486670.67530108132087; Fri, 16 Aug 2019 17:16:54 -0700 (PDT) Return-Path: X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:52 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319265" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:51 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 13/37] CoffeelakeSiliconPkg/SystemAgent: Add Include headers Date: Fri, 16 Aug 2019 17:15:39 -0700 Message-Id: <20190817001603.30632-14-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001014; bh=8yccDg3EK0On4HcVwFNVYIW4kqLnNH0xqOB3KEToOFI=; h=Cc:Date:From:Reply-To:Subject:To; b=kgUM2WwjA953L96MZMfr/yLBj/cO/YJDsshA+Cn0ph8Pi8mxvj2RJu6Jb/alGu9JJ+Q joPkRhVQNBVrYXpPUFC1u+VGA9RjoovYpUMo/tAcE0zbd/EH7ekj2kHgCrJbm7KcyENR/ 16Y/nYA7JvLRqrK7O4p6IUzG1k4EgS5lUm8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds header files common to System Agent (SA) modules. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/GnaConf= ig.h | 33 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic= sDxeConfig.h | 53 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic= sPeiConfig.h | 96 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Graphic= sPeiPreMemConfig.h | 70 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/IpuPreM= emConfig.h | 46 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryC= onfig.h | 534 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryD= xeConfig.h | 61 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/MiscDxe= Config.h | 33 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/OverClo= ckingConfig.h | 51 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxe= Config.h | 135 +++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PciePei= Config.h | 60 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/PciePei= PreMemConfig.h | 354 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscP= eiConfig.h | 61 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscP= eiPreMemConfig.h | 103 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Switcha= bleGraphicsConfig.h | 63 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VbiosDx= eConfig.h | 39 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/VtdConf= ig.h | 42 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRemappingTable.h= | 77 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/DxeSaPolicy= Lib.h | 60 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/PeiSaPolicy= Lib.h | 87 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/SaPlatformL= ib.h | 88 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h = | 259 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Gra= phicsInitLib.h | 15 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Leg= acyRegion.h | 33 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/Pei= CpuTraceHubLib.h | 23 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Library/SaP= cieLib.h | 70 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/Sa= IotrapSmi.h | 36 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protocol/Sa= NvsArea.h | 31 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaConfigHob= .h | 89 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaNvsAreaDe= f.h | 151 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopCompone= ntName2.h | 63 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopPolicy.= h | 73 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/IgdOpRegio= n.h | 24 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/MemInfo.h = | 132 +++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h= | 66 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsGna.= h | 32 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsHost= Bridge.h | 214 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIgd.= h | 50 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsIpu.= h | 37 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaRegsPeg.= h | 64 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h = | 106 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommonDefinitions= .h | 23 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciExpressLib.h = | 25 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicyCommon.h = | 51 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h = | 32 ++ 45 files changed, 3845 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/GnaConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/C= onfigBlock/GnaConfig.h new file mode 100644 index 0000000000..020a4aeab5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gn= aConfig.h @@ -0,0 +1,33 @@ +/** @file + Policy definition for GNA Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GNA_CONFIG_H_ +#define _GNA_CONFIG_H_ +#pragma pack(push, 1) + +#define GNA_CONFIG_REVISION 1 +/** + GNA config block for configuring GNA.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 C= onfig Block Header + /** + Offset 28:0 + This policy enables the GNA Device (SA Device 8) if supported. + If FALSE, all other policies in this config block will be ignored. + 1=3DTRUE; + 0=3DFALSE. + **/ + UINT32 GnaEnable : 1; + UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved f= or future use +} GNA_CONFIG; +#pragma pack(pop) + +#endif // _GNA_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/GraphicsDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/I= nclude/ConfigBlock/GraphicsDxeConfig.h new file mode 100644 index 0000000000..cc337a83f3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gr= aphicsDxeConfig.h @@ -0,0 +1,53 @@ +/** @file + Graphics DXE Policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_DXE_CONFIG_H_ +#define _GRAPHICS_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define GRAPHICS_DXE_CONFIG_REVISION 2 + +#define MAX_BCLM_ENTRIES 20 + +/** + This configuration block is to configure IGD related variables used in D= XE. + If Intel Gfx Device is not supported or disabled, all policies will be i= gnored. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. + Revision 2: + - Adding BCLM[MAX_BCLM_ENTRIES] +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header + UINT32 Size; ///< Offset 28 - 31: Thi= s field gives the size of the GOP VBT Data buffer + EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: Thi= s field points to the GOP VBT data buffer + UINT8 PlatformConfig; ///< Offset 40: This fie= ld gives the Platform Configuration Information (0=3DPlatform is S0ix Capab= le for ULT SKUs only, 1=3DPlatform is not S0ix Capable, 2=3DForce Pl= atform is S0ix Capable for All SKUs) + UINT8 AlsEnable; ///< Offset 41: Ambient = Light Sensor Enable: 0=3DDisable, 2=3DEnable + UINT8 BacklightControlSupport; ///< Offset 42: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal + UINT8 IgdBootType; ///< Offset 43: IGD Boot= Type CMOS option: 0=3DDefault, 0x01=3DCRT, 0x04=3DEFP, 0x08=3DLFP, = 0x20=3DEFP3, 0x40=3DEFP2, 0x80=3DLFP2 + UINT32 IuerStatusVal; ///< Offset 44 - 47: Off= set 16 This field holds the current status of all the supported Ultrabook e= vents (Intel(R) Ultrabook Event Status bits) + CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This= field holds the GOP Driver Version. It is an Output Protocol and updated b= y the Silicon code + /** + Offset 80: IGD Panel Type CMOS option\n + 0=3DDefault, 1=3D640X480LVDS, 2=3D800X600LVDS, 3=3D1024X768LVDS= , 4=3D1280X1024LVDS, 5=3D1400X1050LVDS1\n + 6=3D1400X1050LVDS2, 7=3D1600X1200LVDS, 8=3D1280X768LVDS, 9=3D1680X1050= LVDS, 10=3D1920X1200LVDS, 13=3D1600X900LVDS\n + 14=3D1280X800LVDS, 15=3D1280X600LVDS, 16=3D2048X1536LVDS, 17=3D1366X76= 8LVDS + **/ + UINT8 IgdPanelType; + UINT8 IgdPanelScaling; ///< Offset 81: IGD Pane= l Scaling: 0=3DAUTO, 1=3DOFF, 6=3DForce scaling + UINT8 IgdBlcConfig; ///< Offset 82: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal + UINT8 IgdDvmtMemSize; ///< Offset 83: IGD DVMT= Memory Size: 1=3D128MB, 2=3D256MB, 3=3DMAX + UINT8 GfxTurboIMON; ///< Offset 84: IMON Cur= rent Value: 14=3DMinimal, 31=3DMaximum + UINT8 Reserved[3]; ///< Offset 85: Reserved= for DWORD alignment. + UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Back= light Brightness Level Duty cycle Mapping Table. +} GRAPHICS_DXE_CONFIG; +#pragma pack(pop) + +#endif // _GRAPHICS_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/GraphicsPeiConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/I= nclude/ConfigBlock/GraphicsPeiConfig.h new file mode 100644 index 0000000000..276289ae81 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gr= aphicsPeiConfig.h @@ -0,0 +1,96 @@ +/** @file + Policy definition for Internal Graphics Config Block (PostMem) + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_PEI_CONFIG_H_ +#define _GRAPHICS_PEI_CONFIG_H_ +#pragma pack(push, 1) + +#define GRAPHICS_PEI_CONFIG_REVISION 4 +#define DDI_DEVICE_NUMBER 4 + +// +// DDI defines +// +typedef enum { + DdiDisable =3D 0x00, + DdiDdcEnable =3D 0x01, + DdiTbtLsxEnable =3D 0x02, +} DDI_DDC_TBT_VAL; + +typedef enum { + DdiHpdDisable =3D 0x00, + DdiHpdEnable =3D 0x01, +} DDI_HPD_VAL; + +typedef enum { + DdiPortADisabled =3D 0x00, + DdiPortAEdp =3D 0x01, + DdiPortAMipiDsi =3D 0x02, +} DDI_PORTA_SETTINGS; +/** + This structure configures the Native GPIOs for DDI port per VBT settings. +**/ +typedef struct { + UINT8 DdiPortEdp; /// The setting of eDP port, this settings must mat= ch VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortDHpd; /// The HPD setting of DDI Port D, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortFHpd; /// The HPD setting of DDI Port F, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortDDdc; /// The DDC setting of DDI Port D, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 DdiPortFDdc; /// The DDC setting of DDI Port F, this settings mu= st match VBT's settings. 0- Disable, 1- Enable + UINT8 Rsvd[3]; ///< Reserved for 4 bytes alignment +} DDI_CONFIGURATION; + +/** + This configuration block is to configure IGD related variables used in P= ostMem PEI. + If Intel Gfx Device is not supported, all policies can be ignored. + Revision 1: + - Initial version. + Revision 2: + - Added SkipS3CdClockInit. + Revision 3: + - Added DeltaT12PowerCycleDelay, BltBufferAddress, BltBufferSize. + Revision 4: + - Deprecated DeltaT12PowerCycleDelay. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header + UINT32 RenderStandby : 1; ///< Offset 28:0 :(Te= st) This field is used to enable or disable RC6 (Render Standby): 0=3DF= ALSE, 1=3DTRUE + UINT32 PmSupport : 1; ///< Offset 28:1 :(Te= st) IGD PM Support TRUE/FALSE: 0=3DFALSE, 1=3DTRUE + UINT32 PavpEnable : 1; ///< Offset 28:2 :IGD PA= VP TRUE/FALSE: 0=3DFALSE, 1=3DTRUE + /** + Offset 28:3 + CdClock Frequency select\n + CFL\n + 0 =3D 337.5 Mhz, 1 =3D 450 Mhz,\n + 2 =3D 540 Mhz, 3 =3D 675 Mhz,\n + + **/ + UINT32 CdClock : 3; + UINT32 PeiGraphicsPeimInit: 1; ///< Offset 28:6 : This = policy is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable + UINT32 CdynmaxClampEnable : 1; ///< Offset 28:7 : This = policy is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enabl= e, 0- Disable + UINT32 GtFreqMax : 8; ///< Offset 28:8 : (T= est) Max GT frequency limited by user in multiples of 50MHz: Default va= lue which indicates normal frequency is 0xFF + UINT32 DisableTurboGt : 1; ///< Offset 28:9 : This = policy is used to enable/disable DisableTurboGt 0- Disable, 1- Enable + UINT32 RsvdBits0 : 15; ///< Offser 28:15 :Reser= ved for future use + VOID* LogoPtr; ///< Offset 32 Address o= f Intel Gfx PEIM Logo to be displayed + UINT32 LogoSize; ///< Offset 36 Intel Gfx= PEIM Logo Size + VOID* GraphicsConfigPtr; ///< Offset 40 Address o= f the Graphics Configuration Table + DDI_CONFIGURATION DdiConfiguration; ///< Offset 44 DDI confi= guration, need to match with VBT settings. + UINT32 SkipS3CdClockInit : 1; ///< Offset 56 SKip full= CD clock initialization being done during S3 resume.0- Disable<\b>, 1- = Enable + UINT32 ReservedBits : 31; ///< Offset 56: 1 : Rese= rved for future use. + UINT16 DeltaT12PowerCycleDelay; ///< Offset 60 @deprecat= ed Power Cycle Delay required for eDP as per VESA standard.0 - 0 ms<\b>,= 0xFFFF - Auto calculate to max 500 ms + UINT8 Reserved[2]; ///< Offset 62 Reserved = for future use. + VOID* BltBufferAddress; ///< Offset 64 Address o= f Blt buffer for PEIM Logo use + UINT32 BltBufferSize; ///< Offset 68 The size = for Blt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size= of EFI_GRAPHICS_OUTPUT_BLT_PIXEL) +} GRAPHICS_PEI_CONFIG; +#pragma pack(pop) + +#endif // _GRAPHICS_PEI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/GraphicsPeiPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemA= gent/Include/ConfigBlock/GraphicsPeiPreMemConfig.h new file mode 100644 index 0000000000..4986fdab60 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Gr= aphicsPeiPreMemConfig.h @@ -0,0 +1,70 @@ +/** @file + Policy definition for Internal Graphics Config Block (PreMem) + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_PEI_PREMEM_CONFIG_H_ +#define _GRAPHICS_PEI_PREMEM_CONFIG_H_ +#pragma pack(push, 1) + +#define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 2 + + +/** + This Configuration block is to configure GT related PreMem data/variable= s.\n + Revision 1: + - Initial version. + Revision 2: + - Added DeltaT12PowerCycleDelayPreMem. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header + /** + Offset 28:0 + Selection of the primary display device: 0=3DiGFX, 1=3DPEG, 2=3DPCIe G= raphics on PCH, 3=3DAUTO, 4=3DSwitchable Graphics\n + When AUTO mode selected, the priority of display devices is: PCIe Grap= hics on PCH > PEG > iGFX + **/ + UINT32 PrimaryDisplay : 3; + /** + Offset 28:3 + Intel Gfx Support. It controls enabling/disabling iGfx device. + When AUTO mode selected, iGFX will be turned off when external graphic= s detected. + If FALSE, all other polices can be ignored. + 2 =3D AUTO; + 0 =3D FALSE; + 1 =3D TRUE. + **/ + UINT32 InternalGraphics : 2; + /** + Offset 28:5 + Pre-allocated memory for iGFX\n + 0 =3D 0MB,1 or 247 =3D 32MB,\n + 2 =3D 64MB,\n + 240 =3D 4MB, 241 =3D 8MB,\n + 242 =3D 12MB, 243 =3D 16MB,\n + 244 =3D 20MB, 245 =3D 24MB,\n + 246 =3D 28MB, 248 =3D 36MB,\n + 249 =3D 40MB, 250 =3D 44MB,\n + 251 =3D 48MB, 252 =3D 52MB,\n + 253 =3D 56MB, 254 =3D 60MB,\n + Note: enlarging pre-allocated memory for iGFX may need to reduce Mm= ioSize because of 4GB boundary limitation + **/ + UINT32 IgdDvmt50PreAlloc : 8; + UINT32 PanelPowerEnable : 1; ///< Offset 28:13 = :(Test) Control for enabling/disabling VDD force bit (Required only = for early enabling of eDP panel): 0=3DFALSE, 1=3DTRUE + UINT32 ApertureSize : 7; ///< Offser 28:14 = :Graphics aperture size (256MB is the recommended size as per BWG) : 0=3D12= 8MB, 1=3D256MB, 3=3D512MB, 7=3D1024MB, 15=3D2048MB. + UINT32 GtPsmiSupport : 1; ///< Offser 28:21 = :PSMI support On/Off: 0=3DFALSE, 1=3DTRUE + UINT32 PsmiRegionSize : 3; ///< Offser 28:22 = :Psmi region size: 0=3D32MB, 1=3D288MB, 2=3D544MB, 3=3D800MB, 4=3D10= 56MB + UINT32 RsvdBits0 : 7; ///< Offser 28:25 = :Reserved for future use + UINT32 GttMmAdr; ///< Offset 32 Tem= p Address of System Agent GTTMMADR : Default is 0xCF000000< / b> + UINT16 GttSize; ///< Offset 36 Sel= ection of iGFX GTT Memory size: 1=3D2MB, 2=3D4MB, 3=3D8MB + UINT8 Rsvd1[2]; ///< Offset 38 Res= erved for DWORD alignment + UINT32 GmAdr; ///< Offset 40 Tem= p Address of System Agent GMADR : Default is 0xD0000000< / b> + UINT16 DeltaT12PowerCycleDelayPreMem; ///< Offset 44 Pow= er Cycle Delay required for eDP as per VESA standard.0 - 0 ms<\b>, 0xFFF= F - Auto calculate to max 500 ms + UINT8 Reserved[2]; ///< Offset 46 Res= erved for future use. +} GRAPHICS_PEI_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _GRAPHICS_PEI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/IpuPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inc= lude/ConfigBlock/IpuPreMemConfig.h new file mode 100644 index 0000000000..79025d16fe --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Ip= uPreMemConfig.h @@ -0,0 +1,46 @@ +/** @file + IPU policy definitions (PreMem) + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IPU_CONFIG_PREMEM_H_ +#define _IPU_CONFIG_PREMEM_H_ + +#pragma pack(push, 1) + +#define IPU_PREMEM_CONFIG_REVISION 1 + +#define SA_IMR_IPU_CAMERA 0 +#define SA_IMR_IPU_GEN 1 + +/** + IPU PreMem configuration\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block He= ader + /** + Offset 28:0 : + (Test) It enables the SA IPU Device if supported and not fused of= f. + If FALSE, all other policies in this config block will be ignored. + 1=3DTRUE; + 0=3DFALSE. + **/ + UINT32 SaIpuEnable:1; + /** + Offset 28:1 : + (Test) It configure the IPU IMR to IPU Camera or IPU Gen when IPU= is enabled. + If FALSE, all other policies in this config block will be ignored. + 0=3DIPU Camera; + 1=3DIPU Gen + **/ + UINT32 SaIpuImrConfiguration:1; + UINT32 RsvdBits0:30; /// Offset 28:2 :Reserved fo= r future use. +} IPU_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _IPU_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/MemoryConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Includ= e/ConfigBlock/MemoryConfig.h new file mode 100644 index 0000000000..8374ff5f68 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Me= moryConfig.h @@ -0,0 +1,534 @@ +/** @file + Policy definition of Memory Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEMORY_CONFIG_H_ +#define _MEMORY_CONFIG_H_ + +#include + +#pragma pack(push, 1) + +#define SA_MRC_ITERATION_MAX (6) +#define SA_MRC_MAX_RCOMP (3) +#define SA_MRC_MAX_RCOMP_TARGETS (5) + +#define MEMORY_CONFIG_REVISION 3 + +/// +/// SMRAM Memory Range +/// +#define PEI_MR_SMRAM_ABSEG_MASK 0x01 +#define PEI_MR_SMRAM_HSEG_MASK 0x02 + +/// +/// SA SPD profile selections. +/// +typedef enum { + Default, ///< 0, Default SPD + UserDefined, ///< 1, User Defined profile + XMPProfile1, ///< 2, XMP Profile 1 + XMPProfile2, ///< 3, XMP Profile 2 + XMPProfileMax =3D 0xFF ///< Ensures SA_SPD is UINT8 +} SA_SPD; + +/// +/// Define the boot modes used by the SPD read function. +/// +typedef enum { + SpdCold, ///< Cold boot + SpdWarm, ///< Warm boot + SpdS3, ///< S3 resume + SpdFast, ///< Fast boot + SpdBootModeMax ///< Delimiter +} SPD_BOOT_MODE; + +typedef struct { + UINT8 SpdData[SA_MC_MAX_CHANNELS][SA_MC_MAX_SLOTS][SA_MC_MAX_SPD_SIZE]; +//Next Field Offset 2048 +} SPD_DATA_BUFFER; + +typedef struct { + UINT8 DqByteMap[SA_MC_MAX_CHANNELS][SA_MRC_ITERATION_MAX][2]; +//Next Field Offset 24 +} SA_MEMORY_DQ_MAPPING; + +typedef struct { + UINT8 DqsMapCpu2Dram[SA_MC_MAX_CHANNELS][SA_MC_MAX_BYTES_NO_ECC]; +//Next Field Offset 16 +} SA_MEMORY_DQS_MAPPING; + +typedef struct { + UINT16 RcompResistor[SA_MRC_MAX_RCOMP]; ///< Offset 0: Reference = RCOMP resistors on motherboard + UINT16 RcompTarget[SA_MRC_MAX_RCOMP_TARGETS]; ///< Offset 6: RCOMP targ= et values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv +//Next Field Offset 16 +} SA_MEMORY_RCOMP; + +typedef struct { + UINT16 Start; ///< Offset 0 + UINT16 End; ///< Offset 2 + UINT8 BootMode; ///< Offset 4 + UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use +} SPD_OFFSET_TABLE; + +/// +/// SA memory address decode. +/// +typedef struct +{ + UINT8 Controller; ///< Offset 0 Zero based Controller number + UINT8 Channel; ///< Offset 1 Zero based Channel number + UINT8 Dimm; ///< Offset 2 Zero based DIMM number + UINT8 Rank; ///< Offset 3 Zero based Rank number + UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number + UINT8 Bank; ///< Offset 5 Zero based Bank number + UINT16 Cas; ///< Offset 6 Zero based CAS number + UINT32 Ras; ///< Offset 8 Zero based RAS number +} SA_ADDRESS_DECODE; + +typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress); +typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress); +typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress); +typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress,= UINT8 Value); +typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress,= UINT16 Value); +typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress,= UINT32 Value); +typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); +typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); +typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); +typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); +typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, U= INT8 Value); +typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, U= INT16 Value); +typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, U= INT32 Value); +typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, U= INT64 Value); +typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, R= ETURN_STATUS *Status); +typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, R= ETURN_STATUS *Status); +typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, U= INT8 Value, RETURN_STATUS *Status); +typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, U= INT16 Value, RETURN_STATUS *Status); +typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); +typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); +typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, U= INT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); +typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID *GlobalData= ); +typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destinatio= n, CONST VOID *Source, UINTN NumBytes); +typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UI= NTN NumBytes, UINT8 Value); +typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UI= NTN NumWords, UINT16 Value); +typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UI= NTN NumDwords, UINT32 Value); +typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); +typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); +typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplic= and, UINT32 Multiplier); +typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend,= UINT64 Divisor, UINT64 *Remainder); +typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE Bo= otMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3Table= Size, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 Lpd= drTableSize); +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, = SA_ADDRESS_DECODE *DramAddress); +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECOD= E *DramAddress, UINT64 Address); +typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UIN= T32 Command, UINT32 *Value, UINT32 *Status); +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UIN= T32 Command, UINT32 Value, UINT32 *Status); +typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd); +typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd, UINT32 Value); +typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData= , UINT32 CheckPoint, VOID *Scratch); +typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData= , UINT16 DisplayDebugNumber); +typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, U= INT8 Channel); +typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UIN= T32 Level, char *Format, ...); +typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); +typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData= , UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel= , UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWai= t, UINT32 RegFileParam); +typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UIN= T8 OldMsb, UINT8 NewMsb); +typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData= , UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 Ne= wValue, UINT8 UpdateHost); +typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData= , UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 O= ffset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); +typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location); +typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location); +typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location,= UINT64 Data); +typedef UINT32 (EFIAPI * SA_THERMAL_OVERRIDES) (VOID *GlobalData= ); +typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData= , UINT32 MrcStatus); +typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseA= ddress, UINT32 ResetValue); +typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT32 PrmrrBase= Address, UINT32 PrmrrSize); + + +/// +/// Function calls into the SA. +/// +typedef struct { + SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU= I/O port 8-bit read. + SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU= I/O port 16-bit read. + SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU= I/O port 32-bit read. + SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU= I/O port 8-bit write. + SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU= I/O port 16-bit write. + SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU= I/O port 32-bit write. + SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Mem= ory Mapped I/O port 8-bit read. + SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Mem= ory Mapped I/O port 16-bit read. + SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Mem= ory Mapped I/O port 32-bit read. + SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Mem= ory Mapped I/O port 64-bit read. + SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Mem= ory Mapped I/O port 8-bit write. + SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Mem= ory Mapped I/O port 16-bit write. + SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Mem= ory Mapped I/O port 32-bit write. + SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Mem= ory Mapped I/O port 64-bit write. + SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smb= us 8-bit read. + SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smb= us 16-bit read. + SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smb= us 8-bit write. + SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smb= us 16-bit write. + SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get= PCI device address. + SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get= PCI express device address. + SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get= the current time value. + SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The= current CPU time in milliseconds. + SA_MEMORY_COPY CopyMem; ///< Offset 88: - Per= form byte copy operation. + SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Per= form byte initialization operation. + SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Per= form word initialization operation. + SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Per= form dword initialization operation. + SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Lef= t shift the 64-bit data value by specified number of bits. + SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Rig= ht shift the 64-bit data value by specified number of bits. + SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Mul= tiply a 64-bit data value by a 32-bit data value. + SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Div= ide a 64-bit data value by a 64-bit data value. + SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Rea= d the SPD data over the SMBus, at the given SmBus SPD address and copy the = data to the data structure. + SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get= the next random 32-bit number. + SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Per= form a CPU mailbox read. + SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Per= form a CPU mailbox write. + SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get= the current memory voltage (VDD). + SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set= the memory voltage (VDD) to the given value. + SA_CHECKPOINT CheckPoint; ///< Offset 144: - Che= ck point that is called at various points in the MRC. + SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typ= ically used to display to the I/O port 80h. + SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Out= put a string to the debug stream/device. + SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get= the current value of the specified RTC CMOS location. + SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get= the current value of the specified MSR location. + SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set= the current value of the specified MSR location. + SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hoo= k function after returning from MrcStartMemoryConfiguration() + SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Ass= ert or deassert DRAM_RESET# pin; this is used in JEDEC Reset. +} SA_FUNCTION_CALLS; + +/// +/// Function calls into the MRC. +/// +typedef struct { + SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Retu= rns whether Channel is or is not present. + SA_PRINTF MrcPrintf; ///< Offset 4: - Prin= t to output stream/device. + SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Chan= ge the margin. + SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign= extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7). + SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move= CMD/CTL/CLK/CKE PIs during training. + SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Upda= te the Vref value and wait until it is stable. +} SA_MEMORY_FUNCTIONS; + +/** + Memory Configuration + The contents of this structure are CRC'd by the MRC for option change det= ection. + This structure is copied en mass to the MrcInput structure. If you add fi= elds here, you must update the MrcInput structure. + Revision 1: + - Initial version. + Revision 2: + - Removed GearType. + - Added Lp4DqsOscEn, RMTLoopCount, EnBER, DualDimmPerChannelBoardType. + Revision 3: + - Removed EvLoader, EvLoaderDelay. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + UINT16 Size; ///< Offset 28 The size of this structur= e, in bytes. Must be the first entry in this structure. + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MRC + + UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection= - for XMP supported DIMM: 0=3DDefault DIMM profile, 1=3DCustomized = profile, 2=3DXMP profile 1, 3=3DXMP profile 2. + + // The following parameters are used only when SpdProfileSelected is Use= rDefined (CUSTOM PROFILE) + UINT16 tCL; ///< Offset 32 User defined Memory Timin= g tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 31=3DMaximum. + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timin= g tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE= : 0=3DAUTO, 63=3DMaximum + UINT16 tRAS; ///< Offset 36 User defined Memory Timin= g tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 64=3DMaximum. + UINT16 tWR; ///< Offset 38 User defined Memory Timin= g tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24. + UINT16 tRFC; ///< Offset 40 User defined Memory Timin= g tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 1023=3DMaximum. + UINT16 tRRD; ///< Offset 42 User defined Memory Timin= g tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. + UINT16 tWTR; ///< Offset 44 User defined Memory Timin= g tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 28=3DMaximum. + UINT16 tRTP; ///< Offset 46 User defined Memory Timin= g tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12 + UINT16 tFAW; ///< Offset 48 User defined Memory Timin= g tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 63=3DMaximum. + UINT16 tCWL; ///< Offset 50 User defined Memory Timin= g tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 20=3DMaximum. + UINT16 tREFI; ///< Offset 52 User defined Memory Timin= g tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 65535=3DMaximum. + UINT16 PciIndex; ///< Offset 54 Pci index register addres= s: 0xCF8=3DDefault + UINT16 PciData; ///< Offset 56 Pci data register address= : 0xCFC=3DDefault + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in mil= livolts: 0=3DPlatform Default (no override), 1200=3D1.2V, 1350=3D1.3= 5V etc. + UINT16 Idd3n; ///< Offset 60 EPG Active standby curren= t (Idd3N) in milliamps from DIMM datasheet. + UINT16 Idd3p; ///< Offset 62 EPG Active power-down cur= rent (Idd3P) in milliamps from DIMM datasheet. + + UINT32 EccSupport:1; ///< Offset 64 DIMM Ecc Support = option - for Desktop only: 0=3DDisable, 1=3DEnable + UINT32 MrcSafeConfig:1; ///< - MRC Safe Mode: 0=3DDi= sable, 1=3DEnable + UINT32 RemapEnable:1; ///< - This option is used to c= ontrol whether to enable/disable memory remap above 4GB: 0=3DDisable, 1= =3DEnable. + UINT32 ScramblerSupport:1; ///< - Memory scrambler support= : 0=3DDisable, 1=3DEnable + UINT32 Vc1ReadMeter:1; ///< - VC1 Read Metering Enable= : 0=3DDisable, 1=3DEnable + UINT32 DdrThermalSensor:1; ///< - Ddr Thermal Sensor: 0=3D= Disable, 1=3DEnable + UINT32 LpddrMemWriteLatencySet:1; ///< - LPDDR3 Write Latency Set= option: 0=3DSet A, 1=3DSet B + UINT32 Off64Bits7to8Rsvd:2; ///< - Bit 7-8 Reserved + UINT32 SimicsFlag:1; ///< - Option to Enable SIMICS:= 0=3DDisable, 1=3DEnable + UINT32 Ddr4DdpSharedClock:1; ///< - Select if CLK0 is shared= between Rank0 and Rank1 in DDR4 DDP package. 0=3DNot shared, 1=3DSh= ared + UINT32 SharedZqPin:1; ///< - Select if ZQ pin is shar= ed between Rank ranks. For CFL, this option only works for DDR4. the opti= on works for LPDDR4 and DDR4. 0=3DNot shared, 1=3DShared + // Thermal Management + UINT32 ThermalManagement:1; ///< - Memory Thermal Man= agement Support: 0=3DDisable, 1=3DEnable. + UINT32 PeciInjectedTemp:1; ///< - Enable/Disable mem= ory temperatures to be injected to the processor via PECI: 0=3DDisable, 1=3DEnable. + UINT32 ExttsViaTsOnBoard:1; ///< - Enable/Disable rou= ting TS-on-Board's ALERT# and THERM# to EXTTS# pins on the PCH: 0=3DDisa= ble, 1=3DEnable. + UINT32 ExttsViaTsOnDimm:1; ///< - Enable/Disable rou= ting TS-on-DIMM's ALERT# to EXTTS# pin on the PCH: 0=3DDisable, 1=3D= Enable. + UINT32 VirtualTempSensor:1; ///< - Enable/Disable Vir= tual Temperature Sensor (VTS): 0=3DDisable, 1=3DEnable. + UINT32 Lp4DqsOscEn :1; ///< - LpDdrDqDqsReTraini= ng - DqDqsReTraining Enable: 0=3DDisable, 1=3DEnable + UINT32 DualDimmPerChannelBoardType:1; ///< - DualDimmPerChannel= BoardType - Option to indicate if the Memory Design for the board includes = two DIMMs per channel: 0=3DSingle DIMM Design, 1=3DDual DIMM Design + UINT32 ReservedBits1:13; + /** + Disables a DIMM slot in the channel even if a DIMM is present\n + Array index represents the channel number (0 =3D channel 0, 1 =3D chann= el 1)\n + 0x0 =3D DIMM 0 and DIMM 1 enabled\n + 0x1 =3D DIMM 0 disabled, DIMM 1 enabled\n + 0x2 =3D DIMM 0 enabled, DIMM 1 disabled\n + 0x3 =3D DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n + **/ + UINT8 DisableDimmChannel[SA_MC_MAX_CHANNELS]; ///< Offset 68 + /** + Selects the ratio to multiply the reference clock by for the DDR freque= ncy\n + When RefClk is 133MHz\n + 0x00 =3D Auto, 0x03 through 0x0C are valid values, all others ar= e invalid\n + When RefClk is 100MHz\n + 0x00 =3D Auto, 0x06 through 0x10 are valid values, all others ar= e invalid\n + **/ + UINT8 Ratio; ///< Offset 70 + UINT8 ProbelessTrace; ///< Offset 71 Probeless Trace: 0=3DD= isabled, 1=3DEnabled + UINT32 BClkFrequency; ///< Offset 72 Base reference clock valu= e, in Hertz: 100000000 =3D 100Hz, 125000000=3D125Hz, 167000000=3D167= Hz, 250000000=3D250Hz + /** + - Channel Hash Enable.\n + NOTE: BIT7 will interleave the channels at a 2 cache-line granularity,= BIT8 at 4 and BIT9 at 8\n + 0=3DBIT6, 1=3DBIT7, 2=3DBIT8, 3=3DBIT9 + **/ + UINT8 ChHashInterleaveBit; ///< Offset 76 Option to select interlea= ve Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW= are 0-7 for BITS 6 - 13) + UINT8 EnergyScaleFact; ///< Offset 77 Energy Scale Factor. 0=3D= Minimal, 7=3DMaximum, 4=3DDefault + BOOLEAN PerBankRefresh; ///< Offset 78 Enables and Disable= s the per bank refresh. This only impacts memory technologies that support= PBR: LPDDR3, LPDDR4. FALSE=3DDisabled, TRUE=3DEnabled + UINT8 McLock; ///< Offset 79 Enable/Disable memo= ry configuration register locking: 0=3DDisable, 1=3DEnable. + // Training Algorithms 1 + UINT32 ECT:1; ///< Offset 80 Enable/Disable Early Comm= and Training. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable. + UINT32 SOT:1; ///< - Enable/Disable Sense Amp Offset = Training. Note it is not recommended to change this setting from the defaul= t value: 0=3DDisable, 1=3DEnable. + UINT32 ERDMPRTC2D:1; ///< - Enable/Disable Early ReadMPR Tim= ing Centering 2D. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable. + UINT32 RDMPRT:1; ///< - Enable/Disable Read MPR Training= . Note it is not recommended to change this setting from the default value:= 0=3DDisable, 1=3DEnable. + UINT32 RCVET:1; ///< - Enable/Disable Receive Enable Tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 JWRL:1; ///< - Enable/Disable JEDEC Write Level= ing Training. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable. + UINT32 EWRTC2D:1; ///< - Enable/Disable Early Write Time = Centering 2D Training. Note it is not recommended to change this setting fr= om the default value: 0=3DDisable, 1=3DEnable. + UINT32 ERDTC2D:1; ///< - Enable/Disable Early Read Time C= entering 2D Training. Note it is not recommended to change this setting fro= m the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRTC1D:1; ///< - Enable/Disable 1D Write Timing C= entering Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable. + UINT32 WRVC1D:1; ///< - Enable/Disable 1D Write Voltage = Centering Training. Note it is not recommended to change this setting from = the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDTC1D:1; ///< - Enable/Disable 1D Read Timing Ce= ntering Training. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable. + UINT32 DIMMODTT:1; ///< - Enable/Disable DIMM ODT Training= . Note it is not recommended to change this setting from the default value:= 0=3DDisable, 1=3DEnable. + UINT32 DIMMRONT:1; ///< - Enable/Disable DIMM RON training= . Note it is not recommended to change this setting from the default value:= 0=3DDisable, 1=3DEnable. + UINT32 WRDSEQT:1; ///< - Enable/Disable Write Drive Stren= gth / Equalization Training 2D. Note it is not recommended to change this s= etting from the default value: 0=3DDisable, 1=3DEnable. + UINT32 WRSRT:1; ///< - Enable/Disable Write Slew Rate t= raning. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable. + UINT32 RDODTT:1; ///< - Enable/Disable Read ODT Training= . Note it is not recommended to change this setting from the default value:= 0=3DDisable, 1=3DEnable. + UINT32 RDEQT:1; ///< - Enable/Disable Read Equalization= Training. Note it is not recommended to change this setting from the defau= lt value: 0=3DDisable, 1=3DEnable. + UINT32 RDAPT:1; ///< - Enable/Disable Read Amplifier Po= wer Training. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable. + UINT32 WRTC2D:1; ///< - Enable/Disable 2D Write Timing C= entering Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable. + UINT32 RDTC2D:1; ///< - Enable/Disable 2D Read Timing Ce= ntering Training. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable. + UINT32 WRVC2D:1; ///< - Enable/Disable 2D Write Voltage = Centering Training. Note it is not recommended to change this setting from = the default value: 0=3DDisable, 1=3DEnable. + UINT32 RDVC2D:1; ///< - Enable/Disable 2D Read Voltage C= entering Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable. + UINT32 CMDVC:1; ///< - Enable/Disable Command Vref Cent= ering Training. Note it is not recommended to change this setting from the = default value 0=3DDisable, 1=3DEnable. + UINT32 LCT:1; ///< - Enable/Disable Late Command Trai= ning. Note it is not recommended to change this setting from the default va= lue: 0=3DDisable, 1=3DEnable. + UINT32 RTL:1; ///< - Enable/Disable Round Trip Latenc= y function. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable. + UINT32 TAT:1; ///< - Enable/Disable Turn Around Time = function. Note it is not recommended to change this setting from the defaul= t value: 0=3DDisable, 1=3DEnable. + UINT32 RMT:1; ///< - Enable/Disable Rank Margin Tool = function: 0=3DDisable, 1=3DEnable. + UINT32 MEMTST:1; ///< - Enable/Disable Memory Test funct= ion: 0=3DDisable, 1=3DEnable. + UINT32 ALIASCHK:1; ///< - Enable/Disable DIMM SPD Alias Ch= eck: 0=3DDisable, 1=3DEnable + UINT32 RCVENC1D:1; ///< - Enable/Disable Receive Enable Ce= ntering Training (LPDDR Only). Note it is not recommended to change this se= tting from the default value: 0=3DDisable, 1=3DEnable + UINT32 RMC:1; ///< - Enable/Disable Retrain Margin Ch= eck. Note it is not recommended to change this setting from the default va= lue: 0=3DDisable, 1=3DEnable + UINT32 WRDSUDT:1; ///< - Enable/Disable Write Drive Stren= gth Up/Dn independently. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable + // Training Algorithms 2 + UINT32 CMDSR : 1; ///< Offset 84 - Enable/Disable CM= D Slew Rate Training: 0=3DDisable, 1=3DEnable. + UINT32 CMDDSEQ : 1; ///< - Enable/Disable CMD Drive S= trength and Tx Equalization: 0=3DDisable, 1=3DEnable. + UINT32 CMDNORM : 1; ///< - Enable/Disable CMD Normali= zation: 0=3DDisable, 1=3DEnable. + UINT32 EWRDSEQ : 1; ///< - Enable/Disable Early DQ Wr= ite Drive Strength and Equalization Training: 0=3DDisable, 1=3DEnable. + UINT32 RDVC1D : 1; ///< - Enable/Disable Read Voltag= e Centering 1D + UINT32 TXTCO : 1; ///< - Enable/Disable Write TCO C= omp Training + UINT32 CLKTCO : 1; ///< - Enable/Disable Clock TCO C= omp Training + UINT32 ReservedBits2 :25; + + UINT32 OddRatioMode:1; ///< Offset 88 If Odd Ratio Mode is = enabled, QCLK frequency has an addition of 133/100 MHz: 0=3DDisable,= 1=3DEnable + UINT32 MrcTimeMeasure:1; ///< - Enables serial debug level t= o display the MRC execution times only: 0=3DDisable, 1=3DEnable + UINT32 MrcFastBoot:1; ///< - Enables the MRC fast boot pa= th for faster cold boot execution: 0=3DDisable, 1=3DEnable + UINT32 DqPinsInterleaved:1; ///< - Interleaving mode of DQ/DQS = pins for HSW_ULT which depends on board routing: 0=3DDisable, 1=3DEn= able + UINT32 RankInterleave:1; ///< - Rank Interleave Mode: 0=3DDi= sable, 1=3DEnable + UINT32 EnhancedInterleave:1; ///< - Enhanced Interleave Mode: 0= =3DDisable, 1=3DEnable + UINT32 WeaklockEn:1; ///< - Weak Lock Enable: 0=3DDisabl= e, 1=3DEnable + UINT32 CmdTriStateDis:1; ///< - CMD Tri-State Support: 0= =3DEnable, 1=3DDisable. Note: This should be set to 1 (Disable) if Comm= and RTT is not present on the platform. + UINT32 MemoryTrace:1; ///< - Memory Trace to second DDR c= hannel using Stacked Mode: 0=3DDisable, 1=3DEnable + UINT32 ChHashEnable:1; ///< - Channel Hash Enable: 0=3DDis= able, 1=3DEnable + UINT32 EnableExtts:1; ///< - Enable Extts: 0=3DDisable= , 1=3DEnable + UINT32 EnableCltm:1; ///< - Enable Closed Loop Thermal M= anagement: 0=3DDisable, 1=3DEnable + UINT32 EnableOltm:1; ///< - Enable Open Loop Thermal Man= agement: 0=3DDisable, 1=3DEnable + UINT32 EnablePwrDn:1; ///< - Enable Power Down control fo= r DDR: 0=3DPCODE control, 1=3DBIOS control + UINT32 EnablePwrDnLpddr:1; ///< - Enable Power Down for LPDDR:= 0=3DPCODE control, 1=3DBIOS control + UINT32 LockPTMregs:1; ///< - Lock PCU Thermal Management = registers: 0=3DDisable, 1=3DEnable + UINT32 UserPowerWeightsEn:1; ///< - Allows user to explicitly se= t power weight, scale factor, and channel power floor values: 0=3DDisabl= e, 1=3DEnable + UINT32 RaplLim2Lock:1; ///< - Lock DDR_RAPL_LIMIT register= : 0=3DDisable, 1=3DEnable + UINT32 RaplLim2Ena:1; ///< - Enable Power Limit 2: 0= =3DDisable, 1=3DEnable + UINT32 RaplLim1Ena:1; ///< - Enable Power Limit 1: 0= =3DDisable, 1=3DEnable + UINT32 SrefCfgEna:1; ///< - Enable Self Refresh: 0=3DDis= able, 1=3DEnable + UINT32 ThrtCkeMinDefeatLpddr:1; ///< - Throttler CKE min defeature = for LPDDR: 0=3DDisable, 1=3DEnable + UINT32 ThrtCkeMinDefeat:1; ///< - Throttler CKE min defeature:= 0=3DDisable, 1=3DEnable + UINT32 AutoSelfRefreshSupport:1; ///< - FALSE =3D No auto self refre= sh support, TRUE =3D auto self refresh support + UINT32 ExtTemperatureSupport:1; ///< - FALSE =3D No extended temper= ature support, TRUE =3D extended temperature support + UINT32 MobilePlatform:1; ///< - Memory controller device id = indicates: TRUE if mobile, FALSE if not. Note: This will be auto-det= ected and updated. + UINT32 Force1Dpc:1; ///< - TRUE means force one DIMM pe= r channel, FALSE means no limit + UINT32 ForceSingleRank:1; ///< - TRUE means use Rank0 only (i= n each DIMM): 0=3DDisable, 1=3DEnable + UINT32 RhPrevention:1; ///< - RH Prevention Enable/Disable= : 0=3DDisable, 1=3DEnable + UINT32 VttTermination:1; ///< - Vtt Termination for Data ODT= : 0=3DDisable, 1=3DEnable + UINT32 VttCompForVsshi:1; ///< - Enable/Disable Vtt Comparato= r For Vsshi: 0=3DDisable, 1=3DEnable + UINT32 ExitOnFailure:1; ///< - MRC option for exit on failu= re or continue on failure: 0=3DDisable, 1=3DEnable + + UINT32 VddSettleWaitTime; ///< Offset 92 Amount of time in microse= conds to wait for Vdd to settle on top of 200us required by JEDEC spec: = Default=3D0 + UINT16 FreqSaGvLow; ///< Offset 96 SA GV: 0 is Auto/default,= otherwise holds the frequency value: 0=3DDefault, 1067, 1200, 1333,= 1400, 1600, 1800, 1867. + UINT16 SrefCfgIdleTmr; ///< Offset 98 Self Refresh idle timer: = 512=3DMinimal, 65535=3DMaximum + UINT8 RhActProbability; ///< Offset 100 Activation probability f= or Hardware RHP + UINT8 SmramMask; ///< Offset 101 Reserved memory ranges f= or SMRAM + UINT16 Vc1ReadMeterThreshold; ///< Offset 102 VC1 Read Meter Thr= eshold (within Time Window): 0=3DMinimal, 0xFFFF=3DMaximum, 0x118=3DDefa= ult + UINT32 Vc1ReadMeterTimeWindow; ///< Offset 104 VC1 Read Meter Tim= e Window: 0=3DMinimal, 0x1FFFF=3DMaximum, 0x320=3DDefault + UINT64 BerAddress[4]; ///< Offset 108 - 139 BER Address(es): <= b>0=3DMinimal, 0xFFFFFFFFFFFFFFFF=3DMaximum (step is 0x40) + + UINT16 ChHashMask; ///< Offset 140 Channel Hash Mask: 0x000= 1=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT[19= :18, 13:12 ,9:7] set + UINT16 DdrFreqLimit; ///< Offset 142 Memory Frequency setting= : 3=3D1067, 5=3D1333, 7=3D1600, 9=3D1867, 11=3D2133, 13=3D2400, 15=3D266= 7 + UINT8 RaplLim2WindX; ///< Offset 144 Power Limit 2 Time Windo= w X value: 0=3DMinimal, 3=3DMaximum, 1=3DDefault + UINT8 RaplLim2WindY; ///< Offset 145 Power Limit 2 Time Windo= w Y value: 0=3DMinimal, 3=3DMaximum, 1=3DDefault + UINT8 RaplLim1WindX; ///< Offset 146 Power Limit 1 Time Windo= w X value: 0=3DMinimal, 3=3DMaximum + UINT8 RaplLim1WindY; ///< Offset 147 Power Limit 1 Time Windo= w Y value: 0=3DMinimal, 31=3DMaximum + UINT16 RaplLim2Pwr; ///< Offset 148 Power Limit 2: 0=3DMini= mal, 16383=3DMaximum, 222=3DDefault + UINT16 RaplLim1Pwr; ///< Offset 150 Power Limit 1: 0=3DM= inimal, 16383=3DMaximum + UINT8 WarmThresholdCh0Dimm0; ///< Offset 152 Warm Threshold (Channel = 0, Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmThresholdCh0Dimm1; ///< Offset 153 Warm Threshold (Channel = 0, Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 WarmThresholdCh1Dimm0; ///< Offset 154 Warm Threshold (Channel = 1, Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmThresholdCh1Dimm1; ///< Offset 155 Warm Threshold (Channel = 1, Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 HotThresholdCh0Dimm0; ///< Offset 156 Hot Threshold (Channel 0= , Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotThresholdCh0Dimm1; ///< Offset 157 Hot Threshold (Channel 0= , Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 HotThresholdCh1Dimm0; ///< Offset 158 Hot Threshold (Channel 1= , Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotThresholdCh1Dimm1; ///< Offset 159 Hot Threshold (Channel 1= , Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudgetCh0Dimm0; ///< Offset 160 Warm Budget (Channel 0, = Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudgetCh0Dimm1; ///< Offset 161 Warm Budget (Channel 0, = Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudgetCh1Dimm0; ///< Offset 162 Warm Budget (Channel 1, = Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudgetCh1Dimm1; ///< Offset 163 Warm Budget (Channel 1, = Dimm 1): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudgetCh0Dimm0; ///< Offset 164 Hot Budget (Channel 0, D= imm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudgetCh0Dimm1; ///< Offset 165 Hot Budget (Channel 0, D= imm 1): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudgetCh1Dimm0; ///< Offset 166 Hot Budget (Channel 1, D= imm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudgetCh1Dimm1; ///< Offset 167 Hot Budget (Channel 1, D= imm 1): 0=3DMinimal, 255=3DMaximum + UINT8 IdleEnergyCh0Dimm0; ///< Offset 168 Idle Energy (Channel 0, = Dimm 0): 0=3DMinimal, 63=3DMaximum, 10=3DDefault + UINT8 IdleEnergyCh0Dimm1; ///< Offset 169 Idle Energy (Channel 0, = Dimm 1): 0=3DMinimal, 63=3DMaximum, 10=3DDefault + UINT8 IdleEnergyCh1Dimm0; ///< Offset 170 Idle Energy (Channel 1, = Dimm 0): 0=3DMinimal, 63=3DMaximum, 10=3DDefault + UINT8 IdleEnergyCh1Dimm1; ///< Offset 171 Idle Energy (Channel 1, = Dimm 1): 0=3DMinimal, 63=3DMaximum, 10=3DDefault + UINT8 PdEnergyCh0Dimm0; ///< Offset 172 Power Down Energy (Chann= el 0, Dimm 0): 0=3DMinimal, 63=3DMaximum, 6=3DDefault + UINT8 PdEnergyCh0Dimm1; ///< Offset 173 Power Down Energy (Chann= el 0, Dimm 1): 0=3DMinimal, 63=3DMaximum, 6=3DDefault + UINT8 PdEnergyCh1Dimm0; ///< Offset 174 Power Down Energy (Chann= el 1, Dimm 0): 0=3DMinimal, 63=3DMaximum, 6=3DDefault + UINT8 PdEnergyCh1Dimm1; ///< Offset 175 Power Down Energy (Chann= el 1, Dimm 1): 0=3DMinimal, 63=3DMaximum, 6=3DDefault + UINT8 ActEnergyCh0Dimm0; ///< Offset 176 Activation Energy (Chann= el 0, Dimm 0): 0=3DMinimal, 255=3DMaximum, 172=3DDefault + UINT8 ActEnergyCh0Dimm1; ///< Offset 177 Activation Energy (Chann= el 0, Dimm 1): 0=3DMinimal, 255=3DMaximum, 172=3DDefault + UINT8 ActEnergyCh1Dimm0; ///< Offset 178 Activation Energy (Chann= el 1, Dimm 0): 0=3DMinimal, 255=3DMaximum, 172=3DDefault + UINT8 ActEnergyCh1Dimm1; ///< Offset 179 Activation Energy (Chann= el 1, Dimm 1): 0=3DMinimal, 255=3DMaximum, 172=3DDefault + UINT8 RdEnergyCh0Dimm0; ///< Offset 180 Read Energy (Channel 0, = Dimm 0): 0=3DMinimal, 255=3DMaximum, 212=3DDefault + UINT8 RdEnergyCh0Dimm1; ///< Offset 181 Read Energy (Channel 0, = Dimm 1): 0=3DMinimal, 255=3DMaximum, 212=3DDefault + UINT8 RdEnergyCh1Dimm0; ///< Offset 182 Read Energy (Channel 1, = Dimm 0): 0=3DMinimal, 255=3DMaximum, 212=3DDefault + UINT8 RdEnergyCh1Dimm1; ///< Offset 183 Read Energy (Channel 1, = Dimm 1): 0=3DMinimal, 255=3DMaximum, 212=3DDefault + UINT8 WrEnergyCh0Dimm0; ///< Offset 184 Write Energy (Channel 0,= Dimm 0): 0=3DMinimal, 255=3DMaximum, 221=3DDefault + UINT8 WrEnergyCh0Dimm1; ///< Offset 185 Write Energy (Channel 0,= Dimm 1): 0=3DMinimal, 255=3DMaximum, 221=3DDefault + UINT8 WrEnergyCh1Dimm0; ///< Offset 186 Write Energy (Channel 1,= Dimm 0): 0=3DMinimal, 255=3DMaximum, 221=3DDefault + UINT8 WrEnergyCh1Dimm1; ///< Offset 187 Write Energy (Channel 1,= Dimm 1): 0=3DMinimal, 255=3DMaximum, 221=3DDefault + + + UINT8 MaxRttWr; ///< Offset 188 Maximum DIMM RTT_WR to u= se in power training: 0=3DODT Off, 1 =3D 120 ohms + UINT8 ThrtCkeMinTmr; ///< Offset 189 Throttler CKE min timer:= 0=3DMinimal, 0xFF=3DMaximum, 0x30=3DDefault + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 190 Throttler CKE min timer = for LPDDR: 0=3DMinimal, 0xFF=3DMaximum, 0x40=3DDefault + UINT8 BerEnable; ///< Offset 191 BER Enable and # of Addr= esses passed in: 0=3DMinimal, 8=3DMaximum + UINT8 CkeRankMapping; ///< Offset 192 Bits [7:4] - Channel 1, = bits [3:0] - Channel 0. 0xAA=3DDefault Bit [i] specifies which rank = CKE[i] goes to. + UINT8 StrongWkLeaker; ///< Offset 193 Strong Weak Leaker: 1=3D= Minimal, 7=3DMaximum + UINT8 CaVrefConfig; ///< Offset 194 0=3DVREF_CA goes to both= CH_A and CH_B, 1=3DVREF_CA to CH_A, VREF_DQ_A to CH_B, 2=3DVREF_CA to C= H_A, VREF_DQ_B to CH_B + UINT8 SaGv; ///< Offset 195 SA GV: 0=3DDisabled; 1= =3DFixedLow; CFL: 2=3DFixedHigh, CNL: 2=3DFixedMid; CFL: 3=3DEnabled= CNL: 3=3DFixedHigh; CNL: 4=3DEnabled + UINT8 RaplPwrFlCh1; ///< Offset 196 Power Channel 1 Floor va= lue: 0=3DMinimal, 255=3DMaximum + UINT8 RaplPwrFlCh0; ///< Offset 197 Power Channel 0 Floor va= lue: 0=3DMinimal, 255=3DMaximum + UINT8 NModeSupport; ///< Offset 198 Memory N Mode Support - = Enable user to select Auto, 1N or 2N: 0=3DAUTO, 1=3D1N, 2=3D2N. + UINT8 RefClk; ///< Offset 199 Selects the DDR base ref= erence clock. 0x01 =3D 100MHz, 0x00 =3D 133MHz + UINT8 EnCmdRate; ///< Offset 200 CMD Rate Enable: 0=3DDis= able, 1=3D1 CMD, 2=3D2 CMDs, 3=3D3 CMDs, 4=3D4 CMDs, 5=3D5 CMDs, 6= =3D6 CMDs, 7=3D7 CMDs + UINT8 Refresh2X; ///< Offset 201 Refresh 2x: 0=3DDisab= le, 1=3DEnable for WARM or HOT, 2=3DEnable for HOT only + UINT8 EpgEnable; ///< Offset 202 Enable Energy Performanc= e Gain. + UINT8 RhSolution; ///< Offset 203 Type of solution to be u= sed for RHP - 0/1 =3D HardwareRhp/Refresh2x + UINT8 UserThresholdEnable; ///< Offset 204 Flag to manually select = the DIMM CLTM Thermal Threshold, 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 UserBudgetEnable; ///< Offset 205 Flag to manually select = the Budget Registers for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0= =3DDefault + UINT8 TsodTcritMax; ///< Offset 206 TSOD Tcrit Maximum Value= to be Configure , 0=3DMinimal, 128=3DMaximum, , 105=3DDefault + + UINT8 TsodEventMode; ///< Offset 207 Flag to Enable Event Mod= e Interruption in TSOD Configuration Register, 0=3DDisable, 1=3DEnable, 1=3DDefault + UINT8 TsodEventPolarity; ///< Offset 208 Event Signal Polarity in= TSOD Configuration Register, 0=3DLow, 1=3DHigh, 0=3DDefault + UINT8 TsodCriticalEventOnly; ///< Offset 209 Critical Trigger Only in= TSOD Configuration Register,0=3DDisable, 1=3DEnable, 1=3DDefault + UINT8 TsodEventOutputControl; ///< Offset 210 Event Output Control in = TSOD Configuration Register,0=3DDisable, 1=3DEnable, 1=3DDefault + UINT8 TsodAlarmwindowLockBit; ///< Offset 211 Alarm Windows Lock Bit i= n TSOD Configuration Register,0=3DUnlock, 1=3DLock, 0=3DDefault + UINT8 TsodCriticaltripLockBit;///< Offset 212 Critical Trip Lock Bit i= n TSOD Configuration Register,0=3DUnlock, 1=3DLock, 0=3DDefault + UINT8 TsodShutdownMode; ///< Offset 213 Shutdown Mode TSOD Confi= guration Register,0=3DEnable, 1=3DDisable, 0=3DDefault + UINT8 TsodThigMax; ///< Offset 214 Thigh Max Value In the = for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 TsodManualEnable; ///< Offset 215 Flag to manually select = the TSOD Register Values , 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 DllBwEn0; ///< Offset 216 DllBwEn value for 1067 + UINT8 DllBwEn1; ///< Offset 217 DllBwEn value for 1333 + UINT8 DllBwEn2; ///< Offset 218 DllBwEn value for 1600 + UINT8 DllBwEn3; ///< Offset 219 DllBwEn value for 1867 a= nd up + UINT8 RetrainOnFastFail; ///< Offset 220 Restart MRC in Cold mode= if SW MemTest fails during Fast flow. 0 =3D Disabled, 1 =3D Enabled + UINT8 ForceOltmOrRefresh2x; ///< Offset 221 Force OLTM or 2X Refresh= when needed. 0 =3D Force OLTM, 1 =3D Force 2x Refresh + UINT8 PowerDownMode; ///< Offset 222 CKE Power Down Mode: = 0xFF=3DAUTO, 0=3DNo Power Down, 1=3D APD mode, 6=3DPPD-DLL Off mode + UINT8 PwdwnIdleCounter; ///< Offset 223 CKE Power Down Mode Idle= Counter: 0=3DMinimal, 255=3DMaximum, 0x80=3D0x80 DCLK + UINT8 IsvtIoPort; ///< Offset 224 ISVT IO Port Address: 0= =3DMinimal, 0xFF=3DMaximum, 0x99=3DDefault + UINT8 CmdRanksTerminated; ///< Offset 225 LPDDR4: Bitmask of= ranks that have CA bus terminated. 0x01=3DDefault, Rank0 is terminating= and Rank1 is non-terminating + UINT8 GdxcEnable; ///< Offset 226 GDXC MOT enable + UINT8 GdxcIotSize; ///< Offset 227 IOT size in multip= les of 8MEG + UINT8 GdxcMotSize; ///< Offset 228 MOT size in multip= les of 8MEG + UINT8 RMTLoopCount; ///< Offset 229 Indicates the Loop Count= to be used for Rank Margin Tool Testing: 1=3DMinimal, 32=3DMaximum, 0=3DAU= TO, 0=3DDefault + UINT16 FreqSaGvMid; ///< Offset 230 SA GV: 0 is Auto/default= , otherwise holds the frequency value expressed as an integer: 0=3DDefau= lt, 1600, 1800, 1867, 2000, 2133, etc. + + UINT32 RmtPerTask:1; ///< Offset 232 Bit 0: Rank Margin= Tool Per Task. 0 =3D Disabled, 1 =3D Enabled + UINT32 TrainTrace:1; ///< Offset 232 Bit 1: Trained sta= te tracing debug. 0 =3D Disabled, 1 =3D Enabled + UINT32 SafeMode:1; ///< Offset 232 Bit 2: Define if s= afe mode is enabled for MC/IO + UINT32 EnBER:1; ///< Offset 232 Bit 3: Define if E= nBER is enabled for Rank Margin Tool + UINT32 Ddr4MixedUDimm2DpcLimit:1; ///< Offset 232 Bit 4: Enable/Disa= ble 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. 0= =3D Disabled, 1 =3D Enabled + UINT32 FastBootRmt:1; ///< Offset 232 Bit 5: Enable/Disa= ble RMT on FastBoot. 0 =3D Disabled, 1 =3D Enabled + UINT32 MrcTrainOnWarm:1; ///< Offset 232 Bit 6: Force MRC t= raining on warm boot : 0 =3D Disabled, 1 =3D Enabled + UINT32 LongFlyByModeEnabled:1; ///< Offset 232 Bit 7: Long FlyBy = Mode Enabled : 0 =3D Disabled, 1 =3D Enabled + UINT32 Off232RsvdBits:24; ///< Offset 232 Bit 8-31: Reserved + + // TurnAround Timing + UINT8 tRd2RdSG; ///< Offset 236 - Read-to-Read Same Gr= oup Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2RdDG; ///< Offset 237 - Read-to-Read Differe= nt Group Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. Sa= me Group and Different Group Timings must be the same for Non-DDR4 memory. + UINT8 tRd2RdDR; ///< Offset 238 - Read-to-Read Differe= nt Rank Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2RdDD; ///< Offset 239 - Read-to-Read Differe= nt DIMM Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2WrSG; ///< Offset 240 - Read-to-Write Same Gr= oup Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2WrDG; ///< Offset 241 - Read-to-Write Differe= nt Group Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. Sa= me Group and Different Group Timings must be the same for Non-DDR4 memory. + UINT8 tRd2WrDR; ///< Offset 242 - Read-to-Write Differe= nt Rank Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tRd2WrDD; ///< Offset 243 - Read-to-Write Differe= nt DIMM Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2RdSG; ///< Offset 244 - Write-to-Read Same Gr= oup Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 86=3DMaximum. + UINT8 tWr2RdDG; ///< Offset 245 - Write-to-Read Differe= nt Group Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. Sa= me Group and Different Group Timings must be the same for Non-DDR4 memory. + UINT8 tWr2RdDR; ///< Offset 246 - Write-to-Read Differe= nt Rank Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2RdDD; ///< Offset 247 - Write-to-Read Differe= nt DIMM Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2WrSG; ///< Offset 248 - Write-to-Write Same Gr= oup Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2WrDG; ///< Offset 249 - Write-to-Write Differe= nt Group Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. Sa= me Group and Different Group Timings must be the same for Non-DDR4 memory. + UINT8 tWr2WrDR; ///< Offset 250 - Write-to-Write Differe= nt Rank Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT8 tWr2WrDD; ///< Offset 251 - Write-to-Write Differe= nt DIMM Turn Around Timing: 0=3DAUTO, 4=3DMinimal, 64=3DMaximum. + UINT16 tRRD_L; ///< Offset 252 - User defined DDR= 4 Memory Timing tRRD_L value, valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 15=3DMaximum. + UINT16 tRRD_S; ///< Offset 254 - User defined DDR= 4 Memory Timing tRRD_S value, valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 15=3DMaximum. + UINT16 tWTR_L; ///< Offset 266 - User defined DDR= 4 Memory Timing tWTR_L value, valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 28=3DMaximum. + UINT16 tWTR_S; ///< Offset 268 - User defined DDR= 4 Memory Timing tWTR_S value, valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 28=3DMaximum. + +} MEMORY_CONFIGURATION; + +/// Memory Configuration +/// The contents of this structure are not CRC'd by the MRC for option cha= nge detection. +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Bl= ock Header + SA_FUNCTION_CALLS SaCall; ///< Offset 24 Function = calls into the SA. + SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 200 Function = calls into the MRC. + SPD_DATA_BUFFER *SpdData; ///< Offset 236 Memory SP= D data, will be used by the MRC when SPD SmBus address is zero. + SA_MEMORY_DQ_MAPPING *DqByteMap; ///< Offset 240 LPDDR3 DQ= byte mapping to CMD/CTL/CLK, from the CPU side. + SA_MEMORY_DQS_MAPPING *DqsMap; ///< Offset 244 LPDDR3 DQ= S byte swizzling between CPU and DRAM. + SA_MEMORY_RCOMP *RcompData; ///< Offset 248 DDR RCOMP= resistors and target values. + UINT64 PlatformMemorySize; ///< Offset 252 The minim= um platform memory size required to pass control into DXE + UINT32 CleanMemory:1; ///< Offset 260 Ask MRC t= o clear memory content: FALSE=3DDo not Clear Memory; TRUE=3DClear Me= mory + UINT32 MemTestOnWarmBoot:1; ///< Offset 260 Run Base = Memory Test On WarmBoot: 0=3DDisabled, 1=3DEnabled + UINT32 ReservedBits5:30; + /** + Sets the serial debug message level\n + 0x00 =3D Disabled\n + 0x01 =3D Errors only\n + 0x02 =3D Errors and Warnings\n + 0x03 =3D Errors, Warnings, and Info\n + 0x04 =3D Errors, Warnings, Info, and Events\n + 0x05 =3D Displays Memory Init Execution Time Summary only\n + **/ + UINT8 SerialDebugLevel; ///< Offset 264 + UINT8 Reserved11[3]; ///< Offset 265 Reserved +} MEMORY_CONFIG_NO_CRC; +#pragma pack(pop) + +#endif // _MEMORY_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/MemoryDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inc= lude/ConfigBlock/MemoryDxeConfig.h new file mode 100644 index 0000000000..9f01c172f2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Me= moryDxeConfig.h @@ -0,0 +1,61 @@ +/** @file + Memory DXE Policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEMORY_DXE_CONFIG_H_ +#define _MEMORY_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define MEMORY_DXE_CONFIG_REVISION 1 + +/** + The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mec= hanical present bit map. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header +/** + Offset 28: + Dimm SPD address + Only Server support 2 channels * 3 slots per channel =3D 6 sockets total= ly + The Desktop and mobile only support 2 channels * 2 slots per channel =3D= 4 sockets totally + So there is mapping rule here for Desktop and mobile that there are no m= ore 4 DIMMS totally in a system: + Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0] + Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1] + Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2] + Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3] + Refer to SmbiosMemory.c for use + If change the mapping rule, please update the Revision number. +**/ + UINT8 *SpdAddressTable; +/** + Offset 36: + Channel A DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -= > DIMM1, ... + if the bit is 1, the related DIMM slot is present. + E.g. if channel A has 2 DIMMs, ChannelASlotMap =3D 0x03; + E.g. if channel A has only 1 DIMMs, ChannelASlotMap =3D 0x01; + Refer to SmbiosMemory.c +**/ + UINT8 ChannelASlotMap; +/** + Offset 37: + Channel B DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -= > DIMM1, ... + if the bit is 1, the related DIMM slot is present. + E.g. if channel B has 2 DIMMs, ChannelBSlotMap =3D 0x03; + E.g. if channel B has only 1 DIMMs, ChannelBSlotMap =3D 0x01; + Refer to SmbiosMemory.c +**/ + UINT8 ChannelBSlotMap; + UINT8 MrcTimeMeasure; ///< Offset 38: MRC execution ti= me measurement: 0=3DDisable, 1=3DEnable + UINT8 MrcFastBoot; ///< Offset 39: Fast boot: 0=3DD= isable, 1=3DEnable +} MEMORY_DXE_CONFIG; +#pragma pack(pop) + +#endif // _MEMORY_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/MiscDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/MiscDxeConfig.h new file mode 100644 index 0000000000..7a8894a5c0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mi= scDxeConfig.h @@ -0,0 +1,33 @@ +/** @file + MISC DXE policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MISC_DXE_CONFIG_H_ +#define _MISC_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define MISC_DXE_CONFIG_REVISION 2 + +/** + This data structure includes miscellaneous configuration variables such = SA thermal device + control. The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. + Revision 2: + - Added RmrrCsmeBaseAddress fields. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config= Block Header + EFI_PHYSICAL_ADDRESS *RmrrUsbBaseAddress; ///< Offset 28 The fiel= d is used to describe the platform USB Reserved memory for Intel VT-d suppo= rt. Platform code should provide this information for Intel VT-d DXE driver= use + UINT32 EnableAbove4GBMmio : 1; ///< Offset 29:0 Enable= /disable above 4GB MMIO resource support: 0=3DDisable, 1=3DEnable + UINT32 RsvdBits0 : 31; ///< Offset 29:1 Reserv= ed bits. + EFI_PHYSICAL_ADDRESS *RmrrCsmeBaseAddress; ///< The field is used = to describe the CSME Reserved memory. +} MISC_DXE_CONFIG; +#pragma pack(pop) + +#endif // _MISC_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/OverClockingConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/= Include/ConfigBlock/OverClockingConfig.h new file mode 100644 index 0000000000..b623f14c15 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Ov= erClockingConfig.h @@ -0,0 +1,51 @@ +/** @file + Policy definition for System Agent overclocking Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _OVERCLOCKING_PREMEM_CONFIG__H_ +#define _OVERCLOCKING_PREMEM_CONFIG__H_ +#pragma pack(push, 1) + +#define SA_OVERCLOCKING_CONFIG_REVISION 2 + +/** + Defines the overclocking configuration parameters for System Agent.\n + Revision 1: + - Initial version. + Revision 2: + - Add GT unslice support. + +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header + /** + Offset 28:0 : + Enable disable of SA overclocking mailbox commands. + If disabled, or if PcdSaOcEnable is disabled, all other policies in this= config block are ignored. + 0=3DDisable, + 1=3DEnable + **/ + UINT32 OcSupport : 1; + UINT32 GtVoltageMode : 1; ///< Offset 28:1 :Specifies whethe= r GT voltage is operating in Adaptive or Override mode: 0=3DAdaptive= , 1=3DOverride + UINT32 RealtimeMemoryTiming : 1; ///< Offset 28:2 :Enable/Disable t= he message sent to the CPU to allow realtime memory timing changes after MR= C_DONE. 0=3DDisable, 1=3DEnable + UINT32 GtusVoltageMode : 1; ///< Offset 28:3 :Specifies whethe= r GT unslice voltage is operating in Adaptive or Override mode: 0=3DAdap= tive, 1=3DOverride + UINT32 RsvdBits0 : 28; ///< Offset 28:4 - 31 :Reserved fo= r future use + UINT8 GtMaxOcRatio; ///< Offset 32 Maximum GT turbo ra= tio override: 0=3DMinimal, 255=3DMaximum, 0=3DAUTO + UINT8 Rsvd0; ///< Offset 33 Reserved for DWORD = alignment + INT16 GtVoltageOffset; ///< Offset 34 The voltage offset = applied to GT slice. Valid range from -1000mv to 1000mv: 0=3DMinimal= , 1000=3DMaximum + UINT16 GtVoltageOverride; ///< Offset 36 The GT voltage over= ride which is applied to the entire range of GT frequencies 0=3DDefault<= /b> + UINT16 GtExtraTurboVoltage; ///< Offset 38 The adaptive voltag= e applied during turbo frequencies. Valid range from 0 to 2000mV: 0=3DMi= nimal, 2000=3DMaximum + INT16 SaVoltageOffset; ///< Offset 40 The voltage offset = applied to the SA. Valid range from -1000mv to 1000mv: 0=3DDefault + INT16 GtusVoltageOffset; ///< Offset 42 The voltage offset = applied to GT unslice. Valid range from -1000mv to 1000mv: 0=3DMinimal, 1000=3DMaximum + UINT16 GtusVoltageOverride; ///< Offset 44 The GT unslice volt= age override which is applied to the entire range of GT frequencies: 0= =3DDefault + UINT16 GtusExtraTurboVoltage; ///< Offset 46 The adaptive voltag= e applied during turbo frequencies. Valid range from 0 to 2000mV: 0=3DDe= fault + UINT8 GtusMaxOcRatio; ///< Offset 48 Maximum GTus turbo = ratio override: 0=3DMinimal, 6=3DMaximum, 0=3DAUTO + UINT8 Rsvd1[3]; ///< Offset 49-51 Reserved for DWO= RD alignment +} OVERCLOCKING_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _OVERCLOCKING_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/PcieDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/PcieDxeConfig.h new file mode 100644 index 0000000000..f0b9670f64 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pc= ieDxeConfig.h @@ -0,0 +1,135 @@ +/** @file + PCIE DXE policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_DXE_CONFIG_H_ +#define _PCIE_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define PCIE_DXE_CONFIG_REVISION 1 + +/// +/// Device List for special ASPM override +/// +typedef struct { + UINT16 VendorId; ///< Offset 0 PCI Configuration space offset 0 + UINT16 DeviceId; ///< Offset 2 PCI Configuration space offset 2 + UINT8 RevId; ///< Offset 4 PCI Configuration space offset 8= ; 0xFF means all steppings + UINT8 RootApmcMask; ///< Offset 5 Root ASPM override bit mask 0= =3DNo override + UINT8 EndpointApmcMask; ///< Offset 6 Endpoint ASPM override bit mask = 0=3DNo override + UINT8 Rsvd; ///< Offset 7 Reserved +} PCIE_ASPM_OVERRIDE_LIST; + +typedef struct { + UINT16 VendorId; ///< Offset 0 PCI Config space offset 0 + UINT16 DeviceId; ///< Offset 2 PCI Config space offset 2 +/** + Offset 4: + SnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are = valid + When clear values in bits 9:0 will be ignored + BIT[14] - Should be set to 0b + BIT[13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in the= se bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Snoop Latency Value. The value in these bits will be multi= plied with + the scale in bits 12:10 +**/ + UINT16 SnoopLatency; +/** + Offset 6: + NonSnoopLatency bit definition + Note: All Reserved bits must be set to 0 + + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are = valid + When clear values in bits 9:0 will be ignored + BIT[14] - Should be set to 0b + BIT[13] - Reserved + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in the= se bits + 000b - 1 ns + 001b - 32 ns + 010b - 1024 ns + 011b - 32,768 ns + 100b - 1,048,576 ns + 101b - 33,554,432 ns + 110b - Reserved + 111b - Reserved + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be m= ultiplied with + the scale in bits 12:10 +**/ + UINT16 NonSnoopLatency; + UINT8 RevId; ///< Offset 8 PCI Config space offset 8; 0xFF means = all steppings + UINT8 Rsvd0[3]; ///< Offset 9 +} PCIE_LTR_DEV_INFO; + +/// +/// PCIE Power Optimizer config +/// +typedef struct { + UINT16 LtrMaxSnoopLatency; ///< Offset 0 LTR Maximum Snoop Latency: <= b>0x0846=3D70us + UINT16 LtrMaxNoSnoopLatency; ///< Offset 2 LTR Maximum Non-Snoop Latenc= y: 0x0846=3D70us + UINT8 ObffEnable; ///< Offset 4 LTR enable/disable: 0=3DDisa= ble, 1=3DEnable + UINT8 LtrEnable; ///< Offset 5 LTR enable/disable: 0=3DDisa= ble, 1=3DEnable + UINT8 Rsvd0[2]; ///< Offset 6 Reserved +} SA_PCIE_PWR_OPT; + + +/** + The PCI Express Configuration info includes PCI Resources Range Base and= Limits and the control + for PEG ASPM. + The data elements should be initialized by a Platform Module.\n + @note Optional. These policies will be ignored if there is no PEG= port present on board. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-2= 7 Config Block Header +/** + Offset 28: This field is used to describe the ASPM control for PEG Ports= \n + 0=3DASPM Disabled, 1=3DASPM L0s Enabled, 2=3DASPM L1 Enabled, 3=3DASPM L= 0sL1 Enabled, 4=3DASPM AUTO +**/ + UINT8 PegAspm[SA_PEG_MAX_FUN]; +/** + Offset 32: This field is used to describe the PEG L0s advanced control + 0=3DASPM L0s disabled, 1=3DASPM L0s enabled on RP, 2=3DASPM L0s enabled = on EP, 3=3DASPM L0s enabled on both RP and EP +**/ + UINT8 PegAspmL0s[SA_PEG_MAX_FUN]; +/** + Offset 36: PCIe Hot Plug Enable/Disable. It has 2 policies. + - Disabled (0x0) : No hotplug. + - Enabled (0x1) : Bios assist hotplug. +**/ + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN]; +/** + Offset 40: This field is used as a pointer to the ASPM device override t= able, default points to an\n + existing table mPcieAspmDevsOverride\n + Refer to DxeSaPolicyLib.c for the usage. + Note: This exclusion list helps avoid potential system hangs. +**/ + PCIE_ASPM_OVERRIDE_LIST *PcieAspmDevsOverride; +/** + Offset 48: This field is used as a pointer to the LTR device override ta= ble, default points to an existing + table mPcieLtrDevsOverride.\n + Refer to DxeSaPolicyLib.c for the usage. +**/ + PCIE_LTR_DEV_INFO *PcieLtrDevsOverride; + SA_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< Offset 60: = This field is used to describe the PCIe LTR/OBFF relevant settings + UINT8 Rsvd1[3]; /// Reserved for= future use +} PCIE_DXE_CONFIG; +#pragma pack(pop) + +#endif // _PCIE_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/PciePeiConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/PciePeiConfig.h new file mode 100644 index 0000000000..7899504865 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pc= iePeiConfig.h @@ -0,0 +1,60 @@ +/** @file + Policy definition for PCIe Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_PEI_CONFIG_H_ +#define _PCIE_PEI_CONFIG_H_ + +#include +#include + +#pragma pack(push, 1) + +#define SA_PCIE_PEI_CONFIG_REVISION 1 + +/** + PCI Express and DMI controller configuration - PostMem\n + @note Optional. These policies will be ignored if there is no PEG = port present on board. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header + /** + Offset 28:0 + (Test)DMI Extended Sync Control + - Disabled (0x0) : Disable DMI Extended Sync (Default) + - Enabled (0x1) : Enable DMI Extended Sync + **/ + UINT32 DmiExtSync : 1; + /** + Offset 28:1 + (Test)DMI IOT Control + - Disabled (0x0) : Disable DMI IOT (Default) + - Enabled (0x1) : Enable DMI IOT + **/ + UINT32 DmiIot : 1; + UINT32 RsvdBits1 : 30; ///<= Offset 28:2-31 :Reserved for future use. + UINT8 DmiAspm; ///<= Offset 32 This field is used to describe the ASPM control for DMI: 3=3D= PcieAspmL0sL1, 2=3DPcieAspmL1, 1=3DPcieAspmL0s, 0=3DPcieAspmDisabled. + UINT8 Rsvd1[3]; ///<= Offset 33 to 35 + UINT8 PegDeEmphasis[SA_PEG_MAX_FUN]; ///<= Offset 36 This field is used to describe the DeEmphasis control for PEG (-= 6 dB and -3.5 dB are the options)SA_PEG_MAX_FUN =3D 3 for CFL and SA_PEG_MA= X_FUN =3D 4 for CNL, offsets are adjusted accordingly + UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///<= (Test) Offset 39/40 This field is used to describe the PEG Max Pay = Load Size (0xFF: Auto, 0:128B, 1:256B) + /** + PCIe Slot Power Capabilities. SlotPowerLimitValue in combination with S= lotPowerLimitScale specifies the upper limit on power supplied by slot. + **/ + UINT8 PegSlotPowerLimitValue[SA_PEG_MAX_FUN]; ///<= Offset 42/44 8 bit value + UINT8 PegSlotPowerLimitScale[SA_PEG_MAX_FUN]; ///<= Offset 45/48 2 bit value: 00 =3D 1.0x, 01 =3D 0.1x, 10 =3D 0.01x an= d 11 =3D 0.001x + /** + Offset 48/52 + PCIe Physical Slot Number (13 bit value). Indicates the physical slot n= umber attached to the port. + **/ + UINT16 PegPhysicalSlotNumber[SA_PEG_MAX_FUN]; + UINT8 Rsvd2[2]; +} PCIE_PEI_CONFIG; +#pragma pack(pop) + +#endif // _PCIE_PEI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/PciePeiPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent= /Include/ConfigBlock/PciePeiPreMemConfig.h new file mode 100644 index 0000000000..a53bf3c7bd --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pc= iePeiPreMemConfig.h @@ -0,0 +1,354 @@ +/** @file + Policy definition for PCIe Config Block + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIE_PEI_PREMEM_CONFIG_H_ +#define _PCIE_PEI_PREMEM_CONFIG_H_ + +#include +#include + +#pragma pack(push, 1) + +#define SA_PCIE_PEI_PREMEM_CONFIG_REVISION 3 + +/// +/// SA GPIO Data Structure +/// +typedef struct { + GPIO_PAD GpioPad; ///< Offset 0: GPIO Pad + UINT8 Value; ///< Offset 4: GPIO Value + UINT8 Rsvd0[3]; ///< Offset 5: Reserved for 4 bytes alignm= ent + UINT32 Active :1; ///< Offset 8: 0=3DActive Low; 1=3DActive = High + UINT32 RsvdBits0:31; +} SA_GPIO_INFO_PCIE; + +/// +/// SA Board PEG GPIO Info +/// +typedef struct { + SA_GPIO_INFO_PCIE SaPeg0ResetGpio; ///< Offset 0: PEG0 PERST# GPIO = assigned, must be a PCH GPIO pin + SA_GPIO_INFO_PCIE SaPeg3ResetGpio; ///< Offset 12: PEG3 PERST# GPIO = assigned, must be a PCH GPIO pin + BOOLEAN GpioSupport; ///< Offset 24: 1=3DSupported; 0= =3DNot Supported + UINT8 Rsvd0[3]; ///< Offset 25: Reserved for 4 by= tes alignment +} PEG_GPIO_DATA; + + +/** + PCI Express and DMI controller configuration\n + @note Optional. These policies will be ignored if there is no PEG = port present on board. + Revision 1: + - Initial version. + Revision 2: + - Change PegGen3RxCtleOverride of PCIE_PEI_PREMEM_CONFIG from one bit to= UINT8 + - Change DmiGen3RxCtlePeaking default to 0 + Revision 3: + - Added PEG IMR support + - Added UINT8 PegImrEnable + - Added UINT16 PegImrSize + - Added UINT8 ImrRpSelection +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///<= Offset 0-27 Config Block Header + /** + Offset 28:0 : + (Test) DMI Link Speed Control + - Auto (0x0) : Maximum possible link speed (Default) + - Gen1 (0x1) : Limit Link to Gen1 Speed + - Gen2 (0x2) : Limit Link to Gen2 Speed + - Gen3 (0x3) : Limit Link to Gen3 Speed + **/ + UINT32 DmiMaxLinkSpeed : 2; + /** + Offset 28:2 : + (Test) DMI Equalization Phase 2 Enable Control + - Disabled (0x0) : Disable phase 2 + - Enabled (0x1) : Enable phase 2 + - Auto (0x2) : Use the current default method (Default) + **/ + UINT32 DmiGen3EqPh2Enable : 2; + /** + Offset 28:4 : + (Test) Selects the method for performing Phase3 of Gen3 Equaliza= tion on DMI + - Auto (0x0) : Use the current default method (Default) + - HwEq (0x1) : Use Adaptive Hardware Equalization + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented i= n BIOS Reference Code) + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPre= set array for Phase1 AND Phase3 (Instead of just Phase1) + - Disabled (0x4) : Bypass Equalization Phase 3 + **/ + UINT32 DmiGen3EqPh3Method : 3; + /** + Offset 28:7 : + (Test) Program DMI Gen3 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 DmiGen3ProgramStaticEq : 1; + + /** + Offset 28:8 to 28:15 : + (Test) PEG Enable Control + - Disabled (0x0) : Disable PEG Port + - Enabled (0x1) : Enable PEG Port (If Silicon SKU permits it) + - Auto (0x2) : If an endpoint is present, enable the PEG Port, D= isable otherwise (Default) + **/ + UINT32 Peg0Enable : 2; ///<= Enable/Disable PEG 0:1:0 Root Port + UINT32 Peg1Enable : 2; ///<= (Test) Enable/Disable PEG 0:1:1 Root Port + UINT32 Peg2Enable : 2; ///<= (Test) Enable/Disable PEG 0:1:2 Root Port + UINT32 Peg3Enable : 2; ///<= (Test) Enable/Disable PEG 0:6:0 Root Port. + + /** + Offset 28:16 : + (Test) PCIe Link Speed Control + - Auto (0x0) : Maximum possible Link speed (Default) + - Gen1 (0x1) : Limit Link to Gen1 Speed + - Gen2 (0x2) : Limit Link to Gen2 Speed + - Gen3 (0x3) : Limit Link to Gen3 Speed + **/ + UINT32 Peg0MaxLinkSpeed : 2; ///<= PCIe Link Speed Control for PEG 0:1:0 Root Port. + UINT32 Peg1MaxLinkSpeed : 2; ///<= (Test) PCIe Link Speed Control for PEG 0:1:1 Root Port. + UINT32 Peg2MaxLinkSpeed : 2; ///<= (Test) PCIe Link Speed Control for PEG 0:1:2 Root Port. + UINT32 Peg3MaxLinkSpeed : 2; ///<= (Test) PCIe Link Speed Control for PEG 0:6:0 Root Port. + UINT32 RsvdBits0 : 8; ///<= Offset 28:24 :Reserved for future use + + /** + Offset 32:0 : + (Test) PCIe Link Width Control + - Auto (0x0) : Maximum possible Link width (Default) + - X1 (0x1) : Limit Link to X1 Width + - X2 (0x2) : Limit Link to X2 Width + - X4 (0x3) : Limit Link to X4 Width + - X8 (0x4) : Limit Link to X8 Width + **/ + UINT32 Peg0MaxLinkWidth : 3; ///<= PCIe Link Width Control for PEG 0:1:0 Root Port. + UINT32 Peg1MaxLinkWidth : 3; ///<= (Test) PCIe Link Width Control for PEG 0:1:1 Root Port. + UINT32 Peg2MaxLinkWidth : 3; ///<= (Test) PCIe Link Width Control for PEG 0:1:2 Root Port. + UINT32 Peg3MaxLinkWidth : 3; ///<= (Test) PCIe Link Width Control for PEG 0:6:0 Root Port. + /** + Offset 32:12 to 32:15 : + Power down unused lanes on the PEG Root Port. + - Disabled (0x0) : No power saving. + - Auto (0x1) : Bios will power down unused lanes based on the ma= x possible link width + **/ + UINT32 Peg0PowerDownUnusedLanes : 1; ///<= Power down unused lanes on the PEG 0:1:0 Root Port. + UINT32 Peg1PowerDownUnusedLanes : 1; ///<= Power down unused lanes on the PEG 0:1:1 Root Port. + UINT32 Peg2PowerDownUnusedLanes : 1; ///<= Power down unused lanes on the PEG 0:1:2 Root Port. + UINT32 Peg3PowerDownUnusedLanes : 1; ///<= Power down unused lanes on the PEG 0:6:0 Root Port. + + /** + Offset 32:16 to 32:23 : + (Test) PCIe Equalization Phase 2 Enable Control + - Disabled (0x0) : Disable phase 2 + - Enabled (0x1) : Enable phase 2 + - Auto (0x2) : Use the current default method (Default) + **/ + UINT32 Peg0Gen3EqPh2Enable : 2; ///<= Phase2 EQ enable on the PEG 0:1:0 Root Port. + UINT32 Peg1Gen3EqPh2Enable : 2; ///<= (Test) Phase2 EQ enable on the PEG 0:1:1 Root Port. + UINT32 Peg2Gen3EqPh2Enable : 2; ///<= (Test) Phase2 EQ enable on the PEG 0:1:2 Root Port. + UINT32 Peg3Gen3EqPh2Enable : 2; ///<= (Test) Phase2 EQ enable on the PEG 0:6:0 Root Port. + UINT32 RsvdBits1 : 8; ///<= Offset 32:24 :Reserved for future use + /** + Offset 36:0 to 36:11 : + (Test) Select the method for performing Phase3 of Gen3 Equalizat= ion. + - Auto (0x0) : Use the current default method (Default) + - HwEq (0x1) : Use Adaptive Hardware Equalization + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented i= n BIOS Reference Code) + - Static (0x3) : Use the Static EQs provided in PegGen3EndPointPre= set array for Phase1 AND Phase3 (Instead of just Phase1) + - Disabled (0x4) : Bypass Equalization Phase 3 + **/ + UINT32 Peg0Gen3EqPh3Method : 3; ///<= Phase3 EQ method on the PEG 0:1:0 Root Port. + UINT32 Peg1Gen3EqPh3Method : 3; ///<= (Test) Phase3 EQ method on the PEG 0:1:1 Root Port. + UINT32 Peg2Gen3EqPh3Method : 3; ///<= (Test) Phase3 EQ method on the PEG 0:1:2 Root Port. + UINT32 Peg3Gen3EqPh3Method : 3; ///<= (Test) Phase3 EQ method on the PEG 0:6:0 Root Port. + /** + Offset 36:12 : + (Test) Program PEG Gen3 EQ Phase1 Static Presets + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default) + **/ + UINT32 PegGen3ProgramStaticEq : 1; + /** + Offset 36:13 : + (Test) Always Attempt Gen3 Software Equalization + + When enabled, Gen3 Software Equalization will be executed every boot. = When disabled, it will be only executed if the CPU + or EP is changed, otherwise it is skipped and the previous EQ value wil= l be re-used. + + This setting will only have an effect if Software Equalization is enabl= ed and OEM Platform Code implements + save/restore of the PegDataPtr data (see below). If PegDataPtr is not = saved/restored RC forces this to be enabled. + + - Disabled (0x0) : Reuse EQ settings saved/restored from NVRAM w= henever possible (Default) + - Enabled (0x1) : Re-test and generate new EQ values every boot= , not recommended + **/ + UINT32 Gen3SwEqAlwaysAttempt : 1; + /** + Offset 36:14 to 36:16 : + (Test) Select number of TxEq presets to test in the PCIe/DMI Sof= tware Equalization Algorithm + - P7,P3,P5,P8 (0x0) : Test Presets 7, 3, 5, and 8 + - P0-P9 (0x1) : Test Presets 0-9 + - Auto (0x2) : Use the current default method (Default) + Auto will test Presets 7, 3, 5, and 8. It is possible for this default = to change over time; + using "Auto" will ensure Reference Code always uses the latest default s= ettings. + @warning Do not change from the default. Hard to detect issues are like= ly. + **/ + UINT32 Gen3SwEqNumberOfPresets : 3; + /** + Offset 36:17 to 36:18: + (Test) Offset 36 Enable use of the Voltage Offset and Centering = Test in the PCIe Software Equalization Algorithm + - Disabled (0x0) : Disable VOC Test + - Enabled (0x1) : Enable VOC Test + - Auto (0x2) : Use the current default (Default) + **/ + UINT32 Gen3SwEqEnableVocTest : 2; + /** + Offset 36:19 : + Select when PCIe ASPM programming will happen in relation to the Oprom + - Before (0x0) : Do PCIe ASPM programming before Oprom. (Default) + - After (0x1) : Do PCIe ASPM programming after Oprom. This will = require an SMI handler to save/restore ASPM settings. + **/ + UINT32 InitPcieAspmAfterOprom : 1; + /** + Offset 36:20 : + (Test) PCIe Rx Compliance Testing Mode + - Disabled (0x0) : Normal Operation - Disable PCIe Rx= Compliance testing (Default) + - Enabled (0x1) : PCIe Rx Compliance Test Mode - PEG controller = is in Rx Compliance Testing Mode; it should only be set when doing PCIe com= pliance testing + **/ + UINT32 PegRxCemTestingMode : 1; + + /** + Offset 36:21 to 36:24 : + (Test) PCIe Rx Compliance Loopback Lane + + When PegRxCemTestingMode is Enabled, the specificied Lane (0 - 15) wil= l be + used for RxCEMLoopback. + + Default is Lane 0. + **/ + UINT32 PegRxCemLoopbackLane : 4; + /** + Offset 36:25 to 36:28 : + (Test) Generate PCIe BDAT Margin Table. Set this policy to enabl= e the generation and addition of PCIe margin data to the BDAT table. + - Disabled (0x0) : Normal Operation - Disable PCIe BDAT = margin data generation (Default) + - PortData (0x1) : Port Data - Generate PCIe BDAT= margin data + **/ + UINT32 PegGenerateBdatMarginTable : 4; + /** + Offset 36:29 : + (Test) PCIe Non-Protocol Awareness for Rx Compliance Testing + - Disabled (0x0) : Normal Operation - Disable non-= protocol awareness (Default) + - Enabled (0x1) : Non-Protocol Awareness Enabled - Enable non-p= rotocol awareness for compliance testing + **/ + UINT32 PegRxCemNonProtocolAwareness : 1; + /** + Offset 36:30 : + (Test) PCIe Disable Spread Spectrum Clocking. This feature shoul= d be TRUE only for compliance testing + - False (0x0) : Normal Operation - SSC e= nabled (Default) + - True (0x1) : Disable SSC - Disab= le SSC for compliance testing + **/ + UINT32 PegDisableSpreadSpectrumClocking : 1; + + UINT32 RsvdBits2 : 1; + + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<= Offset 40 Used for programming DMI Gen3 preset values per lane. Range: 0-9= , 8 is default for each lane + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<= Offset 44 Used for programming DMI Gen3 preset values per lane. Range: 0-9= , 7 is default for each lane + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///<= Offset 48 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is= default for each lane + /** + Offset 52 : + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15)= . This setting + has to be specified based upon platform design and must follow the guid= eline. Default is 0. + **/ + + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE]; + + UINT8 PegGen3RootPortPreset[SA_PEG_MAX_LANE]; ///<= Offset 54 (Test) Used for programming PEG Gen3 preset values per la= ne. Range: 0-9, 8 is default for each lane + UINT8 PegGen3EndPointPreset[SA_PEG_MAX_LANE]; ///<= Offset 70 (Test) Used for programming PEG Gen3 preset values per la= ne. Range: 0-9, 7 is default for each lane + UINT8 PegGen3EndPointHint[SA_PEG_MAX_LANE]; ///<= Offset 86 (Test) Hint value per lane for the PEG Gen3 End Point. Ra= nge: 0-6, 2 is default for each lane + /** + Offset 102: + PCIe Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15= ). This setting + has to be specified based upon platform design and must follow the guid= eline. Default is 12. + **/ + UINT8 PegGen3RxCtlePeaking[SA_PEG_MAX_BUNDLE]; + /** + Offset 110: + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, d= efault is 1000. + @warning Do not change from the default. Hard to detect issues are like= ly. + @note An attack on this policy could result in an apparent hang, + but the system will eventually boot. This variable should be protecte= d. + **/ + UINT16 Gen3SwEqJitterDwellTime; + /** + Offset 112: + This is a memory data pointer for saved preset search results. The refe= rence code will store + the Gen3 Preset Search results in the SaPegHob. In order to skip the Ge= n3 + preset search on boots where the PEG card configuration has not changed= since the previous boot, + platform code can save the contents of the SaPegHob in DXE (When it pre= sent and for size reported by Header.HobLength) + and provide a pointer to a restored copy of that data. Default value is= NULL, which results in a full + preset search every boot. + + @note An attack on this policy could prevent the PCIe display from work= ing until a boot when + PegDataPtr is NULL or Gen3SwEqAlwaysAttempt is enabled. The variable u= sed to save the + preset search results should be protected in a way that it can only be = modified by the + platform manufacturer. + **/ + VOID *PegDataPtr; + /** + Offset 116: + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, d= efault is 1. + @warning Do not change from the default. Hard to detect issues are like= ly. + **/ + UINT16 Gen3SwEqJitterErrorTarget; + + /** + Offset 118: + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, d= efault is 10000. + @warning Do not change from the default. Hard to detect issues are like= ly. + @note An attack on this policy could result in an apparent hang, + but the system will eventually boot. This variable should be protecte= d. + **/ + UINT16 Gen3SwEqVocDwellTime; + + /** + Offset 120: + (Test)Used for PCIe Gen3 Software Equalization. Range: 0-65535, d= efault is 2. + @warning Do not change from the default. Hard to detect issues are like= ly. + **/ + UINT16 Gen3SwEqVocErrorTarget; + /** + Offset 122: + PCIe Hot Plug Enable/Disable. It has 2 policies. + - Disabled (0x0) : No hotplug. + - Enabled (0x1) : Bios assist hotplug. + **/ + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN]; + UINT8 DmiDeEmphasis; ///<= Offset 125 This field is used to describe the DeEmphasis control for DMI (= -6 dB and -3.5 dB are the options) + UINT8 Rsvd0[2]; ///<= Offset 126 + /** + Offset 128: + This contains the PCIe PERST# GPIO information. This structure is requ= ired + for PCIe Gen3 operation. The reference code will use the information in= this structure in + order to reset PCIe Gen3 devices during equalization, if necessary. Re= fer to the Platform + Developer's Guide (PDG) for additional details. + **/ + PEG_GPIO_DATA PegGpioData; + + /** + Offset 156 + (Test) PCIe Override RxCTLE. This feature should only be true to= disable RxCTLE adaptive behavior for compliance testing + - False (0x0) : Normal Operation - RxCTL= E adaptive behavior enabled (Default) + - True (0x1) : Override RxCTLE - Disab= le RxCTLE adaptive behavior to keep the configured RxCTLE peak values unmod= ified + From CFL onwards, modularity is introduced to this setup option so that = the RxCTLE adaptive behavior could be controlled at the controller level. + Making this variable a UINT8 to accomodate the values of all controllers= as bit definition + **/ + UINT8 PegGen3RxCtleOverride; + UINT8 Reserved1; + UINT16 Reserved2; + +} PCIE_PEI_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _PCIE_PEI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/SaMiscPeiConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inc= lude/ConfigBlock/SaMiscPeiConfig.h new file mode 100644 index 0000000000..12648b836b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Sa= MiscPeiConfig.h @@ -0,0 +1,61 @@ +/** @file + Policy details for miscellaneous configuration in System Agent + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_MISC_PEI_CONFIG_H_ +#define _SA_MISC_PEI_CONFIG_H_ + +#pragma pack(push, 1) + +#ifndef SA_MC_MAX_SOCKETS +#define SA_MC_MAX_SOCKETS 4 +#endif + +#define SA_MISC_PEI_CONFIG_REVISION 1 + +/// +/// Subsystem Vendor ID / Subsystem ID +/// +typedef struct _SA_DEFAULT_SVID_SID{ + UINT16 SubSystemVendorId; + UINT16 SubSystemId; +} SA_DEFAULT_SVID_SID; + +/** + This configuration block is to configure SA Miscellaneous variables duri= ng PEI Post-Mem.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + /** + Offset 28:0 + This policy is used to control enable or disable System Agent Thermal de= vice (0,4,0). + The default value is 1: TRUE for WHL, and 0: FALSE for all= other CPU's + **/ + UINT32 Device4Enable:1; + /** + Offset 28:1 + (Test)This policy is used to control enable or disable System Age= nt Chap device (0,7,0). + 0=3DFALSE, + 1=3DTRUE. + **/ + UINT32 ChapDeviceEnable:1; + /** + Offset 28:2 + For Platforms supporting Intel(R) SIPP, this policy is use control enabl= e/disable Compatibility Revision ID (CRID) feature. + 0=3DFALSE, + 1=3DTRUE + **/ + UINT32 CridEnable:1; + UINT32 SkipPamLock:1; ///< Offset 28:3 :To skip PAM= register locking. @note It is still recommended to set PCI Config space B0= : D0: F0: Offset 80h[0]=3D1 in platform code even Silicon code skipped this= .\n 0=3DAll PAM registers will be locked in Silicon code, 1=3DSkip l= ock PAM registers in Silicon code. + UINT32 EdramTestMode:2; ///< Offset 28:4 :EDRAM Test = Mode. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, 2- = EDRAM HW Mode + UINT32 RsvdBits0 :26; ///< Offset 28:7 :Reserved fo= r future use +} SA_MISC_PEI_CONFIG; +#pragma pack(pop) + +#endif // _SA_MISC_PEI_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/SaMiscPeiPreMemConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAge= nt/Include/ConfigBlock/SaMiscPeiPreMemConfig.h new file mode 100644 index 0000000000..2c831404ef --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Sa= MiscPeiPreMemConfig.h @@ -0,0 +1,103 @@ +/** @file + Policy details for miscellaneous configuration in System Agent + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_ +#define _SA_MISC_PEI_PREMEM_CONFIG_H_ + +#pragma pack(push, 1) + +#ifndef SA_MC_MAX_SOCKETS +#define SA_MC_MAX_SOCKETS 4 +#endif + +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 3 + +/** + This configuration block is to configure SA Miscellaneous variables duri= ng PEI Pre-Mem phase like programming + different System Agent BARs, TsegSize, IedSize, MmioSize required etc. + Revision 1: + - Initial version. + Revision 2: + - add BdatTestType, default is RMT + Revision 3: + - Remove SgSubSystemId. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT8 SpdAddressTable[SA_MC_MAX_SOCKETS];///< Offset 28 Memory DIMMs' = SPD address for reading SPD data. example: SpdAddressTable[0]=3D0xA2(C0D= 0), SpdAddressTable[1]=3D0xA0(C0D1), SpdAddressTable[2]=3D0xA2(C1D0), SpdAd= dressTable[3]=3D0xA0(C1D1) + VOID *S3DataPtr; ///< Offset 32 Memory data sa= ve pointer for S3 resume. The memory space should be allocated and filled w= ith proper S3 resume data on a resume path + UINT32 MchBar; ///< Offset 36 Address of Sys= tem Agent MCHBAR: 0xFED10000 + UINT32 DmiBar; ///< Offset 40 Address of Sys= tem Agent DMIBAR: 0xFED18000 + UINT32 EpBar; ///< Offset 44 Address of Sys= tem Agent EPBAR: 0xFED19000 + UINT32 SmbusBar; ///< Offset 48 Address of Sys= tem Agent SMBUS BAR: 0xEFA0 + UINT32 GdxcBar; ///< Offset 52 Address of Sys= tem Agent GDXCBAR: 0xFED84000 + /** + Offset 56 Size of TSEG in bytes. (Must be power of 2) + 0x400000: 4MB for Release build (When IED enabled, it will be 8= MB) + 0x1000000 : 16MB for Debug build (Regardless IED enabled or disab= led) + **/ + UINT32 TsegSize; + UINT32 EdramBar; ///< Offset 60 Address of Sys= tem Agent EDRAMBAR: 0xFED80000 + /** + Offset 64 + (Test) Size of IED region in bytes. + 0 : IED Disabled (no memory occupied) + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG) + Note: Enabling IED may also enlarge TsegSize together. + **/ + UINT32 IedSize; + UINT8 UserBd; ///< Offset 68 0=3DMobile/= Mobile Halo, 1=3DDesktop/DT Halo, 5=3DULT/ULX/Mobile Halo, 7=3DUP Server + UINT8 SgMode; ///< Offset 69 SgMode: 0= =3DDisabled, 1=3DSG Muxed, 2=3DSG Muxless, 3=3DPEG + UINT16 SgDelayAfterPwrEn; ///< Offset 70 Dgpu Delay aft= er Power enable using Setup option: 0=3DMinimal, 1000=3DMaximum, 300=3D3= 00 microseconds + UINT16 SgDelayAfterHoldReset; ///< Offset 72 Dgpu Delay aft= er Hold Reset using Setup option: 0=3DMinimal, 1000=3DMaximum, 100=3D100= microseconds + UINT32 SkipExtGfxScan:1; ///< (Test) OFfset 74:= 0 :1=3DSkip External Gfx Device Scan; 0=3DScan for external graphics dev= ices. Set this policy to skip External Graphics card scanning if the pl= atform uses Internal Graphics only. + UINT32 BdatEnable:1; ///< Offset 74:1 :This field = enables the generation of the BIOS DATA ACPI Tables: 0=3DFALSE, 1=3D= TRUE. + UINT32 TxtImplemented:1; ///< OFfset 74:2 :This field = currently is used to tell MRC if it should run after TXT initializatoin com= pleted: 0=3DRun without waiting for TXT, 1=3DRun after TXT initializ= ation by callback + /** + Offset 74:3 : + (Test) Scan External Discrete Graphics Devices for Legacy Only V= GA OpROMs + + When enabled, if the primary graphics device is an external discrete gr= aphics device, Si will scan the + graphics device for legacy only VGA OpROMs. If the primary graphics de= vice only implements legacy VBIOS, then the + LegacyOnlyVgaOpRomDetected field in the SA_DATA_HOB will be set to 1. + + This is intended to ease the implementation of a BIOS feature to automa= tically enable CSM if the Primary Gfx device + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling = CSM won't result in no video being displayed. + This is useful for platforms that implement PCIe slots that allow the e= nd user to install an arbitrary Gfx device. + + This setting will only take effect if SkipExtGfxScan =3D=3D 0. It is i= gnored otherwise. + + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Defaul= t) + - Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM + **/ + UINT32 ScanExtGfxForLegacyOpRom:1; + UINT32 RsvdBits0 :28; ///< OFfset 74:4 :Reserved fo= r future use + UINT8 LockPTMregs; ///< (Test) Offset 78 = Lock PCU Thermal Management registers: 0=3DFALSE, 1=3DTRUE + UINT8 BdatTestType; ///< Offset 79 When BdatEnabl= e is set to TRUE, this option selects the type of data which will be popula= ted in the BIOS Data ACPI Tables: 0=3DRMT, 1=3DRMT Per Bit, 2=3DMarg= in 2D. + UINT8 Rsvd1[4]; ///< Offset 80 Reserved for f= uture use + /** + Offset 84 : + Size of reserved MMIO space for PCI devices\n + 0=3DAUTO, 512=3D512MB, 768=3D768MB, 1024=3D1024MB, 1280=3D1280M= B, 1536=3D1536MB, 1792=3D1792MB, + 2048=3D2048MB, 2304=3D2304MB, 2560=3D2560MB, 2816=3D2816MB, 3072=3D307= 2MB\n + When AUTO mode selected, the MMIO size will be calculated by required = MMIO size from PCIe devices detected. + **/ + UINT16 MmioSize; + INT16 MmioSizeAdjustment; ///< Offset 86 Increase (give= n positive value) or Decrease (given negative value) the Reserved MMIO size= when Dynamic Tolud/AUTO mode enabled (in MBs): 0=3Dno adjustment + UINT64 AcpiReservedMemoryBase; ///< Offset 88 The Base addre= ss of a Reserved memory buffer allocated in previous boot for S3 resume use= d. Originally it is retrieved from AcpiVariableCompatibility variable. + UINT64 SystemMemoryLength; ///< Offset 96 Total system m= emory length from previous boot, this is required for S3 resume. Originally= it is retrieved from AcpiVariableCompatibility variable. + UINT32 AcpiReservedMemorySize; ///< Offset 104 The Size of a= Reserved memory buffer allocated in previous boot for S3 resume used. Orig= inally it is retrieved from AcpiVariableCompatibility variable. + UINT32 OpRomScanTempMmioBar; ///< (Test) Offset 108= Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanEx= tGfxForLegacyOpRom feature. MUST BE 16MB ALIGNED! + UINT32 OpRomScanTempMmioLimit; ///< (Test) Offset 112= Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom fea= ture. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >=3D 16MB! + + // Since the biggest element is UINT64, this structure should be aligned= with 64 bits. + UINT8 Rsvd[4]; ///< Reserved for config bloc= k alignment. +} SA_MISC_PEI_PREMEM_CONFIG; +#pragma pack(pop) + +#endif // _SA_MISC_PEI_PREMEM_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/SwitchableGraphicsConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/System= Agent/Include/ConfigBlock/SwitchableGraphicsConfig.h new file mode 100644 index 0000000000..cc6179a61c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Sw= itchableGraphicsConfig.h @@ -0,0 +1,63 @@ +/** @file + Switchable Graphics policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SWITCHABLE_GRAPHICS_CONFIG_H_ +#define _SWITCHABLE_GRAPHICS_CONFIG_H_ + +#define SWITCHABLE_GRAPHICS_CONFIG_REVISION 1 + +#define GP_ENABLE 1 +#define GP_DISABLE 0 + +#pragma pack(push, 1) +/// +/// GPIO Support +/// +typedef enum { + NotSupported =3D 0, + PchGpio, + I2CGpio, +} GPIO_SUPPORT; + +/// +/// SA GPIO Data Structure +/// +typedef struct { + UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO + BOOLEAN Active; ///< Offset 1 0=3DActive Low; 1=3DActive High + UINT8 Rsvd0[2]; ///< Offset 2 Reserved + UINT32 GpioNo; ///< Offset 4 GPIO pad +} SA_GPIO_INFO; + +/** + SA PCIE RTD3 GPIO Data Structure +**/ +typedef struct { + SA_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe HLD RE= SET GPIO value and level information + SA_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe PWR En= able GPIO value and level information + UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe RTD3 = Device Wake GPIO Number + UINT8 GpioSupport; ///< Offset 20 Depends on board design the G= PIO configuration may be different: 0=3DNot Supported, 1=3DPCH Based= , 2=3DI2C based + UINT8 Rsvd0[3]; ///< Offset 21 +} SA_PCIE_RTD3_GPIO; + +/** + This Configuration block configures SA PCI Express 0/1/2 RTD3 GPIOs & Ro= ot Port. + Swithable Gfx/Hybrid Gfx uses the same GPIOs & Root port as PCI Express = 0/1/2 RTD3. + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block He= ader + SA_PCIE_RTD3_GPIO SaRtd3Pcie0Gpio; ///< Offset 28 RTD3 GPIOs used f= or PCIe0 + SA_PCIE_RTD3_GPIO SaRtd3Pcie1Gpio; ///< Offset 52 RTD3 GPIOs used f= or PCIe1 + SA_PCIE_RTD3_GPIO SaRtd3Pcie2Gpio; ///< Offset 76 RTD3 GPIOs used f= or PCIe2 + UINT8 RootPortIndex; ///< Offset 124 Root Port Index = number used for SG + UINT8 Rsvd0[3]; ///< Offset 125 Reserved for DWO= RD Alignment +} SWITCHABLE_GRAPHICS_CONFIG; +#pragma pack(pop) +#endif // _SWITCHABLE_GRAPHICS_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/VbiosDxeConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Incl= ude/ConfigBlock/VbiosDxeConfig.h new file mode 100644 index 0000000000..690ad8630a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Vb= iosDxeConfig.h @@ -0,0 +1,39 @@ +/** @file + VBIOS DXE policy definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _VBIOS_DXE_CONFIG_H_ +#define _VBIOS_DXE_CONFIG_H_ + +#pragma pack(push, 1) + +#define VBIOS_DXE_CONFIG_REVISION 1 + +/** + This data structure includes Switchable Graphics VBIOS configuration. + If Switchable Graphics/Hybrid Gfaphics feature is not supported, all the= policies in this configuration block can be ignored. + The data elements should be initialized by a Platform Module.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header + UINT8 LoadVbios : 1; ///< Offset 28:0 :This field = is used to describe if the dGPU VBIOS needs to be loaded: 0=3DNot load, 1=3DLoad + UINT8 ExecuteVbios : 1; ///< Offset 28:1 :This field = is used to describe if the dGPU VBIOS need to be executed: 0=3DNot execu= te, 1=3DExecute +/** + Offset 28:2 : + This field is used to identify the source location of dGPU VBIOS\n + 1 =3D secondary display device VBIOS Source is PCI Card\n + 0 =3D secondary display device VBIOS Source is FW Volume\n +**/ + UINT8 VbiosSource : 1; + UINT8 RsvdBits0 : 5; ///< Offset 28:3 Reserved for= future use + UINT8 Rsvd[3]; ///< Offset 29 : Reserved for= DWORD alignment +} VBIOS_DXE_CONFIG; +#pragma pack(pop) + +#endif // _VBIOS_DXE_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigB= lock/VtdConfig.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/C= onfigBlock/VtdConfig.h new file mode 100644 index 0000000000..adde1f836b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/ConfigBlock/Vt= dConfig.h @@ -0,0 +1,42 @@ +/** @file + VT-d policy definitions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _VTD_CONFIG_H_ +#define _VTD_CONFIG_H_ + +#pragma pack(push, 1) + +#define VTD_CONFIG_REVISION 2 + +/** + The data elements should be initialized by a Platform Module. + The data structure is for VT-d driver initialization\n + Revision 1: + - Initial version. + Revision 2: + - Add DMA_CONTROL_GUARANTEE bit in the DMAR table +**/ +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Confi= g Block Header + /** + Offset 28:0 : + VT-D Support can be verified by reading CAP ID register as expalined i= n BIOS Spec. + This policy is for debug purpose only. + If VT-D is not supported, all other policies in this config block will= be ignored. + 0 =3D To use Vt-d; + 1 =3D Avoids programming Vtd bars, Vtd overrides and DMAR table. + **/ + UINT32 VtdDisable : 1; + UINT32 X2ApicOptOut : 1; ///< Offset 28:1 :This= field is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=3DEnab= le/Set and 0=3DDisable/Clear + UINT32 DmaControlGuarantee : 1; ///< Offset 28:2 :This= field is used to enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1= =3DEnable/Set and 0=3DDisable/Clear + UINT32 RsvdBits0 : 29; ///< Offset 28:3 :Rese= rved bits for future use + UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< Offset 32: This f= ield is used to describe the base addresses for VT-d function: BaseAddre= ss[0]=3D0xFED90000, BaseAddress[1]=3D0xFED92000, BaseAddress[2]=3D0xFED9100= 0 +} VTD_CONFIG; +#pragma pack(pop) + +#endif // _VTD_CONFIG_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRema= ppingTable.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRe= mappingTable.h new file mode 100644 index 0000000000..a1d88cb5a2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/DmaRemappingTa= ble.h @@ -0,0 +1,77 @@ +/** @file + This code defines ACPI DMA Remapping table related definitions. + See the System Agent BIOS specification for definition of the table. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DMA_REMAPPING_TABLE_H_ +#define _DMA_REMAPPING_TABLE_H_ + +#include +#include +#include +#include + +#pragma pack(1) +/// +/// DMAR table signature +/// +#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE 0x52414D44 ///< "DMAR" +#define EFI_ACPI_DMAR_TABLE_REVISION 1 +#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH 0x10 +#define EFI_ACPI_RMRR_HEADER_LENGTH 0x18 +#define MAX_PCI_DEPTH 5 + +typedef struct { + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER DeviceScopeStructureHeader; + EFI_ACPI_DMAR_PCI_PATH PciPath; // device, func= tion +} EFI_ACPI_DEV_SCOPE_STRUCTURE; + +typedef struct { + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; +} EFI_ACPI_DRHD_ENGINE1_STRUCT; + +typedef struct { + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader; + // + // @todo use PCD + // + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2]; +} EFI_ACPI_DRHD_ENGINE3_STRUCT; + +typedef struct { + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2]; +} EFI_ACPI_RMRR_USB_STRUC; + +typedef struct { + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD +} EFI_ACPI_RMRR_IGD_STRUC; + +typedef struct { + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader; + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // CSME +} EFI_ACPI_RMRR_CSME_STRUC; + +typedef struct { + EFI_ACPI_DMAR_ANDD_HEADER AnddHeader; + UINT8 AcpiObjectName[20]; +} EFI_ACPI_ANDD_STRUC; + +typedef struct { + EFI_ACPI_DMAR_HEADER DmarHeader; + EFI_ACPI_DRHD_ENGINE1_STRUCT DrhdEngine1; + EFI_ACPI_DRHD_ENGINE3_STRUCT DrhdEngine3; + EFI_ACPI_RMRR_USB_STRUC RmrrUsb; + EFI_ACPI_RMRR_IGD_STRUC RmrrIgd; + EFI_ACPI_RMRR_CSME_STRUC RmrrCsme; +} EFI_ACPI_DMAR_TABLE; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library= /DxeSaPolicyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/= Library/DxeSaPolicyLib.h new file mode 100644 index 0000000000..663b0f2202 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/DxeSaP= olicyLib.h @@ -0,0 +1,60 @@ +/** @file + Prototype of the DxeSaPolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SA_POLICY_LIB_H_ +#define _DXE_SA_POLICY_LIB_H_ + +#include + +/** + This function prints the DXE phase policy. + + @param[in] SaPolicy - SA DXE Policy protocol +**/ +VOID +SaPrintPolicyProtocol ( + IN SA_POLICY_PROTOCOL *SaPolicy + ) +; + +/** + CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] SaPolicy The pointer to get SA Policy Proto= col instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CreateSaDxeConfigBlocks( + IN OUT SA_POLICY_PROTOCOL **SaPolicy +); + +/** + SaInstallPolicyProtocol installs SA Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SaPolicy The pointer to SA Policy Protocol = instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +SaInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN SA_POLICY_PROTOCOL *SaPolicy + ) +; + +#endif // _DXE_SA_POLICY_LIB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library= /PeiSaPolicyLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/= Library/PeiSaPolicyLib.h new file mode 100644 index 0000000000..c29d67a305 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/PeiSaP= olicyLib.h @@ -0,0 +1,87 @@ +/** @file + Prototype of the PeiSaPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SA_POLICY_LIB_H_ +#define _PEI_SA_POLICY_LIB_H_ + +#include +#include + +/** + This function prints the PEI phase PreMem policy. + + @param[in] SiPolicyPreMemPpi The RC PreMem Policy PPI insta= nce +**/ +VOID +EFIAPI +SaPrintPolicyPpiPreMem ( + IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi + ); + +/** + This function prints the PEI phase policy. + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +SaPrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ); + +/** + Get SA config block table total size. + + @retval Size of SA config block table +**/ +UINT16 +EFIAPI +SaGetConfigBlockTotalSize ( + VOID + ); + +/** + Get SA config block table total size. + + @retval Size of SA config block table +**/ +UINT16 +EFIAPI +SaGetConfigBlockTotalSizePreMem ( + VOID + ); + +/** + SaAddConfigBlocksPreMem add all SA config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add SA config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +SaAddConfigBlocksPreMem ( + IN VOID *ConfigBlockTableAddress + ); + +/** + SaAddConfigBlocks add all SA config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add SA config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +SaAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ); + +#endif // _PEI_SA_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library= /SaPlatformLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/L= ibrary/SaPlatformLib.h new file mode 100644 index 0000000000..a1289abe81 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Library/SaPlat= formLib.h @@ -0,0 +1,88 @@ +/** @file + Header file for SaPlatformLib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_PLATFORM_LIB_H_ +#define _SA_PLATFORM_LIB_H_ + +#include +#include + +/** + Determine if PCH Link is DMI/OPI + + @param[in] CpuModel CPU model + + @retval TRUE DMI + @retval FALSE OPI +**/ +BOOLEAN +IsPchLinkDmi ( + IN CPU_FAMILY CpuModel + ); + +/** + Returns the number of DMI lanes for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxDmiLanes ( + ); + + +/** + Returns the number of DMI bundles for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxDmiBundles ( + ); + + +/** + Returns the function numbers for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegFuncs ( + ); + + +/** + Returns the number of DMI lanes for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegLanes ( + ); + + +/** + Returns the number of DMI bundles for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegBundles ( + ); + +/** + Checks if PEG port is present + + @retval TRUE PEG is presented + @retval FALSE PEG is not presented +**/ +BOOLEAN +IsPegPresent ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfo= Hob.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h new file mode 100644 index 0000000000..da285bbcba --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/MemInfoHob.h @@ -0,0 +1,259 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 1 +#define MAX_CH 2 +#define MAX_DIMM 2 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the c= ontroller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is di= sabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is ena= bled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be= detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of p= resence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pa= ir and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank p= air. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef bmCold +#define bmCold 0 // Cold boot +#endif +#ifndef bmWarm +#define bmWarm 1 // Warm boot +#endif +#ifndef bmS3 +#define bmS3 2 // S3 resume +#endif +#ifndef bmFast +#define bmFast 3 // Fast boot +#endif + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif + +#define MAX_PROFILE_NUM 4 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's comma= nd rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS l= atency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minim= um CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minim= um four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minim= um active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minim= um RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minim= um Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minim= um per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minim= um row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minim= um internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minim= um write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum= CAS-to-CAS delay for same bank group. +} MRC_CH_TIMING; + +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the = same bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when sw= itching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when sw= itching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when sw= itching between DIMMs. +} MRC_TA_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the= definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DD= R3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20= bytes + UINT8 RankInDimm; ///< The number of ranks in th= is DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType i= nformation needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType infor= mation needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusW= idth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing in= formation needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed= of the device, in MHz. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this ch= annel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs tha= t exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output char= acteristics. + MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Aroun= d Timings + MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Aroun= d Timings + MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Aroun= d Timings + MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Aroun= d Timings +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this c= ontroller should be used. + UINT16 DeviceId; ///< The PCI device id of thi= s memory controller. + UINT8 RevisionId; ///< The PCI revision id of t= his memory controller. + UINT8 ChannelCount; ///< Number of valid channels= that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channe= l level definitions. + MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to = CHANNEL_INFO. Read-to-Read Turn Around Timings + MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to = CHANNEL_INFO. Read-to-Write Turn Around Timings + MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to = CHANNEL_INFO. Write-to-Read Turn Around Timings + MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to = CHANNEL_INFO. Write-to-Write Turn Around Timings +} CONTROLLER_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of t= his memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or = LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed= of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock = speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK= value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable= DIMMs are detected, this will indicate which XMP Profiles are common among= all DIMMs. + UINT8 Ratio; + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + CONTROLLER_INFO Controller[MAX_NODE]; +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddre= ss fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT32 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + UINT32 GdxcIotBase; + UINT32 GdxcIotSize; + UINT32 GdxcMotBase; + UINT32 GdxcMotSize; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Library/GraphicsInitLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent= /Include/Private/Library/GraphicsInitLib.h new file mode 100644 index 0000000000..ff7cfa838f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Librar= y/GraphicsInitLib.h @@ -0,0 +1,15 @@ +/** @file + Graphics header file + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_INIT_H_ +#define _GRAPHICS_INIT_H_ + +#include +#include + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Library/LegacyRegion.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/In= clude/Private/Library/LegacyRegion.h new file mode 100644 index 0000000000..497c860824 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Librar= y/LegacyRegion.h @@ -0,0 +1,33 @@ +/** @file + This code supports a private implementation of the Legacy Region protoco= l. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _LEGACY_REGION_H_ +#define _LEGACY_REGION_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Install Driver to produce Legacy Region protocol. + + @param[in] ImageHandle Handle for the image of this driver + + @retval EFI_SUCCESS - Legacy Region protocol installed + @retval Other - No protocol installed, unload driver. +**/ +EFI_STATUS +LegacyRegionInstall ( + IN EFI_HANDLE ImageHandle + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Library/PeiCpuTraceHubLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAge= nt/Include/Private/Library/PeiCpuTraceHubLib.h new file mode 100644 index 0000000000..8bf46528ab --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Librar= y/PeiCpuTraceHubLib.h @@ -0,0 +1,23 @@ +/** @file + Header file for North TraceHub Lib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _NORTH_TRACEHUB_LIB_H_ +#define _NORTH_TRACEHUB_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Library/SaPcieLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/Private/Library/SaPcieLib.h new file mode 100644 index 0000000000..19dd634a35 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Librar= y/SaPcieLib.h @@ -0,0 +1,70 @@ +/** @file + Defines and prototypes for the System Agent PCIe library module + This library is expected to share between DXE and SMM drivers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_PCIE_LIB_H_ +#define _SA_PCIE_LIB_H_ + +#include +#include + +#define MAX_SUPPORTED_ROOT_BRIDGE_NUMBER 3 +#define MAX_SUPPORTED_DEVICE_NUMBER 192 + +/** + Enumerate all end point devices connected to root bridge ports and recor= d their MMIO base address + + @exception EFI_UNSUPPORTED PCIe capability structure not found + @retval EFI_SUCCESS All done successfully +**/ +EFI_STATUS +EnumerateAllPcieDevices ( + VOID + ); + +/** + Sets Common Clock, TCx-VC0 mapping, and Max Payload for PCIe +**/ +VOID +SaPcieConfigBeforeOpRom ( + VOID + ); + +/** + This function does all SA ASPM initialization +**/ +VOID +SaAspm ( + VOID + ); + +/** + This function checks PEG end point device for extended tag capability an= d enables them if they are. +**/ +VOID +EnableExtendedTag ( + VOID + ); + +/** + This function handles SA S3 resume +**/ +VOID +SaS3Resume ( + VOID + ); + +/** + Wrapper function for all SA S3 resume tasks which can be a callback func= tion. +**/ +VOID +SaS3ResumeCallback ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Protocol/SaIotrapSmi.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/In= clude/Private/Protocol/SaIotrapSmi.h new file mode 100644 index 0000000000..2c765b09b8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protoc= ol/SaIotrapSmi.h @@ -0,0 +1,36 @@ +/** @file + This file defines the SA Iotrap SMI Protocol to provide the + I/O address for registered Iotrap SMI. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_ +#define _SA_IOTRAP_SMI_PROTOCOL_H_ + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gSaIotrapSmiProtocolGuid; + +#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1 + +// +// SA IO Trap SMI Protocol definition (Private protocol for RC internal us= e only) +// +typedef struct { +/* + Protocol revision number + Any backwards compatible changes to this protocol will result in an updat= e in the revision number + Major changes will require publication of a new protocol + + Revision 1: + - First version +*/ + UINT8 Revision; + UINT16 SaIotrapSmiAddress; +} SA_IOTRAP_SMI_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /Protocol/SaNvsArea.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Incl= ude/Private/Protocol/SaNvsArea.h new file mode 100644 index 0000000000..1bae2d95e5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/Protoc= ol/SaNvsArea.h @@ -0,0 +1,31 @@ +/** @file + Definition of the System Agent global NVS area protocol. + This protocol publishes the address and format of a global ACPI NVS buff= er + used as a communications buffer between SMM/DXE/PEI code and ASL code. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SYSTEM_AGENT_NVS_AREA_H_ +#define _SYSTEM_AGENT_NVS_AREA_H_ + +// +// SA NVS Area definition +// +#include + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gSaNvsAreaProtocolGuid; + +/// +/// System Agent Global NVS Area Protocol +/// +typedef struct { + SYSTEM_AGENT_NVS_AREA *Area; ///< System Agent Global NVS Area St= ructure +} SYSTEM_AGENT_NVS_AREA_PROTOCOL; + +#endif // _SYSTEM_AGENT_NVS_AREA_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /SaConfigHob.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Pri= vate/SaConfigHob.h new file mode 100644 index 0000000000..f1b72488ca --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaConf= igHob.h @@ -0,0 +1,89 @@ +/** @file + The GUID definition for SaConfigHob + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_CONFIG_HOB_H_ +#define _SA_CONFIG_HOB_H_ + +#include +#include + +extern EFI_GUID gSaConfigHobGuid; + +#pragma pack (push,1) +/// +#define DPR_DIRECTORY_MAX 2 ///< DPR Maximum Size +/// DPR directory entry definition +/// +typedef struct { + UINT8 Type; ///< DPR Directory Type + UINT8 Size; ///< DPR Size in MB + UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear) + UINT16 Reserved; ///< Must be 0 +} DPR_DIRECTORY_ENTRY; + +/// +/// The data elements should be initialized by a Platform Module. +/// The data structure is for VT-d driver initialization +/// +typedef struct { + BOOLEAN VtdDisable; ///< 1 =3D Avoi= ds programming Vtd bars, Vtd overrides and DMAR table + UINT32 BaseAddress[SA_VTD_ENGINE_NUMBER]; ///< This field= is used to describe the base addresses for VT-d function + BOOLEAN X2ApicOptOut; ///< This field= is used to enable the X2APIC_OPT_OUT bit in the DMAR table. 1=3DEnable/= Set and 0=3DDisable/Clear + BOOLEAN InterruptRemappingSupport; ///< This field= is used to indicate Interrupt Remapping supported or not +} SA_VTD_CONFIGURATION_HOB; + +/// +/// SA GPIO Data Structure +/// +typedef struct { + UINT8 ExpanderNo; ///< =3DExpander No For I2C based GPIO + UINT32 GpioNo; ///< GPIO pad + BOOLEAN Active; ///< 0=3DActive Low; 1=3DActive High +} SA_GPIO; + +/// +/// SA PCIE RTD3 GPIO Data Structure +/// +typedef struct { + UINT8 GpioSupport; ///< 0=3DNot Supported; 1=3DPCH bas= ed; 2=3DI2C Based + SA_GPIO HoldRst; ///< Offset 8 This field contain PC= Ie HLD RESET GPIO value and level information + SA_GPIO PwrEnable; ///< This field contain PCIe PWR En= able GPIO value and level information + UINT32 WakeGpioNo; ///< This field contain PCIe RTD3 D= evice Wake GPIO number +} PCIE_RTD3_GPIO; + +/// +/// SG Info HOB +/// +typedef struct { + SG_MODE SgMode; + UINT8 RootPortIndex; + PCIE_RTD3_GPIO Rtd3Pcie0Gpio; + PCIE_RTD3_GPIO Rtd3Pcie1Gpio; + PCIE_RTD3_GPIO Rtd3Pcie2Gpio; + UINT16 DelayAfterPwrEn; + UINT16 DelayAfterHoldReset; +} SA_RTD3; + +/// +/// System Agent Config Hob +/// +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< = GUID Hob type structure for gSaConfigHobGuid + DPR_DIRECTORY_ENTRY DprDirectory[DPR_DIRECTORY_MAX]; ///< = DPR directory entry definition + BOOLEAN InitPcieAspmAfterOprom; ///< = 1=3Dinitialize PCIe ASPM after Oprom; 0=3Dbefore (This will be set basing o= n policy) + SA_RTD3 SaRtd3; ///< = SG Info HOB + UINT8 ApertureSize; ///< = Aperture size value + UINT8 IpuAcpiMode; ///< = IPU ACPI mode: 0=3DDisabled, 1=3DIGFX Child device, 2=3DACPI device + SA_VTD_CONFIGURATION_HOB VtdData; ///< = VT-d Data HOB + BOOLEAN CridEnable; ///< = This field inidicates if CRID is enabled or disabled (to support Intel(R) S= IPP) + BOOLEAN SkipPamLock; ///< = 0=3DAll PAM registers will be locked in System Agent code, 1=3DDo not lock = PAM registers in System Agent code. + UINT8 PowerDownUnusedBundles[SA_PEG_MAX_FUN]; ///< = PCIe power down unused bundles support + UINT8 PegMaxPayload[SA_PEG_MAX_FUN]; ///< = PEG Max Pay Load Size (0xFF: Auto, 0:128B, 1:256B) +} SA_CONFIG_HOB; +#pragma pack (pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private= /SaNvsAreaDef.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Pr= ivate/SaNvsAreaDef.h new file mode 100644 index 0000000000..095942d483 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Private/SaNvsA= reaDef.h @@ -0,0 +1,151 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // + // Define SA NVS Area operatino region. + // + +#ifndef _SA_NVS_AREA_DEF_H_ +#define _SA_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + UINT32 IgdOpRegionAddress; ///< Offset 0 IG= D OpRegion base address + UINT8 GfxTurboIMON; ///< Offset 4 IM= ON Current Value + UINT8 IgdState; ///< Offset 5 IG= D State (Primary Display =3D 1) + UINT8 IgdBootType; ///< Offset 6 IG= D Boot Display Device + UINT8 IgdPanelType; ///< Offset 7 IG= D Panel Type CMOS option + UINT8 IgdPanelScaling; ///< Offset 8 IG= D Panel Scaling + UINT8 IgdBiaConfig; ///< Offset 9 IG= D BIA Configuration + UINT8 IgdSscConfig; ///< Offset 10 IG= D SSC Configuration + UINT8 IgdDvmtMemSize; ///< Offset 11 IG= D DVMT Memory Size + UINT8 IgdFunc1Enable; ///< Offset 12 IG= D Function 1 Enable + UINT8 IgdHpllVco; ///< Offset 13 HP= LL VCO + UINT8 IgdSciSmiMode; ///< Offset 14 GM= CH SMI/SCI mode (0=3DSCI) + UINT8 IgdPAVP; ///< Offset 15 IG= D PAVP data + UINT8 CurrentDeviceList; ///< Offset 16 Cu= rrent Attached Device List + UINT16 CurrentDisplayState; ///< Offset 17 Cu= rrent Display State + UINT16 NextDisplayState; ///< Offset 19 Ne= xt Display State + UINT8 NumberOfValidDeviceId; ///< Offset 21 Nu= mber of Valid Device IDs + UINT32 DeviceId1; ///< Offset 22 De= vice ID 1 + UINT32 DeviceId2; ///< Offset 26 De= vice ID 2 + UINT32 DeviceId3; ///< Offset 30 De= vice ID 3 + UINT32 DeviceId4; ///< Offset 34 De= vice ID 4 + UINT32 DeviceId5; ///< Offset 38 De= vice ID 5 + UINT32 DeviceId6; ///< Offset 42 De= vice ID 6 + UINT32 DeviceId7; ///< Offset 46 De= vice ID 7 + UINT32 DeviceId8; ///< Offset 50 De= vice ID 8 + UINT32 DeviceId9; ///< Offset 54 De= vice ID 9 + UINT32 DeviceId10; ///< Offset 58 De= vice ID 10 + UINT32 DeviceId11; ///< Offset 62 De= vice ID 11 + UINT32 DeviceId12; ///< Offset 66 De= vice ID 12 + UINT32 DeviceId13; ///< Offset 70 De= vice ID 13 + UINT32 DeviceId14; ///< Offset 74 De= vice ID 14 + UINT32 DeviceId15; ///< Offset 78 De= vice ID 15 + UINT32 DeviceIdX; ///< Offset 82 De= vice ID for eDP device + UINT32 NextStateDid1; ///< Offset 86 Ne= xt state DID1 for _DGS + UINT32 NextStateDid2; ///< Offset 90 Ne= xt state DID2 for _DGS + UINT32 NextStateDid3; ///< Offset 94 Ne= xt state DID3 for _DGS + UINT32 NextStateDid4; ///< Offset 98 Ne= xt state DID4 for _DGS + UINT32 NextStateDid5; ///< Offset 102 Ne= xt state DID5 for _DGS + UINT32 NextStateDid6; ///< Offset 106 Ne= xt state DID6 for _DGS + UINT32 NextStateDid7; ///< Offset 110 Ne= xt state DID7 for _DGS + UINT32 NextStateDid8; ///< Offset 114 Ne= xt state DID8 for _DGS + UINT32 NextStateDidEdp; ///< Offset 118 Ne= xt state DID for eDP + UINT8 LidState; ///< Offset 122 Li= d State (Lid Open =3D 1) + UINT32 AKsv0; ///< Offset 123 Fi= rst four bytes of AKSV (manufacturing mode) + UINT8 AKsv1; ///< Offset 127 Fi= fth byte of AKSV (manufacturing mode) + UINT8 BrightnessPercentage; ///< Offset 128 Br= ightness Level Percentage + UINT8 AlsEnable; ///< Offset 129 Am= bient Light Sensor Enable + UINT8 AlsAdjustmentFactor; ///< Offset 130 Am= bient Light Adjusment Factor + UINT8 LuxLowValue; ///< Offset 131 LU= X Low Value + UINT8 LuxHighValue; ///< Offset 132 LU= X High Value + UINT8 ActiveLFP; ///< Offset 133 Ac= tive LFP + UINT8 IpuAcpiMode; ///< Offset 134 IP= U ACPI device type (0=3DDisabled, 1=3DAVStream virtual device as child of G= FX) + UINT8 EdpValid; ///< Offset 135 Ch= eck for eDP display device + UINT8 SgMode; ///< Offset 136 SG= Mode (0=3DDisabled, 1=3DSG Muxed, 2=3DSG Muxless, 3=3DDGPU Only) + UINT8 SgFeatureList; ///< Offset 137 SG= Feature List + UINT8 Pcie0GpioSupport; ///< Offset 138 PC= Ie0 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) + UINT8 Pcie0HoldRstExpanderNo; ///< Offset 139 PC= Ie0 HLD RST IO Expander Number + UINT32 Pcie0HoldRstGpioNo; ///< Offset 140 PC= Ie0 HLD RST GPIO Number + UINT8 Pcie0HoldRstActiveInfo; ///< Offset 144 PC= Ie0 HLD RST GPIO Active Information + UINT8 Pcie0PwrEnExpanderNo; ///< Offset 145 PC= Ie0 PWR Enable IO Expander Number + UINT32 Pcie0PwrEnGpioNo; ///< Offset 146 PC= Ie0 PWR Enable GPIO Number + UINT8 Pcie0PwrEnActiveInfo; ///< Offset 150 PC= Ie0 PWR Enable GPIO Active Information + UINT8 Pcie1GpioSupport; ///< Offset 151 PC= Ie1 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) + UINT8 Pcie1HoldRstExpanderNo; ///< Offset 152 PC= Ie1 HLD RST IO Expander Number + UINT32 Pcie1HoldRstGpioNo; ///< Offset 153 PC= Ie1 HLD RST GPIO Number + UINT8 Pcie1HoldRstActiveInfo; ///< Offset 157 PC= Ie1 HLD RST GPIO Active Information + UINT8 Pcie1PwrEnExpanderNo; ///< Offset 158 PC= Ie1 PWR Enable IO Expander Number + UINT32 Pcie1PwrEnGpioNo; ///< Offset 159 PC= Ie1 PWR Enable GPIO Number + UINT8 Pcie1PwrEnActiveInfo; ///< Offset 163 PC= Ie1 PWR Enable GPIO Active Information + UINT8 Pcie2GpioSupport; ///< Offset 164 PC= Ie2 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) + UINT8 Pcie2HoldRstExpanderNo; ///< Offset 165 PC= Ie2 HLD RST IO Expander Number + UINT32 Pcie2HoldRstGpioNo; ///< Offset 166 PC= Ie2 HLD RST GPIO Number + UINT8 Pcie2HoldRstActiveInfo; ///< Offset 170 PC= Ie2 HLD RST GPIO Active Information + UINT8 Pcie2PwrEnExpanderNo; ///< Offset 171 PC= Ie2 PWR Enable IO Expander Number + UINT32 Pcie2PwrEnGpioNo; ///< Offset 172 PC= Ie2 PWR Enable GPIO Number + UINT8 Pcie2PwrEnActiveInfo; ///< Offset 176 PC= Ie2 PWR Enable GPIO Active Information + UINT16 DelayAfterPwrEn; ///< Offset 177 De= lay after power enable for PCIe + UINT16 DelayAfterHoldReset; ///< Offset 179 De= lay after Hold Reset for PCIe + UINT8 Pcie0EpCapOffset; ///< Offset 181 PC= Ie0 Endpoint Capability Structure Offset + UINT32 XPcieCfgBaseAddress; ///< Offset 182 An= y Device's PCIe Config Space Base Address + UINT16 GpioBaseAddress; ///< Offset 186 GP= IO Base Address + UINT32 NvIgOpRegionAddress; ///< Offset 188 NV= IG opregion address + UINT32 NvHmOpRegionAddress; ///< Offset 192 NV= HM opregion address + UINT32 ApXmOpRegionAddress; ///< Offset 196 AM= DA opregion address + UINT8 Peg0LtrEnable; ///< Offset 200 La= tency Tolerance Reporting Enable + UINT8 Peg0ObffEnable; ///< Offset 201 Op= timized Buffer Flush and Fill + UINT8 Peg1LtrEnable; ///< Offset 202 La= tency Tolerance Reporting Enable + UINT8 Peg1ObffEnable; ///< Offset 203 Op= timized Buffer Flush and Fill + UINT8 Peg2LtrEnable; ///< Offset 204 La= tency Tolerance Reporting Enable + UINT8 Peg2ObffEnable; ///< Offset 205 Op= timized Buffer Flush and Fill + UINT8 Peg3LtrEnable; ///< Offset 206 La= tency Tolerance Reporting Enable + UINT8 Peg3ObffEnable; ///< Offset 207 Op= timized Buffer Flush and Fill + UINT16 PegLtrMaxSnoopLatency; ///< Offset 208 SA= Peg Latency Tolerance Reporting Max Snoop Latency + UINT16 PegLtrMaxNoSnoopLatency; ///< Offset 210 SA= Peg Latency Tolerance Reporting Max No Snoop Latency + UINT8 Peg0PowerDownUnusedBundles; ///< Offset 212 Pe= g0 Unused Bundle Control + UINT8 Peg1PowerDownUnusedBundles; ///< Offset 213 Pe= g1 Unused Bundle Control + UINT8 Peg2PowerDownUnusedBundles; ///< Offset 214 Pe= g2 Unused Bundle Control + UINT8 Peg3PowerDownUnusedBundles; ///< Offset 215 Pe= g3 Unused Bundle Control + UINT8 PackageCstateLimit; ///< Offset 216 Th= e lowest C-state for the package + UINT8 PwrDnBundlesGlobalEnable; ///< Offset 217 Pe= gx Unused Bundle Control Global Enable (0=3DDisabled, 1=3DEnabled) + UINT64 Mmio64Base; ///< Offset 218 Ba= se of above 4GB MMIO resource + UINT64 Mmio64Length; ///< Offset 226 Le= ngth of above 4GB MMIO resource + UINT32 CpuIdInfo; ///< Offset 234 CP= U ID info to get Family Id or Stepping + UINT8 Pcie1EpCapOffset; ///< Offset 238 PC= Ie1 Endpoint Capability Structure Offset + UINT8 Pcie2EpCapOffset; ///< Offset 239 PC= Ie2 Endpoint Capability Structure Offset + UINT8 Pcie0SecBusNum; ///< Offset 240 PC= Ie0 Secondary Bus Number (PCIe0 Endpoint Bus Number) + UINT8 Pcie1SecBusNum; ///< Offset 241 PC= Ie1 Secondary Bus Number (PCIe0 Endpoint Bus Number) + UINT8 Pcie2SecBusNum; ///< Offset 242 PC= Ie2 Secondary Bus Number (PCIe0 Endpoint Bus Number) + UINT32 Mmio32Base; ///< Offset 243 Ba= se of below 4GB MMIO resource + UINT32 Mmio32Length; ///< Offset 247 Le= ngth of below 4GB MMIO resource + UINT32 Pcie0WakeGpioNo; ///< Offset 251 PC= Ie0 RTD3 Device Wake GPIO Number + UINT32 Pcie1WakeGpioNo; ///< Offset 255 PC= Ie1 RTD3 Device Wake GPIO Number + UINT32 Pcie2WakeGpioNo; ///< Offset 259 PC= Ie2 RTD3 Device Wake GPIO Number + UINT8 VtdDisable; ///< Offset 263 VT= -d Enable/Disable + UINT32 VtdBaseAddress1; ///< Offset 264 VT= -d Base Address 1 + UINT32 VtdBaseAddress2; ///< Offset 268 VT= -d Base Address 2 + UINT32 VtdBaseAddress3; ///< Offset 272 VT= -d Base Address 3 + UINT16 VtdEngine1Vid; ///< Offset 276 VT= -d Engine#1 Vendor ID + UINT16 VtdEngine2Vid; ///< Offset 278 VT= -d Engine#2 Vendor ID + UINT8 Pcie3SecBusNum; ///< Offset 280 PC= Ie3 Secondary Bus Number (PCIe3 Endpoint Bus Number) + UINT8 Pcie3GpioSupport; ///< Offset 281 PC= Ie3 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based) + UINT8 Pcie3HoldRstExpanderNo; ///< Offset 282 PC= Ie3 HLD RST IO Expander Number + UINT32 Pcie3HoldRstGpioNo; ///< Offset 283 PC= Ie3 HLD RST GPIO Number + UINT8 Pcie3HoldRstActiveInfo; ///< Offset 287 PC= Ie3 HLD RST GPIO Active Information + UINT8 Pcie3PwrEnExpanderNo; ///< Offset 288 PC= Ie3 PWR Enable IO Expander Number + UINT32 Pcie3PwrEnGpioNo; ///< Offset 289 PC= Ie3 PWR Enable GPIO Number + UINT8 Pcie3PwrEnActiveInfo; ///< Offset 293 PC= Ie3 PWR Enable GPIO Active Information + UINT32 Pcie3WakeGpioNo; ///< Offset 294 PC= Ie3 RTD3 Device Wake GPIO Number + UINT8 Pcie3EpCapOffset; ///< Offset 298 PC= Ie3 Endpoint Capability Structure Offset + UINT8 RootPortIndex; ///< Offset 299 Ro= otPort Number + UINT32 RootPortAddress; ///< Offset 300 Ro= otPortAddress + UINT8 Reserved0[196]; ///< Offset 304:499 +} SYSTEM_AGENT_NVS_AREA; + +#pragma pack(pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/GopComponentName2.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Incl= ude/Protocol/GopComponentName2.h new file mode 100644 index 0000000000..a9db25404f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopCo= mponentName2.h @@ -0,0 +1,63 @@ +/** @file + Protocol to retrieve the GOP driver version + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GOP_COMPONENT_NAME2_H_ +#define _GOP_COMPONENT_NAME2_H_ + + +typedef struct _GOP_COMPONENT_NAME2_PROTOCOL GOP_COMPONENT_NAME2_PROTOCOL; + +/// +/// GOP Component protocol for retrieving driver name +/// +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN CHAR8 *Language, + OUT CHAR16 **DriverName + ); + +/// +/// GOP Component protocol for retrieving controller name +/// +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN EFI_HANDLE ControllerHandle, + IN EFI_HANDLE ChildHandle OPTIONAL, + IN CHAR8 *Language, + OUT CHAR16 **ControllerName + ); + +/// +/// GOP Component protocol for retrieving driver version +/// +typedef +EFI_STATUS +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) ( + IN GOP_COMPONENT_NAME2_PROTOCOL * This, + IN CHAR8 *Language, + OUT CHAR16 **DriverVersion + ); + +/** + GOP Component protocol\n + This protocol will be installed by GOP driver and can be used to retriev= e GOP information. +**/ +struct _GOP_COMPONENT_NAME2_PROTOCOL { + GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; ///< Pr= otocol function to get driver name + GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion; ///< Pr= otocol function to get driver version + GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName; ///< Pr= otocol function to get controller name + CHAR8 *SupportedLanguages; ///< Nu= mber of Supported languages. +}; + +extern EFI_GUID gGopComponentName2ProtocolGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/GopPolicy.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Prot= ocol/GopPolicy.h new file mode 100644 index 0000000000..866f60b9c2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/GopPo= licy.h @@ -0,0 +1,73 @@ +/** @file + Interface definition for GopPolicy Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GOP_POLICY_PROTOCOL_H_ +#define _GOP_POLICY_PROTOCOL_H_ + + +#define GOP_POLICY_PROTOCOL_REVISION_01 0x01 +#define GOP_POLICY_PROTOCOL_REVISION_03 0x03 + +typedef enum { + LidClosed, + LidOpen, + LidStatusMax +} LID_STATUS; + +typedef enum { + Docked, + UnDocked, + DockStatusMax +} DOCK_STATUS; + +/// +/// Function to retrieve LID status +/// +typedef +EFI_STATUS +(EFIAPI *GET_PLATFORM_LID_STATUS) ( + OUT LID_STATUS * CurrentLidStatus + ); + +/// +/// Function to retrieve Dock status +/// +typedef +EFI_STATUS +(EFIAPI *GET_PLATFORM_DOCK_STATUS) ( + OUT DOCK_STATUS CurrentDockStatus +); + +/// +/// Function to retrieve VBT table address and size +/// +typedef +EFI_STATUS +(EFIAPI *GET_VBT_DATA) ( + OUT EFI_PHYSICAL_ADDRESS * VbtAddress, + OUT UINT32 *VbtSize + ); + +/** + System Agent Graphics Output Protocol (GOP) - Policy Protocol\n + Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs= for EFI boot\n + When GOP Driver is used this protocol can be consumed by GOP driver or p= latform code for GOP relevant initialization\n + All functions in this protocol should be initialized by platform code ba= sing on platform implementation\n +**/ +typedef struct { + UINT32 Revision; ///< Protocol revision + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Protocol function = to get Lid Status. Platform code should provide this function basing on des= ign. + GET_VBT_DATA GetVbtData; ///< Protocol function = to get Vbt Data address and size. Platform code should provide this functio= n basing on design. + GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus; ///< Function pointer = for get platform dock status. + EFI_GUID GopOverrideGuid; ///< A GUID provided b= y BIOS in case GOP is to be overridden. +} GOP_POLICY_PROTOCOL; + +extern EFI_GUID gGopPolicyProtocolGuid; +extern EFI_GUID gIntelGraphicsVbtGuid; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/IgdOpRegion.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Pr= otocol/IgdOpRegion.h new file mode 100644 index 0000000000..ef2edfe122 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/IgdOp= Region.h @@ -0,0 +1,24 @@ +/** @file + This file is part of the IGD OpRegion Implementation. The IGD OpRegion = is + an interface between system BIOS, ASL code, and Graphics drivers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IGD_OPREGION_PROTOCOL_H_ +#define _IGD_OPREGION_PROTOCOL_H_ + +#include + +extern EFI_GUID gIgdOpRegionProtocolGuid; + +/// +/// IGD OpRegion Protocol +/// +typedef struct { + IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure +} IGD_OPREGION_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/MemInfo.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoc= ol/MemInfo.h new file mode 100644 index 0000000000..031e55b9b4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/MemIn= fo.h @@ -0,0 +1,132 @@ +/** @file + This protocol provides the memory information data, such as + total physical memory size, memory frequency, memory size + of each dimm and rank. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MEM_INFO_PROTOCOL_H_ +#define _MEM_INFO_PROTOCOL_H_ + + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gMemInfoProtocolGuid; + +// +// Protocol definitions +// +#define NODE_NUM 1 +#define CH_NUM 2 +#define DIMM_NUM 2 +#define RANK_NUM 2 +#define SLOT_NUM (CH_NUM * DIMM_NUM) +#define PROFILE_NUM 4 // number of memory profiles supported +#define XMP_PROFILE_NUM 2 // number of XMP profiles supported + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR4 +#define MRC_DDR_TYPE_DDR4 0 +#endif +#ifndef MRC_DDR_TYPE_DDR3 +#define MRC_DDR_TYPE_DDR3 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR3 +#define MRC_DDR_TYPE_LPDDR3 2 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 3 +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be= detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of p= resence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pa= ir and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank p= air. +#endif + +#pragma pack(1) +/// +/// Memory timing Structure +/// +typedef struct { + UINT32 tCK; ///< Offset 0 Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Offset 4 Number of tCK cycles for the channel DIMM'= s command rate mode. + UINT16 tCL; ///< Offset 6 Number of tCK cycles for the channel DIMM'= s CAS latency. + UINT16 tCWL; ///< Offset 8 Number of tCK cycles for the channel DIMM'= s minimum CAS write latency time. + UINT16 tFAW; ///< Offset 10 Number of tCK cycles for the channel DIMM= 's minimum four activate window delay time. + UINT16 tRAS; ///< Offset 12 Number of tCK cycles for the channel DIMM= 's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Offset 14 Number of tCK cycles for the channel DIMM= 's minimum RAS# to CAS# delay time and Row Precharge delay time + UINT16 tREFI; ///< Offset 16 Number of tCK cycles for the channel DIMM= 's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Offset 18 Number of tCK cycles for the channel DIMM= 's minimum refresh recovery delay time. + UINT16 tRPab; ///< Offset 20 Number of tCK cycles for the channel DIMM= 's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Offset 22 Number of tCK cycles for the channel DIMM= 's minimum row active to row active delay time. + UINT16 tRTP; ///< Offset 24 Number of tCK cycles for the channel DIMM= 's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Offset 26 Number of tCK cycles for the channel DIMM= 's minimum write recovery time. + UINT16 tWTR; ///< Offset 28 Number of tCK cycles for the channel DIMM= 's minimum internal write to read command delay time. + UINT16 tRRD_L; ///< Offset 30 Number of tCK cycles for the channel DIMM= 's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Offset 32 Number of tCK cycles for the channel DIMM= 's minimum row active to row active delay time for different bank groups. + UINT16 tWTR_L; ///< Offset 34 Number of tCK cycles for the channel DIMM= 's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Offset 36 Number of tCK cycles for the channel DIMM= 's minimum internal write to read command delay time for different bank gro= ups. + UINT8 Rsvd[2]; ///< Offset 38 +} MEMORY_TIMING; + +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the sa= me bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when swit= ching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when swit= ching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when swit= ching between DIMMs +} TURNAROUND_TIMING; + +// @todo use the MemInfoHob data instead of duplicate structure. +/// +/// Memory information Data Structure +/// +typedef struct { + MEMORY_TIMING Timing[PROFILE_NUM]; ///< Offset 0 Timmi= ng information for the DIMM + UINT32 memSize; ///< Offset 128 Tot= al physical memory size + UINT16 ddrFreq; ///< Offset 132 DDR= Current Frequency + UINT16 ddrFreqMax; ///< Offset 134 DDR= Maximum Frequency + UINT16 dimmSize[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 136 Siz= e of each DIMM + UINT16 VddVoltage[PROFILE_NUM]; ///< Offset 144 The= voltage setting for the DIMM + UINT8 DimmStatus[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 152 The= enumeration value from MrcDimmSts + UINT8 RankInDimm[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 156 No.= of ranks in a dimm + UINT8 *DimmsSpdData[NODE_NUM * CH_NUM * DIMM_NUM]; ///< Offset 160 SPD= data of each DIMM + UINT8 RefClk; ///< Offset 192 Ref= erence Clock + UINT8 Ratio; ///< Offset 193 Clo= ck Multiplier + BOOLEAN EccSupport; ///< Offset 194 ECC= supported or not + UINT8 Profile; ///< Offset 195 Cur= rently running memory profile + UINT8 XmpProfileEnable; ///< Offset 196: 0 = =3D no XMP DIMMs in system + UINT8 DdrType; ///< Offset 197: Cu= rrent DDR type, see DDR_TYPE_xxx defines above + UINT8 Reserved[2]; ///< Offset 198 Res= erved bytes for future use + UINT32 DefaultXmptCK[XMP_PROFILE_NUM]; ///< Offset 200 The= Default XMP tCK values read from SPD. + TURNAROUND_TIMING tRd2Rd[CH_NUM]; ///< Read-to-Read = Turn Around Timings + TURNAROUND_TIMING tRd2Wr[CH_NUM]; ///< Read-to-Write = Turn Around Timings + TURNAROUND_TIMING tWr2Rd[CH_NUM]; ///< Write-to-Read = Turn Around Timings + TURNAROUND_TIMING tWr2Wr[CH_NUM]; ///< Write-to-Write= Turn Around Timings +} MEMORY_INFO_DATA; +#pragma pack() + +/// +/// Memory information Protocol definition +/// +typedef struct { + MEMORY_INFO_DATA MemInfoData; ///< Memory Information Data Structure +} MEM_INFO_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protoco= l/SaPolicy.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Proto= col/SaPolicy.h new file mode 100644 index 0000000000..7b68f3072b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Protocol/SaPol= icy.h @@ -0,0 +1,66 @@ +/** @file + Interface definition details between System Agent and platform drivers d= uring DXE phase. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_POLICY_H_ +#define _SA_POLICY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gSaPolicyProtocolGuid; +extern EFI_GUID gGraphicsDxeConfigGuid; +extern EFI_GUID gMiscDxeConfigGuid; +extern EFI_GUID gPcieDxeConfigGuid; +extern EFI_GUID gMemoryDxeConfigGuid; +extern EFI_GUID gVbiosDxeConfigGuid; + +/** + Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external + modules maybe have consumed this macro in their source code. Directly + update the SA_POLICY_PROTOCOL_REVISION version number may cause those + external modules to auto mark themselves wrong version info. + Always create new version macro for new Policy protocol interface. +**/ +#define SA_POLICY_PROTOCOL_REVISION 1 + +#define SA_PCIE_DEV_END_OF_TABLE 0xFFFF + +#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Snoop Latency +#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Non-Snoop Latency + + +/** + SA DXE Policy + + The SA_POLICY_PROTOCOL producer drvier is recommended to + set all the SA_POLICY_PROTOCOL size buffer zero before init any member pa= rameter, + this clear step can make sure no random value for those unknow new versio= n parameters. + + Make sure to update the Revision if any change to the protocol, including= the existing + internal structure definations.\n + Note: Here revision will be bumped up when adding/removing any config bl= ock under this structure.\n + Revision 1: + - Initial version. +**/ +typedef struct { + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31 +/* + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock() +*/ +} SA_POLICY_PROTOCOL; + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsGna.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsGna.h new file mode 100644 index 0000000000..6f3541e3e9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sGna.h @@ -0,0 +1,32 @@ +/** @file + Register names for GNA block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_GNA_H_ +#define _SA_REGS_GNA_H_ + +// +// Device 8 Equates +// +#define SA_GNA_BUS_NUM 0x00 +#define SA_GNA_DEV_NUM 0x08 +#define SA_GNA_FUN_NUM 0x00 +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsHostBridge.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Inclu= de/Register/SaRegsHostBridge.h new file mode 100644 index 0000000000..2cc0e5be68 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sHostBridge.h @@ -0,0 +1,214 @@ +/** @file + Register names for Host Bridge block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_HOST_BRIDGE_H_ +#define _SA_REGS_HOST_BRIDGE_H_ + +// +// DEVICE 0 (Memory Controller Hub) +// +#define SA_MC_BUS 0x00 +#define SA_MC_DEV 0x00 +#define SA_MC_FUN 0x00 +#define V_SA_MC_VID 0x8086 +#define R_SA_MC_DEVICE_ID 0x02 +#define R_SA_MC_CAPID0_B 0xE8 + +/// +/// Maximum number of SDRAM channels supported by the memory controller +/// +#define SA_MC_MAX_CHANNELS 2 + +/// +/// Maximum number of DIMM sockets supported by each channel +/// +#define SA_MC_MAX_SLOTS 2 + +/// +/// Maximum number of sides supported per DIMM +/// +#define SA_MC_MAX_SIDES 2 + +/// +/// Maximum number of DIMM sockets supported by the memory controller +/// +#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS * SA_MC_MAX_SLOTS) + +/// +/// Maximum number of rows supported by the memory controller +/// +#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES) + +/// +/// Maximum number of rows supported by the memory controller +/// +#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS) + +/// +/// Maximum memory supported by the memory controller +/// 4 GB in terms of KB +/// +#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024) + +/// +/// Define the maximum number of data bytes on a system with no ECC memory= support. +/// +#define SA_MC_MAX_BYTES_NO_ECC (8) + +/// +/// Define the maximum number of SPD data bytes on a DIMM. +/// +#define SA_MC_MAX_SPD_SIZE (512) +// +// Maximum DMI lanes and bundles supported (x8 and 4 lanes) +// +#define SA_DMI_MAX_LANE 0x04 +#define SA_DMI_MAX_BUNDLE 0x02 + +#define SA_DMI_CFL_MAX_LANE 0x04 +#define SA_DMI_CFL_MAX_BUNDLE 0x02 +// +// KabyLake CPU Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_KBL_MB_ULT_1 0x5904 ///< Kabylake Ult (OPI) (2+1F= /1.5F/2F/3/3E) Mobile SA DID +// +// KabyLake CPU Halo SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_KBL_HALO_2 0x5910 ///< Kabylake Halo (4+2/4E/3F= E) SA DID +// +// KabyLake CPU Desktop SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_KBL_DT_2 0x591F ///< Kabylake Desktop (4+1.5F= /2/4) SA DID +// +// KabyLake CPU Server SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_KBL_SVR_2 0x5918 ///< Kabylake Server (4+1/2/4= E) SA DID + +// +// CoffeeLake CPU Mobile SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_ULT_1 0x3ED0 ///< CoffeeLake Mobile (C= FL-U 4+3e) SA DID +#define V_SA_DEVICE_ID_CFL_ULT_2 0x3ECC ///< CoffeeLake Mobile (C= FL-U 2+3e) SA DID +#define V_SA_DEVICE_ID_CFL_ULT_3 0x3E34 ///< CoffeeLake Mobile (C= FL-U 4+(1 or 2)) SA DID +#define V_SA_DEVICE_ID_CFL_ULT_4 0x3E35 ///< CoffeeLake Mobile (C= FL-U 2+(1 or 2)) SA DID +#define V_SA_DEVICE_ID_CFL_ULT_6 0x3ECC ///< CoffeeLake Mobile (C= FL-U 2+3e) SA DID + +// +// CoffeeLake CPU Desktop SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_DT_1 0x3EC2 ///< CoffeeLake Desktop (= 6+2) SA DID +#define V_SA_DEVICE_ID_CFL_DT_2 0x3E1F ///< CoffeeLake Desktop (= 4+2) SA DID +#define V_SA_DEVICE_ID_CFL_DT_3 0x3E0F ///< CoffeeLake Desktop (= 2+2) SA DID +#define V_SA_DEVICE_ID_CFL_DT_4 0x3E30 ///< CoffeeLake Desktop (= 8+2) SA DID + +// +// CoffeeLake CPU Halo SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_HALO_1 0x3EC4 ///< CoffeeLake Halo (6+2= ) SA DID +#define V_SA_DEVICE_ID_CFL_HALO_2 0x3E10 ///< CoffeeLake Halo (4+2= ) SA DID +#define V_SA_DEVICE_ID_CFL_HALO_3 0x3E20 ///< CoffeeLake Halo (8+2= ) SA DID + +// +// CoffeeLake CPU WS SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_WS_1 0x3EC6 ///< CoffeeLake WorkStati= on (6+2) SA DID +#define V_SA_DEVICE_ID_CFL_WS_2 0x3E18 ///< CoffeeLake WrokStati= on (4+2) SA DID +#define V_SA_DEVICE_ID_CFL_WS_3 0x3E31 ///< CoffeeLake WrokStati= on (8+2) SA DID + +// +// CPU Server SA Device IDs B0:D0:F0 +// +#define V_SA_DEVICE_ID_CFL_SVR_1 0x3ECA ///< CoffeeLake Server (6= +0) SA DID +#define V_SA_DEVICE_ID_CFL_SVR_2 0x3E32 ///< CoffeeLake Server (8= +0) SA DID +#define V_SA_DEVICE_ID_CFL_SVR_3 0x3E33 ///< CoffeeLake Server (4= +0) SA DID +/** + Description: + - This is the base address for the Host Memory Mapped Configuration space= . There is no physical memory within this 32KB window that can be addresse= d. The 32KB reserved by this register does not alias to any PCI 2.3 compli= ant memory mapped space. On reset, the Host MMIO Memory Mapped Configuatio= n space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, = offset48h, bit 0]. + - All the bits in this register are locked in LT mode. + - The register space contains memory control, initialization, timing, and= buffer strength registers; clocking registers; and power and thermal manag= ement registers. +**/ +#define R_SA_MCHBAR (0x48) +/** + Description: + - All the bits in this register are LT lockable. +**/ +#define R_SA_GGC (0x50) +#define N_SA_GGC_GMS_OFFSET (0x8) +#define B_SA_GGC_GMS_MASK (0xff00) +#define N_SA_GGC_GGMS_OFFSET (0x6) +#define B_SA_GGC_GGMS_MASK (0xc0) +#define V_SA_GGC_GGMS_8MB 3 +/** + Description: + - Allows for enabling/disabling of PCI devices and functions that are wit= hin the CPU package. The table below the bit definitions describes the beha= vior of all combinations of transactions to devices controlled by this regi= ster. + All the bits in this register are LT Lockable. +**/ +#define R_SA_DEVEN (0x54) +#define B_SA_DEVEN_D2EN_MASK (0x10) +/** + Description: + This is the base address for the PCI Express configuration space. This = window of addresses contains the 4KB of configuration space for each PCI Ex= press device that can potentially be part of the PCI Express Hierarchy asso= ciated with the Uncore. There is no actual physical memory within this win= dow of up to 256MB that can be addressed. The actual size of this range is= determined by a field in this register. + Each PCI Express Hierarchy requires a PCI Express BASE register. The Un= core supports one PCI Express Hierarchy. The region reserved by this regis= ter does not alias to any PCI2.3 compliant memory mapped space. For exampl= e, the range reserved for MCHBAR is outside of PCIEXBAR space. + On reset, this register is disabled and must be enabled by writing a 1 t= o the enable field in this register. This base address shall be assigned o= n a boundary consistent with the number of buses (defined by the length fie= ld in this register), above TOLUD and still within 39-bit addressable memor= y space. + The PCI Express Base Address cannot be less than the maximum address wri= tten to the Top of physical memory register (TOLUD). Software must guarant= ee that these ranges do not overlap with known ranges located above TOLUD. + Software must ensure that the sum of the length of the enhanced configur= ation region + TOLUD + any other known ranges reserved above TOLUD is not g= reater than the 39-bit addessable limit of 512GB. In general, system imple= mentation and the number of PCI/PCI Express/PCI-X buses supported in the hi= erarchy will dictate the length of the region. + All the bits in this register are locked in LT mode. +**/ +#define R_SA_PCIEXBAR (0x60) + +/** + Description: + - This register controls the read, write and shadowing attributes of the = BIOS range from F_0000h to F_FFFFh. The Uncore allows programmable memory = attributes on 13 legacy memory segments of various sizes in the 768KB to 1M= B address range. Seven Programmable Attribute Map (PAM) registers are used= to support these features. Cacheability of these areas is controlled via = the MTRR register in the core. + - Two bits are used to specify memory attributes for each memory segment.= These bits apply to host accesses to the PAM areas. These attributes are: + - RE - Read Enable. When RE=3D1, the host read accesses to the correspon= ding memory segment are claimed by the Uncore and directed to main memory. = Conversely, when RE=3D0, the host read accesses are directed to DMI. + - WE - Write Enable. When WE=3D1, the host write accesses to the corresp= onding memory segment are claimed by the Uncore and directed to main memory= . Conversely, when WE=3D0, the host read accesses are directed to DMI. + - The RE and WE attributes permit a memory segment to be Read Only, Write= Only, Read/Write or Disabled. For example, if a memory segment has RE=3D1= and WE=3D0, the segment is Read Only. +**/ +#define R_SA_PAM0 (0x80) + +/// +/// Description: +/// The SMRAMC register controls how accesses to Compatible SMRAM spaces = are treated. The Open, Close and Lock bits function only when G_SMRAME bit= is set to 1. Also, the Open bit must be reset before the Lock bit is set. +/// +#define R_SA_SMRAMC (0x88) +#define B_SA_SMRAMC_D_LCK_MASK (0x10) +#define B_SA_SMRAMC_D_CLS_MASK (0x20) +#define B_SA_SMRAMC_D_OPEN_MASK (0x40) +/// +/// Description: +/// This register contains the Top of low memory address. +/// +#define R_SA_TOLUD (0xbc) +#define R_SA_MC_CAPID0_A_OFFSET 0xE4 +// +// MCHBAR IO Register Offset Equates +// +#define R_SA_MCHBAR_BIOS_RESET_CPL_OFFSET 0x5DA8 + +#define V_SA_LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel reco= mmended maximum value for Snoop Latency (70us) +#define V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel reco= mmended maximum value for Non-Snoop Latency (70us) +/// +/// Vt-d Engine base address. +/// +#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT1 for = IGD +#define R_SA_MCHBAR_VTD3_OFFSET 0x5410 ///< HW UNIT3 for all other -= PEG, USB, SATA etc +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsIgd.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsIgd.h new file mode 100644 index 0000000000..f8b794a9fb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sIgd.h @@ -0,0 +1,50 @@ +/** @file + Register names for IGD block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_IGD_H_ +#define _SA_REGS_IGD_H_ + +/// +/// Device 2 Register Equates +/// +// +// The following equates must be reviewed and revised when the specificati= on is ready. +// +#define SA_IGD_BUS 0x00 +#define SA_IGD_DEV 0x02 +#define SA_IGD_FUN_0 0x00 +#define SA_IGD_DEV_FUN (SA_IGD_DEV << 3) +#define SA_IGD_BUS_DEV_FUN (SA_MC_BUS << 8) + SA_IGD_DEV_FUN + +#define V_SA_IGD_VID 0x8086 +#define SA_GT_APERTURE_SIZE_256MB 1 ///< 256MB is the recommanded = GT Aperture Size as per BWG. + +#define V_SA_PCI_DEV_2_GT2_CFL_ULT_1_ID 0x3EA0 ///< Dev2 CFL-U GT2 +#define V_SA_PCI_DEV_2_GT1_CFL_ULT_1_ID 0x3EA1 ///< Dev2 CFL-U GT1 +#define R_SA_IGD_VID 0x00 +#define R_SA_IGD_DID 0x02 +#define R_SA_IGD_CMD 0x04 + +#define R_SA_IGD_SWSCI_OFFSET 0x00E8 +#define R_SA_IGD_ASLS_OFFSET 0x00FC ///< ASL Storage + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsIpu.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsIpu.h new file mode 100644 index 0000000000..b26c79ec95 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sIpu.h @@ -0,0 +1,37 @@ +/** @file + Register names for IPU block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_IPU_H_ +#define _SA_REGS_IPU_H_ + +// +// Device 5 Equates +// +#define SA_IPU_BUS_NUM 0x00 +#define SA_IPU_DEV_NUM 0x05 +#define SA_IPU_FUN_NUM 0x00 + +// +// GPIO native features pins data +// +#define SA_GPIO_IMGUCLK_NUMBER_OF_PINS 2 +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Registe= r/SaRegsPeg.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Regi= ster/SaRegsPeg.h new file mode 100644 index 0000000000..b7e9416fc6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/Register/SaReg= sPeg.h @@ -0,0 +1,64 @@ +/** @file + Register names for PEG block + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_PEG_H_ +#define _SA_REGS_PEG_H_ +// +// Device 1 Memory Mapped IO Register Offset Equates +// +#define SA_PEG_BUS_NUM 0x00 +#define SA_PEG_DEV_NUM 0x01 +#define SA_PEG0_DEV_NUM SA_PEG_DEV_NUM +#define SA_PEG0_FUN_NUM 0x00 +#define SA_PEG1_DEV_NUM SA_PEG_DEV_NUM +#define SA_PEG1_FUN_NUM 0x01 +#define SA_PEG2_DEV_NUM SA_PEG_DEV_NUM +#define SA_PEG2_FUN_NUM 0x02 +// +// Temporary Device & Function Number used for Switchable Graphics DGPU +// +#define SA_TEMP_DGPU_DEV 0x00 +#define SA_TEMP_DGPU_FUN 0x00 + +// +// SA PCI Express* Port configuration +// +#define SA_PEG_MAX_FUN 0x03 +#define SA_PEG_MAX_LANE 0x10 +#define SA_PEG_MAX_BUNDLE 0x08 + +// +// Silicon and SKU- specific MAX defines +// +#define SA_PEG_CNL_H_MAX_FUN SA_PEG_MAX_FUN // CNL-H- SKU s= upports 4 controllers with 20 PEG lanes and 10 bundles +#define SA_PEG_CNL_H_MAX_LANE SA_PEG_MAX_LANE +#define SA_PEG_CNL_H_MAX_BUNDLE SA_PEG_MAX_BUNDLE +#define SA_PEG_NON_CNL_H_MAX_FUN 0x03 // All non-CNL-= H- SKU supports 3 controllers with 16 PEG lanes and 8 bundles +#define SA_PEG_NON_CNL_H_MAX_LANE 0x10 +#define SA_PEG_NON_CNL_H_MAX_BUNDLE 0x08 + + + +#define R_SA_PEG_VID_OFFSET 0x00 ///< Vendor ID +#define R_SA_PEG_DID_OFFSET 0x02 ///< Device ID +#define R_SA_PEG_SS_OFFSET 0x8C ///< Subsystem ID +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAcces= s.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h new file mode 100644 index 0000000000..b98f1732ba --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaAccess.h @@ -0,0 +1,106 @@ +/** @file + Macros to simplify and abstract the interface to PCI configuration. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SAACCESS_H_ +#define _SAACCESS_H_ + +#include "SaRegs.h" +#include "SaCommonDefinitions.h" + +/// +/// SystemAgent Base Address definition +/// +#ifndef STALL_ONE_MICRO_SECOND +#define STALL_ONE_MICRO_SECOND 1 +#endif +#ifndef STALL_ONE_MILLI_SECOND +#define STALL_ONE_MILLI_SECOND 1000 +#endif + +// +// SA Segement Number +// +#define SA_SEG_NUM 0x00 + +#define V_SA_DEVICE_ID_INVALID 0xFFFF + + +/// +/// The value before AutoConfig match the setting of PCI Express Base Spec= ification 1.1, please be careful for adding new feature +/// +typedef enum { + PcieAspmDisabled, + PcieAspmL0s, + PcieAspmL1, + PcieAspmL0sL1, + PcieAspmAutoConfig, + PcieAspmMax +} SA_PCIE_ASPM_CONFIG; + +/// +/// SgMode settings +/// +typedef enum { + SgModeDisabled =3D 0, + SgModeReserved, + SgModeMuxless, + SgModeDgpu, + SgModeMax +} SG_MODE; + +// +// Macros that judge which type a device ID belongs to +// +#define IS_SA_DEVICE_ID_MOBILE(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_KBL_MB_ULT_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_ULT_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_ULT_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_ULT_3) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_ULT_4) \ + ) + +/// +/// Device IDs that are Desktop specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_DESKTOP(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_KBL_DT_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_DT_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_DT_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_DT_3) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_DT_4) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_WS_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_WS_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_WS_3) \ + ) + +/// +/// Device IDS that are Server specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_SERVER(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_KBL_SVR_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_SVR_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_SVR_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_SVR_3) \ + ) + +/// +/// Device IDs that are Halo specific B0:D0:F0 +/// +#define IS_SA_DEVICE_ID_HALO(DeviceId) \ + ( \ + (DeviceId =3D=3D V_SA_DEVICE_ID_KBL_HALO_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_HALO_1) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_HALO_2) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_HALO_3) || \ + (DeviceId =3D=3D V_SA_DEVICE_ID_CFL_HALO_IOT_1) \ + ) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommo= nDefinitions.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaC= ommonDefinitions.h new file mode 100644 index 0000000000..ab9224e573 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaCommonDefini= tions.h @@ -0,0 +1,23 @@ +/** @file + This header file provides common definitions just for System Agent using= to avoid including extra module's file. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_COMMON_DEFINITIONS_H_ +#define _SA_COMMON_DEFINITIONS_H_ + +#define ERROR_BY_16 (0xEE15) +#define ERROR_NOT_BY_16 (0xED15) + +#define MAX_PCIE_ASPM_OVERRIDE 500 +#define MAX_PCIE_LTR_OVERRIDE 500 + +#define DISABLED 0 +#define ENABLED 1 + +#define SA_VTD_ENGINE_NUMBER 3 + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciEx= pressLib.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciEx= pressLib.h new file mode 100644 index 0000000000..87aa105df2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPciExpressLi= b.h @@ -0,0 +1,25 @@ +/** @file + Header file for the PCI Express library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_PCI_EXPRESS_LIB_H_ +#define _SA_PCI_EXPRESS_LIB_H_ + + +/** + Gets the base address of PCI Express. + + This internal functions retrieves PCI Express Base Address. + + @return The base address of PCI Express. +**/ +VOID* +GetPciExpressBaseAddress ( + VOID +); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolic= yCommon.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicy= Common.h new file mode 100644 index 0000000000..086c60bfed --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaPolicyCommon= .h @@ -0,0 +1,51 @@ +/** @file + Main System Agent Policy structure definition which will contain several= config blocks during runtime. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_POLICY_COMMON_H_ +#define _SA_POLICY_COMMON_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +// +// Extern the GUID for PPI users. +// +extern EFI_GUID gSiPolicyPpiGuid; +extern EFI_GUID gSaMiscPeiConfigGuid; +extern EFI_GUID gGraphicsPeiConfigGuid; +extern EFI_GUID gSaPciePeiConfigGuid; +extern EFI_GUID gGnaConfigGuid; +extern EFI_GUID gVtdConfigGuid; +extern EFI_GUID gSaOverclockingPreMemConfigGuid; +extern EFI_GUID gSiPreMemPolicyPpiGuid; +extern EFI_GUID gSaMiscPeiPreMemConfigGuid; +extern EFI_GUID gSaPciePeiPreMemConfigGuid; +extern EFI_GUID gGraphicsPeiPreMemConfigGuid; +extern EFI_GUID gIpuPreMemConfigGuid; +extern EFI_GUID gSwitchableGraphicsConfigGuid; +extern EFI_GUID gCpuTraceHubConfigGuid; +extern EFI_GUID gMemoryConfigGuid; +extern EFI_GUID gMemoryConfigNoCrcGuid; + +#endif // _SA_POLICY_COMMON_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.= h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h new file mode 100644 index 0000000000..593b907d2a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Include/SaRegs.h @@ -0,0 +1,32 @@ +/** @file + Register names for System Agent (SA) registers + Conventions: + - Prefixes: + - Definitions beginning with "R_" are registers + - Definitions beginning with "B_" are bits within registers + - Definitions beginning with "V_" are meaningful values of bits within= the registers + - Definitions beginning with "S_" are register sizes + - Definitions beginning with "N_" are the bit position + - In general, SA registers are denoted by "_SA_" in register names + - Registers / bits that are different between SA generations are denoted= by + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_" + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]" + at the end of the register/bit names + - Registers / bits of new devices introduced in a SA generation will be = just named + as "_SA_" without [generation_name] inserted. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_REGS_H_ +#define _SA_REGS_H_ + +#include +#include +#include +#include +#include + +#endif --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45889): https://edk2.groups.io/g/devel/message/45889 Mute This Topic: https://groups.io/mt/32918181/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45891+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45891+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001014; cv=none; d=zoho.com; s=zohoarc; b=Y2CA6z2i/ivMwVpuUN5ZEnoGplC92zFZ8Rbnt2EElVEuU7DexMNvXFCPoPFotRbhH1PBaVVaa68JoImtIY+2rw9vu49qaBgUz7alcGWkFgXtvpOs+DrAddo9TlfaXWbue01rl0pANAsVphTTABbnOK9J/Pho/TLXElt4A2oaggo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001014; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=UKYkPaHL9JBj0uhbFZ0WJ8clTYysHDIxHSRPkYGP4bA=; b=ZpCIUZ53olb+kySRLpryqvMzjezdz6x10dB4dpDWmc5u+4Rtf9cchMzvLIlt8eB2EEU5qN5WOKzoKI1LdGGrU92HMt69hJaQbAHDHfCmyq7X4cXQvdesJMfeFuN8ajsgNNEpO0thLndNezeKObMuH7iuD/99uk1vLgrg6ktOqmI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45891+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001014967798.8410037167225; Fri, 16 Aug 2019 17:16:54 -0700 (PDT) Return-Path: X-Received: from mga04.intel.com (mga04.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:53 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319268" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:51 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 14/37] CoffeelakeSiliconPkg: Add package common library instances Date: Fri, 16 Aug 2019 17:15:40 -0700 Message-Id: <20190817001603.30632-15-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001014; bh=vkagZPdDpjC1b8XdQTxmPY/p3SRiTD/FqvM/YUXIrXg=; h=Cc:Date:From:Reply-To:Subject:To; b=U2YHzVntSsca146OnJ2atfg8oseXhC3HDsJTBQzGiSlBQXTm33wI18zZFadDyGGSR7H qng6TlCoJoAQ6GPWtV4fw7EsbYbCAvbqcojTyY51Nr0ZzEUflhAmWkcU9Ch9PLwDycAKn OoHwqJgkgqS82BBMqwRBKjjakx0jVYAVv9c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds package-level library class instances. * BaseConfigBlockLib - Library functions for config block management. * BaseSiConfigBlockLib - Library functions for managing component config blocks. * DxeAslUpdateLib - Services to update ACPI tables. * PeiDxeSmmMmPciLib - Services to manage PCI Express addresses. * PeiStallPpiLib - Installs an instance of EFI_PEI_STALL_PPI. * PeiSiPolicyLib - Installs an instance of the Silicon Policy PPI. Prints the Silicon Policy PPI values when DEBUG prints are enabled. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBl= ockLib.inf | 29 ++ Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConf= igBlockLib.inf | 33 ++ Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib= .inf | 40 ++ Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdat= eLibNull.inf | 30 ++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPc= iLib.inf | 35 ++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiStallP= piLib.inf | 31 ++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.i= nf | 51 +++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibra= ry.h | 35 ++ Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBl= ockLib.c | 146 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConf= igBlockLib.c | 87 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpdateLib= .c | 403 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAslUpdat= eLibNull.c | 126 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPc= iLib.c | 32 ++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiStallP= piLib.c | 78 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLib.c= | 214 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicyLibPr= eMem.c | 122 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/SiPrintPolicy.c = | 36 ++ 17 files changed, 1528 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/= BaseConfigBlockLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseCon= figBlockLib/BaseConfigBlockLib.inf new file mode 100644 index 0000000000..a7def2481d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseCon= figBlockLib.inf @@ -0,0 +1,29 @@ +## @file +# Component INF file for the BaseConfigBlock library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseConfigBlockLib +FILE_GUID =3D 1EC07EA8-7808-4e06-9D79-309AE331D2D5 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D ConfigBlockLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +BaseConfigBlockLib.c + +[LibraryClasses] +DebugLib +BaseMemoryLib +MemoryAllocationLib diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLi= b/BaseSiConfigBlockLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/Bas= eSiConfigBlockLib/BaseSiConfigBlockLib.inf new file mode 100644 index 0000000000..b04dc3cfa4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseS= iConfigBlockLib.inf @@ -0,0 +1,33 @@ +## @file +# Component description file for the BaseSiConfigBlockLib library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseSiConfigBlockLib +FILE_GUID =3D 6C068D0F-F48E-48CB-B369-433E507AF4A2 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D SiConfigBlockLib + + +[LibraryClasses] +DebugLib +IoLib +ConfigBlockLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +BaseSiConfigBlockLib.c + + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/Dxe= AslUpdateLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateL= ib/DxeAslUpdateLib.inf new file mode 100644 index 0000000000..658caccb43 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpda= teLib.inf @@ -0,0 +1,40 @@ +## @file +# Provides services to update ASL tables. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeAslUpdateLib +FILE_GUID =3D 8621697D-4E3A-4bf2-ADB0-3E2FF06559CA +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D AslUpdateLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PcdLib +BaseMemoryLib +UefiLib +MemoryAllocationLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +DxeAslUpdateLib.c + + +[Protocols] +gEfiAcpiTableProtocolGuid ## CONSUMES +gEfiAcpiSdtProtocolGuid ## CONSUMES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull= /DxeAslUpdateLibNull.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAs= lUpdateLibNull/DxeAslUpdateLibNull.inf new file mode 100644 index 0000000000..ae78a8e8f9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAsl= UpdateLibNull.inf @@ -0,0 +1,30 @@ +## @file +# Provides services to update ASL tables. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeAslUpdateLibNull +FILE_GUID =3D C7A3725F-6146-4FAB-B2EF-B4CED222DA52 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D AslUpdateLib + + + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +DxeAslUpdateLibNull.c + + + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/P= eiDxeSmmMmPciLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmm= MmPciLib/PeiDxeSmmMmPciLib.inf new file mode 100644 index 0000000000..fdf376bc70 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSm= mMmPciLib.inf @@ -0,0 +1,35 @@ +## @file +# Component description file for the PeiDxeSmmMmPciLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmMmPciLib +FILE_GUID =3D D03D6670-A032-11E2-9E96-0800200C9A66 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D MmPciLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] +BaseLib +PcdLib +DebugLib + +[Packages] +MdePkg/MdePkg.dec + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + +[Sources] +PeiDxeSmmMmPciLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiL= ib/PeiStallPpiLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInsta= llStallPpiLib/PeiStallPpiLib.inf new file mode 100644 index 0000000000..2e07a90406 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiS= tallPpiLib.inf @@ -0,0 +1,31 @@ +## @file +# Library description file for Stall Ppi installation +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiStallPpiLib +FILE_GUID =3D 73E3DD0E-B2C1-4429-B0B8-F8C2BD64F8CE +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D StallPpiLib + +[Sources] +PeiStallPpiLib.c + +[LibraryClasses] +BaseLib +DebugLib +TimerLib +PeiServicesLib + +[Packages] +MdePkg/MdePkg.dec + +[Ppis] +gEfiPeiStallPpiGuid ## PRODUCES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiS= iPolicyLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/= PeiSiPolicyLib.inf new file mode 100644 index 0000000000..c5945c3129 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicy= Lib.inf @@ -0,0 +1,51 @@ +## @file +# Component description file for the PeiSiPolicyLib library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiSiPolicyLib +FILE_GUID =3D 97584FAE-9299-4202-9889-2D339E4BFA5B +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D SiPolicyLib + + +[LibraryClasses] +DebugLib +IoLib +PeiServicesLib +BaseMemoryLib +MemoryAllocationLib +ConfigBlockLib +CpuPolicyLib +PchPolicyLib +PeiSaPolicyLib +PeiMePolicyLib +PcdLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PeiSiPolicyLib.c +PeiSiPolicyLibrary.h +SiPrintPolicy.c +PeiSiPolicyLibPreMem.c + + +[Guids] +gSiConfigGuid ## CONSUMES + + +[Ppis] +gSiPolicyPpiGuid ## PRODUCES +gSiPreMemPolicyPpiGuid ## PRODUCES + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiS= iPolicyLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLi= b/PeiSiPolicyLibrary.h new file mode 100644 index 0000000000..cb6b14fdd1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicy= Library.h @@ -0,0 +1,35 @@ +/** @file + Header file for the PeiSiPolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SI_POLICY_LIBRARY_H_ +#define _PEI_SI_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TEMP_MEM_BASE_ADDRESS 0xFE600000 +#define TEMP_IO_BASE_ADDRESS 0xD000 + +// +// IO/MMIO resource limits +// +#define TEMP_MEM_SIZE V_PCH_XDCI_MEM_LENGTH +#define TEMP_IO_SIZE 0x10 + +#endif // _PEI_SI_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/= BaseConfigBlockLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfi= gBlockLib/BaseConfigBlockLib.c new file mode 100644 index 0000000000..369dab97ee --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseConfigBlockLib/BaseCon= figBlockLib.c @@ -0,0 +1,146 @@ +/** @file + Library functions for Config Block management. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +/** + Create config block table + + @param[in] TotalSize - Max size to be allocated f= or the Config Block Table + @param[out] ConfigBlockTableAddress - On return, points to a poi= nter to the beginning of Config Block Table Address + + @retval EFI_INVALID_PARAMETER - Invalid Parameter + @retval EFI_OUT_OF_RESOURCES - Out of resources + @retval EFI_SUCCESS - Successfully created Config Block Table = at ConfigBlockTableAddress +**/ +EFI_STATUS +EFIAPI +CreateConfigBlockTable ( + IN UINT16 TotalSize, + OUT VOID **ConfigBlockTableAddress + ) +{ + CONFIG_BLOCK_TABLE_HEADER *ConfigBlkTblAddrPtr; + UINT32 ConfigBlkTblHdrSize; + + ConfigBlkTblHdrSize =3D (UINT32)(sizeof (CONFIG_BLOCK_TABLE_HEADER)); + + if (TotalSize <=3D (ConfigBlkTblHdrSize + sizeof (CONFIG_BLOCK_HEADER)))= { + DEBUG ((DEBUG_ERROR, "Invalid Parameter\n")); + return EFI_INVALID_PARAMETER; + } + + ConfigBlkTblAddrPtr =3D (CONFIG_BLOCK_TABLE_HEADER *)AllocateZeroPool (T= otalSize); + if (ConfigBlkTblAddrPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Could not allocate memory.\n")); + return EFI_OUT_OF_RESOURCES; + } + ConfigBlkTblAddrPtr->NumberOfBlocks =3D 0; + ConfigBlkTblAddrPtr->Header.GuidHob.Header.HobLength =3D TotalSize; + ConfigBlkTblAddrPtr->AvailableSize =3D TotalSize - ConfigBlkTblHdrSize; + + *ConfigBlockTableAddress =3D (VOID *)ConfigBlkTblAddrPtr; + + return EFI_SUCCESS; +} + +/** + Add config block into config block table structure + + @param[in] ConfigBlockTableAddress - A pointer to the beginning= of Config Block Table Address + @param[out] ConfigBlockAddress - On return, points to a poi= nter to the beginning of Config Block Address + + @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add= new Config Block or + Config Block Offset Table is full and can= not add new Config Block. + @retval EFI_SUCCESS - Successfully added Config Block +**/ +EFI_STATUS +EFIAPI +AddConfigBlock ( + IN VOID *ConfigBlockTableAddress, + OUT VOID **ConfigBlockAddress + ) +{ + CONFIG_BLOCK *TempConfigBlk; + CONFIG_BLOCK_TABLE_HEADER *ConfigBlkTblAddrPtr; + CONFIG_BLOCK *ConfigBlkAddrPtr; + UINT16 ConfigBlkSize; + + ConfigBlkTblAddrPtr =3D (CONFIG_BLOCK_TABLE_HEADER *)ConfigBlockTableAdd= ress; + ConfigBlkAddrPtr =3D (CONFIG_BLOCK *)(*ConfigBlockAddress); + ConfigBlkSize =3D ConfigBlkAddrPtr->Header.GuidHob.Header.HobLength; + DEBUG ((DEBUG_INFO, "Config Block GUID: %g / Config Block Size: 0x%x byt= es\n", &(ConfigBlkAddrPtr->Header.GuidHob.Name), ConfigBlkSize)); + if ((ConfigBlkSize % 4) !=3D 0) { + DEBUG ((DEBUG_ERROR, "Config Block must be multiples of 4 bytes\n")); + return EFI_INVALID_PARAMETER; + } + if (ConfigBlkTblAddrPtr->AvailableSize < ConfigBlkSize) { + DEBUG ((DEBUG_ERROR, "Config Block Table is full and cannot add new Co= nfig Block.\n")); + DEBUG ((DEBUG_ERROR, "Available Config Block Size: 0x%x bytes / Reques= ted Config Block Size: 0x%x bytes\n", ConfigBlkTblAddrPtr->AvailableSize, C= onfigBlkSize)); + return EFI_OUT_OF_RESOURCES; + } + + TempConfigBlk =3D (CONFIG_BLOCK *)((UINTN)ConfigBlkTblAddrPtr + (UINTN)(= ConfigBlkTblAddrPtr->Header.GuidHob.Header.HobLength - ConfigBlkTblAddrPtr-= >AvailableSize)); + CopyMem (&TempConfigBlk->Header, &ConfigBlkAddrPtr->Header, sizeof(CONFI= G_BLOCK_HEADER)); + + ConfigBlkTblAddrPtr->NumberOfBlocks++; + ConfigBlkTblAddrPtr->AvailableSize =3D ConfigBlkTblAddrPtr->AvailableSiz= e - ConfigBlkSize; + + *ConfigBlockAddress =3D (VOID *) TempConfigBlk; + DEBUG ((DEBUG_INFO, "Config Block Address: 0x%x / Available Config Block= Size: 0x%x bytes\n", (UINT32)(UINTN)*ConfigBlockAddress, ConfigBlkTblAddrP= tr->AvailableSize)); + return EFI_SUCCESS; +} + +/** + Retrieve a specific Config Block data by GUID + + @param[in] ConfigBlockTableAddress - A pointer to the beginnin= g of Config Block Table Address + @param[in] ConfigBlockGuid - A pointer to the GUID use= s to search specific Config Block + @param[out] ConfigBlockAddress - On return, points to a po= inter to the beginning of Config Block Address + + @retval EFI_NOT_FOUND - Could not find the Config Block + @retval EFI_SUCCESS - Config Block found and return +**/ +EFI_STATUS +EFIAPI +GetConfigBlock ( + IN VOID *ConfigBlockTableAddress, + IN EFI_GUID *ConfigBlockGuid, + OUT VOID **ConfigBlockAddress + ) +{ + UINT16 OffsetIndex; + CONFIG_BLOCK *TempConfigBlk; + CONFIG_BLOCK_TABLE_HEADER *ConfigBlkTblAddrPtr; + UINT32 ConfigBlkTblHdrSize; + UINT32 ConfigBlkOffset; + UINT16 NumOfBlocks; + + ConfigBlkTblHdrSize =3D (UINT32)(sizeof (CONFIG_BLOCK_TABLE_HEADER)); + ConfigBlkTblAddrPtr =3D (CONFIG_BLOCK_TABLE_HEADER *)ConfigBlockTableAdd= ress; + NumOfBlocks =3D ConfigBlkTblAddrPtr->NumberOfBlocks; + + ConfigBlkOffset =3D 0; + for (OffsetIndex =3D 0; OffsetIndex < NumOfBlocks; OffsetIndex++) { + if ((ConfigBlkTblHdrSize + ConfigBlkOffset) > (ConfigBlkTblAddrPtr->He= ader.GuidHob.Header.HobLength)) { + break; + } + TempConfigBlk =3D (CONFIG_BLOCK *)((UINTN)ConfigBlkTblAddrPtr + (UINTN= )ConfigBlkTblHdrSize + (UINTN)ConfigBlkOffset); + if (CompareGuid (&(TempConfigBlk->Header.GuidHob.Name), ConfigBlockGui= d)) { + *ConfigBlockAddress =3D (VOID *)TempConfigBlk; + return EFI_SUCCESS; + } + ConfigBlkOffset =3D ConfigBlkOffset + TempConfigBlk->Header.GuidHob.He= ader.HobLength; + } + DEBUG ((DEBUG_ERROR, "Could not find the config block.\n")); + return EFI_NOT_FOUND; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLi= b/BaseSiConfigBlockLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseS= iConfigBlockLib/BaseSiConfigBlockLib.c new file mode 100644 index 0000000000..16a14b3245 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseS= iConfigBlockLib.c @@ -0,0 +1,87 @@ +/** @file + This file is BaseSiConfigBlockLib library is used to add config blocks + to config block header. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + + +/** + GetComponentConfigBlockTotalSize get config block table total size. + + @param[in] ComponentBlocks Component blocks array + @param[in] TotalBlockCount Number of blocks + + @retval Size of config block table +**/ +UINT16 +EFIAPI +GetComponentConfigBlockTotalSize ( + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, + IN UINT16 TotalBlockCount + ) +{ + UINT16 TotalBlockSize; + UINT16 BlockCount; + + TotalBlockSize =3D 0; + for (BlockCount =3D 0 ; BlockCount < TotalBlockCount; BlockCount++) { + TotalBlockSize +=3D (UINT32) ComponentBlocks[BlockCount].Size; + DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]=3D 0x%x\n= ", BlockCount, TotalBlockSize)); + } + + return TotalBlockSize; +} + +/** + AddComponentConfigBlocks add all config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add config blocks + @param[in] ComponentBlocks Config blocks array + @param[in] TotalBlockCount Number of blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +AddComponentConfigBlocks ( + IN VOID *ConfigBlockTableAddress, + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks, + IN UINT16 TotalBlockCount + ) +{ + UINT16 BlockCount; + VOID *ConfigBlockPointer; + CONFIG_BLOCK ConfigBlockBuf; + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + // + // Initialize ConfigBlockPointer to NULL + // + ConfigBlockPointer =3D NULL; + // + // Loop to identify each config block from ComponentBlocks[] Table and a= dd each of them + // + for (BlockCount =3D 0 ; BlockCount < TotalBlockCount; BlockCount++) { + CopyMem (&(ConfigBlockBuf.Header.GuidHob.Name), ComponentBlocks[BlockC= ount].Guid, sizeof (EFI_GUID)); + ConfigBlockBuf.Header.GuidHob.Header.HobLength =3D ComponentBlocks[Blo= ckCount].Size; + ConfigBlockBuf.Header.Revision =3D ComponentBlocks[BlockCount].= Revision; + ConfigBlockPointer =3D (VOID *)&ConfigBlockBuf; + Status =3D AddConfigBlock ((VOID *)ConfigBlockTableAddress, (VOID *)&C= onfigBlockPointer); + ASSERT_EFI_ERROR (Status); + ComponentBlocks[BlockCount].LoadDefault (ConfigBlockPointer); + } + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/Dxe= AslUpdateLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib= /DxeAslUpdateLib.c new file mode 100644 index 0000000000..04cf66fd2f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLib/DxeAslUpda= teLib.c @@ -0,0 +1,403 @@ +/** @file + Boot service DXE ASL update library implementation. + + These functions in this file can be called during DXE and cannot be call= ed during runtime + or in SMM which should use a RT or SMM library. + + This library uses the ACPI Support protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// +// Function implemenations +// +static EFI_ACPI_SDT_PROTOCOL *mAcpiSdt =3D NULL; +static EFI_ACPI_TABLE_PROTOCOL *mAcpiTable =3D NULL; + +/** + Initialize the ASL update library state. + This must be called prior to invoking other library functions. + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +InitializeAslUpdateLib ( + VOID + ) +{ + EFI_STATUS Status; + + /// + /// Locate ACPI tables + /// + Status =3D gBS->LocateProtocol (&gEfiAcpiSdtProtocolGuid, NULL, (VOID **= ) &mAcpiSdt); + ASSERT_EFI_ERROR (Status); + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID = **) &mAcpiTable); + ASSERT_EFI_ERROR (Status); + return Status; +} + + +/** + This procedure will update immediate value assigned to a Name + + @param[in] AslSignature - The signature of Operation Region that we= want to update. + @param[in] Buffer - source of data to be written over origina= l aml + @param[in] Length - length of data to be overwritten + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_NOT_FOUND - Failed to locate AcpiTable. +**/ +EFI_STATUS +UpdateNameAslCode ( + IN UINT32 AslSignature, + IN VOID *Buffer, + IN UINTN Length + ) +{ + EFI_STATUS Status; + EFI_ACPI_DESCRIPTION_HEADER *Table; + UINT8 *CurrPtr; + UINT32 *Signature; + UINT8 *DsdtPointer; + UINTN Handle; + UINT8 DataSize; + + if (mAcpiTable =3D=3D NULL) { + InitializeAslUpdateLib (); + if (mAcpiTable =3D=3D NULL) { + return EFI_NOT_READY; + } + } + + /// + /// Locate table with matching ID + /// + Handle =3D 0; + Status =3D LocateAcpiTableBySignature ( + EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATUR= E, + (EFI_ACPI_DESCRIPTION_HEADER **) &Table, + &Handle + ); + if (EFI_ERROR (Status)) { + return Status; + } + + /// + /// Point to the beginning of the DSDT table + /// + CurrPtr =3D (UINT8 *) Table; + if (CurrPtr =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + /// + /// Loop through the ASL looking for values that we must fix up. + /// + for (DsdtPointer =3D CurrPtr; DsdtPointer < (CurrPtr + ((EFI_ACPI_COMMON= _HEADER *) CurrPtr)->Length); DsdtPointer++) { + /// + /// Get a pointer to compare for signature + /// + Signature =3D (UINT32 *) DsdtPointer; + /// + /// Check if this is the Device Object signature we are looking for + /// + if ((*Signature) =3D=3D AslSignature) { + /// + /// Look for Name Encoding + /// + if (*(DsdtPointer-1) =3D=3D AML_NAME_OP) { + /// + /// Check if size of new and old data is the same + /// + DataSize =3D *(DsdtPointer+4); + if ((Length =3D=3D 1 && DataSize =3D=3D 0xA) || + (Length =3D=3D 2 && DataSize =3D=3D 0xB) || + (Length =3D=3D 4 && DataSize =3D=3D 0xC)) { + CopyMem (DsdtPointer+5, Buffer, Length); + } else if (Length =3D=3D 1 && ((*(UINT8*) Buffer) =3D=3D 0 || (*(U= INT8*) Buffer) =3D=3D 1) && (DataSize =3D=3D 0 || DataSize =3D=3D 1)) { + CopyMem (DsdtPointer+4, Buffer, Length); + } else { + FreePool (Table); + return EFI_BAD_BUFFER_SIZE; + } + Status =3D mAcpiTable->UninstallAcpiTable ( + mAcpiTable, + Handle + ); + Handle =3D 0; + Status =3D mAcpiTable->InstallAcpiTable ( + mAcpiTable, + Table, + Table->Length, + &Handle + ); + FreePool (Table); + return Status; + } + } + } + return EFI_NOT_FOUND; +} + +/** + This procedure will update the name of ASL Method + + @param[in] AslSignature - The signature of Operation Region that we= want to update. + @param[in] Buffer - source of data to be written over origina= l aml + @param[in] Length - length of data to be overwritten + + @retval EFI_SUCCESS - The function completed successfully. + @retval EFI_NOT_FOUND - Failed to locate AcpiTable. +**/ +EFI_STATUS +UpdateMethodAslCode ( + IN UINT32 AslSignature, + IN VOID *Buffer, + IN UINTN Length + ) +{ + EFI_STATUS Status; + EFI_ACPI_DESCRIPTION_HEADER *Table; + UINT8 *CurrPtr; + UINT32 *Signature; + UINT8 *DsdtPointer; + UINTN Handle; + + if (mAcpiTable =3D=3D NULL) { + InitializeAslUpdateLib (); + if (mAcpiTable =3D=3D NULL) { + return EFI_NOT_READY; + } + } + + /// + /// Locate table with matching ID + /// + Handle =3D 0; + Status =3D LocateAcpiTableBySignature ( + EFI_ACPI_3_0_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATUR= E, + (EFI_ACPI_DESCRIPTION_HEADER **) &Table, + &Handle + ); + if (EFI_ERROR (Status)) { + return Status; + } + + /// + /// Point to the beginning of the DSDT table + /// + CurrPtr =3D (UINT8 *) Table; + if (CurrPtr =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + /// + /// Loop through the ASL looking for values that we must fix up. + /// + for (DsdtPointer =3D CurrPtr; DsdtPointer < (CurrPtr + ((EFI_ACPI_COMMON= _HEADER *) CurrPtr)->Length); DsdtPointer++) { + /// + /// Get a pointer to compare for signature + /// + Signature =3D (UINT32 *) DsdtPointer; + /// + /// Check if this is the Device Object signature we are looking for + /// + if ((*Signature) =3D=3D AslSignature) { + /// + /// Look for Name Encoding + /// + if ((*(DsdtPointer-3) =3D=3D AML_METHOD_OP) + || (*(DsdtPointer-2) =3D=3D AML_METHOD_OP) + ) + { + CopyMem (DsdtPointer, Buffer, Length); + Status =3D mAcpiTable->UninstallAcpiTable ( + mAcpiTable, + Handle + ); + Handle =3D 0; + Status =3D mAcpiTable->InstallAcpiTable ( + mAcpiTable, + Table, + Table->Length, + &Handle + ); + FreePool (Table); + return Status; + } + } + } + return EFI_NOT_FOUND; +} + +/** + This function uses the ACPI SDT protocol to locate an ACPI table. + It is really only useful for finding tables that only have a single inst= ance, + e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc. + + @param[in] Signature - Pointer to an ASCII string containing t= he OEM Table ID from the ACPI table header + @param[in, out] Table - Updated with a pointer to the table + @param[in, out] Handle - AcpiSupport protocol table handle for t= he table found + @param[in, out] Version - The version of the table desired + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +LocateAcpiTableBySignature ( + IN UINT32 Signature, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle + ) +{ + EFI_STATUS Status; + INTN Index; + EFI_ACPI_TABLE_VERSION Version; + EFI_ACPI_DESCRIPTION_HEADER *OrgTable; + + if (mAcpiSdt =3D=3D NULL) { + InitializeAslUpdateLib (); + if (mAcpiSdt =3D=3D NULL) { + return EFI_NOT_READY; + } + } + + /// + /// Locate table with matching ID + /// + Version =3D 0; + Index =3D 0; + do { + Status =3D mAcpiSdt->GetAcpiTable (Index, (EFI_ACPI_SDT_HEADER **)&Org= Table, &Version, Handle); + if (Status =3D=3D EFI_NOT_FOUND) { + break; + } + ASSERT_EFI_ERROR (Status); + Index++; + } while (OrgTable->Signature !=3D Signature); + + if (Status !=3D EFI_NOT_FOUND) { + *Table =3D AllocateCopyPool (OrgTable->Length, OrgTable); + ASSERT (*Table); + } + + /// + /// If we found the table, there will be no error. + /// + return Status; +} + +/** + This function uses the ACPI SDT protocol to locate an ACPI SSDT table. + + @param[in] TableId - Pointer to an ASCII string containing the= OEM Table ID from the ACPI table header + @param[in] TableIdSize - Length of the TableId to match. Table ID= are 8 bytes long, this function + will consider it a match if the first Tab= leIdSize bytes match + @param[in, out] Table - Updated with a pointer to the table + @param[in, out] Handle - AcpiSupport protocol table handle for the= table found + @param[in, out] Version - See AcpiSupport protocol, GetAcpiTable fu= nction for use + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +LocateAcpiTableByOemTableId ( + IN UINT8 *TableId, + IN UINT8 TableIdSize, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle + ) +{ + EFI_STATUS Status; + INTN Index; + EFI_ACPI_TABLE_VERSION Version; + EFI_ACPI_DESCRIPTION_HEADER *OrgTable; + + if (mAcpiSdt =3D=3D NULL) { + InitializeAslUpdateLib (); + if (mAcpiSdt =3D=3D NULL) { + return EFI_NOT_READY; + } + } + /// + /// Locate table with matching ID + /// + Version =3D 0; + Index =3D 0; + do { + Status =3D mAcpiSdt->GetAcpiTable (Index, (EFI_ACPI_SDT_HEADER **)&Org= Table, &Version, Handle); + if (Status =3D=3D EFI_NOT_FOUND) { + break; + } + ASSERT_EFI_ERROR (Status); + Index++; + } while (CompareMem (&(OrgTable->OemTableId), TableId, TableIdSize)); + + if (Status !=3D EFI_NOT_FOUND) { + *Table =3D AllocateCopyPool (OrgTable->Length, OrgTable); + ASSERT (*Table); + } + + /// + /// If we found the table, there will be no error. + /// + return Status; +} + +/** + This function calculates and updates an UINT8 checksum. + + @param[in] Buffer Pointer to buffer to checksum + @param[in] Size Number of bytes to checksum + @param[in] ChecksumOffset Offset to place the checksum result in + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +AcpiChecksum ( + IN VOID *Buffer, + IN UINTN Size, + IN UINTN ChecksumOffset + ) +{ + UINT8 Sum; + UINT8 *Ptr; + + Sum =3D 0; + /// + /// Initialize pointer + /// + Ptr =3D Buffer; + + /// + /// set checksum to 0 first + /// + Ptr[ChecksumOffset] =3D 0; + + /// + /// add all content of buffer + /// + while (Size--) { + Sum =3D (UINT8) (Sum + (*Ptr++)); + } + /// + /// set checksum + /// + Ptr =3D Buffer; + Ptr[ChecksumOffset] =3D (UINT8) (0xff - Sum + 1); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull= /DxeAslUpdateLibNull.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslU= pdateLibNull/DxeAslUpdateLibNull.c new file mode 100644 index 0000000000..a7ce92b7c3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/DxeAslUpdateLibNull/DxeAsl= UpdateLibNull.c @@ -0,0 +1,126 @@ +/** @file + Boot service DXE ASL update library implementation. + + These functions in this file can be called during DXE and cannot be call= ed during runtime + or in SMM which should use a RT or SMM library. + + This library uses the ACPI Support protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +// +// Function implemenations +// + +/** + Initialize the ASL update library state. + This must be called prior to invoking other library functions. + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +InitializeAslUpdateLib ( + VOID + ) +{ + return EFI_SUCCESS; +} + + +/** + This procedure will update immediate value assigned to a Name + + @param[in] AslSignature - The signature of Operation Region that we= want to update. + @param[in] Buffer - source of data to be written over origina= l aml + @param[in] Length - length of data to be overwritten + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +UpdateNameAslCode ( + IN UINT32 AslSignature, + IN VOID *Buffer, + IN UINTN Length + ) +{ + return EFI_SUCCESS; +} + + +/** + This function uses the ACPI SDT protocol to locate an ACPI table. + It is really only useful for finding tables that only have a single inst= ance, + e.g. FADT, FACS, MADT, etc. It is not good for locating SSDT, etc. + + @param[in] Signature - Pointer to an ASCII string containing t= he OEM Table ID from the ACPI table header + @param[in, out] Table - Updated with a pointer to the table + @param[in, out] Handle - AcpiSupport protocol table handle for t= he table found + @param[in, out] Version - The version of the table desired + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +LocateAcpiTableBySignature ( + IN UINT32 Signature, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle + ) +{ + return EFI_SUCCESS; +} + +/** + This function uses the ACPI SDT protocol to locate an ACPI SSDT table. + + @param[in] TableId - Pointer to an ASCII string containing the= OEM Table ID from the ACPI table header + @param[in] TableIdSize - Length of the TableId to match. Table ID= are 8 bytes long, this function + will consider it a match if the first Tab= leIdSize bytes match + @param[in, out] Table - Updated with a pointer to the table + @param[in, out] Handle - AcpiSupport protocol table handle for the= table found + @param[in, out] Version - See AcpiSupport protocol, GetAcpiTable fu= nction for use + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +LocateAcpiTableByOemTableId ( + IN UINT8 *TableId, + IN UINT8 TableIdSize, + IN OUT EFI_ACPI_DESCRIPTION_HEADER **Table, + IN OUT UINTN *Handle + ) +{ + return EFI_SUCCESS; +} + +/** + This function calculates and updates an UINT8 checksum. + + @param[in] Buffer Pointer to buffer to checksum + @param[in] Size Number of bytes to checksum + @param[in] ChecksumOffset Offset to place the checksum result in + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +AcpiChecksum ( + IN VOID *Buffer, + IN UINTN Size, + IN UINTN ChecksumOffset + ) +{ + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/P= eiDxeSmmMmPciLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMm= PciLib/PeiDxeSmmMmPciLib.c new file mode 100644 index 0000000000..5085f29d6d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSm= mMmPciLib.c @@ -0,0 +1,32 @@ +/** @file + This file contains routines that get PCI Express Address + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + This procedure will get PCIE address + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + + @retval PCIE address +**/ +UINTN +MmPciBase ( + IN UINT32 Bus, + IN UINT32 Device, + IN UINT32 Function + ) +{ + ASSERT ((Bus <=3D 0xFF) && (Device <=3D 0x1F) && (Function <=3D 0x7)); + + return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20= ) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiL= ib/PeiStallPpiLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstall= StallPpiLib/PeiStallPpiLib.c new file mode 100644 index 0000000000..d462aef407 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiInstallStallPpiLib/PeiS= tallPpiLib.c @@ -0,0 +1,78 @@ +/** @file + Library to install StallPpi. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +#define PEI_STALL_RESOLUTION 1 + +/** + This function provides a blocking stall for reset at least the given num= ber of microseconds + stipulated in the final argument. + + @param PeiServices General purpose services available to every PEIM. + @param this Pointer to the local data for the interface. + @param Microseconds number of microseconds for which to stall. + + @retval EFI_SUCCESS the function provided at least the required stall. +**/ +EFI_STATUS +EFIAPI +Stall ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_STALL_PPI *This, + IN UINTN Microseconds + ); + + +EFI_PEI_STALL_PPI mStallPpi =3D { + PEI_STALL_RESOLUTION, + Stall +}; + +EFI_PEI_PPI_DESCRIPTOR mPeiInstallStallPpi =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiStallPpiGuid, + &mStallPpi +}; + +EFI_STATUS +EFIAPI +Stall ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN CONST EFI_PEI_STALL_PPI *This, + IN UINTN Microseconds + ) +{ + MicroSecondDelay (Microseconds); + return EFI_SUCCESS; +} + +/** + This function will install the StallPpi. + + @retval EFI_SUCCESS if StallPpi is installed successfully. +**/ +EFI_STATUS +EFIAPI +InstallStallPpi ( + VOID + ) +{ + EFI_STATUS Status; + + DEBUG((DEBUG_INFO, "Installing StallPpi \n")); + + Status =3D PeiServicesInstallPpi (&mPeiInstallStallPpi); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiS= iPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/Pe= iSiPolicyLib.c new file mode 100644 index 0000000000..de8d9745d3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicy= Lib.c @@ -0,0 +1,214 @@ +/** @file + This file is PeiSiPolicyLib library creates default settings of RC + Policy and installs RC Policy PPI. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSiPolicyLibrary.h" +#include + +/** + Get Si config block table total size. + + @retval Size of PCH config block table +**/ +UINT16 +EFIAPI +SiGetConfigBlockTotalSize ( + VOID + ) +{ + return (UINT16) sizeof (SI_CONFIG); +} + +EFI_STATUS +EFIAPI +LoadSiConfigBlockDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SI_CONFIG *SiConfig; + + SiConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "SiConfig->Header.GuidHob.Name =3D %g\n", &SiConfig-= >Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "SiConfig->Header.GuidHob.Header.HobLength =3D 0x%x\= n", SiConfig->Header.GuidHob.Header.HobLength)); + + SiConfig->Header.Revision =3D SI_CONFIG_REVISION; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + VOID *ConfigBlockPointer; + EFI_STATUS Status; + CONFIG_BLOCK_HEADER SiBlock; + + // + // Initalize SiBlock + // + CopyMem (&(SiBlock.GuidHob.Name), &gSiConfigGuid, sizeof (EFI_GUID)); + SiBlock.GuidHob.Header.HobLength =3D sizeof (SI_CONFIG); + SiBlock.Revision =3D SI_CONFIG_REVISION; + // + // Initialize ConfigBlockPointer + // + ConfigBlockPointer =3D (VOID *)&SiBlock; + // + // Add config block fro SiBlock + // + DEBUG ((DEBUG_INFO, "gSiConfigGuid =3D %g\n", &gSiConfigGuid)); + DEBUG ((DEBUG_INFO, "SiConfig->Header.GuidHob.Name =3D %g\n", &(SiBlock.= GuidHob.Name))); + Status =3D AddConfigBlock (ConfigBlockTableAddress, (VOID *) &ConfigBloc= kPointer); + ASSERT_EFI_ERROR (Status); + + LoadSiConfigBlockDefault ((VOID *) ConfigBlockPointer); + + return Status; +} + +/** + SiCreateConfigBlocks creates the config blocksg of Silicon Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] SiPolicyPpi The pointer to get Silicon Policy PPI in= stance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiCreateConfigBlocks ( + OUT SI_POLICY_PPI **SiPolicyPpi + ) +{ + UINT16 TotalBlockSize; + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicy; + UINT16 RequiredSize; + + SiPolicy =3D NULL; + // + // TotalBlockSize =3D Si, Pch, ME, SA and CPU config block size. + // + TotalBlockSize =3D SiGetConfigBlockTotalSize () + + PchGetConfigBlockTotalSize () + + MeGetConfigBlockTotalSize () + + SaGetConfigBlockTotalSize () + + CpuGetConfigBlockTotalSize (); + DEBUG ((DEBUG_INFO, "TotalBlockSize =3D 0x%x\n", TotalBlockSize)); + + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize; + + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *) &SiPolicy); + ASSERT_EFI_ERROR (Status); + + // + // General initialization + // + SiPolicy->TableHeader.Header.Revision =3D SI_POLICY_REVISION; + // + // Add config blocks. + // + Status =3D SiAddConfigBlocks ((VOID *) SiPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D PchAddConfigBlocks ((VOID *) SiPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D MeAddConfigBlocks ((VOID *) SiPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D SaAddConfigBlocks ((VOID *) SiPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D CpuAddConfigBlocks ((VOID *) SiPolicy); + ASSERT_EFI_ERROR (Status); + + // + // Assignment for returning SaInitPolicy config block base address + // + *SiPolicyPpi =3D SiPolicy; + return Status; +} + +/** + Print out all silicon policy information. + + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance + + @retval none +**/ +VOID +DumpSiPolicy ( + IN SI_POLICY_PPI *SiPolicyPpi + ) +{ + // + // Print SI config blocks and serial out. + // + SiPrintPolicyPpi (SiPolicyPpi); + // + // Print PCH config blocks and serial out. + // + PchPrintPolicyPpi (SiPolicyPpi); + // + // Print ME config blocks and serial out. + // + MePrintPolicyPpi (SiPolicyPpi); + // + // Print SA config blocks and serial out. + // + SaPrintPolicyPpi (SiPolicyPpi); + // + // Print CPU config block and serial out. + // + CpuPrintPolicy (SiPolicyPpi); +} + +/** + SiInstallPolicyPpi installs SiPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] SiPolicyPpi The pointer to Silicon Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiInstallPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPpiDesc; + SI_CONFIG *SiConfig; + + SiPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof = (EFI_PEI_PPI_DESCRIPTOR)); + if (SiPolicyPpiDesc =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + SiPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESC= RIPTOR_TERMINATE_LIST; + SiPolicyPpiDesc->Guid =3D &gSiPolicyPpiGuid; + SiPolicyPpiDesc->Ppi =3D SiPolicyPpi; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *= ) &SiConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Dump Silicon Policy update by Platform...\n")); + DumpSiPolicy (SiPolicyPpi); + + // + // Install Silicon Policy PPI + // + Status =3D PeiServicesInstallPpi (SiPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiS= iPolicyLibPreMem.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicy= Lib/PeiSiPolicyLibPreMem.c new file mode 100644 index 0000000000..499f895e8e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/PeiSiPolicy= LibPreMem.c @@ -0,0 +1,122 @@ +/** @file + This file is PeiSiPolicyLib library creates default settings of RC + Policy and installs RC Policy PPI. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSiPolicyLibrary.h" +#include + +/** + SiCreatePreMemConfigBlocks creates the config blocksg of Silicon PREMEM = Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] SiPreMemPolicyPpi The pointer to get Silicon Policy PPI in= stance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiCreatePreMemConfigBlocks ( + OUT SI_PREMEM_POLICY_PPI **SiPreMemPolicyPpi + ) +{ + UINT16 TotalBlockSize; + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; + UINT16 RequiredSize; + + SiPreMemPolicy =3D NULL; + // + // TotalBlockSize =3D Pch , SA, ME and CPU config block size. + // + TotalBlockSize =3D PchGetPreMemConfigBlockTotalSize () + + MeGetConfigBlockTotalSizePreMem () + + SaGetConfigBlockTotalSizePreMem () + + CpuGetPreMemConfigBlockTotalSize (); + DEBUG ((DEBUG_INFO, "TotalBlockSize =3D 0x%x\n", TotalBlockSize)); + + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize; + + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *)&SiPreMemPolicy= ); + ASSERT_EFI_ERROR (Status); + + // + // General initialization + // + SiPreMemPolicy->TableHeader.Header.Revision =3D SI_PREMEM_POLICY_REVISIO= N; + // + // Add config blocks. + // + Status =3D PchAddPreMemConfigBlocks ((VOID *) SiPreMemPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D MeAddConfigBlocksPreMem ((VOID *) SiPreMemPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D SaAddConfigBlocksPreMem ((VOID *) SiPreMemPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D CpuAddPreMemConfigBlocks ((VOID *) SiPreMemPolicy); + ASSERT_EFI_ERROR (Status); + // + // Assignment for returning SaInitPolicy config block base address + // + *SiPreMemPolicyPpi =3D SiPreMemPolicy; + return Status; +} + +/** + SiPreMemInstallPolicyPpi installs SiPreMemPolicyPpi. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] SiPreMemPolicyPpi The pointer to Silicon Policy PPI instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer +**/ +EFI_STATUS +EFIAPI +SiPreMemInstallPolicyPpi ( + IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *SiPolicyPreMemPpiDesc; + + SiPolicyPreMemPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (s= izeof (EFI_PEI_PPI_DESCRIPTOR)); + if (SiPolicyPreMemPpiDesc =3D=3D NULL) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + SiPolicyPreMemPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PP= I_DESCRIPTOR_TERMINATE_LIST; + SiPolicyPreMemPpiDesc->Guid =3D &gSiPreMemPolicyPpiGuid; + SiPolicyPreMemPpiDesc->Ppi =3D SiPolicyPreMemPpi; + + // + // Print whole PCH_POLICY_PPI and serial out. + // + PchPreMemPrintPolicyPpi (SiPolicyPreMemPpi); + // + // Print ME config blocks and serial out. + // + MePrintPolicyPpiPreMem (SiPolicyPreMemPpi); + // + // Print whole SI_POLICY_PPI and serial out. + // + SaPrintPolicyPpiPreMem (SiPolicyPreMemPpi); + // + // Print whole CPU of SI_PREMEM_POLICY_PPI and serial out. + // + CpuPreMemPrintPolicy (SiPolicyPreMemPpi); + // + // Install Silicon Policy PPI + // + Status =3D PeiServicesInstallPpi (SiPolicyPreMemPpiDesc); + ASSERT_EFI_ERROR (Status); + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/SiPr= intPolicy.c b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/SiP= rintPolicy.c new file mode 100644 index 0000000000..cf7e1b2308 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Library/PeiSiPolicyLib/SiPrintPoli= cy.c @@ -0,0 +1,36 @@ +/** @file + This file is PeiSiPolicyLib library for printing Policy settings. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSiPolicyLibrary.h" + +/** + Print whole SI_POLICY_PPI and serial out. + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +SiPrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ) +{ + DEBUG_CODE_BEGIN (); + SI_CONFIG *SiConfig; + EFI_STATUS Status; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSiConfigGuid, (VOID *= ) &SiConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "------------------------ Silicon Print Policy Start= ------------------------\n")); + DEBUG ((DEBUG_INFO, " CsmFlag=3D %x\n", SiConfig->CsmFlag)); + DEBUG ((DEBUG_INFO, " TraceHubMemBase =3D 0x%08x\n", SiConfig->TraceHubM= emBase)); + + DEBUG ((DEBUG_INFO, "------------------------ Silicon Print Policy End -= -------------------------\n")); + DEBUG_CODE_END (); +} + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45891): https://edk2.groups.io/g/devel/message/45891 Mute This Topic: https://groups.io/mt/32918183/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45892+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45892+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001015; cv=none; d=zoho.com; s=zohoarc; b=F//8YQ15h55IV/2zkPI5wI4mRIdAp3hZCUFCYw4t5Ojy6CWQLmcEfj19j1l3/3cqSZ+z1BnLzijLhZ9/47WMVn4ftewQD16q4w69bIE966jROAPWk996Fej98xgC6uURxQK3XyUyH4Y2zARu15QXONkRb9+rxiv73DnuY28pncM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001015; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=vzH5nMkGgvNlMvzQATVHBcBG5D6h5JkwNUraDs6//pc=; b=kEP912O9oc+QIKZq1uDTItHTB3uQoDRGEpf81bZtqSZGH8AHVUn43tgzvj3BxhbyOyVn8z5clHSOnI/C/TvSmHUtDTNQKIlAGsSQE5m8rwRhsgRcqZ68tP/Y+WMu2vetVmGdgZ//uEACuwyNzrJv0l8rJbaKzxjDKix2b/eYcRc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45892+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001015530295.7720893755685; Fri, 16 Aug 2019 17:16:55 -0700 (PDT) Return-Path: X-Received: from mga04.intel.com (mga04.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:53 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319272" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:52 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 15/37] CoffeelakeSiliconPkg/Cpu: Add library instances Date: Fri, 16 Aug 2019 17:15:41 -0700 Message-Id: <20190817001603.30632-16-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001014; bh=+z8BjZVm2MRMq8YaxIdkDYWBNs6wJ2eqxge08YFBLXU=; h=Cc:Date:From:Reply-To:Subject:To; b=Efc+EiY4SROPxV/CC0rW8E6nIVeeNA2g7W/C6OBoPHyO5C4L/f84IVGtMYJU+4xJ+fd BPAPuHaJ493xNNiXuWtFNzrNIi8xd+ailjn5jgmCKK+8FJotgI1QCS6Gyecp2zi/efgYi T6Ldq7viCzPywxWT7LpyUtgDTQp/ZA9g6eo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds CPU library class instances. * BaseCpuMailboxLibNull - Generic CPU mailbox interaction services. * PeiCpuPolicyLib - CPU policy configuration services. * PeiCpuPolicyLibPreMem - CPU policy pre-memory configuration services. * PeiDxeSmmCpuPlatformLib - CPU platform services. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseC= puMailboxLibNull.inf | 22 + Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLib.inf | 65 +++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLibPreMem.inf | 43 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/Pei= DxeSmmCpuPlatformLib.inf | 39 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLibrary.h | 30 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/Cpu= PlatformLibrary.h | 28 ++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/BaseC= puMailboxLibNull.c | 90 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPol= icy.c | 293 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPrintPol= icyPreMem.c | 108 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLib.c | 434 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpuPolic= yLibPreMem.c | 160 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/Cpu= PlatformLibrary.c | 415 +++++++++++++++++++ 12 files changed, 1727 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxL= ibNull/BaseCpuMailboxLibNull.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/L= ibrary/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.inf new file mode 100644 index 0000000000..4fcfca4670 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/= BaseCpuMailboxLibNull.inf @@ -0,0 +1,22 @@ +## @file +# Component description file for Cpu Mailbox Null Lib +# +# Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseCpuMailboxLibNull +FILE_GUID =3D 74F470BC-1769-4732-B9C0-EE9AB0B12411 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D CpuMailboxLib + +[Packages] +MdePkg/MdePkg.dec + +[Sources] +BaseCpuMailboxLibNull.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCp= uPolicyLib/PeiCpuPolicyLib.inf new file mode 100644 index 0000000000..c986e35360 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLib.inf @@ -0,0 +1,65 @@ +## @file +# Component description file for the PeiCpuPolicyLib library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiCpuPolicyLib +FILE_GUID =3D 5baafc8f-25c6-4d19-b141-585757509372 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D CpuPolicyLib + + +[LibraryClasses] +DebugLib +IoLib +PeiServicesLib +BaseMemoryLib +MemoryAllocationLib +CpuPlatformLib +PciSegmentLib +SaPlatformLib +SiConfigBlockLib +PostCodeLib +PcdLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +PeiCpuPolicyLib.c +PeiCpuPolicyLibrary.h +CpuPrintPolicy.c +PeiCpuPolicyLibPreMem.c +CpuPrintPolicyPreMem.c + +[Ppis] +gSiPolicyPpiGuid ## CONSUMES +gSiPreMemPolicyPpiGuid ## CONSUMES + +[FixedPcd] +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize + +[Pcd] +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## Produces + +[Guids] +gCpuConfigGuid ## PRODUCES +gCpuSgxConfigGuid ## PRODUCES +gCpuPowerMgmtBasicConfigGuid ## PRODUCES +gCpuPowerMgmtCustomConfigGuid ## PRODUCES +gCpuTestConfigGuid ## PRODUCES +gCpuPidTestConfigGuid ## PRODUCES +gCpuPowerMgmtTestConfigGuid ## PRODUCES +gCpuConfigLibPreMemConfigGuid ## PRODUCES +gCpuSecurityPreMemConfigGuid ## PRODUCES +gCpuOverclockingPreMemConfigGuid ## CONSUMES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLibPreMem.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library= /PeiCpuPolicyLib/PeiCpuPolicyLibPreMem.inf new file mode 100644 index 0000000000..52dc989f74 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLibPreMem.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for the PeiCpuPolicyLibPreMem library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiCpuPolicyLibPreMem +FILE_GUID =3D 5F4C2CF1-9DFE-4D99-9318-98FD31C8517D +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D CpuPolicyLibPreMem + +[LibraryClasses] +DebugLib +IoLib +PeiServicesLib +BaseMemoryLib +MemoryAllocationLib +CpuPlatformLib +SiConfigBlockLib +PostCodeLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +PeiCpuPolicyLib.c +PeiCpuPolicyLibrary.h +CpuPrintPolicy.c + +[Ppis] +gSiPreMemPolicyPpiGuid ## CONSUMES + +[Guids] +gCpuSecurityPreMemConfigGuid ## PRODUCES +gCpuOverclockingPreMemConfigGuid ## PRODUCES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPla= tformLib/PeiDxeSmmCpuPlatformLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/C= pu/Library/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf new file mode 100644 index 0000000000..0a56e42817 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLi= b/PeiDxeSmmCpuPlatformLib.inf @@ -0,0 +1,39 @@ +## @file +# Component description file for CPU Platform Lib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmCpuPlatformLib +FILE_GUID =3D 11647130-6AA4-41A4-A3A8-5FA296ABD977 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D CpuPlatformLib + +[LibraryClasses] +BaseLib +BaseMemoryLib +DebugLib +IoLib +PcdLib +CpuLib +TimerLib +SynchronizationLib +PciSegmentLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + +[Sources] +CpuPlatformLibrary.h +CpuPlatformLibrary.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/Pei= CpuPolicyLib/PeiCpuPolicyLibrary.h new file mode 100644 index 0000000000..6e993053fc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLibrary.h @@ -0,0 +1,30 @@ +/** @file + Header file for the PeiCpuPolicyLib library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_CPU_POLICY_LIBRARY_H_ +#define _PEI_CPU_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_MICROCODE_PATCH_SIZE 0x20000 + +#endif // _PEI_CPU_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPla= tformLib/CpuPlatformLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Libr= ary/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.h new file mode 100644 index 0000000000..0b780acd22 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLi= b/CpuPlatformLibrary.h @@ -0,0 +1,28 @@ +/** @file + Header file for Cpu Platform Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_ +#define _CPU_PLATFORM_LIBRARY_IMPLEMENTATION_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxL= ibNull/BaseCpuMailboxLibNull.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Lib= rary/BaseCpuMailboxLibNull/BaseCpuMailboxLibNull.c new file mode 100644 index 0000000000..2af11ce8d0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/BaseCpuMailboxLibNull/= BaseCpuMailboxLibNull.c @@ -0,0 +1,90 @@ +/** @file + Mailbox Library. + + Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + Generic Mailbox function for mailbox write commands. This function will + poll the mailbox interface for control, issue the write request, poll + for completion, and verify the write was successful. + + @param[in] MailboxType The type of mailbox interface to read. The O= verclocking mailbox is defined as MAILBOX_TYPE_OC =3D 2. + @param[in] MailboxCommand Overclocking mailbox command data + @param[in] MailboxData Overclocking mailbox interface data + @param[out] *MailboxStatus Pointer to the mailbox status returned from = pcode. Possible mailbox status values are: + - SUCCESS (0) Command succeede= d. + - OC_LOCKED (1) Overclocking is = locked. Service is read-only. + - INVALID_DOMAIN (2) Invalid Domain I= D provided in command data. + - MAX_RATIO_EXCEEDED (3) Ratio exceeds ma= ximum overclocking limits. + - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds = input VR's max voltage. + - OC_NOT_SUPPORTED (5) Domain does not = support overclocking. + + @retval EFI_SUCCESS Command succeeded. + @retval EFI_INVALID_PARAMETER Invalid read data detected from pcode. + @retval EFI_UNSUPPORTED Unsupported MailboxType parameter. +**/ +EFI_STATUS +EFIAPI +MailboxWrite ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + IN UINT32 MailboxData, + OUT UINT32 *MailboxStatus + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Generic Mailbox function for mailbox read commands. This function will w= rite + the read request from MailboxType, and populate the read results in the = MailboxDataPtr. + + @param[in] MailboxType The type of mailbox interface to read. The O= verclocking mailbox is defined as MAILBOX_TYPE_OC =3D 2. + @param[in] MailboxCommand Overclocking mailbox command data + @param[out] *MailboxDataPtr Pointer to the overclocking mailbox interfac= e data + @param[out] *MailboxStatus Pointer to the mailbox status returned from = pcode. Possible mailbox status are + - SUCCESS (0) Command succeede= d. + - OC_LOCKED (1) Overclocking is = locked. Service is read-only. + - INVALID_DOMAIN (2) Invalid Domain I= D provided in command data. + - MAX_RATIO_EXCEEDED (3) Ratio exceeds ma= ximum overclocking limits. + - MAX_VOLTAGE_EXCEEDED (4) Voltage exceeds = input VR's max voltage. + - OC_NOT_SUPPORTED (5) Domain does not = support overclocking. + + @retval EFI_SUCCESS Command succeeded. + @retval EFI_INVALID_PARAMETER Invalid read data detected from pcode. + @retval EFI_UNSUPPORTED Unsupported MailboxType parameter. +**/ +EFI_STATUS +EFIAPI +MailboxRead ( + IN UINT32 MailboxType, + IN UINT32 MailboxCommand, + OUT UINT32 *MailboxDataPtr, + OUT UINT32 *MailboxStatus + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Poll the run/busy bit of the mailbox until available or timeout expires. + + @param[in] MailboxType + + @retval EFI_SUCCESS Command succeeded. + @retval EFI_TIMEOUT Command timeout. +**/ +EFI_STATUS +EFIAPI +PollMailboxReady ( + IN UINT32 MailboxType + ) +{ + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /CpuPrintPolicy.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPo= licyLib/CpuPrintPolicy.c new file mode 100644 index 0000000000..38cf383e8d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPri= ntPolicy.c @@ -0,0 +1,293 @@ +/** @file + This file is PeiCpuPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyLibrary.h" +#include +#include + +/** + Print CPU_CONFIG and serial out. + + @param[in] CpuConfig Pointer to a CPU_CONFIG +**/ +VOID +CpuConfigPrint ( + IN CONST CPU_CONFIG *CpuConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ CPU Config ------------------\n"= )); + DEBUG ((DEBUG_INFO, " CPU_CONFIG : AesEnable : 0x%x\n", CpuConfig->AesEn= able)); + DEBUG ((DEBUG_INFO, " CPU_CONFIG : MicrocodePatchAddress : 0x%x\n", CpuC= onfig->MicrocodePatchAddress)); + DEBUG ((DEBUG_INFO, " CPU_CONFIG : DebugInterfaceEnable : 0x%X\n", CpuCo= nfig->DebugInterfaceEnable)); +} + +/** + Print CPU_POWER_MGMT_BASIC_CONFIG and serial out. + + @param[in] CpuPowerMgmtBasicConfig Pointer to a CPU_POWER_MGMT_BASIC_C= ONFIG +**/ +VOID +CpuPowerMgmtBasicConfigPrint ( + IN CONST CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Basic Config ----= --------------\n")); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG : OneCoreRatioLimit : = 0x%X , TwoCoreRatioLimit =3D 0x%X , ThreeCoreRatioLimit =3D 0x%X , FourCore= RatioLimit =3D 0x%X, FiveCoreRatioLimit =3D 0x%X, SixCoreRatioLimit =3D 0x%= X, SevenCoreRatioLimit =3D 0x%X, EightCoreRatioLimit =3D 0x%X \n", CpuPowe= rMgmtBasicConfig->OneCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->TwoCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->FourCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->FiveCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->SixCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->SevenCoreRatioLimit, \ + CpuPowerMgmtBasicConfig->EightCoreRatioLimit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: Hwp : 0x%x\n", CpuPow= erMgmtBasicConfig->Hwp)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: SkipSetBootPState : 0= x%x\n", CpuPowerMgmtBasicConfig->SkipSetBootPState)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: HdcControl : 0x%X\n",= CpuPowerMgmtBasicConfig->HdcControl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: (Intel Turbo Boost Ma= x Technology 3.0)EnableItbm : 0x%X\n", CpuPowerMgmtBasicConfig->EnableItbm)= ); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: EnableItbmDriver : 0x= %X\n", CpuPowerMgmtBasicConfig->EnableItbmDriver)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit2 : 0x%x\n"= , CpuPowerMgmtBasicConfig->PowerLimit2)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TurboPowerLimitLock := 0x%x\n", CpuPowerMgmtBasicConfig->TurboPowerLimitLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3DutyCycle = : 0x%x\n", CpuPowerMgmtBasicConfig->PowerLimit3DutyCycle)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3Lock : 0x%= x\n", CpuPowerMgmtBasicConfig->PowerLimit3Lock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit4Lock : 0x%= x\n", CpuPowerMgmtBasicConfig->PowerLimit4Lock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetClamp : 0x%X= \n", CpuPowerMgmtBasicConfig->TccOffsetClamp)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetLock : 0x%X\= n", CpuPowerMgmtBasicConfig->TccOffsetLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TurboMode : 0x%x\n", = CpuPowerMgmtBasicConfig->TurboMode)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccActivationOffset := 0x%X\n", CpuPowerMgmtBasicConfig->TccActivationOffset)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit1 : 0x%x\n"= , CpuPowerMgmtBasicConfig->PowerLimit1)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit2Power : 0x= %x\n", CpuPowerMgmtBasicConfig->PowerLimit2Power)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3 : 0x%x\n"= , CpuPowerMgmtBasicConfig->PowerLimit3)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit4 : 0x%x\n"= , CpuPowerMgmtBasicConfig->PowerLimit4)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit1Time : 0x%= x\n", CpuPowerMgmtBasicConfig->PowerLimit1Time)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: PowerLimit3Time : 0x%= x\n", CpuPowerMgmtBasicConfig->PowerLimit3Time)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: TccOffsetTimeWindowFo= rRatl : 0x%X\n", CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: HwpInterruptControl := 0x%x\n", CpuPowerMgmtBasicConfig->HwpInterruptControl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: MinRingRatioLimit : 0= x%x\n", CpuPowerMgmtBasicConfig->MinRingRatioLimit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_BASIC_CONFIG: MaxRingRatioLimit : 0= x%x\n", CpuPowerMgmtBasicConfig->MaxRingRatioLimit)); +} + +/** + Print CPU_POWER_MGMT_CUSTOM_CONFIG and serial out. + + @param[in] CpuPowerMgmtCustomConfig Pointer to a CPU_POWER_MGMT_CUSTOM= _CONFIG +**/ +VOID +CpuPowerMgmtCustomConfigPrint ( + IN CONST CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig + ) +{ + UINT32 Index =3D 0; + DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Custom Config ---= ---------------\n")); + DEBUG ((DEBUG_INFO, "\n CustomRatioTable... \n")); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidNumber : 0x%x\n",= CpuPowerMgmtCustomConfig->CustomRatioTable.NumberOfEntries)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidCpuid : 0x%x\n", = CpuPowerMgmtCustomConfig->CustomRatioTable.Cpuid)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: VidMaxRatio : 0x%x\n= ", CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio)); + for (Index =3D 0; Index < MAX_CUSTOM_RATIO_TABLE_ENTRIES; Index++) { + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: StateRatio[%d] : 0= x%x\n", Index, CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatio[Index]= )); + } + for (Index =3D 0; Index < MAX_16_CUSTOM_RATIO_TABLE_ENTRIES; Index++) { + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: StateRatioMax16[%d= ] : 0x%x\n", Index, CpuPowerMgmtCustomConfig->CustomRatioTable.StateRatioMa= x16[Index])); + } + for (Index =3D 0; Index < MAX_CUSTOM_CTDP_ENTRIES; Index++) { + DEBUG ( + (DEBUG_INFO, + " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] Cust= omPowerLimit1 : 0x%x\n", + Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].C= ustomPowerLimit1) + ); + DEBUG ( + (DEBUG_INFO, + " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] Cust= omPowerLimit2 : 0x%x\n", + Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].C= ustomPowerLimit2) + ); + DEBUG ( + (DEBUG_INFO, + " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] Cust= omPowerLimit1Time : 0x%x\n", + Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].C= ustomPowerLimit1Time) + ); + DEBUG ( + (DEBUG_INFO, + " CPU_POWER_MGMT_CUSTOM_CONFIG: CustomConfigTdpTable[%d] Cust= omTurboActivationRatio : 0x%x\n", + Index,CpuPowerMgmtCustomConfig->CustomConfigTdpTable[Index].C= ustomTurboActivationRatio) + ); + } + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: ConfigTdpLock : 0x%x= \n", CpuPowerMgmtCustomConfig->ConfigTdpLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_CUSTOM_CONFIG: ConfigTdpBios : 0x%x= \n", CpuPowerMgmtCustomConfig->ConfigTdpBios)); +} + +/** + Print CPU_TEST_CONFIG and serial out. + + @param[in] CpuTestConfig Pointer to a CPU_TEST_CONFIG +**/ +VOID +CpuTestConfigPrint ( + IN CONST CPU_TEST_CONFIG *CpuTestConfig + ) +{ + UINT8 PcdCpuApLoopMode; + + PcdCpuApLoopMode =3D PcdGet8 (PcdCpuApLoopMode); + + DEBUG ((DEBUG_INFO, "------------------ CPU Test Config ----------------= --\n")); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MlcStreamerPrefetcher : 0x%X\n", = CpuTestConfig->MlcStreamerPrefetcher)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MlcSpatialPrefetcher : 0x%X\n", C= puTestConfig->MlcSpatialPrefetcher)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MonitorMwaitEnable : 0x%X\n", Cpu= TestConfig->MonitorMwaitEnable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: MachineCheckEnable : 0x%X\n", Cpu= TestConfig->MachineCheckEnable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: DebugInterfaceLockEnable : 0x%X\n= ", CpuTestConfig->DebugInterfaceLockEnable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcessorTraceOutputScheme : 0x%X= \n", CpuTestConfig->ProcessorTraceOutputScheme)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcessorTraceEnable : 0x%X\n", C= puTestConfig->ProcessorTraceEnable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcessorTraceMemBase : 0x%llX\n"= , CpuTestConfig->ProcessorTraceMemBase)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ProcessorTraceMemLength : 0x%X\n"= , CpuTestConfig->ProcessorTraceMemLength)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: ThreeStrikeCounterDisable : 0x%X\= n", CpuTestConfig->ThreeStrikeCounterDisable)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: VoltageOptimization : 0x%X\n", Cp= uTestConfig->VoltageOptimization)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: CpuWakeUpTimer : 0x%X\n", CpuTest= Config->CpuWakeUpTimer)); + DEBUG ((DEBUG_INFO, " CPU_TEST_CONFIG: PcdCpuApLoopMode: 0x%X\n", PcdCpu= ApLoopMode)); +} + +/** + Print CPU_PID_TEST_CONFIG and serial out. + + @param[in] CpuPidTestConfig Pointer to a CPU_PID_TEST_CONFIG +**/ +VOID +CpuPidTestConfigPrint ( + IN CONST CPU_PID_TEST_CONFIG *CpuPidTestConfig + ) +{ + UINT32 Index =3D 0; + DEBUG ((DEBUG_INFO, "------------------ CPU PID Test Config ------------= ------\n")); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PidTuning : 0x%X\n", Index, = CpuPidTestConfig->PidTuning)); + if ( CpuPidTestConfig->PidTuning =3D=3D 1) { + for (Index =3D PID_DOMAIN_KP; Index <=3D PID_DOMAIN_KD; Index++) { + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : Ratl[%X] : 0x%X\n", In= dex, CpuPidTestConfig->Ratl[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr0[%X] : 0x%X\n"= , Index, CpuPidTestConfig->VrTdcVr0[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr1[%X] : 0x%X\n"= , Index, CpuPidTestConfig->VrTdcVr1[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr2[%X] : 0x%X\n"= , Index, CpuPidTestConfig->VrTdcVr2[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : VrTdcVr3[%X] : 0x%X\n"= , Index, CpuPidTestConfig->VrTdcVr3[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl1Msr[%X] : 0x= %X\n", Index, CpuPidTestConfig->PbmPsysPl1Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl1MmioPcs[%X] = : 0x%X\n", Index, CpuPidTestConfig->PbmPsysPl1MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl2Msr[%X] : 0x= %X\n", Index, CpuPidTestConfig->PbmPsysPl2Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPsysPl2MmioPcs[%X] = : 0x%X\n", Index, CpuPidTestConfig->PbmPsysPl2MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl1Msr[%X] : 0x%= X\n", Index, CpuPidTestConfig->PbmPkgPl1Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl1MmioPcs[%X] := 0x%X\n", Index, CpuPidTestConfig->PbmPkgPl1MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl2Msr[%X] : 0x%= X\n", Index, CpuPidTestConfig->PbmPkgPl2Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : PbmPkgPl2MmioPcs[%X] := 0x%X\n", Index, CpuPidTestConfig->PbmPkgPl2MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl1Msr[%X] : 0x%X\n= ", Index, CpuPidTestConfig->DdrPl1Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl1MmioPcs[%X] : 0x= %X\n", Index, CpuPidTestConfig->DdrPl1MmioPcs[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl2Msr[%X] : 0x%X\n= ", Index, CpuPidTestConfig->DdrPl2Msr[Index])); + DEBUG ((DEBUG_INFO, " CPU_PID_TEST_CONFIG : DdrPl2MmioPcs[%X] : 0x= %X\n", Index, CpuPidTestConfig->DdrPl2MmioPcs[Index])); + } + } +} + +/** + Print CPU_POWER_MGMT_TEST_CONFIG and serial out. + + @param[in] CpuPowerMgmtTestConfig Pointer to a CPU_POWER_MGMT_TEST_CON= FIG +**/ +VOID +CpuPowerMgmtTestConfigPrint ( + IN CONST CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig + ) +{ + CPU_GENERATION CpuGeneration; + CpuGeneration =3D GetCpuGeneration(); + DEBUG ((DEBUG_INFO, "------------------ CPU Power Mgmt Test Config -----= -------------\n")); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: Eist : 0x%x\n", CpuPow= erMgmtTestConfig->Eist)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: EnergyEfficientPState = : 0x%x\n", CpuPowerMgmtTestConfig->EnergyEfficientPState)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: EnergyEfficientTurbo := 0x%x\n", CpuPowerMgmtTestConfig->EnergyEfficientTurbo)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: TStates : 0x%x\n", Cpu= PowerMgmtTestConfig->TStates)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: BiProcHot : 0x%x\n", C= puPowerMgmtTestConfig->BiProcHot)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: DisableProcHotOut : 0x= %x\n", CpuPowerMgmtTestConfig->DisableProcHotOut)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ProcHotResponse : 0x%x= \n", CpuPowerMgmtTestConfig->ProcHotResponse)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: DisableVrThermalAlert = : 0x%x\n", CpuPowerMgmtTestConfig->DisableVrThermalAlert)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: AutoThermalReporting := 0x%x\n", CpuPowerMgmtTestConfig->AutoThermalReporting)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ThermalMonitor : 0x%x\= n", CpuPowerMgmtTestConfig->ThermalMonitor)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: Cx : 0x%x\n", CpuPower= MgmtTestConfig->Cx)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PmgCstCfgCtrlLock : 0x= %x\n", CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1e : 0x%x\n", CpuPowe= rMgmtTestConfig->C1e)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1Autodemotion : 0x%x\= n", CpuPowerMgmtTestConfig->C1AutoDemotion)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C1Undemotion : 0x%x\n"= , CpuPowerMgmtTestConfig->C1UnDemotion)); + if(CpuGeneration =3D=3D EnumCflCpu){ + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C3AutoDemotion : 0x%= x\n", CpuPowerMgmtTestConfig->C3AutoDemotion)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: C3UnDemotion : 0x%x\= n", CpuPowerMgmtTestConfig->C3UnDemotion)); + } + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCState Demotion : 0= x%x\n", CpuPowerMgmtTestConfig->PkgCStateDemotion)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCstateUndemotion : = 0x%x\n", CpuPowerMgmtTestConfig->PkgCStateUnDemotion)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CStatePreWake : 0x%x\n= ", CpuPowerMgmtTestConfig->CStatePreWake)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: TimedMwait : 0x%x\n", = CpuPowerMgmtTestConfig->TimedMwait)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstCfgCtrIoMwaitRedire= ction : 0x%x\n", CpuPowerMgmtTestConfig->CstCfgCtrIoMwaitRedirection)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ProcHotLock : 0x%x\n",= CpuPowerMgmtTestConfig->ProcHotLock)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: ConfigTdpLevel : 0x%x\= n", CpuPowerMgmtTestConfig->ConfigTdpLevel)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: RaceToHalt : 0x%x\n",= CpuPowerMgmtTestConfig->RaceToHalt)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl0I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl0T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl1I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl2I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl3I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl4I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl5I= rtl : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: PkgCStateLimit : 0x%x\= n", CpuPowerMgmtTestConfig->PkgCStateLimit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl1T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl2T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl3T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl4T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CstateLatencyControl5T= imeUnit : 0x%x\n", CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit)); + DEBUG ((DEBUG_INFO, " CPU_POWER_MGMT_TEST_CONFIG: CustomPowerUnit : 0x%x= \n", CpuPowerMgmtTestConfig->CustomPowerUnit)); + DEBUG ((DEBUG_INFO, " PpmIrmSetting : 0x%x\n", CpuPowerMgmtTestConfig->P= pmIrmSetting)); +} +/** + Print whole CPU config blocks of SI_POLICY_PPI and serial out in PostMem. + + @param[in] SiPolicyPpi The SI Policy PPI instance +**/ +VOID +CpuPrintPolicy ( + IN SI_POLICY_PPI *SiPolicyPpi + ) +{ +DEBUG_CODE_BEGIN(); + EFI_STATUS Status; + CPU_CONFIG *CpuConfig; + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CPU_TEST_CONFIG *CpuTestConfig; + CPU_PID_TEST_CONFIG *CpuPidTestConfig; + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConf= igGuid, (VOID *) &CpuPowerMgmtBasicConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomCon= figGuid, (VOID *) &CpuPowerMgmtCustomConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (V= OID *) &CpuTestConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPidTestConfigGuid,= (VOID *) &CpuPidTestConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfi= gGuid, (VOID *) &CpuPowerMgmtTestConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "\n ------------------------ SiCpuPolicy Print Begin= in PostMem----------------- \n")); + DEBUG ((DEBUG_INFO, " Revision=3D %x\n", SiPolicyPpi->TableHeader.Header= .Revision)); + + CpuConfigPrint(CpuConfig); + CpuPowerMgmtBasicConfigPrint(CpuPowerMgmtBasicConfig); + CpuPowerMgmtCustomConfigPrint(CpuPowerMgmtCustomConfig); + CpuTestConfigPrint(CpuTestConfig); + CpuPidTestConfigPrint(CpuPidTestConfig); + CpuPowerMgmtTestConfigPrint(CpuPowerMgmtTestConfig); + DEBUG ((DEBUG_INFO, "\n ------------------------ SiCpuPolicy Print End i= n PostMem ----------------- \n\n")); +DEBUG_CODE_END(); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /CpuPrintPolicyPreMem.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/Pe= iCpuPolicyLib/CpuPrintPolicyPreMem.c new file mode 100644 index 0000000000..0bcb34c99c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/CpuPri= ntPolicyPreMem.c @@ -0,0 +1,108 @@ +/** @file + This file is PeiCpuPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyLibrary.h" +#include + +/** + Print CPU_CONFIG_LIB_PREMEM_CONFIG and serial out. + + @param[in] CpuConfigLibPreMemConfig Pointer to a CPU_CONFIG_LIB_PREM= EM_CONFIG + +**/ +VOID +CpuConfigLibPreMemConfigPrint ( + IN CONST CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig + ) +{ + CPU_GENERATION CpuGeneration; + CpuGeneration =3D GetCpuGeneration(); + DEBUG ((DEBUG_INFO, "------------------ CPU Config Lib PreMem Config ---= ---------------\n")); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : HyperThreading =3D 0= x%x\n", CpuConfigLibPreMemConfig->HyperThreading)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : BootFrequency =3D 0x= %x\n", CpuConfigLibPreMemConfig->BootFrequency)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : ActiveCoreCount =3D = 0x%x\n", CpuConfigLibPreMemConfig->ActiveCoreCount)); + if(CpuGeneration =3D=3D EnumCflCpu){ + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : FClkFrequency =3D = 0x%x\n", CpuConfigLibPreMemConfig->FClkFrequency)); + } + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : JtagC10PowerGateDisa= ble =3D 0x%x\n", CpuConfigLibPreMemConfig->JtagC10PowerGateDisable)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : BistOnReset =3D 0x%x= \n", CpuConfigLibPreMemConfig->BistOnReset)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : VmxEnable =3D 0x%x\n= ", CpuConfigLibPreMemConfig->VmxEnable)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : CpuRatio =3D 0x%x\n"= , CpuConfigLibPreMemConfig->CpuRatio)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : PeciSxReset =3D 0x%x= \n", CpuConfigLibPreMemConfig->PeciSxReset)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : PeciC10Reset =3D 0x%= x\n", CpuConfigLibPreMemConfig->PeciC10Reset)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : SkipMpInit =3D 0x%x\= n", CpuConfigLibPreMemConfig->SkipMpInit)); + DEBUG ((DEBUG_INFO, "CPU_CONFIG_LIB_PREMEM_CONFIG : DpSscMarginEnable = =3D 0x%x\n", CpuConfigLibPreMemConfig->DpSscMarginEnable)); +} + +/** + Print CPU_OVERCLOCKING_PREMEM_CONFIG and serial out. + + @param[in] CpuOverClockingConfig Pointer to a CPU_OVERCLOCKING_CONFIG +**/ +VOID +CpuOverClockingPreMemConfigPrint ( + IN CONST CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ CPU OverClocking Config --------= ----------\n")); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: OcSupport : 0x%X\= n", CpuOverClockingPreMemConfig->OcSupport)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: OcLock : 0x%X\n",= CpuOverClockingPreMemConfig->OcLock)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageMode := 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageMode)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreMaxOcRatio := 0x%X\n", CpuOverClockingPreMemConfig->CoreMaxOcRatio)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageOverri= de : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageOverride)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageAdapti= ve : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageAdaptive)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CoreVoltageOffset= : 0x%X\n", CpuOverClockingPreMemConfig->CoreVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingVoltageMode := 0x%X\n", CpuOverClockingPreMemConfig->RingVoltageMode)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingVoltageOverri= de : 0x%X\n", CpuOverClockingPreMemConfig->RingVoltageOverride)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingVoltageAdapti= ve : 0x%X\n", CpuOverClockingPreMemConfig->RingVoltageAdaptive)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingVoltageOffset= : 0x%X\n", CpuOverClockingPreMemConfig->RingVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingMaxOcRatio := 0x%X\n", CpuOverClockingPreMemConfig->RingMaxOcRatio)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingDownBin := 0x%X\n", CpuOverClockingPreMemConfig->RingDownBin)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: Avx2RatioOffset := 0x%X\n", CpuOverClockingPreMemConfig->Avx2RatioOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: Avx3RatioOffset := 0x%X\n", CpuOverClockingPreMemConfig->Avx3RatioOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: BclkAdaptiveVolta= ge : 0x%X\n", CpuOverClockingPreMemConfig->BclkAdaptiveVoltage)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: CorePllVoltageOff= set : 0x%X\n", CpuOverClockingPreMemConfig->CorePllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: GtPllVoltageOffse= t : 0x%X\n", CpuOverClockingPreMemConfig->GtPllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: RingPllVoltageOff= set : 0x%X\n", CpuOverClockingPreMemConfig->RingPllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: SaPllVoltageOffse= t : 0x%X\n", CpuOverClockingPreMemConfig->SaPllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: McPllVoltageOffse= t : 0x%X\n", CpuOverClockingPreMemConfig->McPllVoltageOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: TjMaxOffset = : 0x%X\n", CpuOverClockingPreMemConfig->TjMaxOffset)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: TvbRatioClipping = : 0x%X\n", CpuOverClockingPreMemConfig->TvbRatioClipping)); + DEBUG ((DEBUG_INFO, " CPU_OVERCLOCKING_PREMEM_CONFIG:: TvbVoltageOptimiz= ation : 0x%X\n", CpuOverClockingPreMemConfig->TvbVoltageOptimization)); +} + + +/** + Print whole CPU Config blocks of SI_PREMEM_POLICY_PPI and serial out in = PreMem. + + @param[in] SiPreMemPolicyPpi The SI Pre-Mem Policy PPI instance +**/ +VOID +CpuPreMemPrintPolicy ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ +DEBUG_CODE_BEGIN(); + EFI_STATUS Status; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverclockingPreMemConfig; + + DEBUG ((DEBUG_INFO, "\n------------------------ CPU - SiPreMemPolicyPpi = Print Begin in PreMem -----------------\n")); + + DEBUG ((DEBUG_INFO, " Revision=3D %x\n", SiPreMemPolicyPpi->TableHeader.= Header.Revision)); + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre= MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclocking= PreMemConfigGuid, (VOID *) &CpuOverclockingPreMemConfig); + ASSERT_EFI_ERROR (Status); + CpuConfigLibPreMemConfigPrint(CpuConfigLibPreMemConfig); + CpuOverClockingPreMemConfigPrint(CpuOverclockingPreMemConfig); + + DEBUG ((DEBUG_INFO, "\n------------------------ CPU - SiPreMemPolicyPpi = Print End -----------------\n\n")); +DEBUG_CODE_END(); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuP= olicyLib/PeiCpuPolicyLib.c new file mode 100644 index 0000000000..181b72fec5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLib.c @@ -0,0 +1,434 @@ +/** @file + This file is PeiCpuPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyLibrary.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef FSP_FLAG +/** + Get the next microcode patch pointer. + + @param[in, out] MicrocodeData - Input is a pointer to the last microcode= patch address found, + and output points to the next patch addr= ess found. + + @retval EFI_SUCCESS - Patch found. + @retval EFI_NOT_FOUND - Patch not found. +**/ +EFI_STATUS +EFIAPI +RetrieveMicrocode ( + IN OUT CPU_MICROCODE_HEADER **MicrocodeData + ) +{ + UINTN MicrocodeStart; + UINTN MicrocodeEnd; + UINTN TotalSize; + + if ((FixedPcdGet32 (PcdFlashMicrocodeFvBase) =3D=3D 0) || (FixedPcdGet32= (PcdFlashMicrocodeFvSize) =3D=3D 0)) { + return EFI_NOT_FOUND; + } + + /// + /// Microcode binary in SEC + /// + MicrocodeStart =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + + ((EFI_FIRMWARE_VOLUME_HEADER *) (UINTN) FixedPcdGet32 (PcdFlashM= icrocodeFvBase))->HeaderLength + + sizeof (EFI_FFS_FILE_HEADER); + + MicrocodeEnd =3D (UINTN) FixedPcdGet32 (PcdFlashMicrocodeFvBase) + (UINT= N) FixedPcdGet32 (PcdFlashMicrocodeFvSize); + + if (*MicrocodeData =3D=3D NULL) { + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart; + } else { + if (*MicrocodeData < (CPU_MICROCODE_HEADER *) (UINTN) MicrocodeStart) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData < MicrocodeStart \n")= ); + return EFI_NOT_FOUND; + } + + TotalSize =3D (UINTN) ((*MicrocodeData)->TotalSize); + if (TotalSize =3D=3D 0) { + TotalSize =3D 2048; + } + + *MicrocodeData =3D (CPU_MICROCODE_HEADER *) ((UINTN)*MicrocodeData + T= otalSize); + if (*MicrocodeData >=3D (CPU_MICROCODE_HEADER *) (UINTN) (MicrocodeEnd= ) || (*MicrocodeData)->TotalSize =3D=3D (UINT32) -1) { + DEBUG ((DEBUG_INFO, "[CpuPolicy]*MicrocodeData >=3D MicrocodeEnd \n"= )); + return EFI_NOT_FOUND; + } + } + return EFI_SUCCESS; +} + +/** + Get the microcode patch pointer. + + @retval EFI_PHYSICAL_ADDRESS - Address of the microcode patch, or NULL i= f not found. +**/ +EFI_PHYSICAL_ADDRESS +PlatformCpuLocateMicrocodePatch ( + VOID + ) +{ + EFI_STATUS Status; + CPU_MICROCODE_HEADER *MicrocodeData; + EFI_CPUID_REGISTER Cpuid; + UINT32 UcodeRevision; + UINTN MicrocodeBufferSize; + VOID *MicrocodeBuffer =3D NULL; + + AsmCpuid ( + CPUID_VERSION_INFO, + &Cpuid.RegEax, + &Cpuid.RegEbx, + &Cpuid.RegEcx, + &Cpuid.RegEdx + ); + + UcodeRevision =3D GetCpuUcodeRevision (); + MicrocodeData =3D NULL; + while (TRUE) { + /// + /// Find the next patch address + /// + Status =3D RetrieveMicrocode (&MicrocodeData); + DEBUG ((DEBUG_INFO, "MicrocodeData =3D %x\n", MicrocodeData)); + + if (Status !=3D EFI_SUCCESS) { + break; + } else if (CheckMicrocode (Cpuid.RegEax, MicrocodeData, &UcodeRevision= )) { + break; + } + } + + if (EFI_ERROR (Status)) { + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; + } + + /// + /// Check that microcode patch size is <=3D 128K max size, + /// then copy the patch from FV to temp buffer for faster access. + /// + MicrocodeBufferSize =3D (UINTN) MicrocodeData->TotalSize; + + if (MicrocodeBufferSize <=3D MAX_MICROCODE_PATCH_SIZE) { + MicrocodeBuffer =3D AllocatePages (EFI_SIZE_TO_PAGES (MicrocodeBufferS= ize)); + if (MicrocodeBuffer !=3D NULL) { + DEBUG(( DEBUG_INFO, "Copying Microcode to temp buffer.\n")); + CopyMem (MicrocodeBuffer, MicrocodeData, MicrocodeBufferSize); + + return (EFI_PHYSICAL_ADDRESS) (UINTN) MicrocodeBuffer; + } else { + DEBUG(( DEBUG_ERROR, "Failed to allocate enough memory for Microcode= Patch.\n")); + } + } else { + DEBUG(( DEBUG_ERROR, "Microcode patch size is greater than max allowed= size of 128K.\n")); + } + return (EFI_PHYSICAL_ADDRESS) (UINTN) NULL; +} +#endif + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_CONFIG *CpuConfig; + CpuConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CpuConfig->Header.GuidHob.Name =3D %g\n", &CpuConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", CpuConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + CPU configuration + ********************************/ + CpuConfig->AesEnable =3D CPU_FEATURE_ENABLE; +#ifndef FSP_FLAG + CpuConfig->MicrocodePatchAddress =3D PlatformCpuLocateMicrocodePatch (); +#endif //FSP_FLAG +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuSgxConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + + /******************************** + CPU SGX configuration + ********************************/ +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuPowerMgmtBasicConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + CPU_SKU CpuSku; + MSR_REGISTER TempMsr; + + CpuPowerMgmtBasicConfig =3D ConfigBlockPointer; + CpuSku =3D GetCpuSku(); + + DEBUG ((DEBUG_INFO, "CpuPowerMgmtBasicConfig->Header.GuidHob.Name =3D %g= \n", &CpuPowerMgmtBasicConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuPowerMgmtBasicConfig->Header.GuidHob.Header.HobL= ength =3D 0x%x\n", CpuPowerMgmtBasicConfig->Header.GuidHob.Header.HobLength= )); + + /******************************** + CPU Power Management Basic configuration + ********************************/ + CpuPowerMgmtBasicConfig->Hwp =3D TRUE; + CpuPowerMgmtBasicConfig->HdcControl =3D TRUE; + CpuPowerMgmtBasicConfig->PowerLimit2 =3D TRUE; + CpuPowerMgmtBasicConfig->PowerLimit3Lock =3D TRUE; + CpuPowerMgmtBasicConfig->TccOffsetLock =3D FALSE; + CpuPowerMgmtBasicConfig->EnableItbm =3D TRUE; + CpuPowerMgmtBasicConfig->EnableItbmDriver =3D FALSE; + + /// + /// Initialize RATL (Runtime Average Temperature Limit) Config for ULX. + /// + if (CpuSku =3D=3D EnumCpuUlx) { + CpuPowerMgmtBasicConfig->TccActivationOffset =3D 15; + CpuPowerMgmtBasicConfig->TccOffsetTimeWindowForRatl =3D 5000; // 5 sec + CpuPowerMgmtBasicConfig->TccOffsetClamp =3D CPU_FEATURE_EN= ABLE; + } + CpuPowerMgmtBasicConfig->TurboMode =3D TRUE; + + TempMsr.Qword =3D AsmReadMsr64 (MSR_TURBO_RATIO_LIMIT); + CpuPowerMgmtBasicConfig->OneCoreRatioLimit =3D TempMsr.Bytes.FirstByte; + CpuPowerMgmtBasicConfig->TwoCoreRatioLimit =3D TempMsr.Bytes.SecondByte; + CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit =3D TempMsr.Bytes.ThirdByte; + CpuPowerMgmtBasicConfig->FourCoreRatioLimit =3D TempMsr.Bytes.FouthByte; + CpuPowerMgmtBasicConfig->FiveCoreRatioLimit =3D TempMsr.Bytes.FifthByte; + CpuPowerMgmtBasicConfig->SixCoreRatioLimit =3D TempMsr.Bytes.SixthByte; + CpuPowerMgmtBasicConfig->SevenCoreRatioLimit =3D TempMsr.Bytes.SeventhBy= te; + CpuPowerMgmtBasicConfig->EightCoreRatioLimit =3D TempMsr.Bytes.EighthByt= e; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuPowerMgmtCustomConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CpuPowerMgmtCustomConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CpuPowerMgmtCustomConfig->Header.GuidHob.Name =3D %= g\n", &CpuPowerMgmtCustomConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuPowerMgmtCustomConfig->Header.GuidHob.Header.Hob= Length =3D 0x%x\n", CpuPowerMgmtCustomConfig->Header.GuidHob.Header.HobLeng= th)); + + /******************************** + CPU Power Management Custom configuration + ********************************/ + CpuPowerMgmtCustomConfig->CustomRatioTable.Cpuid =3D (UINT16) ((GetCpuFa= mily() | GetCpuStepping()) & (0x0FFF)); +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuTestConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_TEST_CONFIG *CpuTestConfig; + CPU_SKU CpuSku; + CpuTestConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CpuTestConfig->Header.GuidHob.Name =3D %g\n", &CpuT= estConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuTestConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", CpuTestConfig->Header.GuidHob.Header.HobLength)); + + CpuSku =3D GetCpuSku(); + /******************************** + CPU Test configuration + ********************************/ + + CpuTestConfig->MlcStreamerPrefetcher =3D CPU_FEATURE_ENABLE; + CpuTestConfig->MlcSpatialPrefetcher =3D CPU_FEATURE_ENABLE; + CpuTestConfig->MonitorMwaitEnable =3D CPU_FEATURE_ENABLE; + CpuTestConfig->MachineCheckEnable =3D CPU_FEATURE_ENABLE; + CpuTestConfig->DebugInterfaceLockEnable =3D CPU_FEATURE_ENABLE; + + if ((CpuSku =3D=3D EnumCpuUlx) || (CpuSku =3D=3D EnumCpuUlt)){ + /** + This policy should be used to enable or disable Voltage Optimization f= eature. Recommended defaults: + Enable - For Mobile SKUs(U/Y) + Disable - Rest of all SKUs other than Mobile. + **/ + CpuTestConfig->VoltageOptimization =3D CPU_FEATURE_ENABLE; + } + else { + CpuTestConfig->VoltageOptimization =3D CPU_FEATURE_DISABLE; + } +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuPidTestConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_PID_TEST_CONFIG *CpuPidTestConfig; + CpuPidTestConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CpuPidTestConfig->Header.GuidHob.Name =3D %g\n", &C= puPidTestConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuPidTestConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", CpuPidTestConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + CPU PID Test configuration + ********************************/ +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuPowerMgmtTestConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + CPU_GENERATION CpuGeneration; + UINT16 CpuDid; + + CpuPowerMgmtTestConfig =3D ConfigBlockPointer; + CpuDid =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_= MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID)); + + DEBUG ((DEBUG_INFO, "CpuPowerMgmtTestConfig->Header.GuidHob.Name =3D %g\= n", &CpuPowerMgmtTestConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuPowerMgmtTestConfig->Header.GuidHob.Header.HobLe= ngth =3D 0x%x\n", CpuPowerMgmtTestConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + CPU Power Management Test configuration + ********************************/ + CpuPowerMgmtTestConfig->Eist =3D TRUE; + CpuPowerMgmtTestConfig->EnergyEfficientPState =3D TRUE; + CpuPowerMgmtTestConfig->EnergyEfficientTurbo =3D TRUE; + if ((CpuDid =3D=3D V_SA_DEVICE_ID_CFL_DT_1) || (CpuDid =3D=3D V_SA_DEVIC= E_ID_CFL_DT_2) + || (CpuDid =3D=3D V_SA_DEVICE_ID_CFL_DT_3) || (CpuDid =3D=3D V_SA_DEV= ICE_ID_CFL_DT_4)) { + /// + /// CFL-S 6+2, CFL S 8+2, CFl S 4+2, CFL S 2+2 + /// + CpuPowerMgmtTestConfig->EnergyEfficientTurbo =3D FALSE; + } + CpuPowerMgmtTestConfig->BiProcHot =3D TRUE; + CpuPowerMgmtTestConfig->DisableProcHotOut =3D TRUE; + CpuPowerMgmtTestConfig->AutoThermalReporting =3D TRUE; + CpuPowerMgmtTestConfig->ThermalMonitor =3D TRUE; + CpuPowerMgmtTestConfig->Cx =3D TRUE; + CpuPowerMgmtTestConfig->PmgCstCfgCtrlLock =3D TRUE; + CpuPowerMgmtTestConfig->C1e =3D TRUE; + CpuPowerMgmtTestConfig->C1AutoDemotion =3D TRUE; + CpuPowerMgmtTestConfig->C1UnDemotion =3D TRUE; + CpuGeneration =3D GetCpuGeneration(); + if(CpuGeneration =3D=3D EnumCflCpu){ + CpuPowerMgmtTestConfig->C3AutoDemotion =3D TRUE; + CpuPowerMgmtTestConfig->C3UnDemotion =3D TRUE; + } + + CpuPowerMgmtTestConfig->CStatePreWake =3D TRUE; + CpuPowerMgmtTestConfig->RaceToHalt =3D TRUE; + CpuPowerMgmtTestConfig->CstateLatencyControl0TimeUnit =3D TimeUnit1024ns; + CpuPowerMgmtTestConfig->CstateLatencyControl1TimeUnit =3D TimeUnit1024ns; + CpuPowerMgmtTestConfig->CstateLatencyControl2TimeUnit =3D TimeUnit1024ns; + CpuPowerMgmtTestConfig->CstateLatencyControl3TimeUnit =3D TimeUnit1024ns; + CpuPowerMgmtTestConfig->CstateLatencyControl4TimeUnit =3D TimeUnit1024ns; + CpuPowerMgmtTestConfig->CstateLatencyControl5TimeUnit =3D TimeUnit1024ns; + CpuPowerMgmtTestConfig->CstateLatencyControl0Irtl =3D C3_LATENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl1Irtl =3D C6_C7_SHORT_LA= TENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl2Irtl =3D C6_C7_LONG_LAT= ENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl3Irtl =3D C8_LATENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl4Irtl =3D C9_LATENCY; + CpuPowerMgmtTestConfig->CstateLatencyControl5Irtl =3D C10_LATENCY; + + CpuPowerMgmtTestConfig->PkgCStateLimit =3D PkgAuto; + CpuPowerMgmtTestConfig->CustomPowerUnit =3D PowerUnit125Mi= lliWatts; + CpuPowerMgmtTestConfig->PpmIrmSetting =3D PpmIrmPairFixe= dPriority; +} + +static COMPONENT_BLOCK_ENTRY mCpuIpBlocks [] =3D { + {&gCpuConfigGuid, sizeof (CPU_CONFIG), = CPU_CONFIG_REVISION, LoadCpuConfigDefault= }, + {&gCpuPowerMgmtBasicConfigGuid, sizeof (CPU_POWER_MGMT_BASIC_CONFI= G), CPU_POWER_MGMT_BASIC_CONFIG_REVISION, LoadCpuPowerMgmtBasi= cConfigDefault}, + {&gCpuPowerMgmtCustomConfigGuid, sizeof (CPU_POWER_MGMT_CUSTOM_CONF= IG), CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION, LoadCpuPowerMgmtCust= omConfigDefault}, + {&gCpuTestConfigGuid, sizeof (CPU_TEST_CONFIG), = CPU_TEST_CONFIG_REVISION, LoadCpuTestConfigDef= ault}, + {&gCpuPidTestConfigGuid, sizeof (CPU_PID_TEST_CONFIG), = CPU_PID_TEST_CONFIG_REVISION, LoadCpuPidTestConfig= Default}, + {&gCpuPowerMgmtTestConfigGuid, sizeof (CPU_POWER_MGMT_TEST_CONFIG= ), CPU_POWER_MGMT_TEST_CONFIG_REVISION, LoadCpuPowerMgmtTest= ConfigDefault}, +}; + +/** + Get CPU config block table total size. + + @retval Size of CPU config block table +**/ +UINT16 +EFIAPI +CpuGetConfigBlockTotalSize ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mCpuIpBlocks[0], sizeof (mCpuI= pBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + CpuAddConfigBlocks add all Cpu config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add CPU config bloc= ks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CpuAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + EFI_STATUS Status; + DEBUG((DEBUG_INFO, "CPU Post-Mem Entry \n")); + PostCode (0xC00); + + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress, &mCpuIpBlo= cks[0], sizeof (mCpuIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); + DEBUG ((DEBUG_INFO, "CpuAddConfigBlocks Done \n")); + PostCode (0xC09); + + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib= /PeiCpuPolicyLibPreMem.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/P= eiCpuPolicyLib/PeiCpuPolicyLibPreMem.c new file mode 100644 index 0000000000..7d45e10236 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiCpuPolicyLib/PeiCpu= PolicyLibPreMem.c @@ -0,0 +1,160 @@ +/** @file + This file is PeiCpuPolicyLibPreMem library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyLibrary.h" +#include +#include +#include +#include + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuSecurityPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuConfigLibPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_GENERATION CpuGeneration; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + CPU_FAMILY CpuFamily; + CPU_SKU CpuSku; + BOOLEAN PegDisabled; + UINT64 MchBar; + UINT64 SaPciBase; + + CpuConfigLibPreMemConfig =3D ConfigBlockPointer; + CpuFamily =3D GetCpuFamily(); + CpuSku =3D GetCpuSku(); + + DEBUG ((DEBUG_INFO, "CpuConfigLibPreMemConfig->Header.GuidHob.Name =3D %= g\n", &CpuConfigLibPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuConfigLibPreMemConfig->Header.GuidHob.Header.Hob= Length =3D 0x%x\n", CpuConfigLibPreMemConfig->Header.GuidHob.Header.HobLeng= th)); + + /******************************** + CPU Config Lib PreMem configuration + ********************************/ + CpuConfigLibPreMemConfig->HyperThreading =3D CPU_FEATURE_ENABLE; + CpuConfigLibPreMemConfig->BootFrequency =3D 1; // Maximum n= on-turbo Performance + CpuConfigLibPreMemConfig->ActiveCoreCount =3D 0; // All cores= active + CpuConfigLibPreMemConfig->JtagC10PowerGateDisable =3D CPU_FEATURE_DISABL= E; + CpuConfigLibPreMemConfig->BistOnReset =3D CPU_FEATURE_DISABL= E; + CpuConfigLibPreMemConfig->VmxEnable =3D CPU_FEATURE_ENABLE; + CpuConfigLibPreMemConfig->CpuRatio =3D (RShiftU64 (AsmReadMsr64 (MSR_PLA= TFORM_INFO), N_PLATFORM_INFO_MAX_RATIO) & B_PLATFORM_INFO_RATIO_MASK); + + CpuGeneration =3D GetCpuGeneration(); + if(CpuGeneration =3D=3D EnumCflCpu){ + /// + /// FCLK Frequency + /// + + SaPciBase =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, SA_MC_DE= V, SA_MC_FUN, 0); + PciSegmentReadBuffer (SaPciBase + R_SA_MCHBAR, sizeof (MchBar), &MchBa= r); + MchBar &=3D ((UINT64) ~BIT0); + if (IsPchLinkDmi (CpuFamily) && (PciSegmentRead16 (PCI_SEGMENT_LIB_ADD= RESS (SA_SEG_NUM, SA_PEG_BUS_NUM, SA_PEG_DEV_NUM, SA_PEG0_FUN_NUM, PCI_VEND= OR_ID_OFFSET)) !=3D 0xFFFF)) { + PegDisabled =3D MmioRead32 ((UINTN) MchBar + R_SA_MCHBAR_BIOS_RESET_= CPL_OFFSET) & BIT3; + } else { + PegDisabled =3D 1; + } + + /// + /// DT/Halo FCLK =3D 1GHz + /// Ulx/Ult FCLK =3D 800MHz + /// + if (((CpuSku =3D=3D EnumCpuHalo) && (!PegDisabled)) || (CpuSku =3D=3D = EnumCpuTrad)) { + CpuConfigLibPreMemConfig->FClkFrequency =3D 1; // 1Ghz + } + else { + CpuConfigLibPreMemConfig->FClkFrequency =3D 0; // 800MHz + } + /// + /// Disable Peci Reset on C10 exit on CFL based CPU's + /// Setting to 1 will activate the message that disables peci reset. + /// + CpuConfigLibPreMemConfig->PeciC10Reset =3D 1; + } +} + +/** + Load Overclocking pre-mem Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCpuOverclockingPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverclockingPreMemConfig; + CpuOverclockingPreMemConfig =3D ConfigBlockPointer; + + /******************************** + CPU Overclocking PreMem configuration + ********************************/ + DEBUG ((DEBUG_INFO, "CpuOverclockingPreMemConfig->Header.GuidHob.Name = =3D %g\n", &CpuOverclockingPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CpuOverclockingPreMemConfig->Header.GuidHob.Header.= HobLength =3D 0x%x\n", CpuOverclockingPreMemConfig->Header.GuidHob.Header.H= obLength)); +} + +static COMPONENT_BLOCK_ENTRY mCpuIpBlocksPreMem [] =3D { + {&gCpuConfigLibPreMemConfigGuid, sizeof (CPU_CONFIG_LIB_PREMEM_CONFIG= ), CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION, LoadCpuConfigLibPreMemConfigD= efault}, + {&gCpuOverclockingPreMemConfigGuid, sizeof (CPU_OVERCLOCKING_PREMEM_CONF= IG), CPU_OVERCLOCKING_CONFIG_REVISION, LoadCpuOverclockingPreMemConf= igDefault}, +}; + +/** + Get CPU PREMEM config block table total size. + + @retval Size of CPU PREMEM config block table +**/ +UINT16 +EFIAPI +CpuGetPreMemConfigBlockTotalSize ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mCpuIpBlocksPreMem[0], sizeof = (mCpuIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + CpuAddPreMemConfigBlocks add all CPU PREMEM config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add CPU PREMEM conf= ig blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CpuAddPreMemConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + EFI_STATUS Status; + DEBUG((DEBUG_INFO, "CPU Pre-Mem Entry \n")); + PostCode (0xC00); + + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress, &mCpuIpBlo= cksPreMem[0], sizeof (mCpuIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY)); + DEBUG((DEBUG_INFO, "CpuAddPreMemConfigBlocks Done \n")); + PostCode (0xC0F); + + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPla= tformLib/CpuPlatformLibrary.c b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Libr= ary/PeiDxeSmmCpuPlatformLib/CpuPlatformLibrary.c new file mode 100644 index 0000000000..18f2028fa9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLi= b/CpuPlatformLibrary.c @@ -0,0 +1,415 @@ +/** @file + CPU Platform Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "CpuPlatformLibrary.h" +#include +#include + +#define SKIP_MICROCODE_CHECKSUM_CHECK 1 +#define C6DRAM_ENABLE 1 +#define C6DRAM_DISABLE 0 + +/** + Return CPU Family ID + + @retval CPU_FAMILY CPU Family ID +**/ +CPU_FAMILY +EFIAPI +GetCpuFamily ( + VOID + ) +{ + EFI_CPUID_REGISTER Cpuid; + /// + /// Read the CPUID information + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEc= x, &Cpuid.RegEdx); + return ((CPU_FAMILY) (Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL)); +} + +/** + Return Cpu stepping type + + @retval UINT8 Cpu stepping type +**/ +CPU_STEPPING +EFIAPI +GetCpuStepping ( + VOID + ) +{ + EFI_CPUID_REGISTER Cpuid; + /// + /// Read the CPUID information + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEc= x, &Cpuid.RegEdx); + return ((CPU_STEPPING) (Cpuid.RegEax & CPUID_FULL_STEPPING)); +} + +/** + Return CPU Sku + + @retval UINT8 CPU Sku +**/ +UINT8 +EFIAPI +GetCpuSku ( + VOID + ) +{ + UINT8 CpuType; + UINT16 CpuDid; + UINT32 CpuFamilyModel; + EFI_CPUID_REGISTER Cpuid; + BOOLEAN SkuFound; + + SkuFound =3D TRUE; + CpuType =3D EnumCpuUnknown; + + /// + /// Read the CPUID & DID information + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEc= x, &Cpuid.RegEdx); + CpuFamilyModel =3D Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL; + CpuDid =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_= BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID)); + + switch (CpuFamilyModel) { + case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX: + switch (CpuDid) { + case V_SA_DEVICE_ID_KBL_MB_ULT_1: // KBL ULT OPI + case V_SA_DEVICE_ID_CFL_ULT_1: // CFL ULT + case V_SA_DEVICE_ID_CFL_ULT_2: // CFL ULT + case V_SA_DEVICE_ID_CFL_ULT_3: // CFL ULT + case V_SA_DEVICE_ID_CFL_ULT_4: // CFL ULT + CpuType =3D EnumCpuUlt; + break; + + default: + SkuFound =3D FALSE; + break; + } + break; + + case CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO: + switch (CpuDid) { + + case V_SA_DEVICE_ID_KBL_DT_2: // DT + case V_SA_DEVICE_ID_KBL_SVR_2: // Server + case V_SA_DEVICE_ID_CFL_DT_1: // DT + case V_SA_DEVICE_ID_CFL_DT_2: // DT + case V_SA_DEVICE_ID_CFL_DT_3: // DT + case V_SA_DEVICE_ID_CFL_DT_4: // DT + case V_SA_DEVICE_ID_CFL_WS_1: // WorkStation + case V_SA_DEVICE_ID_CFL_WS_2: // Workstation + case V_SA_DEVICE_ID_CFL_WS_3: // Workstation + case V_SA_DEVICE_ID_CFL_SVR_1: // Server + case V_SA_DEVICE_ID_CFL_SVR_2: // Server + case V_SA_DEVICE_ID_CFL_SVR_3: // Server + CpuType =3D EnumCpuTrad; + break; + + case V_SA_DEVICE_ID_KBL_HALO_2: // Halo + case V_SA_DEVICE_ID_CFL_HALO_1: // Halo + case V_SA_DEVICE_ID_CFL_HALO_2: // Halo + case V_SA_DEVICE_ID_CFL_HALO_3: // Halo + CpuType =3D EnumCpuHalo; + break; + + default: + SkuFound =3D FALSE; + break; + } + break; + + default: + SkuFound =3D FALSE; + break; + } +#ifdef CFL_SIMICS + CpuType =3D EnumCpuTrad; +#else + if (!SkuFound) { + DEBUG ((DEBUG_ERROR, "Unsupported CPU SKU, Device ID: 0x%02X, CPUID: 0= x%08X!\n", CpuDid, CpuFamilyModel)); + ASSERT (FALSE); + } +#endif + + return CpuType; +} + +/** + Returns the processor microcode revision of the processor installed in t= he system. + + @retval Processor Microcode Revision +**/ +UINT32 +GetCpuUcodeRevision ( + VOID + ) +{ + AsmWriteMsr64 (MSR_IA32_BIOS_SIGN_ID, 0); + AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL); + return (UINT32) RShiftU64 (AsmReadMsr64 (MSR_IA32_BIOS_SIGN_ID), 32); +} + +/** + Verify the DWORD type checksum + + @param[in] ChecksumAddr - The start address to be checkumed + @param[in] ChecksumLen - The length of data to be checksumed + + @retval EFI_SUCCESS - Checksum correct + @retval EFI_CRC_ERROR - Checksum incorrect +**/ +EFI_STATUS +Checksum32Verify ( + IN UINT32 *ChecksumAddr, + IN UINT32 ChecksumLen + ) +{ +#if SKIP_MICROCODE_CHECKSUM_CHECK + return EFI_SUCCESS; +#else + UINT32 Checksum; + UINT32 Index; + + Checksum =3D 0; + + for (Index =3D 0; Index < ChecksumLen; Index++) { + Checksum +=3D ChecksumAddr[Index]; + } + + return (Checksum =3D=3D 0) ? EFI_SUCCESS : EFI_CRC_ERROR; +#endif +} + +/** + This function checks the MCU revision to decide if BIOS needs to load + microcode. + + @param[in] MicrocodePointer - Microcode in memory + @param[in] Revision - Current CPU microcode revision + + @retval EFI_SUCCESS - BIOS needs to load microcode + @retval EFI_ABORTED - Don't need to update microcode +**/ +EFI_STATUS +CheckMcuRevision ( + IN CPU_MICROCODE_HEADER *MicrocodePointer, + IN UINT32 Revision + ) +{ + EFI_STATUS Status; + Status =3D EFI_ABORTED; + + if ((MicrocodePointer->UpdateRevision & 0x80000000) || + (MicrocodePointer->UpdateRevision > Revision) || + (Revision =3D=3D 0)) { + Status =3D EFI_SUCCESS; + } + + return Status; +} + +/** + Check if this microcode is correct one for processor + + @param[in] Cpuid - processor CPUID + @param[in] MicrocodeEntryPoint - entry point of microcode + @param[in] Revision - revision of microcode + + @retval CorrectMicrocode if this microcode is correct +**/ +BOOLEAN +CheckMicrocode ( + IN UINT32 Cpuid, + IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint, + IN UINT32 *Revision + ) +{ + EFI_STATUS Status; + UINT8 ExtendedIndex; + MSR_IA32_PLATFORM_ID_REGISTER Msr; + UINT32 ExtendedTableLength; + UINT32 ExtendedTableCount; + BOOLEAN CorrectMicrocode; + CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; + CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; + + Status =3D EFI_NOT_FOUND; + ExtendedTableLength =3D 0; + CorrectMicrocode =3D FALSE; + + if (MicrocodeEntryPoint =3D=3D NULL) { + return FALSE; + } + + Msr.Uint64 =3D AsmReadMsr64 (MSR_IA32_PLATFORM_ID); + + /// + /// Check if the microcode is for the Cpu and the version is newer + /// and the update can be processed on the platform + /// + if ((MicrocodeEntryPoint->HeaderVersion =3D=3D 0x00000001) && + !EFI_ERROR (CheckMcuRevision (MicrocodeEntryPoint, *Revision)) + ) { + if ((MicrocodeEntryPoint->ProcessorId =3D=3D Cpuid) && (MicrocodeEntry= Point->ProcessorFlags & (1 << (UINT8) Msr.Bits.PlatformId))) { + if (MicrocodeEntryPoint->DataSize =3D=3D 0) { + Status =3D Checksum32Verify ((UINT32 *) MicrocodeEntryPoint, 2048 = / sizeof (UINT32)); + } else { + Status =3D Checksum32Verify ( + (UINT32 *) MicrocodeEntryPoint, + (MicrocodeEntryPoint->DataSize + sizeof (CPU_MICROCODE_= HEADER)) / sizeof (UINT32) + ); + } + + if (!EFI_ERROR (Status)) { + CorrectMicrocode =3D TRUE; + } + } else if ((MicrocodeEntryPoint->DataSize !=3D 0)) { + /// + /// Check the Extended Signature if the entended signature exist + /// Only the data size !=3D 0 the extended signature may exist + /// + ExtendedTableLength =3D MicrocodeEntryPoint->TotalSize - (MicrocodeE= ntryPoint->DataSize + sizeof (CPU_MICROCODE_HEADER)); + if (ExtendedTableLength !=3D 0) { + /// + /// Extended Table exist, check if the CPU in support list + /// + ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((= UINT8 *) (MicrocodeEntryPoint) + MicrocodeEntryPoint->DataSize + 48); + /// + /// Calulate Extended Checksum + /// + if ((ExtendedTableLength % 4) =3D=3D 0) { + Status =3D Checksum32Verify ((UINT32 *) ExtendedTableHeader, Ext= endedTableLength / sizeof (UINT32)); + if (!EFI_ERROR (Status)) { + /// + /// Checksum correct + /// + ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignature= Count; + ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (Exte= ndedTableHeader + 1); + for (ExtendedIndex =3D 0; ExtendedIndex < ExtendedTableCount; = ExtendedIndex++) { + /// + /// Verify Header + /// + if ((ExtendedTable->ProcessorSignature =3D=3D Cpuid) && (Ext= endedTable->ProcessorFlag & (1 << (UINT8) Msr.Bits.PlatformId))) { + Status =3D Checksum32Verify ( + (UINT32 *) ExtendedTable, + sizeof (CPU_MICROCODE_EXTENDED_TABLE) / sizeof = (UINT32) + ); + if (!EFI_ERROR (Status)) { + /// + /// Find one + /// + CorrectMicrocode =3D TRUE; + break; + } + } + + ExtendedTable++; + } + } + } + } + } + } + + return CorrectMicrocode; +} + +/** + Check on the processor if SGX is supported. + + @retval TRUE if SGX supported + @retval FALSE if SGX is not supported +**/ +BOOLEAN +IsSgxSupported ( + VOID + ) +{ + EFI_CPUID_REGISTER CpuidRegs; + + // + // Processor support SGX feature by reading CPUID.(EAX=3D7,ECX=3D0):EBX[= 2] + // + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, &CpuidRegs.RegEa= x,&CpuidRegs.RegEbx,&CpuidRegs.RegEcx,&CpuidRegs.RegEdx); + + /// + /// SGX feature is supported with CPUID.(EAX=3D7,ECX=3D0):EBX[2]=3D1 + /// PRMRR configuration enabled, MSR IA32_MTRRCAP (FEh) [12] =3D=3D 1 + /// + if (((CpuidRegs.RegEbx & BIT2)) && (AsmReadMsr64 (MSR_IA32_MTRRCAP) & BI= T12)) { + return TRUE; + } + return FALSE; +} + +/** + Get processor generation + + @retval CPU_GENERATION Returns the executing thread's processor generat= ion. +**/ +CPU_GENERATION +GetCpuGeneration ( + VOID + ) +{ + EFI_CPUID_REGISTER Cpuid; + CPU_FAMILY CpuFamilyModel; + CPU_GENERATION CpuGeneration; + + CpuGeneration =3D EnumCflCpu; + /// + /// Read the CPUID information + /// + AsmCpuid (CPUID_VERSION_INFO, &Cpuid.RegEax, &Cpuid.RegEbx, &Cpuid.RegEc= x, &Cpuid.RegEdx); + CpuFamilyModel =3D (CPU_FAMILY) (Cpuid.RegEax & CPUID_FULL_FAMILY_MODEL); + + switch (CpuFamilyModel) { + case EnumCpuCflUltUlx: + case EnumCpuCflDtHalo: + CpuGeneration =3D EnumCflCpu; + break; + + default: + CpuGeneration =3D EnumCpuUnknownGeneration; + ASSERT (FALSE); + break; + } + + return CpuGeneration; +} + +/** + Is Whiskey Lake CPU. + + @retval TRUE The CPUID corresponds with a Whiskey Lake CPU + @retval FALSE The CPUID does not correspond with a Whiskey Lake CPU +**/ +BOOLEAN +IsWhlCpu ( + VOID + ) +{ + CPU_FAMILY CpuFamily; + CPU_STEPPING CpuStepping; + + CpuFamily =3D GetCpuFamily (); + CpuStepping =3D GetCpuStepping (); + + // + // Check if it is Whiskey Lake CPU + // + if ((CpuFamily =3D=3D EnumCpuCflUltUlx) && ((CpuStepping =3D=3D EnumCflW= 0) || (CpuStepping =3D=3D EnumCflV0))) { + return TRUE; + } + + return FALSE; +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45892): https://edk2.groups.io/g/devel/message/45892 Mute This Topic: https://groups.io/mt/32918184/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45893+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45893+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001015; cv=none; d=zoho.com; s=zohoarc; b=WMwU226//EffoQZV8ePDxzFZn0/xA6gLbdwV4zMZD5n9CYnDaVHrT9QUhqgkJ+wPZ5SBZwaznJqcWJPQtJ2w/Otgjnz61BuYCB3kqSm9IPNga+iah4rNDlOHEdMqMpI0VC0Sc0hqaFiHlsg9eDqnEk3TY7IoWY9+izEnE6SwQ+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001015; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=KPydHxQmXqMMwvTzpjF1jpjL9cwd5QZC6HtYdgrgDNc=; b=R+oBuD4EosDWs9C6mAwxl6AhZpIv+u+yqUlqpKbp0BVu230XrsBpMrzB76Hvm46EF70i6avSa3tjQcexbAsBinSWbiVAZbGE5Wplomwo31n4OjoWInU65WflG1FD5EmB2F0BTgU6KvEgdhxjjn+KArll1UBdEZjEij6NQEgUEcE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45893+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001015745781.9345324531279; Fri, 16 Aug 2019 17:16:55 -0700 (PDT) Return-Path: X-Received: from mga04.intel.com (mga04.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:53 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319274" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:52 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 16/37] CoffeelakeSiliconPkg/Me: Add library instances Date: Fri, 16 Aug 2019 17:15:42 -0700 Message-Id: <20190817001603.30632-17-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001015; bh=do6Nt7DGqqn4y2PKc5/LJXU0R+z/SRwpaFwYxWf9qag=; h=Cc:Date:From:Reply-To:Subject:To; b=b4WqT53JV3cFhTaNrOhmBOw+BYxRak2s526mNkyInJrUwtqJVEx+Ul5rZIYt38oTjF1 Fnr/qpax4YelAqievTg/PXXEQSbohm0DOhaZGcvYKMtSIa+oe64UevQIyJDpX04bvk+lq s0ZHAF0yo/RCYlF2FizU2pCxyhc6J7xM8xM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds ME library class instances. * PeiMePolicyLib - PEI ME policy configuration services. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi= b.inf | 44 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi= brary.h | 25 ++ Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePolicyLi= b.c | 251 ++++++++++++++++++++ 3 files changed, 320 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/P= eiMePolicyLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePoli= cyLib/PeiMePolicyLib.inf new file mode 100644 index 0000000000..85a227f950 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePol= icyLib.inf @@ -0,0 +1,44 @@ +## @file +# Component description file for the PeiMePolicyLib libbrary. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiMePolicyLib +FILE_GUID =3D 2655FA94-4559-F393-B0B1-85A8E79C1532 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D PeiMePolicyLib + + +[LibraryClasses] +DebugLib +IoLib +PeiServicesLib +BaseMemoryLib +MemoryAllocationLib +ConfigBlockLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +PeiMePolicyLib.c +PeiMePolicyLibrary.h + + +[Ppis] +gSiPolicyPpiGuid ## PRODUCES +gSiPreMemPolicyPpiGuid ## PRODUCES + + +[Guids] +gMePeiPreMemConfigGuid +gMePeiConfigGuid diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/P= eiMePolicyLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePo= licyLib/PeiMePolicyLibrary.h new file mode 100644 index 0000000000..3ac6a639e9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePol= icyLibrary.h @@ -0,0 +1,25 @@ +/** @file + Header file for the PeiMePolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_ME_POLICY_LIBRARY_H_ +#define _PEI_ME_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif // _PEI_ME_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/P= eiMePolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicy= Lib/PeiMePolicyLib.c new file mode 100644 index 0000000000..6f3d70b841 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Me/Library/PeiMePolicyLib/PeiMePol= icyLib.c @@ -0,0 +1,251 @@ +/** @file + This file is PeiMePolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiMePolicyLibrary.h" + +/** + Load default settings for ME config block in pre-mem phase. + + @param[in] ConfigBlockPointer The pointer to the config = block +**/ +VOID +LoadMePeiPreMemDefault ( + IN VOID *ConfigBlockPointer + ); + +/** + Load default settings for ME config block in PEI phase. + + @param[in] ConfigBlockPointer The pointer to the config = block +**/ +VOID +LoadMePeiDefault ( + IN VOID *ConfigBlockPointer + ); + +STATIC COMPONENT_BLOCK_ENTRY mMeCompontBlockPreMemBlocks [] =3D { + {&gMePeiPreMemConfigGuid, sizeof (ME_PEI_PREMEM_CONFIG), ME_PEI_PREMEM_= CONFIG_REVISION, LoadMePeiPreMemDefault} +}; + +STATIC COMPONENT_BLOCK_ENTRY mMeCompontBlockBlocks [] =3D { + {&gMePeiConfigGuid, sizeof (ME_PEI_CONFIG), ME_PEI_CONFIG_= REVISION, LoadMePeiDefault} +}; + +/** + Load default settings for ME config block in pre-mem phase. + + @param[in] ConfigBlockPointer The pointer to the config = block +**/ +VOID +LoadMePeiPreMemDefault ( + IN VOID *ConfigBlockPointer + ) +{ + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; + MePeiPreMemConfig =3D ConfigBlockPointer; + + MePeiPreMemConfig->HeciTimeouts =3D 1; + + MePeiPreMemConfig->Heci1BarAddress =3D 0xFED1A000; + MePeiPreMemConfig->Heci2BarAddress =3D 0xFED1B000; + MePeiPreMemConfig->Heci3BarAddress =3D 0xFED1C000; + + // + // Test policies + // + MePeiPreMemConfig->SendDidMsg =3D 1; + + MePeiPreMemConfig->KtDeviceEnable =3D 1; +} + +/** + Load default settings for ME config block in PEI phase. + + @param[in] ConfigBlockPointer The pointer to the config = block +**/ +VOID +LoadMePeiDefault ( + IN VOID *ConfigBlockPointer + ) +{ + ME_PEI_CONFIG *MePeiConfig; + MePeiConfig =3D ConfigBlockPointer; + + MePeiConfig->EndOfPostMessage =3D EOP_SEND_IN_DXE; + MePeiConfig->MeUnconfigOnRtcClear =3D 1; +} + +/** + Dump values of ME config block in pre-mem phase. + + @param[in] MePeiPreMemConfig The pointer to the conf= ig block +**/ +VOID +EFIAPI +PrintMePeiPreMemConfig ( + IN ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig + ) +{ + DEBUG_CODE_BEGIN (); + DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_PREMEM_CONFIG -----= ------------\n")); + DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiPreMemCo= nfig->Header.Revision)); + ASSERT (MePeiPreMemConfig->Header.Revision =3D=3D ME_PEI_PREMEM_CONFIG_R= EVISION); + + DEBUG ((DEBUG_INFO, " HeciTimeouts : 0x%x\n", MePeiPreMemCo= nfig->HeciTimeouts)); + DEBUG ((DEBUG_INFO, " DidInitStat : 0x%x\n", MePeiPreMemCo= nfig->DidInitStat)); + DEBUG ((DEBUG_INFO, " DisableCpuReplacedPolling : 0x%x\n", MePeiPreMemCo= nfig->DisableCpuReplacedPolling)); + DEBUG ((DEBUG_INFO, " SendDidMsg : 0x%x\n", MePeiPreMemCo= nfig->SendDidMsg)); + DEBUG ((DEBUG_INFO, " DisableHeciRetry : 0x%x\n", MePeiPreMemCo= nfig->DisableHeciRetry)); + DEBUG ((DEBUG_INFO, " DisableMessageCheck : 0x%x\n", MePeiPreMemCo= nfig->DisableMessageCheck)); + DEBUG ((DEBUG_INFO, " SkipMbpHob : 0x%x\n", MePeiPreMemCo= nfig->SkipMbpHob)); + DEBUG ((DEBUG_INFO, " HeciCommunication2 : 0x%x\n", MePeiPreMemCo= nfig->HeciCommunication2)); + DEBUG ((DEBUG_INFO, " KtDeviceEnable : 0x%x\n", MePeiPreMemCo= nfig->KtDeviceEnable)); + DEBUG ((DEBUG_INFO, " Heci1BarAddress : 0x%x\n", MePeiPreMemCo= nfig->Heci1BarAddress)); + DEBUG ((DEBUG_INFO, " Heci2BarAddress : 0x%x\n", MePeiPreMemCo= nfig->Heci2BarAddress)); + DEBUG ((DEBUG_INFO, " Heci3BarAddress : 0x%x\n", MePeiPreMemCo= nfig->Heci3BarAddress)); + DEBUG_CODE_END (); +} + +/** + Dump values of ME config block in PEI phase. + + @param[in] MePeiConfig The pointer to the config block +**/ +VOID +EFIAPI +PrintMePeiConfig ( + IN ME_PEI_CONFIG *MePeiConfig + ) +{ + DEBUG_CODE_BEGIN (); + DEBUG ((DEBUG_INFO, "------------------------ ME_PEI_CONFIG ------------= -----\n")); + DEBUG ((DEBUG_INFO, " Revision : 0x%x\n", MePeiConfig->= Header.Revision)); + ASSERT (MePeiConfig->Header.Revision =3D=3D ME_PEI_CONFIG_REVISION); + + DEBUG ((DEBUG_INFO, " MctpBroadcastCycle : 0x%x\n", MePeiConfig->= MctpBroadcastCycle)); + DEBUG ((DEBUG_INFO, " EndOfPostMessage : 0x%x\n", MePeiConfig->= EndOfPostMessage)); + DEBUG ((DEBUG_INFO, " Heci3Enabled : 0x%x\n", MePeiConfig->= Heci3Enabled)); + DEBUG ((DEBUG_INFO, " DisableD0I3SettingForHeci : 0x%x\n", MePeiConfig->= DisableD0I3SettingForHeci)); + DEBUG ((DEBUG_INFO, " MeUnconfigOnRtcClear : 0x%x\n", MePeiConfig->= MeUnconfigOnRtcClear)); + + DEBUG_CODE_END (); +} + +/** + Print PEI ME config block + + @param[in] SiPolicyPpiPreMem The RC Policy PPI instance +**/ +VOID +EFIAPI +MePrintPolicyPpiPreMem ( + IN SI_PREMEM_POLICY_PPI *SiPolicyPpiPreMem + ) +{ + DEBUG_CODE_BEGIN (); + EFI_STATUS Status; + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpiPreMem, &gMePeiPreMemConf= igGuid, (VOID *) &MePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "\n---------------------- Me Config Block Pre-Mem Pr= int Begin -----------------\n")); + PrintMePeiPreMemConfig (MePeiPreMemConfig); + DEBUG ((DEBUG_INFO, "\n---------------------- Me Config Block Pre-Mem Pr= int End -------------------\n")); + DEBUG_CODE_END (); +} + +/** + Print PEI ME config block + + @param[in] SiPolicyPpi The RC Policy PPI instance +**/ +VOID +EFIAPI +MePrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ) +{ + DEBUG_CODE_BEGIN (); + EFI_STATUS Status; + ME_PEI_CONFIG *MePeiConfig; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI= D *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "\n---------------------- Me Config Block Print Begi= n -----------------\n")); + PrintMePeiConfig (MePeiConfig); + DEBUG ((DEBUG_INFO, "\n---------------------- Me Config Block Print End = -------------------\n")); + DEBUG_CODE_END (); +} + +/** + Get ME config block table total size. + + @retval Size of ME config block table +**/ +UINT16 +EFIAPI +MeGetConfigBlockTotalSizePreMem ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mMeCompontBlockPreMemBlocks[0]= , sizeof (mMeCompontBlockPreMemBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + Get ME config block table total size. + + @retval Size of ME config block table +**/ +UINT16 +EFIAPI +MeGetConfigBlockTotalSize ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mMeCompontBlockBlocks[0], size= of (mMeCompontBlockBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + MeAddConfigBlocksPreMem add all config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +MeAddConfigBlocksPreMem ( + IN VOID *ConfigBlockTableAddress + ) +{ + DEBUG ((DEBUG_INFO, "Me AddConfigBlocks. TotalBlockCount =3D 0x%x\n", s= izeof (mMeCompontBlockPreMemBlocks) / sizeof (COMPONENT_BLOCK_ENTRY))); + + return AddComponentConfigBlocks (ConfigBlockTableAddress, &mMeCompontBlo= ckPreMemBlocks[0], sizeof (mMeCompontBlockPreMemBlocks) / sizeof (COMPONENT= _BLOCK_ENTRY)); +} + +/** + MeAddConfigBlocks add all config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +MeAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + DEBUG ((DEBUG_INFO, "ME AddConfigBlocks. TotalBlockCount =3D 0x%x\n", s= izeof (mMeCompontBlockBlocks) / sizeof (COMPONENT_BLOCK_ENTRY))); + + return AddComponentConfigBlocks (ConfigBlockTableAddress, &mMeCompontBlo= ckBlocks[0], sizeof (mMeCompontBlockBlocks) / sizeof (COMPONENT_BLOCK_ENTRY= )); +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45893): https://edk2.groups.io/g/devel/message/45893 Mute This Topic: https://groups.io/mt/32918185/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45894+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45894+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001016; cv=none; d=zoho.com; s=zohoarc; b=okpbQ+dEK/dMVhMv8/Uj9zeBQdPwtC1Dh2YJd8TRTd+BjlIk1N2LyhO+C5O4NmedOE3kVkk9SWQa7ygx2GXKQFMUU9PPjANt+brD3rJGfEDVCnQGXsdDyqGSFpV0LKaAw8Mrl4fzhlSHTuLs0pDsknsFUF+9PvG204r6yP6P33g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001016; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=gDt/bHyJdnE4kvMmehA2ULSYoiYo8HId8+35loyUyNs=; b=ab/bZkvI6kgImcs3GLw/e9hapLYrYZ6efQOVB5HyEwd3dh9CM32prIzdiRYwlLCG7fkFQfUkLu3dVc5INdqQZPF3cIgHq1VkSGvSguDkEhCQSTGLbFLMUoHMdnt/fcSSTnT5a8euJpUQlgDbFeRFb40Tkxfk9P4UgVOp70dcwZE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45894+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001016097224.4896886529217; Fri, 16 Aug 2019 17:16:56 -0700 (PDT) Return-Path: X-Received: from mga04.intel.com (mga04.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:53 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319279" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:52 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 17/37] CoffeelakeSiliconPkg/Pch: Add Base library instances Date: Fri, 16 Aug 2019 17:15:43 -0700 Message-Id: <20190817001603.30632-18-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001015; bh=e8iGEYOfVgRobMO3GkVpCDj8THa4WFAf42Yqf5i/huM=; h=Cc:Date:From:Reply-To:Subject:To; b=d6BdDxN/tgCrl8wDGcCYhGppzI0ofPS32HbGUxL0SLje4SdA0b0zUceoWP3+4MpfYql D9cAESPKI1HOCkwzw6YAEV7G/AOv2CoJFx2BD8xjbLd6HfGkdYKFORN6Aeo+UR1PKOtwI HYJD/ql4kbG40wBkOfklKcFrHTf8I3pgWKk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds PCH Base library class instances. * BaseResetSystemLib * BaseSmbusLib Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRese= tSystemLib.inf | 38 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.i= nf | 39 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseRese= tSystemLib.c | 153 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbusLib.c= | 993 ++++++++++++++++++++ 4 files changed, 1223 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystem= Lib/BaseResetSystemLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library= /BaseResetSystemLib/BaseResetSystemLib.inf new file mode 100644 index 0000000000..8d68f2dd83 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/Bas= eResetSystemLib.inf @@ -0,0 +1,38 @@ +## @file +# Component description file for Intel Ich7 Reset System Library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseResetSystemLib +FILE_GUID =3D D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +UEFI_SPECIFICATION_VERSION =3D 2.00 +LIBRARY_CLASS =3D ResetSystemLib +CONSTRUCTOR =3D BaseResetSystemLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +IoLib +DebugLib +PmcLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +BaseResetSystemLib.c + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/Ba= seSmbusLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLi= b/BaseSmbusLib.inf new file mode 100644 index 0000000000..f3388a2624 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbus= Lib.inf @@ -0,0 +1,39 @@ +## @file +# Component description file for PCH Smbus Library. +# +# SMBUS Library that layers on top of the I/O Library to directly +# access a standard SMBUS host controller. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseSmbusLib +FILE_GUID =3D 5C4D0430-F81B-42D3-BB88-4A6CD2796FF8 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D SmbusLib +CONSTRUCTOR =3D BaseSmbusLibConstructor + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] +BaseLib +DebugLib +IoLib +PciSegmentLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +BaseSmbusLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystem= Lib/BaseResetSystemLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/B= aseResetSystemLib/BaseResetSystemLib.c new file mode 100644 index 0000000000..a603f5e794 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseResetSystemLib/Bas= eResetSystemLib.c @@ -0,0 +1,153 @@ +/** @file + System reset library services. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mBaseResetSystemABase; + +/** + Calling this function causes a system-wide reset. This sets + all circuitry within the system to its initial state. This type of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + System reset should not return, if it returns, it means the system does + not support cold reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes a system-wide initialization. The processors + are set to their initial state, and pending cycles are not corrupted. + + System reset should not return, if it returns, it means the system does + not support warm reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET); +} + +/** + Calling this function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + System shutdown should not return, if it returns, it means the system do= es + not support shut down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + UINT16 ABase; + UINT32 Data32; + + ABase =3D mBaseResetSystemABase; + if (ABase =3D=3D 0) { + ABase =3D PmcGetAcpiBase (); + } + /// + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the s= ystem from S5 + /// + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0); + + /// + /// Secondly, PwrSts register must be cleared + /// + /// Write a "1" to bit[8] of power button status register at + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit + /// + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PWRBTN); + + /// + /// Finally, transform system into S5 sleep state + /// + Data32 =3D IoRead32 (ABase + R_ACPI_IO_PM1_CNT); + + Data32 =3D (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP + B_ACPI_IO_PM= 1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5); + + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32); + + Data32 =3D Data32 | B_ACPI_IO_PM1_CNT_SLP_EN; + + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32); + + return; +} + +/** + Calling this function causes the system to enter a power state for platf= orm specific. + + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes the system to enter a power state for capsu= le update. + + Reset update should not return, if it returns, it means the system does + not support capsule update. + +**/ +VOID +EFIAPI +EnterS3WithImmediateWake ( + VOID + ) +{ + ASSERT (FALSE); +} + +/** + The library constructuor. + + The function does the necessary initialization work for this library ins= tance. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. +**/ +EFI_STATUS +EFIAPI +BaseResetSystemLibConstructor ( + VOID + ) +{ + mBaseResetSystemABase =3D PmcGetAcpiBase (); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/Ba= seSmbusLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/= BaseSmbusLib.c new file mode 100644 index 0000000000..3d6386d433 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/BaseSmbusLib/BaseSmbus= Lib.c @@ -0,0 +1,993 @@ +/** @file + PCH SMBUS library implementation built upon I/O library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mSmbusIoBase =3D 0; + +/** + Gets Io port base address of Smbus Host Controller. + + @retval The Io port base address of Smbus host controller. + +**/ +UINT16 +InternalGetSmbusIoPortBaseAddress ( + VOID + ) +{ + UINT64 SmbusPciBase; + UINT16 IoPortBaseAddress; + + if (mSmbusIoBase !=3D 0) { + return mSmbusIoBase; + } + + SmbusPciBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SMBUS, + PCI_FUNCTION_NUMBER_PCH_SMBUS, + 0 + ); + IoPortBaseAddress =3D (UINT16) PciSegmentRead32 (SmbusPciBase + R_SMBUS_= CFG_BASE); + + // + // Make sure that the IO port base address has been properly set. + // + if ((IoPortBaseAddress =3D=3D 0) || (IoPortBaseAddress =3D=3D 0xFFFF)) { + ASSERT (FALSE); + return 0; + } + + IoPortBaseAddress &=3D B_SMBUS_CFG_BASE_BAR; + mSmbusIoBase =3D IoPortBaseAddress; + + return IoPortBaseAddress; +} + + +/** + Acquires the ownership of SMBUS. + + This internal function reads the host state register. + If the SMBUS is not available, RETURN_TIMEOUT is returned; + Otherwise, it performs some basic initializations and returns + RETURN_SUCCESS. + + @param[in] IoPortBaseAddress The Io port base address of Smbus Host con= troller. + + @retval RETURN_SUCCESS The SMBUS command was executed successfull= y. + @retval RETURN_TIMEOUT A timeout occurred while executing the SMB= US command. + +**/ +RETURN_STATUS +InternalSmBusAcquire ( + IN UINT16 IoPortBaseAddress + ) +{ + UINT8 HostStatus; + + HostStatus =3D IoRead8 (IoPortBaseAddress + R_SMBUS_IO_HSTS); + if ((HostStatus & B_SMBUS_IO_IUS) !=3D 0) { + return RETURN_TIMEOUT; + } else if ((HostStatus & B_SMBUS_IO_HBSY) !=3D 0) { + // + // Clear host status register and exit. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HSTS, B_SMBUS_IO_HSTS_ALL); + return RETURN_TIMEOUT; + } + // + // Clear out any odd status information (Will Not Clear In Use). + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HSTS, HostStatus); + + return RETURN_SUCCESS; +} + +/** + Starts the SMBUS transaction and waits until the end. + + This internal function start the SMBUS transaction and waits until the t= ransaction + of SMBUS is over by polling the INTR bit of Host status register. + If the SMBUS is not available, RETURN_TIMEOUT is returned; + Otherwise, it performs some basic initializations and returns + RETURN_SUCCESS. + + @param[in] IoPortBaseAddress The Io port base address of Smbus Host c= ontroller. + @param[in] HostControl The Host control command to start SMBUS = transaction. + + @retval RETURN_SUCCESS The SMBUS command was executed successfu= lly. + @retval RETURN_CRC_ERROR The checksum is not correct (PEC is inco= rrect). + @retval RETURN_DEVICE_ERROR The request was not completed because a = failure reflected + in the Host Status Register bit. Device= errors are + a result of a transaction collision, ill= egal command field, + unclaimed cycle (host initiated), or bus= errors (collisions). + +**/ +RETURN_STATUS +InternalSmBusStart ( + IN UINT16 IoPortBaseAddress, + IN UINT8 HostControl + ) +{ + UINT8 HostStatus; + UINT8 AuxiliaryStatus; + + // + // Set Host Control Register (Initiate Operation, Interrupt disabled). + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HCTL, (UINT8)(HostControl + B_S= MBUS_IO_START)); + + do { + // + // Poll INTR bit of Host Status Register. + // + HostStatus =3D IoRead8 (IoPortBaseAddress + R_SMBUS_IO_HSTS); + } while ((HostStatus & (B_SMBUS_IO_INTR | B_SMBUS_IO_ERROR | B_SMBUS_IO_= BYTE_DONE_STS)) =3D=3D 0); + + if ((HostStatus & B_SMBUS_IO_ERROR) =3D=3D 0) { + return RETURN_SUCCESS; + } + // + // Clear error bits of Host Status Register. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HSTS, B_SMBUS_IO_ERROR); + // + // Read Auxiliary Status Register to judge CRC error. + // + AuxiliaryStatus =3D IoRead8 (IoPortBaseAddress + R_SMBUS_IO_AUXS); + if ((AuxiliaryStatus & B_SMBUS_IO_CRCE) !=3D 0) { + return RETURN_CRC_ERROR; + } + + return RETURN_DEVICE_ERROR; +} + +/** + Executes an SMBUS quick, byte or word command. + + This internal function executes an SMBUS quick, byte or word commond. + If Status is not NULL, then the status of the executed command is return= ed in Status. + + @param[in] HostControl The value of Host Control Register to set. + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The byte/word write to the SMBUS. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NUL= L. + + @retval The byte/word read from the SMBUS. + +**/ +UINT16 +InternalSmBusNonBlock ( + IN UINT8 HostControl, + IN UINTN SmBusAddress, + IN UINT16 Value, + OUT RETURN_STATUS *Status + ) +{ + RETURN_STATUS ReturnStatus; + UINT16 IoPortBaseAddress; + UINT8 AuxiliaryControl; + + IoPortBaseAddress =3D InternalGetSmbusIoPortBaseAddress (); + + // + // Try to acquire the ownership of SMBUS. + // + ReturnStatus =3D InternalSmBusAcquire (IoPortBaseAddress); + if (RETURN_ERROR (ReturnStatus)) { + goto Done; + } + // + // Set the appropriate Host Control Register and auxiliary Control Regis= ter. + // + AuxiliaryControl =3D 0; + if (SMBUS_LIB_PEC (SmBusAddress)) { + AuxiliaryControl |=3D B_SMBUS_IO_AAC; + } + // + // Set Host Commond Register. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HCMD, (UINT8) SMBUS_LIB_COMMAND= (SmBusAddress)); + // + // Write value to Host Data 0 and Host Data 1 Registers. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HD0, (UINT8) Value); + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HD1, (UINT8) (Value >> 8)); + // + // Set Auxiliary Control Regiester. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_AUXC, AuxiliaryControl); + // + // Set SMBUS slave address for the device to send/receive from. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_TSA, (UINT8) SmBusAddress); + // + // Start the SMBUS transaction and wait for the end. + // + ReturnStatus =3D InternalSmBusStart (IoPortBaseAddress, HostControl); + // + // Read value from Host Data 0 and Host Data 1 Registers. + // + Value =3D (UINT16)(IoRead8 (IoPortBaseAddress + R_SMBUS_IO_HD1) << 8); + Value =3D (UINT16)(Value | IoRead8 (IoPortBaseAddress + R_SMBUS_IO_HD0)); + // + // Clear Host Status Register and Auxiliary Status Register. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HSTS, B_SMBUS_IO_HSTS_ALL); + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_AUXS, B_SMBUS_IO_CRCE); + +Done: + if (Status !=3D NULL) { + *Status =3D ReturnStatus; + } + + return Value; +} + +/** + Executes an SMBUS quick read command. + + Executes an SMBUS quick read command on the SMBUS device specified by Sm= BusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If PEC is set in SmBusAddress, then ASSERT(). + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + +**/ +VOID +EFIAPI +SmBusQuickRead ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (!SMBUS_LIB_PEC (SmBusAddress)); + ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if (SMBUS_LIB_PEC (SmBusAddress) || + (SMBUS_LIB_COMMAND (SmBusAddress) !=3D 0) || + (SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return; + } + + InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_QUICK, + SmBusAddress | B_SMBUS_IO_READ, + 0, + Status + ); +} + +/** + Executes an SMBUS quick write command. + + Executes an SMBUS quick write command on the SMBUS device specified by S= mBusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If PEC is set in SmBusAddress, then ASSERT(). + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + +**/ +VOID +EFIAPI +SmBusQuickWrite ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (!SMBUS_LIB_PEC (SmBusAddress)); + ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if (SMBUS_LIB_PEC (SmBusAddress) || + (SMBUS_LIB_COMMAND (SmBusAddress) !=3D 0) || + (SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return; + } + + InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_QUICK, + SmBusAddress | B_SMBUS_IO_WRITE, + 0, + Status + ); +} + +/** + Executes an SMBUS receive byte command. + + Executes an SMBUS receive byte command on the SMBUS device specified by = SmBusAddress. + Only the SMBUS slave address field of SmBusAddress is required. + The byte received from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The byte received from the SMBUS. + +**/ +UINT8 +EFIAPI +SmBusReceiveByte ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((SMBUS_LIB_COMMAND (SmBusAddress) !=3D 0) || + (SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return (UINT8) InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_BYTE, + SmBusAddress | B_SMBUS_IO_READ, + 0, + Status + ); +} + +/** + Executes an SMBUS send byte command. + + Executes an SMBUS send byte command on the SMBUS device specified by SmB= usAddress. + The byte specified by Value is sent. + Only the SMBUS slave address field of SmBusAddress is required. Value i= s returned. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If Command in SmBusAddress is not zero, then ASSERT(). + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The 8-bit value to send. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The parameter of Value. + +**/ +UINT8 +EFIAPI +SmBusSendByte ( + IN UINTN SmBusAddress, + IN UINT8 Value, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (SMBUS_LIB_COMMAND (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((SMBUS_LIB_COMMAND (SmBusAddress) !=3D 0) || + (SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return (UINT8) InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_BYTE, + SmBusAddress | B_SMBUS_IO_WRITE, + Value, + Status + ); +} + +/** + Executes an SMBUS read data byte command. + + Executes an SMBUS read data byte command on the SMBUS device specified b= y SmBusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress ar= e required. + The 8-bit value read from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NUL= L. + + @retval The byte read from the SMBUS. + +**/ +UINT8 +EFIAPI +SmBusReadDataByte ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return (UINT8) InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_BYTE_DATA, + SmBusAddress | B_SMBUS_IO_READ, + 0, + Status + ); +} + +/** + Executes an SMBUS write data byte command. + + Executes an SMBUS write data byte command on the SMBUS device specified = by SmBusAddress. + The 8-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress ar= e required. + Value is returned. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The 8-bit value to write. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The parameter of Value. + +**/ +UINT8 +EFIAPI +SmBusWriteDataByte ( + IN UINTN SmBusAddress, + IN UINT8 Value, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return (UINT8) InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_BYTE_DATA, + SmBusAddress | B_SMBUS_IO_WRITE, + Value, + Status + ); +} + +/** + Executes an SMBUS read data word command. + + Executes an SMBUS read data word command on the SMBUS device specified b= y SmBusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress ar= e required. + The 16-bit value read from the SMBUS is returned. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The byte read from the SMBUS. + +**/ +UINT16 +EFIAPI +SmBusReadDataWord ( + IN UINTN SmBusAddress, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_WORD_DATA, + SmBusAddress | B_SMBUS_IO_READ, + 0, + Status + ); +} + +/** + Executes an SMBUS write data word command. + + Executes an SMBUS write data word command on the SMBUS device specified = by SmBusAddress. + The 16-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress ar= e required. + Value is returned. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The 16-bit value to write. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The parameter of Value. + +**/ +UINT16 +EFIAPI +SmBusWriteDataWord ( + IN UINTN SmBusAddress, + IN UINT16 Value, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_WORD_DATA, + SmBusAddress | B_SMBUS_IO_WRITE, + Value, + Status + ); +} + +/** + Executes an SMBUS process call command. + + Executes an SMBUS process call command on the SMBUS device specified by = SmBusAddress. + The 16-bit value specified by Value is written. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress ar= e required. + The 16-bit value returned by the process call command is returned. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If Length in SmBusAddress is not zero, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] Value The 16-bit value to write. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The 16-bit value returned by the process call command. + +**/ +UINT16 +EFIAPI +SmBusProcessCall ( + IN UINTN SmBusAddress, + IN UINT16 Value, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return InternalSmBusNonBlock ( + V_SMBUS_IO_SMB_CMD_PROCESS_CALL, + SmBusAddress | B_SMBUS_IO_WRITE, + Value, + Status + ); +} + +/** + Executes an SMBUS block command. + + Executes an SMBUS block read, block write and block write-block read com= mand + on the SMBUS device specified by SmBusAddress. + Bytes are read from the SMBUS and stored in Buffer. + The number of bytes read is returned, and will never return a value larg= er than 32-bytes. + If Status is not NULL, then the status of the executed command is return= ed in Status. + It is the caller's responsibility to make sure Buffer is large enough fo= r the total number of bytes read. + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not n= eed to be any larger than 32 bytes. + + @param[in] HostControl The value of Host Control Register to set. + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] WriteBuffer Pointer to the buffer of bytes to write to t= he SMBUS. + @param[out] ReadBuffer Pointer to the buffer of bytes to read from = the SMBUS. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NUL= L. + + @retval The number of bytes read from the SMBUS. + +**/ +UINTN +InternalSmBusBlock ( + IN UINT8 HostControl, + IN UINTN SmBusAddress, + IN UINT8 *WriteBuffer, + OUT UINT8 *ReadBuffer, + OUT RETURN_STATUS *Status + ) +{ + RETURN_STATUS ReturnStatus; + UINTN Index; + UINTN BytesCount; + UINT16 IoPortBaseAddress; + UINT8 AuxiliaryControl; + + IoPortBaseAddress =3D InternalGetSmbusIoPortBaseAddress (); + + BytesCount =3D SMBUS_LIB_LENGTH (SmBusAddress); + + // + // Try to acquire the ownership of SMBUS. + // + ReturnStatus =3D InternalSmBusAcquire (IoPortBaseAddress); + if (RETURN_ERROR (ReturnStatus)) { + goto Done; + } + // + // Set the appropriate Host Control Register and auxiliary Control Regis= ter. + // + AuxiliaryControl =3D B_SMBUS_IO_E32B; + if (SMBUS_LIB_PEC (SmBusAddress)) { + AuxiliaryControl |=3D B_SMBUS_IO_AAC; + } + // + // Set Host Command Register. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HCMD, (UINT8) SMBUS_LIB_COMMAND= (SmBusAddress)); + // + // Set Auxiliary Control Regiester. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_AUXC, AuxiliaryControl); + // + // Clear byte pointer of 32-byte buffer. + // + IoRead8 (IoPortBaseAddress + R_SMBUS_IO_HCTL); + + if (WriteBuffer !=3D NULL) { + // + // Write the number of block to Host Block Data Byte Register. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HD0, (UINT8) BytesCount); + // + // Write data block to Host Block Data Register. + // + for (Index =3D 0; Index < BytesCount; Index++) { + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HBD, WriteBuffer[Index]); + } + } + // + // Set SMBUS slave address for the device to send/receive from. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_TSA, (UINT8) SmBusAddress); + // + // Start the SMBUS transaction and wait for the end. + // + ReturnStatus =3D InternalSmBusStart (IoPortBaseAddress, HostControl); + if (RETURN_ERROR (ReturnStatus)) { + goto Done; + } + + if (ReadBuffer !=3D NULL) { + // + // Read the number of block from host block data byte register. + // + BytesCount =3D IoRead8 (IoPortBaseAddress + R_SMBUS_IO_HD0); + // + // Write data block from Host Block Data Register. + // + for (Index =3D 0; Index < BytesCount; Index++) { + ReadBuffer[Index] =3D IoRead8 (IoPortBaseAddress + R_SMBUS_IO_HBD); + } + } + +Done: + // + // Clear Host Status Register and Auxiliary Status Register. + // + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_HSTS, B_SMBUS_IO_HSTS_ALL); + IoWrite8 (IoPortBaseAddress + R_SMBUS_IO_AUXS, B_SMBUS_IO_CRCE); + + if (Status !=3D NULL) { + *Status =3D ReturnStatus; + } + + return BytesCount; +} + +/** + Executes an SMBUS read block command. + + Executes an SMBUS read block command on the SMBUS device specified by Sm= BusAddress. + Only the SMBUS slave address and SMBUS command fields of SmBusAddress ar= e required. + Bytes are read from the SMBUS and stored in Buffer. + The number of bytes read is returned, and will never return a value larg= er than 32-bytes. + If Status is not NULL, then the status of the executed command is return= ed in Status. + It is the caller's responsibility to make sure Buffer is large enough fo= r the total number of bytes read. + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not n= eed to be any larger than 32 bytes. + If Length in SmBusAddress is not zero, then ASSERT(). + If Buffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Buffer Pointer to the buffer to store the bytes read = from the SMBUS. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The number of bytes read. + +**/ +UINTN +EFIAPI +SmBusReadBlock ( + IN UINTN SmBusAddress, + OUT VOID *Buffer, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (Buffer !=3D NULL); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((Buffer =3D=3D NULL) || + (SMBUS_LIB_LENGTH (SmBusAddress) !=3D 0) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return InternalSmBusBlock ( + V_SMBUS_IO_SMB_CMD_BLOCK, + SmBusAddress | B_SMBUS_IO_READ, + NULL, + Buffer, + Status + ); +} + +/** + Executes an SMBUS write block command. + + Executes an SMBUS write block command on the SMBUS device specified by S= mBusAddress. + The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBus= Address are required. + Bytes are written to the SMBUS from Buffer. + The number of bytes written is returned, and will never return a value l= arger than 32-bytes. + If Status is not NULL, then the status of the executed command is return= ed in Status. + If Length in SmBusAddress is zero or greater than 32, then ASSERT(). + If Buffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[out] Buffer Pointer to the buffer to store the bytes read = from the SMBUS. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The number of bytes written. + +**/ +UINTN +EFIAPI +SmBusWriteBlock ( + IN UINTN SmBusAddress, + OUT VOID *Buffer, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (Buffer !=3D NULL); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >=3D 1); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <=3D 32); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((Buffer =3D=3D NULL) || + (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0) || + (SMBUS_LIB_LENGTH (SmBusAddress) > 32) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return InternalSmBusBlock ( + V_SMBUS_IO_SMB_CMD_BLOCK, + SmBusAddress | B_SMBUS_IO_WRITE, + Buffer, + NULL, + Status + ); +} + +/** + Executes an SMBUS block process call command. + + Executes an SMBUS block process call command on the SMBUS device specifi= ed by SmBusAddress. + The SMBUS slave address, SMBUS command, and SMBUS length fields of SmBus= Address are required. + Bytes are written to the SMBUS from WriteBuffer. Bytes are then read fr= om the SMBUS into ReadBuffer. + If Status is not NULL, then the status of the executed command is return= ed in Status. + It is the caller's responsibility to make sure ReadBuffer is large enoug= h for the total number of bytes read. + SMBUS supports a maximum transfer size of 32 bytes, so Buffer does not n= eed to be any larger than 32 bytes. + If Length in SmBusAddress is zero or greater than 32, then ASSERT(). + If WriteBuffer is NULL, then ASSERT(). + If ReadBuffer is NULL, then ASSERT(). + If any reserved bits of SmBusAddress are set, then ASSERT(). + + @param[in] SmBusAddress Address that encodes the SMBUS Slave Address, + SMBUS Command, SMBUS Data Length, and PEC. + @param[in] WriteBuffer Pointer to the buffer of bytes to write to the= SMBUS. + @param[out] ReadBuffer Pointer to the buffer of bytes to read from th= e SMBUS. + @param[out] Status Return status for the executed command. + This is an optional parameter and may be NULL. + + @retval The number of bytes written. + +**/ +UINTN +EFIAPI +SmBusBlockProcessCall ( + IN UINTN SmBusAddress, + IN VOID *WriteBuffer, + OUT VOID *ReadBuffer, + OUT RETURN_STATUS *Status OPTIONAL + ) +{ + ASSERT (WriteBuffer !=3D NULL); + ASSERT (ReadBuffer !=3D NULL); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) >=3D 1); + ASSERT (SMBUS_LIB_LENGTH (SmBusAddress) <=3D 32); + ASSERT (SMBUS_LIB_RESERVED (SmBusAddress) =3D=3D 0); + + if ((WriteBuffer =3D=3D NULL) || + (ReadBuffer =3D=3D NULL) || + (SMBUS_LIB_LENGTH (SmBusAddress) =3D=3D 0) || + (SMBUS_LIB_LENGTH (SmBusAddress) > 32) || + (SMBUS_LIB_RESERVED (SmBusAddress) !=3D 0)) + { + if (Status !=3D NULL) { + *Status =3D RETURN_INVALID_PARAMETER; + } + return 0; + } + + return InternalSmBusBlock ( + V_SMBUS_IO_SMB_CMD_BLOCK_PROCESS, + SmBusAddress | B_SMBUS_IO_WRITE, + WriteBuffer, + ReadBuffer, + Status + ); +} + +/** + The library constructuor. + + The function does the necessary initialization work for this library ins= tance. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. +**/ +RETURN_STATUS +EFIAPI +BaseSmbusLibConstructor ( + VOID + ) +{ + UINT64 SmbusPciBase; + UINT16 IoPortBaseAddress; + + // + // Init mSmbusIoBase variable. + // + SmbusPciBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SMBUS, + PCI_FUNCTION_NUMBER_PCH_SMBUS, + 0 + ); + IoPortBaseAddress =3D (UINT16) PciSegmentRead32 (SmbusPciBase + R_SMBUS_= CFG_BASE); + + if ((IoPortBaseAddress !=3D 0) && (IoPortBaseAddress !=3D 0xFFFF)) { + mSmbusIoBase =3D IoPortBaseAddress & B_SMBUS_CFG_BASE_BAR; + } + + return RETURN_SUCCESS; +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45894): https://edk2.groups.io/g/devel/message/45894 Mute This Topic: https://groups.io/mt/32918186/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45895+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45895+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001016; cv=none; d=zoho.com; s=zohoarc; b=CrLAhz1ZkTizlQPZ+gxCBE1RROro80W3aWKI5P+WGIEZ2ckmi4BrhDsONE57KmNH9ICOL15J+fDQpRoQWxtoJhqQ+fCzTG6d05NUM40E/fl9SEXPUGU5hdXaLiap2l7j7MTPKr3h6EL/AlT7AHYSRYGgkcnqpIJNvVqBaD3ZB3s= ARC-Message-Signature: i=1; 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16 Aug 2019 17:16:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319283" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:52 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 18/37] CoffeelakeSiliconPkg/Pch: Add DXE library instances Date: Fri, 16 Aug 2019 17:15:44 -0700 Message-Id: <20190817001603.30632-19-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001015; bh=7hQbpnCTsQJFYM9kAJDmZB1aS+GpEmFtkhss6/doygU=; h=Cc:Date:From:Reply-To:Subject:To; b=UE7wFu6KBIX2Au7Vv5ET3Fx4VL5bY/FVl/Xi5dcVPIgGO+cQLfCEB2uKFgBZqX1bFQO msbA9p3zDHznTGYxYCsBsnLdjN6tgfJTQek9rSix8GUKzFgI1vKN090cgTIZyfd6AZz/7 0tquXWbYOJUQc1BtK4xuGJel9D3P8ia0hfQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds PCH DXE library class instances. * DxePchPolicyLib * DxeResetSystemLib * DxeRuntimeResetSystemLib Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic= yLib.inf | 41 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetS= ystemLib.inf | 49 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/Dx= eRuntimeResetSystemLib.inf | 52 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolic= yLib.c | 218 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeResetS= ystemLib.c | 310 +++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemLib/Dx= eRuntimeResetSystemLib.c | 323 ++++++++++++++++++++ 6 files changed, 993 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib= /DxePchPolicyLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePc= hPolicyLib/DxePchPolicyLib.inf new file mode 100644 index 0000000000..8845ab796c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePch= PolicyLib.inf @@ -0,0 +1,41 @@ +## @file +# Component description file for the PeiPchPolicy library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxePchPolicyLib +FILE_GUID =3D E2179D04-7026-48A5-9475-309CEA2F21A3 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D DxePchPolicyLib + + +[LibraryClasses] +BaseMemoryLib +UefiBootServicesTableLib +DebugLib +ConfigBlockLib +SiConfigBlockLib +PchInfoLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +DxePchPolicyLib.c + + +[Guids] +gHdAudioDxeConfigGuid +gGpioDxeConfigGuid + +[Protocols] +gPchPolicyProtocolGuid ## PRODUCES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemL= ib/DxeResetSystemLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/D= xeResetSystemLib/DxeResetSystemLib.inf new file mode 100644 index 0000000000..0bb2d6e247 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeR= esetSystemLib.inf @@ -0,0 +1,49 @@ +## @file +# Component description file for Intel Ich7 Reset System Library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeResetSystemLib +FILE_GUID =3D 239383BC-499E-4DC5-8CDC-F85AF27B1BC4 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_DRIVER +UEFI_SPECIFICATION_VERSION =3D 2.00 +LIBRARY_CLASS =3D ResetSystemLib +CONSTRUCTOR =3D DxeResetSystemLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +IoLib +BaseLib +DebugLib +TimerLib +BaseMemoryLib +UefiBootServicesTableLib +PmcLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +DxeResetSystemLib.c + + +[Protocols] +gPchResetCallbackProtocolGuid ## CONSUMES + + +[Guids] +gPchGlobalResetGuid diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeReset= SystemLib/DxeRuntimeResetSystemLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg= /Pch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.inf new file mode 100644 index 0000000000..a1777293ab --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf @@ -0,0 +1,52 @@ +## @file +# Component description file for Intel Ich7 Reset System Library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeRuntimeResetSystemLib +FILE_GUID =3D 1026813A-E46F-43D1-B709-FF1F996F2E72 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_RUNTIME_DRIVER +UEFI_SPECIFICATION_VERSION =3D 2.00 +LIBRARY_CLASS =3D ResetSystemLib +CONSTRUCTOR =3D DxeRuntimeResetSystemLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +IoLib +BaseLib +DebugLib +TimerLib +BaseMemoryLib +UefiRuntimeLib +DxeServicesTableLib +UefiBootServicesTableLib +PmcLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +DxeRuntimeResetSystemLib.c + + +[Protocols] +gPchResetCallbackProtocolGuid ## CONSUMES + + +[Guids] +gPchGlobalResetGuid +gEfiEventVirtualAddressChangeGuid diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib= /DxePchPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchP= olicyLib/DxePchPolicyLib.c new file mode 100644 index 0000000000..62c8a91eb9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePch= PolicyLib.c @@ -0,0 +1,218 @@ +/** @file + This file provide services for DXE phase policy default initialization + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Load DXE Config block default for HD Audio + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadHdAudioDxeConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_HDAUDIO_DXE_CONFIG *HdAudioDxeConfig; + HdAudioDxeConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "HdaDxeConfig->Header.GuidHob.Name =3D %g\n", &HdAud= ioDxeConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "HdaDxeConfig->Header.GuidHob.Header.HobLength =3D 0= x%x\n", HdAudioDxeConfig->Header.GuidHob.Header.HobLength)); + + HdAudioDxeConfig->DspEndpointDmic =3D PchHdaDmic4chArray; + HdAudioDxeConfig->NhltDefaultFlow =3D TRUE; +} + +/** + Load DXE Config block default for GPIO + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadGpioDxeConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_GPIO_DXE_CONFIG *GpioDxeConfig; + GpioDxeConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "GpioDxeConfig->Header.GuidHob.Name =3D %g\n", &Gpio= DxeConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "GpioDxeConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", GpioDxeConfig->Header.GuidHob.Header.HobLength)); + + GpioDxeConfig->HideGpioAcpiDevice =3D 0; +} + +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mPchDxeIpBlocks [] = =3D { + {&gHdAudioDxeConfigGuid, sizeof (PCH_HDAUDIO_DXE_CONFIG), HDAUDIO_DXE_CO= NFIG_REVISION, LoadHdAudioDxeConfigDefault}, + {&gGpioDxeConfigGuid, sizeof (PCH_GPIO_DXE_CONFIG), GPIO_DXE_CONFIG_REVI= SION, LoadGpioDxeConfigDefault} +}; + +/** + Print PCH_HDAUDIO_DXE_CONFIG. + + @param[in] HdaDxeConfig Pointer to a PCH_HDAUDIO_DXE_CONFIG that= provides the HD Audio settings +**/ +VOID +PchPrintHdAudioDxeConfig ( + IN CONST PCH_HDAUDIO_DXE_CONFIG *HdaDxeConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH HD-Audio DXE Config --------= ----------\n")); + DEBUG ((DEBUG_INFO, " DSP Endpoint: DMIC : %d\n", HdaDxeConfig->DspEndpo= intDmic)); + DEBUG ((DEBUG_INFO, " DSP Endpoint: I2S : %d\n", HdaDxeConfig->DspEndpo= intI2s)); + DEBUG ((DEBUG_INFO, " DSP Endpoint: BT : %d\n", HdaDxeConfig->DspEndpo= intBluetooth)); + DEBUG ((DEBUG_INFO, " DSP Feature Mask : 0x%x\n", HdaDxeConfig->DspFea= tureMask)); + DEBUG ((DEBUG_INFO, " Nhlt Default Flow : %d\n", HdaDxeConfig->NhltDefa= ultFlow)); +} + +/** + Print PCH_GPIO_DXE_CONFIG. + + @param[in] GpioDxeConfig Pointer to a PCH_GPIO_DXE_CONFIG that p= rovides the GPIO settings +**/ +VOID +PchPrintGpioDxeConfig ( + IN CONST PCH_GPIO_DXE_CONFIG *GpioDxeConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH GPIO DXE Config ------------= ------\n")); + DEBUG ((DEBUG_INFO, " HideGpioAcpiDevice : %d\n", GpioDxeConfig->HideGpi= oAcpiDevice)); +} + +/** + This function prints the PCH DXE phase policy. + + @param[in] PchPolicy - PCH DXE Policy protocol +**/ +VOID +PchPrintPolicyProtocol ( + IN PCH_POLICY_PROTOCOL *PchPolicy + ) +{ + DEBUG_CODE_BEGIN(); + EFI_STATUS Status; + PCH_HDAUDIO_DXE_CONFIG *HdaDxeConfig; + PCH_GPIO_DXE_CONFIG *GpioDxeConfig; + + // + // Get requisite IP Config Blocks which needs to be used here + // + Status =3D GetConfigBlock ((VOID *) PchPolicy, &gHdAudioDxeConfigGuid, (= VOID *)&HdaDxeConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) PchPolicy, &gGpioDxeConfigGuid, (VOI= D *)&GpioDxeConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "------------------------ PCH Policy (DXE) Print Sta= rt ------------------------\n")); + DEBUG ((DEBUG_INFO, " Revision : %x\n", PchPolicy->TableHeader.Header.Re= vision)); + + PchPrintHdAudioDxeConfig (HdaDxeConfig); + PchPrintGpioDxeConfig (GpioDxeConfig); + + DEBUG ((DEBUG_INFO, "------------------------ PCH Policy (DXE) Print End= --------------------------\n")); + DEBUG_CODE_END(); +} + +/** + CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] PchPolicy The pointer to get PCH DXE Protoco= l instance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CreatePchDxeConfigBlocks ( + IN OUT PCH_POLICY_PROTOCOL **DxePchPolicy + ) +{ + UINT16 TotalBlockSize; + EFI_STATUS Status; + PCH_POLICY_PROTOCOL *PchPolicyInit; + UINT16 RequiredSize; + + + DEBUG ((DEBUG_INFO, "PCH Create Dxe Config Blocks\n")); + + PchPolicyInit =3D NULL; + + TotalBlockSize =3D GetComponentConfigBlockTotalSize (&mPchDxeIpBlocks[0]= , sizeof (mPchDxeIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); + + DEBUG ((DEBUG_INFO, "TotalBlockSize =3D 0x%x\n", TotalBlockSize)); + + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize; + + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *) &PchPolicyInit= ); + ASSERT_EFI_ERROR (Status); + + // + // General initialization + // + PchPolicyInit->TableHeader.Header.Revision =3D PCH_POLICY_PROTOCOL_REVIS= ION; + // + // Add config blocks. + // + Status =3D AddComponentConfigBlocks ((VOID *) PchPolicyInit, &mPchDxeIp= Blocks[0], sizeof (mPchDxeIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); + ASSERT_EFI_ERROR (Status); + + // + // Assignment for returning SaInitPolicy config block base address + // + *DxePchPolicy =3D PchPolicyInit; + return Status; +} + +/** + PchInstallPolicyProtocol installs PCH Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SaPolicy The pointer to SA Policy Protocol = instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +PchInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN PCH_POLICY_PROTOCOL *PchPolicy + ) +{ + + EFI_STATUS Status; + + /// + /// Print PCH DXE Policy + /// + PchPrintPolicyProtocol (PchPolicy); + + /// + /// Install protocol to to allow access to this Policy. + /// + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gPchPolicyProtocolGuid, + PchPolicy, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemL= ib/DxeResetSystemLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Dxe= ResetSystemLib/DxeResetSystemLib.c new file mode 100644 index 0000000000..fd3c280605 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeResetSystemLib/DxeR= esetSystemLib.c @@ -0,0 +1,310 @@ +/** @file + System reset library services. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mDxeResetSystemPwrmBase; +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mDxeResetSystemABase; + +/** + Dump reset message for debug build readability +**/ +VOID +DumpResetMessage ( + VOID + ) +{ + DEBUG_CODE_BEGIN (); + UINTN Index; + // + // ****************************** + // ** SYSTEM REBOOT !!! ** + // ****************************** + // + for (Index =3D 0; Index < 30; Index++) { + DEBUG ((DEBUG_INFO, "*")); + } + DEBUG ((DEBUG_INFO, "\n** SYSTEM REBOOT !!! **\n")); + for (Index =3D 0; Index < 30; Index++) { + DEBUG ((DEBUG_INFO, "*")); + } + DEBUG ((DEBUG_INFO, "\n")); + DEBUG_CODE_END (); +} + +/** + Execute call back function for Pch Reset. + + @param[in] ResetType Reset Types which includes GlobalReset. + @param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the Res= et Type Guid. +**/ +VOID +EFIAPI +PchResetCallback ( + IN EFI_RESET_TYPE ResetType, + IN EFI_GUID *ResetTypeGuid + ) +{ + EFI_STATUS Status; + UINTN NumHandles; + EFI_HANDLE *HandleBuffer; + UINTN Index; + PCH_RESET_CALLBACK_PROTOCOL *PchResetCallback; + + /// + /// Retrieve all instances of Pch Reset Callback protocol + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gPchResetCallbackProtocolGuid, + NULL, + &NumHandles, + &HandleBuffer + ); + + if (EFI_ERROR (Status)) { + /// + /// Those drivers that need to install Pch Reset Callback protocol hav= e the responsibility + /// to make sure themselves execute before Pch Reset Runtime driver. + /// + if (Status =3D=3D EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR | DEBUG_INFO, "None of Pch Reset Callback protoc= ol is installed.\n")); + } + return; + } + + for (Index =3D 0; Index < NumHandles; Index++) { + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gPchResetCallbackProtocolGuid, + (VOID **) &PchResetCallback + ); + ASSERT_EFI_ERROR (Status); + + if (!EFI_ERROR (Status)) { + PchResetCallback->ResetCallback (ResetType, ResetTypeGuid); + } + } +} + +/** + Calling this function causes a system-wide reset. This sets + all circuitry within the system to its initial state. This type of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + System reset should not return, if it returns, it means the system does + not support cold reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback Protocol + // + PchResetCallback (EfiResetCold, NULL); + + DumpResetMessage (); + + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes a system-wide initialization. The processors + are set to their initial state, and pending cycles are not corrupted. + + System reset should not return, if it returns, it means the system does + not support warm reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback Protocol + // + PchResetCallback (EfiResetWarm, NULL); + + DumpResetMessage (); + // + // In case there are pending capsules to process, need to flush the cach= e. + // + AsmWbinvd (); + + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET); +} + +/** + Calling this function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + System shutdown should not return, if it returns, it means the system do= es + not support shut down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + UINT32 Data32; + + // + // Loop through callback functions of PchResetCallback Protocol + // + PchResetCallback (EfiResetShutdown, NULL); + + /// + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the s= ystem from S5 + /// + IoWrite32 (mDxeResetSystemABase + R_ACPI_IO_GPE0_EN_127_96, 0); + + /// + /// Secondly, PwrSts register must be cleared + /// + /// Write a "1" to bit[8] of power button status register at + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit + /// + IoWrite16 (mDxeResetSystemABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_P= WRBTN); + + /// + /// Finally, transform system into S5 sleep state + /// + Data32 =3D IoRead32 (mDxeResetSystemABase + R_ACPI_IO_PM1_CNT); + + Data32 =3D (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP + B_ACPI_IO_PM= 1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5); + + IoWrite32 (mDxeResetSystemABase + R_ACPI_IO_PM1_CNT, Data32); + + Data32 =3D Data32 | B_ACPI_IO_PM1_CNT_SLP_EN; + + DumpResetMessage (); + + IoWrite32 (mDxeResetSystemABase + R_ACPI_IO_PM1_CNT, Data32); + + return; +} + +/** + Internal function to execute the required HECI command for GlobalReset, + if failed will use PCH Reest. + +**/ +STATIC +VOID +PchGlobalReset ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback Protocol + // + PchResetCallback (EfiResetPlatformSpecific, &gPchGlobalResetGuid); + + // + // PCH BIOS Spec Section 4.6 GPIO Reset Requirement + // + MmioOr32 ( + mDxeResetSystemPwrmBase + R_PMC_PWRM_ETR3, + (UINT32) B_PMC_PWRM_ETR3_CF9GR + ); + + DumpResetMessage (); + + // + // ME Global Reset should fail after EOP is sent. Go to use PCH Reset. + // + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes the system to enter a power state for platf= orm specific. + + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + EFI_GUID *GuidPtr; + + if (ResetData =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "[DxeResetSystemLib] ResetData is not available.\= n")); + return; + } + GuidPtr =3D (EFI_GUID *) ((UINT8 *) ResetData + DataSize - sizeof (EFI_G= UID)); + if (CompareGuid (GuidPtr, &gPchGlobalResetGuid)) { + PchGlobalReset(); + } else { + return; + } +} + +/** + Calling this function causes the system to enter a power state for capsu= le update. + + Reset update should not return, if it returns, it means the system does + not support capsule update. + +**/ +VOID +EFIAPI +EnterS3WithImmediateWake ( + VOID + ) +{ + ASSERT (FALSE); +} + +/** + The library constructuor. + + The function does the necessary initialization work for this library DXE= instance. + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. +**/ +EFI_STATUS +EFIAPI +DxeResetSystemLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mDxeResetSystemABase =3D PmcGetAcpiBase (); + mDxeResetSystemPwrmBase =3D PmcGetPwrmBase (); + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeReset= SystemLib/DxeRuntimeResetSystemLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/P= ch/Library/DxeRuntimeResetSystemLib/DxeRuntimeResetSystemLib.c new file mode 100644 index 0000000000..a39e171804 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.c @@ -0,0 +1,323 @@ +/** @file + System reset library services. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mDxeRuntimeResetSystemPwrmB= ase; +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mDxeRuntimeResetSystemABase; + +/** + Dump reset message for debug build readability +**/ +VOID +DumpResetMessage ( + VOID + ) +{ + DEBUG_CODE_BEGIN (); + UINTN Index; + // + // ****************************** + // ** SYSTEM REBOOT !!! ** + // ****************************** + // + if (!EfiAtRuntime ()) { + for (Index =3D 0; Index < 30; Index++) { + DEBUG ((DEBUG_INFO, "*")); + } + DEBUG ((DEBUG_INFO, "\n** SYSTEM REBOOT !!! **\n")); + for (Index =3D 0; Index < 30; Index++) { + DEBUG ((DEBUG_INFO, "*")); + } + DEBUG ((DEBUG_INFO, "\n")); + } + DEBUG_CODE_END (); +} + +/** + Execute call back function for Pch Reset. + + @param[in] ResetType Reset Types which includes GlobalReset. + @param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the Res= et Type Guid. +**/ +VOID +EFIAPI +PchResetCallback ( + IN EFI_RESET_TYPE ResetType, + IN EFI_GUID *ResetTypeGuid + ) +{ + EFI_STATUS Status; + UINTN NumHandles; + EFI_HANDLE *HandleBuffer; + UINTN Index; + PCH_RESET_CALLBACK_PROTOCOL *PchResetCallback; + + if (!EfiAtRuntime ()) { + /// + /// Retrieve all instances of Pch Reset Callback protocol + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gPchResetCallbackProtocolGuid, + NULL, + &NumHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + /// + /// Those drivers that need to install Pch Reset Callback protocol h= ave the responsibility + /// to make sure themselves execute before Pch Reset Runtime driver. + /// + if (Status =3D=3D EFI_NOT_FOUND) { + DEBUG ((DEBUG_ERROR | DEBUG_INFO, "None of Pch Reset Callback prot= ocol is installed.\n")); + } + return; + } + + for (Index =3D 0; Index < NumHandles; Index++) { + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gPchResetCallbackProtocolGuid, + (VOID **) &PchResetCallback + ); + ASSERT_EFI_ERROR (Status); + + if (!EFI_ERROR (Status)) { + PchResetCallback->ResetCallback (ResetType, ResetTypeGuid); + } + } + } +} + +/** + Calling this function causes a system-wide reset. This sets + all circuitry within the system to its initial state. This type of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + System reset should not return, if it returns, it means the system does + not support cold reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback Protocol + // + PchResetCallback (EfiResetCold, NULL); + + DumpResetMessage (); + + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes a system-wide initialization. The processors + are set to their initial state, and pending cycles are not corrupted. + + System reset should not return, if it returns, it means the system does + not support warm reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback Protocol + // + PchResetCallback (EfiResetWarm, NULL); + + DumpResetMessage (); + // + // In case there are pending capsules to process, need to flush the cach= e. + // + AsmWbinvd (); + + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET); +} + +/** + Calling this function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + System shutdown should not return, if it returns, it means the system do= es + not support shut down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + UINT32 Data32; + + // + // Loop through callback functions of PchResetCallback Protocol + // + PchResetCallback (EfiResetShutdown, NULL); + + /// + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the s= ystem from S5 + /// + IoWrite32 (mDxeRuntimeResetSystemABase + R_ACPI_IO_GPE0_EN_127_96, 0); + + /// + /// Secondly, PwrSts register must be cleared + /// + /// Write a "1" to bit[8] of power button status register at + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit + /// + IoWrite16 (mDxeRuntimeResetSystemABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM= 1_STS_PWRBTN); + + /// + /// Finally, transform system into S5 sleep state + /// + Data32 =3D IoRead32 (mDxeRuntimeResetSystemABase + R_ACPI_IO_PM1_CNT); + + Data32 =3D (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP + B_ACPI_IO_PM= 1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5); + + IoWrite32 (mDxeRuntimeResetSystemABase + R_ACPI_IO_PM1_CNT, Data32); + + Data32 =3D Data32 | B_ACPI_IO_PM1_CNT_SLP_EN; + + DumpResetMessage (); + + IoWrite32 (mDxeRuntimeResetSystemABase + R_ACPI_IO_PM1_CNT, Data32); + + return; +} + +/** + Internal function to execute the required HECI command for GlobalReset, + if failed will use PCH Reest. + +**/ +STATIC +VOID +PchGlobalReset ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback Protocol + // + PchResetCallback (EfiResetPlatformSpecific, &gPchGlobalResetGuid); + + DumpResetMessage (); + + // + // Let ME do global reset if Me Fw is available + // + if (!EfiAtRuntime ()) { + // + // PCH BIOS Spec Section 4.6 GPIO Reset Requirement + // + MmioOr32 ( + mDxeRuntimeResetSystemPwrmBase + R_PMC_PWRM_ETR3, + (UINT32) B_PMC_PWRM_ETR3_CF9GR + ); + } + + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes the system to enter a power state for platf= orm specific. + + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + EFI_GUID *GuidPtr; + + if (ResetData =3D=3D NULL) { + if (!EfiAtRuntime ()) { + DEBUG ((DEBUG_ERROR, "[DxeRuntimeResetSystemLib] ResetData is not av= ailable.\n")); + } + return; + } + GuidPtr =3D (EFI_GUID *) ((UINT8 *) ResetData + DataSize - sizeof (EFI_G= UID)); + if (CompareGuid (GuidPtr, &gPchGlobalResetGuid)) { + PchGlobalReset (); + } else { + return; + } +} + +/** + Calling this function causes the system to enter a power state for capsu= le update. + + Reset update should not return, if it returns, it means the system does + not support capsule update. + +**/ +VOID +EFIAPI +EnterS3WithImmediateWake ( + VOID + ) +{ + ASSERT (FALSE); +} + +/** + The library constructuor. + + The function does the necessary initialization work for this library ins= tance. + + The PMC PCI configuration and PWRM space memory ranges are converted int= o EFI_RUNTIME_XXX + in PciHostBridgeEntryPoint + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. + @retval EFI_ERROR Please reference LocateProtocol for error = code details. +**/ +EFI_STATUS +EFIAPI +DxeRuntimeResetSystemLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + mDxeRuntimeResetSystemABase =3D PmcGetAcpiBase (); + mDxeRuntimeResetSystemPwrmBase =3D PmcGetPwrmBase (); + + return EFI_SUCCESS; +} + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45895): https://edk2.groups.io/g/devel/message/45895 Mute This Topic: https://groups.io/mt/32918187/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45896+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45896+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001016; cv=none; d=zoho.com; s=zohoarc; b=DV7lBaA+5kChWdyj89lF8aM9fRv5RfMDvxtlKA1sKQVyyjIQOymskqn0Tnl+pUBU4+feYvY7/qnYOzvvo+j3PmfGzmfjFrUMe588IipoVA6L4MMALCwUbtIrtsWZwa6QzYgoBL9n/TjD4Rh2HmIhpjE76E25kKs5ndOQXz/v59o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001016; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=g87vlHJj3TpOj7tQPPcUwKGlGQuAGjOIIpVmNv5cXX8=; b=B/XaO/y/Xo6qr31AExaDTnroAbeYbKlrdJaQCy2ihOqBYhA2Qwdr74bg3sTsYkJVSJQ5YcdpxdnHJEsplbvxGAWoLiWUjzoiGepVL13xwmKsd1TJTwU9YgVhnCmPdUp4/d2S9QOfDxIpvCe6I1v400E99KV4rvISNbDv+kRMOcc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45896+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156600101683333.564689990129864; Fri, 16 Aug 2019 17:16:56 -0700 (PDT) Return-Path: X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:54 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319290" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:52 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 19/37] CoffeelakeSiliconPkg/Pch: Add PEI library instances Date: Fri, 16 Aug 2019 17:15:45 -0700 Message-Id: <20190817001603.30632-20-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001016; bh=y9b4+Gv3hExUslxWd2YtU70BDtNKxXzK/dHmv2tjPmE=; h=Cc:Date:From:Reply-To:Subject:To; b=k+Z0+x7KvGdaUG1bGrnTkX6JmMfck9lfV1XEw5mEHMu0N7rhL/yqj/pqg9qIcyzAa4F kA+7ZfEUU4LOZeC5BQP74tA/IJt+f8SabrjEPmJHe/yR5q5PSeAiwokPvLbaQdi5IlFbE KXLJ+FbgZolRjMv+vpTH8LuabKjLnx+HXu8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds PCH PEI library class instances. These libraries may also be compatible in other boot phases as indicated by the library type. * PeiDxeSmmBiosLockLib * PeiDxeSmmGpioLib * PeiDxeSmmPchCycleDecodingLib * PeiDxeSmmPchDmiWithS3Lib * PeiDxeSmmPchEspiLib * PeiDxeSmmPchGbeLib * PeiDxeSmmPchHsioLib * PeiDxeSmmPchInfoLib * PeiDxeSmmPchPcieRpLib * PeiDxeSmmPchPcrLib * PeiDxeSmmPchPmcLib * PeiDxeSmmPchSbiAccessLib * PeiDxeSmmPchSerialIoLib * PeiDxeSmmPchSerialIoUartLib * PeiDxeSmmPchWdtCommonLib * PeiDxeSmmPmcLib * PeiDxeSmmSataLib * PeiOcWdtLib * PeiOcWdtLibNull * PeiPchPolicyLib * PeiPchResetLib * PeiResetSystemLib * PeiSpiLib Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmBiosLockLib/PeiDxe= SmmBiosLockLib.inf | 40 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/PeiDxeSmmG= pioLib.inf | 48 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLi= b/PeiDxeSmmPchCycleDecodingLib.inf | 42 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchEspiLib/PeiDxeS= mmPchEspiLib.inf | 38 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PeiDxeSm= mPchGbeLib.inf | 38 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchHsioLib/PeiDxeS= mmPchHsioLib.inf | 37 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeS= mmPchInfoLibCnl.inf | 42 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcieRpLib/PeiDx= eSmmPchPcieRpLib.inf | 37 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/PeiDxeSm= mPchPcrLib.inf | 35 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSm= mPchPmcLib.inf | 36 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSbiAccessLib/Pe= iDxeSmmPchSbiAccessLib.inf | 35 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoLib/Pei= DxeSmmPchSerialIoLibCnl.inf | 39 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoUartLib= /PeiDxeSmmPchSerialIoUartLib.inf | 35 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchWdtCommonLib/Pe= iDxeSmmPchWdtCommonLib.inf | 31 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPm= cLib.inf | 43 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLib/PeiDxeSmmS= ataLibCnl.inf | 32 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLib/PeiOcWdtLib.inf= | 39 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLibNull/PeiOcWdtLib= Null.inf | 24 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolic= yLibCnl.inf | 86 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchResetLib/PeiPchResetL= ib.inf | 41 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiResetSystemLib/PeiResetS= ystemLib.inf | 49 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf = | 42 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioLibrar= y.h | 117 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo= LibPrivate.h | 45 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoLib/Pch= SerialIoLibInternal.h | 16 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolic= yLibrary.h | 35 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmBiosLockLib/BiosLo= ckLib.c | 98 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioInit.c= | 553 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioLib.c = | 2710 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioNames.= c | 87 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioNative= Lib.c | 234 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLi= b/PchCycleDecodingLib.c | 1136 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchEspiLib/PchEspi= Lib.c | 505 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/PchGbeLi= b.c | 82 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchHsioLib/PchHsio= Lib.c | 127 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo= Lib.c | 272 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo= LibClient.c | 87 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfo= LibCnl.c | 386 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcieRpLib/PchPc= ieRpLib.c | 183 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/PchPcrLi= b.c | 279 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/PchPmcLi= b.c | 101 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSbiAccessLib/Pc= hSbiAccessLib.c | 270 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoLib/Pch= SerialIoLib.c | 516 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoLib/Pch= SerialIoLibCnl.c | 181 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoUartLib= /PeiDxeSmmPchSerialIoUartLib.c | 372 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchWdtCommonLib/Wd= tCommon.c | 242 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PmcLib.c = | 330 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLib/SataLib.c = | 41 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLib/SataLibCdf= .c | 101 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLib/SataLibCnl= .c | 88 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLib/PeiOcWdtLib.c = | 130 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLibNull/PeiOcWdtLib= Null.c | 23 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPreMemPr= intPolicy.c | 307 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPrintPol= icy.c | 778 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolic= yLib.c | 739 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolic= yLibCnl.c | 169 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPreMe= mPolicyLib.c | 318 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchResetLib/PchReset.c = | 109 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiResetSystemLib/PeiResetS= ystemLib.c | 257 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PchSpi.c = | 217 ++ 60 files changed, 13130 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmBiosLo= ckLib/PeiDxeSmmBiosLockLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Lib= rary/PeiDxeSmmBiosLockLib/PeiDxeSmmBiosLockLib.inf new file mode 100644 index 0000000000..6db81f6cf3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmBiosLockLib/P= eiDxeSmmBiosLockLib.inf @@ -0,0 +1,40 @@ +## @file +# BIOS LOCK library. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmBiosLockLib +FILE_GUID =3D 64EBA6B1-CC36-4C2E-A0F5-D90199432E6C +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D BiosLockLib + + +[LibraryClasses] +BaseLib +DebugLib +PcdLib +PciSegmentLib +S3BootScriptLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +BiosLockLib.c + + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLi= b/PeiDxeSmmGpioLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pei= DxeSmmGpioLib/PeiDxeSmmGpioLib.inf new file mode 100644 index 0000000000..00d06591fc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/PeiDx= eSmmGpioLib.inf @@ -0,0 +1,48 @@ +## @file +# Component description file for the PeiDxeSmmGpioLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmGpioLib +FILE_GUID =3D 16EC5CA8-8195-4847-B6CB-662BD7B763F2 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D GpioLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PrintLib +PchCycleDecodingLib +PchSbiAccessLib +PmcPrivateLib +GpioPrivateLib +SataLib +GpioHelpersLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +GpioLib.c +GpioLibrary.h +GpioNativeLib.c +GpioInit.c +GpioNames.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchCyc= leDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf b/Silicon/Intel/CoffeelakeSi= liconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecoding= Lib.inf new file mode 100644 index 0000000000..2a53f42004 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecod= ingLib/PeiDxeSmmPchCycleDecodingLib.inf @@ -0,0 +1,42 @@ +## @file +# PCH cycle decoding Lib. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchCycleDecodingLib +FILE_GUID =3D 676C749F-9CD1-46B7-BAFD-4B1BC36B4C8E +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchCycleDecodingLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchInfoLib +PchPcrLib +PchDmiLib +PchEspiLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec +PcAtChipsetPkg/PcAtChipsetPkg.dec + +[Sources] +PchCycleDecodingLib.c + +[Pcd] +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress ## CONSUMES +gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress ## CONSUMES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchEsp= iLib/PeiDxeSmmPchEspiLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Libra= ry/PeiDxeSmmPchEspiLib/PeiDxeSmmPchEspiLib.inf new file mode 100644 index 0000000000..a775210984 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchEspiLib/Pe= iDxeSmmPchEspiLib.inf @@ -0,0 +1,38 @@ +## @file +# Component description file for the PeiDxeSmmPchEspiLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchEspiLib +FILE_GUID =3D 7F25F990-7989-4413-B414-1EDE557E9389 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchEspiLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PchPcrLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchEspiLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbe= Lib/PeiDxeSmmPchGbeLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library= /PeiDxeSmmPchGbeLib/PeiDxeSmmPchGbeLib.inf new file mode 100644 index 0000000000..a685104249 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/Pei= DxeSmmPchGbeLib.inf @@ -0,0 +1,38 @@ +## @file +# PCH Gbe Library. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchGbeLib +FILE_GUID =3D FC022ED0-6EB3-43E1-A740-0BA27CBBD010 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchGbeLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchInfoLib +PchPcrLib +PchCycleDecodingLib +PmcPrivateLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchGbeLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchHsi= oLib/PeiDxeSmmPchHsioLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Libra= ry/PeiDxeSmmPchHsioLib/PeiDxeSmmPchHsioLib.inf new file mode 100644 index 0000000000..7c67e0fa20 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchHsioLib/Pe= iDxeSmmPchHsioLib.inf @@ -0,0 +1,37 @@ +## @file +# PCH HSIO Library. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchHsioLib +FILE_GUID =3D 6B2D3D0D-9A04-4E7C-AE84-1C2EF2E00E2E +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchHsioLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +MmPciLib +PchInfoLib +PchPcrLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchHsioLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInf= oLib/PeiDxeSmmPchInfoLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Li= brary/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibCnl.inf new file mode 100644 index 0000000000..b9781de810 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pe= iDxeSmmPchInfoLibCnl.inf @@ -0,0 +1,42 @@ +## @file +# PCH information library for PCH. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchInfoLibCnl +FILE_GUID =3D 455CD363-0E78-46B7-8DD3-634003F1614F +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchInfoLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PrintLib +PciSegmentLib +PchPcrLib +PmcPrivateLib +PcdLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchInfoLib.c +PchInfoLibClient.c +PchInfoLibCnl.c + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPci= eRpLib/PeiDxeSmmPchPcieRpLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/L= ibrary/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLib.inf new file mode 100644 index 0000000000..b1ee095423 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcieRpLib/= PeiDxeSmmPchPcieRpLib.inf @@ -0,0 +1,37 @@ +## @file +# PCH PCIE root port Library. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchPcieRpLib +FILE_GUID =3D B4129C2C-E0C5-4E04-A82A-C61D4F0B2C75 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchPcieRpLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchInfoLib +PchPcrLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchPcieRpLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcr= Lib/PeiDxeSmmPchPcrLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library= /PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf new file mode 100644 index 0000000000..0244e1c0c8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/Pei= DxeSmmPchPcrLib.inf @@ -0,0 +1,35 @@ +## @file +# PCH PCR Library. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchPcrLib +FILE_GUID =3D 117C8D19-445B-46BF-B624-109F63709375 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchPcrLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PchInfoLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchPcrLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmc= Lib/PeiDxeSmmPchPmcLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library= /PeiDxeSmmPchPmcLib/PeiDxeSmmPchPmcLib.inf new file mode 100644 index 0000000000..3b1f1e467b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/Pei= DxeSmmPchPmcLib.inf @@ -0,0 +1,36 @@ +## @file +# PEI/DXE/SMM PCH PMC Lib. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchPmcLib +FILE_GUID =3D 9D60C364-5086-41E3-BC9D-C62AB7233DBF +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchPmcLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +MmPciLib +PchCycleDecodingLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchPmcLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSbi= AccessLib/PeiDxeSmmPchSbiAccessLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg= /Pch/Library/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf new file mode 100644 index 0000000000..ceb109168b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSbiAccessL= ib/PeiDxeSmmPchSbiAccessLib.inf @@ -0,0 +1,35 @@ +## @file +# PCH SBI access library. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchSbiAccessLib +FILE_GUID =3D 96ECB0FB-A975-4DC8-B88A-D90C3378CE87 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchSbiAccessLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchSbiAccessLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSer= ialIoLib/PeiDxeSmmPchSerialIoLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPk= g/Pch/Library/PeiDxeSmmPchSerialIoLib/PeiDxeSmmPchSerialIoLibCnl.inf new file mode 100644 index 0000000000..3bfada0b22 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoLi= b/PeiDxeSmmPchSerialIoLibCnl.inf @@ -0,0 +1,39 @@ +## @file +# Component description file for PEI/DXE/SMM PCH Serial IO Lib. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchSerialIoLibCnl +FILE_GUID =3D 613A22A2-5736-40f8-909B-DF10EA389C72 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchSerialIoLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PcdLib +PciSegmentLib +GpioPrivateLib +PchPcrLib +PchSerialIoUartLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchSerialIoLib.c +PchSerialIoLibCnl.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSer= ialIoUartLib/PeiDxeSmmPchSerialIoUartLib.inf b/Silicon/Intel/CoffeelakeSili= conPkg/Pch/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.= inf new file mode 100644 index 0000000000..1becfc7a96 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoUa= rtLib/PeiDxeSmmPchSerialIoUartLib.inf @@ -0,0 +1,35 @@ +## @file +# Component description file for PCH Serial IO UART Lib. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchSerialIoUartLib +FILE_GUID =3D 55463A54-FD0D-4e8e-8D57-D54FAAEFDC2F +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchSerialIoUartLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PchSerialIoLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PeiDxeSmmPchSerialIoUartLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchWdt= CommonLib/PeiDxeSmmPchWdtCommonLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg= /Pch/Library/PeiDxeSmmPchWdtCommonLib/PeiDxeSmmPchWdtCommonLib.inf new file mode 100644 index 0000000000..8a01a749bf --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchWdtCommonL= ib/PeiDxeSmmPchWdtCommonLib.inf @@ -0,0 +1,31 @@ +## @file +# Component description file for the PchWdtCommonLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiDxeSmmPchWdtCommonLib + FILE_GUID =3D 171F78D2-0A52-4692-8830-AB693791EA23 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PchWdtCommonLib + +[Sources] + WdtCommon.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + IoLib + DebugLib + PmcLib + +[Pcd] + gSiPkgTokenSpaceGuid.PcdOcEnableWdtforDebug ## CONSUMES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib= /PeiDxeSmmPmcLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDx= eSmmPmcLib/PeiDxeSmmPmcLib.inf new file mode 100644 index 0000000000..78e212eeb0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PeiDxe= SmmPmcLib.inf @@ -0,0 +1,43 @@ +## @file +# PEI/DXE/SMM PCH PMC Lib. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPmcLib +FILE_GUID =3D 9D60C364-5086-41E3-BC9D-C62AB7233DBF +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PmcLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PchCycleDecodingLib +PchPcrLib +PchInfoLib +PmcPrivateLib +BaseMemoryLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress + + +[Sources] +PmcLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLi= b/PeiDxeSmmSataLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/= PeiDxeSmmSataLib/PeiDxeSmmSataLibCnl.inf new file mode 100644 index 0000000000..128b348b3d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLib/PeiDx= eSmmSataLibCnl.inf @@ -0,0 +1,32 @@ +## @file +# PEI/DXE/SMM PCH SATA library for Cannon Lake PCH. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchSataLibCnl +FILE_GUID =3D 5163ECE3-5372-47E1-B057-2282E753DD55 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D SataLib + +[LibraryClasses] +BaseLib +PciSegmentLib +PchInfoLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +SataLib.c +SataLibCnl.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLib/Pei= OcWdtLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLib/P= eiOcWdtLib.inf new file mode 100644 index 0000000000..37d0c80ea4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLib/PeiOcWdtLi= b.inf @@ -0,0 +1,39 @@ +## @file +# Component Description File for OcWdt Support. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiOcWdtLib +FILE_GUID =3D D5207C23-3632-4078-A671-3B5C364B2BDB +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D OcWdtLib + + +[LibraryClasses] +IoLib +DebugLib +PeiServicesLib +PchWdtCommonLib +PmcLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PeiOcWdtLib.c + + +[Ppis] +gWdtPpiGuid ## PRODUCES + +[Pcd] +gSiPkgTokenSpaceGuid.PcdOcEnableWdtforDebug ## CONSUMES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLibNull= /PeiOcWdtLibNull.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOc= WdtLibNull/PeiOcWdtLibNull.inf new file mode 100644 index 0000000000..68ff41ef7f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLibNull/PeiOcW= dtLibNull.inf @@ -0,0 +1,24 @@ +## @file +# Component Description File for OcWdt Support. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiOcWdtLib +FILE_GUID =3D DB65B36B-E276-4A2b-AB20-61764889E483 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D OcWdtLib + + +[Packages] +MdePkg/MdePkg.dec + + +[Sources] +PeiOcWdtLibNull.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib= /PeiPchPolicyLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pe= iPchPolicyLib/PeiPchPolicyLibCnl.inf new file mode 100644 index 0000000000..49e63cfc51 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPch= PolicyLibCnl.inf @@ -0,0 +1,86 @@ +## @file +# Component description file for the PeiPchPolicy libbrary. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiPchPolicyLibCnl +FILE_GUID =3D BB1AC992-B2CA-4744-84B7-915C185576C5 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D PchPolicyLib + + +[LibraryClasses] +DebugLib +IoLib +PcdLib +PeiServicesLib +BaseMemoryLib +MemoryAllocationLib +PchInfoLib +ConfigBlockLib +SiConfigBlockLib +SataLib +PchPcieRpLib +CpuPlatformLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable +gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber + + +[Sources] +PeiPchPolicyLib.c +PeiPchPolicyLibCnl.c +PeiPchPolicyLibrary.h +PeiPchPreMemPolicyLib.c +PchPrintPolicy.c +PchPreMemPrintPolicy.c + +[Guids] +gPchGeneralConfigGuid ## CONSUMES +gPcieRpConfigGuid ## CONSUMES +gSataConfigGuid ## CONSUMES +gIoApicConfigGuid ## CONSUMES +gDmiConfigGuid ## CONSUMES +gFlashProtectionConfigGuid ## CONSUMES +gHdAudioConfigGuid ## CONSUMES +gInterruptConfigGuid ## CONSUMES +gIshConfigGuid ## CONSUMES +gLanConfigGuid ## CONSUMES +gLockDownConfigGuid ## CONSUMES +gP2sbConfigGuid ## CONSUMES +gPmConfigGuid ## CONSUMES +gScsConfigGuid ## CONSUMES +gSerialIoConfigGuid ## CONSUMES +gSerialIrqConfigGuid ## CONSUMES +gThermalConfigGuid ## CONSUMES +gUsbConfigGuid ## CONSUMES +gEspiConfigGuid ## CONSUMES +gCnviConfigGuid ## CONSUMES +gHsioConfigGuid ## CONSUMES +gPchGeneralPreMemConfigGuid ## COMSUMES +gDciPreMemConfigGuid ## CONSUMES +gWatchDogPreMemConfigGuid ## CONSUMES +gPchTraceHubPreMemConfigGuid ## CONSUMES +gSmbusPreMemConfigGuid ## CONSUMES +gLpcPreMemConfigGuid ## CONSUMES +gHsioPciePreMemConfigGuid ## CONSUMES +gHsioSataPreMemConfigGuid ## CONSUMES +gPcieRpPreMemConfigGuid ## CONSUMES +gHdAudioPreMemConfigGuid ## CONSUMES +gIshPreMemConfigGuid ## CONSUMES + +[Ppis] diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchResetLib/= PeiPchResetLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchR= esetLib/PeiPchResetLib.inf new file mode 100644 index 0000000000..41e339a2e8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchResetLib/PeiPchR= esetLib.inf @@ -0,0 +1,41 @@ +## @file +# Component description file for PCH Reset Lib Pei Phase +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiPchResetLib +FILE_GUID =3D DB91FFF0-5B99-4A88-9EC8-183A2106DCA2 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D PchResetLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +DebugLib +PeiServicesLib +PeiServicesTablePointerLib +MemoryAllocationLib +ResetSystemLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchReset.c + +[Ppis] +gEfiPeiReset2PpiGuid ## PRODUCES + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiResetSystemL= ib/PeiResetSystemLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/P= eiResetSystemLib/PeiResetSystemLib.inf new file mode 100644 index 0000000000..f8f8bf1b66 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiResetSystemLib/PeiR= esetSystemLib.inf @@ -0,0 +1,49 @@ +## @file +# Component description file for Intel Ich7 Reset System Library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiResetSystemLib +FILE_GUID =3D D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +UEFI_SPECIFICATION_VERSION =3D 2.00 +LIBRARY_CLASS =3D ResetSystemLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +IoLib +DebugLib +BaseMemoryLib +PeiServicesLib +PmcLib +PmcPrivateLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PeiResetSystemLib.c + + +[Ppis] +gMeDidSentPpiGuid ## CONSUMES +gPchResetCallbackPpiGuid ## CONSUMES + + +[Guids] +gPchGlobalResetGuid + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSp= iLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiL= ib.inf new file mode 100644 index 0000000000..fb2fad78d3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PeiSpiLib.inf @@ -0,0 +1,42 @@ +## @file +# Component description file for PCH Reset Lib Pei Phase +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiSpiLib +FILE_GUID =3D 4998447D-7948-448F-AB75-96E24E18FF23 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D SpiLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +DebugLib +PeiServicesLib +PeiServicesTablePointerLib +MemoryAllocationLib +PciSegmentLib +PchSpiCommonLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchSpi.c + + +[Ppis] +gPchSpiPpiGuid ## PRODUCES + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLi= b/GpioLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmG= pioLib/GpioLibrary.h new file mode 100644 index 0000000000..7a480b6cad --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioL= ibrary.h @@ -0,0 +1,117 @@ +/** @file + Header file for GPIO Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_LIBRARY_H_ +#define _GPIO_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// BIT15-0 - pad number +// BIT31-16 - group info +// BIT23- 16 - group index +// BIT31- 24 - chipset ID +#define PAD_INFO_MASK 0x0000FFFF +#define GROUP_INFO_POSITION 16 +#define GROUP_INFO_MASK 0xFFFF0000 +#define GROUP_INDEX_MASK 0x00FF0000 +#define UNIQUE_ID_MASK 0xFF000000 +#define UNIQUE_ID_POSITION 24 + +#define GPIO_PAD_DEF(Group,Pad) (UINT32)(((Group) << 16) + (= Pad)) +#define GPIO_GROUP_DEF(Index,ChipsetId) ((Index) | ((ChipsetId) << 8= )) +#define GPIO_GET_GROUP_INDEX(Group) ((Group) & 0xFF) +#define GPIO_GET_GROUP_FROM_PAD(Pad) ((Pad) >> 16) +#define GPIO_GET_GROUP_INDEX_FROM_PAD(Pad) GPIO_GET_GROUP_INDEX (((Pad)= >> 16)) +#define GPIO_GET_PAD_NUMBER(Pad) ((Pad) & 0xFFFF) +#define GPIO_GET_CHIPSET_ID(Pad) ((Pad) >> 24) + +#define GPIO_GET_PAD_POSITION(PadNumber) ((PadNumber) % 32) +#define GPIO_GET_DW_NUM(PadNumber) ((PadNumber) / 32u) + +// +// Number of PADCFG_DW registers +// +#define GPIO_PADCFG_DW_REG_NUMBER 4 + +/** + This internal procedure will calculate GPIO_RESET_CONFIG value (new typ= e) + based on provided PadRstCfg for a specific GPIO Pad. + + @param[in] GpioPad GPIO Pad + @param[in] PadRstCfg GPIO PadRstCfg value + + @retval GpioResetConfig GPIO Reset configuration (new type) +**/ +GPIO_RESET_CONFIG +GpioResetConfigFromPadRstCfg ( + IN GPIO_PAD GpioPad, + IN UINT32 PadRstCfg + ); + +/** + This internal procedure will calculate PadRstCfg register value based + on provided GPIO Reset configuration for a certain pad. + + @param[in] GpioPad GPIO Pad + @param[in] GpioResetConfig GPIO Reset configuration + @param[out] PadRstCfg GPIO PadRstCfg value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid configuration +**/ +EFI_STATUS +GpioPadRstCfgFromResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG GpioResetConfig, + OUT UINT32 *PadRstCfg + ); + +/** + This procedure will calculate PADCFG register value based on GpioConfig = data + + @param[in] GpioPad GPIO Pad + @param[in] GpioConfig GPIO Configuration data + @param[out] PadCfgDwReg PADCFG DWx register value + @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits= to be modified +**/ +VOID +GpioPadCfgRegValueFromGpioConfig ( + IN GPIO_PAD GpioPad, + IN CONST GPIO_CONFIG *GpioConfig, + OUT UINT32 *PadCfgDwReg, + OUT UINT32 *PadCfgDwRegMask + ); + +/** + Generates GPIO group name from GroupIndex + + @param[in] GroupIndex Gpio GroupIndex + + @retval CHAR8* Pointer to the GPIO group name +**/ +CONST +CHAR8* +GpioGetGroupName ( + IN UINT32 GroupIndex + ); + +#endif // _GPIO_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInf= oLib/PchInfoLibPrivate.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/P= eiDxeSmmPchInfoLib/PchInfoLibPrivate.h new file mode 100644 index 0000000000..79e03fef44 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pc= hInfoLibPrivate.h @@ -0,0 +1,45 @@ +/** @file + Private header for PCH Info Lib. + + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +/** + Structure for PCH SKU string mapping +**/ +struct PCH_SKU_STRING { + UINT16 Id; + CHAR8 *String; +}; + +extern struct PCH_SKU_STRING mSkuStrs[]; + +/** + Determine Pch Series based on Device Id + + @param[in] LpcDeviceId Lpc Device Id + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeriesFromLpcDid ( + IN UINT16 LpcDeviceId + ); + +/** +Determine Pch Generation based on Device Id + +@param[in] LpcDeviceId Lpc Device Id + +@retval PCH_GENERATION Pch Generation +**/ +PCH_GENERATION +PchGenerationFromDid ( + IN UINT16 LpcDeviceId + ); + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSer= ialIoLib/PchSerialIoLibInternal.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/= Library/PeiDxeSmmPchSerialIoLib/PchSerialIoLibInternal.h new file mode 100644 index 0000000000..17e4bb863a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoLi= b/PchSerialIoLibInternal.h @@ -0,0 +1,16 @@ +/** @file + Header file for PchSerialIoLibInternal. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SERIAL_IO_LIB_INTERNAL_H_ +#define _PCH_SERIAL_IO_LIB_INTERNAL_H_ + +typedef struct { + UINT8 DevNum; + UINT8 FuncNum; +} SERIAL_IO_BDF_NUMBERS; +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib= /PeiPchPolicyLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pei= PchPolicyLib/PeiPchPolicyLibrary.h new file mode 100644 index 0000000000..abd7e63365 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPch= PolicyLibrary.h @@ -0,0 +1,35 @@ +/** @file + Header file for the PeiPchPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PCH_POLICY_LIBRARY_H_ +#define _PEI_PCH_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Adds interrupt configuration for device + + @param[in/out] InterruptConfig Pointer to interrupt config +**/ +VOID +LoadDeviceInterruptConfig ( + IN OUT PCH_INTERRUPT_CONFIG *InterruptConfig + ); + +#endif // _PEI_PCH_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmBiosLo= ckLib/BiosLockLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxe= SmmBiosLockLib/BiosLockLib.c new file mode 100644 index 0000000000..20c024e893 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmBiosLockLib/B= iosLockLib.c @@ -0,0 +1,98 @@ +/** @file + Bios Lock library. + + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Enable BIOS lock. This will set the LE (Lock Enable) and EISS (Enable In= SMM.STS). + When this is set, attempts to write the WPD (Write Protect Disable) bit = in PCH + will cause a SMI which will allow the BIOS to verify that the write is f= rom a valid source. + + Bios should always enable LockDownConfig.BiosLock policy to set Bios Loc= k bit in FRC. + If capsule udpate is enabled, it's expected to not do BiosLock by settin= g BiosLock policy disable + so it can udpate BIOS region. + After flash update, it should utilize this lib to do BiosLock for securi= ty. +**/ +VOID +BiosLockEnable ( + VOID + ) +{ + UINT64 LpcBaseAddress; + UINT64 SpiBaseAddress; + + LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + SpiBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + + /// + /// PCH BIOS Spec Flash Security Recommendation + /// + /// BIOS needs to enable the BIOS Lock Enable (BLE) feature of the PCH b= y setting + /// SPI/eSPI/LPC PCI offset DCh[1] =3D 1b. + /// When this bit is set, attempts to write the Write Protect Disable (W= PD) bit + /// in PCH will cause a SMI which will allow the BIOS to verify that the= write is + /// from a valid source. + /// Remember that BIOS needs to set SPI/LPC/eSPI PCI Offset DC [0] =3D 0= b to enable + /// BIOS region protection before exiting the SMI handler. + /// Also, TCO_EN bit needs to be set (SMI_EN Register, ABASE + 30h[13] = =3D 1b) to keep + /// BLE feature enabled after booting to the OS. + /// Intel requires that BIOS enables the Lock Enable (LE) feature of the= PCH to + /// ensure SMM protection of flash. + /// RC installs a default SMI handler that clears WPD. + /// There could be additional SMI handler to log such attempt if desired. + /// + /// BIOS needs to enable the "Enable in SMM.STS" (EISS) feature of the P= CH by setting + /// SPI PCI offset DCh[5] =3D 1b for SPI or setting eSPI PCI offset DCh[= 5] =3D 1b for eSPI. + /// When this bit is set, the BIOS region is not writable until SMM sets= the InSMM.STS bit, + /// to ensure BIOS can only be modified from SMM. Please refer to CPU BW= G for more details + /// on InSMM.STS bit. + /// Intel requires that BIOS enables the Lock Enable (LE) feature of the= PCH to ensure + /// SMM protection of flash. + /// SPI PCI offset DCh[1] =3D 1b for SPI or setting eSPI PCI offset DCh[= 1] =3D 1b for eSPI. + /// When this bit is set, EISS is locked down. + /// + PciSegmentOr8 (SpiBaseAddress + R_SPI_CFG_BC, B_SPI_CFG_BC_EISS | B_SPI_= CFG_BC_LE); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint8, + PcdGet64 (PcdPciExpressBaseAddress) + SpiBaseAddress + R_SPI_CFG_BC, + 1, + (VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + SpiBaseAddress= + R_SPI_CFG_BC) + ); + PciSegmentOr8 (LpcBaseAddress + R_LPC_CFG_BC, B_LPC_CFG_BC_EISS | B_LPC_= CFG_BC_LE); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint8, + PcdGet64 (PcdPciExpressBaseAddress) + LpcBaseAddress + R_LPC_CFG_BC, + 1, + (VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + LpcBaseAddress= + R_LPC_CFG_BC) + ); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLi= b/GpioInit.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpio= Lib/GpioInit.c new file mode 100644 index 0000000000..76eb3a9b81 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioI= nit.c @@ -0,0 +1,553 @@ +/** @file + This file contains routines for GPIO initialization + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "GpioLibrary.h" +#include + +// +// GPIO_GROUP_DW_DATA structure is used by GpioConfigurePch function +// to cache values which will be programmed into respective GPIO registers +// after all GpioPads are processed. This way MMIO accesses are decreased +// and instead of doing one programming for one GpioPad there is only +// one access for whole register. +// +typedef struct { + UINT32 HostSoftOwnReg; + UINT32 HostSoftOwnRegMask; + UINT32 GpiGpeEnReg; + UINT32 GpiGpeEnRegMask; + UINT32 GpiNmiEnReg; + UINT32 GpiNmiEnRegMask; + UINT32 GpiSmiEnReg; + UINT32 GpiSmiEnRegMask; + UINT32 ConfigUnlockMask; + UINT32 OutputUnlockMask; +} GPIO_GROUP_DW_DATA; + +// +// GPIO_GROUP_DW_NUMBER contains number of DWords required to +// store Pad data for all groups. Each pad uses one bit. +// +// For Cannonlake only vGPIO group has >32 pads but those pads +// will not be accessed by this function so GPIO_GROUP_DW_NUMBER can be 1 +// +#define GPIO_GROUP_DW_NUMBER 1 + +/** + Get GPIO DW Register values (HOSTSW_OWN, GPE_EN, NMI_EN, Lock). + + @param[in] PadNumber GPIO pad number + @param[in] GpioConfig GPIO Config data + @param[in out] DwRegsValues Values for GPIO DW Registers + + @retval None +**/ +STATIC +VOID +GpioDwRegValueFromGpioConfig ( + IN UINT32 PadNumber, + IN CONST GPIO_CONFIG *GpioConfig, + IN OUT GPIO_GROUP_DW_DATA *GroupDwData + ) +{ + UINT32 PadBitPosition; + UINT32 DwNum; + + PadBitPosition =3D GPIO_GET_PAD_POSITION (PadNumber); + DwNum =3D GPIO_GET_DW_NUM (PadNumber); + + if (DwNum >=3D GPIO_GROUP_DW_NUMBER) { + ASSERT (FALSE); + return; + } + // + // Update value to be programmed in HOSTSW_OWN register + // + GroupDwData[DwNum].HostSoftOwnRegMask |=3D (GpioConfig->HostSoftPadOwn &= 0x1) << PadBitPosition; + GroupDwData[DwNum].HostSoftOwnReg |=3D (GpioConfig->HostSoftPadOwn >> 0x= 1) << PadBitPosition; + + // + // Update value to be programmed in GPI_GPE_EN register + // + GroupDwData[DwNum].GpiGpeEnRegMask |=3D (GpioConfig->InterruptConfig & 0= x1) << PadBitPosition; + GroupDwData[DwNum].GpiGpeEnReg |=3D ((GpioConfig->InterruptConfig & Gpio= IntSci) >> 3) << PadBitPosition; + + // + // Update value to be programmed in GPI_NMI_EN register + // + GroupDwData[DwNum].GpiNmiEnRegMask |=3D (GpioConfig->InterruptConfig & 0= x1) << PadBitPosition; + GroupDwData[DwNum].GpiNmiEnReg |=3D ((GpioConfig->InterruptConfig & Gpio= IntNmi) >> 1) << PadBitPosition; + + // + // Update value to be programmed in GPI_SMI_EN register + GroupDwData[DwNum].GpiSmiEnRegMask |=3D (GpioConfig->InterruptConfig & 0= x1) << PadBitPosition; + GroupDwData[DwNum].GpiSmiEnReg |=3D ((GpioConfig->InterruptConfig & Gpio= IntSmi) >> 2) << PadBitPosition; + if ((GpioConfig->InterruptConfig & GpioIntSmi) =3D=3D GpioIntSmi) { + GroupDwData[DwNum].HostSoftOwnRegMask |=3D 1 << PadBitPosition; + GroupDwData[DwNum].HostSoftOwnReg |=3D 1 << PadBitPosition; + } + + // + // Update information on Pad Configuration Lock + // + GroupDwData[DwNum].ConfigUnlockMask |=3D ((GpioConfig->LockConfig >> 1) = & 0x1) << PadBitPosition; + + // + // Update information on Pad Configuration Lock Tx + // + GroupDwData[DwNum].OutputUnlockMask |=3D ((GpioConfig->LockConfig >> 3) = & 0x1) << PadBitPosition; + + // + // if pad in GpioMode is an output default action should be to leave out= put unlocked + // + if ((GpioConfig->PadMode =3D=3D GpioPadModeGpio) && + (GpioConfig->Direction =3D=3D GpioDirOut) && + ((GpioConfig->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) =3D= =3D GpioLockDefault)) { + GroupDwData[DwNum].OutputUnlockMask |=3D 0x1 << PadBitPosition; + } +} + +/** + This internal procedure will scan GPIO initialization table and unlock + all pads present in it + + @param[in] NumberOfItem Number of GPIO pad records in table + @param[in] GpioInitTableAddress GPIO initialization table + @param[in] Index Index of GPIO Initialization table= record + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +STATIC +EFI_STATUS +GpioUnlockPadsForAGroup ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress, + IN UINT32 Index + ) +{ + UINT32 PadsToUnlock[GPIO_GROUP_DW_NUMBER]; + UINT32 DwNum; + UINT32 PadBitPosition; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + CONST GPIO_INIT_CONFIG *GpioData; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GpioData =3D &GpioInitTableAddress[Index]; + Group =3D GpioGetGroupFromGpioPad (GpioData->GpioPad); + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioData->GpioPad); + + ZeroMem (PadsToUnlock, sizeof (PadsToUnlock)); + // + // Loop through pads for one group. If pad belongs to a different group = then + // break and move to register programming. + // + while (Index < NumberOfItems) { + + GpioData =3D &GpioInitTableAddress[Index]; + if (GroupIndex !=3D GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)) { + //if next pad is from different group then break loop + break; + } + + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioData->GpioPad); + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible r= ange for group %d\n", PadNumber, GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + PadBitPosition =3D GPIO_GET_PAD_POSITION (PadNumber); + DwNum =3D GPIO_GET_DW_NUM (PadNumber); + + if (DwNum >=3D GPIO_GROUP_DW_NUMBER) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Update pads which need to be unlocked + // + PadsToUnlock[DwNum] |=3D 0x1 << PadBitPosition; + + //Move to next item + Index++; + } + + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].= PadPerGroup); DwNum++) { + // + // Unlock pads + // + if (PadsToUnlock[DwNum] !=3D 0) { + GpioUnlockPadCfgForGroupDw (Group, DwNum, PadsToUnlock[DwNum]); + GpioUnlockPadCfgTxForGroupDw (Group, DwNum, PadsToUnlock[DwNum]); + } + } + + return EFI_SUCCESS; +} + +/** + This procedure will initialize multiple PCH GPIO pins + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +STATIC +EFI_STATUS +GpioConfigurePch ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ) +{ + UINT32 Index; + UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER]; + UINT32 PadCfgDwRegMask[GPIO_PADCFG_DW_REG_NUMBER]; + UINT32 PadCfgReg; + GPIO_GROUP_DW_DATA GroupDwData[GPIO_GROUP_DW_NUMBER]; + UINT32 DwNum; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + GPIO_PAD_OWN PadOwnVal; + CONST GPIO_INIT_CONFIG *GpioData; + UINT32 GroupIndex; + UINT32 PadNumber; + PCH_SBI_PID GpioCom; + + PadOwnVal =3D GpioPadOwnHost; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + Index =3D 0; + while (Index < NumberOfItems) { + + GpioData =3D &GpioInitTableAddress[Index]; + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioData->GpioPad); + GpioCom =3D GpioGroupInfo[GroupIndex].Community; + + DEBUG_CODE_BEGIN(); + if (!GpioIsCorrectPadForThisChipset (GpioData->GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on= this chipset!\n", GpioData->GpioPad)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + DEBUG_CODE_END (); + + // + // Unlock pads for a given group which are going to be reconfigured + // + // + // Because PADCFGLOCK/LOCKTX register reset domain is Powergood, lock = settings + // will get back to default only after G3 or DeepSx transition. On the= other hand GpioPads + // configuration is controlled by a configurable type of reset - PadRs= tCfg. This means that if + // PadRstCfg !=3D Powergood GpioPad will have its configuration locked= despite it being not the + // one desired by BIOS. Before reconfiguring all pads they will get un= locked. + // + GpioUnlockPadsForAGroup (NumberOfItems, GpioInitTableAddress, Index); + + ZeroMem (GroupDwData, sizeof (GroupDwData)); + // + // Loop through pads for one group. If pad belongs to a different grou= p then + // break and move to register programming. + // + while (Index < NumberOfItems) { + + GpioData =3D &GpioInitTableAddress[Index]; + if (GroupIndex !=3D GpioGetGroupIndexFromGpioPad (GpioData->GpioPad)= ) { + //if next pad is from different group then break loop + break; + } + + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioData->GpioPad); + + DEBUG_CODE_BEGIN (); + // + // Check if legal pin number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible= range for group %d\n", PadNumber, GroupIndex)); + return EFI_INVALID_PARAMETER; + } + + // + // Check if selected GPIO Pad is not owned by CSME/ISH + // + GpioGetPadOwnership (GpioData->GpioPad, &PadOwnVal); + + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Accessing pad not owned by host = (Group=3D%d, Pad=3D%d)!\n", GroupIndex, PadNumber)); + DEBUG ((DEBUG_ERROR, "** Please make sure the GPIO usage in sync b= etween CSME and BIOS configuration. \n")); + DEBUG ((DEBUG_ERROR, "** All the GPIO occupied by CSME should not = do any configuration by BIOS.\n")); + //Move to next item + Index++; + continue; + } + + // + // Check if Pad enabled for SCI is to be in unlocked state + // + if (((GpioData->GpioConfig.InterruptConfig & GpioIntSci) =3D=3D Gpio= IntSci) && + ((GpioData->GpioConfig.LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_= LOCK_MASK) !=3D GpioPadConfigUnlock)){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: %a used for SCI is not unlocked!= \n", GpioName (GpioData->GpioPad))); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + DEBUG_CODE_END (); + + ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg)); + ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask)); + // + // Get GPIO PADCFG register value from GPIO config data + // + GpioPadCfgRegValueFromGpioConfig ( + GpioData->GpioPad, + &GpioData->GpioConfig, + PadCfgDwReg, + PadCfgDwRegMask + ); + + // + // Create PADCFG register offset using group and pad number + // + PadCfgReg =3D S_GPIO_PCR_PADCFG * PadNumber + GpioGroupInfo[GroupInd= ex].PadCfgOffset; + + // + // Write PADCFG DW0 register + // + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioCom, PadCfgReg), + ~PadCfgDwRegMask[0], + PadCfgDwReg[0] + ); + + // + // Write PADCFG DW1 register + // + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioCom, PadCfgReg + 0x4), + ~PadCfgDwRegMask[1], + PadCfgDwReg[1] + ); + + // + // Write PADCFG DW2 register + // + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioCom, PadCfgReg + 0x8), + ~PadCfgDwRegMask[2], + PadCfgDwReg[2] + ); + + // + // Get GPIO DW register values from GPIO config data + // + GpioDwRegValueFromGpioConfig ( + PadNumber, + &GpioData->GpioConfig, + GroupDwData + ); + + //Move to next item + Index++; + } + + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex= ].PadPerGroup); DwNum++) { + // + // Write HOSTSW_OWN registers + // + if (GpioGroupInfo[GroupIndex].HostOwnOffset !=3D NO_REGISTER_FOR_PRO= PERTY) { + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioCom, GpioGroupInfo[GroupIndex].HostOwnOffse= t + DwNum * 0x4), + ~GroupDwData[DwNum].HostSoftOwnRegMask, + GroupDwData[DwNum].HostSoftOwnReg + ); + } + + // + // Write GPI_GPE_EN registers + // + if (GpioGroupInfo[GroupIndex].GpiGpeEnOffset !=3D NO_REGISTER_FOR_PR= OPERTY) { + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioCom, GpioGroupInfo[GroupIndex].GpiGpeEnOffs= et + DwNum * 0x4), + ~GroupDwData[DwNum].GpiGpeEnRegMask, + GroupDwData[DwNum].GpiGpeEnReg + ); + } + + // + // Write GPI_NMI_EN registers + // + if (GpioGroupInfo[GroupIndex].NmiEnOffset !=3D NO_REGISTER_FOR_PROPE= RTY) { + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioCom, GpioGroupInfo[GroupIndex].NmiEnOffset = + DwNum * 0x4), + ~GroupDwData[DwNum].GpiNmiEnRegMask, + GroupDwData[DwNum].GpiNmiEnReg + ); + } else if (GroupDwData[DwNum].GpiNmiEnReg !=3D 0x0) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting = NMI\n", GroupIndex)); + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + } + + // + // Write GPI_SMI_EN registers + // + if (GpioGroupInfo[GroupIndex].SmiEnOffset !=3D NO_REGISTER_FOR_PROPE= RTY) { + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioCom, GpioGroupInfo[GroupIndex].SmiEnOffset = + DwNum * 0x4), + ~GroupDwData[DwNum].GpiSmiEnRegMask, + GroupDwData[DwNum].GpiSmiEnReg + ); + } else if (GroupDwData[DwNum].GpiSmiEnReg !=3D 0x0) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %d has no pads supporting = SMI\n", GroupIndex)); + ASSERT_EFI_ERROR (EFI_UNSUPPORTED); + } + + // + // Update Pad Configuration unlock data + // + if (GroupDwData[DwNum].ConfigUnlockMask) { + GpioStoreGroupDwUnlockPadConfigData (GroupIndex, DwNum, GroupDwDat= a[DwNum].ConfigUnlockMask); + } + + // + // Update Pad Output unlock data + // + if (GroupDwData[DwNum].OutputUnlockMask) { + GpioStoreGroupDwUnlockOutputData (GroupIndex, DwNum, GroupDwData[D= wNum].OutputUnlockMask); + } + } + } + + return EFI_SUCCESS; +} + +/** + This procedure will clear all status bits of any GPIO interrupts. +**/ +STATIC +VOID +GpioClearAllGpioInterrupts ( + VOID + ) +{ + GPIO_GROUP Group; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + GPIO_GROUP GpioGroupLowest; + GPIO_GROUP GpioGroupHighest; + UINT32 GroupIndex; + UINT32 GpioGroupInfoLength; + UINT32 DwNum; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GpioGroupLowest =3D GpioGetLowestGroup (); + GpioGroupHighest =3D GpioGetHighestGroup (); + + for (Group =3D GpioGroupLowest; Group <=3D GpioGroupHighest; Group++) { + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + // + // Check if group has GPI IS register + // + if (GpioGroupInfo[GroupIndex].GpiIsOffset !=3D NO_REGISTER_FOR_PROPERT= Y) { + // + // Clear all GPI_IS Status bits by writing '1' + // + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGroupInfo[GroupInd= ex].PadPerGroup); DwNum++) { + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupI= nfo[GroupIndex].GpiIsOffset + DwNum * 0x4), + 0xFFFFFFFF + ); + } + } + + // + // Check if group has GPI_GPE_STS register + // + if (GpioGroupInfo[GroupIndex].GpiGpeStsOffset !=3D NO_REGISTER_FOR_PRO= PERTY) { + // + // Clear all GPI_GPE_STS Status bits by writing '1' + // + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGroupInfo[GroupInd= ex].PadPerGroup); DwNum++) { + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupI= nfo[GroupIndex].GpiGpeStsOffset + DwNum * 0x4), + 0xFFFFFFFF + ); + } + } + + // + // Check if group has SMI_STS register + // + if (GpioGroupInfo[GroupIndex].SmiStsOffset !=3D NO_REGISTER_FOR_PROPER= TY) { + // + // Clear all SMI_STS Status bits by writing '1' + // + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGroupInfo[GroupInd= ex].PadPerGroup); DwNum++) { + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupI= nfo[GroupIndex].SmiStsOffset + DwNum * 4), + 0xFFFFFFFF + ); + } + } + + // + // Check if group has NMI_STS register + // + if (GpioGroupInfo[GroupIndex].NmiStsOffset !=3D NO_REGISTER_FOR_PROPER= TY) { + // + // Clear all NMI_STS Status bits by writing '1' + // + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGroupInfo[GroupInd= ex].PadPerGroup); DwNum++) { + MmioWrite32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, GpioGroupI= nfo[GroupIndex].NmiStsOffset + DwNum * 4), + 0xFFFFFFFF + ); + } + } + + } +} + +/** + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG = structure. + Structure contains fields that can be used to configure each pad. + Pad not configured using GPIO_INIT_CONFIG will be left with hardware def= ault values. + Separate fields could be set to hardware default if it does not matter, = except + GpioPad and PadMode. + Function will work in most efficient way if pads which belong to the sam= e group are + placed in adjacent records of the table. + Although function can enable pads for Native mode, such programming is d= one + by reference code when enabling related silicon feature. + + @param[in] NumberofItem Number of GPIO pads to be updated + @param[in] GpioInitTableAddress GPIO initialization table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioConfigurePads ( + IN UINT32 NumberOfItems, + IN GPIO_INIT_CONFIG *GpioInitTableAddress + ) +{ + EFI_STATUS Status; + Status =3D GpioConfigurePch (NumberOfItems, GpioInitTableAddress); + GpioClearAllGpioInterrupts (); + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLi= b/GpioLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioL= ib/GpioLib.c new file mode 100644 index 0000000000..0be50f75df --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioL= ib.c @@ -0,0 +1,2710 @@ +/** @file + This file contains routines for GPIO + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "GpioLibrary.h" +#include + +/** + This procedure will check if GpioGroup argument is correct and + supplied DW reg number can be used for this group to access DW registers. + Function will check below conditions: + - Valid GpioGroup + - DwNum is has valid value for this group + + @param[in] Group GPIO group + @param[in] DwNum Register number for current group (parameter app= licable in accessing whole register). + For group which has less then 32 pads per group = DwNum must be 0. + + @retval TRUE DW Reg number and GpioGroup is valid + @retval FALSE DW Reg number and GpioGroup is invalid +**/ +STATIC +BOOLEAN +GpioIsGroupAndDwNumValid ( + IN GPIO_GROUP Group, + IN UINT32 DwNum + ) +{ + UINT32 GroupIndex; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + + if ((Group < GpioGetLowestGroup ()) || (Group > GpioGetHighestGroup ()) = || (GroupIndex >=3D GpioGroupInfoLength)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group argument (%d) is not within ra= nge of possible groups for this PCH\n", GroupIndex)); + goto Error; + } + + // + // Check if DwNum argument does not exceed number of DWord registers + // resulting from available pads for certain group + // + if (DwNum > GPIO_GET_DW_NUM (GpioGroupInfo[GroupIndex].PadPerGroup - 1)){ + goto Error; + } + + return TRUE; +Error: + ASSERT (FALSE); + return FALSE; +} + +// +// Possible registers to be accessed using GpioReadReg()/GpioWriteReg() fu= nctions +// +typedef enum { + GpioHostOwnershipRegister =3D 0, + GpioGpeEnableRegister, + GpioGpeStatusRegister, + GpioSmiEnableRegister, + GpioSmiStatusRegister, + GpioNmiEnableRegister, + GpioPadConfigLockRegister, + GpioPadLockOutputRegister +} GPIO_REG; + +/** + This procedure will read GPIO register + + @param[in] RegType GPIO register type + @param[in] Group GPIO group + @param[in] DwNum Register number for current group (param= eter applicable in accessing whole register). + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] ReadVal Read data +**/ +STATIC +VOID +GpioReadReg ( + IN GPIO_REG RegType, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *ReadVal + ) +{ + UINT32 RegOffset; + UINT32 GroupIndex; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + + RegOffset =3D NO_REGISTER_FOR_PROPERTY; + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + switch (RegType) { + case GpioHostOwnershipRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].HostOwnOffset; + break; + case GpioGpeEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].GpiGpeEnOffset; + break; + case GpioGpeStatusRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].GpiGpeStsOffset; + break; + case GpioSmiEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].SmiEnOffset; + break; + case GpioSmiStatusRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].SmiStsOffset; + break; + case GpioNmiEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].NmiEnOffset; + break; + case GpioPadConfigLockRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].PadCfgLockOffset; + break; + case GpioPadLockOutputRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].PadCfgLockTxOffset; + break; + default: + break; + } + + // + // Check if selected register exists + // + if (RegOffset =3D=3D NO_REGISTER_FOR_PROPERTY) { + *ReadVal =3D 0; + ASSERT (FALSE); + return; + } + + // + // If there are more then 32 pads per group then certain + // group information would be split into more then one DWord register. + // + if ((RegType =3D=3D GpioPadConfigLockRegister) || (RegType =3D=3D GpioPa= dLockOutputRegister)) { + // + // PadConfigLock and OutputLock registers when used for group containi= ng more than 32 pads + // are not placed in a continuous way, e.g: + // 0x0 - PadConfigLock_DW0 + // 0x4 - OutputLock_DW0 + // 0x8 - PadConfigLock_DW1 + // 0xC - OutputLock_DW1 + // + RegOffset +=3D DwNum * 0x8; + } else { + RegOffset +=3D DwNum * 0x4; + } + + *ReadVal =3D MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Comm= unity, RegOffset)); +} + +/** + This function determines if the group is SMI capable. + + @param[in] Group GPIO group + @param[in] DwNum Register number for current group (param= eter applicable in accessing whole register). + For group which has less then 32 pads pe= r group DwNum must be 0. + @retval TRUE The function completed successfully + @retval FALSE Setting SMI for a group is not supported +**/ +STATIC +BOOLEAN +GpioIsSmiSupportedByGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 Dw + ) +{ + UINT32 RegOffset; + UINT32 GroupIndex; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + RegOffset =3D GpioGroupInfo[GroupIndex].SmiStsOffset; + + // + // Check if selected register exists + // + if (RegOffset =3D=3D NO_REGISTER_FOR_PROPERTY) { + return FALSE; + } + + return TRUE; +} + +/** + This function determines if the group is NMI capable. + + @param[in] Group GPIO group + @param[in] DwNum Register number for current group (param= eter applicable in accessing whole register). + For group which has less then 32 pads pe= r group DwNum must be 0. + @retval TRUE The function completed successfully + @retval FALSE Setting NMI for a group is not supported +**/ +STATIC +BOOLEAN +GpioIsNmiSupportedByGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 Dw + ) +{ + UINT32 RegOffset; + UINT32 GroupIndex; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + RegOffset =3D GpioGroupInfo[GroupIndex].NmiEnOffset; + + // + // Check if selected register exists + // + if (RegOffset =3D=3D NO_REGISTER_FOR_PROPERTY) { + return FALSE; + } + + return TRUE; +} + +/** + This procedure will write GPIO register + + @param[in] RegType GPIO register type + @param[in] Group GPIO group + @param[in] DwNum Register number for current group (param= eter applicable in accessing whole register). + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] RegAndMask Mask which will be AND'ed with register = value + @param[in] RegOrMask Mask which will be OR'ed with register v= alue +**/ +STATIC +VOID +GpioWriteReg ( + IN GPIO_REG RegType, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 RegAndMask, + IN UINT32 RegOrMask + ) +{ + UINT32 RegOffset; + UINT32 GroupIndex; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 PadCfgLock; + BOOLEAN Lockable; + EFI_STATUS Status; + + Lockable =3D FALSE; + PadCfgLock =3D 0; + RegOffset =3D NO_REGISTER_FOR_PROPERTY; + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + switch (RegType) { + case GpioHostOwnershipRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].HostOwnOffset; + break; + case GpioGpeEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].GpiGpeEnOffset; + Lockable =3D TRUE; + break; + case GpioGpeStatusRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].GpiGpeStsOffset; + break; + case GpioSmiEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].SmiEnOffset; + Lockable =3D TRUE; + break; + case GpioSmiStatusRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].SmiStsOffset; + break; + case GpioNmiEnableRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].NmiEnOffset; + Lockable =3D TRUE; + break; + case GpioPadConfigLockRegister: + case GpioPadLockOutputRegister: + default: + break; + } + + // + // Check if selected register exists + // + if (RegOffset =3D=3D NO_REGISTER_FOR_PROPERTY) { + return; + } + + if (Lockable) { + GpioGetPadCfgLockForGroupDw (Group, DwNum, &PadCfgLock); + if (PadCfgLock) { + // + // Check if for pads which are going to be reconfigured lock is set. + // + if ((~RegAndMask | RegOrMask) & PadCfgLock) { + // + // Unlock all pads for this Group DW reg for simplicity + // even if not all of those pads will have their settings reprogra= mmed + // + Status =3D GpioUnlockPadCfgForGroupDw (Group, DwNum, PadCfgLock); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return; + } + } else { + // + // No need to perform an unlock as pads which are going to be reco= nfigured + // are not in locked state + // + PadCfgLock =3D 0; + } + } + } + + // + // If there are more then 32 pads per group then certain + // group information would be split into more then one DWord register. + // + RegOffset +=3D DwNum * 0x4; + + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, RegOffset), + RegAndMask, + RegOrMask + ); + + if (Lockable && PadCfgLock) { + // + // Lock previously unlocked pads + // + Status =3D GpioLockPadCfgForGroupDw (Group, DwNum, PadCfgLock); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return; + } + } +} + +/** + This procedure will write GPIO Lock/LockTx register using SBI. + + @param[in] RegType GPIO register (Lock or LockTx) + @param[in] Group GPIO group number + @param[in] DwNum Register number for current group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] LockRegAndMask Mask which will be AND'ed with Lock regi= ster value + @param[in] LockRegOrMask Mask which will be Or'ed with Lock regis= ter value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_UNSUPPORTED Feature is not supported for this group = or pad +**/ +STATIC +EFI_STATUS +GpioWriteLockReg ( + IN GPIO_REG RegType, + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 LockRegAndMask, + IN UINT32 LockRegOrMask + ) +{ + UINT8 Response; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 RegOffset; + UINT32 OldLockVal; + UINT32 NewLockVal; + UINT32 GroupIndex; + EFI_STATUS Status; + + OldLockVal =3D 0; + NewLockVal =3D 0; + + RegOffset =3D NO_REGISTER_FOR_PROPERTY; + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + switch (RegType) { + case GpioPadConfigLockRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].PadCfgLockOffset; + GpioGetPadCfgLockForGroupDw (Group, DwNum, &OldLockVal); + break; + case GpioPadLockOutputRegister: + RegOffset =3D GpioGroupInfo[GroupIndex].PadCfgLockTxOffset; + GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &OldLockVal); + break; + default: + break; + } + + // + // Check if selected register exists + // + if (RegOffset =3D=3D NO_REGISTER_FOR_PROPERTY) { + return EFI_UNSUPPORTED; + } + + // + // If there are more then 32 pads per group then certain + // group information would be split into more then one DWord register. + // PadConfigLock and OutputLock registers when used for group containing= more than 32 pads + // are not placed in a continuous way, e.g: + // 0x0 - PadConfigLock_DW0 + // 0x4 - OutputLock_DW0 + // 0x8 - PadConfigLock_DW1 + // 0xC - OutputLock_DW1 + // + RegOffset +=3D DwNum *0x8; + + NewLockVal =3D (OldLockVal & LockRegAndMask) | LockRegOrMask; + + Status =3D PchSbiExecutionEx ( + GpioGroupInfo[GroupIndex].Community, + RegOffset, + GpioLockUnlock, + FALSE, + 0x000F, + 0x0000, + 0x0000, + &NewLockVal, + &Response + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + This internal procedure will calculate GPIO_RESET_CONFIG value (new typ= e) + based on provided PadRstCfg for a specific GPIO Pad. + + @param[in] GpioPad GPIO Pad + @param[in] PadRstCfg GPIO PadRstCfg value + + @retval GpioResetConfig GPIO Reset configuration (new type) +**/ +GPIO_RESET_CONFIG +GpioResetConfigFromPadRstCfg ( + IN GPIO_PAD GpioPad, + IN UINT32 PadRstCfg + ) +{ + GPIO_GROUP Group; + + static GPIO_RESET_CONFIG GppPadRstCfgToGpioResetConfigMap[] =3D { + GpioResumeReset, + GpioHostDeepReset, + GpioPlatformReset}; + static GPIO_RESET_CONFIG GpdPadRstCfgToGpioResetConfigMap[] =3D { + GpioDswReset, + GpioHostDeepReset, + GpioPlatformReset, + GpioResumeReset}; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + + if (GpioIsDswGroup (Group) && PadRstCfg < 4) { + return GpdPadRstCfgToGpioResetConfigMap[PadRstCfg]; + } else if (PadRstCfg < 3) { + return GppPadRstCfgToGpioResetConfigMap[PadRstCfg]; + } else { + ASSERT (FALSE); + return GpioResetDefault; + } +} + +/** + This internal procedure will calculate PadRstCfg register value based + on provided GPIO Reset configuration for a certain pad. + + @param[in] GpioPad GPIO Pad + @param[in] GpioResetConfig GPIO Reset configuration + @param[out] PadRstCfg GPIO PadRstCfg value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid configuration +**/ +EFI_STATUS +GpioPadRstCfgFromResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG GpioResetConfig, + OUT UINT32 *PadRstCfg + ) +{ + GPIO_GROUP Group; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + + switch (GpioResetConfig) { + case GpioResetDefault: + *PadRstCfg =3D 0x0; + break; + case GpioHostDeepReset: + *PadRstCfg =3D V_GPIO_PCR_RST_CONF_DEEP_RST; + break; + case GpioPlatformReset: + *PadRstCfg =3D V_GPIO_PCR_RST_CONF_GPIO_RST; + break; + case GpioResumeReset: + if (GpioIsDswGroup (Group)) { + *PadRstCfg =3D V_GPIO_PCR_RST_CONF_RESUME_RST; + } else { + *PadRstCfg =3D V_GPIO_PCR_RST_CONF_POW_GOOD; + } + break; + case GpioDswReset: + if (GpioIsDswGroup (Group)) { + *PadRstCfg =3D V_GPIO_PCR_RST_CONF_POW_GOOD; + } else { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Only GPD group pads can use Gpio= DswReset: %a\n", GpioName (GpioPad))); + goto Error; + } + break; + default: + goto Error; + } + + return EFI_SUCCESS; +Error: + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; +} + +/** + This internal procedure will get GPIO_CONFIG data from PADCFG registers = value + + @param[in] GpioPad GPIO Pad + @param[in] PadCfgDwReg PADCFG DWx register values + @param[out] GpioData GPIO Configuration data + + @retval Status +**/ +STATIC +VOID +GpioConfigFromPadCfgRegValue ( + IN GPIO_PAD GpioPad, + IN CONST UINT32 *PadCfgDwReg, + OUT GPIO_CONFIG *GpioConfig + ) +{ + UINT32 PadRstCfg; + + // + // Get Reset Type (PadRstCfg) + // + PadRstCfg =3D (PadCfgDwReg[0] & B_GPIO_PCR_RST_CONF) >> N_GPIO_PCR_RST_C= ONF; + + GpioConfig->PowerConfig =3D GpioResetConfigFromPadRstCfg ( + GpioPad, + PadRstCfg + ); + + // + // Get how interrupt is triggered (RxEvCfg) + // + GpioConfig->InterruptConfig =3D ((PadCfgDwReg[0] & B_GPIO_PCR_RX_LVL_EDG= ) >> (N_GPIO_PCR_RX_LVL_EDG - (N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS + 1))) | = (0x1 << N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS); + + // + // Get interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI) + // + GpioConfig->InterruptConfig |=3D ((PadCfgDwReg[0] & (B_GPIO_PCR_RX_NMI_R= OUTE | B_GPIO_PCR_RX_SCI_ROUTE | B_GPIO_PCR_RX_SMI_ROUTE | B_GPIO_PCR_RX_AP= IC_ROUTE)) >> (N_GPIO_PCR_RX_NMI_ROUTE - (N_GPIO_INT_CONFIG_INT_SOURCE_BIT_= POS + 1))) | (0x1 << N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS); + + // + // Get GPIO direction (GPIORxDis and GPIOTxDis) + // + GpioConfig->Direction =3D ((PadCfgDwReg[0] & (B_GPIO_PCR_RXDIS | B_GPIO_= PCR_TXDIS)) >> (N_GPIO_PCR_TXDIS - (N_GPIO_DIRECTION_DIR_BIT_POS + 1))) | (= 0x1 << N_GPIO_DIRECTION_DIR_BIT_POS); + + // + // Get GPIO input inversion (RXINV) + // (Only meaningful if input enabled) + // + if((PadCfgDwReg[0] & B_GPIO_PCR_RXDIS) =3D=3D 0) { + GpioConfig->Direction |=3D ((PadCfgDwReg[0] & B_GPIO_PCR_RXINV) >> (N_= GPIO_PCR_RXINV - (N_GPIO_DIRECTION_INV_BIT_POS + 1))) | (0x1 << N_GPIO_DIRE= CTION_INV_BIT_POS); + } + + // + // Get GPIO output state (GPIOTxState) + // + GpioConfig->OutputState =3D ((PadCfgDwReg[0] & B_GPIO_PCR_TX_STATE) << (= N_GPIO_PCR_TX_STATE + (N_GPIO_OUTPUT_BIT_POS + 1))) | (0x1 << N_GPIO_OUTPUT= _BIT_POS); + + // + // Configure GPIO RX raw override to '1' (RXRAW1) + // + GpioConfig->OtherSettings =3D ((PadCfgDwReg[0] & B_GPIO_PCR_RX_RAW1) >> = (N_GPIO_PCR_RX_RAW1 - (N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS + 1))) | (0x1 << N= _GPIO_OTHER_CONFIG_RXRAW_BIT_POS); + + // + // Get GPIO Pad Mode (PMode) + // + GpioConfig->PadMode =3D ((PadCfgDwReg[0] & B_GPIO_PCR_PAD_MODE) >> (N_GP= IO_PCR_PAD_MODE - (N_GPIO_PAD_MODE_BIT_POS + 1))) | (0x1 << N_GPIO_PAD_MODE= _BIT_POS); + + // + // Get GPIO termination (Term) + // + GpioConfig->ElectricalConfig =3D ((PadCfgDwReg[1] & B_GPIO_PCR_TERM) >> = (N_GPIO_PCR_TERM - (N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS + 1))) | (= 0x1 << N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS); +} + +/** + This procedure will read multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[out] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadConfig ( + IN GPIO_PAD GpioPad, + OUT GPIO_CONFIG *GpioData + ) +{ + UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER]; + UINT32 RegVal; + GPIO_GROUP Group; + UINT32 PadNumber; + UINT32 PadBitPosition; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + PadBitPosition =3D GPIO_GET_PAD_POSITION (PadNumber); + + if (!GpioIsPadValid (GpioPad)) { + return EFI_UNSUPPORTED; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + // + // Read PADCFG DW0 register + // + PadCfgDwReg[0] =3D GpioReadPadCfgReg (GpioPad, 0); + + // + // Read PADCFG DW1 register + // + PadCfgDwReg[1] =3D GpioReadPadCfgReg (GpioPad, 1); + + // + // Read PADCFG DW2 register + // + PadCfgDwReg[2] =3D GpioReadPadCfgReg (GpioPad, 2); + + GpioConfigFromPadCfgRegValue ( + GpioPad, + PadCfgDwReg, + GpioData + ); + + // + // Read HOSTSW_OWN registers + // + GpioReadReg ( + GpioHostOwnershipRegister, + Group, + GPIO_GET_DW_NUM (PadNumber), + &RegVal + ); + + // + // Get Host Software Ownership + // + GpioData->HostSoftPadOwn =3D (((RegVal >> PadBitPosition) & 0x1) << (N_G= PIO_HOSTSW_OWN_BIT_POS + 1)) | (0x1 << N_GPIO_HOSTSW_OWN_BIT_POS); + + // + // Read PADCFGLOCK register + // + GpioReadReg ( + GpioPadConfigLockRegister, + Group, + GPIO_GET_DW_NUM (PadNumber), + &RegVal + ); + + // + // Get Pad Configuration Lock state + // + GpioData->LockConfig =3D ((!((RegVal >> PadBitPosition) & 0x1)) << 1) | = 0x1; + + // + // Read PADCFGLOCKTX register + // + GpioReadReg ( + GpioPadLockOutputRegister, + Group, + GPIO_GET_DW_NUM (PadNumber), + &RegVal + ); + + // + // Get Pad Configuration Lock Tx state + // + GpioData->LockConfig |=3D ((!((RegVal >> PadBitPosition) & 0x1)) << 2) |= 0x1; + + return EFI_SUCCESS; +} + +/** + This procedure will calculate PADCFG register value based on GpioConfig = data + + @param[in] GpioPad GPIO Pad + @param[in] GpioConfig GPIO Configuration data + @param[out] PadCfgDwReg PADCFG DWx register value + @param[out] PadCfgDwRegMask Mask with PADCFG DWx register bits= to be modified +**/ +VOID +GpioPadCfgRegValueFromGpioConfig ( + IN GPIO_PAD GpioPad, + IN CONST GPIO_CONFIG *GpioConfig, + OUT UINT32 *PadCfgDwReg, + OUT UINT32 *PadCfgDwRegMask + ) +{ + UINT32 PadRstCfg; + EFI_STATUS Status; + + // + // Configure Reset Type (PadRstCfg) + // Reset configuration depends on group type. + // This field requires support for new and deprecated settings. + // + Status =3D GpioPadRstCfgFromResetConfig ( + GpioPad, + GpioConfig->PowerConfig, + &PadRstCfg + ); + if (EFI_ERROR (Status)) { + return; + } + + PadCfgDwRegMask[0] |=3D ((((GpioConfig->PowerConfig & B_GPIO_RESET_CONFI= G_RESET_MASK) >> N_GPIO_RESET_CONFIG_RESET_BIT_POS) =3D=3D GpioHardwareDefa= ult) ? 0x0 : B_GPIO_PCR_RST_CONF); + PadCfgDwReg[0] |=3D PadRstCfg << N_GPIO_PCR_RST_CONF; + + // + // Configure how interrupt is triggered (RxEvCfg) + // + PadCfgDwRegMask[0] |=3D ((((GpioConfig->InterruptConfig & B_GPIO_INT_CON= FIG_INT_TYPE_MASK) >> N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS) =3D=3D GpioHardwa= reDefault) ? 0x0 : B_GPIO_PCR_RX_LVL_EDG); + PadCfgDwReg[0] |=3D (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_I= NT_TYPE_MASK) >> (N_GPIO_INT_CONFIG_INT_TYPE_BIT_POS + 1)) << N_GPIO_PCR_RX= _LVL_EDG); + + // + // Configure interrupt generation (GPIRoutIOxAPIC/SCI/SMI/NMI) + // + PadCfgDwRegMask[0] |=3D ((((GpioConfig->InterruptConfig & B_GPIO_INT_CON= FIG_INT_SOURCE_MASK) >> N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS) =3D=3D GpioHa= rdwareDefault) ? 0x0 : (B_GPIO_PCR_RX_NMI_ROUTE | B_GPIO_PCR_RX_SCI_ROUTE = | B_GPIO_PCR_RX_SMI_ROUTE | B_GPIO_PCR_RX_APIC_ROUTE)); + PadCfgDwReg[0] |=3D (((GpioConfig->InterruptConfig & B_GPIO_INT_CONFIG_I= NT_SOURCE_MASK) >> (N_GPIO_INT_CONFIG_INT_SOURCE_BIT_POS + 1)) << N_GPIO_PC= R_RX_NMI_ROUTE); + + // + // Configure GPIO direction (GPIORxDis and GPIOTxDis) + // + PadCfgDwRegMask[0] |=3D ((((GpioConfig->Direction & B_GPIO_DIRECTION_DIR= _MASK) >> N_GPIO_DIRECTION_DIR_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 := (B_GPIO_PCR_RXDIS | B_GPIO_PCR_TXDIS)); + PadCfgDwReg[0] |=3D (((GpioConfig->Direction & B_GPIO_DIRECTION_DIR_MASK= ) >> (N_GPIO_DIRECTION_DIR_BIT_POS + 1)) << N_GPIO_PCR_TXDIS); + + // + // Configure GPIO input inversion (RXINV) + // + PadCfgDwRegMask[0] |=3D ((((GpioConfig->Direction & B_GPIO_DIRECTION_INV= _MASK) >> N_GPIO_DIRECTION_INV_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 = : B_GPIO_PCR_RXINV); + PadCfgDwReg[0] |=3D (((GpioConfig->Direction & B_GPIO_DIRECTION_INV_MASK= ) >> (N_GPIO_DIRECTION_INV_BIT_POS + 1)) << N_GPIO_PCR_RXINV); + + // + // Configure GPIO output state (GPIOTxState) + // + PadCfgDwRegMask[0] |=3D ((((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK= ) >> N_GPIO_OUTPUT_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_= TX_STATE); + PadCfgDwReg[0] |=3D (((GpioConfig->OutputState & B_GPIO_OUTPUT_MASK) >> = (N_GPIO_OUTPUT_BIT_POS + 1)) << N_GPIO_PCR_TX_STATE); + + // + // Configure GPIO RX raw override to '1' (RXRAW1) + // + PadCfgDwRegMask[0] |=3D ((((GpioConfig->OtherSettings & B_GPIO_OTHER_CON= FIG_RXRAW_MASK) >> N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS) =3D=3D GpioHardwareDe= fault) ? 0x0 : B_GPIO_PCR_RX_RAW1); + PadCfgDwReg[0] |=3D (((GpioConfig->OtherSettings & B_GPIO_OTHER_CONFIG_R= XRAW_MASK) >> (N_GPIO_OTHER_CONFIG_RXRAW_BIT_POS + 1)) << N_GPIO_PCR_RX_RAW= 1); + + // + // Configure GPIO Pad Mode (PMode) + // + PadCfgDwRegMask[0] |=3D ((((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) = >> N_GPIO_PAD_MODE_BIT_POS) =3D=3D GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_= PAD_MODE); + PadCfgDwReg[0] |=3D (((GpioConfig->PadMode & B_GPIO_PAD_MODE_MASK) >> (N= _GPIO_PAD_MODE_BIT_POS + 1)) << N_GPIO_PCR_PAD_MODE); + + // + // Configure GPIO termination (Term) + // + PadCfgDwRegMask[1] |=3D ((((GpioConfig->ElectricalConfig & B_GPIO_ELECTR= ICAL_CONFIG_TERMINATION_MASK) >> N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_P= OS) =3D=3D GpioHardwareDefault) ? 0x0 : B_GPIO_PCR_TERM); + PadCfgDwReg[1] |=3D (((GpioConfig->ElectricalConfig & B_GPIO_ELECTRICAL_= CONFIG_TERMINATION_MASK) >> (N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS += 1)) << N_GPIO_PCR_TERM); +} + +/** + This procedure will configure multiple GPIO settings + + @param[in] GpioPad GPIO Pad + @param[in] GpioData GPIO data structure + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_CONFIG *GpioData + ) +{ + EFI_STATUS Status; + UINT32 PadCfgDwReg[GPIO_PADCFG_DW_REG_NUMBER]; + UINT32 PadCfgDwRegMask[GPIO_PADCFG_DW_REG_NUMBER]; + UINT32 HostSoftOwnReg; + UINT32 HostSoftOwnRegMask; + UINT32 GpiGpeEnReg; + UINT32 GpiGpeEnRegMask; + UINT32 GpiNmiEnReg; + UINT32 GpiNmiEnRegMask; + UINT32 GpiSmiEnReg; + UINT32 GpiSmiEnRegMask; + GPIO_GROUP Group; + UINT32 GroupIndex; + UINT32 PadNumber; + UINT32 PadBitPosition; + UINT32 DwNum; + GPIO_LOCK_CONFIG LockConfig; + + Status =3D EFI_SUCCESS; + ZeroMem (PadCfgDwReg, sizeof (PadCfgDwReg)); + ZeroMem (PadCfgDwRegMask, sizeof (PadCfgDwRegMask)); + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + PadBitPosition =3D GPIO_GET_PAD_POSITION (PadNumber); + DwNum =3D GPIO_GET_DW_NUM (PadNumber); + + if (!GpioIsPadValid (GpioPad)) { + return EFI_UNSUPPORTED; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + // + // Check if Pad enabled for SCI is to be in unlocked state + // + if (((GpioData->InterruptConfig & GpioIntSci) =3D=3D GpioIntSci) && + ((GpioData->LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK) !=3D= GpioPadConfigUnlock)){ + DEBUG ((DEBUG_ERROR, "GPIO ERROR: %a for SCI is not unlocked!\n", Gpio= Name (GpioPad))); + return EFI_INVALID_PARAMETER; + } + + // + // Get GPIO PADCFG register value from GPIO config data + // + GpioPadCfgRegValueFromGpioConfig ( + GpioPad, + GpioData, + PadCfgDwReg, + PadCfgDwRegMask + ); + + // + // Write PADCFG DW0 register + // + GpioWritePadCfgReg ( + GpioPad, + 0, + ~PadCfgDwRegMask[0], + PadCfgDwReg[0] + ); + + // + // Write PADCFG DW1 register + // + GpioWritePadCfgReg ( + GpioPad, + 1, + ~PadCfgDwRegMask[1], + PadCfgDwReg[1] + ); + + // + // Write PADCFG DW2 register + // + GpioWritePadCfgReg ( + GpioPad, + 2, + ~PadCfgDwRegMask[2], + PadCfgDwReg[2] + ); + + // + // Update value to be programmed in HOSTSW_OWN register + // + if ((GpioData->InterruptConfig & GpioIntSmi) =3D=3D GpioIntSmi) { + HostSoftOwnRegMask =3D 1 << PadBitPosition; + HostSoftOwnReg =3D 1 << PadBitPosition; + } else { + HostSoftOwnRegMask =3D (GpioData->HostSoftPadOwn & 0x1) << PadBitPosit= ion; + HostSoftOwnReg =3D (GpioData->HostSoftPadOwn >> 0x1) << PadBitPosition; + } + + // + // Write HOSTSW_OWN registers + // + GpioWriteReg ( + GpioHostOwnershipRegister, + Group, + DwNum, + ~HostSoftOwnRegMask, + HostSoftOwnReg + ); + + // + // Update value to be programmed in GPI_GPE_EN register + // + GpiGpeEnRegMask =3D (GpioData->InterruptConfig & 0x1) << PadBitPosition; + GpiGpeEnReg =3D ((GpioData->InterruptConfig & GpioIntSci) >> 3) << PadBi= tPosition; + + // + // Write GPI_GPE_EN registers + // + GpioWriteReg ( + GpioGpeEnableRegister, + Group, + DwNum, + ~GpiGpeEnRegMask, + GpiGpeEnReg + ); + + // + // Update value to be programmed in GPI_NMI_EN register + // + GpiNmiEnRegMask =3D (GpioData->InterruptConfig & 0x1) << PadBitPosition; + GpiNmiEnReg =3D ((GpioData->InterruptConfig & GpioIntNmi) >> 1) << PadBi= tPosition; + + if (GpioIsNmiSupportedByGroupDw (Group, DwNum)) { + GpioWriteReg ( + GpioNmiEnableRegister, + Group, + DwNum, + ~GpiNmiEnRegMask, + GpiNmiEnReg + ); + } else { + if (GpiNmiEnReg =3D=3D 0) { + // + // Not all GPIO have NMI capabilities. Since we always try to progra= m this register, + // even when not enabling NMI for a pad so do not report such access= as an error + // + Status =3D EFI_SUCCESS; + } else { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %a has no pads supporting NM= I\n", GpioGetGroupName (GroupIndex))); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + } + + // + // Update value to be programmed in GPI_SMI_EN register + // + GpiSmiEnRegMask =3D (GpioData->InterruptConfig & 0x1) << PadBitPosition; + GpiSmiEnReg =3D ((GpioData->InterruptConfig & GpioIntSmi) >> 2) << PadBi= tPosition; + + if (GpioIsSmiSupportedByGroupDw (Group, DwNum)) { + GpioWriteReg ( + GpioSmiEnableRegister, + Group, + DwNum, + ~GpiSmiEnRegMask, + GpiSmiEnReg + ); + } else { + if (GpiSmiEnReg =3D=3D 0) { + // + // Not all GPIO have SMI capabilities. Since we always try to progra= m this register, + // even when not enabling SMI for a pad so do not report such access= as an error + // + Status =3D EFI_SUCCESS; + } else { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %a has no pads supporting SM= I\n", GpioGetGroupName (GroupIndex))); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + } + + // + // Store unlock data + // + if (GpioData->LockConfig !=3D GpioLockDefault) { + LockConfig =3D GpioData->LockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK= _MASK; + // + // If pad in GpioMode is an output default action should be to leave o= utput unlocked + // + if ((GpioData->PadMode =3D=3D GpioPadModeGpio) && + (GpioData->Direction =3D=3D GpioDirOut) && + ((GpioData->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) =3D=3D= GpioLockDefault)) { + LockConfig |=3D GpioOutputStateUnlock; + } else { + LockConfig |=3D GpioData->LockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOC= K_MASK; + } + Status =3D GpioStoreUnlockData (GpioPad, LockConfig); + } + + return Status; +} + +/** + This procedure will set GPIO output level + + @param[in] GpioPad GPIO pad + @param[in] Value Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetOutputValue ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + if (Value > 1) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + GpioWritePadCfgReg ( + GpioPad, + 0, + (UINT32)~B_GPIO_PCR_TX_STATE, + Value << N_GPIO_PCR_TX_STATE + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO output level + + @param[in] GpioPad GPIO pad + @param[out] OutputVal GPIO Output value + 0: OutputLow, 1: OutputHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetOutputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *OutputVal + ) +{ + UINT32 PadCfgReg; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + PadCfgReg =3D GpioReadPadCfgReg (GpioPad, 0); + + *OutputVal =3D (PadCfgReg & B_GPIO_PCR_TX_STATE) >> N_GPIO_PCR_TX_STATE; + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO input level + + @param[in] GpioPad GPIO pad + @param[out] InputVal GPIO Input value + 0: InputLow, 1: InpuHigh + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetInputValue ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InputVal + ) +{ + UINT32 PadCfgReg; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + PadCfgReg =3D GpioReadPadCfgReg (GpioPad, 0); + + *InputVal =3D (PadCfgReg & B_GPIO_PCR_RX_STATE) >> N_GPIO_PCR_RX_STATE; + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO IOxAPIC interrupt number + + @param[in] GpioPad GPIO pad + @param[out] IrqNum IRQ number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadIoApicIrqNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *IrqNum + ) +{ + UINT32 PadCfgReg; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + PadCfgReg =3D GpioReadPadCfgReg (GpioPad, 1); + + *IrqNum =3D (PadCfgReg & B_GPIO_PCR_INTSEL) >> N_GPIO_PCR_INTSEL; + + return EFI_SUCCESS; +} + +/** + This procedure will configure GPIO input inversion + + @param[in] GpioPad GPIO pad + @param[in] Value Value for GPIO input inversion + 0: No input inversion, 1: Invert input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetInputInversion ( + IN GPIO_PAD GpioPad, + IN UINT32 Value + ) +{ + if (Value > 1) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + GpioWritePadCfgReg ( + GpioPad, + 0, + (UINT32)~B_GPIO_PCR_RXINV, + Value << N_GPIO_PCR_RXINV + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO pad input inversion value + + @param[in] GpioPad GPIO pad + @param[out] InvertState GPIO inversion state + 0: No input inversion, 1: Inverted input + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetInputInversion ( + IN GPIO_PAD GpioPad, + OUT UINT32 *InvertState + ) +{ + UINT32 PadCfgReg; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + PadCfgReg =3D GpioReadPadCfgReg (GpioPad, 0); + + *InvertState =3D (PadCfgReg & B_GPIO_PCR_RXINV) >> N_GPIO_PCR_RXINV; + return EFI_SUCCESS; +} + +/** + This procedure will set GPIO interrupt settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Level/Edge + use GPIO_INT_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadInterruptConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_INT_CONFIG Value + ) +{ + EFI_STATUS Status; + BOOLEAN IsNmiSupported; + UINT32 RxLvlEdgeValue; + UINT32 IntRouteValue; + UINT32 PadNumber; + UINT32 GpeEnable; + UINT32 NmiEnable; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + Status =3D EFI_SUCCESS; + + if (((Value & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> N_GPIO_INT_CONFIG_INT_= TYPE_BIT_POS) !=3D GpioHardwareDefault) { + RxLvlEdgeValue =3D ((Value & B_GPIO_INT_CONFIG_INT_TYPE_MASK) >> (N_GP= IO_INT_CONFIG_INT_TYPE_BIT_POS + 1)) << N_GPIO_PCR_RX_LVL_EDG; + + GpioWritePadCfgReg ( + GpioPad, + 0, + (UINT32)~B_GPIO_PCR_RX_LVL_EDG, + RxLvlEdgeValue + ); + } + + if (((Value & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> N_GPIO_INT_CONFIG_IN= T_SOURCE_BIT_POS) !=3D GpioHardwareDefault) { + + IntRouteValue =3D ((Value & B_GPIO_INT_CONFIG_INT_SOURCE_MASK) >> (N_G= PIO_INT_CONFIG_INT_SOURCE_BIT_POS + 1)) << N_GPIO_PCR_RX_NMI_ROUTE; + + GpioWritePadCfgReg ( + GpioPad, + 0, + (UINT32)~(B_GPIO_PCR_RX_NMI_ROUTE | B_GPIO_PCR_RX_SCI_ROUTE | B_GPIO= _PCR_RX_SMI_ROUTE | B_GPIO_PCR_RX_APIC_ROUTE), + IntRouteValue + ); + + if ((Value & GpioIntSci) =3D=3D GpioIntSci) { + GpeEnable =3D 0x1; + } else { + GpeEnable =3D 0x0; + } + + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioWriteReg ( + GpioGpeEnableRegister, + GpioGetGroupFromGpioPad (GpioPad), + GPIO_GET_DW_NUM (PadNumber), + ~(1 << GPIO_GET_PAD_POSITION (PadNumber)), + GpeEnable << GPIO_GET_PAD_POSITION (PadNumber) + ); + + if ((Value & GpioIntNmi) =3D=3D GpioIntNmi) { + NmiEnable =3D 0x1; + } else { + NmiEnable =3D 0x0; + } + + IsNmiSupported =3D GpioIsNmiSupportedByGroupDw ( + GpioGetGroupFromGpioPad (GpioPad), + GPIO_GET_DW_NUM (PadNumber) + ); + if (IsNmiSupported) { + GpioWriteReg ( + GpioNmiEnableRegister, + GpioGetGroupFromGpioPad (GpioPad), + GPIO_GET_DW_NUM (PadNumber), + ~(1 << GPIO_GET_PAD_POSITION (PadNumber)), + NmiEnable << GPIO_GET_PAD_POSITION (PadNumber) + ); + } else { + if (NmiEnable =3D=3D 0) { + // + // Not all GPIO have NMI capabilities. Since we always try to prog= ram this register, + // even when not enabling NMI for a pad so do not report such acce= ss as an error + // + return EFI_SUCCESS; + } else { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Group %a has no pads supporting = NMI\n", GpioGetGroupName (GpioGetGroupIndexFromGpioPad (GpioPad)))); + ASSERT (FALSE); + } + } + } + + return Status; +} + +/** + This procedure will set GPIO electrical settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of termination + use GPIO_ELECTRICAL_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadElectricalConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_ELECTRICAL_CONFIG Value + ) +{ + UINT32 TermValue; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + if (((Value & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> N_GPIO_ELECT= RICAL_CONFIG_TERMINATION_BIT_POS) !=3D GpioHardwareDefault) { + TermValue =3D ((Value & B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK) >> = (N_GPIO_ELECTRICAL_CONFIG_TERMINATION_BIT_POS + 1)) << N_GPIO_PCR_TERM; + + GpioWritePadCfgReg ( + GpioPad, + 1, + (UINT32)~B_GPIO_PCR_TERM, + TermValue + ); + } + + return EFI_SUCCESS; +} + +/** + This procedure will set GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value for Pad Reset Configuration + use GPIO_RESET_CONFIG as argument + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG Value + ) +{ + UINT32 PadRstCfg; + EFI_STATUS Status; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + if (((Value & B_GPIO_RESET_CONFIG_RESET_MASK) >> N_GPIO_RESET_CONFIG_RES= ET_BIT_POS) !=3D GpioHardwareDefault) { + + // + // Reset configuration depends on group type. + // This field requires support for new and deprecated settings. + // + Status =3D GpioPadRstCfgFromResetConfig ( + GpioPad, + Value, + &PadRstCfg + ); + if (EFI_ERROR (Status)) { + return Status; + } + GpioWritePadCfgReg ( + GpioPad, + 0, + (UINT32)~B_GPIO_PCR_RST_CONF, + PadRstCfg << N_GPIO_PCR_RST_CONF + ); + } + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO Reset settings + + @param[in] GpioPad GPIO pad + @param[in] Value Value of Pad Reset Configuration + based on GPIO_RESET_CONFIG + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadResetConfig ( + IN GPIO_PAD GpioPad, + IN GPIO_RESET_CONFIG *Value + ) +{ + UINT32 PadRstCfg; + UINT32 PadCfgDw0Reg; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + PadCfgDw0Reg =3D GpioReadPadCfgReg (GpioPad, 0); + + // + // Get Reset Type (PadRstCfg) + // + PadRstCfg =3D (PadCfgDw0Reg & B_GPIO_PCR_RST_CONF) >> N_GPIO_PCR_RST_CON= F; + + *Value =3D GpioResetConfigFromPadRstCfg ( + GpioPad, + PadRstCfg + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *HostSwRegVal + ) +{ + if (!GpioIsGroupAndDwNumValid (Group, DwNum)) { + return EFI_INVALID_PARAMETER; + } + + GpioReadReg ( + GpioHostOwnershipRegister, + Group, + DwNum, + HostSwRegVal + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO Host Software Pad Ownership for certain gro= up + + @param[in] Group GPIO group + @param[in] DwNum Host Ownership register number for curre= nt group + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] HostSwRegVal Value of Host Software Pad Ownership reg= ister + Bit position - PadNumber + Bit value - 0: ACPI Mode, 1: GPIO Driver= mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioSetHostSwOwnershipForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 HostSwRegVal + ) +{ + if (!GpioIsGroupAndDwNumValid (Group, DwNum)) { + return EFI_INVALID_PARAMETER; + } + + GpioWriteReg ( + GpioHostOwnershipRegister, + Group, + DwNum, + 0, + HostSwRegVal + ); + return EFI_SUCCESS; +} + +/** + This procedure will get Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadHostSwOwn Value of Host Software Pad Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadHostSwOwn + ) +{ + UINT32 PadNumber; + UINT32 HostSwRegVal; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioReadReg ( + GpioHostOwnershipRegister, + GpioGetGroupFromGpioPad (GpioPad), + GPIO_GET_DW_NUM (PadNumber), + &HostSwRegVal + ); + + *PadHostSwOwn =3D (HostSwRegVal >> GPIO_GET_PAD_POSITION (PadNumber)) & = 0x1; + + return EFI_SUCCESS; +} + +/** + This procedure will set Gpio Pad Host Software Ownership + + @param[in] GpioPad GPIO pad + @param[in] PadHostSwOwn Pad Host Software Owner + 0: ACPI Mode, 1: GPIO Driver mode + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioSetHostSwOwnershipForPad ( + IN GPIO_PAD GpioPad, + IN UINT32 PadHostSwOwn + ) +{ + UINT32 PadNumber; + + if (!GpioIsPadValid (GpioPad) || (PadHostSwOwn > 1)) { + return EFI_INVALID_PARAMETER; + } + + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioWriteReg ( + GpioHostOwnershipRegister, + GpioGetGroupFromGpioPad (GpioPad), + GPIO_GET_DW_NUM (PadNumber), + (UINT32)~(1 << GPIO_GET_PAD_POSITION (PadNumber)), + PadHostSwOwn << GPIO_GET_PAD_POSITION (PadNumber) + ); + + return EFI_SUCCESS; +} + +/** + This procedure will get Gpio Pad Ownership + + @param[in] GpioPad GPIO pad + @param[out] PadOwnVal Value of Pad Ownership + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadOwnership ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_OWN *PadOwnVal + ) +{ + UINT32 Mask; + UINT32 RegOffset; + UINT32 GroupIndex; + UINT32 PadNumber; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 PadOwnRegValue; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Calculate RegOffset using Pad Ownership offset and GPIO Pad number. + // One DWord register contains information for 8 pads. + // + RegOffset =3D GpioGroupInfo[GroupIndex].PadOwnOffset + (PadNumber >> 3) = * 0x4; + + // + // Calculate pad bit position within DWord register + // + PadNumber %=3D 8; + Mask =3D (BIT1 | BIT0) << (PadNumber * 4); + + PadOwnRegValue =3D MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex= ].Community, RegOffset)); + + *PadOwnVal =3D (GPIO_PAD_OWN) ((PadOwnRegValue & Mask) >> (PadNumber * 4= )); + + return EFI_SUCCESS; +} + +/** + This procedure will check state of Pad Config Lock for pads within one g= roup + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockRegVal Value of PadCfgLock register + Bit position - PadNumber + Bit value - 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockRegVal + ) +{ + if (!GpioIsGroupAndDwNumValid (Group, DwNum)) { + return EFI_INVALID_PARAMETER; + } + + GpioReadReg ( + GpioPadConfigLockRegister, + Group, + DwNum, + PadCfgLockRegVal + ); + + return EFI_SUCCESS; +} + +/** + This procedure will check state of Pad Config Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLock for selected pad + 0: NotLocked, 1: Locked + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadCfgLock ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLock + ) +{ + UINT32 PadNumber; + UINT32 PadCfgLockRegVal; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioReadReg ( + GpioPadConfigLockRegister, + GpioGetGroupFromGpioPad (GpioPad), + GPIO_GET_DW_NUM (PadNumber), + &PadCfgLockRegVal + ); + + *PadCfgLock =3D (PadCfgLockRegVal >> GPIO_GET_PAD_POSITION (PadNumber)) = & 0x1; + + return EFI_SUCCESS; +} + +/** + This procedure will check state of Pad Config Tx Lock for pads within on= e group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register + Bit position - PadNumber + Bit value - 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioGetPadCfgLockTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + OUT UINT32 *PadCfgLockTxRegVal + ) +{ + if (!GpioIsGroupAndDwNumValid (Group, DwNum)) { + return EFI_INVALID_PARAMETER; + } + + GpioReadReg ( + GpioPadLockOutputRegister, + Group, + DwNum, + PadCfgLockTxRegVal + ); + + return EFI_SUCCESS; +} + +/** + This procedure will check state of Pad Config Tx Lock for selected pad + + @param[in] GpioPad GPIO pad + @param[out] PadCfgLock PadCfgLockTx for selected pad + 0: NotLockedTx, 1: LockedTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadCfgLockTx ( + IN GPIO_PAD GpioPad, + OUT UINT32 *PadCfgLockTx + ) +{ + UINT32 PadNumber; + UINT32 PadCfgLockTxRegVal; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioReadReg ( + GpioPadLockOutputRegister, + GpioGetGroupFromGpioPad (GpioPad), + GPIO_GET_DW_NUM (PadNumber), + &PadCfgLockTxRegVal + ); + + *PadCfgLockTx =3D (PadCfgLockTxRegVal >> GPIO_GET_PAD_POSITION (PadNumbe= r)) & 0x1; + + return EFI_SUCCESS; +} + +/** + This procedure will clear PadCfgLock for selected pads within one group. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlock Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnlock, 1: Unlock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlock + ) +{ + if (!GpioIsGroupAndDwNumValid (Group, DwNum)) { + return EFI_INVALID_PARAMETER; + } + + return GpioWriteLockReg ( + GpioPadConfigLockRegister, + Group, + DwNum, + ~PadsToUnlock, + 0 + ); +} + +/** + This procedure will clear PadCfgLock for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfg ( + IN GPIO_PAD GpioPad + ) +{ + GPIO_GROUP Group; + UINT32 PadNumber; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + return GpioUnlockPadCfgForGroupDw ( + Group, + GPIO_GET_DW_NUM (PadNumber), + 1 << GPIO_GET_PAD_POSITION (PadNumber) + ); +} + +/** + This procedure will set PadCfgLock for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLock Bitmask for pads which are going to be l= ocked + Bit position - PadNumber + Bit value - 0: DoNotLock, 1: Lock + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLock + ) +{ + if (!GpioIsGroupAndDwNumValid (Group, DwNum)) { + return EFI_INVALID_PARAMETER; + } + + return GpioWriteLockReg ( + GpioPadConfigLockRegister, + Group, + DwNum, + ~0u, + PadsToLock + ); +} + +/** + This procedure will set PadCfgLock for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfg ( + IN GPIO_PAD GpioPad + ) +{ + GPIO_GROUP Group; + UINT32 PadNumber; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + return GpioLockPadCfgForGroupDw ( + Group, + GPIO_GET_DW_NUM (PadNumber), + 1 << GPIO_GET_PAD_POSITION (PadNumber) + ); +} + +/** + This procedure will clear PadCfgLockTx for selected pads within one grou= p. + This function should be used only inside SMI. + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLockTx register number for current= group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToUnlockTx Bitmask for pads which are going to be u= nlocked, + Bit position - PadNumber + Bit value - 0: DoNotUnLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToUnlockTx + ) +{ + if (!GpioIsGroupAndDwNumValid (Group, DwNum)) { + return EFI_INVALID_PARAMETER; + } + + return GpioWriteLockReg ( + GpioPadLockOutputRegister, + Group, + DwNum, + ~PadsToUnlockTx, + 0 + ); +} + +/** + This procedure will clear PadCfgLockTx for selected pad. + This function should be used only inside SMI. + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioUnlockPadCfgTx ( + IN GPIO_PAD GpioPad + ) +{ + GPIO_GROUP Group; + UINT32 PadNumber; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + return GpioUnlockPadCfgTxForGroupDw ( + Group, + GPIO_GET_DW_NUM (PadNumber), + 1 << GPIO_GET_PAD_POSITION (PadNumber) + ); +} + +/** + This procedure will set PadCfgLockTx for selected pads within one group + + @param[in] Group GPIO group + @param[in] DwNum PadCfgLock register number for current g= roup. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] PadsToLockTx Bitmask for pads which are going to be l= ocked, + Bit position - PadNumber + Bit value - 0: DoNotLockTx, 1: LockTx + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number +**/ +EFI_STATUS +GpioLockPadCfgTxForGroupDw ( + IN GPIO_GROUP Group, + IN UINT32 DwNum, + IN UINT32 PadsToLockTx + ) +{ + if (!GpioIsGroupAndDwNumValid (Group, DwNum)) { + return EFI_INVALID_PARAMETER; + } + + return GpioWriteLockReg ( + GpioPadLockOutputRegister, + Group, + DwNum, + ~0u, + PadsToLockTx + ); +} + +/** + This procedure will set PadCfgLockTx for selected pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPadCfgTx ( + IN GPIO_PAD GpioPad + ) +{ + GPIO_GROUP Group; + UINT32 PadNumber; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + return GpioLockPadCfgTxForGroupDw ( + Group, + GPIO_GET_DW_NUM (PadNumber), + 1 << GPIO_GET_PAD_POSITION (PadNumber) + ); +} + +/** + This procedure will get Group to GPE mapping. + It will assume that only first 32 pads can be mapped to GPE. + To handle cases where groups have more than 32 pads and higher part of g= roup + can be mapped please refer to GpioGetGroupDwToGpeDwX() + + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupToGpeDwX ( + IN GPIO_GROUP *GroupToGpeDw0, + IN GPIO_GROUP *GroupToGpeDw1, + IN GPIO_GROUP *GroupToGpeDw2 + ) +{ + UINT32 GroupDw[3]; + UINT32 Index; + EFI_STATUS Status; + + Status =3D GpioGetGroupDwToGpeDwX ( + GroupToGpeDw0, + &GroupDw[0], + GroupToGpeDw1, + &GroupDw[1], + GroupToGpeDw2, + &GroupDw[2] + ); + + for (Index =3D 0; Index < ARRAY_SIZE (GroupDw); Index++) { + if (GroupDw[Index] !=3D 0) { + Status =3D EFI_UNSUPPORTED; + ASSERT (FALSE); + } + } + return Status; +} + + +/** + This procedure will get Group to GPE mapping. If group has more than 32 = bits + it is possible to map only single DW of pins (e.g. 0-31, 32-63) because + ACPI GPE_DWx register is 32 bits large. + + @param[out] GroupToGpeDw0 GPIO group mapped to GPE_DW0 + @param[out] GroupDwForGpeDw0 DW of pins mapped to GPE_DW0 + @param[out] GroupToGpeDw1 GPIO group mapped to GPE_DW1 + @param[out] GroupDwForGpeDw1 DW of pins mapped to GPE_DW1 + @param[out] GroupToGpeDw2 GPIO group mapped to GPE_DW2 + @param[out] GroupDwForGpeDw2 DW of pins mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetGroupDwToGpeDwX ( + OUT GPIO_GROUP *GroupToGpeDw0, + OUT UINT32 *GroupDwForGpeDw0, + OUT GPIO_GROUP *GroupToGpeDw1, + OUT UINT32 *GroupDwForGpeDw1, + OUT GPIO_GROUP *GroupToGpeDw2, + OUT UINT32 *GroupDwForGpeDw2 + ) +{ + UINT32 PmcGpeDwXValue[3]; + GPIO_GROUP GroupToGpeDwX[3]; + UINT32 GroupDwForGpeDwX[3]; + UINT8 GpeDwXIndex; + UINT32 Index; + GPIO_GROUP_TO_GPE_MAPPING *GpioGpeMap; + UINT32 GpioGpeMapLength; + + ZeroMem (GroupToGpeDwX, sizeof (GroupToGpeDwX)); + ZeroMem (GroupDwForGpeDwX, sizeof (GroupDwForGpeDwX)); + + PmcGetGpioGpe (&PmcGpeDwXValue[0], &PmcGpeDwXValue[1], &PmcGpeDwXValue[2= ]); + + GpioGetGroupToGpeMapping (&GpioGpeMap, &GpioGpeMapLength); + + for (GpeDwXIndex =3D 0; GpeDwXIndex < 3; GpeDwXIndex++) { + for (Index =3D 0; Index < GpioGpeMapLength; Index++) { + + if (GpioGpeMap[Index].PmcGpeDwxVal =3D=3D PmcGpeDwXValue[GpeDwXIndex= ]) { + GroupToGpeDwX[GpeDwXIndex] =3D GpioGpeMap[Index].Group; + GroupDwForGpeDwX[GpeDwXIndex] =3D GpioGpeMap[Index].GroupDw; + break; + } + } + } + + if ((GroupToGpeDwX[0] =3D=3D 0) || + (GroupToGpeDwX[1] =3D=3D 0) || + (GroupToGpeDwX[2] =3D=3D 0)) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + *GroupToGpeDw0 =3D GroupToGpeDwX[0]; + *GroupDwForGpeDw0 =3D GroupDwForGpeDwX[0]; + *GroupToGpeDw1 =3D GroupToGpeDwX[1]; + *GroupDwForGpeDw1 =3D GroupDwForGpeDwX[1]; + *GroupToGpeDw2 =3D GroupToGpeDwX[2]; + *GroupDwForGpeDw2 =3D GroupDwForGpeDwX[2]; + + return EFI_SUCCESS; +} + + +/** + This procedure will set Group to GPE mapping. + It will assume that only first 32 pads can be mapped to GPE. + To handle cases where groups have more than 32 pads and higher part of g= roup + can be mapped please refer to GpioSetGroupDwToGpeDwX() + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN GPIO_GROUP GroupToGpeDw2 + ) +{ + return GpioSetGroupDwToGpeDwX ( + GroupToGpeDw0, + 0, + GroupToGpeDw1, + 0, + GroupToGpeDw2, + 0 + ); +} + +/** + This procedure will set Group to GPE mapping. If group has more than 32 = bits + it is possible to map only single DW of pins (e.g. 0-31, 32-63) because + ACPI GPE_DWx register is 32 bits large. + + @param[in] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0 + @param[in] GroupDwForGpeDw0 DW of pins to be mapped to GPE_DW0 + @param[in] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1 + @param[in] GroupDwForGpeDw1 DW of pins to be mapped to GPE_DW1 + @param[in] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2 + @param[in] GroupDwForGpeDw2 DW of pins to be mapped to GPE_DW2 + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetGroupDwToGpeDwX ( + IN GPIO_GROUP GroupToGpeDw0, + IN UINT32 GroupDwForGpeDw0, + IN GPIO_GROUP GroupToGpeDw1, + IN UINT32 GroupDwForGpeDw1, + IN GPIO_GROUP GroupToGpeDw2, + IN UINT32 GroupDwForGpeDw2 + ) +{ + UINT32 Data32Or; + UINT32 Data32And; + PCH_SBI_PID *GpioComSbiIds; + UINT32 NoOfGpioComs; + UINT32 GpioComIndex; + UINT32 GpioGpeDwx[3]; + UINT32 PmcGpeDwx[3]; + GPIO_GROUP GroupToGpeDwX[3]; + UINT32 GroupDwForGpeDwX[3]; + UINT8 GpeDwXIndex; + UINT32 Index; + GPIO_GROUP_TO_GPE_MAPPING *GpioGpeMap; + UINT32 GpioGpeMapLength; + + ZeroMem (GpioGpeDwx, sizeof (GpioGpeDwx)); + ZeroMem (PmcGpeDwx, sizeof (PmcGpeDwx)); + // + // Check if each group number is unique + // + if ((GroupToGpeDw0 =3D=3D GroupToGpeDw1) || + (GroupToGpeDw0 =3D=3D GroupToGpeDw2) || + (GroupToGpeDw1 =3D=3D GroupToGpeDw2)) { + return EFI_INVALID_PARAMETER; + } + + GroupToGpeDwX[0] =3D GroupToGpeDw0; + GroupDwForGpeDwX[0] =3D GroupDwForGpeDw0; + GroupToGpeDwX[1] =3D GroupToGpeDw1; + GroupDwForGpeDwX[1] =3D GroupDwForGpeDw1; + GroupToGpeDwX[2] =3D GroupToGpeDw2; + GroupDwForGpeDwX[2] =3D GroupDwForGpeDw2; + + GpioGetGroupToGpeMapping (&GpioGpeMap, &GpioGpeMapLength); + + for (GpeDwXIndex =3D 0; GpeDwXIndex < 3; GpeDwXIndex++) { + for (Index =3D 0; Index < GpioGpeMapLength; Index++) { + + if ((GpioGpeMap[Index].Group =3D=3D GroupToGpeDwX[GpeDwXIndex]) && + (GpioGpeMap[Index].GroupDw =3D=3D GroupDwForGpeDwX[GpeDwXIndex])= ) { + PmcGpeDwx[GpeDwXIndex] =3D GpioGpeMap[Index].PmcGpeDwxVal; + GpioGpeDwx[GpeDwXIndex] =3D GpioGpeMap[Index].GpioGpeDwxVal; + break; + } + } + + if (Index =3D=3D GpioGpeMapLength) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + } + + // + // Program GPE configuration in PMC register + // + PmcSetGpioGpe ( + PmcGpeDwx[0], + PmcGpeDwx[1], + PmcGpeDwx[2] + ); + + // + // Program GPE configuration in GPIO registers + // + Data32And =3D (UINT32) ~(B_GPIO_PCR_MISCCFG_GPE0_DW2 | B_GPIO_PCR_MISCCF= G_GPE0_DW1 | B_GPIO_PCR_MISCCFG_GPE0_DW0); + Data32Or =3D (UINT32) ((GpioGpeDwx[2] << N_GPIO_PCR_MISCCFG_GPE0_DW2) | + (GpioGpeDwx[1] << N_GPIO_PCR_MISCCFG_GPE0_DW1) | + (GpioGpeDwx[0] << N_GPIO_PCR_MISCCFG_GPE0_DW0)); + + NoOfGpioComs =3D GpioGetComSbiPortIds (&GpioComSbiIds); + + // + // Program MISCCFG register for each community + // + for (GpioComIndex =3D 0; GpioComIndex < NoOfGpioComs; GpioComIndex++) { + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioComSbiIds[GpioComIndex], R_GPIO_PCR_MISCCFG), + Data32And, + Data32Or + ); + } + + return EFI_SUCCESS; +} + +/** + This procedure will get GPE number for provided GpioPad. + PCH allows to configure mapping between GPIO groups and related GPE (Gpi= oSetGroupToGpeDwX()) + what results in the fact that certain Pad can cause different General Pu= rpose Event. Only three + GPIO groups can be mapped to cause unique GPE (1-tier), all others group= s will be under one common + event (GPE_111 for 2-tier). + + 1-tier: + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used + to determine what _LXX ACPI method would be called on event on selected = GPIO pad + + 2-tier: + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to = 1-tier GPE + will be under one master GPE_111 which is linked to _L6F ACPI method. If= it is needed to determine + what Pad from 2-tier has caused the event, _L6F method should check GPI_= GPE_STS and GPI_GPE_EN + registers for all GPIO groups not mapped to 1-tier GPE. + + @param[in] GpioPad GPIO pad + @param[out] GpeNumber GPE number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpeNumber ( + IN GPIO_PAD GpioPad, + OUT UINT32 *GpeNumber + ) +{ + GPIO_GROUP GroupToGpeDwX[3]; + UINT32 GroupDw[3]; + GPIO_GROUP Group; + UINT32 PadNumber; + UINT32 Index; + EFI_STATUS Status; + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + // + // Get GPIO groups mapping to 1-tier GPE + // This mapping is dependent on GPIO IP implementation + // and may change between chipset generations + // + Status =3D GpioGetGroupDwToGpeDwX ( + &GroupToGpeDwX[0], &GroupDw[0], + &GroupToGpeDwX[1], &GroupDw[1], + &GroupToGpeDwX[2], &GroupDw[2] + ); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Check if pad is routed to 1-Tier GPE + // + for (Index =3D 0; Index < 3; Index++) { + if ((Group =3D=3D GroupToGpeDwX[Index]) && (PadNumber >=3D (32 * Group= Dw[Index])) && (PadNumber < (32 * (GroupDw[Index] + 1)))) { + *GpeNumber =3D PadNumber + (32 * Index) - (32 * GroupDw[Index]); + return EFI_SUCCESS; + } + } + + // + // If Group number doesn't match any of above then + // it means that the pad is routed to 2-tier GPE + // which corresponds to GPE_111 (0x6F) + // + *GpeNumber =3D PCH_GPIO_2_TIER_MASTER_GPE_NUMBER; + + return EFI_SUCCESS; +} + +/** + This procedure is used to clear SMI STS for a specified Pad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioClearGpiSmiSts ( + IN GPIO_PAD GpioPad + ) +{ + GPIO_GROUP Group; + UINT32 PadNumber; + UINT32 DwNum; + UINT32 PadBitPosition; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_UNSUPPORTED; + } + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + DwNum =3D GPIO_GET_DW_NUM (PadNumber); + PadBitPosition =3D GPIO_GET_PAD_POSITION (PadNumber); + + // + // Clear GPI SMI Status bit by writing '1' + // + GpioWriteReg ( + GpioSmiStatusRegister, + Group, + DwNum, + 0u, + (UINT32) (BIT0 << PadBitPosition) + ); + + return EFI_SUCCESS; +} + +/** + This procedure is used by PchSmiDispatcher and will clear + all GPI SMI Status bits + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioClearAllGpiSmiSts ( + VOID + ) +{ + UINT32 DwNum; + GPIO_GROUP Group; + GPIO_GROUP GroupMin; + GPIO_GROUP GroupMax; + + GroupMin =3D GpioGetLowestGroup (); + GroupMax =3D GpioGetHighestGroup (); + + for (Group =3D GroupMin; Group <=3D GroupMax; Group++) { + // + // Clear all GPI SMI STS + // + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGetPadPerGroup (Grou= p)); DwNum++) { + if (GpioIsSmiSupportedByGroupDw(Group, DwNum)) { + GpioWriteReg ( + GpioSmiStatusRegister, + Group, + DwNum, + 0u, + 0xFFFFFFFF + ); + } + } + } + return EFI_SUCCESS; + +} + +/** + This procedure is used to disable all GPI SMI + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioDisableAllGpiSmi ( + VOID + ) +{ + UINT32 DwNum; + GPIO_GROUP Group; + GPIO_GROUP GroupMin; + GPIO_GROUP GroupMax; + UINT32 SmiEnRegVal; + + GroupMin =3D GpioGetLowestGroup (); + GroupMax =3D GpioGetHighestGroup (); + + for (Group =3D GroupMin; Group <=3D GroupMax; Group++) { + // + // Disable all GPI SMI + // + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGetPadPerGroup (Grou= p)); DwNum++) { + if (GpioIsSmiSupportedByGroupDw (Group, DwNum)) { + SmiEnRegVal =3D 0; + // + // Check which pins have SMI_EN set + // + GpioReadReg ( + GpioSmiEnableRegister, + Group, + DwNum, + &SmiEnRegVal + ); + // + // Set HOSTSW_OWN to GPIO mode (1) for those pins to disable SMI= capability + // + GpioWriteReg ( + GpioHostOwnershipRegister, + Group, + DwNum, + ~0u, + SmiEnRegVal + ); + } + } + } + return EFI_SUCCESS; +} + +/** + This procedure is used to register GPI SMI dispatch function. + + @param[in] GpioPad GPIO pad + @param[out] GpiNum GPI number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiSmiNum ( + IN GPIO_PAD GpioPad, + OUT UINTN *GpiNum + ) +{ + UINT32 GroupIndex; + UINT32 Index; + UINT32 PadNumber; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + if (!GpioIsPadValid (GpioPad)) { + return EFI_UNSUPPORTED; + } + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + *GpiNum =3D 0; + + for (Index =3D 0; Index < GroupIndex; Index++) { + *GpiNum +=3D (UINTN) (GpioGroupInfo[Index].PadPerGroup); + } + *GpiNum +=3D (UINTN) PadNumber; + + return EFI_SUCCESS; +} + +/** + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier = architecture + + @param[in] GpioPad GPIO pad + + @retval Data 0 means 1-tier, 1 means 2-tier +**/ +BOOLEAN +GpioCheckFor2Tier ( + IN GPIO_PAD GpioPad + ) +{ + UINT32 Data32; + EFI_STATUS Status; + + Status =3D GpioGetGpeNumber (GpioPad, &Data32); + if (EFI_ERROR (Status)) { + DEBUG (( DEBUG_ERROR, "GpioCheckFor2Tier: Failed to get GPE number. St= atus: %r\n", Status )); + return FALSE; + } + + if (Data32 =3D=3D PCH_GPIO_2_TIER_MASTER_GPE_NUMBER) { + return TRUE; + } + + return FALSE; +} + +/** + This procedure is used to clear GPE STS for a specified GpioPad + + @param[in] GpioPad GPIO pad + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioClearGpiGpeSts ( + IN GPIO_PAD GpioPad + ) +{ + GPIO_GROUP Group; + UINT32 PadNumber; + UINT32 DwNum; + UINT32 PadBitPosition; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_UNSUPPORTED; + } + + // + // Check for 2-tier + // + if (!(GpioCheckFor2Tier (GpioPad))) { + return EFI_INVALID_PARAMETER; + } + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + DwNum =3D GPIO_GET_DW_NUM (PadNumber); + PadBitPosition =3D GPIO_GET_PAD_POSITION (PadNumber); + + // + // Clear GPI GPE Status bit by writing '1' + // + GpioWriteReg ( + GpioGpeStatusRegister, + Group, + DwNum, + 0u, + (UINT32) (BIT0 << PadBitPosition) + ); + + return EFI_SUCCESS; +} + +/** + This procedure is used to read GPE STS for a specified Pad + + @param[in] GpioPad GPIO pad + @param[out] Data GPE STS data + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetGpiGpeSts ( + IN GPIO_PAD GpioPad, + OUT UINT32 *Data + ) +{ + UINT32 GpeStsRegVal; + GPIO_GROUP Group; + UINT32 PadNumber; + UINT32 DwNum; + UINT32 PadBitPosition; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_UNSUPPORTED; + } + + // + // Check for 2-tier + // + if (!(GpioCheckFor2Tier (GpioPad))) { + return EFI_INVALID_PARAMETER; + } + + Group =3D GpioGetGroupFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + DwNum =3D GPIO_GET_DW_NUM (PadNumber); + PadBitPosition =3D GPIO_GET_PAD_POSITION (PadNumber); + + // + // Read GPI GPE Status bits + // + GpioReadReg ( + GpioGpeStatusRegister, + Group, + DwNum, + &GpeStsRegVal + ); + + *Data =3D (GpeStsRegVal >> PadBitPosition) & 0x1; + + return EFI_SUCCESS; +} + +/** + This procedure is used to lock all GPIO pads except the ones + which were requested during their configuration to be left unlocked. + This function must be called before BIOS_DONE - before POSTBOOT_SAI is e= nabled. + FSP - call this function from wrapper before transition to FSP-S + UEFI/EDK - call this function before EndOfPei event + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioLockPads ( + VOID + ) +{ + UINT32 DwNum; + GPIO_GROUP Group; + GPIO_GROUP GroupMin; + GPIO_GROUP GroupMax; + UINT32 UnlockedPads; + EFI_STATUS Status; + + GroupMin =3D GpioGetLowestGroup (); + GroupMax =3D GpioGetHighestGroup (); + + for (Group =3D GroupMin; Group <=3D GroupMax; Group++) { + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGetPadPerGroup (Grou= p)); DwNum++) { + + UnlockedPads =3D GpioGetGroupDwUnlockPadConfigMask (GpioGetGroupInde= xFromGroup (Group), DwNum); + + Status =3D GpioLockPadCfgForGroupDw (Group, DwNum, (UINT32)~Unlocked= Pads); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + + UnlockedPads =3D GpioGetGroupDwUnlockOutputMask (GpioGetGroupIndexFr= omGroup (Group), DwNum); + + Status =3D GpioLockPadCfgTxForGroupDw (Group, DwNum, (UINT32)~Unlock= edPads); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + } + } + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLi= b/GpioNames.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpi= oLib/GpioNames.c new file mode 100644 index 0000000000..ec33d06156 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioN= ames.c @@ -0,0 +1,87 @@ +/** @file + This file contains GPIO name library implementation + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "GpioLibrary.h" +#include + +/** + Generates GPIO group name from GpioPad + + @param[in] GpioPad GpioPad + + @retval CHAR8* Pointer to the GPIO group name +**/ +CONST +CHAR8* +GpioGetGroupName ( + IN UINT32 GroupIndex + ) +{ + CONST GPIO_GROUP_NAME_INFO* GroupNameInfo; + + GroupNameInfo =3D GpioGetGroupNameInfo (GroupIndex); + if (GroupNameInfo =3D=3D NULL) { + return NULL; + } else { + return GroupNameInfo->GpioGroupPrefix; + } +} + +/** + Generates GPIO name from GpioPad + + @param[in] GpioPad GpioPad + @param[out] GpioNameBuffer Caller allocated buffer of GPIO_NAME_LEN= GTH_MAX size + @param[in] GpioNameBufferSize Size of the buffer + + @retval CHAR8* Pointer to the GPIO name +**/ +CHAR8* +GpioGetPadName ( + IN GPIO_PAD GpioPad, + OUT CHAR8* GpioNameBuffer, + IN UINT32 GpioNameBufferSize + ) +{ + UINT32 GroupIndex; + UINT32 PadNumber; + UINT32 FirstUniquePadNumber; + CONST GPIO_GROUP_NAME_INFO* GroupNameInfo; + + if (GpioNameBuffer =3D=3D NULL) { + ASSERT (FALSE); + return NULL; + } + if ((GpioNameBufferSize < GPIO_NAME_LENGTH_MAX) || !GpioIsPadValid (Gpio= Pad)) { + ASSERT (FALSE); + *GpioNameBuffer =3D 0; + return NULL; + } + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + GroupNameInfo =3D GpioGetGroupNameInfo (GroupIndex); + if (GroupNameInfo =3D=3D NULL) { + return NULL; + } + + FirstUniquePadNumber =3D GpioGetPadNumberFromGpioPad (GroupNameInfo->Fir= stUniqueGpio); + if ((PadNumber < FirstUniquePadNumber) || (GroupNameInfo->GroupUniqueNam= es =3D=3D NULL)) { + AsciiSPrint (GpioNameBuffer, GPIO_NAME_LENGTH_MAX, "GPIO_%a%d", GpioGe= tGroupName (GroupIndex), PadNumber); + } else { + if (PadNumber - FirstUniquePadNumber < GroupNameInfo->UniqueNamesTable= Size) { + AsciiSPrint (GpioNameBuffer, GPIO_NAME_LENGTH_MAX, "GPIO_%a", GroupN= ameInfo->GroupUniqueNames[PadNumber - FirstUniquePadNumber]); + } else { + AsciiSPrint (GpioNameBuffer, GPIO_NAME_LENGTH_MAX, "GPIO_%08X", Gpio= Pad); + ASSERT (FALSE); + } + } + + return GpioNameBuffer; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLi= b/GpioNativeLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSm= mGpioLib/GpioNativeLib.c new file mode 100644 index 0000000000..9b71cb1d95 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmGpioLib/GpioN= ativeLib.c @@ -0,0 +1,234 @@ +/** @file + This file contains routines for GPIO native and chipset specific usage + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "GpioLibrary.h" + +/** + This procedure will get number of pads for certain GPIO group + + @param[in] Group GPIO group number + + @retval Value Pad number for group + If illegal group number then return 0 +**/ +UINT32 +GpioGetPadPerGroup ( + IN GPIO_GROUP Group + ) +{ + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 GroupIndex; + // + // Check if group argument exceeds GPIO GROUP INFO array + // + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + + if ((UINTN) GroupIndex >=3D GpioGroupInfoLength) { + return 0; + } else { + return GpioGroupInfo[GroupIndex].PadPerGroup; + } +} + +/** + This procedure will get number of groups + + @param[in] none + + @retval Value Group number +**/ +UINT32 +GpioGetNumberOfGroups ( + VOID + ) +{ + UINT32 GpioGroupInfoLength; + + GpioGetGroupInfoTable (&GpioGroupInfoLength); + return GpioGroupInfoLength; +} +/** + This procedure will get lowest group + + @param[in] none + + @retval Value Lowest Group +**/ +GPIO_GROUP +GpioGetLowestGroup ( + VOID + ) +{ + return GpioGetGroupFromGroupIndex (0); +} +/** + This procedure will get highest group + + @param[in] none + + @retval Value Highest Group +**/ +GPIO_GROUP +GpioGetHighestGroup ( + VOID + ) +{ + return GpioGetGroupFromGroupIndex (GpioGetNumberOfGroups () - 1); +} + +/** + This procedure will get group number + + @param[in] GpioPad Gpio Pad + + @retval Value Group number +**/ +GPIO_GROUP +GpioGetGroupFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return GPIO_GET_GROUP_FROM_PAD (GpioPad); +} + +/** + This procedure will get group index (0 based) + + @param[in] GpioPad Gpio Pad + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return (UINT32) GPIO_GET_GROUP_INDEX_FROM_PAD (GpioPad); +} + +/** + This procedure will get group index (0 based) from group + + @param[in] GpioGroup Gpio Group + + @retval Value Group Index +**/ +UINT32 +GpioGetGroupIndexFromGroup ( + IN GPIO_GROUP GpioGroup + ) +{ + return (UINT32) GPIO_GET_GROUP_INDEX (GpioGroup); +} + +/** + This procedure will get group from group index (0 based) + + @param[in] GroupIndex Group Index + + @retval GpioGroup Gpio Group +**/ +GPIO_GROUP +GpioGetGroupFromGroupIndex ( + IN UINT32 GroupIndex + ) +{ + return GPIO_GROUP_DEF (GroupIndex, GpioGetThisChipsetId ()); +} + +/** + This procedure will get pad number (0 based) from Gpio Pad + + @param[in] GpioPad Gpio Pad + + @retval Value Pad Number +**/ +UINT32 +GpioGetPadNumberFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + return (UINT32) GPIO_GET_PAD_NUMBER (GpioPad); +} +/** + This procedure will return GpioPad from Group and PadNumber + + @param[in] Group GPIO group + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupAndPadNumber ( + IN GPIO_GROUP Group, + IN UINT32 PadNumber + ) +{ + if (IsPchLp ()) { + return GPIO_PAD_DEF (Group,PadNumber); + } else { + return GPIO_PAD_DEF (Group,PadNumber); + } +} + +/** + This procedure will return GpioPad from GroupIndex and PadNumber + + @param[in] GroupIndex GPIO GroupIndex + @param[in] PadNumber GPIO PadNumber + + @retval GpioPad GpioPad +**/ +GPIO_PAD +GpioGetGpioPadFromGroupIndexAndPadNumber ( + IN UINT32 GroupIndex, + IN UINT32 PadNumber + ) +{ + GPIO_GROUP Group; + + Group =3D GPIO_GROUP_DEF (GroupIndex, GpioGetThisChipsetId ()); + return GPIO_PAD_DEF (Group, PadNumber); +} + +/** + This function checks if SATA GP pin is enabled + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + + @retval TRUE SATA GPx is enabled (pad is in required = native mode) + FALSE SATA GPx is not enabled +**/ +BOOLEAN +GpioIsSataGpEnabled ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort + ) +{ + EFI_STATUS Status; + GPIO_PAD_NATIVE_FUNCTION SataGpGpio; + GPIO_PAD_MODE GpioMode; + + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + GpioGetSataGpPin ( + SataCtrlIndex, + SataPort, + &SataGpGpio + ); + + Status =3D GpioGetPadMode (SataGpGpio.Pad, &GpioMode); + if ((EFI_ERROR (Status)) || (GpioMode !=3D SataGpGpio.Mode)) { + return FALSE; + } else { + return TRUE; + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchCyc= leDecodingLib/PchCycleDecodingLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pc= h/Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c new file mode 100644 index 0000000000..24afbbf712 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecod= ingLib/PchCycleDecodingLib.c @@ -0,0 +1,1136 @@ +/** @file + PCH cycle deocding configuration and query library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + SlaveLpcEspiCS0, + SlaveEspiCS1, + SlaveId_Max +} SLAVE_ID_INDEX; + +/** + Set PCH TCO base address. + This cycle decoding is required also on DMI side + Programming steps: + 1. set Smbus PCI offset 54h [8] to enable TCO base address. + 2. program Smbus PCI offset 50h [15:5] to TCO base address. + 3. set Smbus PCI offset 54h [8] to enable TCO base address. + 4. program "TCO Base Address" in DMI + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchTcoBaseSet ( + IN UINT16 Address + ) +{ + UINT64 SmbusBase; + EFI_STATUS Status; + + if ((Address & ~B_SMBUS_CFG_TCOBASE_BAR) !=3D 0) { + DEBUG ((DEBUG_ERROR, "PchTcoBaseSet Error. Invalid Address: %x.\n", Ad= dress)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Status =3D PchDmiSetTcoBase (Address); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + SmbusBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SMBUS, + PCI_FUNCTION_NUMBER_PCH_SMBUS, + 0 + ); + if (PciSegmentRead16 (SmbusBase) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Verify TCO base is not locked. + // + if ((PciSegmentRead8 (SmbusBase + R_SMBUS_CFG_TCOCTL) & B_SMBUS_CFG_TCOC= TL_TCO_BASE_LOCK) !=3D 0) { + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + // + // Disable TCO in SMBUS Device first before changing base address. + // Byte access to not touch the TCO_BASE_LOCK bit + // + PciSegmentAnd8 ( + SmbusBase + R_SMBUS_CFG_TCOCTL + 1, + (UINT8) ~(B_SMBUS_CFG_TCOCTL_TCO_BASE_EN >> 8) + ); + // + // Program TCO in SMBUS Device + // + PciSegmentAndThenOr16 ( + SmbusBase + R_SMBUS_CFG_TCOBASE, + (UINT16) (~B_SMBUS_CFG_TCOBASE_BAR), + Address + ); + // + // Enable TCO in SMBUS Device and lock TCO BASE + // + PciSegmentOr16 ( + SmbusBase + R_SMBUS_CFG_TCOCTL, + B_SMBUS_CFG_TCOCTL_TCO_BASE_EN | B_SMBUS_CFG_TCOCTL_TCO_BASE_LOCK + ); + + return Status; +} + +/** + Get PCH TCO base address. + + @param[out] Address Address of TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid pointer passed. +**/ +EFI_STATUS +PchTcoBaseGet ( + OUT UINT16 *Address + ) +{ + if (Address =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "PchTcoBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + // + // Read "TCO Base Address" from DMI + // Don't read TCO base address from SMBUS PCI register since SMBUS might= be disabled. + // + *Address =3D PchDmiGetTcoBase (); + + return EFI_SUCCESS; +} + +/** + Returns PCH LPC device PCI base address. + + @retval PCH LPC PCI base address. +**/ +STATIC +UINT64 +LpcPciBase ( + VOID + ) +{ + return PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); +} + +/** + Function checks if passed Generic LPC IO Address and Length meets requir= ements. + + @param[in] Address Address for generic IO range decod= ing. + @param[in] Length Length of generic IO range. + + @retval TRUE Passed IO range meets requirements + @retval FALSE Passed IO range does not meets req= uirements. +**/ +STATIC +BOOLEAN +IsLpcIoRangeValid ( + IN UINT32 Address, + IN UINT32 Length + ) +{ + UINT32 Index; + UINT32 NumRanges; + + STATIC struct EXCEPT_RANGE { + UINT8 Start; + UINT8 Length; + } ExceptRanges[] =3D { {0x00, 0x20}, {0x44, 0x08}, {0x54, 0x0C}, {0x68, = 0x08}, {0x80, 0x10}, {0xC0, 0x40} }; + + NumRanges =3D ARRAY_SIZE (ExceptRanges); + // + // For generic IO range, the base address must align to 4 and less than = 0xFFFF, + // the length must be power of 2 and less than or equal to 256, and the = address must be length aligned. + // IO range below 0x100 will be rejected in this function except below r= anges: + // 0x00-0x1F, + // 0x44-0x4B, + // 0x54-0x5F, + // 0x68-0x6F, + // 0x80-0x8F, + // 0xC0-0xFF + // + if (((Length & (Length - 1)) !=3D 0) || + ((Address & (UINT16) ~B_LPC_CFG_GENX_DEC_IOBAR) !=3D 0) || + (Length > 256)) { + return FALSE; + } + if (Address < 0x100) { + for (Index =3D 0; Index < NumRanges; Index++) { + if ((Address >=3D ExceptRanges[Index].Start) && + ((Address + Length) <=3D ((UINTN) ExceptRanges[Index].Start + (U= INTN) ExceptRanges[Index].Length))) { + break; + } + } + if (Index >=3D NumRanges) { + return FALSE; + } + } + + return TRUE; +} + +/** + Function checks if passed Generic LPC IO Range is already in Gen IO Rang= e list + + @param[in] Address Address for generic IO range decod= ing. + @param[in] Length Length of generic IO range. + @param[in] GenIoRangeList Pointer to Generic IO Ranges List + + @retval TRUE Passed IO range alredy covered + @retval FALSE Passed IO range NOT covered +**/ +STATIC +BOOLEAN +IsRangeInList ( + IN UINT32 Address, + IN UINT32 Length, + IN PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList + ) +{ + UINT32 CurrentBaseAddr; + UINT32 CurrentLength; + UINT32 Index; + + for (Index =3D 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + CurrentBaseAddr =3D GenIoRangeList->Range[Index].BaseAddr; + CurrentLength =3D GenIoRangeList->Range[Index].Length; + if (GenIoRangeList->Range[Index].Enable =3D=3D 0) { + continue; + } + if ((Address >=3D CurrentBaseAddr) && ((Address + Length) <=3D (Curren= tBaseAddr + CurrentLength))) { + return TRUE; + } + } + + return FALSE; +} + +/** + Function checks if passed Generic LPC IO Range overlaps with existing ra= nge + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + @param[in] GenIoRangeList Pointer to Generic IO Ranges List + + @retval TRUE Passed LPC IO range overlaps with = existing range + @retval FALSE Passed LPC IO range NOT overlaps +**/ +STATIC +BOOLEAN +FindOverlappingGenIoRange ( + IN UINT32 Address, + IN UINT32 Length, + IN PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList + ) +{ + UINT32 Index; + UINT32 CurrentBaseAddr; + UINT32 CurrentLength; + + for (Index =3D 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + CurrentBaseAddr =3D GenIoRangeList->Range[Index].BaseAddr; + CurrentLength =3D GenIoRangeList->Range[Index].Length; + if (GenIoRangeList->Range[Index].Enable =3D=3D 0) { + continue; + } + + if ((Address >=3D CurrentBaseAddr) && + (Address <=3D (CurrentBaseAddr + CurrentLength))) { + return TRUE; + } else if (((Address + Length) >=3D CurrentBaseAddr) && + ((Address + Length) <=3D (CurrentBaseAddr + CurrentLength)))= { + return TRUE; + } + } + + return FALSE; +} + +/** + Function look for empty Generic IO range register. + If found return range index. + + @param[in] GenIoRangeList Pointer to Generic IO Ranges List + @param[in] ListLength Length of passed list + @param[out] RangeIndex Generic IO Range Index + + @retval TRUE Empty range found + @retval FALSE NOT found empty range +**/ +STATIC +BOOLEAN +FindEmptyGenIoRange ( + IN PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList, + IN UINT32 ListLength, + OUT UINT32 *RangeIndex + ) +{ + UINT32 Index; + + for (Index =3D 0; Index < ListLength; Index++) { + if (GenIoRangeList->Range[Index].Enable =3D=3D 0) { + *RangeIndex =3D Index; + return TRUE; + } + } + + return FALSE; +} + +/** + Get PCH LPC/eSPI and eSPI CS1# generic IO range list. + This function returns a list of base address, length, and enable for all= LPC/eSPI or eSPI CS1# generic IO range registers. + + @param[in] RangeIndex Slave ID (refer to SLAVE_ID_INDEX) + @param[out] GenIoRangeList LPC/eSPI or eSPI CS1# generic IO r= ange registers. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +LpcEspiGenIoRangeGetHelper ( + IN SLAVE_ID_INDEX SlaveId, + OUT PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList + ) +{ + UINT32 Index; + UINT64 LpcBase; + UINT32 Data32; + UINT32 GenIoReg; + + if ((GenIoRangeList =3D=3D NULL) || (SlaveId >=3D SlaveId_Max)) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase =3D LpcPciBase (); + + if (SlaveId =3D=3D SlaveEspiCS1) { + GenIoReg =3D R_ESPI_CFG_CS1GIR1; + } else { + GenIoReg =3D R_LPC_CFG_GEN1_DEC; + } + + for (Index =3D 0; Index < PCH_LPC_GEN_IO_RANGE_MAX; Index++) { + if ((SlaveId =3D=3D SlaveEspiCS1) && + (Index > 0)) { + // For eSPI CS1# we have only one range. Reset remaining entries to = zero. + GenIoRangeList->Range[Index].BaseAddr =3D 0; + GenIoRangeList->Range[Index].Enable =3D 0; + GenIoRangeList->Range[Index].Length =3D 0; + continue; + } + Data32 =3D PciSegmentRead32 (LpcBase + GenIoReg + Index * 4); + GenIoRangeList->Range[Index].BaseAddr =3D Data32 & B_LPC_CFG_GENX_DEC_= IOBAR; + GenIoRangeList->Range[Index].Length =3D ((Data32 & B_LPC_CFG_GENX_DE= C_IODRA) >> 16) + 4; + GenIoRangeList->Range[Index].Enable =3D Data32 & B_LPC_CFG_GENX_DEC_= EN; + } + + return EFI_SUCCESS; +} + + +/** + Function checks if passed Generic LPC IO Range colliding + with range alredy defined for other eSPI chiselect (CS) + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX) + + @retval TRUE Passed IO range conflicting + @retval FALSE There is no conflict +**/ +STATIC +BOOLEAN +IsRangeColliding ( + IN UINT32 Address, + IN UINT32 Length, + IN SLAVE_ID_INDEX SlaveId + ) +{ + EFI_STATUS Status; + PCH_LPC_GEN_IO_RANGE_LIST GenIoRangeList; + + if (SlaveId =3D=3D SlaveEspiCS1) { + Status =3D LpcEspiGenIoRangeGetHelper (SlaveLpcEspiCS0, &GenIoRangeLi= st); + if (!EFI_ERROR (Status)) { + if (FindOverlappingGenIoRange (Address, Length, &GenIoRangeList) || + IsRangeInList (Address, Length, &GenIoRangeList)) { + return TRUE; + } + } + } else { + Status =3D LpcEspiGenIoRangeGetHelper (SlaveEspiCS1, &GenIoRangeList); + if (!EFI_ERROR (Status)) { + if (FindOverlappingGenIoRange (Address, Length, &GenIoRangeList) || + IsRangeInList (Address, Length, &GenIoRangeList)) { + return TRUE; + } + } + } + + return FALSE; +} + +/** + Set PCH LPC/eSPI and eSPI CS1# generic IO range decoding. + + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h (LPC, eSPI CS0#) or A4h (eSPI C= S1#) of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range in DMI + + @param[in] Address Address for generic IO range decod= ing. + @param[in] Length Length of generic IO range. + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX) + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMI configuration is locked, + GenIO range conflicting with other= eSPI CS +**/ +STATIC +EFI_STATUS +LpcEspiGenIoRangeSetHelper ( + IN UINT32 Address, + IN UINT32 Length, + IN SLAVE_ID_INDEX SlaveId + ) +{ + EFI_STATUS Status; + PCH_LPC_GEN_IO_RANGE_LIST GenIoRangeList; + UINT32 RangeIndex; + UINT32 Data32; + UINT32 GenIoReg; + UINT32 ListLength; + + // + // Check if pasesed Address and Length meets all requirements + // + if(!IsLpcIoRangeValid (Address, Length) || (SlaveId >=3D SlaveId_Max)) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Read current Generic IO configuration + // + Status =3D LpcEspiGenIoRangeGetHelper (SlaveId, &GenIoRangeList); + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Check if passed Generic IO range is already covered in current config= uration + // + if (IsRangeInList (Address, Length, &GenIoRangeList)) { + return EFI_SUCCESS; + } + + // + // Check if passed Generic IO range conflicting with other eSPI CS decod= ing + // + if (IsRangeColliding (Address, Length, SlaveId)) { + return EFI_UNSUPPORTED; + } + + if (SlaveId =3D=3D SlaveEspiCS1) { + GenIoReg =3D R_ESPI_CFG_CS1GIR1; + ListLength =3D ESPI_CS1_GEN_IO_RANGE_MAX; + } else { + GenIoReg =3D R_LPC_CFG_GEN1_DEC; + ListLength =3D PCH_LPC_GEN_IO_RANGE_MAX; + } + + RangeIndex =3D ListLength; + // + // Check if there is an empty Generic IO range register + // + if (FindEmptyGenIoRange (&GenIoRangeList, ListLength, &RangeIndex) =3D= =3D FALSE) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Program decoding in DMI and LPC/eSPI registers + // + if (SlaveId =3D=3D SlaveEspiCS1) { + ASSERT (RangeIndex =3D=3D 0); + Status =3D PchDmiSetEspiCs1GenIoRange (Address, Length); + } else { + Status =3D PchDmiSetLpcGenIoRange (Address, Length, RangeIndex); + } + if (EFI_ERROR (Status)) { + return Status; + } + + // + // Program LPC/eSPI generic IO range register accordingly. + // + Data32 =3D (UINT32) (((Length - 1) << 16) & B_LPC_CFG_GENX_DEC_IODRA); + Data32 |=3D (UINT32) Address; + Data32 |=3D B_LPC_CFG_GENX_DEC_EN; + + // + // Program LPC/eSPI PCI Offset 84h ~ 93h (LPC, eSPI CS0#) or A4h (eSPI C= S1#) of Mask, Address, and Enable. + // + PciSegmentWrite32 ( + LpcPciBase () + GenIoReg + RangeIndex * 4, + Data32 + ); + + return Status; +} + +/** + Set PCH LPC/eSPI generic IO range. + For generic IO range, the base address must align to 4 and less than 0xF= FFF, and the length must be power of 2 + and less than or equal to 256. Moreover, the address must be length alig= ned. + This function basically checks the address and length, which should not = overlap with all other generic ranges. + If no more generic range register available, it returns out of resource = error. + This cycle decoding is also required on DMI side + Some IO ranges below 0x100 have fixed target. The target might be ITSS,R= TC,LPC,PMC or terminated inside P2SB + but all predefined and can't be changed. IO range below 0x100 will be re= jected in this function except below ranges: + 0x00-0x1F, + 0x44-0x4B, + 0x54-0x5F, + 0x68-0x6F, + 0x80-0x8F, + 0xC0-0xFF + Steps of programming generic IO range: + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable. + 2. Program LPC/eSPI Generic IO Range in DMI + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcGenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + ) +{ + return LpcEspiGenIoRangeSetHelper ((UINT32)Address, (UINT32)Length, Slav= eLpcEspiCS0); +} + +/** + Set PCH eSPI CS1# generic IO range decoding. + + Steps of programming generic IO range: + 1. Program eSPI PCI Offset A4h (eSPI CS1#) of Mask, Address, and Enable. + 2. Program eSPI Generic IO Range in DMI + + @param[in] Address Address for generic IO range decod= ing. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +PchEspiCs1GenIoRangeSet ( + IN UINT16 Address, + IN UINTN Length + ) +{ + if (!IsEspiSecondSlaveSupported ()) { + return EFI_UNSUPPORTED; + } + + return LpcEspiGenIoRangeSetHelper ((UINT32)Address, (UINT32)Length, Slav= eEspiCS1); +} + +/** + Get PCH LPC/eSPI generic IO range list. + This function returns a list of base address, length, and enable for all= LPC/eSPI generic IO range registers. + + @param[out] LpcGenIoRangeList Return all LPC/eSPI generic IO ran= ge register status. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +PchLpcGenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *LpcGenIoRangeList + ) +{ + return LpcEspiGenIoRangeGetHelper (SlaveLpcEspiCS0, LpcGenIoRangeList); +} + +/** + Get PCH eSPI CS1# generic IO range list. + This function returns a list of base address, length, and enable for all= eSPI CS1# generic IO range registers. + + @param[out] GenIoRangeList eSPI generic IO range registers. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +PchEspiCs1GenIoRangeGet ( + OUT PCH_LPC_GEN_IO_RANGE_LIST *GenIoRangeList + ) +{ + if (!IsEspiSecondSlaveSupported ()) { + return EFI_UNSUPPORTED; + } + + return LpcEspiGenIoRangeGetHelper (SlaveEspiCS1, GenIoRangeList); +} + +/** + Set PCH LPC/eSPI and eSPI CS1# memory range decoding. + This cycle decoding is required to be set on DMI side + Programming steps: + 1. Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [= 0] to [0] to disable memory decoding first before changing base address. + 2. Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [= 31:16, 0] to [Address, 1]. + 3. Program LPC/eSPI Memory Range in DMI + + @param[in] Address Address for memory for decoding. + @param[in] RangeIndex Slave ID (refer to SLAVE_ID_INDEX) + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. +**/ +EFI_STATUS +LpcEspiMemRangeSetHelper ( + IN UINT32 Address, + IN SLAVE_ID_INDEX SlaveId + ) +{ + UINT64 LpcBase; + EFI_STATUS Status; + UINT32 GenMemReg; + UINT32 MemRangeAddr; + + if (((Address & (~B_LPC_CFG_LGMR_MA)) !=3D 0) || (SlaveId >=3D SlaveId_M= ax)) { + DEBUG ((DEBUG_ERROR, "PchLpcEspiMemRangeSet Error. Invalid Address: %x= or invalid SlaveId\n", Address)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + LpcBase =3D LpcPciBase (); + + MemRangeAddr =3D ~Address; + if (SlaveId =3D=3D SlaveEspiCS1) { + GenMemReg =3D R_ESPI_CFG_CS1GMR1; + // Memory Range already decoded for LPC/eSPI? + Status =3D PchLpcMemRangeGet (&MemRangeAddr); + if (MemRangeAddr !=3D Address) { + Status =3D PchDmiSetEspiCs1MemRange (Address); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + } + } else { + GenMemReg =3D R_LPC_CFG_LGMR; + // Memory Range already decoded for eSPI CS1? + Status =3D PchEspiCs1MemRangeGet (&MemRangeAddr); + if (MemRangeAddr !=3D Address) { + Status =3D PchDmiSetLpcMemRange (Address); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + } + } + + // + // Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [= 0] to [0] to disable memory decoding first before changing base address. + // + PciSegmentAnd32 ( + LpcBase + GenMemReg, + (UINT32) ~B_LPC_CFG_LGMR_LMRD_EN + ); + // + // Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [= 31:16, 0] to [Address, 1]. + // + PciSegmentWrite32 ( + LpcBase + GenMemReg, + (Address | B_LPC_CFG_LGMR_LMRD_EN) + ); + + return Status; +} + +/** + Set PCH LPC/eSPI memory range decoding. + This cycle decoding is required to be set on DMI side + Programming steps: + 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding firs= t before changing base address. + 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1]. + 3. Program LPC Memory Range in DMI + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_OUT_OF_RESOURCES No more generic range available. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcMemRangeSet ( + IN UINT32 Address + ) +{ + return LpcEspiMemRangeSetHelper (Address, SlaveLpcEspiCS0); +} + +/** + Set PCH eSPI CS1# memory range decoding. + This cycle decoding is required to be set on DMI side + Programming steps: + 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory = decoding first before changing base address. + 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1]. + 3. Program eSPI Memory Range in DMI + + @param[in] Address Address for memory for decoding. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +PchEspiCs1MemRangeSet ( + IN UINT32 Address + ) +{ + if (!IsEspiSecondSlaveSupported ()) { + return EFI_UNSUPPORTED; + } + + return LpcEspiMemRangeSetHelper (Address, SlaveEspiCS1); +} + +/** + @deprecated. Keep this for backward compatibility. + It's replaced by PchEspiCs1MemRangeSet. +**/ +EFI_STATUS +PchEspiMemRange2Set ( + IN UINT32 Address + ) +{ + return PchEspiCs1MemRangeSet (Address); +} + +/** + Get PCH LPC/eSPI and eSPI CS1# memory range decoding address. + + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX) + @param[out] Address Address of LPC/eSPI or eSPI CS1# m= emory decoding base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +LpcEspiMemRangeGetHelper ( + IN SLAVE_ID_INDEX SlaveId, + OUT UINT32 *Address + ) +{ + UINT32 GenMemReg; + + if ((Address =3D=3D NULL) || (SlaveId >=3D SlaveId_Max)) { + DEBUG ((DEBUG_ERROR, "PchLpcEspiMemRangeGet Error. Invalid pointer or = SlaveId.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + if (SlaveId =3D=3D SlaveEspiCS1) { + GenMemReg =3D R_ESPI_CFG_CS1GMR1; + } else { + GenMemReg =3D R_LPC_CFG_LGMR; + } + *Address =3D PciSegmentRead32 (LpcPciBase () + GenMemReg) & B_LPC_CFG_LG= MR_MA; + return EFI_SUCCESS; +} + +/** + Get PCH LPC/eSPI memory range decoding address. + + @param[out] Address Address of LPC/eSPI memory decodin= g base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. +**/ +EFI_STATUS +PchLpcMemRangeGet ( + OUT UINT32 *Address + ) +{ + return LpcEspiMemRangeGetHelper (SlaveLpcEspiCS0, Address); +} + +/** + Get PCH eSPI CS1# memory range decoding address. + + @param[out] Address Address of eSPI CS1# memory decodi= ng base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED eSPI secondary slave not supported +**/ +EFI_STATUS +PchEspiCs1MemRangeGet ( + OUT UINT32 *Address + ) +{ + if (!IsEspiSecondSlaveSupported ()) { + return EFI_UNSUPPORTED; + } + + return LpcEspiMemRangeGetHelper (SlaveEspiCS1, Address); +} + +/** + Set PCH BIOS range deocding. + This will check General Control and Status bit 10 (GCS.BBS) to identify = SPI or LPC/eSPI and program BDE register accordingly. + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + This cycle decoding is also required in DMI + Programming steps: + 1. if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable. + if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEnabl= e. + 2. program LPC BIOS Decode Enable in DMI + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchBiosDecodeEnableSet ( + IN UINT16 BiosDecodeEnable + ) +{ + UINT64 BaseAddr; + EFI_STATUS Status; + + Status =3D PchDmiSetBiosDecodeEnable (BiosDecodeEnable); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // Check Boot BIOS Strap in DMI + // + if (PchDmiIsBootBiosStrapSetForSpi ()) { + BaseAddr =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + // + // Read SPI CFG cycle before write SPI CFG cycle + PciSegmentRead16 (BaseAddr + R_SPI_CFG_BDE); + // + // If SPI, Program SPI offset D8h to BiosDecodeEnable. + // + PciSegmentWrite16 (BaseAddr + R_SPI_CFG_BDE, BiosDecodeEnable); + } else { + BaseAddr =3D LpcPciBase (); + // + // If LPC/eSPi, program LPC offset D8h to BiosDecodeEnable. + // + PciSegmentWrite16 (BaseAddr + R_LPC_CFG_BDE, BiosDecodeEnable); + } + + return Status; +} + +/** + Set PCH LPC/eSPI IO decode ranges. + Program LPC/eSPI I/O Decode Ranges in DMI to the same value programmed i= n LPC/eSPI PCI offset 80h. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoDecodeRangesSet ( + IN UINT16 LpcIoDecodeRanges + ) +{ + UINT64 LpcBaseAddr; + EFI_STATUS Status; + + // + // Note: Inside this function, don't use debug print since it's could us= ed before debug print ready. + // + + LpcBaseAddr =3D LpcPciBase (); + + // + // check if setting is identical + // + if (LpcIoDecodeRanges =3D=3D PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_I= OD)) { + return EFI_SUCCESS; + } + + Status =3D PchDmiSetLpcIoDecodeRanges (LpcIoDecodeRanges); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // program LPC/eSPI PCI offset 80h. + // + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOD, LpcIoDecodeRanges); + + return Status; +} + +/** + Set PCH LPC/eSPI and eSPI CS1# IO enable decoding. + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offse= t 82h (LPC, eSPI CS0#) or A0h (eSPI CS1#). + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] or A0h[13:10] is always forwarded by D= MI to subtractive agent for handling. + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definition. + + @param[in] IoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings. + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX) + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMI configuration is locked +**/ +EFI_STATUS +LpcEspiIoEnableDecodingSetHelper ( + IN UINT16 IoEnableDecoding, + IN SLAVE_ID_INDEX SlaveId + ) +{ + UINT64 LpcBaseAddr; + EFI_STATUS Status; + UINT16 Cs1IoEnableDecodingOrg; + UINT16 Cs0IoEnableDecodingOrg; + UINT16 IoEnableDecodingMerged; + + LpcBaseAddr =3D LpcPciBase (); + + Cs0IoEnableDecodingOrg =3D PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_IOE= ); + + if (IsEspiSecondSlaveSupported ()) { + Cs1IoEnableDecodingOrg =3D PciSegmentRead16 (LpcBaseAddr + R_ESPI_CFG_= CS1IORE); + } else { + Cs1IoEnableDecodingOrg =3D 0; + } + + if (SlaveId =3D=3D SlaveEspiCS1) { + if (IoEnableDecoding =3D=3D Cs1IoEnableDecodingOrg) { + return EFI_SUCCESS; + } else { + IoEnableDecodingMerged =3D (Cs0IoEnableDecodingOrg | IoEnableDecodin= g); + } + } else { + if ((IoEnableDecoding | Cs1IoEnableDecodingOrg) =3D=3D Cs0IoEnableDeco= dingOrg) { + return EFI_SUCCESS; + } else { + IoEnableDecodingMerged =3D (Cs1IoEnableDecodingOrg | IoEnableDecodin= g); + } + } + + Status =3D PchDmiSetLpcIoEnable (IoEnableDecodingMerged); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + // + // program PCI offset 82h for LPC/eSPI. + // + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOE, IoEnableDecodingMerged); + + if (SlaveId =3D=3D SlaveEspiCS1) { + // + // For eSPI CS1# device program eSPI PCI offset A0h. + // + PciSegmentWrite16 (LpcBaseAddr + R_ESPI_CFG_CS1IORE, IoEnableDecoding); + } + + return Status; +} + + +/** + Set PCH LPC and eSPI CS0# IO enable decoding. + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offse= t 82h. + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtract= ive agent for handling. + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit setting= s. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchLpcIoEnableDecodingSet ( + IN UINT16 LpcIoEnableDecoding + ) +{ + return LpcEspiIoEnableDecodingSetHelper (LpcIoEnableDecoding, SlaveLpcEs= piCS0); +} + +/** + Set PCH eSPI CS1# IO enable decoding. + Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0= h (eSPI CS1#). + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field + in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive = agent for handling. + Please check EDS for detail of eSPI IO decode ranges bit definition. + + @param[in] IoEnableDecoding eSPI IO enable decoding bit settin= gs. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMI configuration is locked +**/ +EFI_STATUS +PchEspiCs1IoEnableDecodingSet ( + IN UINT16 IoEnableDecoding + ) +{ + if (!IsEspiSecondSlaveSupported ()) { + return EFI_UNSUPPORTED; + } + + return LpcEspiIoEnableDecodingSetHelper (IoEnableDecoding, SlaveEspiCS1); +} + +/** + Set PCH IO port 80h cycle decoding to PCIE root port. + System BIOS is likely to do this very soon after reset before PCI bus en= umeration. + This cycle decoding is allowed to set when DMI is unlocked + + @param[in] RpNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoPort80DecodeSet ( + IN UINTN RpNumber + ) +{ + EFI_STATUS Status; + + Status =3D PchDmiSetIoPort80Decode (RpNumber); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Get IO APIC registers base address. + + @param[out] IoApicBase Buffer of IO APIC register address + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchIoApicBaseGet ( + OUT UINT32 *IoApicBase + ) +{ + *IoApicBase =3D PcdGet32 (PcdIoApicBaseAddress); + return EFI_SUCCESS; +} + +/** + Get HPET base address. + + @param[out] HpetBase Buffer of HPET base address + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid offset passed. +**/ +EFI_STATUS +PchHpetBaseGet ( + OUT UINT32 *HpetBase + ) +{ + if (HpetBase =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "PchHpetBaseGet Error. Invalid pointer.\n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + *HpetBase =3D PcdGet32 (PcdSiHpetBaseAddress); + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchEsp= iLib/PchEspiLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSm= mPchEspiLib/PchEspiLib.c new file mode 100644 index 0000000000..1bbecc71ed --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchEspiLib/Pc= hEspiLib.c @@ -0,0 +1,505 @@ +/** @file + This file contains routines for eSPI + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define CHANNEL_RESET_TIMEOUT 100 ///< Channel reset timeout in us a= fter which to report error +#define SLAVE_CHANNELS_MAX 7 ///< Max number of channels + +// +// eSPI Slave registers +// +#define R_ESPI_SLAVE_GENCAP 0x08 ///< General Capabilit= ies and Configurations +#define B_ESPI_SLAVE_GENCAP_SUPPCHAN 0xFF ///< Channels supporte= d bit mask +#define R_ESPI_SLAVE_CHACAP_BASE 0x10 ///< Base address from= which channel Cap and Conf registers start on slave +#define S_ESPI_SLAVE_CHACAP_OFFSET 0x10 ///< Offset for each c= hannel from base +#define B_ESPI_SLAVE_CHACAP_CHEN BIT0 ///< Slave Channel ena= ble bit +#define B_ESPI_SLAVE_CHACAP_CHRDY BIT1 ///< Slave Channel rea= dy bit + +/** + Checks if second slave capability is enabled + + @retval TRUE There's second slave + @retval FALSE There's no second slave +**/ +BOOLEAN +IsEspiSecondSlaveSupported ( + VOID + ) +{ + return (IsPchH () && ((PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SOFTSTRAPS)= & R_ESPI_PCR_SOFTSTRAPS_CS1_EN) !=3D 0)); +} + +/** + Checks in slave General Capabilities register if it supports channel wit= h requested number + + @param[in] SlaveId Id of slave to check + @param[in] ChannelNumber Number of channel of which to check + + @retval TRUE Channel with requested number is supported by slave de= vice + @retval FALSE Channel with requested number is not supported by slav= e device +**/ +BOOLEAN +IsEspiSlaveChannelSupported ( + UINT8 SlaveId, + UINT8 ChannelNumber + ) +{ + EFI_STATUS Status; + UINT32 Data32; + UINT8 SupportedChannels; + + Status =3D PchEspiSlaveGetConfig (SlaveId, R_ESPI_SLAVE_GENCAP, &Data32); + if (EFI_ERROR (Status)) { + return FALSE; + } + SupportedChannels =3D (UINT8) (Data32 & B_ESPI_SLAVE_GENCAP_SUPPCHAN); + + DEBUG ((DEBUG_INFO, "Slave %d supported channels 0x%4X\n", SlaveId, Supp= ortedChannels)); + + if (ChannelNumber > SLAVE_CHANNELS_MAX || !(SupportedChannels & (BIT0 <<= ChannelNumber))) { + // Incorrect channel number was specified. Either exceeded max or Slav= e doesn't support that channel. + return FALSE; + } + + return TRUE; +} + +/** + Is eSPI enabled in strap. + + @retval TRUE Espi is enabled in strap + @retval FALSE Espi is disabled in strap +**/ +BOOLEAN +IsEspiEnabled ( + VOID + ) +{ + return (PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_CFG_VAL) & B_ESPI_PCR_CFG_= VAL_ESPI_EN) !=3D 0; +} + +/** + eSPI helper function to clear slave configuration register status + + @retval EFI_SUCCESS Write to private config space succeed + @retval others Read / Write failed +**/ +STATIC +VOID +EspiClearScrs ( + VOID + ) +{ + PchPcrAndThenOr32 ( + PID_ESPISPI, + R_ESPI_PCR_SLV_CFG_REG_CTL, + (UINT32) ~0, + B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS + ); +} + +/** + eSPI helper function to poll slave configuration register enable for 0 + and to check for slave configuration register status + + @retval EFI_SUCCESS Enable bit is zero and no error in status bits + @retval EFI_DEVICE_ERROR Error in SCRS + @retval others Read / Write to private config space failed +**/ +STATIC +EFI_STATUS +EspiPollScreAndCheckScrs ( + VOID + ) +{ + UINT32 ScrStat; + + do { + ScrStat =3D PchPcrRead32 (PID_ESPISPI, R_ESPI_PCR_SLV_CFG_REG_CTL); + } while ((ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE) !=3D 0); + + ScrStat =3D (ScrStat & B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS) >> N_ESPI_PCR_SL= V_CFG_REG_CTL_SCRS; + if (ScrStat !=3D V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR) { + DEBUG ((DEBUG_ERROR, "eSPI slave config register status (error) is %x = \n", ScrStat)); + return EFI_DEVICE_ERROR; + } + return EFI_SUCCESS; +} + +typedef enum { + EspiSlaveOperationConfigRead, + EspiSlaveOperationConfigWrite, + EspiSlaveOperationStatusRead, + EspiSlaveOperationInBandReset +} ESPI_SLAVE_OPERATION; + +/** + Helper library to do all the operations regards to eSPI slave + + @param[in] SlaveId eSPI Slave ID + @param[in] SlaveAddress Slave address to be put in R_ESPI_PCR_SL= V_CFG_REG_CTL[11:0] + @param[in] SlaveOperation Based on ESPI_SLAVE_OPERATION + @param[in,out] Data + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PCH_LP + @retval EFI_INVALID_PARAMETER Slave configuration register address excee= d maximum allowed + @retval EFI_INVALID_PARAMETER Slave configuration register address is no= t DWord aligned + @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to 0x7= FF has been locked + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +STATIC +EFI_STATUS +EspiSlaveOperationHelper ( + IN UINT32 SlaveId, + IN UINT32 SlaveAddress, + IN ESPI_SLAVE_OPERATION SlaveOperation, + IN OUT UINT32 *Data + ) +{ + EFI_STATUS Status; + UINT32 Data32; + + // + // Check the SlaveId is 0 or 1 + // + if (SlaveId >=3D PCH_MAX_ESPI_SLAVES) { + DEBUG ((DEBUG_ERROR, "eSPI Slave ID of %d or more is not accepted \n",= PCH_MAX_ESPI_SLAVES)); + return EFI_INVALID_PARAMETER; + } + // + // Check if SlaveId 1 is used, it is a PCH_H + // + if ((SlaveId =3D=3D 1) && (IsPchLp ())) { + DEBUG ((DEBUG_ERROR, "eSPI Slave ID of 1 is only available on PCH_H \n= ")); + return EFI_INVALID_PARAMETER; + } + // + // Check the address is not more then 0xFFF + // + if (SlaveAddress > B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA) { + DEBUG ((DEBUG_ERROR, "eSPI Slave address must be less than 0x%x \n", (= B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA + 1))); + return EFI_INVALID_PARAMETER; + } + // + // Check the address is DWord aligned + // + if ((SlaveAddress & 0x3) !=3D 0) { + DEBUG ((DEBUG_ERROR, "eSPI Slave address must be DWord aligned \n")); + return EFI_INVALID_PARAMETER; + } + + // + // Check if write is allowed + // + if ((SlaveOperation =3D=3D EspiSlaveOperationConfigWrite) && + (SlaveAddress <=3D 0x7FF)) { + + // + // If the SLCRR is not set in corresponding slave, we will check the l= ock bit + // + Data32 =3D PchPcrRead32 (PID_ESPISPI, (UINT16) (R_ESPI_PCR_LNKERR_SLV0= + (SlaveId * S_ESPI_PCR_LNKERR_SLV0))); + if ((Data32 & B_ESPI_PCR_LNKERR_SLV0_SLCRR) =3D=3D 0) { + + Data32 =3D PchPcrRead32 (PID_ESPISPI, (UINT16) R_ESPI_PCR_SLV_CFG_RE= G_CTL); + if ((Data32 & B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL) !=3D 0) { + DEBUG ((DEBUG_ERROR, "eSPI Slave write to address range 0 to 0x7FF= has been locked \n")); + return EFI_ACCESS_DENIED; + } + } + } + + // + // Input check done, now go through all the processes + // + EspiClearScrs (); + + if (SlaveOperation =3D=3D EspiSlaveOperationConfigWrite) { + PchPcrWrite32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_SLV_CFG_REG_DATA, + *Data + ); + } + + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_SLV_CFG_REG_CTL, + (UINT32) ~(B_ESPI_PCR_SLV_CFG_REG_CTL_SID | B_ESPI_PCR_SLV_CFG_REG_CTL= _SCRT | B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA), + (B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE | + (SlaveId << N_ESPI_PCR_SLV_CFG_REG_CTL_SID) | + (((UINT32) SlaveOperation) << N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT) | + SlaveAddress + ) + ); + + Status =3D EspiPollScreAndCheckScrs (); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((SlaveOperation =3D=3D EspiSlaveOperationConfigRead) || (SlaveOperat= ion =3D=3D EspiSlaveOperationStatusRead)) { + Data32 =3D PchPcrRead32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_SLV_CFG_REG_DATA + ); + if (SlaveOperation =3D=3D EspiSlaveOperationStatusRead) { + *Data =3D Data32 & 0xFFFF; + } else { + *Data =3D Data32; + } + } + + return EFI_SUCCESS; +} + +/** + Get configuration from eSPI slave + + @param[in] SlaveId eSPI slave ID + @param[in] SlaveAddress Slave Configuration Register Address + @param[out] OutData Configuration data read + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PCH_LP + @retval EFI_INVALID_PARAMETER Slave configuration register address excee= d maximum allowed + @retval EFI_INVALID_PARAMETER Slave configuration register address is no= t DWord aligned + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +EFI_STATUS +PchEspiSlaveGetConfig ( + IN UINT32 SlaveId, + IN UINT32 SlaveAddress, + OUT UINT32 *OutData + ) +{ + // + // 1. Clear status from previous transaction by writing 111b to status i= n SCRS, PCR[eSPI] + 4000h [30:28] + // 2. Program SLV_CFG_REG_CTL with the right value (Bit[31]=3D01, Bit [2= 0:19]=3D, Bit [17:16] =3D 00b, Bit[11:0] =3D . + // 3. Poll the SCRE (PCR[eSPI] +4000h [31]) to be set back to 0 + // 4. Check the transaction status in SCRS (bits [30:28]) + // 5. Read SLV_CFG_REG_DATA. + // + return EspiSlaveOperationHelper (SlaveId, SlaveAddress, EspiSlaveOperati= onConfigRead, OutData); +} + +/** + Set eSPI slave configuration + + Note: A Set_Configuration must always be followed by a Get_Configuration= in order to ensure + that the internal state of the eSPI-MC is consistent with the Slave's re= gister settings. + + @param[in] SlaveId eSPI slave ID + @param[in] SlaveAddress Slave Configuration Register Address + @param[in] InData Configuration data to write + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PCH_LP + @retval EFI_INVALID_PARAMETER Slave configuration register address excee= d maximum allowed + @retval EFI_INVALID_PARAMETER Slave configuration register address is no= t DWord aligned + @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to 0x7= FF has been locked + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +EFI_STATUS +PchEspiSlaveSetConfig ( + IN UINT32 SlaveId, + IN UINT32 SlaveAddress, + IN UINT32 InData + ) +{ + EFI_STATUS Status; + UINT32 Data32; + + // + // 1. Clear status from previous transaction by writing 111b to status i= n SCRS, PCR[eSPI] + 4000h [30:28] + // 2. Program SLV_CFG_REG_DATA with the write value. + // 3. Program SLV_CFG_REG_CTL with the right value (Bit[31]=3D01, Bit [2= 0:19]=3D, Bit [17:16] =3D 01b, Bit[11:0] =3D . + // 4. Poll the SCRE (PCR[eSPI] +4000h [31]) to be set back to 0 + // 5. Check the transaction status in SCRS (bits [30:28]) + // + Status =3D EspiSlaveOperationHelper (SlaveId, SlaveAddress, EspiSlaveOpe= rationConfigWrite, &InData); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D PchEspiSlaveGetConfig (SlaveId, SlaveAddress, &Data32); + return Status; +} + +/** + Get status from eSPI slave + + @param[in] SlaveId eSPI slave ID + @param[out] OutData Configuration data read + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PCH_LP + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +EFI_STATUS +PchEspiSlaveGetStatus ( + IN UINT32 SlaveId, + OUT UINT16 *OutData + ) +{ + EFI_STATUS Status; + UINT32 TempOutData; + + TempOutData =3D 0; + + // + // 1. Clear status from previous transaction by writing 111b to status i= n SCRS, PCR[eSPI] + 4000h [30:28] + // 2. Program SLV_CFG_REG_CTL with the right value (Bit[31]=3D01, Bit [2= 0:19]=3D, Bit [17:16] =3D 10b, Bit[11:0] =3D . + // 3. Poll the SCRE (PCR[eSPI] +4000h [31]) to be set back to 0 + // 4. Check the transaction status in SCRS (bits [30:28]) + // 5. Read SLV_CFG_REG_DATA [15:0]. + // + Status =3D EspiSlaveOperationHelper (SlaveId, 0, EspiSlaveOperationStatu= sRead, &TempOutData); + *OutData =3D (UINT16) TempOutData; + + return Status; +} + +/** + eSPI slave in-band reset + + @param[in] SlaveId eSPI slave ID + + @retval EFI_SUCCESS Operation succeed + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PCH_LP + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation +**/ +EFI_STATUS +PchEspiSlaveInBandReset ( + IN UINT32 SlaveId + ) +{ + // + // 1. Clear status from previous transaction by writing 111b to status i= n SCRS, PCR[eSPI] + 4000h [30:28] + // 2. Program SLV_CFG_REG_CTL with the right value (Bit[31]=3D01, Bit [2= 0:19]=3D, Bit [17:16] =3D 11b). + // 3. Poll the SCRE (PCR[eSPI] +4000h [31]) to be set back to 0 + // 4. Check the transaction status in SCRS (bits [30:28]) + // + return EspiSlaveOperationHelper (SlaveId, 0, EspiSlaveOperationInBandRes= et, NULL); +} + +/** + eSPI Slave channel reset helper function + + @param[in] SlaveId eSPI slave ID + @param[in] ChannelNumber Number of channel to reset + + @retval EFI_SUCCESS Operation succeeded + @retval EFI_UNSUPPORTED Slave doesn't support that channel or inva= lid number specified + @retval EFI_TIMEOUT Operation has timeouted +**/ +EFI_STATUS +PchEspiSlaveChannelReset ( + IN UINT8 SlaveId, + IN UINT8 ChannelNumber + ) +{ + UINT8 Timeout; + UINT32 Data32; + UINT32 SlaveChannelAddress; + BOOLEAN SlaveBmeSet; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "eSPI slave %d channel %d reset\n", SlaveId, Channel= Number)); + + Timeout =3D CHANNEL_RESET_TIMEOUT; + SlaveBmeSet =3D FALSE; + + if (!IsEspiSlaveChannelSupported (SlaveId, ChannelNumber)) { + // Incorrect channel number was specified. Either exceeded max or Slav= e doesn't support that channel. + DEBUG ((DEBUG_ERROR, "Channel %d is not valid channel number for slave= %d!\n", ChannelNumber, SlaveId)); + return EFI_UNSUPPORTED; + } + + // Calculating slave channel address + SlaveChannelAddress =3D R_ESPI_SLAVE_CHACAP_BASE + (S_ESPI_SLAVE_CHACAP_= OFFSET * ChannelNumber); + + // If we're resetting Peripheral Channel then we need to disable Bus Mas= tering first and reenable after reset + if (ChannelNumber =3D=3D 0) { + Status =3D PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data3= 2); + if (EFI_ERROR (Status)) { + return Status; + } + if ((Data32 & B_ESPI_SLAVE_BME) !=3D 0) { + Data32 &=3D ~(B_ESPI_SLAVE_BME); + Status =3D PchEspiSlaveSetConfig (SlaveId, SlaveChannelAddress, Data= 32); + if (EFI_ERROR (Status)) { + return Status; + } + SlaveBmeSet =3D TRUE; + } + } + + // Disable channel + Status =3D PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data32); + if (EFI_ERROR (Status)) { + return Status; + } + Data32 &=3D ~(B_ESPI_SLAVE_CHACAP_CHEN); + Status =3D PchEspiSlaveSetConfig (SlaveId, SlaveChannelAddress, Data32); + if (EFI_ERROR (Status)) { + return Status; + } + // Enable channel + Status =3D PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data32); + if (EFI_ERROR (Status)) { + return Status; + } + Data32 |=3D B_ESPI_SLAVE_CHACAP_CHEN; + Status =3D PchEspiSlaveSetConfig (SlaveId, SlaveChannelAddress, Data32); + if (EFI_ERROR (Status)) { + return Status; + } + DEBUG ((DEBUG_INFO, "Waiting for Channel Ready bit\n")); + // Wait until channel is ready by polling Channel Ready bit + while (((Data32 & B_ESPI_SLAVE_CHACAP_CHRDY) =3D=3D 0) && (Timeout > 0))= { + Status =3D PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data3= 2); + if (EFI_ERROR (Status)) { + return Status; + } + MicroSecondDelay (1); + --Timeout; + } + + if (Timeout =3D=3D 0) { + // The waiting for channel to be ready has timed out + DEBUG ((DEBUG_ERROR, "The operation of channel %d reset for slave %d h= as timed out!\n", ChannelNumber, SlaveId)); + return EFI_TIMEOUT; + } + + if (ChannelNumber =3D=3D 0 && SlaveBmeSet) { + Status =3D PchEspiSlaveGetConfig (SlaveId, SlaveChannelAddress, &Data3= 2); + if (EFI_ERROR (Status)) { + return Status; + } + Data32 |=3D B_ESPI_SLAVE_BME; + Status =3D PchEspiSlaveSetConfig (SlaveId, SlaveChannelAddress, Data32= ); + if (EFI_ERROR (Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbe= Lib/PchGbeLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmP= chGbeLib/PchGbeLib.c new file mode 100644 index 0000000000..652a47ebaf --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchGbeLib/Pch= GbeLib.c @@ -0,0 +1,82 @@ +/** @file + PCH Gbe Library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Check whether GbE region is valid + Check SPI region directly since GbE might be disabled in SW. + + @retval TRUE Gbe Region is valid + @retval FALSE Gbe Region is invalid +**/ +BOOLEAN +PchIsGbeRegionValid ( + VOID + ) +{ + UINT32 SpiBar; + SpiBar =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + R_SPI_CFG_BAR0)) & ~B_SPI_CFG_BAR0_MASK; + ASSERT (SpiBar !=3D 0); + if (MmioRead32 (SpiBar + R_SPI_MEM_FREG3_GBE) !=3D B_SPI_MEM_FREGX_BASE_= MASK) { + return TRUE; + } + return FALSE; +} + + +/** + Check whether LAN controller is enabled in the platform. + + @retval TRUE GbE is enabled + @retval FALSE GbE is disabled +**/ +BOOLEAN +PchIsGbePresent ( + VOID + ) +{ + // + // Check PCH Support + // + if (!PchIsGbeSupported ()) { + return FALSE; + } + // + // Check PMC strap/fuse + // + if (!PmcIsGbeSupported ()) { + return FALSE; + } + // + // Check GbE NVM + // + if (PchIsGbeRegionValid () =3D=3D FALSE) { + return FALSE; + } + return TRUE; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchHsi= oLib/PchHsioLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSm= mPchHsioLib/PchHsioLib.c new file mode 100644 index 0000000000..2be8e8ed49 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchHsioLib/Pc= hHsioLib.c @@ -0,0 +1,127 @@ +/** @file + PCH HSIO Library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + The function returns the Port Id and lane owner for the specified lane + + @param[in] PhyMode Phymode that needs to be checked + @param[out] PortId Common Lane End Point ID + @param[out] LaneOwner Lane Owner + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid lane number +**/ +EFI_STATUS +EFIAPI +PchGetLaneInfo ( + IN UINT32 LaneNum, + OUT UINT8 *PortId, + OUT UINT8 *LaneOwner + ) +{ + return EFI_SUCCESS; +} + +/** + Determine the lane number of a specified port + + @param[out] LaneNum GBE Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetGbeLaneNum ( + UINT8 *LaneNum + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Determine the lane number of a specified port + + @param[in] Usb3LaneIndex USB3 Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetUsb3LaneNum ( + UINT32 Usb3LaneIndex, + UINT8 *LaneNum + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Determine the lane number of a specified port + + @param[in] SataLaneIndex Sata Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetSataLaneNum ( + UINT32 SataLaneIndex, + UINT8 *LaneNum + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Determine the lane number of a specified port + + @param[in] PcieLaneIndex PCIE Root Port Lane Index + @param[out] LaneNum Lane Number + + @retval EFI_SUCCESS Lane number valid. + @retval EFI_UNSUPPORTED Incorrect input device port +**/ +EFI_STATUS +PchGetPcieLaneNum ( + UINT32 PcieLaneIndex, + UINT8 *LaneNum + ) +{ + + return EFI_UNSUPPORTED; +} + +/** + Get HSIO lane representation needed to perform any operation on the lane. + + @param[in] LaneIndex Number of the HSIO lane + @param[out] HsioLane HSIO lane representation +**/ +VOID +HsioGetLane ( + IN UINT8 LaneIndex, + OUT HSIO_LANE *HsioLane + ) +{ + +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInf= oLib/PchInfoLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSm= mPchInfoLib/PchInfoLib.c new file mode 100644 index 0000000000..7c3ade49b6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pc= hInfoLib.c @@ -0,0 +1,272 @@ +/** @file + Pch information library. + + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PchInfoLibPrivate.h" +#include +#include +#include +#include + +/** + Return LPC Device Id + + @retval PCH_LPC_DEVICE_ID PCH Lpc Device ID +**/ +UINT16 +PchGetLpcDid ( + VOID + ) +{ + UINT64 LpcBaseAddress; + + LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + return PciSegmentRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); +} + +/** + Return Pch Series + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeries ( + VOID + ) +{ + PCH_SERIES PchSer; + static PCH_SERIES PchSeries =3D PCH_UNKNOWN_SERIES; + + if (PchSeries !=3D PCH_UNKNOWN_SERIES) { + return PchSeries; + } + + PchSer =3D PchSeriesFromLpcDid (PchGetLpcDid ()); + + PchSeries =3D PchSer; + + return PchSer; +} + +/** + Return Pch stepping type + + @retval PCH_STEPPING Pch stepping type +**/ +PCH_STEPPING +PchStepping ( + VOID + ) +{ + UINT8 RevId; + UINT64 LpcBaseAddress; + static PCH_STEPPING PchStepping =3D PCH_STEPPING_MAX; + + if (PchStepping !=3D PCH_STEPPING_MAX) { + return PchStepping; + } + + LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + RevId =3D PciSegmentRead8 (LpcBaseAddress + PCI_REVISION_ID_OFFSET); + + PchStepping =3D RevId; + + return RevId; +} + +/** + Determine if PCH is supported + + @retval TRUE PCH is supported + @retval FALSE PCH is not supported +**/ +BOOLEAN +IsPchSupported ( + VOID + ) +{ + UINT16 LpcDeviceId; + UINT16 LpcVendorId; + UINT64 LpcBaseAddress; + + LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + LpcDeviceId =3D PciSegmentRead16 (LpcBaseAddress + PCI_DEVICE_ID_OFFSET); + LpcVendorId =3D PciSegmentRead16 (LpcBaseAddress + PCI_VENDOR_ID_OFFSET); + + /// + /// Verify that this is a supported chipset + /// + if ((LpcVendorId =3D=3D V_LPC_CFG_VENDOR_ID) && (PchSeries () !=3D PCH_U= NKNOWN_SERIES)) { + return TRUE; + } else { + DEBUG ((DEBUG_ERROR, "PCH code doesn't support the LpcDeviceId: 0x%04x= !\n", LpcDeviceId)); + return FALSE; + } +} + +/** + Check if this is PCH LP series + + @retval TRUE It's PCH LP series + @retval FALSE It's not PCH LP series +**/ +BOOLEAN +IsPchLp ( + VOID + ) +{ + return (PchSeries () =3D=3D PCH_LP); +} + +/** + Check if this is PCH H series + + @retval TRUE It's PCH H series + @retval FALSE It's not PCH H series +**/ +BOOLEAN +IsPchH ( + VOID + ) +{ + return (PchSeries () =3D=3D PCH_H); +} + +/** + Check if this is CDF PCH generation + + @retval TRUE It's CDF PCH + @retval FALSE It's not CDF PCH +**/ +BOOLEAN +IsCdfPch ( + VOID + ) +{ + return (PchGeneration () =3D=3D CDF_PCH); +} + +/** + Check if this is PCH generation + + @retval TRUE It's CNL PCH + @retval FALSE It's not CNL PCH +**/ +BOOLEAN +IsCnlPch ( + VOID + ) +{ + return (PchGeneration () =3D=3D CNL_PCH); +} + +/** + Get PCH stepping ASCII string. + Function determines major and minor stepping versions and writes them in= to a buffer. + The return string is zero terminated + + @param [out] Buffer Output buffer of string + @param [in] BufferSize Buffer size. + Must not be less then PCH_STEPPING= _STR_LENGTH_MAX + + @retval EFI_SUCCESS String copied successfully + @retval EFI_INVALID_PARAMETER The stepping is not supported, or = parameters are NULL + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small +**/ +EFI_STATUS +PchGetSteppingStr ( + OUT CHAR8 *Buffer, + IN UINT32 BufferSize + ) +{ + PCH_STEPPING PchStep; + + PchStep =3D PchStepping (); + + if ((Buffer =3D=3D NULL) || (BufferSize =3D=3D 0)) { + return EFI_INVALID_PARAMETER; + } + if (BufferSize < PCH_STEPPING_STR_LENGTH_MAX) { + return EFI_BUFFER_TOO_SMALL; + } + + AsciiSPrint (Buffer, BufferSize, "%c%c", 'A' + (PchStep >> 4), '0' + (Pc= hStep & 0xF)); + + return EFI_SUCCESS; +} + +/** + Get PCH Sku ASCII string + The return string is zero terminated. + + @retval Static ASCII string of PCH Sku +**/ +CHAR8* +PchGetSkuStr ( + VOID + ) +{ + UINTN Index; + UINT16 LpcDid; + + LpcDid =3D PchGetLpcDid (); + + for (Index =3D 0; mSkuStrs[Index].Id !=3D 0xFFFF; Index++) { + if (LpcDid =3D=3D mSkuStrs[Index].Id) { + return mSkuStrs[Index].String; + } + } + + return "Undefined SKU"; +} + +/** + Get Pch Maximum Pcie Controller Number + + @retval Pch Maximum Pcie Root Port Number +**/ +UINT8 +GetPchMaxPcieControllerNum ( + VOID + ) +{ + return GetPchMaxPciePortNum () / PCH_PCIE_CONTROLLER_PORTS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInf= oLib/PchInfoLibClient.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pe= iDxeSmmPchInfoLib/PchInfoLibClient.c new file mode 100644 index 0000000000..7b09a2dbb9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pc= hInfoLibClient.c @@ -0,0 +1,87 @@ +/** @file + Common Pch information library for Client PCH silicon. + + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Get Pch Maximum Pcie Clock Number + + @retval Pch Maximum Pcie Clock Number +**/ +UINT8 +GetPchMaxPcieClockNum ( + VOID + ) +{ + if (IsPchH ()) { + return 16; + } else { + return 6; + } +} + +/** + Get Pch Maximum Serial IO controllers number + + @retval Pch Maximum Serial IO controllers number +**/ +UINT8 +GetPchMaxSerialIoControllersNum ( + VOID + ) +{ + return 12; +} + +/** + Get Pch Maximum Serial IO I2C controllers number + + @retval Pch Maximum Serial IO I2C controllers number +**/ +UINT8 +GetPchMaxSerialIoI2cControllersNum ( + VOID + ) +{ + if (IsPchH ()) { + return 4; + } else { + return 6; + } +} + +/** + Get Pch Maximum Serial IO SPI controllers number + + @retval Pch Maximum Serial IO SPI controllers number +**/ +UINT8 +GetPchMaxSerialIoSpiControllersNum ( + VOID + ) +{ + return 3; +} + +/** + Get Pch Maximum Serial IO UART controllers number + + @retval Pch Maximum Serial IO UART controllers number +**/ +UINT8 +GetPchMaxSerialIoUartControllersNum ( + VOID + ) +{ + return 3; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInf= oLib/PchInfoLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDx= eSmmPchInfoLib/PchInfoLibCnl.c new file mode 100644 index 0000000000..431b1470c2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pc= hInfoLibCnl.c @@ -0,0 +1,386 @@ +/** @file + Pch information library. + + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include "PchInfoLibPrivate.h" +#include +#include + +/** + Determine Pch Series based on Device Id + + @param[in] LpcDeviceId Lpc Device Id + + @retval PCH_SERIES Pch Series +**/ +PCH_SERIES +PchSeriesFromLpcDid ( + IN UINT16 LpcDeviceId + ) +{ + switch (LpcDeviceId & B_LPC_CFG_DID) { + + case V_LPC_CFG_DID_CNL_H: + return PCH_H; + + case V_LPC_CFG_DID_CNL_LP: + return PCH_LP; + + default: + return PCH_UNKNOWN_SERIES; + } +} + +/** + Return Pch Generation + + @retval PCH_GENERATION Pch Generation +**/ +PCH_GENERATION +PchGeneration ( + VOID + ) +{ + return CNL_PCH; +} + +/** + Check if this is Server PCH + + @retval TRUE It's a Server PCH + @retval FALSE It's not a Server PCH +**/ +BOOLEAN +IsPchServer ( + VOID + ) +{ + return FALSE; +} + +/** + Get RST mode supported by the silicon + + @retval RST_MODE RST mode supported by silicon +**/ +RST_MODE +PchGetSupportedRstMode ( + VOID + ) +{ + switch (PchGetLpcDid ()) { + + case V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_4: + case V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A303_SKU: + return RstUnsupported; + break; + + default: + return RstPremium; + break; + } +} + +/** + Check if this is Server SKU + + @retval TRUE It's PCH Server SKU + @retval FALSE It's not PCH Server SKU +**/ +BOOLEAN +IsPchServerSku ( + VOID + ) +{ + UINT16 LpcDid; + + LpcDid =3D PchGetLpcDid (); + + if (LpcDid =3D=3D V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A309_SKU) { + return TRUE; + } else { + return FALSE; + } +} + +/** + Get PCH series ASCII string. + + @retval PCH Series string +**/ +CHAR8* +PchGetSeriesStr ( + VOID + ) +{ + switch (PchSeries ()) { + + case PCH_LP: + return "CNL PCH-LP"; + + case PCH_H: + return "CNL PCH-H"; + + default: + return NULL; + } +} + +GLOBAL_REMOVE_IF_UNREFERENCED +struct PCH_SKU_STRING mSkuStrs[] =3D { + // + // PCH LP Mobile LPC Device IDs + // + {V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_SUPER_SKU, "Super SKU"}, + {V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_0, "(U) Super SKU"}, + {V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_1, "Super SKU (locked)"}, + {V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_2, "(Y) Premium SKU"}, + {V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_3, "(U) Premium SKU"}, + {V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_4, "(U) Base/Mainstream SKU"}, + {V_CNL_PCH_LP_LPC_CFG_DEVICE_ID_MB_5, "(Y) Super SKU"}, + // + // PCH H LPC Device IDs + // + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A300_SKU, "CNL PCH-H SKU A300"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A303_SKU, "H310"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A304_SKU, "H370"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A305_SKU, "Z390"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A306_SKU, "Q370"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A309_SKU, "C246"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30A_SKU, "C242"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30B_SKU, "X399"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30C_SKU, "QM370"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30D_SKU, "HM370"}, + {V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A30E_SKU, "CM246"}, + {0xFFFF, NULL} +}; + +/** + Check whether integrated LAN controller is supported by PCH Series. + + @retval TRUE GbE is supported in current PCH + @retval FALSE GbE is not supported on current PCH +**/ +BOOLEAN +PchIsGbeSupported ( + VOID + ) +{ + return TRUE; +} + +/** + Get Pch Maximum Pcie Root Port Number + + @retval Pch Maximum Pcie Root Port Number +**/ +UINT8 +GetPchMaxPciePortNum ( + VOID + ) +{ + if (IsPchLp ()) { + return 16; + } else { + return 24; + } +} + +/** + Get Pch Usb2 Maximum Physical Port Number + + @retval Pch Usb2 Maximum Physical Port Number +**/ +UINT8 +GetPchUsb2MaxPhysicalPortNum ( + VOID + ) +{ + if (IsPchLp ()) { + return 10; + } else { + return 14; + } +} + +/** + Get Pch Maximum Usb2 Port Number of XHCI Controller + + @retval Pch Maximum Usb2 Port Number of XHCI Controller +**/ +UINT8 +GetPchXhciMaxUsb2PortNum ( + VOID + ) +{ + if (IsPchLp ()) { + return 12; + } else { + return 16; + } +} + +/** + Get Pch Maximum Usb3 Port Number of XHCI Controller + + @retval Pch Maximum Usb3 Port Number of XHCI Controller +**/ +UINT8 +GetPchXhciMaxUsb3PortNum ( + VOID + ) +{ + if (IsPchLp ()) { + return 6; + } else { + return 10; + } +} + +/** + Check if given Display Audio Link T-Mode is supported + + @param[in] Tmode T-mode support to be checked + + @retval TRUE T-mode supported + @retval FALSE T-mode not supported +**/ +BOOLEAN +IsAudioIDispTmodeSupported ( + IN PCH_HDAUDIO_IDISP_TMODE Tmode + ) +{ + // + // iDisplay Audio Link T-mode support per PCH Generation/Series: + // 1. 1T - CNP-LP + // 2. 2T - CNP-LP/H (default) + // + switch (Tmode) { + case PchHdaIDispMode1T: + return IsPchLp (); + case PchHdaIDispMode2T: + return TRUE; + case PchHdaIDispMode4T: + case PchHdaIDispMode8T: + case PchHdaIDispMode16T: + default: + return FALSE; + } +} + +/** + Gets the maximum number of UFS controller supported by this chipset. + + @return Number of supported UFS controllers +**/ +UINT8 +PchGetMaxUfsNum ( + VOID + ) +{ + if (IsPchLp ()) { + return 1; + } else { + return 0; + } +} + +/** + Check if this chipset supports eMMC controller + + @retval BOOLEAN TRUE if supported, FALSE otherwise +**/ +BOOLEAN +IsPchEmmcSupported ( + VOID + ) +{ + if (IsPchLp ()) { + return TRUE; + } + + return FALSE; +} + +/** + Check if this chipset supports SD controller + + @retval BOOLEAN TRUE if supported, FALSE otherwise +**/ +BOOLEAN +IsPchSdCardSupported ( + VOID + ) +{ + return TRUE; +} + +/** + Check if this chipset supports UFS controller + + @retval BOOLEAN TRUE if supported, FALSE otherwise +**/ +BOOLEAN +IsPchUfsSupported ( + VOID + ) +{ + if (IsPchLp ()) { + return TRUE; + } + + return FALSE; +} + +/** + Check if link between PCH and CPU is an P-DMI + + @retval TRUE P-DMI link + @retval FALSE Not an P-DMI link +**/ +BOOLEAN +IsPchWithPdmi ( + VOID + ) +{ + return IsPchH (); +} + +/** + Check if link between PCH and CPU is an OP-DMI + + @retval TRUE OP-DMI link + @retval FALSE Not an OP-DMI link +**/ +BOOLEAN +IsPchWithOpdmi ( + VOID + ) +{ + return !IsPchH (); +} + +/** + Check if link between PCH and CPU is an F-DMI + + @retval TRUE F-DMI link + @retval FALSE Not an F-DMI link +**/ +BOOLEAN +IsPchWithFdmi ( + VOID + ) +{ + return FALSE; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPci= eRpLib/PchPcieRpLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiD= xeSmmPchPcieRpLib/PchPcieRpLib.c new file mode 100644 index 0000000000..9997c3612b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcieRpLib/= PchPcieRpLib.c @@ -0,0 +1,183 @@ +/** @file + PCH PCIE root port library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_PCIE_CONTROLLER_INFO mPchPcieContr= ollerInfo[] =3D { + { PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, PID_SPA, 0 }, + { PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, PID_SPB, 4 }, + { PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, PID_SPC, 8 }, + { PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, PID_SPD, 12 }, + { PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, PID_SPE, 16 }, // PCH-H only + { PCI_DEVICE_NUMBER_PCH_PCIE_DEVICE_3, PID_SPF, 20 } // PCH-H only +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 mPchPcieControllerInfoSize =3D = sizeof (mPchPcieControllerInfo) / sizeof (mPchPcieControllerInfo[0]); + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchLpRstPcieStorageSupportedPort[] = =3D { + RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORA= GE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, // RP1..RP4 + RST_PCIE_STORAGE_CR_1, RST_PCIE_STORAGE_CR_1, RST_PCIE_STORA= GE_CR_1, RST_PCIE_STORAGE_CR_1, // RP5..RP8 + RST_PCIE_STORAGE_CR_2, RST_PCIE_STORAGE_CR_2, RST_PCIE_STORA= GE_CR_2, RST_PCIE_STORAGE_CR_2, // RP9..RP12 + RST_PCIE_STORAGE_CR_3, RST_PCIE_STORAGE_CR_3, RST_PCIE_STORA= GE_CR_3, RST_PCIE_STORAGE_CR_3 // RP13..RP16 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchHRstPcieStorageSupportedPort[] =3D= { + RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORA= GE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, // RP1..RP4 + RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORA= GE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, // RP5..RP8 + RST_PCIE_STORAGE_CR_1, RST_PCIE_STORAGE_CR_1, RST_PCIE_STORA= GE_CR_1, RST_PCIE_STORAGE_CR_1, // RP9..RP12 + RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, RST_PCIE_STORA= GE_CR_INVALID, RST_PCIE_STORAGE_CR_INVALID, // RP13..RP16 + RST_PCIE_STORAGE_CR_3, RST_PCIE_STORAGE_CR_3, RST_PCIE_STORA= GE_CR_3, RST_PCIE_STORAGE_CR_3, // RP17..RP20 + RST_PCIE_STORAGE_CR_2, RST_PCIE_STORAGE_CR_2, RST_PCIE_STORA= GE_CR_2, RST_PCIE_STORAGE_CR_2 // RP21..RP24 +}; + +/** + Get Pch Pcie Root Port Device and Function Number by Root Port physical = Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device = number. + @param[out] RpFun Return corresponding root port functio= n number. + + @retval EFI_SUCCESS Root port device and function is retri= eved + @retval EFI_INVALID_PARAMETER RpNumber is invalid +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpDevFun ( + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFun + ) +{ + UINTN Index; + UINTN FuncIndex; + UINT32 PciePcd; + + if (RpNumber >=3D GetPchMaxPciePortNum ()) { + DEBUG ((DEBUG_ERROR, "GetPchPcieRpDevFun invalid RpNumber %x", RpNumbe= r)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Index =3D RpNumber / PCH_PCIE_CONTROLLER_PORTS; + FuncIndex =3D RpNumber - mPchPcieControllerInfo[Index].RpNumBase; + *RpDev =3D mPchPcieControllerInfo[Index].DevNum; + PciePcd =3D PchPcrRead32 (mPchPcieControllerInfo[Index].Pid, R_SPX_PCR_P= CD); + *RpFun =3D (PciePcd >> (FuncIndex * S_SPX_PCR_PCD_RP_FIELD)) & B_SPX_PCR= _PCD_RP1FN; + + return EFI_SUCCESS; +} + +/** + Get Root Port physical Number by Pch Pcie Root Port Device and Function = Number + + @param[in] RpDev Root port device number. + @param[in] RpFun Root port function number. + @param[out] RpNumber Return corresponding physical Root Por= t index (0-based) + + @retval EFI_SUCCESS Physical root port is retrieved +**/ +EFI_STATUS +EFIAPI +GetPchPcieRpNumber ( + IN UINTN RpDev, + IN UINTN RpFun, + OUT UINTN *RpNumber + ) +{ + UINT64 RpBase; + + RpBase =3D PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH, DEFA= ULT_PCI_BUS_NUMBER_PCH, RpDev, RpFun, 0); + *RpNumber =3D (PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_LCAP) >> N_PCH_= PCIE_CFG_LCAP_PN) -1; + return EFI_SUCCESS; +} + +/** + Gets pci segment base address of PCIe root port. + + @param RpIndex Root Port Index (0 based) + @return PCIe port base address. +**/ +UINT64 +PchPcieBase ( + IN UINT32 RpIndex + ) +{ + UINTN RpDevice; + UINTN RpFunction; + + GetPchPcieRpDevFun (RpIndex, &RpDevice, &RpFunction); + + return PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH, DEFAULT_= PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction, 0); +} + +/** + Determines whether L0s is supported on current stepping. + + @return TRUE if L0s is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieL0sSupported ( + VOID + ) +{ + return TRUE; +} + +/** + Some early PCH steppings require Native ASPM to be disabled due to hardw= are issues: + - RxL0s exit causes recovery + - Disabling PCIe L0s capability disables L1 + Use this function to determine affected steppings. + + @return TRUE if Native ASPM is supported, FALSE otherwise +**/ +BOOLEAN +PchIsPcieNativeAspmSupported ( + VOID + ) +{ + return PchIsPcieL0sSupported (); +} + +/** + Check the RST PCIe Storage Cycle Router number according to the root por= t number and PCH type + + @param[in] RootPortNum Root Port Number + + @return The RST PCIe Storage Cycle Router Number +**/ +UINT8 +RstGetCycleRouterNumber ( + IN UINT32 RootPortNum + ) +{ + if (IsPchLp ()) { + if (RootPortNum < ARRAY_SIZE (mPchLpRstPcieStorageSupportedPort)) { + return mPchLpRstPcieStorageSupportedPort[RootPortNum]; + } + } else if (IsPchH ()) { + if (RootPortNum < ARRAY_SIZE (mPchHRstPcieStorageSupportedPort)) { + return mPchHRstPcieStorageSupportedPort[RootPortNum]; + } + } + return RST_PCIE_STORAGE_CR_INVALID; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcr= Lib/PchPcrLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmP= chPcrLib/PchPcrLib.c new file mode 100644 index 0000000000..6f70733fe7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPcrLib/Pch= PcrLib.c @@ -0,0 +1,279 @@ +/** @file + PCH PCR library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef MDEPKG_NDEBUG +/** + Checks if the offset is valid for a given memory access width + + @param[in] Offset Offset of a register + @param[in] Size Size of memory access in bytes + + @retval FALSE Offset is not valid for a given memory access + @retval TRUE Offset is valid +**/ +STATIC +BOOLEAN +PchIsPcrOffsetValid ( + IN UINT32 Offset, + IN UINTN Size + ) +{ + if (((Offset & (Size - 1)) !=3D 0) || (Offset > 0xFFFF)) { + DEBUG ((DEBUG_ERROR, "PCR offset error. Invalid Offset: %x Size: %x", = Offset, Size)); + return FALSE; + } else { + return TRUE; + } +} +#endif + +/** + Read PCR register. + It returns PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT32 PCR register value. +**/ +UINT32 +PchPcrRead32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ) +{ +#ifndef MDEPKG_NDEBUG + ASSERT (PchIsPcrOffsetValid (Offset, 4)); +#endif + return MmioRead32 (PCH_PCR_ADDRESS (Pid, Offset)); +} + +/** + Read PCR register. + It returns PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT16 PCR register value. +**/ +UINT16 +PchPcrRead16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ) +{ +#ifndef MDEPKG_NDEBUG + ASSERT (PchIsPcrOffsetValid (Offset, 2)); +#endif + return MmioRead16 (PCH_PCR_ADDRESS (Pid, Offset)); +} + +/** + Read PCR register. + It returns PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of this Port ID + + @retval UINT8 PCR register value +**/ +UINT8 +PchPcrRead8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset + ) +{ + return MmioRead8 (PCH_PCR_ADDRESS (Pid, Offset)); +} + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter. + + @retval UINT32 Value written to register +**/ +UINT32 +PchPcrWrite32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 Data + ) +{ +#ifndef MDEPKG_NDEBUG + ASSERT (PchIsPcrOffsetValid (Offset, 4)); +#endif + MmioWrite32 (PCH_PCR_ADDRESS (Pid, Offset), Data); + + return Data; +} + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter. + + @retval UINT16 Value written to register +**/ +UINT16 +PchPcrWrite16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT16 Data + ) +{ +#ifndef MDEPKG_NDEBUG + ASSERT (PchIsPcrOffsetValid (Offset, 2)); +#endif + MmioWrite16 (PCH_PCR_ADDRESS (Pid, Offset), Data); + + return Data; +} + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] Data Input Data. Must be the same size as Size parameter. + + @retval UINT8 Value written to register +**/ +UINT8 +PchPcrWrite8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT8 Data + ) +{ + MmioWrite8 (PCH_PCR_ADDRESS (Pid, Offset), Data); + + return Data; +} + +/** + Write PCR register. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT32 Value written to register + +**/ +UINT32 +PchPcrAndThenOr32 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + return PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) & AndData= ) | OrData); +} + +/** + Write PCR register and read back. + The read back ensures the PCR cycle is completed before next operation. + It programs PCR register and size in 4bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT32 Value read back from the register +**/ +UINT32 +PchPcrAndThenOr32WithReadback ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT32 AndData, + IN UINT32 OrData + ) +{ + PchPcrWrite32 (Pid, Offset, (PchPcrRead32 (Pid, Offset) & AndData) | OrD= ata); + return PchPcrRead32 (Pid, Offset); +} + +/** + Write PCR register. + It programs PCR register and size in 2bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT16 Value written to register + +**/ +UINT16 +PchPcrAndThenOr16 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT16 AndData, + IN UINT16 OrData + ) +{ + return PchPcrWrite16 (Pid, Offset, (PchPcrRead16 (Pid, Offset) & AndData= ) | OrData); +} + +/** + Write PCR register. + It programs PCR register and size in 1bytes. + The Offset should not exceed 0xFFFF and must be aligned with size. + + @param[in] Pid Port ID + @param[in] Offset Register offset of Port ID. + @param[in] AndData AND Data. Must be the same size as Size parameter. + @param[in] OrData OR Data. Must be the same size as Size parameter. + + @retval UINT8 Value written to register + +**/ +UINT8 +PchPcrAndThenOr8 ( + IN PCH_SBI_PID Pid, + IN UINT32 Offset, + IN UINT8 AndData, + IN UINT8 OrData + ) +{ + return PchPcrWrite8 (Pid, Offset, (PchPcrRead8 (Pid, Offset) & AndData) = | OrData); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmc= Lib/PchPmcLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmP= chPmcLib/PchPmcLib.c new file mode 100644 index 0000000000..2654a76983 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchPmcLib/Pch= PmcLib.c @@ -0,0 +1,101 @@ +/** @file + PCH PMC Library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Query PCH to determine the Pm Status + NOTE: + It's matter when did platform code use this library, since some status c= ould be cleared by write one clear. + Therefore this funciton is not always return the same result in one boot. + It's suggested that platform code read this status in the beginning of p= ost. + For the ColdBoot case, this function only returns one case of the cold b= oot. Some cold boot case might + depends on the power cycle scenario and should check with different cond= tion. + + @param[in] PmStatus - The Pch Pm Status to be probed + + @retval Return TRUE if Status querried is Valid or FALSE if otherwise +**/ +BOOLEAN +GetPchPmStatus ( + PCH_PM_STATUS PmStatus + ) +{ + UINTN PmcRegBase; + UINT32 GblRst0; + + PmcRegBase =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + + switch (PmStatus) { + case WarmBoot: + break; + + case PwrFlr: + break; + + case PwrFlrSys: + if (GblRst0 & BIT12) { + return TRUE; + } + break; + + case PwrFlrPch: + if (GblRst0 & BIT11) { + return TRUE; + } + break; + + case ColdBoot: + break; + + default: + break; + } + + return FALSE; +} + +/** + Funtion to check if Battery lost or CMOS cleared. + + @reval TRUE Battery is always present. + @reval FALSE CMOS is cleared. +**/ +BOOLEAN +EFIAPI +PchIsRtcBatteryGood ( + VOID + ) +{ + UINTN PmcBaseAddress; + + // + // Check if the CMOS battery is present + // Checks RTC_PWR_STS bit in the GEN_PMCON_3 register + // + PmcBaseAddress =3D MmPciBase ( + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC + ); + return FALSE; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSbi= AccessLib/PchSbiAccessLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Librar= y/PeiDxeSmmPchSbiAccessLib/PchSbiAccessLib.c new file mode 100644 index 0000000000..43690e2409 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSbiAccessL= ib/PchSbiAccessLib.c @@ -0,0 +1,270 @@ +/** @file + PCH SBI access library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Execute PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiE= xecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. = If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be= checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would = provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + @retval EFI_TIMEOUT Timeout while waiting for response +**/ +EFI_STATUS +EFIAPI +PchSbiExecution ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + // + // Check address valid + // + if (((UINT32) Offset & 0x3) !=3D 0) { + // + // Warning message for the address not DWORD alignment. + // + DEBUG ((DEBUG_INFO, "PchSbiExecution: Address is not DWORD aligned.\n"= )); + } + + return PchSbiExecutionEx ( Pid, + Offset, + Opcode, + Posted, + 0x000F, + 0x0000, + 0x0000, + Data32, + Response + ); +} + +/** + Full function for executing PCH SBI message + Take care of that there is no lock protection when using SBI programming= in both POST time and SMI. + It will clash with POST time SBI programming when SMI happen. + Programmer MUST do the save and restore opration while using the PchSbiE= xecution inside SMI + to prevent from racing condition. + This function will reveal P2SB and hide P2SB if it's originally hidden. = If more than one SBI access + needed, it's better to unhide the P2SB before calling and hide it back a= fter done. + + When the return value is "EFI_SUCCESS", the "Response" do not need to be= checked as it would have been + SBI_SUCCESS. If the return value is "EFI_DEVICE_ERROR", then this would = provide additional information + when needed. + + @param[in] Pid Port ID of the SBI message + @param[in] Offset Offset of the SBI message + @param[in] Opcode Opcode + @param[in] Posted Posted message + @param[in] Fbe First byte enable + @param[in] Bar Bar + @param[in] Fid Function ID + @param[in, out] Data32 Read/Write data + @param[out] Response Response + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_DEVICE_ERROR Transaction fail + @retval EFI_INVALID_PARAMETER Invalid parameter + @retval EFI_TIMEOUT Timeout while waiting for response +**/ +EFI_STATUS +EFIAPI +PchSbiExecutionEx ( + IN PCH_SBI_PID Pid, + IN UINT64 Offset, + IN PCH_SBI_OPCODE Opcode, + IN BOOLEAN Posted, + IN UINT16 Fbe, + IN UINT16 Bar, + IN UINT16 Fid, + IN OUT UINT32 *Data32, + OUT UINT8 *Response + ) +{ + UINT64 P2sbBase; + UINTN Timeout; + UINT16 SbiStat; + + // + // Check opcode valid + // + switch (Opcode) { + case MemoryRead: + case MemoryWrite: + case PciConfigRead: + case PciConfigWrite: + case PrivateControlRead: + case PrivateControlWrite: + case GpioLockUnlock: + break; + default: + return EFI_INVALID_PARAMETER; + break; + } + + P2sbBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_P2SB, + PCI_FUNCTION_NUMBER_PCH_P2SB, + 0 + ); + if (PciSegmentRead16 (P2sbBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_DEVICE_ERROR; + } + /// + /// BWG Section 2.2.1 + /// 1. Poll P2SB PCI offset D8h[0] =3D 0b + /// Make sure the previous opeartion is completed. + /// + Timeout =3D 0xFFFFFFF; + while (Timeout > 0) { + SbiStat =3D PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT); + if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) =3D=3D 0) { + break; + } + Timeout--; + } + if (Timeout =3D=3D 0) { + return EFI_TIMEOUT; + } + // + // Initial Response status + // + *Response =3D SBI_INVALID_RESPONSE; + SbiStat =3D 0; + /// + /// 2. Write P2SB PCI offset D0h[31:0] with Address and Destination Port= ID + /// + PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIADDR, (UINT32) ((Pid << 24) = | (UINT16) Offset)); + /// + /// 3. Write P2SB PCI offset DCh[31:0] with extended address, which is e= xpected to be 0 in PCH. + /// + PciSegmentWrite32 (P2sbBase + R_P2SB_CFG_SBIEXTADDR, (UINT32) RShiftU64 = (Offset, 16)); + /// + /// 5. Set P2SB PCI offset D8h[15:8] =3D 00000110b for read + /// Set P2SB PCI offset D8h[15:8] =3D 00000111b for write + // + // Set SBISTAT[15:8] to the opcode passed in + // Set SBISTAT[7] to the posted passed in + // + PciSegmentAndThenOr16 ( + (P2sbBase + R_P2SB_CFG_SBISTAT), + (UINT16) ~(B_P2SB_CFG_SBISTAT_OPCODE | B_P2SB_CFG_SBISTAT_POSTED), + (UINT16) ((Opcode << 8) | (Posted << 7)) + ); + /// + /// 6. Write P2SB PCI offset DAh[15:0] =3D F000h + /// + // + // Set RID[15:0] =3D Fbe << 12 | Bar << 8 | Fid + // + PciSegmentWrite16 ( + (P2sbBase + R_P2SB_CFG_SBIRID), + (((Fbe & 0x000F) << 12) | ((Bar & 0x0007) << 8) | (Fid & 0x00FF)) + ); + + switch (Opcode) { + case MemoryWrite: + case PciConfigWrite: + case PrivateControlWrite: + case GpioLockUnlock: + /// + /// 4. Write P2SB PCI offset D4h[31:0] with the intended data accord= ingly + /// + PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), *Data32); + break; + default: + /// + /// 4. Write P2SB PCI offset D4h[31:0] with dummy data such as 0, + /// because all D0-DFh register range must be touched in PCH + /// for a successful SBI transaction. + /// + PciSegmentWrite32 ((P2sbBase + R_P2SB_CFG_SBIDATA), 0); + break; + } + /// + /// 7. Set P2SB PCI offset D8h[0] =3D 1b, Poll P2SB PCI offset D8h[0] = =3D 0b + /// + // + // Set SBISTAT[0] =3D 1b, trigger the SBI operation + // + PciSegmentOr16 (P2sbBase + R_P2SB_CFG_SBISTAT, (UINT16) B_P2SB_CFG_SBIST= AT_INITRDY); + // + // Poll SBISTAT[0] =3D 0b, Polling for Busy bit + // + Timeout =3D 0xFFFFFFF; + while (Timeout > 0) { + SbiStat =3D PciSegmentRead16 (P2sbBase + R_P2SB_CFG_SBISTAT); + if ((SbiStat & B_P2SB_CFG_SBISTAT_INITRDY) =3D=3D 0) { + break; + } + Timeout--; + } + if (Timeout =3D=3D 0) { + // + // If timeout, it's fatal error. + // + return EFI_TIMEOUT; + } else { + /// + /// 8. Check if P2SB PCI offset D8h[2:1] =3D 00b for successful transa= ction + /// + *Response =3D (UINT8) ((SbiStat & B_P2SB_CFG_SBISTAT_RESPONSE) >> N_P2= SB_CFG_SBISTAT_RESPONSE); + if (*Response =3D=3D SBI_SUCCESSFUL) { + switch (Opcode) { + case MemoryRead: + case PciConfigRead: + case PrivateControlRead: + /// + /// 9. Read P2SB PCI offset D4h[31:0] for SBI data + /// + *Data32 =3D PciSegmentRead32 (P2sbBase + R_P2SB_CFG_SBIDATA); + break; + default: + break; + } + return EFI_SUCCESS; + } else { + return EFI_DEVICE_ERROR; + } + } +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSer= ialIoLib/PchSerialIoLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/= PeiDxeSmmPchSerialIoLib/PchSerialIoLib.c new file mode 100644 index 0000000000..0e79d83a12 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoLi= b/PchSerialIoLib.c @@ -0,0 +1,516 @@ +/** @file + PCH Serial IO Lib implementation. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCIEX_BAR_ADDR_MASK 0x0000007FFC000000 + +typedef struct { + UINT32 Bar0; + UINT32 Bar1; +} SERIAL_IO_CONTROLLER_DESCRIPTOR; + +GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoAcp= iAddress [PCH_MAX_SERIALIO_CONTROLLERS] =3D +{ + {PCH_SERIAL_IO_BASE_ADDRESS + 0x0000, PCH_SERIAL_IO_BASE_ADDRESS + 0x10= 00}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0x2000, PCH_SERIAL_IO_BASE_ADDRESS + 0x30= 00}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0x4000, PCH_SERIAL_IO_BASE_ADDRESS + 0x50= 00}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0x6000, PCH_SERIAL_IO_BASE_ADDRESS + 0x70= 00}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0x8000, PCH_SERIAL_IO_BASE_ADDRESS + 0x90= 00}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0xA000, PCH_SERIAL_IO_BASE_ADDRESS + 0xB0= 00}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0xC000, PCH_SERIAL_IO_BASE_ADDRESS + 0xD0= 00}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0xE000, PCH_SERIAL_IO_BASE_ADDRESS + 0xF0= 00}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0x10000, PCH_SERIAL_IO_BASE_ADDRESS + 0x11= 000}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0x12000, PCH_SERIAL_IO_BASE_ADDRESS + 0x13= 000}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0x14000, PCH_SERIAL_IO_BASE_ADDRESS + 0x15= 000}, + {PCH_SERIAL_IO_BASE_ADDRESS + 0x16000, PCH_SERIAL_IO_BASE_ADDRESS + 0x17= 000} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchSerialIoPciCfgCtrAddr [PCH_MAX_SE= RIALIO_CONTROLLERS] =3D +{ + R_SERIAL_IO_PCR_PCICFGCTRL1, + R_SERIAL_IO_PCR_PCICFGCTRL2, + R_SERIAL_IO_PCR_PCICFGCTRL3, + R_SERIAL_IO_PCR_PCICFGCTRL4, + R_SERIAL_IO_PCR_PCICFGCTRL5, + R_SERIAL_IO_PCR_PCICFGCTRL6, + R_SERIAL_IO_PCR_PCICFGCTRL13, + R_SERIAL_IO_PCR_PCICFGCTRL14, + R_SERIAL_IO_PCR_PCICFGCTRL9, + R_SERIAL_IO_PCR_PCICFGCTRL10, + R_SERIAL_IO_PCR_PCICFGCTRL11 +}; + +/** + Returns Serial IO Controller Type I2C, SPI or UART + + @param[in] Number Number of SerialIo controller + + @retval I2C, SPI or UART + @retval UNKNOWN - in case if undefined controller +**/ +PCH_SERIAL_IO_CONTROLLER_TYPE +GetSerialIoControllerType ( + IN PCH_SERIAL_IO_CONTROLLER Controller + ) +{ + if (Controller >=3D PchSerialIoIndexI2C0 && Controller <=3D GetMaxI2cNum= ber ()) { + return SERIAL_IO_I2C; + } else if (Controller >=3D PchSerialIoIndexSpi0 && Controller < (PchSeri= alIoIndexSpi0 + GetPchMaxSerialIoSpiControllersNum ())) { + return SERIAL_IO_SPI; + } else if (Controller >=3D PchSerialIoIndexUart0 && Controller <=3D PchS= erialIoIndexUart2) { + return SERIAL_IO_UART; + } + return SERIAL_IO_UNKNOWN; +} + +/** + Checks if given Serial IO Controller Function equals 0 + + @param[in] SerialIoNumber Serial IO device + + @retval TRUE if SerialIO Function is equal= to 0 + FALSE if Function is higher then 0 +**/ +BOOLEAN +IsSerialIoFunctionZero ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ) +{ + if (GetSerialIoFunctionNumber (SerialIoNumber) > 0) { + return FALSE; + } + return TRUE; +} + +/** + Checks if given Serial IO Controller is enabled or not + + @param[in] DeviceNumber device number + @param[in] FunctionNumber function number + + @retval TRUE TRUE if given serial io device is = enabled. + @retval FALSE FALSE if given serial io device is= disabled. +**/ +BOOLEAN +IsSerialIoDeviceEnabled ( + IN UINT8 DeviceNumber, + IN UINT8 FunctionNumber + ) +{ + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBE= R_PCH, DEFAULT_PCI_BUS_NUMBER_PCH, DeviceNumber, FunctionNumber, PCI_DEVICE= _ID_OFFSET)) !=3D 0xFFFF) { + return TRUE; + } + return FALSE; +} + +/** + Checks if given device corresponds to any of LPSS Devices + + @param[in] DeviceNumber device number + @param[in] FunctionNumber function number + + @retval TRUE if SerialIO Device/Function N= umber is equal to any of LPSS devices + FALSE Device/Function is not in Se= rial IO scope +**/ +BOOLEAN +IsSerialIoDevice ( + IN UINT8 DeviceNumber, + IN UINT8 FunctionNumber + ) +{ + PCH_SERIAL_IO_CONTROLLER Controller; + PCH_SERIAL_IO_CONTROLLER ControllerMax; + + ControllerMax =3D GetPchMaxSerialIoControllersNum (); + + for (Controller =3D 0; Controller < ControllerMax; Controller++) { + if ((DeviceNumber =3D=3D GetSerialIoDeviceNumber (Controller)) && + (FunctionNumber =3D=3D GetSerialIoFunctionNumber (Controller))) { + return TRUE; + } + } + return FALSE; +} + +/** + Gets Pci Config control offset + + @param[in] DeviceNumber device number + @param[in] FunctionNumber function number + + @retval CfgCtrAddr Offset of Pci config control + 0 if Device and Function do not co= rrespond to Serial IO +**/ +UINT16 +GetSerialIoConfigControlOffset ( + IN UINT8 DeviceNumber, + IN UINT8 FunctionNumber + ) +{ + PCH_SERIAL_IO_CONTROLLER Controller; + PCH_SERIAL_IO_CONTROLLER ControllerMax; + + ControllerMax =3D GetPchMaxSerialIoControllersNum (); + + for (Controller =3D 0; Controller < ControllerMax; Controller++) { + if ((DeviceNumber =3D=3D GetSerialIoDeviceNumber (Controller)) && + (FunctionNumber =3D=3D GetSerialIoFunctionNumber (Controller))) { + return mPchSerialIoPciCfgCtrAddr[Controller]; + } + } + + return 0; +} + +/** + Checks if Device with given AcpiHid string is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Numbe= r is not updated + + @param[in] AcpiHid String + @param[out] Number Number of SerialIo controller + + @retval TRUE yes it is a SerialIo controller + @retval FALSE no it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoAcpiHid ( + IN CHAR8 *AcpiHid, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ) +{ + PCH_SERIAL_IO_CONTROLLER Controller; + PCH_SERIAL_IO_CONTROLLER ControllerMax; + + ControllerMax =3D GetPchMaxSerialIoControllersNum (); + + for (Controller =3D 0; Controller < ControllerMax; Controller++) { + if (!AsciiStrCmp ((const CHAR8 *) AcpiHid, GetSerialIoAcpiHid(Controll= er))) { + *Number =3D Controller; + return TRUE; + } + } + return FALSE; +} + +/** + Finds BAR values of SerialIo devices. + SerialIo devices can be configured to not appear on PCI so traditional m= ethod of reading BAR might not work. + If the SerialIo device is in PCI mode, a request for BAR1 will return it= s PCI CFG space instead + + @param[in] SerialIoDevice Serial IO device + @param[in] BarNumber 0=3DBAR0, 1=3DBAR1 + + @retval SerialIo Bar value +**/ +UINTN +FindSerialIoBar ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoDevice, + IN UINT8 BarNumber + ) +{ + UINT64 Bar; + UINT64 PcieBase; + UINT64 PciSegBase; + UINT16 VenId; + UINT32 Device; + UINT32 Function; + + Device =3D GetSerialIoDeviceNumber (SerialIoDevice); + Function =3D GetSerialIoFunctionNumber (SerialIoDevice); + + PcieBase =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_M= C_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_PCIEXBAR)); // S0:B0:D0:F0:R60 + PcieBase =3D (PcieBase & PCIEX_BAR_ADDR_MASK) + LShiftU64 (DEFAULT_PCI_B= US_NUMBER_PCH, 20) + LShiftU64 (Device, 15) + LShiftU64 (Function, 12); + + PciSegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + Device, + Function, + 0 + ); + + VenId =3D PciSegmentRead16 (PciSegBase + PCI_VENDOR_ID_OFFSET) & 0xFFFF; + if (VenId =3D=3D V_PCH_INTEL_VENDOR_ID) { + if (BarNumber =3D=3D 1) { + return ((UINTN) PcieBase); + } + Bar =3D PciSegmentRead32 (PciSegBase + PCI_BASE_ADDRESSREG_OFFSET); + // For 64-Bit Memory Space BARs ((BAR[x] & 0xFFFFFFF0) + ((BAR[x+1] & = 0xFFFFFFFF) << 32) + if ((Bar & B_PCI_BAR_MEMORY_TYPE_MASK) =3D=3D B_PCI_BAR_MEMORY_TYPE_64= ) { + Bar =3D (Bar & 0xFFFFF000) + (UINTN) ((UINT64) LShiftU64 ((PciSegmen= tRead32 (PciSegBase + PCI_BASE_ADDRESSREG_OFFSET + 4) & 0xFFFFFFFF), 32)); + return (UINTN) Bar; + } + return (UINTN) (Bar & 0xFFFFF000); + } + //PCI mode failed? Try hardcoded addresses from ACPI + if (BarNumber =3D=3D 0) { + Bar =3D mSerialIoAcpiAddress[SerialIoDevice].Bar0; + } else { + Bar =3D mSerialIoAcpiAddress[SerialIoDevice].Bar1; + } + return (UINTN) Bar; +} + +/** + Get PSF_PORT for a given Serial IO Controller + + @param[in] Controller Serial IO controller number +**/ +STATIC +PSF_PORT +SerialIoPsfPort ( + IN PCH_SERIAL_IO_CONTROLLER Controller + ) +{ + switch (GetSerialIoControllerType (Controller)) { + case SERIAL_IO_I2C: + return PsfSerialIoI2cPort (Controller - PchSerialIoIndexI2C0); + case SERIAL_IO_SPI: + return PsfSerialIoSpiPort (Controller - PchSerialIoIndexSpi0); + case SERIAL_IO_UART: + return PsfSerialIoUartPort (Controller - PchSerialIoIndexUart0); + case SERIAL_IO_UNKNOWN: + default: + return (PSF_PORT){0}; + } +} + +/** + Configures Serial IO Controller + + @param[in] Controller Serial IO controller number + @param[in] DeviceMode Device operation mode + @param[in] PsfDisable Disable device at PSF level + + @retval None +**/ +VOID +ConfigureSerialIoController ( + IN PCH_SERIAL_IO_CONTROLLER Controller, + IN PCH_SERIAL_IO_MODE DeviceMode, + IN BOOLEAN PsfDisable + ) +{ + UINT64 PciCfgBase; + UINT32 Data32And; + UINT32 Data32Or; + UINT16 *SerialIoPciCfgCtrAddr; + UINT8 Uart8BitLoop; + +/* + Please do not add DEBUG message here because this routine is configuring= SerialIoUart. + Printing DEBUG message before SerialIoUart initialization may cause syst= em hang (in Debug build). +*/ + + // + // This is to prevent from overflow of array access. + // + if (Controller >=3D PCH_MAX_SERIALIO_CONTROLLERS) { + return; + } + + if (GetSerialIoControllerType (Controller) =3D=3D SERIAL_IO_UNKNOWN) { + return; + } + + PciCfgBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + GetSerialIoDeviceNumber (Controller), + GetSerialIoFunctionNumber (Controller), + 0 + ); + // + // Do not modify a device that has already been disabled/hidden + // + if (PciSegmentRead16 (PciCfgBase + PCI_VENDOR_ID_OFFSET) !=3D V_PCH_INTE= L_VENDOR_ID) { + return; + } + + /// + /// Step 0. set Bit 16,17,18. + /// + PciSegmentOr32 (PciCfgBase + R_SERIAL_IO_CFG_D0I3MAXDEVPG, BIT18 | BIT17= | BIT16); + + SerialIoPciCfgCtrAddr =3D mPchSerialIoPciCfgCtrAddr; + + switch (DeviceMode) { + case PchSerialIoDisabled: + /// + /// Step 1. Put device in D3 + /// Step 2. Function Disable in PSF + /// + PciSegmentOr32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, BIT1 | BI= T0); + + if (PsfDisable) { + PsfDisableDevice (SerialIoPsfPort (Controller)); + } + break; + case PchSerialIoAcpi: + case PchSerialIoHidden: + /// + /// reenable BAR1 in case it was disabled earlier + /// Read back is needed to enforce the sideband and primary ordering. + /// + PchPcrAndThenOr32WithReadback ( + PID_SERIALIO, + SerialIoPciCfgCtrAddr[Controller], + (UINT32) ~(B_SERIAL_IO_PCR_PCICFGCTRL_BAR1_DIS), + 0 + ); + PsfEnableDeviceBar (SerialIoPsfPort (Controller), BIT3 | BIT2); + /// + /// Step 1. Assign BAR0 + /// Step 2. Assign BAR1 + /// + PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_LOW, mSerialIo= AcpiAddress[Controller].Bar0); + PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_HIGH, 0x0); + PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR1_LOW, mSerialIo= AcpiAddress[Controller].Bar1); + PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR1_HIGH, 0x0); + /// + /// Step 3. Set Memory space Enable + /// + PciSegmentOr32 (PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEM= ORY_SPACE); + /// + /// Step 4. Disable device's PciCfg and enable ACPI interrupts + /// Read back is needed to enforce the sideband and primary = ordering. + /// + PchPcrAndThenOr32WithReadback ( + PID_SERIALIO, + SerialIoPciCfgCtrAddr[Controller], + ~0u, + (B_SERIAL_IO_PCR_PCICFGCTRL_PCI_CFG_DIS | B_SERIAL_IO_PCR_PCICFGCT= RL_ACPI_INTR_EN) + ); + /// + /// Step 5. Disable device's PciCfg in PSF + /// + PsfHideDevice (SerialIoPsfPort (Controller)); + /// + /// get controller out of reset + /// + MmioOr32 ( + mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_PPR_RESETS, + B_SERIAL_IO_MEM_PPR_RESETS_FUNC | B_SERIAL_IO_MEM_PPR_RESETS_APB |= B_SERIAL_IO_MEM_PPR_RESETS_IDMA + ); + break; + case PchSerialIoPci: + // + // Check If device is already initialized + // + if (PciSegmentRead32 (PciCfgBase + PCI_BASE_ADDRESSREG_OFFSET) & 0xF= FFFF000) { + return; + } + /// + /// reenable PciCfg in case it was disabled earlier + /// Read back is needed to enforce the sideband and primary ordering. + /// + PchPcrAndThenOr32WithReadback ( + PID_SERIALIO, + SerialIoPciCfgCtrAddr[Controller], + (UINT32) ~(B_SERIAL_IO_PCR_PCICFGCTRL_PCI_CFG_DIS | B_SERIAL_IO_PC= R_PCICFGCTRL_ACPI_INTR_EN), + 0 + ); + PsfUnhideDevice (SerialIoPsfPort (Controller)); + /// + /// Disable Bar1 + /// Disable Bar1 in PSF + /// Read back is needed to enforce the sideband and primary ordering. + /// + PchPcrAndThenOr32WithReadback ( + PID_SERIALIO, + SerialIoPciCfgCtrAddr[Controller], + ~0u, + B_SERIAL_IO_PCR_PCICFGCTRL_BAR1_DIS + ); + PsfDisableDeviceBar (SerialIoPsfPort (Controller), BIT3 | BIT2); + + // + // Assign BAR0 and Set Memory space Enable + // + PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_LOW, mSerialIo= AcpiAddress[Controller].Bar0); + PciSegmentWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_HIGH, 0x0); + PciSegmentOr32 (PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_= MEMORY_SPACE); + /// + /// get controller out of reset + /// + MmioOr32 ( + mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_PPR_RESETS, + B_SERIAL_IO_MEM_PPR_RESETS_FUNC | B_SERIAL_IO_MEM_PPR_RESETS_APB |= B_SERIAL_IO_MEM_PPR_RESETS_IDMA + ); + break; + default: + return; + } + + /// + /// Step X. Program clock dividers for UARTs + /// Step Y. Enable Byte addressing for UARTs in legacy mode + /// + if ((Controller >=3D PchSerialIoIndexUart0 && Controller <=3D PchSerialI= oIndexUart2) && (DeviceMode !=3D PchSerialIoDisabled)) { + MmioWrite32 (mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_P= PR_CLK, + (B_SERIAL_IO_MEM_PPR_CLK_UPDATE | (V_SERIAL_IO_MEM_PPR_CLK_N_DIV << = 16) | + (V_SERIAL_IO_MEM_PPR_CLK_M_DIV << 1) | B_SERIAL_IO_MEM_PPR_CLK_EN ) + ); + + Data32And =3D (UINT32) (~(B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN = << (Controller - PchSerialIoIndexUart0))); + Data32Or =3D 0x0; + if (DeviceMode =3D=3D PchSerialIoHidden) { + Data32Or =3D (B_SERIAL_IO_PCR_GPPRVRW7_UART0_BYTE_ADDR_EN << (Contro= ller - PchSerialIoIndexUart0)); + } + PchPcrAndThenOr32 (PID_SERIALIO, R_SERIAL_IO_PCR_GPPRVRW7,Data32And,Da= ta32Or); + // + // Dummy read after setting any of GPPRVRW7. + // Required for UART 16550 8-bit Legacy mode to become active + // + MmioRead32 (mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_PP= R_CLK); + // + // Loop until Uart has successfuly moved to 8 bit mode + // + if (DeviceMode =3D=3D PchSerialIoHidden) { + Uart8BitLoop =3D 10; + while (Uart8BitLoop > 0) { + if (DetectAccessMode (mSerialIoAcpiAddress[Controller].Bar0) =3D= =3D AccessMode8bit) { + return; + } + Uart8BitLoop--; + } + } + } + + /// + /// Step Z. Program I2C SDA hold registers + /// + if (Controller >=3D PchSerialIoIndexI2C0 && Controller <=3D GetMaxI2cNum= ber ()) { + if (DeviceMode !=3D PchSerialIoDisabled) { + MmioOr32 (mSerialIoAcpiAddress[Controller].Bar0 + R_SERIAL_IO_MEM_I2= C_SDA_HOLD, V_SERIAL_IO_MEM_I2C_SDA_HOLD_VALUE); + } + } + +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSer= ialIoLib/PchSerialIoLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Libra= ry/PeiDxeSmmPchSerialIoLib/PchSerialIoLibCnl.c new file mode 100644 index 0000000000..28ccd626af --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoLi= b/PchSerialIoLibCnl.c @@ -0,0 +1,181 @@ +/** @file + PCH Serial IO Lib implementation Cannon Lake specific. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "PchSerialIoLibInternal.h" + +GLOBAL_REMOVE_IF_UNREFERENCED CHAR8 mCnlAcpiHid[PCH_MAX_SERIALIO_CONTROLLE= RS][SERIALIO_HID_LENGTH] =3D +{ + "INT34B2", + "INT34B3", + "INT34B4", + "INT34B5", + "INT34B6", + "INT34B7", + "INT34B0", + "INT34B1", + "INT34BC", + "INT34B8", + "INT34B9", + "INT34BA" +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mCnlPchLpSerialIoId [PCH_MAX_SERIALIO= _CONTROLLERS] =3D +{ + V_CNL_PCH_LP_SERIAL_IO_CFG_I2C0_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_I2C1_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_I2C2_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_I2C3_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_I2C4_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_I2C5_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_SPI0_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_SPI1_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_UART0_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_UART1_DEVICE_ID, + V_CNL_PCH_LP_SERIAL_IO_CFG_UART2_DEVICE_ID +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mCnlPchHSerialIoId [PCH_MAX_SERIALIO_= CONTROLLERS] =3D +{ + V_CNL_PCH_H_SERIAL_IO_CFG_I2C0_DEVICE_ID, + V_CNL_PCH_H_SERIAL_IO_CFG_I2C1_DEVICE_ID, + V_CNL_PCH_H_SERIAL_IO_CFG_I2C2_DEVICE_ID, + V_CNL_PCH_H_SERIAL_IO_CFG_I2C3_DEVICE_ID, + 0, + 0, + V_CNL_PCH_H_SERIAL_IO_CFG_SPI0_DEVICE_ID, + V_CNL_PCH_H_SERIAL_IO_CFG_SPI1_DEVICE_ID, + V_CNL_PCH_H_SERIAL_IO_CFG_UART0_DEVICE_ID, + V_CNL_PCH_H_SERIAL_IO_CFG_UART1_DEVICE_ID, + V_CNL_PCH_H_SERIAL_IO_CFG_UART2_DEVICE_ID +}; + +GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_BDF_NUMBERS mSerialIoBdf [PCH_MAX_= SERIALIO_CONTROLLERS] =3D +{ + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_I2C0}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_I2C1}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_I2C2}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_I2C3}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_I2C4}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_I2C5}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_SPI0}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_SPI1}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_UART0}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_UART1}, + {PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2, PCI_FUNCTION_NUMBER_PCH_SERIAL_I= O_UART2} +}; + + +/** + Returns index of the last i2c controller + + @param[in] Number Number of SerialIo controller + + @retval Index of I2C controller +**/ +PCH_SERIAL_IO_CONTROLLER +GetMaxI2cNumber ( + VOID + ) +{ + if (IsPchH ()) { + return PchSerialIoIndexI2C3; + } else { + return PchSerialIoIndexI2C5; + } +} + +/** + Checks if Device with given PciDeviceId is one of SerialIo controllers + If yes, its number is returned through Number parameter, otherwise Numbe= r is not updated + + @param[in] PciDevId Device ID + @param[out] Number Number of SerialIo controller + + @retval TRUE Yes it is a SerialIo controller + @retval FALSE No it isn't a SerialIo controller +**/ +BOOLEAN +IsSerialIoPciDevId ( + IN UINT16 PciDevId, + OUT PCH_SERIAL_IO_CONTROLLER *Number + ) +{ + PCH_SERIAL_IO_CONTROLLER Controller; + + for (Controller =3D 0; Controller < GetPchMaxSerialIoControllersNum (); = Controller++) { + if ((IsPchLp () && (PciDevId =3D=3D mCnlPchLpSerialIoId[Controller])) = || + (IsPchH () && (PciDevId =3D=3D mCnlPchHSerialIoId[Controller]))) + { + *Number =3D Controller; + return TRUE; + } + } + return FALSE; +} + +/** + Finds PCI Device Number of SerialIo devices. + + @param[in] SerialIoNumber Serial IO device + + @retval SerialIo device number +**/ +UINT8 +GetSerialIoDeviceNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ) +{ + return mSerialIoBdf[SerialIoNumber].DevNum; +} + +/** + Finds PCI Function Number of SerialIo devices. + + @param[in] SerialIoNumber Serial IO device + + @retval SerialIo funciton number +**/ +UINT8 +GetSerialIoFunctionNumber ( + IN PCH_SERIAL_IO_CONTROLLER SerialIoNumber + ) +{ + return mSerialIoBdf[SerialIoNumber].FuncNum; +} + +/** + Returns string with AcpiHid assigned to selected SerialIo controller + + @param[in] Number Number of SerialIo controller + + @retval pointer to 8-byte string +**/ +CHAR8* +GetSerialIoAcpiHid ( + IN PCH_SERIAL_IO_CONTROLLER Number + ) +{ + return mCnlAcpiHid[Number]; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSer= ialIoUartLib/PeiDxeSmmPchSerialIoUartLib.c b/Silicon/Intel/CoffeelakeSilico= nPkg/Pch/Library/PeiDxeSmmPchSerialIoUartLib/PeiDxeSmmPchSerialIoUartLib.c new file mode 100644 index 0000000000..621a473cfa --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchSerialIoUa= rtLib/PeiDxeSmmPchSerialIoUartLib.c @@ -0,0 +1,372 @@ +/** @file + PCH Serial IO UART Lib implementation. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_BAUD_RATE 115200 + +#define R_PCH_SERIAL_IO_8BIT_UART_RXBUF 0x00 +#define R_PCH_SERIAL_IO_8BIT_UART_TXBUF 0x00 +#define R_PCH_SERIAL_IO_8BIT_UART_BAUD_LOW 0x00 +#define R_PCH_SERIAL_IO_8BIT_UART_BAUD_HIGH 0x01 +#define R_PCH_SERIAL_IO_8BIT_UART_FCR 0x02 +#define R_PCH_SERIAL_IO_8BIT_UART_IIR 0x02 +#define R_PCH_SERIAL_IO_8BIT_UART_LCR 0x03 +#define R_PCH_SERIAL_IO_8BIT_UART_MCR 0x04 +#define R_PCH_SERIAL_IO_8BIT_UART_LSR 0x05 +#define R_PCH_SERIAL_IO_8BIT_UART_USR 0x1F +#define R_PCH_SERIAL_IO_32BIT_UART_CTR 0xFC //Component Type Registe= r contains identification code +#define UART_COMPONENT_IDENTIFICATION_CODE 0x44570110 + +#define B_PCH_SERIAL_IO_UART_IIR_FIFOSE BIT7|BIT6 +#define B_PCH_SERIAL_IO_UART_LSR_RXDA BIT0 +#define B_PCH_SERIAL_IO_UART_LSR_BI BIT4 +#define B_PCH_SERIAL_IO_UART_LSR_TXRDY BIT5 +#define B_PCH_SERIAL_IO_UART_LCR_DLAB BIT7 +#define B_PCH_SERIAL_IO_UART_FCR_FCR BIT0 +#define B_PCH_SERIAL_IO_UART_MCR_RTS BIT1 +#define B_PCH_SERIAL_IO_UART_MCR_AFCE BIT5 +#define B_PCH_SERIAL_IO_UART_USR_TFNF BIT1 + +/** + Returns UART's currently active access mode, 8 or 32 bit + + @param[in] MmioBase Base address of UART MMIO space + + @retval AccessMode8bit + @retval AccessMode32bit +**/ +UART_ACCESS_MODE +DetectAccessMode ( + IN UINTN MmioBase + ) +{ + if (MmioRead32 (MmioBase + R_PCH_SERIAL_IO_32BIT_UART_CTR) =3D=3D UART_C= OMPONENT_IDENTIFICATION_CODE) { + return AccessMode32bit; + } else { + return AccessMode8bit; + } +} + + +/** + Register access helper. Depending on SerialIO UART mode, + its registers are aligned to 1 or 4 bytes and have 8 or 32bit size + + @param[in] AccessMode Selects between 8bit access to 1-byte aligned= registers or 32bit access to 4-byte algined + @param[in] BaseAddress Base address of UART MMIO space + @param[in] Offset Register offset in 8bit mode + @param[in] Data Data to be written +**/ +STATIC +VOID +WriteRegister ( + IN UART_ACCESS_MODE AccessMode, + IN UINTN BaseAddress, + IN UINTN Offset, + IN UINT8 Data + ) +{ + if (AccessMode =3D=3D AccessMode32bit) { + MmioWrite32 (BaseAddress + 4*Offset, Data); + } else { + MmioWrite8 (BaseAddress + Offset, Data); + } +} + +/** + Register access helper. Depending on SerialIO UART mode, + its registers are aligned to 1 or 4 bytes and have 8 or 32bit size + + @param[in] AccessMode Selects between 8bit access to 1-byte aligned= registers or 32bit access to 4-byte algined + @param[in] BaseAddress Base address of UART MMIO space + @param[in] Offset Register offset in 8bit mode + @retval retrieved register value, always 8bit regardl= ess of access mode +**/ +STATIC +UINT8 +ReadRegister ( + IN UART_ACCESS_MODE AccessMode, + IN UINTN BaseAddress, + IN UINTN Offset + ) +{ + if (AccessMode =3D=3D AccessMode32bit) { + return (UINT8) (0xFF & MmioRead32 (BaseAddress + 4*Offset)); + } else { + return MmioRead8 (BaseAddress + Offset); + } +} + +/** + SerialIo UART in PCI mode will become unavailable when PCI enumerator + disables its memory space. This function re-enables it + + @param[in] UartNumber Selects Serial IO UART device (0-2) +**/ +STATIC +VOID +EnablePciMse ( + IN UINT8 UartNumber + ) +{ + UINTN CfgSpace; + + CfgSpace =3D FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 1); + if (MmioRead16 (CfgSpace + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) { + return; + } + if ((MmioRead16 (CfgSpace + PCI_COMMAND_OFFSET) & EFI_PCI_COMMAND_MEMORY= _SPACE) !=3D EFI_PCI_COMMAND_MEMORY_SPACE) { + if ((MmioRead32 (CfgSpace + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000) = !=3D 0x0 && + (MmioRead32 (CfgSpace + PCI_BASE_ADDRESSREG_OFFSET) & 0xFFFFF000) = !=3D 0xFFFFF000 ) { + MmioOr8 (CfgSpace + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE= ); + } + } +} + +/** + Initialize selected SerialIo UART. + This init function MUST be used prior any SerialIo UART functions to ini= t serial io controller if platform is going use serialio UART as debug outp= ut. + + @param UartNumber Selects Serial IO UART device (0-2) + @param FifoEnable When TRUE, enables 64-byte FIFOs. + @param BaudRate Baud rate. + @param LineControl Data length, parity, stop bits. + @param HardwareFlowControl Automated hardware flow control. If TRUE, h= ardware automatically checks CTS when sending data, and sets RTS when recei= ving data. +**/ +VOID +EFIAPI +PchSerialIoUartInit ( + UINT8 UartNumber, + BOOLEAN FifoEnable, + UINT32 BaudRate, + UINT8 LineControl, + BOOLEAN HardwareFlowControl + ) +{ + UINTN Base; + UINTN Divisor; + UART_ACCESS_MODE AccessMode; + + Base =3D FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0); + if ((Base & 0xFFFFFF00) =3D=3D 0x0 || (Base & 0xFFFFF000) =3D=3D 0xFFFFF= 000) { + // + // Base is not programmed, skip it. + // + return; + } + EnablePciMse (UartNumber); + AccessMode =3D DetectAccessMode (Base); + + Divisor =3D MAX_BAUD_RATE / BaudRate; + + // + // Configure baud rate + // + WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_LCR, B_PCH_SE= RIAL_IO_UART_LCR_DLAB); + WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_BAUD_HIGH, (U= INT8) (Divisor >> 8)); + WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_BAUD_LOW, (UI= NT8) (Divisor & 0xff)); + // + // Configure Line control and switch back to bank 0 + // + WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_LCR, LineCont= rol & 0x1F); + // + // Enable and reset FIFOs + // + WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_FCR, FifoEnab= le?B_PCH_SERIAL_IO_UART_FCR_FCR:0 ); + // + // Put Modem Control Register(MCR) into its reset state of 0x00. + // + WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_MCR, B_PCH_SE= RIAL_IO_UART_MCR_RTS | (HardwareFlowControl?B_PCH_SERIAL_IO_UART_MCR_AFCE:0= )); +} + +/** + Write data to serial device. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param UartNumber Selects Serial IO UART device (0-2) + @param Buffer Point of data buffer which need to be writed. + @param NumberOfBytes Number of output bytes which are cached in Buff= er. + + @retval Actual number of bytes writed to serial device. +**/ +UINTN +EFIAPI +PchSerialIoUartOut ( + IN UINT8 UartNumber, + IN UINT8 *Buffer, + IN UINTN NumberOfBytes + ) +{ + UINTN BytesLeft; + UINTN Base; + UART_ACCESS_MODE AccessMode; + + if (NULL =3D=3D Buffer) { + return 0; + } + + Base =3D FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0); + // + // Sanity checks to avoid infinite loop when trying to print through uni= nitialized UART + // + if ((Base & 0xFFFFFF00) =3D=3D 0x0 || (Base & 0xFFFFF000) =3D=3D 0xFFFFF= 000) { + return 0; + } + EnablePciMse (UartNumber); + AccessMode =3D DetectAccessMode (Base); + + if (ReadRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_USR) =3D= =3D 0xFF) { + return 0; + } + + BytesLeft =3D NumberOfBytes; + + while (BytesLeft !=3D 0) { + // + // Write data while there's room in TXFIFO. If HW Flow Control was ena= bled, it happens automatically on hardware level. + // + if (ReadRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_USR) & B= _PCH_SERIAL_IO_UART_USR_TFNF) { + WriteRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_TXBUF, *B= uffer); + Buffer++; + BytesLeft--; + } + } + + return NumberOfBytes; +} + +/* + Read data from serial device and save the datas in buffer. + + If the buffer is NULL, then return 0; + if NumberOfBytes is zero, then return 0. + + @param UartNumber Selects Serial IO UART device (0-2) + @param Buffer Point of data buffer which need to be write= d. + @param NumberOfBytes Number of output bytes which are cached in = Buffer. + @param WaitUntilBufferFull When TRUE, function waits until whole buffe= r is filled. When FALSE, function returns as soon as no new characters are = available. + + @retval Actual number of bytes raed to serial devic= e. + +**/ +UINTN +EFIAPI +PchSerialIoUartIn ( + IN UINT8 UartNumber, + OUT UINT8 *Buffer, + IN UINTN NumberOfBytes, + IN BOOLEAN WaitUntilBufferFull + ) +{ + UINTN BytesReceived; + UINTN Base; + UART_ACCESS_MODE AccessMode; + UINT8 Lsr; + UINT8 Byte; + + if (NULL =3D=3D Buffer) { + return 0; + } + + Base =3D FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0); + // + // Sanity checks to avoid infinite loop when trying to print through uni= nitialized UART + // + if ((Base & 0xFFFFFF00) =3D=3D 0x0 || (Base & 0xFFFFF000) =3D=3D 0xFFFFF= 000) { + return 0; + } + EnablePciMse (UartNumber); + AccessMode =3D DetectAccessMode (Base); + + BytesReceived =3D 0; + + while (BytesReceived !=3D NumberOfBytes) { + // + // Read the line status register + // + Lsr =3D ReadRegister(AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_LSR); + + // + // If there is data in the RX buffer, read it. + // + if ((Lsr & B_PCH_SERIAL_IO_UART_LSR_RXDA) !=3D 0) { + Byte =3D ReadRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_R= XBUF); + // + // Check if the break interrupt bit is set. If set, the byte read fr= om the + // RX buffer is invalid and should be ignored. If not set, copy the = byte into + // the receive buffer. + // + if ((Lsr & B_PCH_SERIAL_IO_UART_LSR_BI) =3D=3D 0) { + *Buffer =3D Byte; + Buffer++; + BytesReceived++; + } + } else { + if (!WaitUntilBufferFull) { + // + // If there's no data and function shouldn't wait, exit early + // + return BytesReceived; + } + } + } + return BytesReceived; +} + +/** + Polls a serial device to see if there is any data waiting to be read. + + Polls a serial device to see if there is any data waiting to be read. + If there is data waiting to be read from the serial device, then TRUE is= returned. + If there is no data waiting to be read from the serial device, then FALS= E is returned. + + @param UartNumber Selects Serial IO UART device (0-2) + + @retval TRUE Data is waiting to be read from the serial devi= ce. + @retval FALSE There is no data waiting to be read from the se= rial device. + +**/ +BOOLEAN +EFIAPI +PchSerialIoUartPoll ( + IN UINT8 UartNumber + ) +{ + UINTN Base; + UART_ACCESS_MODE AccessMode; + + Base =3D FindSerialIoBar (UartNumber + PchSerialIoIndexUart0, 0); + // + // Sanity checks to avoid infinite loop when trying to print through uni= nitialized UART + // + if ((Base & 0xFFFFFF00) =3D=3D 0x0 || (Base & 0xFFFFF000) =3D=3D 0xFFFFF= 000) { + return 0; + } + EnablePciMse (UartNumber); + AccessMode =3D DetectAccessMode (Base); + + // + // Read the serial port status + // + if ((ReadRegister (AccessMode, Base, R_PCH_SERIAL_IO_8BIT_UART_LSR) & B_= PCH_SERIAL_IO_UART_LSR_RXDA) !=3D 0) { + return TRUE; + } + return FALSE; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchWdt= CommonLib/WdtCommon.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiD= xeSmmPchWdtCommonLib/WdtCommon.c new file mode 100644 index 0000000000..679dcae0ab --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPchWdtCommonL= ib/WdtCommon.c @@ -0,0 +1,242 @@ +/** @file + Library that contains common parts of WdtPei and WdtDxe. Not a standalon= e module. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mAllowExpectedReset =3D 0; + +/** + Reads LPC bridge to get Watchdog Timer address + + + @retval UINT32 Watchdog's address +**/ +UINT32 +WdtGetAddress ( + VOID + ) +{ + return PmcGetAcpiBase () + R_ACPI_IO_OC_WDT_CTL; +} + +/** + Reloads WDT with new timeout value and starts it. Also sets Unexpected R= eset bit, which + causes the next reset to be treated as watchdog expiration - unless Allo= wKnownReset() + function was called too. + + @param[in] TimeoutValue Time in seconds before WDT times out. Su= pported range =3D 1 - 1024. + + @retval EFI_SUCCESS if everything's OK + @retval EFI_INVALID_PARAMETER if TimeoutValue parameter is wrong +**/ +EFI_STATUS +EFIAPI +WdtReloadAndStart ( + IN UINT32 TimeoutValue + ) +{ + UINT32 Readback; + + DEBUG ((DEBUG_INFO, "\n(Wdt) ReloadAndStartTimer(%d)\n", TimeoutValue)); + + if ((TimeoutValue > B_ACPI_IO_OC_WDT_CTL_TOV_MASK) || (TimeoutValue =3D= =3D 0)) { + return EFI_INVALID_PARAMETER; + } + + Readback =3D IoRead32 (WdtGetAddress ()); + Readback |=3D (B_ACPI_IO_OC_WDT_CTL_EN | B_ACPI_IO_OC_WDT_CTL_FORCE_ALL = | B_ACPI_IO_OC_WDT_CTL_ICCSURV); + if (mAllowExpectedReset =3D=3D 0) { + Readback |=3D B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS; + } + + if (PcdGetBool (PcdOcEnableWdtforDebug) =3D=3D FALSE) { + /// + /// WDT will not be turned on. This is to prevent platform reboots tri= ggered + /// by WDT expiration, which can be expected when processor is halted = for debugging + /// + Readback &=3D ~(B_ACPI_IO_OC_WDT_CTL_EN | B_ACPI_IO_OC_WDT_CTL_FORCE_A= LL | B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS); + DEBUG ((DEBUG_INFO, "(Wdt) Wdt disabled in Debug BIOS\n")); + } + + Readback &=3D ~(B_ACPI_IO_OC_WDT_CTL_TOV_MASK); + Readback |=3D ((TimeoutValue - 1) & B_ACPI_IO_OC_WDT_CTL_TOV_MASK); + IoWrite32 (WdtGetAddress (), Readback); + Readback |=3D B_ACPI_IO_OC_WDT_CTL_RLD; + IoWrite32 (WdtGetAddress (), Readback); + return EFI_SUCCESS; +} + +/** + Disables WDT timer. + + +**/ +VOID +EFIAPI +WdtDisable ( + VOID + ) +{ + UINT32 Readback; + + DEBUG ((DEBUG_INFO, "(Wdt) DisableTimer\n")); + + Readback =3D IoRead32 (WdtGetAddress ()); + Readback &=3D ~(B_ACPI_IO_OC_WDT_CTL_EN | B_ACPI_IO_OC_WDT_CTL_FORCE_ALL= | B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS); + IoWrite32 (WdtGetAddress (), Readback); +} + +/** + Returns WDT failure status. + + + @retval V_ACPI_IO_OC_WDT_CTL_STATUS_FAILURE If there was WDT expiratio= n or unexpected reset + @retval V_ACPI_IO_OC_WDT_CTL_STATUS_OK Otherwise +**/ +UINT8 +EFIAPI +WdtCheckStatus ( + VOID + ) +{ + UINT32 Readback; + + DEBUG ((DEBUG_INFO, "(Wdt) CheckTimerStatus\n")); + + Readback =3D IoRead32 (WdtGetAddress ()); + + DEBUG ((DEBUG_INFO, "(Wdt) Readback =3D (%x)\n", Readback)); + + if (Readback & B_ACPI_IO_OC_WDT_CTL_FAILURE_STS) { + DEBUG ((DEBUG_INFO, "(Wdt) Status =3D FAILURE\n")); + return V_ACPI_IO_OC_WDT_CTL_STATUS_FAILURE; + } else { + return V_ACPI_IO_OC_WDT_CTL_STATUS_OK; + } +} + +/** + Normally, each reboot performed while watchdog runs is considered a fail= ure. + This function allows platform to perform expected reboots with WDT runni= ng, + without being interpreted as failures. + In DXE phase, it is enough to call this function any time before reset. + In PEI phase, between calling this function and performing reset, Reload= AndStart() + must not be called. + + +**/ +VOID +EFIAPI +WdtAllowKnownReset ( + VOID + ) +{ + UINT32 Readback; + + DEBUG ((DEBUG_INFO, "(Wdt) AllowKnownReset\n")); + + mAllowExpectedReset =3D 1; + + Readback =3D IoRead32 (WdtGetAddress ()); + Readback &=3D ~(B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS | B_ACPI_IO_OC_WDT_C= TL_FORCE_ALL); + IoWrite32 (WdtGetAddress (), Readback); +} + +/** + Returns information if WDT coverage for the duration of BIOS execution + was requested by an OS application + + + @retval TRUE if WDT was requested + @retval FALSE if WDT was not requested +**/ +UINT8 +EFIAPI +IsWdtRequired ( + VOID + ) +{ + UINT32 Readback; + + DEBUG ((DEBUG_INFO, "(Wdt) IsWdtRequired")); + + Readback =3D IoRead32 (WdtGetAddress ()); + + + if ((Readback & B_ACPI_IO_OC_WDT_CTL_AFTER_POST) !=3D 0) { + DEBUG ((DEBUG_INFO, " - yes\n")); + return TRUE; + } else { + DEBUG ((DEBUG_INFO, " - no\n")); + return FALSE; + } + +} + +/** + Returns WDT enabled/disabled status. + + + @retval TRUE if WDT is enabled + @retval FALSE if WDT is disabled +**/ +UINT8 +EFIAPI +IsWdtEnabled ( + VOID + ) +{ + UINT32 Readback; + + DEBUG ((DEBUG_INFO, "(Wdt) IsWdtEnabled")); + + Readback =3D IoRead32 (WdtGetAddress ()); + + + if ((Readback & B_ACPI_IO_OC_WDT_CTL_EN) !=3D 0) { + DEBUG ((DEBUG_INFO, " - yes\n")); + return TRUE; + } else { + DEBUG ((DEBUG_INFO, " - no\n")); + return FALSE; + } + +} + +/** + Returns WDT locked status. + + + @retval TRUE if WDT is locked + @retval FALSE if WDT is unlocked +**/ +UINT8 +EFIAPI +IsWdtLocked ( + VOID + ) +{ + UINT32 Readback; + + DEBUG ((DEBUG_INFO, "(Wdt) IsWdtLocked")); + + Readback =3D IoRead32 (WdtGetAddress ()); + + + if ((Readback & B_ACPI_IO_OC_WDT_CTL_LCK) !=3D 0) { + DEBUG ((DEBUG_INFO, " - yes\n")); + return TRUE; + } else { + DEBUG ((DEBUG_INFO, " - no\n")); + return FALSE; + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib= /PmcLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/= PmcLib.c new file mode 100644 index 0000000000..8e026b3ab6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmPmcLib/PmcLib= .c @@ -0,0 +1,330 @@ +/** @file + PCH PMC Library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Get PCH ACPI base address. + + @retval Address Address of PWRM base address. +**/ +UINT16 +PmcGetAcpiBase ( + VOID + ) +{ + return PcdGet16 (PcdAcpiBaseAddress); +} + +/** + Get PCH PWRM base address. + + @retval Address Address of PWRM base address. +**/ +UINT32 +PmcGetPwrmBase ( + VOID + ) +{ + return PCH_PWRM_BASE_ADDRESS; +} + +/** + This function enables Power Button SMI +**/ +VOID +PmcEnablePowerButtonSmi ( + VOID + ) +{ + IoOr16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN); +} + +/** + This function disables Power Button SMI +**/ +VOID +PmcDisablePowerButtonSmi ( + VOID + ) +{ + IoAnd16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_EN, (UINT16)~B_ACPI_IO_PM1_EN= _PWRBTN); +} + +/** + This function reads PM Timer Count driven by 3.579545 MHz clock + + @retval PM Timer Count +**/ +UINT32 +PmcGetTimerCount ( + VOID + ) +{ + return IoRead32 (PmcGetAcpiBase () + R_ACPI_IO_PM1_TMR) & B_ACPI_IO_PM1_= TMR_VAL; +} + +/** + Get Sleep Type that platform has waken from + + @retval SleepType Sleep Type +**/ +PMC_SLEEP_STATE +PmcGetSleepTypeAfterWake ( + VOID + ) +{ + UINT16 AcpiBase; + UINT32 PmconA; + + AcpiBase =3D PmcGetAcpiBase (); + PmconA =3D MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A); + + DEBUG ((DEBUG_INFO, "PWRM_PMCON_A =3D 0x%x\n", PmconA)); + + // + // If Global Reset Status, Power Failure. Host Reset Status bits are set= , return S5 State + // + if ((PmconA & (B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS | B_PMC_PWRM_GEN_PMCON= _A_PWR_FLR | B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS)) !=3D 0) { + return PmcNotASleepState; + } + + if (IoRead16 (AcpiBase + R_ACPI_IO_PM1_STS) & B_ACPI_IO_PM1_STS_WAK) { + switch (IoRead16 (AcpiBase + R_ACPI_IO_PM1_CNT) & B_ACPI_IO_PM1_CNT_SL= P_TYP) { + case V_ACPI_IO_PM1_CNT_S0: + return PmcInS0State; + + case V_ACPI_IO_PM1_CNT_S1: + return PmcS1SleepState; + + case V_ACPI_IO_PM1_CNT_S3: + return PmcS3SleepState; + + case V_ACPI_IO_PM1_CNT_S4: + return PmcS4SleepState; + + case V_ACPI_IO_PM1_CNT_S5: + return PmcS5SleepState; + + default: + ASSERT (FALSE); + return PmcUndefinedState; + } + } else { + return PmcNotASleepState; + } +} + +/** + Clear PMC Wake Status +**/ +VOID +PmcClearWakeStatus ( + VOID + ) +{ + IoWrite16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_WAK); +} + +/** + Check if platform boots after shutdown caused by power button override e= vent + + @retval TRUE Power Button Override occurred in last system boot + @retval FALSE Power Button Override didn't occur +**/ +BOOLEAN +PmcIsPowerButtonOverrideDetected ( + VOID + ) +{ + return ((IoRead16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_STS) & B_ACPI_IO_PM= 1_STS_PRBTNOR) !=3D 0); +} + +/** + This function checks if RTC Power Failure occurred by + reading RTC_PWR_FLR bit + + @retval RTC Power Failure state: TRUE - Battery is always present. + FALSE - CMOS is cleared. +**/ +BOOLEAN +PmcIsRtcBatteryGood ( + VOID + ) +{ + return ((MmioRead8 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_= PWRM_GEN_PMCON_B_RTC_PWR_STS) =3D=3D 0); +} + +/** + This function checks if Power Failure occurred by + reading PWR_FLR bit + + @retval Power Failure state +**/ +BOOLEAN +PmcIsPowerFailureDetected ( + VOID + ) +{ + return ((MmioRead16 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A) & B_PMC= _PWRM_GEN_PMCON_A_PWR_FLR) !=3D 0); +} + +/** + This function checks if RTC Power Failure occurred by + reading SUS_PWR_FLR bit + + @retval SUS Power Failure state +**/ +BOOLEAN +PmcIsSusPowerFailureDetected ( + VOID + ) +{ + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) & B_PMC= _PWRM_GEN_PMCON_A_SUS_PWR_FLR) !=3D 0); +} + +/** + This function clears Power Failure status (PWR_FLR) +**/ +VOID +PmcClearPowerFailureStatus ( + VOID + ) +{ + // + // Write 1 to clear PWR_FLR + // Avoid clearing other W1C bits + // + MmioAndThenOr8 ( + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1, + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS >> 8), + B_PMC_PWRM_GEN_PMCON_A_PWR_FLR >> 8 + ); +} + +/** + This function clears Global Reset status (GBL_RST_STS) +**/ +VOID +PmcClearGlobalResetStatus ( + VOID + ) +{ + // + // Write 1 to clear GBL_RST_STS + // Avoid clearing other W1C bits + // + MmioAndThenOr8 ( + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 3, + (UINT8) ~0, + B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS >> 24 + ); +} + +/** + This function clears Host Reset status (HOST_RST_STS) +**/ +VOID +PmcClearHostResetStatus ( + VOID + ) +{ + // + // Write 1 to clear HOST_RST_STS + // Avoid clearing other W1C bits + // + MmioAndThenOr8 ( + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1, + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_PWR_FLR >> 8), + B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS >> 8 + ); +} + +/** + This function clears SUS Power Failure status (SUS_PWR_FLR) +**/ +VOID +PmcClearSusPowerFailureStatus ( + VOID + ) +{ + // + // BIOS clears this bit by writing a '1' to it. + // Take care of other fields, so we don't clear them accidentally. + // + MmioAndThenOr8 ( + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 2, + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_MS4V >> 16), + B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR >> 16 + ); +} + +/** + This function sets state to which platform will get after power is reapp= lied + + @param[in] PowerStateAfterG3 0: S0 state (boot) + 1: S5/S4 State +**/ +VOID +PmcSetPlatformStateAfterPowerFailure ( + IN UINT8 PowerStateAfterG3 + ) +{ + UINT32 PchPwrmBase; + + PchPwrmBase =3D PmcGetPwrmBase (); + + if (PowerStateAfterG3) { + MmioOr8 (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, B_PMC_PWRM_GEN_PMCON_A_= AFTERG3_EN); + } else { + MmioAnd8 (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, (UINT8)~B_PMC_PWRM_GEN= _PMCON_A_AFTERG3_EN); + } +} + +/** + This function checks if SMI Lock is set + + @retval SMI Lock state +**/ +BOOLEAN +PmcIsSmiLockSet ( + VOID + ) +{ + return ((MmioRead8 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B)= ) & B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK) !=3D 0); +} + +/** + Check global SMI enable is set + + @retval TRUE Global SMI enable is set + FALSE Global SMI enable is not set +**/ +BOOLEAN +PmcIsGblSmiEn ( + VOID + ) +{ + return !!(IoRead32 (PmcGetAcpiBase () + R_ACPI_IO_SMI_EN) & B_ACPI_IO_SM= I_EN_GBL_SMI); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLi= b/SataLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataL= ib/SataLib.c new file mode 100644 index 0000000000..05557931c2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLib/SataL= ib.c @@ -0,0 +1,41 @@ +/** @file + Pch SATA library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +/** + Get SATA controller address that can be passed to the PCI Segment Librar= y functions. + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA controller address in PCI Segment Library representation +**/ +UINT64 +GetSataRegBase ( + IN UINT32 SataCtrlIndex + ) +{ + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + return PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + GetSataPcieDeviceNum (SataCtrlIndex), + GetSataPcieFunctionNum (SataCtrlIndex), + 0 + ); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLi= b/SataLibCdf.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSa= taLib/SataLibCdf.c new file mode 100644 index 0000000000..5cec818dd6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLib/SataL= ibCdf.c @@ -0,0 +1,101 @@ +/** @file + Pch SATA library for CedarFork SouthCluster. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +/** + Get Maximum Sata Controller Number + + @param[in] None + + @retval Maximum Sata Controller Number +**/ +UINT8 +GetPchMaxSataControllerNum ( + VOID + ) +{ + return 3; +} + +/** + Get Pch Maximum Sata Port Number + + @param[in] SataCtrlIndex SATA controller index + + @retval Pch Maximum Sata Port Number +**/ +UINT8 +GetPchMaxSataPortNum ( + IN UINT8 SataCtrlIndex + ) +{ + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + return 8; +} + +/** + Get SATA controller PCIe Device Number + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA controller PCIe Device Number +**/ +UINT8 +GetSataPcieDeviceNum ( + IN UINT8 SataCtrlIndex + ) +{ + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + if (SataCtrlIndex =3D=3D SATA_1_CONTROLLER_INDEX) { + return PCI_DEVICE_NUMBER_CDF_PCH_SATA_1; + } else if (SataCtrlIndex =3D=3D SATA_2_CONTROLLER_INDEX) { + return PCI_DEVICE_NUMBER_CDF_PCH_SATA_2; + } else if (SataCtrlIndex =3D=3D SATA_3_CONTROLLER_INDEX) { + return PCI_DEVICE_NUMBER_CDF_PCH_SATA_3; + } else { + ASSERT (FALSE); + return 0; + } +} + +/** + Get SATA controller PCIe Function Number + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA controller PCIe Function Number +**/ +UINT8 +GetSataPcieFunctionNum ( + IN UINT8 SataCtrlIndex + ) +{ + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + if (SataCtrlIndex =3D=3D SATA_1_CONTROLLER_INDEX) { + return PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1; + } else if (SataCtrlIndex =3D=3D SATA_2_CONTROLLER_INDEX) { + return PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2; + } else if (SataCtrlIndex =3D=3D SATA_3_CONTROLLER_INDEX) { + return PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3; + } else { + ASSERT (FALSE); + return 0; + } +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLi= b/SataLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSa= taLib/SataLibCnl.c new file mode 100644 index 0000000000..0eca692a74 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiDxeSmmSataLib/SataL= ibCnl.c @@ -0,0 +1,88 @@ +/** @file + Pch SATA library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Get Maximum Sata Controller Number + + @param[in] None + + @retval Maximum Sata Controller Number +**/ +UINT8 +GetPchMaxSataControllerNum ( + VOID + ) +{ + return 1; +} + +/** + Get Pch Maximum Sata Port Number + + @param[in] SataCtrlIndex SATA controller index + + @retval Pch Maximum Sata Port Number +**/ +UINT8 +GetPchMaxSataPortNum ( + IN UINT32 SataCtrlIndex + ) +{ + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + if (IsPchLp ()) { + return 3; + } else { + return 8; + } +} + +/** + Get SATA controller PCIe Device Number + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA controller PCIe Device Number +**/ +UINT8 +GetSataPcieDeviceNum ( + IN UINT32 SataCtrlIndex + ) +{ + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + return PCI_DEVICE_NUMBER_PCH_SATA; +} + +/** + Get SATA controller PCIe Function Number + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA controller PCIe Function Number +**/ +UINT8 +GetSataPcieFunctionNum ( + IN UINT32 SataCtrlIndex + ) +{ + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + return PCI_FUNCTION_NUMBER_PCH_SATA; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLib/Pei= OcWdtLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLib/Pei= OcWdtLib.c new file mode 100644 index 0000000000..22f6fb215f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLib/PeiOcWdtLi= b.c @@ -0,0 +1,130 @@ +/** @file + The PEI Library Implements OcWdt Support. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +static WDT_PPI mWdtPpi =3D { + WdtReloadAndStart, + WdtCheckStatus, + WdtDisable, + WdtAllowKnownReset, + IsWdtRequired, + IsWdtEnabled +}; + +static EFI_PEI_PPI_DESCRIPTOR mInstallWdtPpi =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gWdtPpiGuid, + &mWdtPpi +}; + +/** + Reads PCH registers to check if platform wakes from S3/S4 + + @retval TRUE if platfrom wakes from S3/S4 + @retval FALSE otherwise +**/ +BOOLEAN +IsWakeFromS3S4 ( + VOID + ) +{ + PMC_SLEEP_STATE SleepType; + + SleepType =3D PmcGetSleepTypeAfterWake (); + if ((SleepType =3D=3D PmcS3SleepState) || (SleepType =3D=3D PmcS4SleepSt= ate)) { + return TRUE; + } + + return FALSE; + +} + +/** + Check for unexpected reset. + If there was an unexpected reset, enforces WDT expiration. +**/ +VOID +OcWdtResetCheck ( + VOID + ) +{ + UINT32 Readback; + + Readback =3D IoRead32 (WdtGetAddress ()); + DEBUG ((DEBUG_INFO, "(WDT) OcWdtResetCheck()\n")); + + /// + /// If there was a WDT expiration, set Failure Status and clear timeout = status bits + /// Timeout status bits are cleared by writing '1' + /// + if (Readback & (B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS | B_ACPI_IO_OC_WDT_CTL_= NO_ICCSURV_STS)) { + DEBUG ((DEBUG_ERROR, "(WDT) Expiration detected.\n", Readback)); + Readback |=3D B_ACPI_IO_OC_WDT_CTL_FAILURE_STS; + Readback |=3D (B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS | B_ACPI_IO_OC_WDT_CTL= _NO_ICCSURV_STS); + Readback &=3D ~(B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS); + } else { + /// + /// If there was unexpected reset but no WDT expiration and no resume = from S3/S4, + /// clear unexpected reset status and enforce expiration. This is to i= nform Firmware + /// which has no access to unexpected reset status bit, that something= went wrong. + /// + if ((Readback & B_ACPI_IO_OC_WDT_CTL_UNXP_RESET_STS) && !IsWakeFromS3S= 4()) { + if (PcdGetBool (PcdOcEnableWdtforDebug)) { + DEBUG ((DEBUG_ERROR, "(WDT) Unexpected reset detected and ignored.= \n")); + Readback &=3D ~(B_ACPI_IO_OC_WDT_CTL_FAILURE_STS | B_ACPI_IO_OC_WD= T_CTL_UNXP_RESET_STS); + Readback |=3D (B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS | B_ACPI_IO_OC_WDT= _CTL_NO_ICCSURV_STS); + } else { + DEBUG ((DEBUG_ERROR, "(WDT) Unexpected reset detected. Enforcing W= dt expiration.\n")); + WdtReloadAndStart (1); + /// + /// wait for reboot caused by WDT expiration + /// + CpuDeadLoop (); + } + } else { + /// + /// No WDT expiration and no unexpected reset - clear Failure status + /// + DEBUG ((DEBUG_INFO, "(WDT) Status OK.\n", Readback)); + Readback &=3D ~(B_ACPI_IO_OC_WDT_CTL_FAILURE_STS); + Readback |=3D (B_ACPI_IO_OC_WDT_CTL_ICCSURV_STS | B_ACPI_IO_OC_WDT_C= TL_NO_ICCSURV_STS); + } + } + + IoWrite32 (WdtGetAddress (), Readback); + + return; +} + +/** + This function install WDT PPI + + @retval EFI_STATUS Results of the installation of the WDT PPI +**/ +EFI_STATUS +EFIAPI +OcWdtInit ( + VOID + ) +{ + EFI_STATUS Status; + + Status =3D PeiServicesInstallPpi (&mInstallWdtPpi); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLibNull= /PeiOcWdtLibNull.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWd= tLibNull/PeiOcWdtLibNull.c new file mode 100644 index 0000000000..182218ffcf --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiOcWdtLibNull/PeiOcW= dtLibNull.c @@ -0,0 +1,23 @@ +/** @file + The Null PEI Library Implements OcWdt Support. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + This function install WDT PPI + + @retval EFI_STATUS Results of the installation of the WDT PPI +**/ +EFI_STATUS +EFIAPI +OcWdtInit ( + VOID + ) +{ + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib= /PchPreMemPrintPolicy.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pe= iPchPolicyLib/PchPreMemPrintPolicy.c new file mode 100644 index 0000000000..bd1e2711da --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPre= MemPrintPolicy.c @@ -0,0 +1,307 @@ +/** @file + Print whole PCH_PREMEM_POLICY_PPI + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyLibrary.h" + +/** + Print PCH_GENERAL_PREMEM_CONFIG and serial out. + + @param[in] PchGeneralPreMemConfig Pointer to a PCH_GENERAL_PREMEM_CO= NFIG that provides the platform setting + +**/ +VOID +PchPrintGeneralPreMemConfig ( + IN CONST PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH General PreMem Config ------= ------------\n")); + DEBUG ((DEBUG_INFO, " Port80Route=3D %x\n", PchGeneralPreMemConfig->Port= 80Route)); +} + +/** + Print PCH_DCI_PREMEM_CONFIG and serial out. + + @param[in] DciPreMemConfig Pointer to a PCH_DCI_PREMEM_CONFIG= that provides the platform setting + +**/ +VOID +PchPrintDciPreMemConfig ( + IN CONST PCH_DCI_PREMEM_CONFIG *DciPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH DCI PreMem Config ----------= --------\n")); + DEBUG ((DEBUG_INFO, "PlatformDebugConsent =3D %x\n", DciPreMemConfig->Pl= atformDebugConsent)); + DEBUG ((DEBUG_INFO, "DciUsb3TypecUfpDbg =3D %x\n", DciPreMemConfig->DciU= sb3TypecUfpDbg)); +} + +/** + Print PCH_WDT_PREMEM_CONFIG and serial out. + + @param[in] WdtPreMemConfig Pointer to a PCH_WDT_PREMEM_CONFIG= that provides the platform setting + +**/ +VOID +PchPrintWdtPreMemConfig ( + IN CONST PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH WDT PreMem Config ----------= --------\n")); + DEBUG ((DEBUG_INFO, "DisableAndLock=3D %x\n", WdtPreMemConfig->DisableAn= dLock)); +} + +/** + Print PCH_TRACE_HUB_CONFIG and serial out. + + @param[in] TraceHubConfig Pointer to a PCH_TRACE_HUB_CONFIG = that provides the platform setting + +**/ +VOID +PchPrintTraceHubPreMemConfig ( + IN CONST PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH TraceHub PreMem Config -----= -------------\n")); + DEBUG ((DEBUG_INFO, "EnableMode=3D %x\n", PchTraceHubPreMemConfig->Enabl= eMode)); + DEBUG ((DEBUG_INFO, "MemReg0Size=3D %x\n", PchTraceHubPreMemConfig->MemR= eg0Size)); + DEBUG ((DEBUG_INFO, "MemReg1Size=3D %x\n", PchTraceHubPreMemConfig->MemR= eg1Size)); +} + +/** + Print PCH_SMBUS_CONFIG and serial out. + + @param[in] SmbusConfig Pointer to a PCH_SMBUS_CONFIG that provid= es the platform setting + +**/ +VOID +PchPrintSmbusPreMemConfig ( + IN CONST PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ PCH SMBUS PreMem Config --------= ----------\n")); + DEBUG ((DEBUG_INFO, " Enable=3D %x\n", SmbusPreMemConfig->Enable)); + DEBUG ((DEBUG_INFO, " ArpEnable=3D %x\n", SmbusPreMemConfig->ArpEnable)); + DEBUG ((DEBUG_INFO, " DynamicPowerGating=3D %x\n", SmbusPreMemConfig->Dy= namicPowerGating)); + DEBUG ((DEBUG_INFO, " SpdWriteDisable=3D %x\n", SmbusPreMemConfig->SpdWr= iteDisable)); + DEBUG ((DEBUG_INFO, " SmbAlertEnable=3D %x\n", SmbusPreMemConfig->SmbAle= rtEnable)); + DEBUG ((DEBUG_INFO, " SmbusIoBase=3D %x\n", SmbusPreMemConfig->SmbusIoBa= se)); + DEBUG ((DEBUG_INFO, " NumRsvdSmbusAddresses=3D %x\n", SmbusPreMemConfig-= >NumRsvdSmbusAddresses)); + DEBUG ((DEBUG_INFO, " RsvdSmbusAddressTable=3D {")); + for (Index =3D 0; Index < SmbusPreMemConfig->NumRsvdSmbusAddresses; ++In= dex) { + DEBUG ((DEBUG_INFO, " %02xh", SmbusPreMemConfig->RsvdSmbusAddressTable= [Index])); + } + DEBUG ((DEBUG_INFO, " }\n")); +} + +/** + Print PCH_LPC_PREMEM_CONFIG and serial out. + + @param[in] LpcPreMemConfig Pointer to a PCH_LPC_PREMEM_= CONFIG that provides the platform setting + +**/ +VOID +PchPrintLpcPreMemConfig ( + IN CONST PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LPC PreMem Config ----------= --------\n")); + DEBUG ((DEBUG_INFO, "EnhancePort8xhDecoding=3D %x\n", LpcPreMemConfig->E= nhancePort8xhDecoding)); +} + +/** + Print PCH_HSIO_PCIE_PREMEM_CONFIG and serial out. + + @param[in] HsioPciePreMemConfig Pointer to a PCH_HSIO_PCIE_PREMEM_CO= NFIG that provides the platform setting + +**/ +VOID +PchPrintHsioPciePreMemConfig ( + IN CONST PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ HSIO PCIE PreMem Config --------= ----------\n")); + for (Index =3D 0; Index < GetPchMaxPciePortNum (); Index++) { + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtleEnable=3D %x\n", Index= , HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioRxSetCtle=3D %x\n", Index, Hsio= PciePreMemConfig->Lane[Index].HsioRxSetCtle)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmpEnable=3D %x\= n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DownscaleAmp=3D %x\n", In= dex, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmpEnable=3D %x\= n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DownscaleAmp=3D %x\n", In= dex, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmpEnable=3D %x\= n", Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen3DownscaleAmp=3D %x\n", In= dex, HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmphEnable=3D %x\n", In= dex, HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen1DeEmph=3D %x\n", Index, H= sioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5Enable=3D %x\n",= Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph3p5=3D %x\n", Index= , HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0Enable=3D %x\n",= Index, HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] HsioTxGen2DeEmph6p0=3D %x\n", Index= , HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0)); + } +} + +/** + Print PCH_HSIO_SATA_PREMEM_CONFIG and serial out. + + @param[in] SataCtrlIndex SATA controller index + @param[in] HsioSataPreMemConfig Pointer to a PCH_HSIO_SATA_PREMEM_CO= NFIG that provides the platform setting +**/ +VOID +PchPrintHsioSataPreMemConfig ( + IN UINT8 SataCtrlIndex, + IN CONST PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "---------------- HSIO SATA PreMem Config for contro= ller %d ----------------\n", SataCtrlIndex)); + for (Index =3D 0; Index < GetPchMaxSataPortNum (SataCtrlIndex); Index++)= { + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMagEnable=3D %= x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnab= le)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen1EqBoostMag=3D %x\n", = Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMagEnable=3D %= x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnab= le)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen2EqBoostMag=3D %x\n", = Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMagEnable=3D %= x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnab= le)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioRxGen3EqBoostMag=3D %x\n", = Index, HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmpEnable=3D= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp= Enable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DownscaleAmp=3D %x\n"= , Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmpEnable=3D= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp= Enable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DownscaleAmp=3D %x\n"= , Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmpEnable=3D= %x\n", Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp= Enable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DownscaleAmp=3D %x\n"= , Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmphEnable=3D %x\n"= , Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen1DeEmph=3D %x\n", Inde= x, HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmphEnable=3D %x\n"= , Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen2DeEmph=3D %x\n", Inde= x, HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmphEnable=3D %x\n"= , Index, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HsioTxGen3DeEmph=3D %x\n", Inde= x, HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph)); + } +} + +/** + Print PCH_PCIE_RP_PREMEM_CONFIG and serial out. + + @param[in] PcieRpPreMemConfig Pointer to a PCH_PCIE_RP_PREMEM_CON= FIG that provides the platform setting + +**/ +VOID +PchPrintPcieRpPreMemConfig ( + IN CONST PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig + ) +{ + UINT32 Index; + DEBUG ((DEBUG_INFO, "------------------ PCH PCIe RP PreMem Config ------= ------------\n")); + + for (Index =3D 0; Index < GetPchMaxPciePortNum (); Index++) { + DEBUG ((DEBUG_INFO, " Port[%d] RpEnabled=3D %x\n", Index, (PcieRpPreMe= mConfig->RpEnabledMask & (UINT32) (1 << Index)) !=3D 0 )); + } + DEBUG ((DEBUG_INFO, " PcieImrEnabled=3D %x\n", PcieRpPreMemConfig->PcieI= mrEnabled)); + DEBUG ((DEBUG_INFO, " PcieImrSize=3D %d MB\n", PcieRpPreMemConfig->PcieI= mrSize)); + DEBUG ((DEBUG_INFO, " ImrRpSelection=3D %d\n", PcieRpPreMemConfig->ImrRp= Selection)); +} + +/** + Print PCH_HDAUDIO_PREMEM_CONFIG and serial out. + + @param[in] LpcPreMemConfig Pointer to a PCH_HDAUDIO_PRE= MEM_CONFIG that provides the platform setting + +**/ +VOID +PchPrintHdAudioPreMemConfig ( + IN CONST PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ HD Audio PreMem Config ---------= ---------\n")); + DEBUG ((DEBUG_INFO, " Enable=3D %x\n", HdaPreMemConfig->Enable)); +} + +/** + Print PCH_ISH_PREMEM_CONFIG and serial out. + + @param[in] IshPreMemConfig Pointer to a PCH_ISH_PREMEM_= CONFIG that provides the platform setting + +**/ +VOID +PchPrintIshPreMemConfig ( + IN CONST PCH_ISH_PREMEM_CONFIG *IshPreMemConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ ISH PreMem Config --------------= ----\n")); + DEBUG ((DEBUG_INFO, " Enable=3D %x\n", IshPreMemConfig->Enable)); +} + + +/** + Print whole PCH_POLICY_PPI and serial out. + + @param[in] SiPreMemPolicyPpi The RC PREMEM Policy PPI instance + +**/ +VOID +EFIAPI +PchPreMemPrintPolicyPpi ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + DEBUG_CODE_BEGIN (); + EFI_STATUS Status; + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; + PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig; + PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig; + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; + PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; + PCH_ISH_PREMEM_CONFIG *IshPreMemConfig; + UINT8 SataCtrlIndex; + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMe= mConfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gDciPreMemConfig= Guid, (VOID *) &DciPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gWatchDogPreMemC= onfigGuid, (VOID *) &WdtPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchTraceHubPreM= emConfigGuid, (VOID *) &PchTraceHubPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSmbusPreMemConf= igGuid, (VOID *) &SmbusPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gLpcPreMemConfig= Guid, (VOID *) &LpcPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHsioPciePreMemC= onfigGuid, (VOID *) &HsioPciePreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPcieRpPreMemCon= figGuid, (VOID *) &PcieRpPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gHdAudioPreMemCo= nfigGuid, (VOID *) &HdaPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gIshPreMemConfig= Guid, (VOID *) &IshPreMemConfig); + ASSERT_EFI_ERROR (Status); + DEBUG ((DEBUG_INFO, "------------------------ PCH Print PreMemPolicy Sta= rt ------------------------\n")); + DEBUG ((DEBUG_INFO, " Revision=3D %x\n", SiPreMemPolicyPpi->TableHeader.= Header.Revision)); + + PchPrintGeneralPreMemConfig (PchGeneralPreMemConfig); + PchPrintDciPreMemConfig (DciPreMemConfig); + PchPrintWdtPreMemConfig (WdtPreMemConfig); + PchPrintTraceHubPreMemConfig (PchTraceHubPreMemConfig); + PchPrintSmbusPreMemConfig (SmbusPreMemConfig); + PchPrintLpcPreMemConfig (LpcPreMemConfig); + PchPrintHsioPciePreMemConfig (HsioPciePreMemConfig); + for (SataCtrlIndex =3D 0; SataCtrlIndex < GetPchMaxSataControllerNum ();= SataCtrlIndex++) { + HsioSataPreMemConfig =3D GetPchHsioSataPreMemConfig (SiPreMemPolicyPpi= , SataCtrlIndex); + PchPrintHsioSataPreMemConfig (SataCtrlIndex, HsioSataPreMemConfig); + } + PchPrintPcieRpPreMemConfig (PcieRpPreMemConfig); + PchPrintHdAudioPreMemConfig (HdaPreMemConfig); + PchPrintIshPreMemConfig (IshPreMemConfig); + + DEBUG ((DEBUG_INFO, "------------------------ PCH Print PreMemPolicy End= --------------------------\n")); + DEBUG_CODE_END (); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib= /PchPrintPolicy.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPo= licyLib/PchPrintPolicy.c new file mode 100644 index 0000000000..d9005b50ef --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PchPri= ntPolicy.c @@ -0,0 +1,778 @@ +/** @file + Print whole PCH_POLICY_PPI + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyLibrary.h" +#include + +/** + Print USB_CONFIG and serial out. + + @param[in] UsbConfig Pointer to a USB_CONFIG that provides the p= latform setting + +**/ +VOID +PchPrintUsbConfig ( + IN CONST USB_CONFIG *UsbConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ PCH USB Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, " EnableComplianceMode =3D %x\n", UsbConfi= g->EnableComplianceMode)); + DEBUG ((DEBUG_INFO, " PdoProgramming =3D %x\n", UsbConfi= g->PdoProgramming)); + DEBUG ((DEBUG_INFO, " OverCurrentEnable =3D %x\n", UsbConfi= g->OverCurrentEnable)); + DEBUG ((DEBUG_INFO, " XhciOcLock =3D %x\n", UsbConfi= g->XhciOcLock)); + DEBUG ((DEBUG_INFO, " Usb2PhySusPgEnable =3D %x\n", UsbConfi= g->Usb2PhySusPgEnable)); + + for (Index =3D 0; Index < GetPchUsb2MaxPhysicalPortNum (); Index++) { + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Enabled =3D %x\n", Index, U= sbConfig->PortUsb20[Index].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].OverCurrentPin =3D OC%x\n", Index,= UsbConfig->PortUsb20[Index].OverCurrentPin)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Petxiset =3D %x\n", Index, U= sbConfig->PortUsb20[Index].Afe.Petxiset)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Txiset =3D %x\n", Index, U= sbConfig->PortUsb20[Index].Afe.Txiset)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Predeemp =3D %x\n", Index, U= sbConfig->PortUsb20[Index].Afe.Predeemp)); + DEBUG ((DEBUG_INFO, " PortUsb20[%d].Afe.Pehalfbit =3D %x\n", Index, U= sbConfig->PortUsb20[Index].Afe.Pehalfbit)); + } + + for (Index =3D 0; Index < GetPchXhciMaxUsb3PortNum (); Index++) { + DEBUG ((DEBUG_INFO, " PortUsb30[%d] Enabled =3D %x\n"= , Index, UsbConfig->PortUsb30[Index].Enable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].OverCurrentPin =3D OC%x\= n", Index, UsbConfig->PortUsb30[Index].OverCurrentPin)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmphEnable =3D %x\n"= , Index, UsbConfig->PortUsb30[Index].HsioTxDeEmphEnable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDeEmph =3D %x\n"= , Index, UsbConfig->PortUsb30[Index].HsioTxDeEmph)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmpEnable =3D %x\n"= , Index, UsbConfig->PortUsb30[Index].HsioTxDownscaleAmpEnable)); + DEBUG ((DEBUG_INFO, " PortUsb30[%d].HsioTxDownscaleAmp =3D %x\n"= , Index, UsbConfig->PortUsb30[Index].HsioTxDownscaleAmp)); + + DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioCtrlAdaptOffsetCfgEnable= =3D %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffset= CfgEnable)); + DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioCtrlAdaptOffsetCfg = =3D %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffset= Cfg)); + DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioFilterSelNEnable = =3D %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelNEnabl= e)); + DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioFilterSelN = =3D %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelN)); + DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioFilterSelPEnable = =3D %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelPEnabl= e)); + DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioFilterSelP = =3D %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelP)); + DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioOlfpsCfgPullUpDwnResEnab= le =3D %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpD= wnResEnable)); + DEBUG ((DEBUG_INFO, " PortUsb30HsioRx[%d].HsioOlfpsCfgPullUpDwnRes = =3D %x\n", Index, UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpD= wnRes)); + } + + DEBUG ((DEBUG_INFO, " XdciConfig.Enable=3D %x\n", UsbConfig->XdciConfig.= Enable)); + +} + +/** + Print PCH_PCIE_CONFIG and serial out. + + @param[in] PcieConfig Pointer to a PCH_PCIE_CONFIG that provides= the platform setting + +**/ +VOID +PchPrintPcieConfig ( + IN CONST PCH_PCIE_CONFIG *PcieConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ PCH PCIE Config ----------------= --\n")); + for (Index =3D 0; Index < GetPchMaxPciePortNum (); Index++) { + DEBUG ((DEBUG_INFO, " RootPort[%d] HotPlug=3D %x\n", Index, PcieConfig= ->RootPort[Index].HotPlug)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PmSci=3D %x\n", Index, PcieConfig->= RootPort[Index].PmSci)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ExtSync=3D %x\n", Index, PcieConfig= ->RootPort[Index].ExtSync)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ClkReqDetect=3D %x\n", Index, PcieC= onfig->RootPort[Index].ClkReqDetect)); + DEBUG ((DEBUG_INFO, " RootPort[%d] UnsupportedRequestReport=3D %x\n", = Index, PcieConfig->RootPort[Index].UnsupportedRequestReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] FatalErrorReport=3D %x\n", Index, P= cieConfig->RootPort[Index].FatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NoFatalErrorReport=3D %x\n", Index,= PcieConfig->RootPort[Index].NoFatalErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CorrectableErrorReport=3D %x\n", In= dex, PcieConfig->RootPort[Index].CorrectableErrorReport)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnFatalError=3D %x\n", I= ndex, PcieConfig->RootPort[Index].SystemErrorOnFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnNonFatalError=3D %x\n"= , Index, PcieConfig->RootPort[Index].SystemErrorOnNonFatalError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SystemErrorOnCorrectableError=3D %x= \n", Index, PcieConfig->RootPort[Index].SystemErrorOnCorrectableError)); + DEBUG ((DEBUG_INFO, " RootPort[%d] MaxPayload=3D %x\n", Index, PcieCon= fig->RootPort[Index].MaxPayload)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotImplemented=3D %x\n", Index, Pc= ieConfig->RootPort[Index].SlotImplemented)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AcsEnabled=3D %x\n", Index, PcieCon= fig->RootPort[Index].AcsEnabled)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PtmEnabled=3D %x\n", Index, PcieCon= fig->RootPort[Index].PtmEnabled)); + DEBUG ((DEBUG_INFO, " RootPort[%d] AdvancedErrorReporting=3D %x\n", In= dex, PcieConfig->RootPort[Index].AdvancedErrorReporting)); + DEBUG ((DEBUG_INFO, " RootPort[%d] TransmitterHalfSwing=3D %x\n", Inde= x, PcieConfig->RootPort[Index].TransmitterHalfSwing)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PcieSpeed=3D %x\n", Index, PcieConf= ig->RootPort[Index].PcieSpeed)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Gen3EqPh3Method=3D %x\n", Index, Pc= ieConfig->RootPort[Index].Gen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " RootPort[%d] PhysicalSlotNumber=3D %x\n", Index,= PcieConfig->RootPort[Index].PhysicalSlotNumber)); + DEBUG ((DEBUG_INFO, " RootPort[%d] CompletionTimeout=3D %x\n", Index, = PcieConfig->RootPort[Index].CompletionTimeout)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Aspm=3D %x\n", Index, PcieConfig->R= ootPort[Index].Aspm)); + DEBUG ((DEBUG_INFO, " RootPort[%d] L1Substates=3D %x\n", Index, PcieCo= nfig->RootPort[Index].L1Substates)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrEnable=3D %x\n", Index, PcieConf= ig->RootPort[Index].LtrEnable)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrConfigLock=3D %x\n", Index, Pcie= Config->RootPort[Index].LtrConfigLock)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxSnoopLatency=3D %x\n", Index,= PcieConfig->RootPort[Index].LtrMaxSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] LtrMaxNoSnoopLatency=3D %x\n", Inde= x, PcieConfig->RootPort[Index].LtrMaxNoSnoopLatency)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMode=3D %x\n", = Index, PcieConfig->RootPort[Index].SnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideMultiplier=3D %= x\n", Index, PcieConfig->RootPort[Index].SnoopLatencyOverrideMultiplier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SnoopLatencyOverrideValue=3D %x\n",= Index, PcieConfig->RootPort[Index].SnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMode=3D %x\n= ", Index, PcieConfig->RootPort[Index].NonSnoopLatencyOverrideMode)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideMultiplier= =3D %x\n", Index, PcieConfig->RootPort[Index].NonSnoopLatencyOverrideMultip= lier)); + DEBUG ((DEBUG_INFO, " RootPort[%d] NonSnoopLatencyOverrideValue=3D %x\= n", Index, PcieConfig->RootPort[Index].NonSnoopLatencyOverrideValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] ForceLtrOverride=3D %x\n", Index, P= cieConfig->RootPort[Index].ForceLtrOverride)); + DEBUG ((DEBUG_INFO, " RootPort[%d] DetectTimeoutMs=3D %x\n", Index, Pc= ieConfig->RootPort[Index].DetectTimeoutMs)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitScale=3D %x\n", Index= , PcieConfig->RootPort[Index].SlotPowerLimitScale)); + DEBUG ((DEBUG_INFO, " RootPort[%d] SlotPowerLimitValue=3D %x\n", Index= , PcieConfig->RootPort[Index].SlotPowerLimitValue)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Uptp=3D %x\n", Index, PcieConfig->R= ootPort[Index].Uptp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] Dptp=3D %x\n", Index, PcieConfig->R= ootPort[Index].Dptp)); + DEBUG ((DEBUG_INFO, " RootPort[%d] EnableCpm=3D %x\n", Index, PcieConf= ig->RootPort[Index].EnableCpm)); + + } + for (Index =3D 0; Index < GetPchMaxPcieClockNum (); Index++) { + DEBUG ((DEBUG_INFO, " Clock[%d] Usage=3D %x\n", Index, PcieConfig->Pci= eClock[Index].Usage)); + DEBUG ((DEBUG_INFO, " Clock[%d] ClkReq=3D %x\n", Index, PcieConfig->Pc= ieClock[Index].ClkReq)); + } + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index++) { + DEBUG ((DEBUG_INFO, " SwEqCoeffCm[%d] =3D %x\n", Index, PcieConfig->Sw= EqCoeffList[Index].Cm)); + DEBUG ((DEBUG_INFO, " SwEqCoeffCp[%d] =3D %x\n", Index, PcieConfig->Sw= EqCoeffList[Index].Cp)); + } + DEBUG ((DEBUG_INFO, " EnablePort8xhDecode=3D %x\n", PcieConfig->EnablePo= rt8xhDecode)); + DEBUG ((DEBUG_INFO, " PchPciePort8xhDecodePortIndex=3D %x\n", PcieConfig= ->PchPciePort8xhDecodePortIndex)); + DEBUG ((DEBUG_INFO, " DisableRootPortClockGating=3D %x\n", PcieConfig->D= isableRootPortClockGating)); + DEBUG ((DEBUG_INFO, " EnablePeerMemoryWrite=3D %x\n", PcieConfig->Enable= PeerMemoryWrite)); + DEBUG ((DEBUG_INFO, " ComplianceTestMode=3D %x\n", PcieConfig->Complianc= eTestMode)); + DEBUG ((DEBUG_INFO, " RpFunctionSwap=3D %x\n", PcieConfig->RpFunctionSwa= p)); + DEBUG ((DEBUG_INFO, " PcieDeviceOverrideTablePtr=3D %x\n", PcieConfig->P= cieDeviceOverrideTablePtr)); +} + +/** + Print PCH_SATA_CONFIG and serial out. + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataConfig Pointer to a PCH_SATA_CONFIG that provides= the platform setting + +**/ +VOID +PchPrintSataConfig ( + IN UINT32 SataCtrlIndex, + IN CONST PCH_SATA_CONFIG *SataConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "--------------- PCH SATA Config for controller %d -= ----------\n", SataCtrlIndex)); + DEBUG ((DEBUG_INFO, " Enable=3D %x\n", SataConfig->Enable)); + DEBUG ((DEBUG_INFO, " SataMode=3D %x\n", SataConfig->SataMode)); + + for (Index =3D 0; Index < GetPchMaxSataPortNum (SataCtrlIndex); Index++)= { + DEBUG ((DEBUG_INFO, " PortSettings[%d] Enabled=3D %x\n", Index, SataCo= nfig->PortSettings[Index].Enable)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] HotPlug=3D %x\n", Index, SataCo= nfig->PortSettings[Index].HotPlug)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] InterlockSw=3D %x\n", Index, Sa= taConfig->PortSettings[Index].InterlockSw)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] External=3D %x\n", Index, SataC= onfig->PortSettings[Index].External)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SpinUp=3D %x\n", Index, SataCon= fig->PortSettings[Index].SpinUp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] SolidStateDrive=3D %x\n", Index= , SataConfig->PortSettings[Index].SolidStateDrive)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DevSlp=3D %x\n", Index, SataCon= fig->PortSettings[Index].DevSlp)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] EnableDitoConfig=3D %x\n", Inde= x, SataConfig->PortSettings[Index].EnableDitoConfig)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DmVal=3D %x\n", Index, SataConf= ig->PortSettings[Index].DmVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] DitoVal=3D %x\n", Index, SataCo= nfig->PortSettings[Index].DitoVal)); + DEBUG ((DEBUG_INFO, " PortSettings[%d] ZpOdd=3D %x\n", Index, SataConf= ig->PortSettings[Index].ZpOdd)); + } + + DEBUG ((DEBUG_INFO, " RaidDeviceId=3D %x\n", SataConfig->Rst.RaidDeviceI= d)); + DEBUG ((DEBUG_INFO, " Sata interrupt mode =3D %x\n", SataConfig->Rst.Sa= taRstInterrupt)); + DEBUG ((DEBUG_INFO, " Raid0=3D %x\n", SataConfig->Rst.Raid0)); + DEBUG ((DEBUG_INFO, " Raid1=3D %x\n", SataConfig->Rst.Raid1)); + DEBUG ((DEBUG_INFO, " Raid10=3D %x\n", SataConfig->Rst.Raid10)); + DEBUG ((DEBUG_INFO, " Raid5=3D %x\n", SataConfig->Rst.Raid5)); + DEBUG ((DEBUG_INFO, " Irrt=3D %x\n", SataConfig->Rst.Irrt)); + DEBUG ((DEBUG_INFO, " OromUiBanner=3D %x\n", SataConfig->Rst.OromUiBanne= r)); + DEBUG ((DEBUG_INFO, " OromUiDelay=3D %x\n", SataConfig->Rst.OromUiDelay)= ); + DEBUG ((DEBUG_INFO, " HddUnlock=3D %x\n", SataConfig->Rst.HddUnlock)); + DEBUG ((DEBUG_INFO, " LedLocate=3D %x\n", SataConfig->Rst.LedLocate)); + DEBUG ((DEBUG_INFO, " IrrtOnly=3D %x\n", SataConfig->Rst.IrrtOnly)); + DEBUG ((DEBUG_INFO, " SmartStorage=3D %x\n", SataConfig->Rst.SmartStorag= e)); + DEBUG ((DEBUG_INFO, " LegacyOrom=3D %x\n", SataConfig->Rst.LegacyOrom)); + DEBUG ((DEBUG_INFO, " OptaneMemory=3D %x\n", SataConfig->Rst.OptaneMemor= y)); + DEBUG ((DEBUG_INFO, " CpuAttachedStorage=3D %x\n", SataConfig->Rst.CpuAt= tachedStorage)); + + DEBUG ((DEBUG_INFO, " SpeedSupport=3D %x\n", SataConfig->SpeedLimit)); + DEBUG ((DEBUG_INFO, " EsataSpeedLimit=3D %x\n", SataConfig->EsataSpeedLi= mit)); + DEBUG ((DEBUG_INFO, " LedEnable=3D %x\n", SataConfig->LedEnable)); + DEBUG ((DEBUG_INFO, " TestMode=3D %x\n", SataConfig->TestMode)); + DEBUG ((DEBUG_INFO, " SalpSupport=3D %x\n", SataConfig->SalpSupport)); + DEBUG ((DEBUG_INFO, " PwrOptEnable=3D %x\n", SataConfig->PwrOptEnable)); + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].Enable = =3D %x\n", Index, SataConfig->RstPcieStorageRemap[Index].Enable)); + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].RstPcieStoragePort = =3D %x\n", Index, SataConfig->RstPcieStorageRemap[Index].RstPcieStoragePort= )); + DEBUG ((DEBUG_INFO, " RstPcieStorageRemap[%d].DeviceResetDelay = =3D %x\n", Index, SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay)); + } + DEBUG ((DEBUG_INFO, " ThermalThrottling P0T1M %x\n", SataConfig->Thermal= Throttling.P0T1M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P0T2M %x\n", SataConfig->Thermal= Throttling.P0T2M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P0T3M %x\n", SataConfig->Thermal= Throttling.P0T3M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P0TDisp %x\n", SataConfig->Therm= alThrottling.P0TDisp)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P0Tinact %x\n", SataConfig->Ther= malThrottling.P0Tinact)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P0TDispFinit %x\n", SataConfig->= ThermalThrottling.P0TDispFinit)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P1T1M %x\n", SataConfig->Thermal= Throttling.P1T1M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P1T2M %x\n", SataConfig->Thermal= Throttling.P1T2M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P1T3M %x\n", SataConfig->Thermal= Throttling.P1T3M)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P1TDisp %x\n", SataConfig->Therm= alThrottling.P1TDisp)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P1Tinact %x\n", SataConfig->Ther= malThrottling.P1Tinact)); + DEBUG ((DEBUG_INFO, " ThermalThrottling P1TDispFinit %x\n", SataConfig->= ThermalThrottling.P1TDispFinit)); + DEBUG ((DEBUG_INFO, " ThermalThrottling SuggestedSetting %x\n", SataConf= ig->ThermalThrottling.SuggestedSetting)); +} + +/** + Print PCH_IOAPIC_CONFIG and serial out. + + @param[in] IoApicConfig Pointer to a PCH_IOAPIC_CONFIG that prov= ides the platform setting + +**/ +VOID +PchPrintIoApicConfig ( + IN CONST PCH_IOAPIC_CONFIG *IoApicConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH IOAPIC Config --------------= ----\n")); + DEBUG ((DEBUG_INFO, " IoApicEntry24_119=3D %x\n", IoApicConfig->IoApicEn= try24_119)); + DEBUG ((DEBUG_INFO, " Enable8254ClockGating=3D %x\n", IoApicConfig->Enab= le8254ClockGating)); + DEBUG ((DEBUG_INFO, " Enable8254ClockGatingOnS3=3D %x\n", IoApicConfig->= Enable8254ClockGatingOnS3)); + DEBUG ((DEBUG_INFO, " IoApicId=3D %x\n", IoApicConfig->IoApicId)); +} + +/** + Print PCH_LOCK_DOWN_CONFIG and serial out. + + @param[in] LockDownConfig Pointer to a PCH_LOCK_DOWN_CONFIG that= provides the platform setting + +**/ +VOID +PchPrintLockDownConfig ( + IN CONST PCH_LOCK_DOWN_CONFIG *LockDownConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH Lock Down Config -----------= -------\n")); + DEBUG ((DEBUG_INFO, " GlobalSmi=3D %x\n", LockDownConfig->GlobalSmi)); + DEBUG ((DEBUG_INFO, " BiosInterface=3D %x\n", LockDownConfig->BiosInterf= ace)); + DEBUG ((DEBUG_INFO, " RtcMemoryLock=3D %x\n", LockDownConfig->RtcMemoryL= ock)); + DEBUG ((DEBUG_INFO, " BiosLock=3D %x\n", LockDownConfig->BiosLock)); + DEBUG ((DEBUG_INFO, " UnlockGpioPads=3D %x\n", LockDownConfig->UnlockGpi= oPads)); +} + +/** + Print PCH_HDAUDIO_CONFIG and serial out. + + @param[in] HdaConfig Pointer to a PCH_HDAUDIO_CONFIG that provid= es the platform setting + +**/ +VOID +PchPrintHdAudioConfig ( + IN CONST PCH_HDAUDIO_CONFIG *HdaConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH HD-Audio Config ------------= ------\n")); + DEBUG ((DEBUG_INFO, " DSP Enable =3D %x\n", HdaConfig->Dsp= Enable)); + DEBUG ((DEBUG_INFO, " DSP UAA Compliance =3D %x\n", HdaConfig->Dsp= UaaCompliance)); + DEBUG ((DEBUG_INFO, " iDisp Codec Disconnect =3D %x\n", HdaConfig->IDi= spCodecDisconnect)); + DEBUG ((DEBUG_INFO, " Pme =3D %x\n", HdaConfig->Pme= )); + DEBUG ((DEBUG_INFO, " Codec Sx Wake Capability =3D %x\n", HdaConfig->Cod= ecSxWakeCapability)); + DEBUG ((DEBUG_INFO, " VC Type =3D %x\n", HdaConfig->VcT= ype)); + DEBUG ((DEBUG_INFO, " HD-A Link Frequency =3D %x\n", HdaConfig->HdA= udioLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link Frequency =3D %x\n", HdaConfig->IDi= spLinkFrequency)); + DEBUG ((DEBUG_INFO, " iDisp Link T-Mode =3D %x\n", HdaConfig->IDi= spLinkTmode)); + DEBUG ((DEBUG_INFO, " Audio Link: HDA Link =3D %x\n", HdaConfig->Aud= ioLinkHda)); + DEBUG ((DEBUG_INFO, " Audio Link: DMIC#0 =3D %x\n", HdaConfig->Aud= ioLinkDmic0)); + DEBUG ((DEBUG_INFO, " Audio Link: DMIC#1 =3D %x\n", HdaConfig->Aud= ioLinkDmic1)); + DEBUG ((DEBUG_INFO, " Audio Link: SSP#0 =3D %x\n", HdaConfig->Aud= ioLinkSsp0)); + DEBUG ((DEBUG_INFO, " Audio Link: SSP#1 =3D %x\n", HdaConfig->Aud= ioLinkSsp1)); + DEBUG ((DEBUG_INFO, " Audio Link: SSP#2 =3D %x\n", HdaConfig->Aud= ioLinkSsp1)); + DEBUG ((DEBUG_INFO, " Audio Link: SoundWire#1 =3D %x\n", HdaConfig->Aud= ioLinkSndw1)); + DEBUG ((DEBUG_INFO, " Audio Link: SoundWire#2 =3D %x\n", HdaConfig->Aud= ioLinkSndw2)); + DEBUG ((DEBUG_INFO, " Audio Link: SoundWire#3 =3D %x\n", HdaConfig->Aud= ioLinkSndw3)); + DEBUG ((DEBUG_INFO, " Audio Link: SoundWire#4 =3D %x\n", HdaConfig->Aud= ioLinkSndw4)); + DEBUG ((DEBUG_INFO, " SoundWire Buffer RCOMP =3D %x\n", HdaConfig->Snd= wBufferRcomp)); + DEBUG ((DEBUG_INFO, " ResetWaitTimer =3D %x\n", HdaConfig->Res= etWaitTimer)); + DEBUG ((DEBUG_INFO, " VerbTableEntryNum =3D %x\n", HdaConfig->Ver= bTableEntryNum)); + DEBUG ((DEBUG_INFO, " VerbTablePtr =3D %x\n", HdaConfig->Ver= bTablePtr)); +} + +/** + Print PCH_PM_CONFIG and serial out. + + @param[in] PmConfig Pointer to a PCH_PM_CONFIG that provides the= platform setting + +**/ +VOID +PchPrintPmConfig ( + IN CONST PCH_PM_CONFIG *PmConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH PM Config ------------------= \n")); + + DEBUG ((DEBUG_INFO, " WakeConfig PmeB0S5Dis =3D %x\n", PmC= onfig->WakeConfig.PmeB0S5Dis)); + DEBUG ((DEBUG_INFO, " WakeConfig WolEnableOverride =3D %x\n", PmC= onfig->WakeConfig.WolEnableOverride)); + DEBUG ((DEBUG_INFO, " WakeConfig LanWakeFromDeepSx =3D %x\n", PmC= onfig->WakeConfig.LanWakeFromDeepSx)); + DEBUG ((DEBUG_INFO, " WakeConfig PcieWakeFromDeepSx =3D %x\n", PmC= onfig->WakeConfig.PcieWakeFromDeepSx)); + DEBUG ((DEBUG_INFO, " WakeConfig WoWlanEnable =3D %x\n", PmC= onfig->WakeConfig.WoWlanEnable)); + DEBUG ((DEBUG_INFO, " WakeConfig WoWlanDeepSxEnable =3D %x\n", PmC= onfig->WakeConfig.WoWlanDeepSxEnable)); + + DEBUG ((DEBUG_INFO, " PchDeepSxPol =3D %x\n", PmC= onfig->PchDeepSxPol)); + DEBUG ((DEBUG_INFO, " PchSlpS3MinAssert =3D %x\n", PmC= onfig->PchSlpS3MinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpS4MinAssert =3D %x\n", PmC= onfig->PchSlpS4MinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpSusMinAssert =3D %x\n", PmC= onfig->PchSlpSusMinAssert)); + DEBUG ((DEBUG_INFO, " PchSlpAMinAssert =3D %x\n", PmC= onfig->PchSlpAMinAssert)); + DEBUG ((DEBUG_INFO, " LpcClockRun =3D %x\n", PmC= onfig->LpcClockRun)); + DEBUG ((DEBUG_INFO, " SlpStrchSusUp =3D %x\n", PmC= onfig->SlpStrchSusUp)); + DEBUG ((DEBUG_INFO, " SlpLanLowDc =3D %x\n", PmC= onfig->SlpLanLowDc)); + DEBUG ((DEBUG_INFO, " PwrBtnOverridePeriod =3D %x\n", PmC= onfig->PwrBtnOverridePeriod)); + DEBUG ((DEBUG_INFO, " DisableEnergyReport =3D %x\n", PmC= onfig->DisableEnergyReport)); + DEBUG ((DEBUG_INFO, " DisableDsxAcPresentPulldown =3D %x\n", PmC= onfig->DisableDsxAcPresentPulldown)); + DEBUG ((DEBUG_INFO, " PchPwrCycDur =3D %x\n", PmC= onfig->PchPwrCycDur)); + DEBUG ((DEBUG_INFO, " PciePllSsc =3D %x\n", PmC= onfig->PciePllSsc)); + DEBUG ((DEBUG_INFO, " DisableNativePowerButton =3D %x\n", PmC= onfig->DisableNativePowerButton)); + DEBUG ((DEBUG_INFO, " SlpS0Enabled =3D %x\n", PmC= onfig->SlpS0Enable)); + DEBUG ((DEBUG_INFO, " MeWakeSts =3D %x\n", PmC= onfig->MeWakeSts)); + DEBUG ((DEBUG_INFO, " WolOvrWkSts =3D %x\n", PmC= onfig->WolOvrWkSts)); + DEBUG ((DEBUG_INFO, " EnableTcoTimer =3D %x\n", PmC= onfig->EnableTcoTimer)); + DEBUG ((DEBUG_INFO, " VrAlert =3D %x\n", PmC= onfig->VrAlert)); + DEBUG ((DEBUG_INFO, " PowerButtonDebounce =3D %x\n", PmC= onfig->PowerButtonDebounce)); + DEBUG ((DEBUG_INFO, " SlpS0VmRuntimeControl =3D %x\n", PmC= onfig->SlpS0VmRuntimeControl)); + DEBUG ((DEBUG_INFO, " SlpS0Vm070VSupport =3D %x\n", PmC= onfig->SlpS0Vm070VSupport)); + DEBUG ((DEBUG_INFO, " SlpS0Vm075VSupport =3D %x\n", PmC= onfig->SlpS0Vm075VSupport)); + DEBUG ((DEBUG_INFO, " SlpS0Override =3D %x\n", PmC= onfig->SlpS0Override)); + DEBUG ((DEBUG_INFO, " SlpS0DisQForDebug =3D %x\n", PmC= onfig->SlpS0DisQForDebug)); + DEBUG ((DEBUG_INFO, " PsOnEnable =3D %x\n", PmC= onfig->PsOnEnable)); + DEBUG ((DEBUG_INFO, " CpuC10GatePinEnable =3D %x\n", PmC= onfig->CpuC10GatePinEnable)); + DEBUG ((DEBUG_INFO, " PmcDbgMsgEn =3D %x\n", PmC= onfig->PmcDbgMsgEn)); + DEBUG ((DEBUG_INFO, " ModPhySusPgEnable =3D %x\n", PmC= onfig->ModPhySusPgEnable)); + DEBUG ((DEBUG_INFO, " SlpS0WithGbeSupport =3D %x\n", PmC= onfig->SlpS0WithGbeSupport)); +} + +/** + Print PCH_DMI_CONFIG and serial out. + + @param[in] DmiConfig Pointer to a PCH_DMI_CONFIG that provides t= he platform setting + +**/ +VOID +PchPrintDmiConfig ( + IN CONST PCH_DMI_CONFIG *DmiConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH DMI Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, " PwrOptEnable=3D %x\n", DmiConfig->PwrOptEnable)); + DEBUG ((DEBUG_INFO, " DmiAspmCtrl=3D %x\n", DmiConfig->DmiAspmCtrl)); +} +/** + Print PCH_LPC_SIRQ_CONFIG and serial out. + + @param[in] SerialIrqConfig Pointer to a PCH_LPC_SIRQ_CONFIG that= provides the platform setting + +**/ +VOID +PchPrintSerialIrqConfig ( + IN CONST PCH_LPC_SIRQ_CONFIG *SerialIrqConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LPC SIRQ Config ------------= ------\n")); + DEBUG ((DEBUG_INFO, " SirqEnable=3D %x\n", SerialIrqConfig->SirqEnable)); + DEBUG ((DEBUG_INFO, " SirqMode=3D %x\n", SerialIrqConfig->SirqMode)); + DEBUG ((DEBUG_INFO, " StartFramePulse=3D %x\n", SerialIrqConfig->StartFr= amePulse)); +} +/** + Print PCH_THERMAL_CONFIG and serial out. + + @param[in] ThermalConfig Pointer to a PCH_THERMAL_CONFIG that pr= ovides the platform setting + +**/ +VOID +PchPrintThermalConfig ( + IN CONST PCH_THERMAL_CONFIG *ThermalConfig + ) +{ + UINTN Index; + + DEBUG ((DEBUG_INFO, "------------------ PCH Thermal Config -------------= -----\n")); + DEBUG ((DEBUG_INFO, " TsmicLock=3D %x\n", ThermalConfig->TsmicLock)); + DEBUG ((DEBUG_INFO, " TTLevels T0Level %x centigrade degree\n", ThermalC= onfig->TTLevels.T0Level)); + DEBUG ((DEBUG_INFO, " TTLevels T1Level %x centigrade degree\n", ThermalC= onfig->TTLevels.T1Level)); + DEBUG ((DEBUG_INFO, " TTLevels T2Level %x centigrade degree\n", ThermalC= onfig->TTLevels.T2Level)); + DEBUG ((DEBUG_INFO, " TTLevels TTEnable %x\n", ThermalConfig->TTLevels.T= TEnable)); + DEBUG ((DEBUG_INFO, " TTLevels TTState13Enable %x\n", ThermalConfig->TTL= evels.TTState13Enable)); + DEBUG ((DEBUG_INFO, " TTLevels TTLock %x\n", ThermalConfig->TTLevels.TTL= ock)); + DEBUG ((DEBUG_INFO, " TTLevels SuggestedSetting %x\n", ThermalConfig->TT= Levels.SuggestedSetting)); + DEBUG ((DEBUG_INFO, " TTLevels PchCrossThrottling %x\n", ThermalConfig->= TTLevels.PchCrossThrottling)); + + DEBUG ((DEBUG_INFO, " DmiHaAWC DmiTsawEn %x\n", ThermalConfig->DmiHaAWC.= DmiTsawEn)); + DEBUG ((DEBUG_INFO, " DmiHaAWC TS0TW %x\n", ThermalConfig->DmiHaAWC.TS0T= W)); + DEBUG ((DEBUG_INFO, " DmiHaAWC TS1TW %x\n", ThermalConfig->DmiHaAWC.TS1T= W)); + DEBUG ((DEBUG_INFO, " DmiHaAWC TS2TW %x\n", ThermalConfig->DmiHaAWC.TS2T= W)); + DEBUG ((DEBUG_INFO, " DmiHaAWC TS3TW %x\n", ThermalConfig->DmiHaAWC.TS3T= W)); + DEBUG ((DEBUG_INFO, " DmiHaAWC SuggestedSetting %x\n", ThermalConfig->Dm= iHaAWC.SuggestedSetting)); + + DEBUG ((DEBUG_INFO, " MemoryThrottling Enable=3D %x\n", ThermalConfig->M= emoryThrottling.Enable)); + for (Index =3D 0; Index < MaxTsGpioPin; Index++) { + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PmsyncEnable= =3D %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[Index].PmsyncEn= able)); + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting C0TransmitEnab= le=3D %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[Index].C0Tran= smitEnable)); + DEBUG ((DEBUG_INFO, " MemoryThrottling TsGpioPinSetting PinSelection= =3D %x\n", ThermalConfig->MemoryThrottling.TsGpioPinSetting[Index].PinSelec= tion)); + } + DEBUG ((DEBUG_INFO, " PchHotEnable =3D %x\n", ThermalConfig->PchHotEnabl= e)); + DEBUG ((DEBUG_INFO, " PchHotLevel =3D %x\n", ThermalConfig->PchHotLevel)= ); +} + +/** + Print PCH_GENERAL_CONFIG and serial out. + + @param[in] PchGeneralConfig Pointer to a PCH_GENERAL_CONFIG that provi= des the platform setting + +**/ +VOID +PchPrintGeneralConfig ( + IN CONST PCH_GENERAL_CONFIG *PchGeneralConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH General Config -------------= -----\n")); + DEBUG ((DEBUG_INFO, " Crid=3D %x\n", PchGeneralConfig->Crid)); + DEBUG ((DEBUG_INFO, " LegacyIoLowLatency =3D %x\n", PchGeneralConfig->Le= gacyIoLowLatency)); +} + +/** + Print PCH_LAN_CONFIG and serial out. + + @param[in] LanConfig Pointer to a PCH_LAN_CONFIG that provides t= he platform setting + +**/ +VOID +PchPrintLanConfig ( + IN CONST PCH_LAN_CONFIG *LanConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH LAN Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, " Enable=3D %x\n", LanConfig->Enable)); + DEBUG ((DEBUG_INFO, " LtrEnable=3D %x\n", LanConfig->LtrEnable)); +} + +/** + Print PCH_SERIAL_IO_CONFIG and serial out. + + @param[in] SerialIoConfig Pointer to a PCH_SERIAL_IO_CONFIG that= provides the platform setting + +**/ +VOID +PchPrintSerialIoConfig ( + IN CONST PCH_SERIAL_IO_CONFIG *SerialIoConfig + ) +{ + UINTN Index; +#ifndef MDEPKG_NDEBUG + static UINT8 DeviceName[PCH_MAX_SERIALIO_CONTROLLERS][5] =3D {"I2C0","I2= C1","I2C2","I2C3","I2C4","I2C5","SPI0","SPI1","SPI2","UA00","UA01","UA02"}; +#endif + + DEBUG ((DEBUG_INFO, "------------------ PCH Serial IO Config -----------= -------\n")); + DEBUG_CODE_BEGIN (); + for (Index =3D 0; Index < GetPchMaxSerialIoControllersNum (); Index++) { + DEBUG ((DEBUG_INFO, " SerialIoController %a: Mode 0x%x\n", DeviceName[= Index], SerialIoConfig->DevMode[Index])); + } + DEBUG_CODE_END (); + for (Index =3D 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index++= ) { + DEBUG ((DEBUG_INFO, " SpiCsPolarity[%d] =3D 0x%x\n", Index, SerialIoCo= nfig->SpiCsPolarity[Index])); + } + for (Index =3D 0; Index < GetPchMaxSerialIoUartControllersNum (); Index+= +) { + DEBUG ((DEBUG_INFO, " UartHwFlowCtrl[%d] =3D 0x%x\n", Index, SerialIoC= onfig->UartHwFlowCtrl[Index])); + } + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index += +) { + DEBUG ((DEBUG_INFO, " I2cPadsTermination[%d] =3D 0x%x\n", Index, Seria= lIoConfig->I2cPadsTermination[Index])); + } + DEBUG ((DEBUG_INFO, " DebugUartNumber =3D 0x%x\n", SerialIoConfig->Debug= UartNumber)); + DEBUG ((DEBUG_INFO, " EnableDebugUartAfterPost =3D 0x%x\n", SerialIoConf= ig->EnableDebugUartAfterPost)); + DEBUG ((DEBUG_INFO, " Uart0PinMuxing =3D 0x%x\n", SerialIoConfig->Uart0P= inMuxing)); +} + +/** + Print PCH_INTERRUPT_CONFIG and serial out + + @param[in] InterruptConfig Pointer to Interrupt Configuration str= ucture + +**/ +VOID +PchPrintInterruptConfig ( + IN CONST PCH_INTERRUPT_CONFIG *InterruptConfig + ) +{ + UINTN Index; + // + // Print interrupt information + // + DEBUG ((DEBUG_INFO, "------------------ PCH Interrupt Config -----------= -------\n")); + DEBUG ((DEBUG_INFO, " Interrupt assignment:\n")); + DEBUG ((DEBUG_INFO, " Dxx:Fx INTx IRQ\n")); + for (Index =3D 0; Index < InterruptConfig->NumOfDevIntConfig; Index++) { + DEBUG ((DEBUG_INFO, " D%02d:F%d %d %03d\n", + InterruptConfig->DevIntConfig[Index].Device, + InterruptConfig->DevIntConfig[Index].Function, + InterruptConfig->DevIntConfig[Index].IntX, + InterruptConfig->DevIntConfig[Index].Irq)); + } + DEBUG ((DEBUG_INFO, " Legacy PIC interrupt routing:\n")); + DEBUG ((DEBUG_INFO, " PIRQx IRQx\n")); + for (Index =3D 0; Index < PCH_MAX_PXRC_CONFIG; Index++) { + DEBUG ((DEBUG_INFO, " PIRQ%c -> IRQ%d\n", Index + 65, InterruptConfig= ->PxRcConfig[Index])); + } + DEBUG ((DEBUG_INFO, " Other interrupt configuration:\n")); + DEBUG ((DEBUG_INFO, " GpioIrqRoute=3D %d\n", InterruptConfig->GpioIrqRo= ute)); + DEBUG ((DEBUG_INFO, " SciIrqSelect=3D %d\n", InterruptConfig->SciIrqSel= ect)); + DEBUG ((DEBUG_INFO, " TcoIrqEnable=3D %d\n", InterruptConfig->TcoIrqEna= ble)); + DEBUG ((DEBUG_INFO, " TcoIrqSelect=3D %d\n", InterruptConfig->TcoIrqSel= ect)); +} + +/** + Print PCH_SCS_CONFIG and serial out. + + @param[in] ScsConfig Pointer to a PCH_SCS_CONFIG that provides t= he platform setting + +**/ +VOID +PchPrintScsConfig ( + IN CONST PCH_SCS_CONFIG *ScsConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH SCS Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, " ScsEmmcEnabled =3D %x\n", ScsConfig->ScsEmmcEnable= d)); + DEBUG ((DEBUG_INFO, " ScsSdcardEnabled =3D %x\n", ScsConfig->ScsSdcardEn= abled)); + DEBUG ((DEBUG_INFO, " SdCardPowerEnableActiveHigh =3D %x\n", ScsConfig->= SdCardPowerEnableActiveHigh)); + DEBUG ((DEBUG_INFO, " ScsUfsEnabled =3D %x\n", ScsConfig->ScsUfsEnabled)= ); + DEBUG ((DEBUG_INFO, " ScsEmmcHs400Enabled =3D %x\n", ScsConfig->ScsEmmcH= s400Enabled)); + DEBUG ((DEBUG_INFO, " ScsEmmcHs400TuningRequired =3D %x\n", ScsConfig->S= csEmmcHs400TuningRequired)); + DEBUG ((DEBUG_INFO, " ScsEmmcHs400DllDataValid =3D %x\n", ScsConfig->Scs= EmmcHs400DllDataValid)); + DEBUG ((DEBUG_INFO, " ScsEmmcHs400RxStrobeDll1 =3D %x\n", ScsConfig->Scs= EmmcHs400RxStrobeDll1)); + DEBUG ((DEBUG_INFO, " ScsEmmcHs400TxDataDll =3D %x\n", ScsConfig->ScsEmm= cHs400TxDataDll)); + DEBUG ((DEBUG_INFO, " ScsEmmcHs400DriverStrength =3D %x\n", ScsConfig->S= csEmmcHs400DriverStrength)); +} + +/** + Print PCH_ISH_CONFIG and serial out. + + @param[in] IshConfig Pointer to a PCH_ISH_CONFIG that provides t= he platform setting + +**/ +VOID +PchPrintIshConfig ( + IN CONST PCH_ISH_CONFIG *IshConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH ISH Config -----------------= -\n")); + DEBUG ((DEBUG_INFO, " SPI GPIO Assigned =3D %x\n", IshConfig->SpiGpioA= ssign)); + DEBUG ((DEBUG_INFO, " UART0 GPIO Assigned =3D %x\n", IshConfig->Uart0Gpi= oAssign)); + DEBUG ((DEBUG_INFO, " UART1 GPIO Assigned =3D %x\n", IshConfig->Uart1Gpi= oAssign)); + DEBUG ((DEBUG_INFO, " I2C0 GPIO Assigned =3D %x\n", IshConfig->I2c0Gpio= Assign)); + DEBUG ((DEBUG_INFO, " I2C1 GPIO Assigned =3D %x\n", IshConfig->I2c1Gpio= Assign)); + DEBUG ((DEBUG_INFO, " I2C2 GPIO Assigned =3D %x\n", IshConfig->I2c2Gpio= Assign)); + DEBUG ((DEBUG_INFO, " GP_0 GPIO Assigned =3D %x\n", IshConfig->Gp0GpioA= ssign)); + DEBUG ((DEBUG_INFO, " GP_1 GPIO Assigned =3D %x\n", IshConfig->Gp1GpioA= ssign)); + DEBUG ((DEBUG_INFO, " GP_2 GPIO Assigned =3D %x\n", IshConfig->Gp2GpioA= ssign)); + DEBUG ((DEBUG_INFO, " GP_3 GPIO Assigned =3D %x\n", IshConfig->Gp3GpioA= ssign)); + DEBUG ((DEBUG_INFO, " GP_4 GPIO Assigned =3D %x\n", IshConfig->Gp4GpioA= ssign)); + DEBUG ((DEBUG_INFO, " GP_5 GPIO Assigned =3D %x\n", IshConfig->Gp5GpioA= ssign)); + DEBUG ((DEBUG_INFO, " GP_6 GPIO Assigned =3D %x\n", IshConfig->Gp6GpioA= ssign)); + DEBUG ((DEBUG_INFO, " GP_7 GPIO Assigned =3D %x\n", IshConfig->Gp7GpioA= ssign)); +} + +/** + Print PCH_FLASH_PROTECTION_CONFIG and serial out. + + @param[in] FlashProtectConfig Pointer to a PCH_FLASH_PROTECTION_CONFIG = that provides the platform setting + +**/ +VOID +PchPrintFlashProtectionConfig ( + IN CONST PCH_FLASH_PROTECTION_CONFIG *FlashProtectConfig + ) +{ + UINT32 Index; + + DEBUG ((DEBUG_INFO, "------------------ PCH Flash Protection Config ----= --------------\n")); + for (Index =3D 0; Index < PCH_FLASH_PROTECTED_RANGES; ++Index) { + DEBUG ((DEBUG_INFO, " WriteProtectionEnable[%d] =3D %x\n", Index, Flas= hProtectConfig->ProtectRange[Index].WriteProtectionEnable)); + DEBUG ((DEBUG_INFO, " ReadProtectionEnable[%d] =3D %x\n", Index, Flas= hProtectConfig->ProtectRange[Index].ReadProtectionEnable)); + DEBUG ((DEBUG_INFO, " ProtectedRangeLimit[%d] =3D %x\n", Index, Flas= hProtectConfig->ProtectRange[Index].ProtectedRangeLimit)); + DEBUG ((DEBUG_INFO, " ProtectedRangeBase[%d] =3D %x\n", Index, Flas= hProtectConfig->ProtectRange[Index].ProtectedRangeBase)); + } +} + +/** + Print PCH_P2SB_CONFIG and serial out. + + @param[in] P2sbConfig Pointer to a PCH_P2SB_CONFIG that = provides the platform setting + +**/ +VOID +PchPrintP2sbConfig ( + IN CONST PCH_P2SB_CONFIG *P2sbConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH P2SB Config ----------------= --\n")); + DEBUG ((DEBUG_INFO, "SbAccessUnlock=3D %x\n", P2sbConfig->SbAccessUnlock= )); +} + +/** + Print PCH_ESPI_CONFIG. + + @param[in] EspiConfig Pointer to a PCH_ESPI_CONFIG that provides= the eSPI setting + +**/ +VOID +PchPrintEspiConfig ( + IN CONST PCH_ESPI_CONFIG *EspiConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH eSPI Config ----------------= --\n")); + DEBUG ((DEBUG_INFO, " LGMR Enable %x\n", EspiConfig->LgmrEnable)); + DEBUG ((DEBUG_INFO, " BME for Master and Slave Enabled %x\n", EspiConfig= ->BmeMasterSlaveEnabled)); +} + +/** + Print PCH_CNVI_CONFIG. + + @param[in] CnviConfig Pointer to a PCH_CNVI_CONFIG that provides= the CNVi settings + +**/ +VOID +PchPrintCnviConfig ( + IN CONST PCH_CNVI_CONFIG *CnviConfig + ) +{ + DEBUG ((DEBUG_INFO, "------------------ PCH CNVi Config ----------------= --\n")); + DEBUG ((DEBUG_INFO, "CNVi Mode =3D %x\n", CnviConfig->Mode)); + DEBUG ((DEBUG_INFO, "CNVi MfUart1 type =3D %x\n", CnviConfig->MfUart1Typ= e)); +} + +/** + Print PCH_HSIO_CONFIG. + + @param[in] HsioConfig Pointer to a PCH_HSIO_CONFIG that provides= the eSPI setting + +**/ +VOID +PchPrintHsioConfig ( + IN CONST PCH_HSIO_CONFIG *HsioConfig + ) +{ + PCH_HSIO_VER_INFO *BiosChipsetInitVerInfoPtr; + DEBUG ((DEBUG_INFO, "------------------ PCH HSIO Config ----------------= --\n")); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Pointer =3D %x\n", H= sioConfig->ChipsetInitBinPtr)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Length =3D %x\n", H= sioConfig->ChipsetInitBinLen)); + BiosChipsetInitVerInfoPtr =3D (PCH_HSIO_VER_INFO *) HsioConfig->ChipsetI= nitBinPtr; + if (HsioConfig->ChipsetInitBinPtr && HsioConfig->ChipsetInitBinLen) { + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base CRC =3D %x\n",= BiosChipsetInitVerInfoPtr->BaseCrc)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM CRC =3D %x\n",= BiosChipsetInitVerInfoPtr->OemCrc)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary SUS CRC =3D %x\n",= BiosChipsetInitVerInfoPtr->SusCrc)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Version =3D %x\n",= BiosChipsetInitVerInfoPtr->Version)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Product =3D %x\n",= BiosChipsetInitVerInfoPtr->Product)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Metal Layer =3D %x\n",= BiosChipsetInitVerInfoPtr->MetalLayer)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base Layer =3D %x\n",= BiosChipsetInitVerInfoPtr->BaseLayer)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM Version =3D %x\n",= BiosChipsetInitVerInfoPtr->OemVersion)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Debug Mode =3D %x\n",= BiosChipsetInitVerInfoPtr->DebugMode)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary OEM CRC Valid =3D %x\n",= BiosChipsetInitVerInfoPtr->OemCrcValid)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary SUS CRC Valid =3D %x\n",= BiosChipsetInitVerInfoPtr->SusCrcValid)); + DEBUG ((DEBUG_INFO, " ChipsetInit Binary Base CRC Valid =3D %x\n",= BiosChipsetInitVerInfoPtr->BaseCrcValid)); + } +} + +/** + Print whole PCH config blocks and serial out. + + @param[in] SiPolicyPpi The RC Policy PPI instance + +**/ +VOID +EFIAPI +PchPrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ) +{ +DEBUG_CODE_BEGIN(); + EFI_STATUS Status; + PCH_GENERAL_CONFIG *PchGeneralConfig; + PCH_PCIE_CONFIG *PcieRpConfig; + PCH_SATA_CONFIG *SataConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_DMI_CONFIG *DmiConfig; + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + PCH_HDAUDIO_CONFIG *HdAudioConfig; + PCH_INTERRUPT_CONFIG *InterruptConfig; + PCH_ISH_CONFIG *IshConfig; + PCH_LAN_CONFIG *LanConfig; + PCH_P2SB_CONFIG *P2sbConfig; + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + PCH_PM_CONFIG *PmConfig; + PCH_SCS_CONFIG *ScsConfig; + PCH_SERIAL_IO_CONFIG *SerialIoConfig; + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; + PCH_THERMAL_CONFIG *ThermalConfig; + USB_CONFIG *UsbConfig; + PCH_ESPI_CONFIG *EspiConfig; + PCH_CNVI_CONFIG *CnviConfig; + PCH_HSIO_CONFIG *HsioConfig; + UINT32 SataCtrlIndex; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid,= (VOID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gPcieRpConfigGuid, (VO= ID *) &PcieRpConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gIoApicConfigGuid, (VO= ID *) &IoApicConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gDmiConfigGuid, (VOID = *) &DmiConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gFlashProtectionConfig= Guid, (VOID *) &FlashProtectionConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gHdAudioConfigGuid, (V= OID *) &HdAudioConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gInterruptConfigGuid, = (VOID *) &InterruptConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gIshConfigGuid, (VOID = *) &IshConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gLanConfigGuid, (VOID = *) &LanConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gLockDownConfigGuid, (= VOID *) &LockDownConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gP2sbConfigGuid, (VOID= *) &P2sbConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gPmConfigGuid, (VOID *= ) &PmConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gScsConfigGuid, (VOID = *) &ScsConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSerialIoConfigGuid, (= VOID *) &SerialIoConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSerialIrqConfigGuid, = (VOID *) &SerialIrqConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gThermalConfigGuid, (V= OID *) &ThermalConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gUsbConfigGuid, (VOID = *) &UsbConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gEspiConfigGuid, (VOID= *) &EspiConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCnviConfigGuid, (VOID= *) &CnviConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gHsioConfigGuid, (VOID= *) &HsioConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "------------------------ PCH Print Policy Start ---= ---------------------\n")); + DEBUG ((DEBUG_INFO, " Revision=3D %x\n", SiPolicyPpi->TableHeader.Header= .Revision)); + + PchPrintGeneralConfig (PchGeneralConfig); + PchPrintPcieConfig (PcieRpConfig); + for (SataCtrlIndex =3D 0; SataCtrlIndex < GetPchMaxSataControllerNum ();= SataCtrlIndex++) { + SataConfig =3D GetPchSataConfig (SiPolicyPpi, SataCtrlIndex); + PchPrintSataConfig (SataCtrlIndex, SataConfig); + } + PchPrintUsbConfig (UsbConfig); + PchPrintIoApicConfig (IoApicConfig); + PchPrintHdAudioConfig (HdAudioConfig); + PchPrintLanConfig (LanConfig); + PchPrintLockDownConfig (LockDownConfig); + PchPrintThermalConfig (ThermalConfig); + PchPrintPmConfig (PmConfig); + PchPrintDmiConfig (DmiConfig); + PchPrintSerialIrqConfig (SerialIrqConfig); + PchPrintSerialIoConfig (SerialIoConfig); + PchPrintInterruptConfig (InterruptConfig); + PchPrintScsConfig (ScsConfig); + PchPrintIshConfig (IshConfig); + PchPrintFlashProtectionConfig (FlashProtectionConfig); + PchPrintP2sbConfig (P2sbConfig); + PchPrintEspiConfig (EspiConfig); + PchPrintCnviConfig (CnviConfig); + PchPrintHsioConfig (HsioConfig); + + DEBUG ((DEBUG_INFO, "------------------------ PCH Print Platform Protoco= l End --------------------------\n")); +DEBUG_CODE_END(); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib= /PeiPchPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchP= olicyLib/PeiPchPolicyLib.c new file mode 100644 index 0000000000..2a1da20667 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPch= PolicyLib.c @@ -0,0 +1,739 @@ +/** @file + This file is PeiPchPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyLibrary.h" +#include +#include +#include + +/** + mPxRcConfig[] table contains data for 8259 routing (how PIRQx is mapped = to IRQy). + This information is used by systems which choose to use legacy PIC + interrupt controller. Only IRQ3-7,9-12,14,15 are valid. Values from this= table + will be programmed into ITSS.PxRC registers. +**/ +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPxRcConfig[] =3D { + 11, // PARC: PIRQA -> IRQ11 + 10, // PBRC: PIRQB -> IRQ10 + 11, // PCRC: PIRQC -> IRQ11 + 11, // PDRC: PIRQD -> IRQ11 + 11, // PERC: PIRQE -> IRQ11 + 11, // PFRC: PIRQF -> IRQ11 + 11, // PGRC: PIRQG -> IRQ11 + 11 // PHRC: PIRQH -> IRQ11 +}; + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPchGeneralConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_GENERAL_CONFIG *PchGeneralConfig; + PchGeneralConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PchGeneralConfig->Header.GuidHob.Name =3D %g\n", &P= chGeneralConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PchGeneralConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", PchGeneralConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + PCH general configuration + ********************************/ +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPcieRpConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINTN Index; + PCH_PCIE_CONFIG *PcieRpConfig; + + PcieRpConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PcieRpConfig->Header.GuidHob.Name =3D %g\n", &PcieR= pConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PcieRpConfig->Header.GuidHob.Header.HobLength =3D 0= x%x\n", PcieRpConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + PCI Express related settings + ********************************/ + PcieRpConfig->RpFunctionSwap =3D TRUE; + + for (Index =3D 0; Index < GetPchMaxPciePortNum (); Index++) { + PcieRpConfig->RootPort[Index].Aspm =3D PchPcieAspmAu= toConfig; + PcieRpConfig->RootPort[Index].PmSci =3D TRUE; + PcieRpConfig->RootPort[Index].AcsEnabled =3D TRUE; + PcieRpConfig->RootPort[Index].PtmEnabled =3D TRUE; + PcieRpConfig->RootPort[Index].DpcEnabled =3D TRUE; + PcieRpConfig->RootPort[Index].RpDpcExtensionsEnabled =3D TRUE; + PcieRpConfig->RootPort[Index].MaxPayload =3D PchPcieMaxPay= load256; + PcieRpConfig->RootPort[Index].SlotImplemented =3D TRUE; + PcieRpConfig->RootPort[Index].PhysicalSlotNumber =3D (UINT8) Index; + PcieRpConfig->RootPort[Index].L1Substates =3D PchPcieL1Subs= tatesL1_1_2; + PcieRpConfig->RootPort[Index].EnableCpm =3D TRUE; + PcieRpConfig->RootPort[Index].Gen3EqPh3Method =3D PchPcieEqHard= ware; + + // + // PCIe LTR Configuration. + // + PcieRpConfig->RootPort[Index].LtrEnable =3D TRUE; + + PcieRpConfig->RootPort[Index].LtrMaxSnoopLatency =3D 0x1= 003; + PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency =3D 0x1= 003; + + PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode =3D 2; + PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier =3D 2; + PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue =3D 6= 0; + PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode =3D 2; + PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier =3D 2; + PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue =3D 6= 0; + + PcieRpConfig->RootPort[Index].Uptp =3D 5; + PcieRpConfig->RootPort[Index].Dptp =3D 7; + + PcieRpConfig->EqPh3LaneParam[Index].Cm =3D 6; + PcieRpConfig->EqPh3LaneParam[Index].Cp =3D 2; + } + + PcieRpConfig->SwEqCoeffList[0].Cm =3D 4; + PcieRpConfig->SwEqCoeffList[0].Cp =3D 8; + PcieRpConfig->SwEqCoeffList[1].Cm =3D 6; + PcieRpConfig->SwEqCoeffList[1].Cp =3D 2; + PcieRpConfig->SwEqCoeffList[2].Cm =3D 8; + PcieRpConfig->SwEqCoeffList[2].Cp =3D 6; + PcieRpConfig->SwEqCoeffList[3].Cm =3D 10; + PcieRpConfig->SwEqCoeffList[3].Cp =3D 8; + PcieRpConfig->SwEqCoeffList[4].Cm =3D 12; + PcieRpConfig->SwEqCoeffList[4].Cp =3D 2; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadSataConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINTN PortIndex; + UINTN Index; + UINT32 SataCtrlIndex; + PCH_SATA_CONFIG *SataConfig; + + SataConfig =3D (PCH_SATA_CONFIG *)ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "SataConfig->Header.GuidHob.Name =3D %g\n", &SataCon= fig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "SataConfig->Header.GuidHob.Header.HobLength =3D 0x%= x\n", SataConfig->Header.GuidHob.Header.HobLength)); + + for (SataCtrlIndex =3D 0; SataCtrlIndex < GetPchMaxSataControllerNum ();= SataCtrlIndex++, SataConfig++) { + /******************************** + SATA related settings + ********************************/ + SataConfig->Enable =3D TRUE; + SataConfig->SalpSupport =3D TRUE; + SataConfig->SataMode =3D PchSataModeAhci; + + for (PortIndex =3D 0; PortIndex < GetPchMaxSataPortNum (SataCtrlIndex)= ; PortIndex++) { + SataConfig->PortSettings[PortIndex].Enable =3D TRUE; + SataConfig->PortSettings[PortIndex].DmVal =3D 15; + SataConfig->PortSettings[PortIndex].DitoVal =3D 625; + } + + SataConfig->Rst.Raid0 =3D TRUE; + SataConfig->Rst.Raid1 =3D TRUE; + SataConfig->Rst.Raid10 =3D TRUE; + SataConfig->Rst.Raid5 =3D TRUE; + SataConfig->Rst.Irrt =3D TRUE; + SataConfig->Rst.OromUiBanner =3D TRUE; + SataConfig->Rst.OromUiDelay =3D PchSataOromDelay2sec; + SataConfig->Rst.HddUnlock =3D TRUE; + SataConfig->Rst.LedLocate =3D TRUE; + SataConfig->Rst.IrrtOnly =3D TRUE; + SataConfig->Rst.SmartStorage =3D TRUE; + SataConfig->Rst.OptaneMemory =3D TRUE; + SataConfig->Rst.CpuAttachedStorage =3D TRUE; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + SataConfig->RstPcieStorageRemap[Index].DeviceResetDelay = =3D 100; + } + + SataConfig->PwrOptEnable =3D TRUE; + SataConfig->ThermalThrottling.SuggestedSetting =3D TRUE; + } +} + +/** + Get Sata Config Policy + + @param[in] SiPolicy The RC Policy PPI instance + @param[in] SataCtrlIndex SATA controller index + + @retval SataConfig Pointer to Sata Config Policy +**/ +PCH_SATA_CONFIG * +GetPchSataConfig ( + IN SI_POLICY_PPI *SiPolicy, + IN UINT32 SataCtrlIndex + ) +{ + PCH_SATA_CONFIG *SataConfig; + EFI_STATUS Status; + + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *)= &SataConfig); + ASSERT_EFI_ERROR (Status); + + SataConfig +=3D SataCtrlIndex; + + return SataConfig; +} + +/** + Load Config block default + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadIoApicConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_IOAPIC_CONFIG *IoApicConfig; + IoApicConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "IoApicConfig->Header.GuidHob.Name =3D %g\n", &IoApi= cConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "IoApicConfig->Header.GuidHob.Header.HobLength =3D 0= x%x\n", IoApicConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + Io Apic configuration + ********************************/ + IoApicConfig->IoApicId =3D 0x02; + IoApicConfig->IoApicEntry24_119 =3D TRUE; + IoApicConfig->Enable8254ClockGating =3D TRUE; + IoApicConfig->Enable8254ClockGatingOnS3 =3D TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadDmiConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_DMI_CONFIG *DmiConfig; + DmiConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "DmiConfig->Header.GuidHob.Name =3D %g\n", &DmiConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "DmiConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", DmiConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + DMI related settings + ********************************/ + DmiConfig->DmiAspmCtrl =3D PchPcieAspmAutoConfig; +} +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadFlashProtectionConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + FlashProtectionConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.GuidHob.Name =3D %g\n= ", &FlashProtectionConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "FlashProtectionConfig->Header.GuidHob.Header.HobLen= gth =3D 0x%x\n", FlashProtectionConfig->Header.GuidHob.Header.HobLength)); +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadHdAudioConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_HDAUDIO_CONFIG *HdAudioConfig; + HdAudioConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "HdAudioConfig->Header.GuidHob.Name =3D %g\n", &HdAu= dioConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "HdAudioConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", HdAudioConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + HD-Audio configuration + ********************************/ + HdAudioConfig->DspEnable =3D TRUE; + HdAudioConfig->HdAudioLinkFrequency =3D PchHdaLinkFreq24MHz; + HdAudioConfig->IDispLinkFrequency =3D PchHdaLinkFreq96MHz; + HdAudioConfig->IDispLinkTmode =3D PchHdaIDispMode2T; + HdAudioConfig->ResetWaitTimer =3D 600; // Must be at least 521us (= 25 frames) + HdAudioConfig->AudioLinkHda =3D TRUE; + HdAudioConfig->AudioLinkDmic0 =3D TRUE; + HdAudioConfig->AudioLinkDmic1 =3D TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadInterruptConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_INTERRUPT_CONFIG *InterruptConfig; + InterruptConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "InterruptConfig->Header.GuidHob.Name =3D %g\n", &In= terruptConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "InterruptConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", InterruptConfig->Header.GuidHob.Header.HobLength)); + + LoadDeviceInterruptConfig (InterruptConfig); + + ASSERT ((sizeof (mPxRcConfig) / sizeof (UINT8)) <=3D PCH_MAX_PXRC_CONFIG= ); + CopyMem ( + InterruptConfig->PxRcConfig, + mPxRcConfig, + sizeof (mPxRcConfig) + ); + + InterruptConfig->GpioIrqRoute =3D 14; + InterruptConfig->SciIrqSelect =3D 9; + InterruptConfig->TcoIrqSelect =3D 9; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadIshConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_ISH_CONFIG *IshConfig; + IshConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "IshConfig->Header.GuidHob.Name =3D %g\n", &IshConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "IshConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", IshConfig->Header.GuidHob.Header.HobLength)); +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadLanConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_LAN_CONFIG *LanConfig; + UINT16 LpcDid; + + LanConfig =3D ConfigBlockPointer; + LpcDid =3D PchGetLpcDid (); + + DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Name =3D %g\n", &LanConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", LanConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + Lan configuration + ********************************/ + LanConfig->Enable =3D TRUE; + LanConfig->LtrEnable =3D TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadLockDownConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + LockDownConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "LockDownConfig->Header.GuidHob.Name =3D %g\n", &Loc= kDownConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "LockDownConfig->Header.GuidHob.Header.HobLength =3D= 0x%x\n", LockDownConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + Lockdown configuration + ********************************/ + LockDownConfig->GlobalSmi =3D TRUE; + LockDownConfig->BiosInterface =3D TRUE; + LockDownConfig->RtcMemoryLock =3D TRUE; + LockDownConfig->BiosLock =3D TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadP2sbConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_P2SB_CONFIG *P2sbConfig; + P2sbConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "P2sbConfig->Header.GuidHob.Name =3D %g\n", &P2sbCon= fig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "P2sbConfig->Header.GuidHob.Header.HobLength =3D 0x%= x\n", P2sbConfig->Header.GuidHob.Header.HobLength)); +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPmConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_PM_CONFIG *PmConfig; + PmConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PmConfig->Header.GuidHob.Name =3D %g\n", &PmConfig-= >Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PmConfig->Header.GuidHob.Header.HobLength =3D 0x%x\= n", PmConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + MiscPm Configuration + ********************************/ + PmConfig->MeWakeSts =3D TRUE; + PmConfig->WolOvrWkSts =3D TRUE; + + PmConfig->WakeConfig.WolEnableOverride =3D TRUE; + PmConfig->WakeConfig.LanWakeFromDeepSx =3D TRUE; + + PmConfig->PchSlpS3MinAssert =3D PchSlpS350ms; + PmConfig->PchSlpS4MinAssert =3D PchSlpS41s; + PmConfig->PchSlpSusMinAssert =3D PchSlpSus4s; + PmConfig->PchSlpAMinAssert =3D PchSlpA2s; + + PmConfig->SlpLanLowDc =3D TRUE; + PmConfig->PciePllSsc =3D 0xFF; + PmConfig->LpcClockRun =3D TRUE; + PmConfig->SlpS0Enable =3D TRUE; + PmConfig->CpuC10GatePinEnable =3D TRUE; + if (IsWhlCpu () && (GetCpuStepping () =3D=3D EnumCflV0)) { + PmConfig->SlpS0WithGbeSupport =3D FALSE; + } else { + PmConfig->SlpS0WithGbeSupport =3D TRUE; + } + + if (IsPchLp ()) { + PmConfig->ModPhySusPgEnable =3D TRUE; + } +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadScsConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_SCS_CONFIG *ScsConfig; + ScsConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "ScsConfig->Header.GuidHob.Name =3D %g\n", &ScsConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "ScsConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", ScsConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + SCS Configuration + ********************************/ + ScsConfig->ScsEmmcEnabled =3D IsPchLp () ? TRUE : FALSE; // eMMC prese= nt on PCH-LP only + ScsConfig->ScsEmmcHs400DriverStrength =3D DriverStrength40Ohm; + //Enable Sd Card controller for Non-Desktop sku platforms + if (GetCpuSku () !=3D EnumCpuTrad) { + ScsConfig->ScsSdcardEnabled =3D TRUE; + } + ScsConfig->SdCardPowerEnableActiveHigh =3D TRUE; + ScsConfig->ScsUfsEnabled =3D TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadSerialIoConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINTN Index; + PCH_SERIAL_IO_CONFIG *SerialIoConfig; + SerialIoConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "SerialIoConfig->Header.GuidHob.Name =3D %g\n", &Ser= ialIoConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "SerialIoConfig->Header.GuidHob.Header.HobLength =3D= 0x%x\n", SerialIoConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + SerialIo Configuration + ********************************/ + for (Index =3D 0; Index < GetPchMaxSerialIoControllersNum (); Index++) { + SerialIoConfig->DevMode[Index] =3D PchSerialIoPci; + } + SerialIoConfig->DebugUartNumber =3D PcdGet8 (PcdSerialIoUartNum= ber); +} +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadSerialIrqConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; + SerialIrqConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.GuidHob.Name =3D %g\n", &Se= rialIrqConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "SerialIrqConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", SerialIrqConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + Serial IRQ Configuration + ********************************/ + SerialIrqConfig->SirqEnable =3D TRUE; + SerialIrqConfig->SirqMode =3D PchQuietMode; + SerialIrqConfig->StartFramePulse =3D PchSfpw4Clk; +} +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadThermalConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_THERMAL_CONFIG *ThermalConfig; + ThermalConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "ThermalConfig->Header.GuidHob.Name =3D %g\n", &Ther= malConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "ThermalConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", ThermalConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + Thermal configuration. + ********************************/ + ThermalConfig->TsmicLock =3D TRUE; + ThermalConfig->PchHotLevel =3D 0x154; + ThermalConfig->TTLevels.SuggestedSetting =3D TRUE; + ThermalConfig->TTLevels.PchCrossThrottling =3D TRUE; + ThermalConfig->DmiHaAWC.SuggestedSetting =3D TRUE; + + ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioC].PmsyncEnable = =3D TRUE; + ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioC].C0TransmitEnab= le =3D TRUE; + ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioD].PmsyncEnable = =3D TRUE; + ThermalConfig->MemoryThrottling.TsGpioPinSetting[TsGpioD].C0TransmitEnab= le =3D TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadUsbConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINTN PortIndex; + USB_CONFIG *UsbConfig; + UsbConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "UsbConfig->Header.GuidHob.Name =3D %g\n", &UsbConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "UsbConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", UsbConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + USB related configuration + ********************************/ + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex= ++) { + UsbConfig->PortUsb20[PortIndex].Enable =3D TRUE; + } + + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex= ++) { + UsbConfig->PortUsb30[PortIndex].Enable =3D TRUE; + } + + // + // BIOS should program PDO in PEI phase by default + // + UsbConfig->PdoProgramming =3D TRUE; + + // + // Default values of USB2 AFE settings. + // + UsbConfig->Usb2PhySusPgEnable =3D TRUE; + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb2PortNum (); PortIndex= ++) { + UsbConfig->PortUsb20[PortIndex].Afe.Petxiset =3D 3; + UsbConfig->PortUsb20[PortIndex].Afe.Txiset =3D 2; + UsbConfig->PortUsb20[PortIndex].Afe.Predeemp =3D 1; + UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit =3D 1; + } + + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex= ++) { + UsbConfig->PortUsb30HsioRx[PortIndex].HsioOlfpsCfgPullUpDwnRes =3D 3; + } + + UsbConfig->XhciOcLock =3D TRUE; + + // + // xDCI configuration + // + UsbConfig->XdciConfig.Enable =3D FALSE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadEspiConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_ESPI_CONFIG *EspiConfig; + EspiConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "EspiConfig->Header.GuidHob.Name =3D %g\n", &EspiCon= fig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "EspiConfig->Header.GuidHob.Header.HobLength =3D 0x%= x\n", EspiConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + Espi configuration. + ********************************/ + EspiConfig->BmeMasterSlaveEnabled =3D TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadCnviConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_CNVI_CONFIG *CnviConfig; + CnviConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "CnviConfig->Header.GuidHob.Name =3D %g\n", &CnviCon= fig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "CnviConfig->Header.GuidHob.Header.HobLength =3D 0x%= x\n", CnviConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + Cnvi configuration. + ********************************/ + CnviConfig->Mode =3D CnviModeAuto; // Automatic detection +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadHsioConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_HSIO_CONFIG *HsioConfig; + HsioConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "HsioConfig->Header.GuidHob.Name =3D %g\n", &HsioCon= fig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "HsioConfig->Header.GuidHob.Header.HobLength =3D 0x%= x\n", HsioConfig->Header.GuidHob.Header.HobLength)); +} + +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mPchIpBlocks [] =3D { + {&gPchGeneralConfigGuid, sizeof (PCH_GENERAL_CONFIG), PC= H_GENERAL_CONFIG_REVISION, LoadPchGeneralConfigDefault}, + {&gPcieRpConfigGuid, sizeof (PCH_PCIE_CONFIG), PC= IE_RP_CONFIG_REVISION, LoadPcieRpConfigDefault}, + {&gSataConfigGuid, sizeof (PCH_SATA_CONFIG), SA= TA_CONFIG_REVISION, LoadSataConfigDefault}, + {&gIoApicConfigGuid, sizeof (PCH_IOAPIC_CONFIG), IO= APIC_CONFIG_REVISION, LoadIoApicConfigDefault}, + {&gDmiConfigGuid, sizeof (PCH_DMI_CONFIG), DM= I_CONFIG_REVISION, LoadDmiConfigDefault}, + {&gFlashProtectionConfigGuid, sizeof (PCH_FLASH_PROTECTION_CONFIG), FL= ASH_PROTECTION_CONFIG_REVISION, LoadFlashProtectionConfigDefault}, + {&gHdAudioConfigGuid, sizeof (PCH_HDAUDIO_CONFIG), HD= AUDIO_CONFIG_REVISION, LoadHdAudioConfigDefault}, + {&gInterruptConfigGuid, sizeof (PCH_INTERRUPT_CONFIG), IN= TERRUPT_CONFIG_REVISION, LoadInterruptConfigDefault}, + {&gIshConfigGuid, sizeof (PCH_ISH_CONFIG), IS= H_CONFIG_REVISION, LoadIshConfigDefault}, + {&gLanConfigGuid, sizeof (PCH_LAN_CONFIG), LA= N_CONFIG_REVISION, LoadLanConfigDefault}, + {&gLockDownConfigGuid, sizeof (PCH_LOCK_DOWN_CONFIG), LO= CK_DOWN_CONFIG_REVISION, LoadLockDownConfigDefault}, + {&gP2sbConfigGuid, sizeof (PCH_P2SB_CONFIG), P2= SB_CONFIG_REVISION, LoadP2sbConfigDefault}, + {&gPmConfigGuid, sizeof (PCH_PM_CONFIG), PM= _CONFIG_REVISION, LoadPmConfigDefault}, + {&gScsConfigGuid, sizeof (PCH_SCS_CONFIG), SC= S_CONFIG_REVISION, LoadScsConfigDefault}, + {&gSerialIoConfigGuid, sizeof (PCH_SERIAL_IO_CONFIG), SE= RIAL_IO_CONFIG_REVISION, LoadSerialIoConfigDefault}, + {&gSerialIrqConfigGuid, sizeof (PCH_LPC_SIRQ_CONFIG), SE= RIAL_IRQ_CONFIG_REVISION, LoadSerialIrqConfigDefault}, + {&gThermalConfigGuid, sizeof (PCH_THERMAL_CONFIG), TH= ERMAL_CONFIG_REVISION, LoadThermalConfigDefault}, + {&gUsbConfigGuid, sizeof (USB_CONFIG), US= B_CONFIG_REVISION, LoadUsbConfigDefault}, + {&gEspiConfigGuid, sizeof (PCH_ESPI_CONFIG), ES= PI_CONFIG_REVISION, LoadEspiConfigDefault}, + {&gCnviConfigGuid, sizeof (PCH_CNVI_CONFIG), CN= VI_CONFIG_REVISION, LoadCnviConfigDefault}, + {&gHsioConfigGuid, sizeof (PCH_HSIO_CONFIG), HS= IO_CONFIG_REVISION, LoadHsioConfigDefault}, +}; + +/** + Get PCH config block table total size. + + @retval Size of PCH config block table +**/ +UINT16 +EFIAPI +PchGetConfigBlockTotalSize ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mPchIpBlocks[0], sizeof (mPchI= pBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + PchAddConfigBlocks add all PCH config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add PCH config bloc= ks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +PchAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + DEBUG ((DEBUG_INFO, "PCH AddConfigBlocks\n")); + + return AddComponentConfigBlocks (ConfigBlockTableAddress, &mPchIpBlocks[= 0], sizeof (mPchIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib= /PeiPchPolicyLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiP= chPolicyLib/PeiPchPolicyLibCnl.c new file mode 100644 index 0000000000..d19692ff2c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPch= PolicyLibCnl.c @@ -0,0 +1,169 @@ +/** @file + This file is PeiPchPolicy library Cannon Lake specific. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyLibrary.h" +#include +#include + +/** + mDevIntConfig[] table contains data on INTx and IRQ for each device. + IRQ value for devices which use ITSS INTx->PIRQx mapping need to be set = in a way + that for each multifunctional Dxx:Fy same interrupt pins must map to the= same IRQ. + Those IRQ values will be used to update ITSS.PIRx register. + In APIC relationship between PIRQs and IRQs is: + PIRQA -> IRQ16 + PIRQB -> IRQ17 + PIRQC -> IRQ18 + PIRQD -> IRQ19 + PIRQE -> IRQ20 + PIRQF -> IRQ21 + PIRQG -> IRQ22 + PIRQH -> IRQ23 + + Devices which use INTx->PIRQy mapping are: cAVS(in PCI mode), SMBus, GbE= , TraceHub, PCIe, + SATA, HECI, IDE-R, KT Redirection, xHCI, Thermal Subsystem, Camera IO Ho= st Controller + + PCI Express Root Ports mapping should be programmed only with values as = in below table (D27/28/29) + otherwise _PRT methods in ACPI for RootPorts would require additional pa= tching as + PCIe Endpoint Device Interrupt is further subjected to INTx to PIRQy Map= ping + + Configured IRQ values are not used if an OS chooses to be in PIC instead= of APIC mode +**/ +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mDevIntConfig[] = =3D { +// {31, 0, PchNoInt, 0}, // LPC/eSPI Interface, doesn't use interrupts +// {31, 1, PchNoInt, 0}, // P2SB, doesn't use interrupts +// {31, 2, PchNoInt, 0}, // PMC , doesn't use interrupts + {31, 3, PchIntA, 16}, // cAVS(Audio, Voice, Speach), INTA is default, pr= ogrammed in PciCfgSpace 3Dh + {31, 4, PchIntA, 16}, // SMBus Controller, no default value, programmed = in PciCfgSpace 3Dh +// {31, 5, PchNoInt, 0}, // SPI , doesn't use interrupts + {31, 7, PchIntA, 16}, // TraceHub, INTA is default, RO register + {30, 0, PchIntA, 20}, // SerialIo: UART #0, INTA is default, programmed = in PCR[SERIALIO] + PCICFGCTRL[7] + {30, 1, PchIntB, 21}, // SerialIo: UART #1, INTA is default, programmed = in PCR[SERIALIO] + PCICFGCTRL[8] + {30, 2, PchIntC, 22}, // SerialIo: SPI #0, INTA is default, programmed i= n PCR[SERIALIO] + PCICFGCTRL[10] + {30, 3, PchIntD, 23}, // SerialIo: SPI #1, INTA is default, programmed i= n PCR[SERIALIO] + PCICFGCTRL[11] + {28, 0, PchIntA, 16}, // PCI Express Port 1, INT is default, programmed = in PciCfgSpace + FCh + {28, 1, PchIntB, 17}, // PCI Express Port 2, INT is default, programmed = in PciCfgSpace + FCh + {28, 2, PchIntC, 18}, // PCI Express Port 3, INT is default, programmed = in PciCfgSpace + FCh + {28, 3, PchIntD, 19}, // PCI Express Port 4, INT is default, programmed = in PciCfgSpace + FCh + {28, 4, PchIntA, 16}, // PCI Express Port 5, INT is default, programmed = in PciCfgSpace + FCh + {28, 5, PchIntB, 17}, // PCI Express Port 6, INT is default, programmed = in PciCfgSpace + FCh + {28, 6, PchIntC, 18}, // PCI Express Port 7, INT is default, programmed = in PciCfgSpace + FCh + {28, 7, PchIntD, 19}, // PCI Express Port 8, INT is default, programmed = in PciCfgSpace + FCh + {25, 2, PchIntC, 34}, // SerialIo UART Controller #2, INTA is default, p= rogrammed in PCR[SERIALIO] + PCICFGCTRL[9] +// {24, 0, 0, 0}, // Reserved (used by RST PCIe Storage Cycle Router) + {23, 0, PchIntA, 16}, // SATA Controller, INTA is default, programmed in= PciCfgSpace + 3Dh + {22, 0, PchIntA, 16}, // CSME: HECI #1 + {22, 1, PchIntB, 17}, // CSME: HECI #2 + {22, 4, PchIntA, 16}, // CSME: HECI #3 +// {22, 7, PchNoInt, 0}, // CSME: WLAN + {21, 0, PchIntA, 16}, // SerialIo I2C Controller #0, INTA is default, pr= ogrammed in PCR[SERIALIO] + PCICFGCTRL[1] + {21, 1, PchIntB, 17}, // SerialIo I2C Controller #1, INTA is default, pr= ogrammed in PCR[SERIALIO] + PCICFGCTRL[2] + {21, 2, PchIntC, 18}, // SerialIo I2C Controller #2, INTA is default, pr= ogrammed in PCR[SERIALIO] + PCICFGCTRL[3] + {21, 3, PchIntD, 19}, // SerialIo I2C Controller #3, INTA is default, pr= ogrammed in PCR[SERIALIO] + PCICFGCTRL[4] + {20, 0, PchIntA, 16}, // USB 3.0 xHCI Controller, no default value, prog= rammed in PciCfgSpace 3Dh + {20, 1, PchIntB, 17}, // USB Device Controller (OTG) + //{20, 2, PchNoInt, 0}, // Shared SRAM, no interrupts + {20, 3, PchIntA, 16}, // CNVi WiFir +// {20, 4, 0, 0}, // TraceHub Phantom (ACPI) Function + {20, 5, PchIntD, 19}, // SCS: SDCard +// {18, 0, PchNoInt, 0}, // CSME: KVMcc, doesn't use interrupts +// {18, 1, PchNoInt, 0}, // CSME: Clink, doesn't use interrupts +// {18, 2, PchNoInt, 0}, // CSME: PMT, doesn't use interrupts +// {18, 3, 0, 0}, // CSME: CSE UMA +// {18, 4, 0, 0} // CSME: fTPM DMA + {18, 5, PchIntA, 16} // SCS: UFS +}; + +// +// mCnlPchLpOnlyDevIntConfig[] table contains data on INTx and IRQ for dev= ices that exist on PCH-LP +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mPchLpOnlyDevInt= Config[] =3D { + {31, 6, PchIntA, 16}, // GbE Controller, INTA is default, programmed in = PciCfgSpace 3Dh + {29, 0, PchIntA, 16}, // PCI Express Port 9, INT is default, programmed = in PciCfgSpace + FCh + {29, 1, PchIntB, 17}, // PCI Express Port 10, INT is default, programmed= in PciCfgSpace + FCh + {29, 2, PchIntC, 18}, // PCI Express Port 11, INT is default, programmed= in PciCfgSpace + FCh + {29, 3, PchIntD, 19}, // PCI Express Port 12, INT is default, programmed= in PciCfgSpace + FCh + {29, 4, PchIntA, 16}, // PCI Express Port 13, INT is default, programmed= in PciCfgSpace + FCh + {29, 5, PchIntB, 17}, // PCI Express Port 14, INT is default, programmed= in PciCfgSpace + FCh + {29, 6, PchIntC, 18}, // PCI Express Port 15, INT is default, programmed= in PciCfgSpace + FCh + {29, 7, PchIntD, 19}, // PCI Express Port 16, INT is default, programmed= in PciCfgSpace + FCh + {26, 0, PchIntA, 16}, // SCS: eMMC + {25, 0, PchIntA, 32}, // SerialIo I2C Controller #4, INTA is default, pr= ogrammed in PCR[SERIALIO] + PCICFGCTRL[5] + {25, 1, PchIntB, 33}, // SerialIo I2C Controller #5, INTA is default, pr= ogrammed in PCR[SERIALIO] + PCICFGCTRL[6] + {22, 2, PchIntC, 18}, // CSME: IDE-Redirection (IDE-R) + {22, 3, PchIntD, 19}, // CSME: Keyboard and Text (KT) Redirection + {19, 0, PchIntA, 20}, // Integrated Sensor Hub + {18, 0, PchIntA, 16}, // Thermal Subsystem + {18, 6, PchIntB, 24} // SerialIo: SPI #2, INTA is default, programmed i= n PCR[SERIALIO] + PCICFGCTRL[12] +}; + +// +// mPchHOnlyDevIntConfig[] table contains data on INTx and IRQ for devices= that exist on PCH-H +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_DEVICE_INTERRUPT_CONFIG mPchHOnlyDevIntC= onfig[] =3D { + {31, 6, PchIntA, 16}, // GbE Controller, INTA is default, programmed in = PciCfgSpace 3Dh + {29, 0, PchIntA, 16}, // PCI Express Port 9, INT is default, programmed = in PciCfgSpace + FCh + {29, 1, PchIntB, 17}, // PCI Express Port 10, INT is default, programmed= in PciCfgSpace + FCh + {29, 2, PchIntC, 18}, // PCI Express Port 11, INT is default, programmed= in PciCfgSpace + FCh + {29, 3, PchIntD, 19}, // PCI Express Port 12, INT is default, programmed= in PciCfgSpace + FCh + {29, 4, PchIntA, 16}, // PCI Express Port 13, INT is default, programmed= in PciCfgSpace + FCh + {29, 5, PchIntB, 17}, // PCI Express Port 14, INT is default, programmed= in PciCfgSpace + FCh + {29, 6, PchIntC, 18}, // PCI Express Port 15, INT is default, programmed= in PciCfgSpace + FCh + {29, 7, PchIntD, 19}, // PCI Express Port 16, INT is default, programmed= in PciCfgSpace + FCh + {27, 0, PchIntA, 16}, // PCI Express Port 17, INT is default, programmed= in PciCfgSpace + FCh + {27, 1, PchIntB, 17}, // PCI Express Port 18, INT is default, programmed= in PciCfgSpace + FCh + {27, 2, PchIntC, 18}, // PCI Express Port 19, INT is default, programmed= in PciCfgSpace + FCh + {27, 3, PchIntD, 19}, // PCI Express Port 20, INT is default, programmed= in PciCfgSpace + FCh + {27, 4, PchIntA, 16}, // PCI Express Port 21 + {27, 5, PchIntB, 17}, // PCI Express Port 22 + {27, 6, PchIntC, 18}, // PCI Express Port 23 + {27, 7, PchIntD, 19}, // PCI Express Port 24 + {22, 2, PchIntC, 18}, // CSME: IDE-Redirection (IDE-R) + {22, 3, PchIntD, 19}, // CSME: Keyboard and Text (KT) Redirection + {19, 0, PchIntA, 20}, // Integrated Sensor Hub + {18, 0, PchIntA, 16}, // Thermal Subsystem + {18, 6, PchIntB, 24} // SerialIo: SPI #2, INTA is default, programmed i= n PCR[SERIALIO] + PCICFGCTRL[12] +}; + +/** + Adds interrupt configuration for device + + @param[in/out] InterruptConfig Pointer to interrupt config +**/ +VOID +LoadDeviceInterruptConfig ( + IN OUT PCH_INTERRUPT_CONFIG *InterruptConfig + ) +{ + UINT8 IntConfigTableEntries; + + IntConfigTableEntries =3D ARRAY_SIZE (mDevIntConfig); + ASSERT (IntConfigTableEntries <=3D PCH_MAX_DEVICE_INTERRUPT_CONFIG); + InterruptConfig->NumOfDevIntConfig =3D IntConfigTableEntries; + CopyMem ( + InterruptConfig->DevIntConfig, + mDevIntConfig, + sizeof (mDevIntConfig) + ); + + if (IsPchLp ()) { + CopyMem ( + &(InterruptConfig->DevIntConfig[InterruptConfig->NumOfDevIntConfig]), + mPchLpOnlyDevIntConfig, + sizeof (mPchLpOnlyDevIntConfig) + ); + InterruptConfig->NumOfDevIntConfig +=3D ARRAY_SIZE (mPchLpOnlyDevIntCo= nfig); + } else if (IsPchH ()) { + CopyMem ( + &(InterruptConfig->DevIntConfig[InterruptConfig->NumOfDevIntConfig]), + mPchHOnlyDevIntConfig, + sizeof (mPchHOnlyDevIntConfig) + ); + InterruptConfig->NumOfDevIntConfig +=3D ARRAY_SIZE (mPchHOnlyDevIntCon= fig); + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib= /PeiPchPreMemPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/P= eiPchPolicyLib/PeiPchPreMemPolicyLib.c new file mode 100644 index 0000000000..dfab5d29c2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPch= PreMemPolicyLib.c @@ -0,0 +1,318 @@ +/** @file + This file is PeiPchPreMemPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyLibrary.h" +#include + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPchGeneralPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + PchGeneralPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PchGeneralPreMemConfig->Header.GuidHob.Name =3D %g\= n", &PchGeneralPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PchGeneralPreMemConfig->Header.GuidHob.Header.HobLe= ngth =3D 0x%x\n", PchGeneralPreMemConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + PCH general premem configuration + ********************************/ +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadDciPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; + DciPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "DciPreMemConfig->Header.GuidHob.Name =3D %g\n", &Dc= iPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "DciPreMemConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", DciPreMemConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + DCI Configuration + ********************************/ +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadWatchDogPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig; + WdtPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "WdtPreMemConfig->Header.GuidHob.Name =3D %g\n", &Wd= tPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "WdtPreMemConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", WdtPreMemConfig->Header.GuidHob.Header.HobLength)); +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPchTraceHubPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig; + PchTraceHubPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PchTraceHubPreMemConfig->Header.GuidHob.Name =3D %g= \n", &PchTraceHubPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PchTraceHubPreMemConfig->Header.GuidHob.Header.HobL= ength =3D 0x%x\n", PchTraceHubPreMemConfig->Header.GuidHob.Header.HobLength= )); +} + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusRsvdAddresses[] =3D { + 0xA0, + 0xA2, + 0xA4, + 0xA6 +}; + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadSmbusPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; + SmbusPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "SmbusPreMemConfig->Header.GuidHob.Name =3D %g\n", &= SmbusPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "SmbusPreMemConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", SmbusPreMemConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + SMBus configuration + ********************************/ + SmbusPreMemConfig->Enable =3D TRUE; + SmbusPreMemConfig->DynamicPowerGating =3D TRUE; + SmbusPreMemConfig->SpdWriteDisable =3D TRUE; + SmbusPreMemConfig->SmbusIoBase =3D PcdGet16 (PcdSmbusBaseAddre= ss); + ASSERT (sizeof (mSmbusRsvdAddresses) <=3D PCH_MAX_SMBUS_RESERVED_ADDRESS= ); + SmbusPreMemConfig->NumRsvdSmbusAddresses =3D sizeof (mSmbusRsvdAddresses= ); + CopyMem ( + SmbusPreMemConfig->RsvdSmbusAddressTable, + mSmbusRsvdAddresses, + sizeof (mSmbusRsvdAddresses) + ); +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadLpcPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; + LpcPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "LpcPreMemConfig->Header.GuidHob.Name =3D %g\n", &Lp= cPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "LpcPreMemConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", LpcPreMemConfig->Header.GuidHob.Header.HobLength)); + + /******************************** + LPC Configuration + ********************************/ + LpcPreMemConfig->EnhancePort8xhDecoding =3D TRUE; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadHsioPciePreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + HsioPciePreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "HsioPciePreMemConfig->Header.GuidHob.Name =3D %g\n"= , &HsioPciePreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "HsioPciePreMemConfig->Header.GuidHob.Header.HobLeng= th =3D 0x%x\n", HsioPciePreMemConfig->Header.GuidHob.Header.HobLength)); +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadHsioSataPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + HsioSataPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "HsioSataPreMemConfig->Header.GuidHob.Name =3D %g\n"= , &HsioSataPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "HsioSataPreMemConfig->Header.GuidHob.Header.HobLeng= th =3D 0x%x\n", HsioSataPreMemConfig->Header.GuidHob.Header.HobLength)); +} + +/** + Get Hsio Sata Pre Mem Config Policy + + @param[in] SiPolicy The RC Policy PPI instance + @param[in] SataCtrlIndex SATA controller index + + @retval Pointer to Hsio Sata Pre Mem Config Policy +**/ +PCH_HSIO_SATA_PREMEM_CONFIG * +GetPchHsioSataPreMemConfig ( + IN SI_PREMEM_POLICY_PPI *SiPreMemPolicy, + IN UINT32 SataCtrlIndex + ) +{ + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + EFI_STATUS Status; + + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConf= igGuid, (VOID *) &HsioSataPreMemConfig); + ASSERT_EFI_ERROR (Status); + + HsioSataPreMemConfig +=3D SataCtrlIndex; + + return HsioSataPreMemConfig; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadPcieRpPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; + UINT32 RpIndex; + + PcieRpPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PcieRpPreMemConfig->Header.GuidHob.Name =3D %g\n", = &PcieRpPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PcieRpPreMemConfig->Header.GuidHob.Header.HobLength= =3D 0x%x\n", PcieRpPreMemConfig->Header.GuidHob.Header.HobLength)); + + for (RpIndex =3D 0; RpIndex < GetPchMaxPciePortNum (); RpIndex ++) { + PcieRpPreMemConfig->RpEnabledMask |=3D (UINT32) (1 << RpIndex); + } +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadHdAudioPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; + HdaPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PcieRpPreMemConfig->Header.GuidHob.Name =3D %g\n", = &HdaPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PcieRpPreMemConfig->Header.GuidHob.Header.HobLength= =3D 0x%x\n", HdaPreMemConfig->Header.GuidHob.Header.HobLength)); + HdaPreMemConfig->Enable =3D 1; +} + +/** + Load Config block default + + @param[in] ConfigBlockPointer Pointer to config block +**/ +VOID +LoadIshPreMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + PCH_ISH_PREMEM_CONFIG *IshPreMemConfig; + IshPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "PcieRpPreMemConfig->Header.GuidHob.Name =3D %g\n", = &IshPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PcieRpPreMemConfig->Header.GuidHob.Header.HobLength= =3D 0x%x\n", IshPreMemConfig->Header.GuidHob.Header.HobLength)); + //Enable ISH controller for Non-Desktop sku platforms + if (GetCpuSku () !=3D EnumCpuTrad) { + IshPreMemConfig->Enable =3D TRUE; + } +} + + +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mPchIpBlocksPreMem []= =3D { + {&gPchGeneralPreMemConfigGuid, sizeof (PCH_GENERAL_PREMEM_CONFIG), = PCH_GENERAL_PREMEM_CONFIG_REVISION, LoadPchGeneralPreMemConfigDefa= ult}, + {&gDciPreMemConfigGuid, sizeof (PCH_DCI_PREMEM_CONFIG), = DCI_PREMEM_CONFIG_REVISION, LoadDciPreMemConfigDefault}, + {&gWatchDogPreMemConfigGuid, sizeof (PCH_WDT_PREMEM_CONFIG), = WATCH_DOG_PREMEM_CONFIG_REVISION, LoadWatchDogPreMemConfigDefaul= t}, + {&gPchTraceHubPreMemConfigGuid, sizeof (PCH_TRACE_HUB_PREMEM_CONFIG),= PCH_TRACEHUB_PREMEM_CONFIG_REVISION, LoadPchTraceHubPreMemConfigDef= ault}, + {&gSmbusPreMemConfigGuid, sizeof (PCH_SMBUS_PREMEM_CONFIG), = SMBUS_PREMEM_CONFIG_REVISION, LoadSmbusPreMemConfigDefault}, + {&gLpcPreMemConfigGuid, sizeof (PCH_LPC_PREMEM_CONFIG), = LPC_PREMEM_CONFIG_REVISION, LoadLpcPreMemConfigDefault}, + {&gHsioPciePreMemConfigGuid, sizeof (PCH_HSIO_PCIE_PREMEM_CONFIG),= HSIO_PCIE_PREMEM_CONFIG_REVISION, LoadHsioPciePreMemConfigDefaul= t}, + {&gHsioSataPreMemConfigGuid, sizeof (PCH_HSIO_SATA_PREMEM_CONFIG),= HSIO_SATA_PREMEM_CONFIG_REVISION, LoadHsioSataPreMemConfigDefaul= t}, + {&gPcieRpPreMemConfigGuid, sizeof (PCH_PCIE_RP_PREMEM_CONFIG), = PCIE_RP_PREMEM_CONFIG_REVISION, LoadPcieRpPreMemConfigDefault}, + {&gHdAudioPreMemConfigGuid, sizeof (PCH_HDAUDIO_PREMEM_CONFIG), = HDAUDIO_PREMEM_CONFIG_REVISION, LoadHdAudioPreMemConfigDefault= }, + {&gIshPreMemConfigGuid, sizeof (PCH_ISH_PREMEM_CONFIG), = ISH_PREMEM_CONFIG_REVISION, LoadIshPreMemConfigDefault}, +}; + +/** + Get PCH PREMEM config block table total size. + + @retval Size of PCH PREMEM config block ta= ble +**/ +UINT16 +EFIAPI +PchGetPreMemConfigBlockTotalSize ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mPchIpBlocksPreMem[0], sizeof = (mPchIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + PchAddPreMemConfigBlocks add all PCH PREMEM config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add PCH PREMEM conf= ig blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +PchAddPreMemConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + DEBUG ((DEBUG_INFO, "PCH AddPreMemConfigBlocks\n")); + + return AddComponentConfigBlocks (ConfigBlockTableAddress, &mPchIpBlocksP= reMem[0], sizeof (mPchIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY)); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchResetLib/= PchReset.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchResetLib/= PchReset.c new file mode 100644 index 0000000000..2210344462 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchResetLib/PchRese= t.c @@ -0,0 +1,109 @@ +/** @file + PCH RESET PEIM DRIVER. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + + +/** + Resets the entire platform. + + @param[in] ResetType UEFI defined reset type. + @param[in] ResetStatus The status code for the reset. + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + +**/ +VOID +EFIAPI +ResetSystem ( + IN EFI_RESET_TYPE ResetType, + IN EFI_STATUS ResetStatus, + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + switch (ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + return; + + case EfiResetPlatformSpecific: + ResetPlatformSpecific (DataSize, ResetData); + return; + + default: + return; + } + + // + // Given we should have reset getting here would be bad + // + ASSERT (FALSE); + CpuDeadLoop(); +} + +/** + Initialize PCH Reset APIs + + @retval EFI_SUCCESS APIs are installed successfully + @retval EFI_OUT_OF_RESOURCES Can't allocate pool +**/ +EFI_STATUS +EFIAPI +PchInitializeReset ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_RESET2_PPI *EfiPeiReset2Ppi; + EFI_PEI_PPI_DESCRIPTOR *EfiPeiReset2Descriptor; + + DEBUG ((DEBUG_INFO, "PchInitializeReset() Start\n")); + + + EfiPeiReset2Descriptor =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (= sizeof (EFI_PEI_PPI_DESCRIPTOR)); + EfiPeiReset2Ppi =3D (EFI_PEI_RESET2_PPI *) AllocateZeroPool (sizeof (EFI= _PEI_RESET2_PPI)); + if ((EfiPeiReset2Descriptor =3D=3D NULL) || + (EfiPeiReset2Ppi =3D=3D NULL)) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + /// + /// Initialize the EFI Reset2 ppi instance + /// + EfiPeiReset2Ppi->ResetSystem =3D ResetSystem; + + EfiPeiReset2Descriptor->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_P= PI_DESCRIPTOR_TERMINATE_LIST; + EfiPeiReset2Descriptor->Guid =3D &gEfiPeiReset2PpiGuid; + EfiPeiReset2Descriptor->Ppi =3D EfiPeiReset2Ppi; + + Status =3D PeiServicesInstallPpi (EfiPeiReset2Descriptor); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "PchInitializeReset() End\n")); + + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiResetSystemL= ib/PeiResetSystemLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pei= ResetSystemLib/PeiResetSystemLib.c new file mode 100644 index 0000000000..58f2d86103 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiResetSystemLib/PeiR= esetSystemLib.c @@ -0,0 +1,257 @@ +/** @file + System reset library services. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Dump reset message for debug build readability +**/ +VOID +DumpResetMessage ( + VOID + ) +{ + DEBUG_CODE_BEGIN (); + UINTN Index; + // + // ****************************** + // ** SYSTEM REBOOT !!! ** + // ****************************** + // + for (Index =3D 0; Index < 30; Index++) { + DEBUG ((DEBUG_INFO, "*")); + } + DEBUG ((DEBUG_INFO, "\n** SYSTEM REBOOT !!! **\n")); + for (Index =3D 0; Index < 30; Index++) { + DEBUG ((DEBUG_INFO, "*")); + } + DEBUG ((DEBUG_INFO, "\n")); + DEBUG_CODE_END (); +} +/** + Execute call back function for Pch Reset. + + @param[in] ResetType Reset Types which includes GlobalReset. + @param[in] ResetTypeGuid Pointer to an EFI_GUID, which is the Res= et Type Guid. +**/ +VOID +PchResetCallback ( + IN EFI_RESET_TYPE ResetType, + IN EFI_GUID *ResetTypeGuid + ) +{ + EFI_STATUS Status; + UINTN Instance; + PCH_RESET_CALLBACK_PPI *PchResetCallbackPpi; + + Instance =3D 0; + do { + Status =3D PeiServicesLocatePpi ( + &gPchResetCallbackPpiGuid, + Instance, + NULL, + (VOID **) &PchResetCallbackPpi + ); + + switch (Status) { + case EFI_SUCCESS: + PchResetCallbackPpi->ResetCallback (ResetType, ResetTypeGuid); + break; + case EFI_NOT_FOUND: + break; + default: + ASSERT_EFI_ERROR (Status); + break; + } + ++Instance; + } while (Status =3D=3D EFI_SUCCESS); +} + +/** + Calling this function causes a system-wide reset. This sets + all circuitry within the system to its initial state. This type of reset + is asynchronous to system operation and operates without regard to + cycle boundaries. + + System reset should not return, if it returns, it means the system does + not support cold reset. +**/ +VOID +EFIAPI +ResetCold ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback PPI + // + PchResetCallback (EfiResetCold, NULL); + DumpResetMessage (); + + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes a system-wide initialization. The processors + are set to their initial state, and pending cycles are not corrupted. + + System reset should not return, if it returns, it means the system does + not support warm reset. +**/ +VOID +EFIAPI +ResetWarm ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback PPI + // + PchResetCallback (EfiResetWarm, NULL); + DumpResetMessage (); + + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET); +} + +/** + Calling this function causes the system to enter a power state equivalent + to the ACPI G2/S5 or G3 states. + + System shutdown should not return, if it returns, it means the system do= es + not support shut down reset. +**/ +VOID +EFIAPI +ResetShutdown ( + VOID + ) +{ + UINT16 ABase; + UINT32 Data32; + + // + // Loop through callback functions of PchResetCallback PPI + // + PchResetCallback (EfiResetShutdown, NULL); + + ABase =3D PmcGetAcpiBase (); + /// + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the s= ystem from S5 + /// + IoWrite32 ((UINTN) (ABase + R_ACPI_IO_GPE0_EN_127_96), 0); + + /// + /// Secondly, PwrSts register must be cleared + /// + /// Write a "1" to bit[8] of power button status register at + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit + /// + IoWrite16 ((UINTN) (ABase + R_ACPI_IO_PM1_STS), B_ACPI_IO_PM1_STS_PWRBTN= ); + + /// + /// Finally, transform system into S5 sleep state + /// + Data32 =3D IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_CNT)); + + Data32 =3D (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP + B_ACPI_IO_PM= 1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5); + + IoWrite32 ((UINTN) (ABase + R_ACPI_IO_PM1_CNT), Data32); + + Data32 =3D Data32 | B_ACPI_IO_PM1_CNT_SLP_EN; + + DumpResetMessage (); + + IoWrite32 ((UINTN) (ABase + R_ACPI_IO_PM1_CNT), Data32); + + return; +} + +/** + Internal function to execute the required HECI command for GlobalReset, + if failed will use PCH Reest. + +**/ +STATIC +VOID +PchGlobalReset ( + VOID + ) +{ + // + // Loop through callback functions of PchResetCallback PPI + // + PchResetCallback (EfiResetPlatformSpecific, &gPchGlobalResetGuid); + + // + // PCH BIOS Spec Section 4.6 GPIO Reset Requirement + // + PmcEnableCf9GlobalReset (); + + DumpResetMessage (); + + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET); +} + +/** + Calling this function causes the system to enter a power state for platf= orm specific. + + @param[in] DataSize The size of ResetData in bytes. + @param[in] ResetData Optional element used to introduce a pla= tform specific reset. + The exact type of the reset is defined b= y the EFI_GUID that follows + the Null-terminated Unicode string. + +**/ +VOID +EFIAPI +ResetPlatformSpecific ( + IN UINTN DataSize, + IN VOID *ResetData OPTIONAL + ) +{ + EFI_GUID *GuidPtr; + + if (ResetData =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "[PeiResetSystemLib] ResetData is not available.\= n")); + return; + } + GuidPtr =3D (EFI_GUID *) ((UINT8 *) ResetData + DataSize - sizeof (EFI_G= UID)); + if (CompareGuid (GuidPtr, &gPchGlobalResetGuid)) { + PchGlobalReset(); + } else { + return; + } +} + +/** + Calling this function causes the system to enter a power state for capsu= le update. + + Reset update should not return, if it returns, it means the system does + not support capsule update. + +**/ +VOID +EFIAPI +EnterS3WithImmediateWake ( + VOID + ) +{ + ASSERT (FALSE); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PchSp= i.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PchSpi.c new file mode 100644 index 0000000000..1a5db7f24a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiSpiLib/PchSpi.c @@ -0,0 +1,217 @@ +/** @file + PCH SPI PEI Library implements the SPI Host Controller Compatibility Int= erface. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef struct { + EFI_PEI_PPI_DESCRIPTOR PpiDescriptor; + SPI_INSTANCE SpiInstance; +} PEI_SPI_INSTANCE; + +/** + PCI Enumeratuion is not done till later in DXE + Initlialize SPI BAR0 to a default value till enumeration is done + also enable memory space decoding for SPI + +**/ +VOID +InitSpiBar0 ( + VOID + ) +{ + UINT64 PchSpiBase; + PchSpiBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + PciSegmentAnd8 (PchSpiBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMMAN= D_MEMORY_SPACE); + PciSegmentWrite32 (PchSpiBase + R_SPI_CFG_BAR0, PCH_SPI_BASE_ADDRESS); + PciSegmentOr8 (PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_S= PACE); +} + +/** + This function Initial SPI services + + @retval EFI_STATUS Results of the installation of the SPI services +**/ +EFI_STATUS +EFIAPI +SpiServiceInit ( + VOID + ) +{ + EFI_STATUS Status; + PEI_SPI_INSTANCE *PeiSpiInstance; + SPI_INSTANCE *SpiInstance; + PCH_SPI_PPI *SpiPpi; + + Status =3D PeiServicesLocatePpi ( + &gPchSpiPpiGuid, + 0, + NULL, + (VOID **)&SpiPpi + ); + + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_INFO, "SpiServiceInit() Start\n")); + + // + // PCI Enumeratuion is not done till later in DXE + // Initlialize SPI BAR0 to a default value till enumeration is done + // also enable memory space decoding for SPI + // + InitSpiBar0 (); + + PeiSpiInstance =3D (PEI_SPI_INSTANCE *) AllocateZeroPool (sizeof (PEI_= SPI_INSTANCE)); + if (NULL =3D=3D PeiSpiInstance) { + return EFI_OUT_OF_RESOURCES; + } + + SpiInstance =3D &(PeiSpiInstance->SpiInstance); + SpiProtocolConstructor (SpiInstance); + + PeiSpiInstance->PpiDescriptor.Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | E= FI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST; + PeiSpiInstance->PpiDescriptor.Guid =3D &gPchSpiPpiGuid; + PeiSpiInstance->PpiDescriptor.Ppi =3D &(SpiInstance->SpiProtocol); + + /// + /// Install the SPI PPI + /// + DEBUG ((DEBUG_INFO, "SPI PPI Installed\n")); + Status =3D PeiServicesInstallPpi (&PeiSpiInstance->PpiDescriptor); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "SpiServiceInit() End\n")); + } + else { + DEBUG ((DEBUG_INFO, "SPI PPI already installed\n")); + } + return Status; +} + +/** + Acquire pch spi mmio address. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval PchSpiBar0 return SPI MMIO address +**/ +UINTN +AcquireSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ) +{ + return PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) & ~(B= _SPI_CFG_BAR0_MASK); +} + +/** + Release pch spi mmio address. Do nothing. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval None +**/ +VOID +ReleaseSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ) +{ +} + +/** + This function is a hook for Spi to disable BIOS Write Protect + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in S= MM phase + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + VOID + ) +{ + UINT64 SpiBaseAddress; + + SpiBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + if ((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_EISS= ) !=3D 0) { + return EFI_ACCESS_DENIED; + } + /// + /// Enable the access to the BIOS space for both read and write cycles + /// + PciSegmentOr8 ( + SpiBaseAddress + R_SPI_CFG_BC, + B_SPI_CFG_BC_WPD + ); + + return EFI_SUCCESS; +} + +/** + This function is a hook for Spi to enable BIOS Write Protect + + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + VOID + ) +{ + UINT64 SpiBaseAddress; + + SpiBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + /// + /// Disable the access to the BIOS space for write cycles + /// + PciSegmentAnd8 ( + SpiBaseAddress + R_SPI_CFG_BC, + (UINT8) (~B_SPI_CFG_BC_WPD) + ); +} + +/** + Check if it's granted to do flash write. + + @retval TRUE It's secure to do flash write. + @retval FALSE It's not secure to do flash write. +**/ +BOOLEAN +IsSpiFlashWriteGranted ( + VOID + ) +{ + return TRUE; +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45896): https://edk2.groups.io/g/devel/message/45896 Mute This Topic: https://groups.io/mt/32918188/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45897+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45897+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001016; cv=none; d=zoho.com; s=zohoarc; b=SmOzyvm1jkMG/KQDJj9wRkTGnFcBxB+DErLV1JO3qcC2wsYTH42JvnRguSSek2Eqk7dtTGYHvJkZA4cdEhmxJptiAR/W7Ws97a5QKYvd1Y1vMUQfMNPUW6iheelwNoTofrQx1TOjQtbg8c6Th1MxLprF05JRmnT6BXYHNvvCgk0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001016; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=VAvxyPXOrbrKOZg82ChKbtC1t8w7XIgHEEYaV1r9AOk=; b=aa3xBAeyjPiwAKppA6TpwXaApuDfxc63QSQusNNjLm4K5akCwNoPOF8MlCjZob5n9+xSm1cIKpI4DuiS+vBuJEa0CjJOiRi/neFokIlFxU1x/u3raaCY0W3KuZ9K94aaytErw8lVSTd5prQ+lMRDLvLxTDiwwjeMWYCxeFeXdT8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45897+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001016874794.0535598599362; Fri, 16 Aug 2019 17:16:56 -0700 (PDT) Return-Path: X-Received: from mga04.intel.com (mga04.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:54 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319292" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:53 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 20/37] CoffeelakeSiliconPkg/Pch: Add SMM library instances Date: Fri, 16 Aug 2019 17:15:46 -0700 Message-Id: <20190817001603.30632-21-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001016; bh=YwT6izAOl0oyUeiNLmAQ+LQzJlxC19hCt/ybtB5TZxU=; h=Cc:Date:From:Reply-To:Subject:To; b=t/ni6F3coLOzV5uAYgKUEOdNAl6F4SuN+M/bUL1zdC1+eLa4CBWdN1gYcZ8A4YVpzUH lPnjsExE0cX7Um1bWADgBvqTb0RsjfSdRzK7ZfqqjSoPd579aLM+KtCqnfA4g7GRgIzzA NfpNff3oehJkD47LKKawA9q9OqFVcfLWOw4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds PCH SMM library class instances. * SmmSpiFlashCommonLib Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SmmSpi= FlashCommonLib.inf | 51 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFla= shCommon.c | 196 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/SpiFla= shCommonSmmLib.c | 54 ++++++ 3 files changed, 301 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashComm= onLib/SmmSpiFlashCommonLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Lib= rary/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 0000000000..abc919867c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/S= mmSpiFlashCommonLib.inf @@ -0,0 +1,51 @@ +## @file +# SMM Library instance of Spi Flash Common Library Class +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmSpiFlashCommonLib + FILE_GUID =3D 9632D96E-E849-4217-9217-DC500B8AAE47 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_SMM_DRIVER + LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER + CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + PciLib + IoLib + MemoryAllocationLib + BaseLib + UefiLib + SmmServicesTableLib + BaseMemoryLib + DebugLib + MmPciLib + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES + +[Sources] + SpiFlashCommonSmmLib.c + SpiFlashCommon.c + +[Protocols] + gPchSmmSpiProtocolGuid ## CONSUMES + +[Depex.X64.DXE_SMM_DRIVER] + gPchSmmSpiProtocolGuid diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashComm= onLib/SpiFlashCommon.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Smm= SpiFlashCommonLib/SpiFlashCommon.c new file mode 100644 index 0000000000..53711db632 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/S= piFlashCommon.c @@ -0,0 +1,196 @@ +/** @file + Wrap EFI_SPI_PROTOCOL to provide some library level interfaces + for module use. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + + +PCH_SPI_PROTOCOL *mSpiProtocol; + +// +// FlashAreaBaseAddress and Size for boottime and runtime usage. +// +UINTN mFlashAreaBaseAddress =3D 0; +UINTN mFlashAreaSize =3D 0; + +/** + Enable block protection on the Serial Flash device. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashLock ( + VOID + ) +{ + return EFI_SUCCESS; +} + +/** + Read NumBytes bytes of data from the address specified by + PAddress into Buffer. + + @param[in] Address The starting physical address of the read. + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number + of bytes actually read. + @param[out] Buffer The destination data buffer for the read. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashRead ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + OUT UINT8 *Buffer + ) +{ + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // This function is implemented specifically for those platforms + // at which the SPI device is memory mapped for read. So this + // function just do a memory copy for Spi Flash Read. + // + CopyMem (Buffer, (VOID *) Address, *NumBytes); + + return EFI_SUCCESS; +} + +/** + Write NumBytes bytes of data from Buffer to the address specified by + PAddresss. + + @param[in] Address The starting physical address of the wri= te. + @param[in,out] NumBytes On input, the number of bytes to write. = On output, + the actual number of bytes written. + @param[in] Buffer The source data buffer for the write. + + @retval EFI_SUCCESS Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashWrite ( + IN UINTN Address, + IN OUT UINT32 *NumBytes, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINT32 Length; + UINT32 RemainingBytes; + + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL)); + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mFlashAreaBaseAddress); + + Offset =3D Address - mFlashAreaBaseAddress; + + ASSERT ((*NumBytes + Offset) <=3D mFlashAreaSize); + + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + while (RemainingBytes > 0) { + if (RemainingBytes > SECTOR_SIZE_4KB) { + Length =3D SECTOR_SIZE_4KB; + } else { + Length =3D RemainingBytes; + } + Status =3D mSpiProtocol->FlashWrite ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + Length, + Buffer + ); + if (EFI_ERROR (Status)) { + break; + } + RemainingBytes -=3D Length; + Offset +=3D Length; + Buffer +=3D Length; + } + + // + // Actual number of bytes written + // + *NumBytes -=3D RemainingBytes; + + return Status; +} + +/** + Erase the block starting at Address. + + @param[in] Address The starting physical address of the block t= o be erased. + This library assume that caller garantee tha= t the PAddress + is at the starting address of this block. + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased. + On output, the actual number of bytes erased. + + @retval EFI_SUCCESS. Opertion is successful. + @retval EFI_DEVICE_ERROR If there is any device errors. + +**/ +EFI_STATUS +EFIAPI +SpiFlashBlockErase ( + IN UINTN Address, + IN UINTN *NumBytes + ) +{ + EFI_STATUS Status; + UINTN Offset; + UINTN RemainingBytes; + + ASSERT (NumBytes !=3D NULL); + if (NumBytes =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Address >=3D mFlashAreaBaseAddress); + + Offset =3D Address - mFlashAreaBaseAddress; + + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0); + ASSERT ((*NumBytes + Offset) <=3D mFlashAreaSize); + + Status =3D EFI_SUCCESS; + RemainingBytes =3D *NumBytes; + + + Status =3D mSpiProtocol->FlashErase ( + mSpiProtocol, + FlashRegionBios, + (UINT32) Offset, + (UINT32) RemainingBytes + ); + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashComm= onLib/SpiFlashCommonSmmLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Libra= ry/SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c new file mode 100644 index 0000000000..43c0218d85 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/SmmSpiFlashCommonLib/S= piFlashCommonSmmLib.c @@ -0,0 +1,54 @@ +/** @file + SMM Library instance of SPI Flash Common Library Class + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +extern PCH_SPI_PROTOCOL *mSpiProtocol; + +extern UINTN mFlashAreaBaseAddress; +extern UINTN mFlashAreaSize; + +/** + The library constructuor. + + The function does the necessary initialization work for this library + instance. + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. + @retval EFI_ERROR Please reference LocateProtocol for error = code details. +**/ +EFI_STATUS +EFIAPI +SmmSpiFlashCommonLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mFlashAreaBaseAddress =3D (UINTN)PcdGet32 (PcdBiosAreaBaseAddress); + mFlashAreaSize =3D (UINTN)PcdGet32 (PcdBiosSize); + + // + // Locate the SMM SPI protocol. + // + Status =3D gSmst->SmmLocateProtocol ( + &gPchSmmSpiProtocolGuid, + NULL, + (VOID **) &mSpiProtocol + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45897): https://edk2.groups.io/g/devel/message/45897 Mute This Topic: https://groups.io/mt/32918189/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45898+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45898+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001017; cv=none; d=zoho.com; s=zohoarc; b=L6QoN8dWswp5kOGNH+CqmzLlieSwxPkDRXCN+kiPom6zR383TeD+P/jJUHIuuEAsSaxu1kLTNSok5mfzzZLY5hlMcNSBvRdYX/hlHU2O0fqAcBjDGojbVtvs4vxiGSYOD1TYpUWorBBgTbPorNntLDc4PrKqqWIYpC4kcWwo7Nc= ARC-Message-Signature: i=1; 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16 Aug 2019 17:16:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319295" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:53 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 21/37] CoffeelakeSiliconPkg/Pch: Add Base library instances Date: Fri, 16 Aug 2019 17:15:47 -0700 Message-Id: <20190817001603.30632-22-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001016; bh=6G6KJiUc3UBdkdg6iI2ry7oKEdEjOK14Ur9iJ0MrIdE=; h=Cc:Date:From:Reply-To:Subject:To; b=aV7MxOYMiRKUDJzeTIachw+chcXA+Uvuh6EyMXdc1Qs3K2H3V1aKCLcyYp55M4h7cTh 6ReTNjXYd2PHgkUdlGMaMJYdSLB9jvyjdNPt+OzZPeW7c9zXWMhl0tkeEDBaCgwKB51J6 OngquoIDYdKIzsxfyMjvlWSyU0PK94HV0t0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds Pch/Library/Private Base library class instances. * BaseGpioHelpersLibNull * BasePchSpiCommonlib * BaseSiScheduleResetLib * BaseSiScheduleResetLibFsp Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibN= ull/BaseGpioHelpersLibNull.inf | 26 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib= /BasePchSpiCommonLib.inf | 28 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleReset= Lib/BaseSiScheduleResetLib.inf | 40 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleReset= Lib/BaseSiScheduleResetLibFsp.inf | 40 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelpersLibN= ull/BaseGpioHelpersLibNull.c | 108 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiCommonLib= /SpiCommon.c | 1081 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleReset= Lib/BaseSiScheduleResetLib.c | 70 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleReset= Lib/BaseSiScheduleResetLibCommon.c | 125 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiScheduleReset= Lib/BaseSiScheduleResetLibFsp.c | 61 ++ 9 files changed, 1579 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpi= oHelpersLibNull/BaseGpioHelpersLibNull.inf b/Silicon/Intel/CoffeelakeSilico= nPkg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf new file mode 100644 index 0000000000..5502af824f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelper= sLibNull/BaseGpioHelpersLibNull.inf @@ -0,0 +1,26 @@ +## @file +# Component description file for the NULL GpioHelpersLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseGpioHelpersLib +FILE_GUID =3D AB282608-2A50-4AE3-9242-64064ECF40D4 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D GpioHelpersLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +BaseGpioHelpersLibNull.c + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePch= SpiCommonLib/BasePchSpiCommonLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/P= ch/Library/Private/BasePchSpiCommonLib/BasePchSpiCommonLib.inf new file mode 100644 index 0000000000..ea23e628c8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiComm= onLib/BasePchSpiCommonLib.inf @@ -0,0 +1,28 @@ +## @file +# Component description file for the PchSpiCommonLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BasePchSpiCommonLib + FILE_GUID =3D A37CB67E-7D85-45B3-B07E-BF65BDB603E8 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PchSpiCommonLib + +[Sources] + SpiCommon.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + IoLib + DebugLib + PmcLib diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiS= cheduleResetLib/BaseSiScheduleResetLib.inf b/Silicon/Intel/CoffeelakeSilico= nPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf new file mode 100644 index 0000000000..de7f6eeb73 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiSchedule= ResetLib/BaseSiScheduleResetLib.inf @@ -0,0 +1,40 @@ +## @file +# Component description file for Si Reset Schedule Library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseSiScheduleResetLib +FILE_GUID =3D E6F3D551-36C0-4737-80C7-47FC57593163 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D SiScheduleResetLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +BaseLib +IoLib +DebugLib +HobLib +ResetSystemLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Guids] +gSiScheduleResetHobGuid +gPchConfigHobGuid + +[Sources] +BaseSiScheduleResetLibCommon.c +BaseSiScheduleResetLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiS= cheduleResetLib/BaseSiScheduleResetLibFsp.inf b/Silicon/Intel/CoffeelakeSil= iconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibFs= p.inf new file mode 100644 index 0000000000..c8fe9e6079 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiSchedule= ResetLib/BaseSiScheduleResetLibFsp.inf @@ -0,0 +1,40 @@ +## @file +# Component description file for Si Reset Schedule Library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D BaseSiScheduleResetLibFsp +FILE_GUID =3D 1478D005-8DEC-4A6E-9619-309C6A7F313A +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D SiScheduleResetLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF +# + +[LibraryClasses] +BaseLib +IoLib +DebugLib +HobLib +PeiServicesTablePointerLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Guids] +gSiScheduleResetHobGuid +gPchConfigHobGuid + +[Sources] +BaseSiScheduleResetLibCommon.c +BaseSiScheduleResetLibFsp.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpi= oHelpersLibNull/BaseGpioHelpersLibNull.c b/Silicon/Intel/CoffeelakeSiliconP= kg/Pch/Library/Private/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.c new file mode 100644 index 0000000000..46390eeca1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseGpioHelper= sLibNull/BaseGpioHelpersLibNull.c @@ -0,0 +1,108 @@ +/** @file + This file contains NULL implementation for GPIO Helpers Lib + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + This procedure stores GPIO pad unlock information + + @param[in] GpioPad GPIO pad + @param[in] GpioLockConfig GPIO Lock Configuration + + @retval Status +**/ +EFI_STATUS +GpioStoreUnlockData ( + IN GPIO_PAD GpioPad, + IN GPIO_LOCK_CONFIG GpioLockConfig + ) +{ + return EFI_SUCCESS; +} + +/** + This procedure stores GPIO group data about pads which PadConfig needs t= o be unlocked. + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: Skip, 1: Leave unlocked + + @retval Status +**/ +EFI_STATUS +GpioStoreGroupDwUnlockPadConfigData ( + IN UINT32 GroupIndex, + IN UINT32 DwNum, + IN UINT32 UnlockedPads + ) +{ + return EFI_SUCCESS; +} + +/** + This procedure stores GPIO group data about pads which Output state need= s to be unlocked. + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: Skip, 1: Leave unlocked + @retval Status +**/ +EFI_STATUS +GpioStoreGroupDwUnlockOutputData ( + IN UINT32 GroupIndex, + IN UINT32 DwNum, + IN UINT32 UnlockedPads + ) +{ + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO group data with pads, which PadConfig is su= pposed to be left unlock + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @retval UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: to be locked, 1: Leave un= locked +**/ +UINT32 +GpioGetGroupDwUnlockPadConfigMask ( + IN UINT32 GroupIndex, + IN UINT32 DwNum + ) +{ + return 0; +} + +/** + This procedure will get GPIO group data with pads, which Output is suppo= sed to be left unlock + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @retval UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: to be locked, 1: Leave un= locked +**/ +UINT32 +GpioGetGroupDwUnlockOutputMask ( + IN UINT32 GroupIndex, + IN UINT32 DwNum + ) +{ + return 0; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePch= SpiCommonLib/SpiCommon.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/P= rivate/BasePchSpiCommonLib/SpiCommon.c new file mode 100644 index 0000000000..bc84a4f27f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BasePchSpiComm= onLib/SpiCommon.c @@ -0,0 +1,1081 @@ +/** @file + PCH SPI Common Driver implements the SPI Host Controller Compatibility I= nterface. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Initialize an SPI protocol instance. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @exception EFI_UNSUPPORTED The PCH is not supported by this module +**/ +EFI_STATUS +SpiProtocolConstructor ( + IN SPI_INSTANCE *SpiInstance + ) +{ + UINTN PchSpiBar0; + UINT32 Data32; + + // + // Initialize the SPI protocol instance + // + SpiInstance->Signature =3D PCH_SPI_PRIVATE_DATA_SIGNA= TURE; + SpiInstance->Handle =3D NULL; + SpiInstance->SpiProtocol.Revision =3D PCH_SPI_SERVICES_REVISION; + SpiInstance->SpiProtocol.FlashRead =3D SpiProtocolFlashRead; + SpiInstance->SpiProtocol.FlashWrite =3D SpiProtocolFlashWrite; + SpiInstance->SpiProtocol.FlashErase =3D SpiProtocolFlashErase; + SpiInstance->SpiProtocol.FlashReadSfdp =3D SpiProtocolFlashReadSfdp; + SpiInstance->SpiProtocol.FlashReadJedecId =3D SpiProtocolFlashReadJedecI= d; + SpiInstance->SpiProtocol.FlashWriteStatus =3D SpiProtocolFlashWriteStatu= s; + SpiInstance->SpiProtocol.FlashReadStatus =3D SpiProtocolFlashReadStatus; + SpiInstance->SpiProtocol.GetRegionAddress =3D SpiProtocolGetRegionAddres= s; + SpiInstance->SpiProtocol.ReadPchSoftStrap =3D SpiProtocolReadPchSoftStra= p; + SpiInstance->SpiProtocol.ReadCpuSoftStrap =3D SpiProtocolReadCpuSoftStra= p; + + SpiInstance->PchSpiBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + + SpiInstance->PchAcpiBase =3D PmcGetAcpiBase (); + ASSERT (SpiInstance->PchAcpiBase !=3D 0); + + PchSpiBar0 =3D PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR= 0) & ~(B_SPI_CFG_BAR0_MASK); + if (PchSpiBar0 =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n")); + ASSERT (FALSE); + } + + if ((MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_FDV) = =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "ERROR : SPI Flash Signature invalid, cannot use = the Hardware Sequencing registers!\n")); + ASSERT (FALSE); + } + + // + // Get Region 0 - 7 read Permission bits, region 8 and above are not per= mitted. + // + SpiInstance->ReadPermission =3D MmioRead8 (PchSpiBar0 + R_SPI_MEM_FRAP) = & B_SPI_MEM_FRAP_BRRA_MASK; + DEBUG ((DEBUG_INFO, "Flash Region read Permission : %0x\n", SpiInstance-= >ReadPermission)); + // + // Get Region 0 - 7 write Permission bits, region 8 and above are not pe= rmitted. + // + SpiInstance->WritePermission =3D (UINT8) ((MmioRead16 (PchSpiBar0 + R_SP= I_MEM_FRAP) & + B_SPI_MEM_FRAP_BRWA_MASK) >> N_= SPI_MEM_FRAP_BRWA); + DEBUG ((DEBUG_INFO, "Flash Region write Permission : %0x\n", SpiInstance= ->WritePermission)); + + SpiInstance->SfdpVscc0Value =3D MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP0= _VSCC0); + DEBUG ((DEBUG_INFO, "Component 0 SFDP VSCC value : %0x\n", SpiInstance->= SfdpVscc0Value)); + SpiInstance->SfdpVscc1Value =3D MmioRead32 (PchSpiBar0 + R_SPI_MEM_SFDP1= _VSCC1); + DEBUG ((DEBUG_INFO, "Component 1 SFDP VSCC value : %0x\n", SpiInstance->= SfdpVscc1Value)); + + // + // Select to Flash Map 0 Register to get the number of flash Component + // + MmioAndThenOr32 ( + PchSpiBar0 + R_SPI_MEM_FDOC, + (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)), + (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_SPI_FLASH_FDBAR_FLASH_MAP0) + ); + + // + // Copy Zero based Number Of Components + // + SpiInstance->NumberOfComponents =3D (UINT8) ((MmioRead16 (PchSpiBar0 + R= _SPI_MEM_FDOD) & B_SPI_FLASH_FDBAR_NC) >> N_SPI_FLASH_FDBAR_NC); + DEBUG ((DEBUG_INFO, "Component Number : %0x\n", SpiInstance->NumberOfCom= ponents + 1)); + + MmioAndThenOr32 ( + PchSpiBar0 + R_SPI_MEM_FDOC, + (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)), + (UINT32) (V_SPI_MEM_FDOC_FDSS_COMP | R_SPI_FLASH_FCBA_FLCOMP) + ); + + // + // Copy Component 0 Density + // + Data32 =3D MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD); + if (SpiInstance->NumberOfComponents > 0) { + SpiInstance->Component1StartAddr =3D V_SPI_FLASH_FLCOMP_COMP_512KB << + (Data32 & B_SPI_FLASH_FLCOMP_COMP0_MASK); + DEBUG ((DEBUG_INFO, "Component 1 StartAddr : %0x\n", SpiInstance->Comp= onent1StartAddr)); + SpiInstance->TotalFlashSize =3D SpiInstance->Component1StartAddr + + (V_SPI_FLASH_FLCOMP_COMP_512KB << + ((Data32 & B_SPI_FLASH_FLCOMP_COMP1_MASK) >> + N_SPI_FLASH_FLCOMP_COMP1)); + } else { + SpiInstance->TotalFlashSize =3D V_SPI_FLASH_FLCOMP_COMP_512KB << + (Data32 & B_SPI_FLASH_FLCOMP_COMP0_MASK); + } + DEBUG ((DEBUG_INFO, "Total Flash Size : %0x\n", SpiInstance->TotalFlashS= ize)); + + // + // Select FLASH_MAP1 to get Flash PCH Strap Base Address + // + MmioAndThenOr32 ( + (PchSpiBar0 + R_SPI_MEM_FDOC), + (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)), + (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_SPI_FLASH_FDBAR_FLASH_MAP1) + ); + // + // Align FPSBA with address bits for the PCH Strap portion of flash desc= riptor + // + Data32 =3D MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD); + SpiInstance->PchStrapBaseAddr =3D (UINT16) (((Data32 & B_SPI_FLASH_FDBAR= _FPSBA) + >> N_SPI_FLASH_FDBAR_FPSBA) + << N_SPI_FLASH_FDBAR_FPSBA_REP= R); + DEBUG ((DEBUG_INFO, "PchStrapBaseAddr : %0x\n", SpiInstance->PchStrapBas= eAddr)); + ASSERT (SpiInstance->PchStrapBaseAddr !=3D 0); + // + // PCH Strap Length, [31:24] represents number of Dwords + // + SpiInstance->PchStrapSize =3D (UINT16) (((Data32 & B_SPI_FLASH_FDBAR_PCH= SL) + >> N_SPI_FLASH_FDBAR_PCHSL) + * sizeof (UINT32)); + DEBUG ((DEBUG_INFO, "PchStrapSize : %0x\n", SpiInstance->PchStrapSize)); + + // + // Select FLASH_MAP2 to get Flash CPU Strap Base Address + // + MmioAndThenOr32 ( + (PchSpiBar0 + R_SPI_MEM_FDOC), + (UINT32) (~(B_SPI_MEM_FDOC_FDSS_MASK | B_SPI_MEM_FDOC_FDSI_MASK)), + (UINT32) (V_SPI_MEM_FDOC_FDSS_FSDM | R_SPI_FLASH_FDBAR_FLASH_MAP2) + ); + // + // Align FPSBA with address bits for the PCH Strap portion of flash desc= riptor + // + Data32 =3D MmioRead32 (PchSpiBar0 + R_SPI_MEM_FDOD); + SpiInstance->CpuStrapBaseAddr =3D (UINT16) (((Data32 & B_SPI_FLASH_FDBAR= _FCPUSBA) + >> N_SPI_FLASH_FDBAR_FCPUSBA) + << N_SPI_FLASH_FDBAR_FCPUSBA_R= EPR); + DEBUG ((DEBUG_INFO, "CpuStrapBaseAddr : %0x\n", SpiInstance->CpuStrapBas= eAddr)); + ASSERT (SpiInstance->CpuStrapBaseAddr !=3D 0); + // + // CPU Strap Length, [15:8] represents number of Dwords + // + SpiInstance->CpuStrapSize =3D (UINT16) (((Data32 & B_SPI_FLASH_FDBAR_CPU= SL) + >> N_SPI_FLASH_FDBAR_CPUSL) + * sizeof (UINT32)); + DEBUG ((DEBUG_INFO, "CpuStrapSize : %0x\n", SpiInstance->CpuStrapSize)); + + return EFI_SUCCESS; +} + +/** + Delay for at least the request number of microseconds for Runtime usage. + + @param[in] ABase Acpi base address + @param[in] Microseconds Number of microseconds to delay. + +**/ +VOID +EFIAPI +PchPmTimerStallRuntimeSafe ( + IN UINT16 ABase, + IN UINTN Microseconds + ) +{ + UINTN Ticks; + UINTN Counts; + UINTN CurrentTick; + UINTN OriginalTick; + UINTN RemainingTick; + + if (Microseconds =3D=3D 0) { + return; + } + + OriginalTick =3D IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_AC= PI_IO_PM1_TMR_VAL; + CurrentTick =3D OriginalTick; + + // + // The timer frequency is 3.579545 MHz, so 1 ms corresponds 3.58 clocks + // + Ticks =3D Microseconds * 358 / 100 + OriginalTick + 1; + + // + // The loops needed by timer overflow + // + Counts =3D Ticks / V_ACPI_IO_PM1_TMR_MAX_VAL; + + // + // Remaining clocks within one loop + // + RemainingTick =3D Ticks % V_ACPI_IO_PM1_TMR_MAX_VAL; + + // + // not intend to use TMROF_STS bit of register PM1_STS, because this add= s extra + // one I/O operation, and maybe generate SMI + // + while ((Counts !=3D 0) || (RemainingTick > CurrentTick)) { + CurrentTick =3D IoRead32 ((UINTN) (ABase + R_ACPI_IO_PM1_TMR)) & B_ACP= I_IO_PM1_TMR_VAL; + // + // Check if timer overflow + // + if ((CurrentTick < OriginalTick)) { + if (Counts !=3D 0) { + Counts--; + } else { + // + // If timer overflow and Counts equ to 0, that means we already st= alled more than + // RemainingTick, break the loop here + // + break; + } + } + + OriginalTick =3D CurrentTick; + } +} + +/** + Wait execution cycle to complete on the SPI interface. + + @param[in] This The SPI protocol instance + @param[in] PchSpiBar0 Spi MMIO base address + @param[in] ErrorCheck TRUE if the SpiCycle needs to do the err= or check + + @retval TRUE SPI cycle completed on the interface. + @retval FALSE Time out while waiting the SPI cycle to = complete. + It's not safe to program the next comman= d on the SPI interface. +**/ +STATIC +BOOLEAN +WaitForSpiCycleComplete ( + IN PCH_SPI_PROTOCOL *This, + IN UINTN PchSpiBar0, + IN BOOLEAN ErrorCheck + ) +{ + UINT64 WaitTicks; + UINT64 WaitCount; + UINT32 Data32; + SPI_INSTANCE *SpiInstance; + + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); + + // + // Convert the wait period allowed into to tick count + // + WaitCount =3D SPI_WAIT_TIME / SPI_WAIT_PERIOD; + // + // Wait for the SPI cycle to complete. + // + for (WaitTicks =3D 0; WaitTicks < WaitCount; WaitTicks++) { + Data32 =3D MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC); + if ((Data32 & B_SPI_MEM_HSFSC_SCIP) =3D=3D 0) { + MmioWrite32 (PchSpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FCERR | B= _SPI_MEM_HSFSC_FDONE); + if (((Data32 & B_SPI_MEM_HSFSC_FCERR) !=3D 0) && (ErrorCheck =3D=3D = TRUE)) { + return FALSE; + } else { + return TRUE; + } + } + PchPmTimerStallRuntimeSafe (SpiInstance->PchAcpiBase, SPI_WAIT_PERIOD); + } + return FALSE; +} + +/** + This function sends the programmed SPI command to the slave device. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SpiRegionType The SPI Region type for flash cycle whic= h is listed in the Descriptor + @param[in] FlashCycleType The Flash SPI cycle type list in HSFC (H= ardware Sequencing Flash Control Register) register + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in,out] Buffer Pointer to caller-allocated buffer conta= ining the dada received or sent during the SPI cycle. + + @retval EFI_SUCCESS SPI command completes successfully. + @retval EFI_DEVICE_ERROR Device error, the command aborts abnorma= lly. + @retval EFI_ACCESS_DENIED Some unrecognized or blocked command enc= ountered in hardware sequencing mode + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. +**/ +STATIC +EFI_STATUS +SendSpiCmd ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN FLASH_CYCLE_TYPE FlashCycleType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + UINT32 Index; + SPI_INSTANCE *SpiInstance; + UINT64 SpiBaseAddress; + UINTN PchSpiBar0; + UINT32 HardwareSpiAddr; + UINT32 FlashRegionSize; + UINT32 SpiDataCount; + UINT32 FlashCycle; + UINT8 BiosCtlSave; + UINT32 SmiEnSave; + UINT16 ABase; + UINT32 HsfstsCtl; + + // + // For flash write, there is a requirement that all CPU threads are in S= MM + // before the flash protection is disabled. + // + if ((FlashCycleType =3D=3D FlashCycleWrite) || (FlashCycleType =3D=3D Fl= ashCycleErase)) { + if (!IsSpiFlashWriteGranted ()) { + return EFI_ACCESS_DENIED; + } + } + + Status =3D EFI_SUCCESS; + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); + SpiBaseAddress =3D SpiInstance->PchSpiBase; + PchSpiBar0 =3D AcquireSpiBar0 (SpiInstance); + ABase =3D SpiInstance->PchAcpiBase; + + // + // Disable SMIs to make sure normal mode flash access is not interrupted= by an SMI + // whose SMI handler accesses flash (e.g. for error logging) + // + // *** NOTE: if the SMI_LOCK bit is set (i.e., PMC PCI Offset A0h [4]=3D= '1'), + // clearing B_GBL_SMI_EN will not have effect. In this situation, some o= ther + // synchronization methods must be applied here or in the consumer of the + // SendSpiCmd. An example method is disabling the specific SMI sources + // whose SMI handlers access flash before flash cycle and re-enabling th= e SMI + // sources after the flash cycle . + // + SmiEnSave =3D IoRead32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN)); + IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave & (UINT32) (~B_= ACPI_IO_SMI_EN_GBL_SMI)); + BiosCtlSave =3D PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_= CFG_BC_SRC; + + // + // If it's write cycle, disable Prefetching, Caching and disable BIOS Wr= ite Protect + // + if ((FlashCycleType =3D=3D FlashCycleWrite) || + (FlashCycleType =3D=3D FlashCycleErase)) { + Status =3D DisableBiosWriteProtect (); + if (EFI_ERROR (Status)) { + goto SendSpiCmdEnd; + } + PciSegmentAndThenOr8 ( + SpiBaseAddress + R_SPI_CFG_BC, + (UINT8) (~B_SPI_CFG_BC_SRC), + (UINT8) (V_SPI_CFG_BC_SRC_PREF_DIS_CACHE_DIS << N_SPI_CFG_BC_SRC) + ); + } + // + // Make sure it's safe to program the command. + // + if (!WaitForSpiCycleComplete (This, PchSpiBar0, FALSE)) { + Status =3D EFI_DEVICE_ERROR; + goto SendSpiCmdEnd; + } + + // + // Check if Write Status isn't disabled in HW Sequencing + // + if (FlashCycleType =3D=3D FlashCycleWriteStatus) { + HsfstsCtl =3D MmioRead32 (PchSpiBar0 + R_SPI_MEM_HSFSC); + if ((HsfstsCtl & B_SPI_MEM_HSFSC_WRSDIS) !=3D 0) { + Status =3D EFI_ACCESS_DENIED; + goto SendSpiCmdEnd; + } + } + + Status =3D SpiProtocolGetRegionAddress (This, FlashRegionType, &Hardware= SpiAddr, &FlashRegionSize); + if (EFI_ERROR (Status)) { + goto SendSpiCmdEnd; + } + HardwareSpiAddr +=3D Address; + if ((Address + ByteCount) > FlashRegionSize) { + Status =3D EFI_INVALID_PARAMETER; + goto SendSpiCmdEnd; + } + + // + // Check for PCH SPI hardware sequencing required commands + // + FlashCycle =3D 0; + switch (FlashCycleType) { + case FlashCycleRead: + FlashCycle =3D (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ << N_SPI_MEM_HSF= SC_CYCLE); + break; + case FlashCycleWrite: + FlashCycle =3D (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE << N_SPI_MEM_HS= FSC_CYCLE); + break; + case FlashCycleErase: + if (((ByteCount % SIZE_4KB) !=3D 0) || + ((HardwareSpiAddr % SIZE_4KB) !=3D 0)) { + ASSERT (FALSE); + Status =3D EFI_INVALID_PARAMETER; + goto SendSpiCmdEnd; + } + break; + case FlashCycleReadSfdp: + FlashCycle =3D (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_SFDP << N_SPI_ME= M_HSFSC_CYCLE); + break; + case FlashCycleReadJedecId: + FlashCycle =3D (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_JEDEC_ID << N_SP= I_MEM_HSFSC_CYCLE); + break; + case FlashCycleWriteStatus: + FlashCycle =3D (UINT32) (V_SPI_MEM_HSFSC_CYCLE_WRITE_STATUS << N_SPI= _MEM_HSFSC_CYCLE); + break; + case FlashCycleReadStatus: + FlashCycle =3D (UINT32) (V_SPI_MEM_HSFSC_CYCLE_READ_STATUS << N_SPI_= MEM_HSFSC_CYCLE); + break; + default: + // + // Unrecognized Operation + // + ASSERT (FALSE); + Status =3D EFI_INVALID_PARAMETER; + goto SendSpiCmdEnd; + break; + } + + do { + SpiDataCount =3D ByteCount; + if ((FlashCycleType =3D=3D FlashCycleRead) || + (FlashCycleType =3D=3D FlashCycleWrite) || + (FlashCycleType =3D=3D FlashCycleReadSfdp)) { + // + // Trim at 256 byte boundary per operation, + // - PCH SPI controller requires trimming at 4KB boundary + // - Some SPI chips require trimming at 256 byte boundary for write = operation + // - Trimming has limited performance impact as we can read / write = atmost 64 byte + // per operation + // + if (HardwareSpiAddr + ByteCount > ((HardwareSpiAddr + BIT8) &~(BIT8 = - 1))) { + SpiDataCount =3D (((UINT32) (HardwareSpiAddr) + BIT8) &~(BIT8 - 1)= ) - (UINT32) (HardwareSpiAddr); + } + // + // Calculate the number of bytes to shift in/out during the SPI data= cycle. + // Valid settings for the number of bytes duing each data portion of= the + // PCH SPI cycles are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32, 40, 48= , 56, 64 + // + if (SpiDataCount >=3D 64) { + SpiDataCount =3D 64; + } else if ((SpiDataCount &~0x07) !=3D 0) { + SpiDataCount =3D SpiDataCount &~0x07; + } + } + if (FlashCycleType =3D=3D FlashCycleErase) { + if (((ByteCount / SIZE_64KB) !=3D 0) && + ((ByteCount % SIZE_64KB) =3D=3D 0) && + ((HardwareSpiAddr % SIZE_64KB) =3D=3D 0)) { + if (HardwareSpiAddr < SpiInstance->Component1StartAddr) { + // + // Check whether Component0 support 64k Erase + // + if ((SpiInstance->SfdpVscc0Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K)= !=3D 0) { + SpiDataCount =3D SIZE_64KB; + } else { + SpiDataCount =3D SIZE_4KB; + } + } else { + // + // Check whether Component1 support 64k Erase + // + if ((SpiInstance->SfdpVscc1Value & B_SPI_MEM_SFDPX_VSCCX_EO_64K)= !=3D 0) { + SpiDataCount =3D SIZE_64KB; + } else { + SpiDataCount =3D SIZE_4KB; + } + } + } else { + SpiDataCount =3D SIZE_4KB; + } + if (SpiDataCount =3D=3D SIZE_4KB) { + FlashCycle =3D (UINT32) (V_SPI_MEM_HSFSC_CYCLE_4K_ERASE << N_SPI_M= EM_HSFSC_CYCLE); + } else { + FlashCycle =3D (UINT32) (V_SPI_MEM_HSFSC_CYCLE_64K_ERASE << N_SPI_= MEM_HSFSC_CYCLE); + } + } + // + // If it's write cycle, load data into the SPI data buffer. + // + if ((FlashCycleType =3D=3D FlashCycleWrite) || (FlashCycleType =3D=3D = FlashCycleWriteStatus)) { + if ((SpiDataCount & 0x07) !=3D 0) { + // + // Use Byte write if Data Count is 0, 1, 2, 3, 4, 5, 6, 7 + // + for (Index =3D 0; Index < SpiDataCount; Index++) { + MmioWrite8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, Buffer[Index= ]); + } + } else { + // + // Use Dword write if Data Count is 8, 16, 24, 32, 40, 48, 56, 64 + // + for (Index =3D 0; Index < SpiDataCount; Index +=3D sizeof (UINT32)= ) { + MmioWrite32 (PchSpiBar0 + R_SPI_MEM_FDATA00 + Index, *(UINT32 *)= (Buffer + Index)); + } + } + } + + // + // Set the Flash Address + // + MmioWrite32 ( + (PchSpiBar0 + R_SPI_MEM_FADDR), + (UINT32) (HardwareSpiAddr & B_SPI_MEM_FADDR_MASK) + ); + + // + // Set Data count, Flash cycle, and Set Go bit to start a cycle + // + MmioAndThenOr32 ( + PchSpiBar0 + R_SPI_MEM_HSFSC, + (UINT32) (~(B_SPI_MEM_HSFSC_FDBC_MASK | B_SPI_MEM_HSFSC_CYCLE_MASK)), + (UINT32) ((((SpiDataCount - 1) << N_SPI_MEM_HSFSC_FDBC) & B_SPI_MEM_= HSFSC_FDBC_MASK) | FlashCycle | B_SPI_MEM_HSFSC_CYCLE_FGO) + ); + // + // end of command execution + // + // Wait the SPI cycle to complete. + // + if (!WaitForSpiCycleComplete (This, PchSpiBar0, TRUE)) { + ASSERT (FALSE); + Status =3D EFI_DEVICE_ERROR; + goto SendSpiCmdEnd; + } + // + // If it's read cycle, load data into the call's buffer. + // + if ((FlashCycleType =3D=3D FlashCycleRead) || + (FlashCycleType =3D=3D FlashCycleReadSfdp) || + (FlashCycleType =3D=3D FlashCycleReadJedecId) || + (FlashCycleType =3D=3D FlashCycleReadStatus)) { + if ((SpiDataCount & 0x07) !=3D 0) { + // + // Use Byte read if Data Count is 0, 1, 2, 3, 4, 5, 6, 7 + // + for (Index =3D 0; Index < SpiDataCount; Index++) { + Buffer[Index] =3D MmioRead8 (PchSpiBar0 + R_SPI_MEM_FDATA00 + In= dex); + } + } else { + // + // Use Dword read if Data Count is 8, 16, 24, 32, 40, 48, 56, 64 + // + for (Index =3D 0; Index < SpiDataCount; Index +=3D sizeof (UINT32)= ) { + *(UINT32 *) (Buffer + Index) =3D MmioRead32 (PchSpiBar0 + R_SPI_= MEM_FDATA00 + Index); + } + } + } + + HardwareSpiAddr +=3D SpiDataCount; + Buffer +=3D SpiDataCount; + ByteCount -=3D SpiDataCount; + } while (ByteCount > 0); + +SendSpiCmdEnd: + // + // Restore the settings for SPI Prefetching and Caching and enable BIOS = Write Protect + // + if ((FlashCycleType =3D=3D FlashCycleWrite) || + (FlashCycleType =3D=3D FlashCycleErase)) { + EnableBiosWriteProtect (); + PciSegmentAndThenOr8 ( + SpiBaseAddress + R_SPI_CFG_BC, + (UINT8) ~B_SPI_CFG_BC_SRC, + BiosCtlSave + ); + } + // + // Restore SMIs. + // + IoWrite32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN), SmiEnSave); + + ReleaseSpiBar0 (SpiInstance); + + return Status; +} + +/** + Read data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received. + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashRead ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *Buffer + ) +{ + EFI_STATUS Status; + + // + // Sends the command to the SPI interface to execute. + // + Status =3D SendSpiCmd ( + This, + FlashRegionType, + FlashCycleRead, + Address, + ByteCount, + Buffer + ); + return Status; +} + +/** + Write data to the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWrite ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount, + IN UINT8 *Buffer + ) +{ + EFI_STATUS Status; + + // + // Sends the command to the SPI interface to execute. + // + Status =3D SendSpiCmd ( + This, + FlashRegionType, + FlashCycleWrite, + Address, + ByteCount, + Buffer + ); + return Status; +} + +/** + Erase some area on the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor. + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions. + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashErase ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + IN UINT32 Address, + IN UINT32 ByteCount + ) +{ + EFI_STATUS Status; + + // + // Sends the command to the SPI interface to execute. + // + Status =3D SendSpiCmd ( + This, + FlashRegionType, + FlashCycleErase, + Address, + ByteCount, + NULL + ); + return Status; +} + +/** + Read SFDP data from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] Address The starting byte address for SFDP data = read. + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadSfdp ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 Address, + IN UINT32 ByteCount, + OUT UINT8 *SfdpData + ) +{ + SPI_INSTANCE *SpiInstance; + EFI_STATUS Status; + UINT32 FlashAddress; + + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); + Status =3D EFI_SUCCESS; + + if (ComponentNumber > SpiInstance->NumberOfComponents) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + FlashAddress =3D 0; + if (ComponentNumber =3D=3D FlashComponent1) { + FlashAddress =3D SpiInstance->Component1StartAddr; + } + FlashAddress +=3D Address; + // + // Sends the command to the SPI interface to execute. + // + Status =3D SendSpiCmd ( + This, + FlashRegionAll, + FlashCycleReadSfdp, + FlashAddress, + ByteCount, + SfdpData + ); + return Status; +} + +/** + Read Jedec Id from the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ComponentNumber The Componen Number for chip select + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadJedecId ( + IN PCH_SPI_PROTOCOL *This, + IN UINT8 ComponentNumber, + IN UINT32 ByteCount, + OUT UINT8 *JedecId + ) +{ + SPI_INSTANCE *SpiInstance; + EFI_STATUS Status; + UINT32 Address; + + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); + Status =3D EFI_SUCCESS; + + if (ComponentNumber > SpiInstance->NumberOfComponents) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Address =3D 0; + if (ComponentNumber =3D=3D FlashComponent1) { + Address =3D SpiInstance->Component1StartAddr; + } + + // + // Sends the command to the SPI interface to execute. + // + Status =3D SendSpiCmd ( + This, + FlashRegionAll, + FlashCycleReadJedecId, + Address, + ByteCount, + JedecId + ); + return Status; +} + +/** + Write the status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashWriteStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + IN UINT8 *StatusValue + ) +{ + EFI_STATUS Status; + + // + // Sends the command to the SPI interface to execute. + // + Status =3D SendSpiCmd ( + This, + FlashRegionAll, + FlashCycleWriteStatus, + 0, + ByteCount, + StatusValue + ); + return Status; +} + +/** + Read status register in the flash part. + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolFlashReadStatus ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 ByteCount, + OUT UINT8 *StatusValue + ) +{ + EFI_STATUS Status; + + // + // Sends the command to the SPI interface to execute. + // + Status =3D SendSpiCmd ( + This, + FlashRegionAll, + FlashCycleReadStatus, + 0, + ByteCount, + StatusValue + ); + return Status; +} + +/** + Get the SPI region base and size, based on the enum type + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor. + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base + @param[out] RegionSize The size for the Region 'n' + + @retval EFI_SUCCESS Read success + @retval EFI_INVALID_PARAMETER Invalid region type given + @retval EFI_DEVICE_ERROR The region is not used +**/ +EFI_STATUS +EFIAPI +SpiProtocolGetRegionAddress ( + IN PCH_SPI_PROTOCOL *This, + IN FLASH_REGION_TYPE FlashRegionType, + OUT UINT32 *BaseAddress, + OUT UINT32 *RegionSize + ) +{ + SPI_INSTANCE *SpiInstance; + UINTN PchSpiBar0; + UINT32 ReadValue; + + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); + + if (FlashRegionType >=3D FlashRegionMax) { + return EFI_INVALID_PARAMETER; + } + + if (FlashRegionType =3D=3D FlashRegionAll) { + *BaseAddress =3D 0; + *RegionSize =3D SpiInstance->TotalFlashSize; + return EFI_SUCCESS; + } + + PchSpiBar0 =3D AcquireSpiBar0 (SpiInstance); + ReadValue =3D MmioRead32 (PchSpiBar0 + (R_SPI_MEM_FREG0_FLASHD + (S_SPI_= MEM_FREGX * ((UINT32) FlashRegionType)))); + ReleaseSpiBar0 (SpiInstance); + + // + // If the region is not used, the Region Base is 7FFFh and Region Limit = is 0000h + // + if (ReadValue =3D=3D B_SPI_MEM_FREGX_BASE_MASK) { + return EFI_DEVICE_ERROR; + } + *BaseAddress =3D ((ReadValue & B_SPI_MEM_FREGX_BASE_MASK) >> N_SPI_MEM_F= REGX_BASE) << + N_SPI_MEM_FREGX_BASE_REPR; + // + // Region limit address Bits[11:0] are assumed to be FFFh + // + *RegionSize =3D ((((ReadValue & B_SPI_MEM_FREGX_LIMIT_MASK) >> N_SPI_MEM= _FREGX_LIMIT) + 1) << + N_SPI_MEM_FREGX_LIMIT_REPR) - *BaseAddress; + + return EFI_SUCCESS; +} + +/** + Read PCH Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadPchSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ) +{ + SPI_INSTANCE *SpiInstance; + UINT32 StrapFlashAddr; + EFI_STATUS Status; + + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); + + if (ByteCount =3D=3D 0) { + *(UINT16 *) SoftStrapValue =3D SpiInstance->PchStrapSize; + return EFI_SUCCESS; + } + + if ((SoftStrapAddr + ByteCount) > (UINT32) SpiInstance->PchStrapSize) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // PCH Strap Flash Address =3D FPSBA + RamAddr + // + StrapFlashAddr =3D SpiInstance->PchStrapBaseAddr + SoftStrapAddr; + + // + // Read PCH Soft straps from using execute command + // + Status =3D SendSpiCmd ( + This, + FlashRegionDescriptor, + FlashCycleRead, + StrapFlashAddr, + ByteCount, + SoftStrapValue + ); + return Status; +} + +/** + Read CPU Soft Strap Values + + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance. + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA. + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle. + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value. + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read. + + @retval EFI_SUCCESS Command succeed. + @retval EFI_INVALID_PARAMETER The parameters specified are not valid. + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally. +**/ +EFI_STATUS +EFIAPI +SpiProtocolReadCpuSoftStrap ( + IN PCH_SPI_PROTOCOL *This, + IN UINT32 SoftStrapAddr, + IN UINT32 ByteCount, + OUT VOID *SoftStrapValue + ) +{ + SPI_INSTANCE *SpiInstance; + UINT32 StrapFlashAddr; + EFI_STATUS Status; + + SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); + + if (ByteCount =3D=3D 0) { + *(UINT16 *) SoftStrapValue =3D SpiInstance->CpuStrapSize; + return EFI_SUCCESS; + } + + if ((SoftStrapAddr + ByteCount) > (UINT32) SpiInstance->CpuStrapSize) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // CPU Strap Flash Address =3D FCPUSBA + RamAddr + // + StrapFlashAddr =3D SpiInstance->CpuStrapBaseAddr + SoftStrapAddr; + + // + // Read Cpu Soft straps from using execute command + // + Status =3D SendSpiCmd ( + This, + FlashRegionDescriptor, + FlashCycleRead, + StrapFlashAddr, + ByteCount, + SoftStrapValue + ); + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiS= cheduleResetLib/BaseSiScheduleResetLib.c b/Silicon/Intel/CoffeelakeSiliconP= kg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c new file mode 100644 index 0000000000..dfc49d9bf6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiSchedule= ResetLib/BaseSiScheduleResetLib.c @@ -0,0 +1,70 @@ +/** @file + Reset scheduling library services + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + This function returns SiScheduleResetHob for library use +**/ +SI_SCHEDULE_RESET_HOB * +SiScheduleGetResetData ( + VOID + ); + +/** + This function performs reset based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is requ= ired +**/ +BOOLEAN +SiScheduleResetPerformReset ( + VOID + ) +{ + UINTN DataSize; + SI_SCHEDULE_RESET_HOB *SiScheduleResetHob; + + if (!SiScheduleResetIsRequired ()) { + return FALSE; + } + SiScheduleResetHob =3D SiScheduleGetResetData (); + + if (SiScheduleResetHob =3D=3D NULL) { + return TRUE; + } + + DEBUG ((DEBUG_INFO, "SiScheduleResetPerformReset : Reset Type =3D 0x%x\n= ", SiScheduleResetHob->ResetType)); + switch (SiScheduleResetHob->ResetType) { + case EfiResetWarm: + ResetWarm (); + break; + + case EfiResetCold: + ResetCold (); + break; + + case EfiResetShutdown: + ResetShutdown (); + break; + + case EfiResetPlatformSpecific: + DataSize =3D sizeof (PCH_RESET_DATA); + ResetPlatformSpecific (DataSize, &SiScheduleResetHob->ResetData); + break; + } + // Code should never reach here + ASSERT (FALSE); + return TRUE; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiS= cheduleResetLib/BaseSiScheduleResetLibCommon.c b/Silicon/Intel/CoffeelakeSi= liconPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibC= ommon.c new file mode 100644 index 0000000000..e1d783b2e2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiSchedule= ResetLib/BaseSiScheduleResetLibCommon.c @@ -0,0 +1,125 @@ +/** @file + Reset scheduling library services + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +/** + This function returns SiScheduleResetHob for library use +**/ +SI_SCHEDULE_RESET_HOB * +SiScheduleGetResetData ( + VOID + ) +{ + STATIC SI_SCHEDULE_RESET_HOB *SiScheduleResetHob =3D NULL; + SI_SCHEDULE_RESET_HOB *SiScheduleResetHobTemp; + VOID *HobPtr; + + if (SiScheduleResetHob !=3D NULL) { + return SiScheduleResetHob; + } + + HobPtr =3D GetFirstGuidHob (&gSiScheduleResetHobGuid); + if (HobPtr =3D=3D NULL) { + SiScheduleResetHobTemp =3D BuildGuidHob (&gSiScheduleResetHobGuid, siz= eof (SI_SCHEDULE_RESET_HOB)); + if (SiScheduleResetHobTemp =3D=3D NULL) { + ASSERT (FALSE); + return SiScheduleResetHobTemp; + } + SiScheduleResetHobTemp->ResetType =3D 0xFF; + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Init SiScheduleResetHob\= n")); + } else { + SiScheduleResetHobTemp =3D (SI_SCHEDULE_RESET_HOB*) GET_GUID_HOB_DATA = (HobPtr); + } + SiScheduleResetHob =3D SiScheduleResetHobTemp; + return SiScheduleResetHobTemp; +} + +/** + This function updates the reset information in SiScheduleResetHob + @param[in] ResetType UEFI defined reset type. + @param[in] ResetData Optional element used to introduce a platfor= m specific reset. + The exact type of the reset is defined by t= he EFI_GUID that follows + the Null-terminated Unicode string. +**/ +VOID +SiScheduleResetSetType ( + IN EFI_RESET_TYPE ResetType, + IN PCH_RESET_DATA *ResetData OPTIONAL + ) +{ + SI_SCHEDULE_RESET_HOB *SiScheduleResetHob; + if (ResetType > EfiResetPlatformSpecific) { + DEBUG ((DEBUG_INFO, "Unsupported Reset Type Requested\n")); + return; + } + SiScheduleResetHob =3D SiScheduleGetResetData (); + if (SiScheduleResetHob =3D=3D NULL) { + return; + } + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Current Reset Type =3D 0x%= x\n", SiScheduleResetHob->ResetType)); + if (SiScheduleResetHob->ResetType =3D=3D ResetType) { + DEBUG ((DEBUG_INFO, "Current Reset Type is same as requested Reset Typ= e\n")); + return; + } + if (SiScheduleResetHob->ResetType =3D=3D 0xFF) { + // + // Init Reset Type to lowest ResetType + // + SiScheduleResetHob->ResetType =3D EfiResetWarm; + } + // + // ResetType Priority set as : ResetPlatformSpecific(3) > ResetShutdown(= 2) > ResetCold(0) > ResetWarm(1) + // + switch (ResetType) { + case EfiResetWarm: + break; + + case EfiResetCold: + if (SiScheduleResetHob->ResetType =3D=3D EfiResetWarm) { + SiScheduleResetHob->ResetType =3D ResetType; + } + break; + + case EfiResetShutdown: + if (SiScheduleResetHob->ResetType < ResetType) + SiScheduleResetHob->ResetType =3D ResetType; + break; + + case EfiResetPlatformSpecific: + SiScheduleResetHob->ResetType =3D ResetType; + SiScheduleResetHob->ResetData =3D *ResetData; + break; + } + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : New Reset Type =3D 0x%x\n"= , SiScheduleResetHob->ResetType)); +} + +/** + This function returns TRUE or FALSE depending on whether a reset is requ= ired based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is requ= ired +**/ +BOOLEAN +SiScheduleResetIsRequired ( + VOID + ) +{ + VOID *HobPtr; + + HobPtr =3D NULL; + HobPtr =3D GetFirstGuidHob (&gSiScheduleResetHobGuid); + if (HobPtr =3D=3D NULL) { + return FALSE; + } + return TRUE; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiS= cheduleResetLib/BaseSiScheduleResetLibFsp.c b/Silicon/Intel/CoffeelakeSilic= onPkg/Pch/Library/Private/BaseSiScheduleResetLib/BaseSiScheduleResetLibFsp.c new file mode 100644 index 0000000000..15ac61a21b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/BaseSiSchedule= ResetLib/BaseSiScheduleResetLibFsp.c @@ -0,0 +1,61 @@ +/** @file + Reset scheduling library services + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + This function returns SiScheduleResetHob for library use +**/ +SI_SCHEDULE_RESET_HOB * +SiScheduleGetResetData ( + VOID + ); + +/** + This function performs reset based on SiScheduleResetHob + + @retval BOOLEAN The function returns FALSE if no reset is requ= ired +**/ +BOOLEAN +SiScheduleResetPerformReset ( + VOID + ) +{ + UINTN DataSize; + SI_SCHEDULE_RESET_HOB *SiScheduleResetHob; + + if (!SiScheduleResetIsRequired ()) { + return FALSE; + } + SiScheduleResetHob =3D SiScheduleGetResetData (); + + if (SiScheduleResetHob =3D=3D NULL) { + return TRUE; + } + + DEBUG ((DEBUG_INFO, "SiScheduleResetPerformReset : Reset Type =3D 0x%x\n= ", SiScheduleResetHob->ResetType)); + if (SiScheduleResetHob->ResetType =3D=3D EfiResetPlatformSpecific) { + DataSize =3D sizeof (PCH_RESET_DATA); + (*GetPeiServicesTablePointer ())->ResetSystem2 (SiScheduleResetHob->Re= setType, EFI_SUCCESS, DataSize, &SiScheduleResetHob->ResetData); + } else { + (*GetPeiServicesTablePointer ())->ResetSystem2 (SiScheduleResetHob->Re= setType, EFI_SUCCESS, 0, NULL); + } + // + // Code should never reach here + // + ASSERT (FALSE); + return TRUE; +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45898): https://edk2.groups.io/g/devel/message/45898 Mute This Topic: https://groups.io/mt/32918190/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45899+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45899+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001017; cv=none; d=zoho.com; s=zohoarc; b=JO8lYAWOj/zRibkP/EJtRA+QJVKn0mZxFSw+TY5LqXUkD+EkOuA4d+HQfWcvbA7xz3QV1i5VXXKUwmAzCngMR/z73wmqJCYtvIEMjQ6yUyN25yKQDIOPTJtpn3gVvYNi9g8XfLciLOAm32b4Gkf65rvNNncdmonb24FWj6OFyw4= ARC-Message-Signature: i=1; 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16 Aug 2019 17:16:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319301" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:53 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 22/37] CoffeelakeSiliconPkg/Pch: Add DXE private library instances Date: Fri, 16 Aug 2019 17:15:48 -0700 Message-Id: <20190817001603.30632-23-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001017; bh=lVsFSH4tPzuuM4YWqoGfPOi+ojaSiT6QvKvvRKIkAxs=; h=Cc:Date:From:Reply-To:Subject:To; b=Cu6LVu/zMwzq10YTQwnmFZZNiuGraXmok3FgmxrFdrzhOR2WROGQImC2M6l66ztwVbw V3PylIqL/pBLzwHULQ8X5XysYdg6ES1EJDDZSwQQjhK3gcb4vuD0UyDlgc/EO0rOg5m9R bsMuP/GAsyUJE+HanFgDlRWoV21yVgjkFfM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds PCH DXE private library class instances. * DxeGpioNameBufferLib * DxePchHdaLib Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLi= b/DxeGpioNameBufferLib.inf | 32 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/DxePch= HdaLib.inf | 43 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBufferLi= b/GpioNameBufferDxe.c | 20 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHda= Endpoints.c | 333 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHda= Lib.c | 886 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/PchHda= NhltConfig.c | 439 ++++++++++ 6 files changed, 1753 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpio= NameBufferLib/DxeGpioNameBufferLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg= /Pch/Library/Private/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf new file mode 100644 index 0000000000..0dc8f9749d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBuf= ferLib/DxeGpioNameBufferLib.inf @@ -0,0 +1,32 @@ +## @file +# Component description file for the DxeGpioMemLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeGpioNameBufferLib +FILE_GUID =3D 16EC6AA8-81D5-4847-B6CB-662CDAB863F2 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_DRIVER +LIBRARY_CLASS =3D GpioNameBufferLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] +BaseLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +GpioNameBufferDxe.c + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchH= daLib/DxePchHdaLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pri= vate/DxePchHdaLib/DxePchHdaLib.inf new file mode 100644 index 0000000000..a8a3f60b53 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/D= xePchHdaLib.inf @@ -0,0 +1,43 @@ +## @file +# Component information file for PCH HD Audio Library +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxePchHdaLib +FILE_GUID =3D DA915B7F-EE08-4C1D-B3D0-DE7C52AB155A +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchHdaLib + + +[LibraryClasses] +BaseLib +DebugLib +MemoryAllocationLib +BaseMemoryLib +PchInfoLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision + gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId + gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision + + +[Sources] +PchHdaLib.c +PchHdaEndpoints.c +PchHdaNhltConfig.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpio= NameBufferLib/GpioNameBufferDxe.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/= Library/Private/DxeGpioNameBufferLib/GpioNameBufferDxe.c new file mode 100644 index 0000000000..af53387faf --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxeGpioNameBuf= ferLib/GpioNameBufferDxe.c @@ -0,0 +1,20 @@ +/** @file + This file contains implementation of the GpioMemLib for DXE phase + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +STATIC CHAR8 mGpioNameBuffer[GPIO_NAME_LENGTH_MAX]; + +CHAR8* +GpioGetStaticNameBuffer ( + VOID + ) +{ + return mGpioNameBuffer; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchH= daLib/PchHdaEndpoints.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pr= ivate/DxePchHdaLib/PchHdaEndpoints.c new file mode 100644 index 0000000000..ea04512501 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/P= chHdaEndpoints.c @@ -0,0 +1,333 @@ +/** @file + This file contains HD Audio NHLT Endpoints definitions + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch1_48kHz16bitFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 1, + 48000, + 96000, + 2, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {16}, + KSAUDIO_SPEAKER_MONO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch2_48kHz16bitFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 2, + 48000, + 192000, + 4, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {16}, + KSAUDIO_SPEAKER_STEREO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch2_48kHz24bitFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 2, + 48000, + 384000, + 8, + 32, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {24}, + KSAUDIO_SPEAKER_STEREO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch2_48kHz32bitFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 2, + 48000, + 384000, + 8, + 32, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {32}, + KSAUDIO_SPEAKER_STEREO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch4_48kHz16bitFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 4, + 48000, + 384000, + 8, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {16}, + KSAUDIO_SPEAKER_QUAD, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE Ch4_48kHz32bitFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 4, + 48000, + 384000, + 8, + 32, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {32}, + KSAUDIO_SPEAKER_QUAD, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE NarrowbandFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 1, + 8000, + 16000, + 2, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {16}, + KSAUDIO_SPEAKER_MONO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE WidebandFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 1, + 16000, + 32000, + 2, + 16, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {16}, + KSAUDIO_SPEAKER_MONO, + KSDATAFORMAT_SUBTYPE_PCM +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST WAVEFORMATEXTENSIBLE A2dpFormat =3D +{ + { + WAVE_FORMAT_EXTENSIBLE, + 2, + 48000, + 384000, + 8, + 32, + sizeof (WAVEFORMATEXTENSIBLE) - sizeof (WAVEFORMATEX) + }, + {24}, + KSAUDIO_SPEAKER_STEREO, + KSDATAFORMAT_SUBTYPE_PCM +}; +GLOBAL_REMOVE_IF_UNREFERENCED +ENDPOINT_DESCRIPTOR HdaEndpointDmicX1 =3D { + 0, // EndpointDescriptorLength + HdaNhltLinkDmic, // LinkType + 0, // InstanceId + 0x8086, // HwVendorId + 0xae20, // HwDeviceId + 1, // HwRevisionId + 1, // HwSubsystemId + HdaNhltDeviceDmic, // DeviceType + 1, // Direction + 0, // VirtualBusId + { 0 }, // EndpointConfig + { 0 }, // FormatsConfig + { 0 } // DevicesInformation +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +ENDPOINT_DESCRIPTOR HdaEndpointDmicX2 =3D { + 0, // EndpointDescriptorLength + HdaNhltLinkDmic, // LinkType + 0, // InstanceId + 0x8086, // HwVendorId + 0xae20, // HwDeviceId + 1, // HwRevisionId + 1, // HwSubsystemId + HdaNhltDeviceDmic, // DeviceType + 1, // Direction + 0, // VirtualBusId + { 0 }, // EndpointConfig + { 0 }, // FormatsConfig + { 0 } // DevicesInformation +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +ENDPOINT_DESCRIPTOR HdaEndpointDmicX4 =3D { + 0, // EndpointDescriptorLength + HdaNhltLinkDmic, // LinkType + 0, // InstanceId + 0x8086, // HwVendorId + 0xae20, // HwDeviceId + 1, // HwRevisionId + 1, // HwSubsystemId + HdaNhltDeviceDmic, // DeviceType + 1, // Direction + 0, // VirtualBusId + { 0 }, // EndpointConfig + { 0 }, // FormatsConfig + { 0 } // DevicesInformation +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +ENDPOINT_DESCRIPTOR HdaEndpointBtRender =3D { + 0, // EndpointDescriptorLength + HdaNhltLinkSsp, // LinkType + 0, // InstanceId + 0x8086, // HwVendorId + 0xae30, // HwDeviceId + 1, // HwRevisionId + 1, // HwSubsystemId + HdaNhltDeviceBt, // DeviceType + 0, // Direction + 2, // VirtualBusId + { 0 }, // EndpointConfig + { 0 }, // FormatsConfig + { 0 } // DevicesInformation +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +ENDPOINT_DESCRIPTOR HdaEndpointBtCapture =3D { + 0, // EndpointDescriptorLength + HdaNhltLinkSsp, // LinkType + 0, // InstanceId + 0x8086, // HwVendorId + 0xae30, // HwDeviceId + 1, // HwRevisionId + 1, // HwSubsystemId + HdaNhltDeviceBt, // DeviceType + 1, // Direction + 2, // VirtualBusId + { 0 }, // EndpointConfig + { 0 }, // FormatsConfig + { 0 } // DevicesInformation +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +ENDPOINT_DESCRIPTOR HdaEndpointI2sRender =3D { + 0, // EndpointDescriptorLength + HdaNhltLinkSsp, // LinkType + 1, // InstanceId + 0x8086, // HwVendorId + 0xae34, // HwDeviceId + 1, // HwRevisionId + 1, // HwSubsystemId + HdaNhltDeviceI2s, // DeviceType + 0, // Direction + 0, // VirtualBusId + { 0 }, // EndpointConfig + { 0 }, // FormatsConfig + { 0 } // DevicesInformation +}; + +GLOBAL_REMOVE_IF_UNREFERENCED +ENDPOINT_DESCRIPTOR HdaEndpointI2sCapture =3D { + 0, // EndpointDescriptorLength + HdaNhltLinkSsp, // LinkType + 1, // InstanceId + 0x8086, // HwVendorId + 0xae34, // HwDeviceId + 1, // HwRevisionId + 1, // HwSubsystemId + HdaNhltDeviceI2s, // DeviceType + 1, // Direction + 0, // VirtualBusId + { 0 }, // EndpointConfig + { 0 }, // FormatsConfig + { 0 } // DevicesInformation +}; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT8 DmicX1Config[] =3D +{ + 0x00, // VirtualSlot + 0x00, // eIntcConfigTypeMicArray =3D 1 , eIntcConfigTypeGeneric =3D 0 +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicX1ConfigSize =3D sizeof (Dm= icX1Config); + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT8 DmicX2Config[] =3D +{ + 0x00, // VirtualSlot + 0x01, // eIntcConfigTypeMicArray =3D 1 , eIntcConfigTypeGeneric =3D 0 + 0x0A // ArrayType +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicX2ConfigSize =3D sizeof (Dm= icX2Config); + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT8 DmicX4Config[] =3D +{ + 0x00, // VirtualSlot + 0x01, // eIntcConfigTypeMicArray =3D 1 , eIntcConfigTypeGeneric =3D 0 + 0x0D // ArrayType +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicX4ConfigSize =3D sizeof (Dm= icX4Config); + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT8 BtConfig[] =3D {0}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 BtConfigSize =3D 0; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT8 I2sRender1Config[] =3D {0}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 I2sRender1ConfigSize =3D 0; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT8 I2sRender2Config[] =3D {0x01}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 I2sRender2ConfigSize =3D sizeof= (I2sRender2Config); + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT8 I2sCaptureConfig[] =3D {0}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 I2sCaptureConfigSize =3D 0; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST DEVICE_INFO I2sRenderDeviceInfo =3D +{ + "INT34C2", // DeviceId + 0x00, // DeviceInstanceId + 0x01 // DevicePortId +}; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST DEVICE_INFO I2sCaptureDeviceInfo =3D +{ + "INT34C2", // DeviceId + 0x00, // DeviceInstanceId + 0x01 // DevicePortId +}; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 NhltConfiguration[] =3D { 0xEFB= EADDE }; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 NhltConfigurationSize =3D sizeo= f (NhltConfiguration); + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchH= daLib/PchHdaLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/= DxePchHdaLib/PchHdaLib.c new file mode 100644 index 0000000000..a87509de1b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/P= chHdaLib.c @@ -0,0 +1,886 @@ +/** @file + PCH HD Audio Library implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Returns pointer to Endpoint ENDPOINT_DESCRIPTOR structure. + + @param[in] *NhltTable Endpoint for which Format address is retrieved + @param[in] FormatIndex Index of Format to be retrieved + + @retval Pointer to ENDPOINT_DESCRIPTOR structure with g= iven index +**/ +ENDPOINT_DESCRIPTOR * +GetNhltEndpoint ( + IN CONST NHLT_ACPI_TABLE *NhltTable, + IN CONST UINT8 EndpointIndex + ) +{ + UINT8 i; + ENDPOINT_DESCRIPTOR *Endpoint; + Endpoint =3D (ENDPOINT_DESCRIPTOR*) (NhltTable->EndpointDescriptors); + + if (EndpointIndex > NhltTable->EndpointCount) { + return NULL; + } + + for (i =3D 0; i < EndpointIndex; i++) { + Endpoint =3D (ENDPOINT_DESCRIPTOR*) ((UINT8*) (Endpoint) + Endpoint->E= ndpointDescriptorLength); + } + + return Endpoint; +} + +/** + Returns pointer to Endpoint Specific Configuration SPECIFIC_CONFIG struc= ture. + + @param[in] *Endpoint Endpoint for which config address is retrieved + + @retval Pointer to SPECIFIC_CONFIG structure with endpo= int's capabilities +**/ +SPECIFIC_CONFIG * +GetNhltEndpointDeviceCapabilities ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint + ) +{ + return (SPECIFIC_CONFIG*) (&Endpoint->EndpointConfig); +} + +/** + Returns pointer to all Formats Configuration FORMATS_CONFIG structure. + + @param[in] *Endpoint Endpoint for which Formats address is retrieved + + @retval Pointer to FORMATS_CONFIG structure +**/ +FORMATS_CONFIG * +GetNhltEndpointFormatsConfig ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint + ) +{ + FORMATS_CONFIG *FormatsConfig; + FormatsConfig =3D (FORMATS_CONFIG*) ((UINT8*) (&Endpoint->EndpointConfig) + + sizeof (Endpoint->EndpointConfig.Ca= pabilitiesSize) + + Endpoint->EndpointConfig.Capabiliti= esSize); + + return FormatsConfig; +} + +/** + Returns pointer to Format Configuration FORMAT_CONFIG structure. + + @param[in] *Endpoint Endpoint for which Format address is retrieved + @param[in] FormatIndex Index of Format to be retrieved + + @retval Pointer to FORMAT_CONFIG structure with given i= ndex +**/ +FORMAT_CONFIG * +GetNhltEndpointFormat ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint, + IN CONST UINT8 FormatIndex + ) +{ + UINT8 i; + UINT32 Length; + FORMATS_CONFIG *FormatsConfig; + FORMAT_CONFIG *Format; + + Length =3D 0; + FormatsConfig =3D GetNhltEndpointFormatsConfig (Endpoint); + Format =3D FormatsConfig->FormatsConfiguration; + + if (FormatIndex > FormatsConfig->FormatsCount) { + return NULL; + } + + for (i =3D 0; i < FormatIndex; i++) { + Length =3D sizeof (Format->Format) + Format->FormatConfiguration.Capab= ilitiesSize + + sizeof (Format->FormatConfiguration.CapabilitiesSize); + Format =3D (FORMAT_CONFIG*) ((UINT8*) (Format) + Length); + } + + return Format; +} + +/** + Returns pointer to all Device Information DEVICES_INFO structure. + + @param[in] *Endpoint Endpoint for which DevicesInfo address is retri= eved + + @retval Pointer to DEVICES_INFO structure +**/ +DEVICES_INFO * +GetNhltEndpointDevicesInfo ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint + ) +{ + DEVICES_INFO *DevicesInfo; + FORMATS_CONFIG *FormatsConfig; + FORMAT_CONFIG *Format; + + FormatsConfig =3D GetNhltEndpointFormatsConfig (Endpoint); + Format =3D GetNhltEndpointFormat (Endpoint, FormatsConfig->FormatsCount); + DevicesInfo =3D (DEVICES_INFO*) ((UINT8*) Format); + + return DevicesInfo; +} + +/** + Returns pointer to Device Information DEVICES_INFO structure. + + @param[in] *Endpoint Endpoint for which Device Info address is ret= rieved + @param[in] DeviceInfoIndex Index of Device Info to be retrieved + + @retval Pointer to DEVICE_INFO structure with given i= ndex +**/ +DEVICE_INFO * +GetNhltEndpointDeviceInfo ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint, + IN CONST UINT8 DeviceInfoIndex + ) +{ + DEVICES_INFO *DevicesInfo; + DEVICE_INFO *DeviceInfo; + + DevicesInfo =3D GetNhltEndpointDevicesInfo (Endpoint); + DeviceInfo =3D DevicesInfo->DeviceInformation; + + if (DevicesInfo =3D=3D NULL) { + return NULL; + } + + if (DeviceInfoIndex > DevicesInfo->DeviceInfoCount) { + return NULL; + } + + DeviceInfo =3D (DEVICE_INFO*) ((UINT8*) (DeviceInfo) + sizeof (*DeviceIn= fo) * DeviceInfoIndex); + + return DeviceInfo; +} + +/** + Returns pointer to OED Configuration SPECIFIC_CONFIG structure. + + @param[in] *NhltTable NHLT table for which OED address is retrieved + + @retval Pointer to SPECIFIC_CONFIG structure with NHLT = capabilities +**/ +SPECIFIC_CONFIG * +GetNhltOedConfig ( + IN CONST NHLT_ACPI_TABLE *NhltTable + ) +{ + ENDPOINT_DESCRIPTOR *Endpoint; + SPECIFIC_CONFIG *OedConfig; + + Endpoint =3D GetNhltEndpoint (NhltTable, (NhltTable->EndpointCount)); + OedConfig =3D (SPECIFIC_CONFIG*) ((UINT8*) (Endpoint)); + + return OedConfig; +} + +/** + Prints Format configuration. + + @param[in] *Format Format to be printed + + @retval None +**/ +VOID +NhltFormatDump ( + IN CONST FORMAT_CONFIG *Format + ) +{ + UINT32 i; + + DEBUG ((DEBUG_INFO, "------------------------------- FORMAT ------------= -------------------\n")); + DEBUG ((DEBUG_INFO, " Format->Format.Format.wFormatTag =3D 0x%x\n",= Format->Format.Format.wFormatTag)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.nChannels =3D %d\n", F= ormat->Format.Format.nChannels)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.nSamplesPerSec =3D %d\n", F= ormat->Format.Format.nSamplesPerSec)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.nAvgBytesPerSec =3D %d\n", F= ormat->Format.Format.nAvgBytesPerSec)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.nBlockAlign =3D %d\n", F= ormat->Format.Format.nBlockAlign)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.wBitsPerSample =3D %d\n", F= ormat->Format.Format.wBitsPerSample)); + DEBUG ((DEBUG_INFO, " Format->Format.Format.cbSize =3D %d\n", F= ormat->Format.Format.cbSize)); + DEBUG ((DEBUG_INFO, " Format->Format.Samples =3D %d\n", F= ormat->Format.Samples)); + DEBUG ((DEBUG_INFO, " Format->Format.dwChannelMask =3D 0x%x\n",= Format->Format.dwChannelMask)); + DEBUG ((DEBUG_INFO, " Format->Format.SubFormat =3D %g\n", F= ormat->Format.SubFormat)); + + + DEBUG ((DEBUG_INFO, " Format->FormatConfiguration.CapabilitiesSize =3D %= d B\n", Format->FormatConfiguration.CapabilitiesSize)); + DEBUG ((DEBUG_VERBOSE, " Format->FormatConfiguration.Capabilities:")); + for (i =3D 0; i < ( Format->FormatConfiguration.CapabilitiesSize ) ; i+= +) { + if (i % 16 =3D=3D 0) { + DEBUG ((DEBUG_VERBOSE, "\n")); + } + DEBUG ((DEBUG_VERBOSE, "0x%02x, ", Format->FormatConfiguration.Capabil= ities[i])); + } + DEBUG ((DEBUG_VERBOSE, "\n")); +} + +/** + Prints Device Information. + + @param[in] *DeviceInfo DeviceInfo to be printed + + @retval None +**/ +VOID +NhltDeviceInfoDump ( + IN CONST DEVICE_INFO *DeviceInfo + ) +{ + DEBUG ((DEBUG_INFO, "----------------------------- DEVICE INFO ---------= -------------------\n")); + DEBUG ((DEBUG_INFO, " DeviceInfo->DeviceId =3D %a\n", DeviceIn= fo->DeviceId)); + DEBUG ((DEBUG_INFO, " DeviceInfo->DeviceInstanceId =3D 0x%x\n", DeviceIn= fo->DeviceInstanceId)); + DEBUG ((DEBUG_INFO, " DeviceInfo->DevicePortId =3D 0x%x\n", DeviceIn= fo->DevicePortId)); +} + +/** + Prints Endpoint configuration. + + @param[in] *Endpoint Endpoint to be printed + + @retval None +**/ +VOID +NhltEndpointDump ( + IN CONST ENDPOINT_DESCRIPTOR *Endpoint + ) +{ + UINT8 i; + FORMATS_CONFIG *FormatsConfigs; + FORMAT_CONFIG *Format; + DEVICES_INFO *DevicesInfo; + DEVICE_INFO *DeviceInfo; + + DEBUG ((DEBUG_INFO, "------------------------------ ENDPOINT -----------= -------------------\n")); + DEBUG ((DEBUG_INFO, " Endpoint->DeviceDescriptorLength =3D %d B\n", Endp= oint->EndpointDescriptorLength)); + DEBUG ((DEBUG_INFO, " Endpoint->LinkType =3D 0x%x\n", Endp= oint->LinkType)); + DEBUG ((DEBUG_INFO, " Endpoint->InstanceId =3D 0x%x\n", Endp= oint->InstanceId)); + DEBUG ((DEBUG_INFO, " Endpoint->HwVendorId =3D 0x%x\n", Endp= oint->HwVendorId)); + DEBUG ((DEBUG_INFO, " Endpoint->HwDeviceId =3D 0x%x\n", Endp= oint->HwDeviceId)); + DEBUG ((DEBUG_INFO, " Endpoint->HwRevisionId =3D 0x%x\n", Endp= oint->HwRevisionId)); + DEBUG ((DEBUG_INFO, " Endpoint->HwSubsystemId =3D 0x%x\n", Endp= oint->HwSubsystemId)); + DEBUG ((DEBUG_INFO, " Endpoint->DeviceType =3D 0x%x\n", Endp= oint->DeviceType)); + DEBUG ((DEBUG_INFO, " Endpoint->Direction =3D 0x%x\n", Endp= oint->Direction)); + DEBUG ((DEBUG_INFO, " Endpoint->VirtualBusId =3D 0x%x\n", Endp= oint->VirtualBusId)); + + DEBUG ((DEBUG_INFO, " Endpoint->EndpointConfig.CapabilitiesSize =3D %d B= \n", Endpoint->EndpointConfig.CapabilitiesSize)); + DEBUG ((DEBUG_VERBOSE, " Endpoint->EndpointConfig.Capabilities:")); + for (i =3D 0; i < (Endpoint->EndpointConfig.CapabilitiesSize ) ; i++) { + if (i % 16 =3D=3D 0) DEBUG ((DEBUG_VERBOSE, "\n")); + DEBUG ((DEBUG_VERBOSE, "0x%02x, ", Endpoint->EndpointConfig.Capabiliti= es[i])); + } + + FormatsConfigs =3D GetNhltEndpointFormatsConfig (Endpoint); + + DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, " Endpoint->FormatsConfig.FormatsCount =3D %d\n", Fo= rmatsConfigs->FormatsCount)); + for (i =3D 0; i < FormatsConfigs->FormatsCount; i++) { + Format =3D GetNhltEndpointFormat (Endpoint, i); + if (Format !=3D NULL) { + NhltFormatDump (Format); + } + } + + DevicesInfo =3D GetNhltEndpointDevicesInfo (Endpoint); + if (DevicesInfo !=3D NULL) { + DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, " Endpoint->DevicesInfo.DeviceInfoCount =3D %d\n",= DevicesInfo->DeviceInfoCount)); + for (i =3D 0; i < DevicesInfo->DeviceInfoCount; i++) { + DeviceInfo =3D GetNhltEndpointDeviceInfo (Endpoint, i); + if (DeviceInfo !=3D NULL) { + NhltDeviceInfoDump (DeviceInfo); + } + } + } + DEBUG ((DEBUG_VERBOSE, "\n")); +} + +/** + Prints OED (Offload Engine Driver) configuration. + + @param[in] *OedConfig OED to be printed + + @retval None +**/ +VOID +NhltOedConfigDump ( + IN CONST SPECIFIC_CONFIG *OedConfig + ) +{ + UINT8 i; + + DEBUG ((DEBUG_INFO, "-------------------------- OED CONFIGURATION ------= -------------------\n")); + DEBUG ((DEBUG_INFO, " OedConfig->CapabilitiesSize =3D %d B\n", OedConfig= ->CapabilitiesSize)); + DEBUG ((DEBUG_VERBOSE, " OedConfig->Capabilities:")); + for (i =3D 0; i < (OedConfig->CapabilitiesSize) ; i++) { + if (i % 16 =3D=3D 0) DEBUG ((DEBUG_VERBOSE, "\n")); + DEBUG ((DEBUG_VERBOSE, "0x%02x, ", OedConfig->Capabilities[i])); + } + + DEBUG ((DEBUG_VERBOSE, "\n")); +} + +/** + Prints NHLT (Non HDA-Link Table) to be exposed via ACPI (aka. OED (Offlo= ad Engine Driver) Configuration Table). + + @param[in] *NhltTable The NHLT table to print + + @retval None +**/ +VOID +NhltAcpiTableDump ( + IN NHLT_ACPI_TABLE *NhltTable + ) +{ + DEBUG_CODE_BEGIN (); + UINT8 i; + + DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, "--- NHLT ACPI Table Dump [OED (Offload Engine Drive= r) Configuration] ---\n")); + + DEBUG ((DEBUG_INFO, "sizeof NHLT_ACPI_TABLE =3D %d B\n", sizeof (NHLT_AC= PI_TABLE))); + DEBUG ((DEBUG_INFO, "sizeof EFI_ACPI_DESCRIPTION_HEADER =3D %d B\n", siz= eof (EFI_ACPI_DESCRIPTION_HEADER))); + DEBUG ((DEBUG_INFO, "sizeof ENDPOINT_DESCRIPTOR =3D %d B\n", sizeof (END= POINT_DESCRIPTOR))); + DEBUG ((DEBUG_INFO, "sizeof SPECIFIC_CONFIG =3D %d B\n", sizeof (SPECIFI= C_CONFIG))); + DEBUG ((DEBUG_INFO, "sizeof FORMATS_CONFIG =3D %d B\n", sizeof (FORMATS_= CONFIG))); + DEBUG ((DEBUG_INFO, "sizeof FORMAT_CONFIG =3D %d B\n", sizeof (FORMAT_CO= NFIG))); + DEBUG ((DEBUG_INFO, "sizeof WAVEFORMATEXTENSIBLE =3D %d B\n", sizeof (WA= VEFORMATEXTENSIBLE))); + DEBUG ((DEBUG_INFO, "sizeof DEVICES_INFO =3D %d B\n", sizeof (DEVICES_IN= FO))); + DEBUG ((DEBUG_INFO, "sizeof DEVICE_INFO =3D %d B\n", sizeof (DEVICE_INFO= ))); + + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.Signature =3D 0x%08x\= n", NhltTable->Header.Signature)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.Length =3D 0x%08x\= n", NhltTable->Header.Length)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.Revision =3D 0x%02x\= n", NhltTable->Header.Revision)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.Checksum =3D 0x%02x\= n", NhltTable->Header.Checksum)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.OemId =3D %a\n", = NhltTable->Header.OemId)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.OemTableId =3D 0x%lx\n= ", NhltTable->Header.OemTableId)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.OemRevision =3D 0x%08x\= n", NhltTable->Header.OemRevision)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.CreatorId =3D 0x%08x\= n", NhltTable->Header.CreatorId)); + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE Header.CreatorRevision =3D 0x%08x\= n", NhltTable->Header.CreatorRevision)); + DEBUG ((DEBUG_INFO, "\n")); + + DEBUG ((DEBUG_INFO, " NHLT_ACPI_TABLE EndpointCount =3D %d\n", NhltTable= ->EndpointCount)); + for (i =3D 0; i < NhltTable->EndpointCount; i++) { + NhltEndpointDump (GetNhltEndpoint (NhltTable, i)); + } + + NhltOedConfigDump (GetNhltOedConfig (NhltTable)); + DEBUG ((DEBUG_INFO, "---------------------------------------------------= -------------------\n")); + + DEBUG_CODE_END (); +} + +/** + Constructs FORMATS_CONFIGS structure based on given formats list. + + @param[in][out] *Endpoint Endpoint for which format structures are c= reated + @param[in] FormatBitmask Bitmask of formats supported for given end= point + + @retval Size of created FORMATS_CONFIGS structure +**/ +UINT32 +NhltFormatsConstructor ( + IN OUT ENDPOINT_DESCRIPTOR *Endpoint, + IN CONST UINT32 FormatsBitmask + ) +{ + FORMATS_CONFIG *FormatsConfig; + FORMAT_CONFIG *Format; + UINT8 FormatIndex; + UINT32 FormatsConfigLength; + + DEBUG ((DEBUG_INFO, "NhltFormatsConstructor() Start, FormatsBitmask =3D = 0x%08x\n", FormatsBitmask)); + + FormatsConfig =3D NULL; + FormatIndex =3D 0; + FormatsConfigLength =3D 0; + + if (!FormatsBitmask) { + DEBUG ((DEBUG_WARN, "No supported format found!\n")); + return 0; + } + + FormatsConfig =3D GetNhltEndpointFormatsConfig (Endpoint); + FormatsConfig->FormatsCount =3D 0; + + if (FormatsBitmask & B_HDA_DMIC_2CH_48KHZ_16BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_DMIC_2CH_48KHZ_16BIT_FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &Ch2_48kHz16bitFormat, sizeof (WAVEFORMA= TEXTENSIBLE)); + Format->FormatConfiguration.CapabilitiesSize =3D DmicStereo16BitForm= atConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicStereo16BitFo= rmatConfig, DmicStereo16BitFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_DMIC_2CH_48KHZ_32BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_DMIC_2CH_48KHZ_32BIT_FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &Ch2_48kHz32bitFormat, sizeof (WAVEFORMA= TEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize =3D DmicStereo32BitForm= atConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicStereo32BitFo= rmatConfig, DmicStereo32BitFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_DMIC_4CH_48KHZ_16BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_DMIC_4CH_48KHZ_16BIT_FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &Ch4_48kHz16bitFormat, sizeof (WAVEFORMA= TEXTENSIBLE)); + Format->FormatConfiguration.CapabilitiesSize =3D DmicQuad16BitFormat= ConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicQuad16BitForm= atConfig, DmicQuad16BitFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_DMIC_4CH_48KHZ_32BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_DMIC_4CH_48KHZ_32BIT_FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &Ch4_48kHz32bitFormat, sizeof (WAVEFORMA= TEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize =3D DmicQuad32BitFormat= ConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicQuad32BitForm= atConfig, DmicQuad32BitFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_DMIC_1CH_48KHZ_16BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_DMIC_1CH_48KHZ_16BIT_FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &Ch1_48kHz16bitFormat, sizeof (WAVEFORMA= TEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize =3D DmicMono16BitFormat= ConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, DmicMono16BitForm= atConfig, DmicMono16BitFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_BT_NARROWBAND_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_BT_NARROWBAND_FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &NarrowbandFormat, sizeof (WAVEFORMATEXT= ENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize =3D BtFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, BtFormatConfig, B= tFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_BT_WIDEBAND_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_BT_WIDEBAND_FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &WidebandFormat, sizeof (WAVEFORMATEXTEN= SIBLE)); + + Format->FormatConfiguration.CapabilitiesSize =3D BtFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, BtFormatConfig, B= tFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_BT_A2DP_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_BT_A2DP_FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &A2dpFormat, sizeof (WAVEFORMATEXTENSIBL= E)); + + Format->FormatConfiguration.CapabilitiesSize =3D BtFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, BtFormatConfig, B= tFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_I2S_RTK274_RENDER_4CH_48KHZ_24BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_I2S_RTK274_RENDER_4CH_48KHZ_24BIT_F= ORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &Ch2_48kHz24bitFormat, sizeof (WAVEFORMA= TEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize =3D I2sRtk274Render4ch4= 8kHz24bitFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, I2sRtk274Render4c= h48kHz24bitFormatConfig, I2sRtk274Render4ch48kHz24bitFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + if (FormatsBitmask & B_HDA_I2S_RTK274_CAPTURE_4CH_48KHZ_24BIT_FORMAT) { + DEBUG ((DEBUG_INFO, "Format: B_HDA_I2S_RTK274_CAPTURE_4CH_48KHZ_24BIT_= FORMAT\n")); + + Format =3D GetNhltEndpointFormat (Endpoint, FormatIndex++); + if (Format !=3D NULL) { + CopyMem (&(Format->Format), &Ch2_48kHz24bitFormat, sizeof (WAVEFORMA= TEXTENSIBLE)); + + Format->FormatConfiguration.CapabilitiesSize =3D I2sRtk274Capture4ch= 48kHz24bitFormatConfigSize; + CopyMem (Format->FormatConfiguration.Capabilities, I2sRtk274Capture4= ch48kHz24bitFormatConfig, I2sRtk274Capture4ch48kHz24bitFormatConfigSize); + + FormatsConfigLength +=3D sizeof (*Format) + - sizeof (Format->FormatConfiguration.Capabilities) + + Format->FormatConfiguration.CapabilitiesSize; + FormatsConfig->FormatsCount++; + } + } + + DEBUG ((DEBUG_INFO, "NhltFormatsConstructor() End, FormatsCount =3D %d, = FormatsConfigLength =3D %d B\n", FormatsConfig->FormatsCount, FormatsConfig= Length)); + return FormatsConfigLength; +} + +/** + Constructs DEVICES_INFO structure based on given device info list. + + @param[in][out] *Endpoint Endpoint for which device info structures= are created + @param[in] DevicesBitmask Bitmask of devices supported for given en= dpoint + + @retval Size of created DEVICES_INFO structure +**/ +UINT32 +NhltDevicesInfoConstructor ( + IN OUT ENDPOINT_DESCRIPTOR *Endpoint, + IN CONST UINT32 DevicesBitmask + ) +{ + DEVICES_INFO *DevicesInfo; + DEVICE_INFO *DeviceInfo; + UINT8 DeviceIndex; + UINT32 DevicesInfoLength; + + DEBUG ((DEBUG_INFO, "NhltDevicesInfoConstructor() Start, DevicesBitmask = =3D 0x%08x\n", DevicesBitmask)); + + DevicesInfo =3D NULL; + DeviceIndex =3D 0; + DevicesInfoLength =3D 0; + + if (!DevicesBitmask) { + return 0; + } + + DevicesInfo =3D GetNhltEndpointDevicesInfo (Endpoint); + if (DevicesInfo =3D=3D NULL) { + return 0; + } + DevicesInfo->DeviceInfoCount =3D 0; + + if (DevicesBitmask & B_HDA_I2S_RENDER_DEVICE_INFO) { + DEBUG ((DEBUG_INFO, "DeviceInfo: B_HDA_I2S_RENDER_DEVICE_INFO\n")); + + DeviceInfo =3D GetNhltEndpointDeviceInfo (Endpoint, DeviceIndex++); + if (DeviceInfo !=3D NULL) { + CopyMem (DeviceInfo, &I2sRenderDeviceInfo, sizeof (DEVICE_INFO)); + DevicesInfo->DeviceInfoCount++; + } + } else if (DevicesBitmask & B_HDA_I2S_CAPTURE_DEVICE_INFO) { + DEBUG ((DEBUG_INFO, "DeviceInfo: B_HDA_I2S_CAPTURE_DEVICE_INFO\n")); + + DeviceInfo =3D GetNhltEndpointDeviceInfo (Endpoint, DeviceIndex++); + if (DeviceInfo !=3D NULL) { + CopyMem (DeviceInfo, &I2sCaptureDeviceInfo, sizeof (DEVICE_INFO)); + DevicesInfo->DeviceInfoCount++; + } + } + + DevicesInfoLength =3D DevicesInfo->DeviceInfoCount * sizeof (DEVICE_INFO= ); + + DEBUG ((DEBUG_INFO, "NhltDevicesInfoConstructor() End, DevicesCount =3D = %d, DevicesInfoLength =3D %d B\n", DevicesInfo->DeviceInfoCount, DevicesInf= oLength)); + return DevicesInfoLength; +} + +/** + Constructs NHLT_ENDPOINT structure based on given endpoint type. + + @param[in][out] *NhltTable NHLT table for which endpoint is= created + @param[in] EndpointType Type of endpoint to be created + @param[in] EndpointFormatsBitmask Bitmask of formats supported by = endpoint + @param[in] EndpointDevicesBitmask Bitmask of device info for endpo= int + @param[in] EndpointIndex Endpoint index in NHLT table + + @retval Size of created NHLT_ENDPOINT structure +**/ +UINT32 +NhltEndpointConstructor ( + IN OUT NHLT_ACPI_TABLE *NhltTable, + IN NHLT_ENDPOINT EndpointType, + IN UINT32 EndpointFormatsBitmask, + IN UINT32 EndpointDevicesBitmask, + IN UINT8 EndpointIndex + ) +{ + + ENDPOINT_DESCRIPTOR *Endpoint; + SPECIFIC_CONFIG *EndpointConfig; + CONST UINT8 *EndpointConfigBuffer; + UINT32 EndpointConfigBufferSize; + UINT32 EndpointDescriptorLength; + + DEBUG ((DEBUG_INFO, "NhltEndpointConstructor() Start, EndpointIndex =3D = %d\n", EndpointIndex)); + + EndpointDescriptorLength =3D 0; + Endpoint =3D GetNhltEndpoint (NhltTable, EndpointIndex); + if (Endpoint =3D=3D NULL) { + return 0; + } + EndpointDescriptorLength =3D sizeof (ENDPOINT_DESCRIPTOR) + - sizeof (SPECIFIC_CONFIG) + - sizeof (FORMAT_CONFIG) + - sizeof (DEVICE_INFO); + + switch (EndpointType) { + case HdaDmicX1: + DEBUG ((DEBUG_INFO, "Endpoint: HdaDmicX1\n")); + CopyMem (Endpoint, &HdaEndpointDmicX1, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer =3D DmicX1Config; + EndpointConfigBufferSize =3D DmicX1ConfigSize; + break; + case HdaDmicX2: + DEBUG ((DEBUG_INFO, "Endpoint: HdaDmicX2\n")); + CopyMem (Endpoint, &HdaEndpointDmicX2, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer =3D DmicX2Config; + EndpointConfigBufferSize =3D DmicX2ConfigSize; + break; + case HdaDmicX4: + DEBUG ((DEBUG_INFO, "Endpoint: HdaDmicX4\n")); + CopyMem (Endpoint, &HdaEndpointDmicX4, sizeof (ENDPOINT_DESCRIPTOR)); + EndpointConfigBuffer =3D DmicX4Config; + EndpointConfigBufferSize =3D DmicX4ConfigSize; + break; + case HdaBtRender: + DEBUG ((DEBUG_INFO, "Endpoint: HdaBtRender\n")); + CopyMem (Endpoint, &HdaEndpointBtRender, sizeof (ENDPOINT_DESCRIPTOR= )); + if (IsPchH ()) { + Endpoint->VirtualBusId =3D 0; + } + + EndpointConfigBuffer =3D BtConfig; + EndpointConfigBufferSize =3D BtConfigSize; + break; + case HdaBtCapture: + DEBUG ((DEBUG_INFO, "Endpoint: HdaBtCapture\n")); + CopyMem (Endpoint, &HdaEndpointBtCapture, sizeof (ENDPOINT_DESCRIPTO= R)); + if (IsPchH ()) { + Endpoint->VirtualBusId =3D 0; + } + + EndpointConfigBuffer =3D BtConfig; + EndpointConfigBufferSize =3D BtConfigSize; + break; + case HdaI2sRender1: + DEBUG ((DEBUG_INFO, "Endpoint: HdaI2sRender1\n")); + CopyMem (Endpoint, &HdaEndpointI2sRender, sizeof (ENDPOINT_DESCRIPTO= R)); + EndpointConfigBuffer =3D I2sRender1Config; + EndpointConfigBufferSize =3D I2sRender1ConfigSize; + break; + case HdaI2sRender2: + DEBUG ((DEBUG_INFO, "Endpoint: HdaI2sRender2\n")); + CopyMem (Endpoint, &HdaEndpointI2sRender, sizeof (ENDPOINT_DESCRIPTO= R)); + EndpointConfigBuffer =3D I2sRender2Config; + EndpointConfigBufferSize =3D I2sRender2ConfigSize; + break; + case HdaI2sCapture: + DEBUG ((DEBUG_INFO, "Endpoint: HdaI2sCapture\n")); + CopyMem (Endpoint, &HdaEndpointI2sCapture, sizeof (ENDPOINT_DESCRIPT= OR)); + EndpointConfigBuffer =3D I2sCaptureConfig; + EndpointConfigBufferSize =3D I2sCaptureConfigSize; + break; + default: + DEBUG ((DEBUG_WARN, "Unknown endpoint!\n")); + return 0; + } + + EndpointConfig =3D GetNhltEndpointDeviceCapabilities (Endpoint); + EndpointConfig->CapabilitiesSize =3D EndpointConfigBufferSize; + CopyMem (EndpointConfig->Capabilities, EndpointConfigBuffer, EndpointCon= fig->CapabilitiesSize); + EndpointDescriptorLength +=3D sizeof (*EndpointConfig) + - sizeof (EndpointConfig->Capabilities) + + EndpointConfig->CapabilitiesSize; + + EndpointDescriptorLength +=3D NhltFormatsConstructor (Endpoint, Endpoint= FormatsBitmask); + EndpointDescriptorLength +=3D NhltDevicesInfoConstructor (Endpoint, Endp= ointDevicesBitmask); + + Endpoint->EndpointDescriptorLength =3D EndpointDescriptorLength; + + DEBUG ((DEBUG_INFO, "NhltEndpointConstructor() End, EndpointDescriptorLe= ngth =3D %d B\n", Endpoint->EndpointDescriptorLength)); + return Endpoint->EndpointDescriptorLength; +} + +/** + Constructs SPECIFIC_CONFIG structure for OED configuration. + + @param[in][out] *NhltTable NHLT table for which OED config is created + + @retval Size of created SPECIFIC_CONFIG structure +**/ +UINT32 +NhltOedConfigConstructor ( + IN OUT NHLT_ACPI_TABLE *NhltTable + ) +{ + SPECIFIC_CONFIG *OedConfig; + UINT32 OedConfigLength; + + OedConfigLength =3D 0; + OedConfig =3D GetNhltOedConfig (NhltTable); + + OedConfig->CapabilitiesSize =3D NhltConfigurationSize; + CopyMem (OedConfig->Capabilities, (UINT8*) NhltConfiguration, NhltConfig= urationSize); + + OedConfigLength =3D sizeof (*OedConfig) + - sizeof (OedConfig->Capabilities) + + OedConfig->CapabilitiesSize; + + return OedConfigLength; +} + +/** + Constructs NHLT_ACPI_TABLE structure based on given Endpoints list. + + @param[in] *EndpointTable List of endpoints for NHLT + @param[in][out] **NhltTable NHLT table to be created + @param[in][out] *NhltTableSize Size of created NHLT table + + @retval EFI_SUCCESS NHLT created successfully + @retval EFI_BAD_BUFFER_SIZE Not enough resources to allocate NHLT +**/ +EFI_STATUS +NhltConstructor ( + IN PCH_HDA_NHLT_ENDPOINTS *EndpointTable, + IN OUT NHLT_ACPI_TABLE **NhltTable, + IN OUT UINT32 *NhltTableSize + ) +{ + EFI_STATUS Status; + UINT8 Index; + UINT32 TableSize; + UINT32 EndpointDescriptorsLength; + UINT32 OedConfigLength; + NHLT_ACPI_TABLE *Table; + + + Status =3D EFI_SUCCESS; + TableSize =3D PCH_HDA_NHLT_TABLE_SIZE; + EndpointDescriptorsLength =3D 0; + OedConfigLength =3D 0; + + Table =3D AllocateZeroPool (TableSize); + + if (Table =3D=3D NULL) { + return EFI_BAD_BUFFER_SIZE; + } + + Table->EndpointCount =3D 0; + + for (Index =3D 0; Index < HdaEndpointMax; Index++) { + if (EndpointTable[Index].Enable =3D=3D TRUE) { + EndpointDescriptorsLength +=3D NhltEndpointConstructor (Table, + EndpointTable[Index].EndpointType, + EndpointTable[Index].EndpointFormatsB= itmask, + EndpointTable[Index].EndpointDevicesB= itmask, + Table->EndpointCount++); + } + } + DEBUG ((DEBUG_INFO, "NhltConstructor: EndpointCount =3D %d, All Endpoint= DescriptorsLength =3D %d B\n", Table->EndpointCount, EndpointDescriptorsLen= gth)); + + OedConfigLength =3D NhltOedConfigConstructor (Table); + DEBUG ((DEBUG_INFO, "NhltConstructor: OedConfigLength =3D %d B\n", OedCo= nfigLength)); + + TableSize =3D EndpointDescriptorsLength + OedConfigLength; + + *NhltTableSize =3D TableSize; + *NhltTable =3D Table; + + return Status; +} + +/** + Constructs EFI_ACPI_DESCRIPTION_HEADER structure for NHLT table. + + @param[in][out] *NhltTable NHLT table for which header will b= e created + @param[in] NhltTableSize Size of NHLT table + + @retval None +**/ +VOID +NhltAcpiHeaderConstructor ( + IN OUT NHLT_ACPI_TABLE *NhltTable, + IN UINT32 NhltTableSize + ) +{ + DEBUG ((DEBUG_INFO, "NhltAcpiHeaderConstructor() Start\n")); + + // Header + NhltTable->Header.Signature =3D NHLT_ACPI_TABLE_SIGNATURE; + NhltTable->Header.Length =3D (UINT32) (NhltTableSize + sizeof (NHLT_ACPI= _TABLE) - sizeof (ENDPOINT_DESCRIPTOR) - sizeof (SPECIFIC_CONFIG)); + NhltTable->Header.Revision =3D 0x0; + NhltTable->Header.Checksum =3D 0x0; + + CopyMem (NhltTable->Header.OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeo= f (NhltTable->Header.OemId)); + NhltTable->Header.OemTableId =3D PcdGet64 (PcdAcpiDefaultOemTableId= ); + NhltTable->Header.OemRevision =3D PcdGet32 (PcdAcpiDefaultOemRevisio= n); + NhltTable->Header.CreatorId =3D PcdGet32 (PcdAcpiDefaultCreatorId); + NhltTable->Header.CreatorRevision =3D PcdGet32 (PcdAcpiDefaultCreatorRev= ision); + + DEBUG ((DEBUG_INFO, "NhltAcpiHeaderConstructor(), NhltAcpiTable->Header.= Length =3D %d B\n", NhltTable->Header.Length)); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchH= daLib/PchHdaNhltConfig.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/P= rivate/DxePchHdaLib/PchHdaNhltConfig.c new file mode 100644 index 0000000000..301b1f8d10 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/DxePchHdaLib/P= chHdaNhltConfig.c @@ -0,0 +1,439 @@ +/** @file + This file contains HD Audio NHLT Configuration BLOBs + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// CFL NHLT Configuration BLOBs +// + +// +// DMIC Configuration BLOBs +// +// DMIC Config 2 channels, 16 bits, 2.4Mhz BCLK +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicStereo16BitFormatConfig[] =3D +{ + 0x00000001,0xffff3210,0xffffff10,0xffffff32,0xffffffff, + 3, + 3, + 0x00300003, + 0x00300003, + 0x3, + 0x1, 0x09001303, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e, + 0x1, 0x09001303, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicStereo16BitFormatConfigSize= =3D sizeof (DmicStereo16BitFormatConfig); + +// DMIC Config 2 channels, 32 bits, 2.4Mhz BCLK +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicStereo32BitFormatConfig[] =3D +{ + 0x00000001,0xffff3210,0xffffff10,0xffffff32,0xffffffff, + 3, + 3, + 0x00380003, + 0x00380003, + 0x3, + 0x1, 0x09001303, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e, + 0x1, 0x09001303, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicStereo32BitFormatConfigSize= =3D sizeof (DmicStereo32BitFormatConfig); + +// DMIC Config 4 channels, 16 bits, 2.4Mhz BCLK +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicQuad16BitFormatConfig[] =3D +{ + 0x00000001,0xffff3210,0xffffff10,0xffffff32,0xffffffff, + 3, + 3, + 0x00320003, + 0x00320003, + 0x3, + 0x1, 0x09001303, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e, + 0x1, 0x09001303, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicQuad16BitFormatConfigSize = =3D sizeof (DmicQuad16BitFormatConfig); + +// DMIC Config 4 channels, 32 bits, 2.4Mhz BCLK +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicQuad32BitFormatConfig[] =3D +{ + 0x00000001,0xffff3210,0xffffff10,0xffffff32,0xffffffff, + 3, + 3, + 0x003A0003, + 0x003A0003, + 0x3, + 0x1, 0x09001303, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e, + 0x1, 0x09001303, 0x0, 0x0303, 0, 0, 0, 0, + 0x11, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x11, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicQuad32BitFormatConfigSize = =3D sizeof (DmicQuad32BitFormatConfig); + + +// DMIC Config 1 channel, 16 bits +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 DmicMono16BitFormatConfig[] =3D +{ + 0x00000000, + 0xfffffff0,0xfffffff0,0xfffffff0,0xfffffff0, + 3, + 3, + 0x00300003, + 0x00300003, + 0x3, + 0x0, 0x09001303, 0x0, 0x0301, 0, 0, 0, 0, + 0x10, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x10, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e, + 0x0, 0x09001303, 0x0, 0x0301, 0, 0, 0, 0, + 0x10, 0x402a0, 0, 0, 0, 0, 0, 0, + 0x10, 0xe03ae, 0, 0, 0, 0, 0, 0, + 0x00008, 0xfffae, 0xfff12, 0xffdfb, 0xffc61, 0xffa5a, 0xff82b, 0xff641, = 0xff520, 0xff544, 0xff6f4, 0xffa25, 0xffe65, + 0x002e0, 0x0068f, 0x00876, 0x007f1, 0x004f5, 0x0002a, 0xffad4, 0xff68a, = 0xff4bf, 0xff64f, 0xffb20, + 0x0020f, 0x00929, 0x00e2d, 0x00f40, 0x00b92, 0x003bf, 0xff9cd, 0xff0b0, = 0xfeb6e, 0xfec2a, 0xff351, + 0xfff4f, 0x00ccd, 0x0179d, 0x01bfc, 0x017d7, 0x00ba3, 0xffa7e, 0xfe96f, = 0xfddf5, 0xfdc4d, 0xfe5ee, + 0xff8ce, 0x00fb7, 0x023a8, 0x02df5, 0x02a74, 0x01910, 0xffe2c, 0xfe19c, = 0xfcc64, 0xfc5ee, 0xfd17e, + 0xfecd4, 0x01071, 0x03198, 0x0457e, 0x044c9, 0x02e24, 0x00728, 0xfdb0e, = 0xfb781, 0xfa86b, 0xfb408, + 0xfd884, 0x00c02, 0x03f37, 0x061e8, 0x06807, 0x04dc5, 0x01954, 0xfd98c, = 0xfa1c8, 0xf840f, 0xf8b52, + 0xfb78c, 0xffd23, 0x047db, 0x080b1, 0x094e3, 0x07c08, 0x03b41, 0xfe45e, = 0xf9101, 0xf5b1e, 0xf54f4, + 0xf8307, 0xfda0b, 0x0418f, 0x09ad0, 0x0c9d6, 0x0be16, 0x0780b, 0x009dd, = 0xf92ba, 0xf3606, 0xf10ed, + 0xf315e, 0xf9135, 0x0172c, 0x09d83, 0x0fc9e, 0x11695, 0x0e05b, 0x065bf, = 0xfc6ed, 0xf2ff4, 0xecc96, + 0xebbc9, 0xf0668, 0xf9be7, 0x05601, 0x1029e, 0x17140, 0x18065, 0x12728, = 0x07874, 0xf9edb, 0xed202, + 0xe486c, 0xe294d, 0xe820f, 0xf424a, 0x03f29, 0x13d68, 0x1ff61, 0x253b2, = 0x220fa, 0x16be1, 0x05638, + 0xf1798, 0xdf165, 0xd211a, 0xcd3f9, 0xd1eb5, 0xdfa89, 0xf4802, 0x0d656, = 0x26d63, 0x3d808, 0x4ecc3, + 0x59315, 0x5c520, 0x58db6, 0x503d6, 0x444dd, 0x36ecb, 0x29b9a, 0x1de5d, = 0x14234, 0x0cae0, 0x07669, + 0x03f40, 0x01e4e, 0x00c95, 0x0043b, 0x000f9,0xff961, 0x00823, 0x0084f, 0= x00a39, 0x00d21, 0x010a8, 0x0149a, 0x018cc, 0x01d15, 0x0214d, 0x02543, 0x02= 8c8, 0x02baa, + 0x02db8, 0x02ec6, 0x02eac, 0x02d4c, 0x02a90, 0x02672, 0x020f9, 0x01a3b, = 0x0125c, 0x00994, 0x00025, + 0xff662, 0xfeca3, 0xfe34c, 0xfdabe, 0xfd364, 0xfcd94, 0xfc9a4, 0xfc7dd, = 0xfc86b, 0xfcb6e, 0xfd0e6, + 0xfd8bb, 0xfe2b9, 0xfee8f, 0xffbd5, 0x00a0c, 0x018a3, 0x026fc, 0x03474, = 0x04065, 0x04a36, 0x0515a, + 0x0555a, 0x055df, 0x052b2, 0x04bc3, 0x0412c, 0x03332, 0x02242, 0x00ef3, = 0xff9fb, 0xfe430, 0xfce78, + 0xfb9c6, 0xfa70f, 0xf973a, 0xf8b1e, 0xf836e, 0xf80b7, 0xf8355, 0xf8b6e, = 0xf98ea, 0xfab78, 0xfc288, + 0xfdd52, 0xffadf, 0x01a0a, 0x03992, 0x05823, 0x07465, 0x08d0c, 0x0a0e3, = 0x0aedc, 0x0b61f, 0x0b614, + 0x0ae6b, 0x09f23, 0x0888d, 0x06b4c, 0x04850, 0x020d3, 0xff647, 0xfca4f, = 0xf9eae, 0xf7533, 0xf4fa8, + 0xf2fc0, 0xf1702, 0xf06ba, 0xeffe6, 0xf032d, 0xf10d3, 0xf28b4, 0xf4a42, = 0xf7486, 0xfa62a, 0xfdd81, + 0x01896, 0x0553d, 0x09128, 0x0c9fe, 0x0fd6f, 0x1294e, 0x14ba5, 0x162cb, = 0x16d75, 0x16ac4, 0x15a52, + 0x13c38, 0x1110d, 0x0d9e9, 0x09856, 0x04e4a, 0xffe17, 0xfaa51, 0xf55c4, = 0xf0350, 0xeb5d6, 0xe7020, + 0xe34c8, 0xe0620, 0xde61c, 0xdd64b, 0xdd7bd, 0xdeb03, 0xe102a, 0xe46b5, = 0xe8dab, 0xee397, 0xf4699, + 0xfb479, 0x02ab3, 0x0a691, 0x1253c, 0x1a3d9, 0x21f98, 0x295cc, 0x30400, = 0x36803, 0x3bff8, 0x40a63, + 0x44628, 0x4729b, 0x48f76, 0x49cd2, 0x49b35, 0x48b71, 0x46ea5, 0x44632, = 0x413a6, 0x3d8b3, 0x3971b, + 0x350a6, 0x30716, 0x2bc15, 0x27131, 0x227cb, 0x1e11d, 0x19e2a, 0x15fc1, = 0x1267c, 0x0f2c0, 0x0c4c2, + 0x09c8b, 0x079fb, 0x05cd2, 0x044b2, 0x0312d, 0x021c5, 0x015f4, 0x0135e +}; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 DmicMono16BitFormatConfigSize = =3D sizeof (DmicMono16BitFormatConfig); + +// +// I2S/SSP Configuration BLOBs +// Audio Format and Configuration details +// +// Frequency: 48kHz, PCM resolution: 24 bits +// TDM slots: 4 +// Codec: Realtek ALC274, mode: slave +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 I2sRtk274Render4ch48kHz24bitFormatConfig[] =3D {0x0, 0xfffff= f10, 0xffffff32, 0xffff3210, 0xffff3210, 0xffff3210, 0xffff3210, 0xffff3210= , 0xffff3210, 0x83d00437, 0xc0700000, 0x0, 0x02010004, 0xf, 0xf, 0x4002, 0x= 4, 0x7070f00, 0x20, 0x00000001, 0x00000fff}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 I2sRtk274Render4ch48kHz24bitFor= matConfigSize =3D sizeof (I2sRtk274Render4ch48kHz24bitFormatConfig); + +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 I2sRtk274Capture4ch48kHz24bitFormatConfig[] =3D {0x0, 0xffff= ff10, 0xffffff10, 0xffffff10, 0xffffff10, 0xffffff10, 0xffffff10, 0xffffff1= 0, 0xffffff10, 0x83d00437, 0xc0700000, 0x0, 0x02010004, 0xf, 0xf, 0x4002, 0= x4, 0x7070f00, 0x20, 0x00000001, 0x00000fff}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 I2sRtk274Capture4ch48kHz24bitFo= rmatConfigSize =3D sizeof (I2sRtk274Capture4ch48kHz24bitFormatConfig); + +// +// BlueTooth Configuration BLOBs +// +GLOBAL_REMOVE_IF_UNREFERENCED +CONST UINT32 BtFormatConfig[] =3D +{ + 0x0, 0xfffffff0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, + 0x0, 0x80c0003f, 0xd3400000, 0x0, 0x02000005, 0x01, 0x01, 0x4002, + 0x0, 0x07020000, 0x0, 0x01, 0x0 +}; +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 BtFormatConfigSize =3D sizeof (= BtFormatConfig); --=20 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View/Reply Online (#45899): https://edk2.groups.io/g/devel/message/45899 Mute This Topic: https://groups.io/mt/32918191/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45900+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45900+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001018; cv=none; d=zoho.com; s=zohoarc; b=SRGRAZBqbJ0Z0TaXXe+UbfI5tfmXRbWb0wBMQm3OFwOglXzmj71YVDmVUuHVZD/CFXTEeaDYk98rI/25NSqMI4WrAPZ1iXGS1FW2+gPzRlmW6S6hGmWZR6bb26hlQm8PevfWdmqOT35Tgu7hYM9bh2DN/7UwFjCNZDlT5wTzxkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001018; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=an2pisSaSiKYhtZQ9YkLrkhPDkMb5sCx71JxluiSqnU=; b=V965iviOLMSDbeQW+EWdd4x8ZysI4SzMB8224pQzmaCckWwxp2BB3ame4YFVctOlEQzzZo61/LiMlcxu/6jwbDGzgmCuEzwfQLwVRfem0JA85ZkGy42HsoPqs1YTZnKIqZwHUe+bhpxQ8PZdLYBPS99HdX4W3eOLr1fbS1Kue/g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45900+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001018294545.091215787959; Fri, 16 Aug 2019 17:16:58 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:55 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319305" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:54 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 23/37] CoffeelakeSiliconPkg/Pch: Add PEI private library instances Date: Fri, 16 Aug 2019 17:15:49 -0700 Message-Id: <20190817001603.30632-24-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001017; bh=rnPMD+3UZnTb3MCh+j+mEIDfH+LjtaIWaSHKag4GhYE=; h=Cc:Date:From:Reply-To:Subject:To; b=ltxEgXobHawZyBwx+Fb+8ruLzKdR4K7HqCLnfbniQLWgYn6AWXLNXZNPa3uoEgH19eQ abLoPLT5tPuMLMH2Qjy8AVU0uQWwfDiKOOxlSE3CoP0izlp5T2Upq873udZbLET9JFUQH Ug+/4OdrU/yE61TrNWBEXkkB65vh5RV0j6I= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds PCH PEI private library class instances. These library instances may be compatible with other boot phases as indicated by the library type. * PeiDxeSmmGpioPrivateLibCnl * PeiDxeSmmPchDmiLib * PeiDxeSmmPchDmiWithS3Lib * PeiDxeSmmPchInitCommonLib * PeiDxeSmmPchPciExpressHelpersLib * PeiDxeSmmPchPsfPrivateLibCnl * PeiDxeSmmPmcPrivateLibCnl * PeiDxeSmmPmcPrivateLibWithS3 * PeiGpioHelpersLib * PeiGpioNameBufferLib * PeiPmcPrivateLibCnl Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivat= eLib/PeiDxeSmmGpioPrivateLibCnl.inf | 45 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDmiLib/= PeiDxeSmmPchDmiLib.inf | 40 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDmiLib/= PeiDxeSmmPchDmiWithS3Lib.inf | 40 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchInitCom= monLib/PeiDxeSmmPchInitCommonLib.inf | 34 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPciExpr= essHelpersLib/PeiDxeSmmPchPciExpressHelpersLib.inf | 42 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPsfPriv= ateLib/PeiDxeSmmPchPsfPrivateLibCnl.inf | 41 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PeiDxeSmmPmcPrivateLibCnl.inf | 48 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PeiDxeSmmPmcPrivateLibWithS3.inf | 39 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PeiPmcPrivateLibCnl.inf | 40 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpioHelpersLib/P= eiGpioHelpersLib.inf | 42 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpioNameBufferLi= b/PeiGpioNameBufferLib.inf | 35 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivat= eLib/GpioNativePrivateLibInternal.h | 477 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDmiLib/= PchDmi14.h | 70 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDmiLib/= PchDmi15.h | 113 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPciExpr= essHelpersLib/PchPciExpressHelpersLibrary.h | 42 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPsfPriv= ateLib/PchPsfPrivateLibInternal.h | 490 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PmcPrivateLibInternal.h | 47 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivat= eLib/GpioNamesCnl.c | 166 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivat= eLib/GpioNativePrivateLib.c | 1304 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivat= eLib/GpioNativePrivateLibCnl.c | 2275 ++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivat= eLib/GpioPrivateLib.c | 752 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivat= eLib/GpioPrivateLibCnl.c | 225 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDmiLib/= PchDmi14.c | 67 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDmiLib/= PchDmi15.c | 113 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDmiLib/= PchDmiLib.c | 569 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDmiLib/= PchDmiWithS3Lib.c | 79 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchInitCom= monLib/PchInitCommon.c | 221 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPciExpr= essHelpersLib/PchPciExpressHelpersLibrary.c | 2407 +++++++++++++++++= +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPsfPriv= ateLib/PchPsfPrivateLib.c | 542 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPsfPriv= ateLib/PchPsfPrivateLibCnl.c | 338 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PeiPmcPrivateLib.c | 92 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PmcPrivateLib.c | 1033 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PmcPrivateLibClient.c | 73 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PmcPrivateLibCnl.c | 360 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivate= Lib/PmcPrivateLibWithS3.c | 194 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpioHelpersLib/P= eiGpioHelpersLib.c | 356 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpioNameBufferLi= b/GpioNameBufferPei.c | 68 + 37 files changed, 12919 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmGpioPrivateLib/PeiDxeSmmGpioPrivateLibCnl.inf b/Silicon/Intel/CoffeelakeS= iliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateL= ibCnl.inf new file mode 100644 index 0000000000..318b54a99c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioP= rivateLib/PeiDxeSmmGpioPrivateLibCnl.inf @@ -0,0 +1,45 @@ +## @file +# Component description file for the PeiDxeSmmGpioPrivateLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmGpioPrivateLibCnl +FILE_GUID =3D E078A734-BEA0-47CF-A476-3742316D01FC +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D GpioPrivateLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + + +[LibraryClasses] + BaseLib + IoLib + DebugLib + PmcLib + PchInfoLib + GpioLib + GpioNameBufferLib + SataLib + + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] + GpioPrivateLib.c + GpioNativePrivateLib.c + GpioPrivateLibCnl.c + GpioNativePrivateLibCnl.c + GpioNamesCnl.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchDmiLib/PeiDxeSmmPchDmiLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch= /Library/Private/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf new file mode 100644 index 0000000000..b36fc15901 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PeiDxeSmmPchDmiLib.inf @@ -0,0 +1,40 @@ +## @file +# Component description file for the PeiDxeSmmPchDmiLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchDmiLib +FILE_GUID =3D 067DC1C4-2668-4F06-9921-307514B66B34 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchDmiLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + BaseLib + IoLib + DebugLib + PchInfoLib + PchPcrLib + + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] + PchDmiLib.c + PchDmi14.c + PchDmi15.c + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf b/Silicon/Intel/CoffeelakeSiliconP= kg/Pch/Library/Private/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf new file mode 100644 index 0000000000..1eda7cdba8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PeiDxeSmmPchDmiWithS3Lib.inf @@ -0,0 +1,40 @@ +## @file +# Component description file for the PeiDxeSmmPchDmiWithS3Lib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchDmiWithS3Lib +FILE_GUID =3D 32CCA047-6AF0-46FF-83DA-32BA62484075 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchDmiWithS3Lib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + BaseLib + IoLib + DebugLib + PchPcrLib + PchInfoLib + S3BootScriptLib + PchDmiLib + + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] + PchDmiWithS3Lib.c + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchInitCommonLib/PeiDxeSmmPchInitCommonLib.inf b/Silicon/Intel/Coffeelake= SiliconPkg/Pch/Library/Private/PeiDxeSmmPchInitCommonLib/PeiDxeSmmPchInitCo= mmonLib.inf new file mode 100644 index 0000000000..d81c428a1c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchIn= itCommonLib/PeiDxeSmmPchInitCommonLib.inf @@ -0,0 +1,34 @@ +## @file +# Component description file for the PchInitCommonLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiDxeSmmPchInitCommonLib + FILE_GUID =3D E9C4FE04-8A79-43FA-B3E0-603359C31B43 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PchInitCommonLib + +[Sources] + PchInitCommon.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + IoLib + DebugLib + PciSegmentLib + PchCycleDecodingLib + PchPcieRpLib + PchSbiAccessLib + PchInfoLib + SataLib + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchPciExpressHelpersLib/PeiDxeSmmPchPciExpressHelpersLib.inf b/Silicon/In= tel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPciExpressHelpersL= ib/PeiDxeSmmPchPciExpressHelpersLib.inf new file mode 100644 index 0000000000..16b1c019b8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPc= iExpressHelpersLib/PeiDxeSmmPchPciExpressHelpersLib.inf @@ -0,0 +1,42 @@ +## @file +# Component description file for the PeiDxeSmmPchPciExpressHelpersLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchPciExpressHelpersLib +FILE_GUID =3D 07E3F76D-6D26-419d-9053-58696A15B519 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchPciExpressHelpersLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + + + +[LibraryClasses] +IoLib +DebugLib +PchPcieRpLib +PchPcrLib +PchInfoLib +GpioLib +TimerLib +PchInitCommonLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchPciExpressHelpersLibrary.c + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchPsfPrivateLib/PeiDxeSmmPchPsfPrivateLibCnl.inf b/Silicon/Intel/Coffeel= akeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPsfPrivateLib/PeiDxeSmmPchPsf= PrivateLibCnl.inf new file mode 100644 index 0000000000..0ed9f30dcc --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPs= fPrivateLib/PeiDxeSmmPchPsfPrivateLibCnl.inf @@ -0,0 +1,41 @@ +## @file +# PEI/DXE/SMM PCH PSF Private Lib for Cannon Lake PCH +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPchPsfPrivateLibCnl +FILE_GUID =3D 7A6C18CA-0353-433E-885D-DD68BFAD38BE +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PchPsfPrivateLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[LibraryClasses] + BaseLib + IoLib + DebugLib + PciSegmentLib + PchInfoLib + PchPcrLib + SataLib + SaPlatformLib + + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] + PchPsfPrivateLib.c + PchPsfPrivateLibCnl.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCnl.inf b/Silicon/Intel/CoffeelakeSil= iconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibCn= l.inf new file mode 100644 index 0000000000..adb154dd14 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PeiDxeSmmPmcPrivateLibCnl.inf @@ -0,0 +1,48 @@ +## @file +# PEI/DXE/SMM PCH PMC Private Lib for Cannon Lake PCH. +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPmcPrivateLibCnl +FILE_GUID =3D A1CB52AD-4FAB-4214-94A0-323E3BE4E934 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PmcPrivateLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +TimerLib +PciSegmentLib +PchInfoLib +PchPcrLib +PmcLib +PchPsfPrivateLib +PchDmiLib +SataLib +BaseMemoryLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress + + +[Sources] +PmcPrivateLib.c +PmcPrivateLibClient.c +PmcPrivateLibCnl.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf b/Silicon/Intel/Coffeelake= SiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLi= bWithS3.inf new file mode 100644 index 0000000000..cd1380dc43 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf @@ -0,0 +1,39 @@ +## @file +# PEI/DXE/SMM PCH private PMC Lib. +# This part of PMC lib includes S3BootScript support +# +# All function in this library is available for PEI, DXE, and SMM, +# But do not support UEFI RUNTIME environment call. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmPmcPrivateLibWithS3 +FILE_GUID =3D 5890CA5A-1955-4A02-A09C-01E4150606CC +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PmcPrivateLibWithS3 + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +PciSegmentLib +PmcLib +PcdLib +S3BootScriptLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PmcPrivateLibWithS3.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PeiPmcPrivateLibCnl.inf b/Silicon/Intel/CoffeelakeSiliconPk= g/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PeiPmcPrivateLibCnl.inf new file mode 100644 index 0000000000..ab3645c61d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PeiPmcPrivateLibCnl.inf @@ -0,0 +1,40 @@ +## @file +# PEI PCH PMC Private Lib for Cannon Lake PCH. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiPmcPrivateLibCnl +FILE_GUID =3D 1DD4EA23-12F2-4F05-93AF-535476106D8C +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D PeiPmcPrivateLib + + +[LibraryClasses] +BaseLib +BaseMemoryLib +IoLib +DebugLib +PeiServicesLib +PciSegmentLib +ConfigBlockLib +PchInfoLib +PchPcrLib +PmcLib +PmcPrivateLib +PchEspiLib +GpioPrivateLib +PeiItssLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +PeiPmcPrivateLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpio= HelpersLib/PeiGpioHelpersLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/L= ibrary/Private/PeiGpioHelpersLib/PeiGpioHelpersLib.inf new file mode 100644 index 0000000000..b6f786d80b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpioHelpers= Lib/PeiGpioHelpersLib.inf @@ -0,0 +1,42 @@ +## @file +# Component description file for the PeiGpioHelpersLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiGpioHelpersLib +FILE_GUID =3D 1838E1E7-3CC4-4A74-90D9-B421EF2A579F +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D GpioHelpersLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +HobLib +GpioLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PeiGpioHelpersLib.c + + +[Guids] +gGpioLibUnlockHobGuid diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpio= NameBufferLib/PeiGpioNameBufferLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg= /Pch/Library/Private/PeiGpioNameBufferLib/PeiGpioNameBufferLib.inf new file mode 100644 index 0000000000..3619a2e6a7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpioNameBuf= ferLib/PeiGpioNameBufferLib.inf @@ -0,0 +1,35 @@ +## @file +# Component description file for the PeiGpioMemLib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiGpioNameBufferLib +FILE_GUID =3D 16EC5CA8-8195-4847-B6CB-662CDAB863F2 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D GpioNameBufferLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +[LibraryClasses] +HobLib +BaseLib +IoLib +DebugLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +GpioNameBufferPei.c + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmGpioPrivateLib/GpioNativePrivateLibInternal.h b/Silicon/Intel/CoffeelakeS= iliconPkg/Pch/Library/Private/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibI= nternal.h new file mode 100644 index 0000000000..e081027c40 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioP= rivateLib/GpioNativePrivateLibInternal.h @@ -0,0 +1,477 @@ +/** @file + Header file for GPIO Private Lib Internal functions. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_ +#define _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_ + +#include + +#define GPIO_PAD_NONE 0 + +/** + This function provides SerialIo I2C controller pins + + @param[in] SerialIoI2cControllerNumber I2C controller + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetSerialIoI2cPins ( + IN UINT32 SerialIoI2cControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides SerialIo UART controller pins + + @param[in] SerialIoUartControllerNumber UART controller + @param[in] HardwareFlowControl Hardware Flow control + @param[in] PinMuxing UART controller pin muxing + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetSerialIoUartPins ( + IN UINT32 SerialIoUartControllerNumber, + IN BOOLEAN HardwareFlowControl, + IN UINT32 PinMuxing, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ); + +/** + This function provides SerialIo SPI controller pins + + @param[in] SerialIoSpiControllerNumber SPI controller + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetSerialIoSpiPins ( + IN UINT32 SerialIoSpiControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ); + +/** + This function provides ISH GP pin data + + @param[in] IshGpPinNumber ISH GP pin number + + @param[out] NativePin ISH GP pin +**/ +VOID +GpioGetIshGpPin ( + IN UINT32 IshGpPinNumber, + OUT GPIO_PAD_NATIVE_FUNCTION *NativePin + ); + +/** + This function provides ISH UART controller pins + + @param[in] IshUartControllerNumber ISH UART controller + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetIshUartPins ( + IN UINT32 IshUartControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides ISH I2C controller pins + + @param[in] IshI2cControllerNumber ISH I2C controller + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetIshI2cPins ( + IN UINT32 IshI2cControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides ISH SPI controller pins + + @param[in] IshSpiControllerNumber SPI controller + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetIshSpiPins ( + IN UINT32 IshSpiControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ); + +/** + This function provides SCS SD CARD controller pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetScsSdCardPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ); + +/** + This function provides SCS SD CARD detect pin + + @retval GpioPin SD CARD Detect pin +**/ +GPIO_PAD +GpioGetScsSdCardDetectPin ( + VOID + ); + +/** + This function provides SCS eMMC controller pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetScsEmmcPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ); + +/** + This function provides HD Audio Link pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetHdAudioLinkPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ); + +/** + This function provides DMIC interface pins + + @param[in] DmicNumber DMIC interface + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetHdaDmicPins ( + IN UINT32 DmicNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides SSP/I2S interface pins + + @param[in] SspInterfaceNumber SSP/I2S interface + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetHdaSspPins ( + IN UINT32 SspInterfaceNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides SNDW interface pins + + @param[in] SndwInterfaceNumber SNDWx interface number + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetHdaSndwPins ( + IN UINT32 SndwInterfaceNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides SMBUS interface pins + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetSmbusPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides SATA DevSlp pin data + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + @param[out] NativePin SATA DevSlp pin +**/ +VOID +GpioGetSataDevSlpPin ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort, + OUT GPIO_PAD_NATIVE_FUNCTION *NativePin + ); + +/** + This function provides PCIe CLKREQ pin data + + @param[in] ClkreqIndex CLKREQ# number + @param[out] NativePin Native pin data +**/ +VOID +GpioGetPcieClkReqPin ( + IN UINT32 ClkreqIndex, + OUT GPIO_PAD_NATIVE_FUNCTION *NativePin + ); + +/** + This function provides eDP pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetEdpPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ); + +/** + This function provides DDPx interface pins + + @param[in] DdpInterface DDPx interface + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetDdpPins ( + IN GPIO_DDP DdpInterface, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides CNVi BT UART pins + + @param[in] ConnectionType CNVi BT UART connection type + @param[out] VCnviBtUartPad Table with vCNV_BT_UARTx pads + @param[out] VCnviBtUartPadMode vCNV_BT_UARTx pad mode + @param[out] VUartForCnviBtPad Table with vUART0 pads + @param[out] VUartForCnviBtPadMode vUART0 pad mode +**/ +VOID +GpioGetCnviBtUartPins ( + IN VGPIO_CNVI_BT_UART_CONNECTION_TYPE ConnectionType, + OUT GPIO_PAD **VCnviBtUartPad, + OUT GPIO_PAD_MODE *VCnviBtUartPadMode, + OUT GPIO_PAD **VUartForCnviBtPad, + OUT GPIO_PAD_MODE *VUartForCnviBtPadMode + ); + +/** + This function provides CNVi BT UART external pads + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnviBtUartExternalPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides CNVi BT I2S pins + + @param[in] ConnectionType CNVi BT I2S connection type + @param[out] VCnviBtI2sPad Table with vCNV_BT_I2Sx pads + @param[out] VCnviBtI2sPadMode vCNV_BT_I2Sx pad mode + @param[out] VSspForCnviBtPad Table with vSSP2 pads + @param[out] VSspForCnviBtPadMode vSSP2 pad mode +**/ +VOID +GpioGetCnviBtI2sPins ( + IN VGPIO_CNVI_BT_I2S_CONNECTION_TYPE ConnectionType, + OUT GPIO_PAD **VCnviBtI2sPad, + OUT GPIO_PAD_MODE *VCnviBtI2sPadMode, + OUT GPIO_PAD **VSspForCnviBtPad, + OUT GPIO_PAD_MODE *VSspForCnviBtPadMode + ); + +/** + This function provides CNVi BT I2S external pads + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnviBtI2sExternalPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides CNVi MFUART1 pins + + @param[in] ConnectionType CNVi MFUART1 connection type + @param[out] VCnviBtI2sPad Table with vCNV_MFUART1x pads + @param[out] VCnviBtI2sPadMode vCNV_MFUART1x pad mode + @param[out] VSspForCnviBtPad Table with vISH_UART0 pads + @param[out] VSspForCnviBtPadMode vISH_UART0 pad mode +**/ +VOID +GpioGetCnviMfUart1Pins ( + IN VGPIO_CNVI_MF_UART1_CONNECTION_TYPE ConnectionType, + OUT GPIO_PAD **VCnviMfUart1Pad, + OUT GPIO_PAD_MODE *VCnviMfUart1PadMode, + OUT GPIO_PAD **VUartForCnviMfUart1Pad, + OUT GPIO_PAD_MODE *VUartForCnviMfUart1PadMode + ); + +/** + This function provides CNVi MFUART1 external pads + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnviMfUart1ExternalPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides CNVi Bluetooth Enable pad + + @retval GpioPad CNVi Bluetooth Enable pad +**/ +GPIO_PAD +GpioGetCnviBtEnablePin ( + VOID + ); + +/** + This function provides CNVi BRI RGI GPIO pads + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnvBriRgiPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides CNVi MFUART2 external pins + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnvMfUart2ExternalPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ); + +/** + This function provides CNVi BT interface select pin + + @retval GpioPad GPIO pad for CNVi BT interface select +**/ +GPIO_PAD +GpioGetCnviBtIfSelectPin ( + VOID + ); + +/** + This function provides CNVi BT Charging pin + + @retval GpioPad GPIO pad for CNVi BT Charging select +**/ +GPIO_PAD +GpioGetCnviBtChargingPin ( + VOID + ); + +/** + This function provides CNVi A4WP pin + + @param[out] GpioNativePad GPIO native pad for CNVi A4WP +**/ +VOID +GpioGetCnviA4WpPin ( + OUT GPIO_PAD_NATIVE_FUNCTION *GpioNativePad + ); + +/** + This function provides CNVi BT host wake int pin + + @retval GpioPad GPIO pad BT host wake int +**/ +GPIO_PAD +GpioGetCnviBtHostWakeIntPin ( + VOID + ); + +/** + This function provides IMGCLKOUT pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetImgClkOutPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ); + +/** + This function provides PWRBTN pin + + @retval GpioPad PWRTBTN pin +**/ +GPIO_PAD +GpioGetPwrBtnPin ( + VOID + ); + +/** + This procedure enables debounce feature on a selected pad configured in = input mode + Debounce time can be specified in microseconds. GPIO HW supports only ce= rtain values + according to below formula: + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period). + RTC clock with f =3D 32 KHz is used for glitch filter. + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us). + Supported DebounceTime values are following: + DebounceTime =3D 0 -> Debounce feature disabled + DebounceTime > 0 && < 250us -> Not supported + DebounceTime =3D 250us - 1024000us -> Supported range (DebounceTime =3D= 250us * 2^n) + For values not supported by GPIO HW, function will round down + to closest supported + + @param[in] GpioPad GPIO pad + @param[in, out] DebounceTime Debounce Time in microseconds + If Debounce Time =3D 0, Debouncer featur= e will be disabled + Function will set DebounceTime argument = to rounded supported value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad or unsupported DebounceD= uration value + @retval EFI_UNSUPPORTED GpioPad is not owned by host +**/ +EFI_STATUS +GpioSetDebounceTimer ( + IN GPIO_PAD GpioPad, + IN OUT UINT32 *DebounceTime + ); + +/** + This function provides LPC pin + + @retval GpioPad LPC pin +**/ +GPIO_PAD +GpioGetLpcPin ( + VOID + ); + +#endif // _GPIO_NATIVE_PRIVATE_LIB_INTERNAL_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchDmiLib/PchDmi14.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pri= vate/PeiDxeSmmPchDmiLib/PchDmi14.h new file mode 100644 index 0000000000..1d50c04b0f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PchDmi14.h @@ -0,0 +1,70 @@ +/** @file + Internal header file for PCH DMI library for SIP14 + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PCH_DMI_14_H__ +#define __PCH_DMI_14_H__ + +#include +#include + +/** + This function checks if DMI SIP14 Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmi14Locked ( + VOID + ); + +/** + Enable PCIe Relaxed Order for DMI SIP14 +**/ +VOID +PchDmi14EnablePcieRelaxedOrder ( + VOID + ); + +/** + This function will switch SAI value to be driven to IOSF Primary Fabric + for cycles with Core BDF from HOSTIA_BOOT_SAI to HOSTIA_POSTBOOT_SAI. + To be used when PCH is paired with CFL CPU. +**/ +VOID +PchDmi14EnablePostBootSai ( + VOID + ); + +/** + Secure Register Lock data + + @param[out] SrlRegOffset Register offset holding Secure Register L= ock setting + @param[out] SrlRegMask Mask for Secure Register Lock setting +**/ +VOID +PchDmi14SrlRegData ( + OUT UINT16 *SrlRegOffset, + OUT UINT32 *SrlRegMask + ); + +/** + Get PCH DMI SIP14 Virtual Channel Control and Status registers + + @param[in] Vc The virtual channel number for programi= ng + @param[out] DmiVcCtlAddress DMI Virtual Channel Control register ad= dress + @param[out] DmiVcStsAddress DMI Virtual Channel Status register add= ress +**/ +VOID +PchDmi14VcRegs ( + IN PCH_DMI_VC_TYPE Vc, + OUT UINT16 *DmiVcCtlAddress, + OUT UINT16 *DmiVcStsAddress + ); + + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchDmiLib/PchDmi15.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pri= vate/PeiDxeSmmPchDmiLib/PchDmi15.h new file mode 100644 index 0000000000..744a96fe14 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PchDmi15.h @@ -0,0 +1,113 @@ +/** @file + Internal header file for PCH DMI library for SIP15 + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PCH_DMI_15_H__ +#define __PCH_DMI_15_H__ + +#include +#include + +/** + This function checks if DMI SIP15 Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmi15Locked ( + VOID + ); + +/** + Set DMI thermal throttling to recommended configuration. + It's intended only for P-DMI SIP15. +**/ +VOID +PchDmi15SetRecommendedThermalThrottling ( + VOID + ); + +/** + Set DMI thermal throttling to custom configuration. + This function will configure Thermal Sensor 0/1/2/3 TargetWidth and set + DMI Thermal Sensor Autonomous Width Enable. + It's intended only for P-DMI SIP15. + + @param[in] DmiThermalThrottling DMI Thermal Throttling structure. +**/ +VOID +PchDmi15SetCustomThermalThrottling ( + IN DMI_THERMAL_THROTTLING DmiThermalThrottling + ); + +/** + Enable PCIe Relaxed Order for DMI SIP15 +**/ +VOID +PchDmi15EnablePcieRelaxedOrder ( + VOID + ); + +/** + This function will switch SAI value to be driven to IOSF Primary Fabric + for cycles with Core BDF from HOSTIA_BOOT_SAI to HOSTIA_POSTBOOT_SAI. + To be used when PCH is paired with CFL CPU. +**/ +VOID +PchDmi15EnablePostBootSai ( + VOID + ); + +/** + This function will do necessary configuration after platform + should have switched to POSTBOOT_SAI. It needs to be called even if + POSTBOOT_SAI was not set. +**/ +VOID +PchDmi15ConfigAfterPostBootSai ( + VOID + ); + +/** + Secure Register Lock data + + @param[out] SrlRegOffset Register offset holding Secure Register L= ock setting + @param[out] SrlRegMask Mask for Secure Register Lock setting +**/ +VOID +PchDmi15SrlRegData ( + OUT UINT16 *SrlRegOffset, + OUT UINT32 *SrlRegMask + ); + +/** + Get PCH DMI SIP15 Virtual Channel Control and Status registers + + @param[in] Vc The virtual channel number for programi= ng + @param[out] DmiVcCtlAddress DMI Virtual Channel Control register ad= dress + @param[out] DmiVcStsAddress DMI Virtual Channel Status register add= ress +**/ +VOID +PchDmi15VcRegs ( + IN PCH_DMI_VC_TYPE Vc, + OUT UINT16 *DmiVcCtlAddress, + OUT UINT16 *DmiVcStsAddress + ); + +/** + The function sets the Target Link Speed to GEN 3 in P-DMI SIP15. + + @param[in] TargetLinkSpeed Target Link Speed + 2: GEN2 + 3: GEN3 +**/ +VOID +PchDmi15SetTargetLinkSpeed ( + IN UINT8 TargetLinkSpeed + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchPciExpressHelpersLib/PchPciExpressHelpersLibrary.h b/Silicon/Intel/Cof= feelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPciExpressHelpersLib/PchP= ciExpressHelpersLibrary.h new file mode 100644 index 0000000000..b14f24b18f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPc= iExpressHelpersLib/PchPciExpressHelpersLibrary.h @@ -0,0 +1,42 @@ +/** @file + Header file for PCH Pci Express helps library implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PCI_EXPRESS_HELPERS_LIBRARY_H_ +#define _PCH_PCI_EXPRESS_HELPERS_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LTR_VALUE_MASK (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6 + B= IT7 + BIT8 + BIT9) +#define LTR_SCALE_MASK (BIT10 + BIT11 + BIT12) + +#define CONFIG_WRITE_LOOP_COUNT 100000 + +// +// LTR related macros +// +#define LTR_LATENCY_VALUE(x) ((x) & LTR_VALUE_MASK) +#define LTR_SCALE_VALUE(x) (((x) & LTR_SCALE_MASK) >> 10) +#define LTR_LATENCY_NS(x) (LTR_LATENCY_VALUE(x) * (1 << (5 * = LTR_SCALE_VALUE(x)))) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchPsfPrivateLib/PchPsfPrivateLibInternal.h b/Silicon/Intel/CoffeelakeSil= iconPkg/Pch/Library/Private/PeiDxeSmmPchPsfPrivateLib/PchPsfPrivateLibInter= nal.h new file mode 100644 index 0000000000..f633df0411 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPs= fPrivateLib/PchPsfPrivateLibInternal.h @@ -0,0 +1,490 @@ +/** @file + This file contains internal header for PSF lib usage + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_PSF_PRIVATE_LIB_INTERNAL_H_ +#define _PCH_PSF_PRIVATE_LIB_INTERNAL_H_ + +#include +#include + +#define PSF_PORT_NULL ((PSF_PORT){0,0}) +#define PSF_IS_PORT_NULL(PsfPort) ((PsfPort.PsfPid =3D=3D 0) && (PsfPort.R= egBase =3D=3D 0)) + +/** + Disable bridge (e.g. PCIe Root Port) at PSF level + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfDisableBridge ( + IN PSF_PORT PsfPort + ); + +/** + Disable bridge (e.g. PCIe Root Port) at PSF level in RS3 + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfRs3DisableBridge ( + IN PSF_PORT PsfPort + ); + +/** + Check if bridge (e.g. PCIe Root Port) is enabled at PSF level + + @param[in] PsfPort PSF PORT data structure + + @retval TRUE Bridge behind PSF Port is enabled + FALSE Bridge behind PSF Port is disabled +**/ +BOOLEAN +PsfIsBridgeEnabled ( + IN PSF_PORT PsfPort + ); + +/** + Disable device IOSpace at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfDisableDeviceIoSpace ( + IN PSF_PORT PsfPort + ); + +/** + Enable device IOSpace at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfEnableDeviceIoSpace ( + IN PSF_PORT PsfPort + ); + +/** + Disable device Memory Space at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfDisableDeviceMemSpace ( + IN PSF_PORT PsfPort + ); + +/** + Enable device Memory Space at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfEnableDeviceMemSpace ( + IN PSF_PORT PsfPort + ); + +/** + Set device BARx address at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure + @param[in] BarNum BAR Number (0:BAR0, 1:BAR1, ...) + @param[in] BarValue 32bit BAR value +**/ +VOID +PsfSetDeviceBarValue ( + IN PSF_PORT PsfPort, + IN UINT8 BarNum, + IN UINT32 BarValue + ); + +/** + Return PSF_PORT for TraceHub device + + @retval PsfPort PSF PORT structure for TraceHub device +**/ +PSF_PORT +PsfTraceHubPort ( + VOID + ); + +/** + This procedure will return PSF_PORT for TraceHub ACPI device + + @retval PsfPort PSF PORT structure for TraceHub ACPI device +**/ +PSF_PORT +PsfTraceHubAcpiDevPort ( + VOID + ); + +/** + Return PSF_PORT for HECI device + + @param[in] HeciDevice HECIx Device (HECI1-4) + + @retval PsfPort PSF PORT structure for HECI device +**/ +PSF_PORT +PsfHeciPort ( + IN UINT8 HeciDevice + ); + +/** + This procedure will return PSF_PORT for SOL device + + @retval PsfPort PSF PORT structure for SOL device +**/ +PSF_PORT +PsfSolPort ( + VOID + ); + +/** + Return PSF_PORT for ISH device + + @retval PsfPort PSF PORT structure for ISH device +**/ +PSF_PORT +PsfIshPort ( + VOID + ); + +/** + Return PSF_PORT for CNVi device + + @retval PsfPort PSF PORT structure for CNVi device +**/ +PSF_PORT +PsfCnviPort ( + VOID + ); + +/** + Return PSF_PORT for PMC device + + @retval PsfPort PSF PORT structure for PMC device +**/ +PSF_PORT +PsfPmcPort ( + VOID + ); + +/** + Return second level PSF_PORT to which PCIE Root Port device is connected= (directly) + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval PsfPort PSF PORT structure for PCIe +**/ +PSF_PORT +PsfPcieSecondLevelPort ( + IN UINT32 RpIndex + ); + +/** + Return PSF_PORT at root PSF level to which PCIe Root Port device is conn= ected + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval PsfPort PSF PORT structure for PCIe + +**/ +PSF_PORT +PsfRootPciePort ( + IN UINT32 RpIndex + ); + +/** + Return RS3 PSF_PORT at root PSF level to which PCIe Root Port device is = connected + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval PsfPort PSF PORT structure for PCIe +**/ +PSF_PORT +PsfRootRs3PciePort ( + IN UINT32 RpIndex + ); + +/** + Check if PCIe Root Port is enabled + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval TRUE PCIe Root Port is enabled + FALSE PCIe Root Port is disabled +**/ +BOOLEAN +PsfIsPcieRootPortEnabled ( + IN UINT32 RpIndex + ); + +// +// Type of enpoint connected to PSF port. +// PsfNullPort is used for ports which do not exist +// +typedef enum { + PsfNullPort, + PsfToPsfPort, + PsfPcieCtrlPort +} PSF_TOPO_PORT_TYPE; + +// +// Structure for storing information on location in PSF topology +// Every PSF node is identified by PsfID and PsfPortId +// +typedef struct { + UINT8 PsfId; + UINT8 PortId; +} PSF_TOPO_PORT; + +#define PSF_TOPO_PORT_NULL ((PSF_TOPO_PORT){0, 0}) +#define PSF_IS_TOPO_PORT_NULL(PsfTopoPort) (((PsfTopoPort).PsfId =3D=3D 0)= && ((PsfTopoPort).PortId =3D=3D 0)) + +// +// This is optional field containing PSF port specific data +// +typedef union { + UINT32 PcieCtrlIndex; +} PSF_TOPO_PORT_DATA; + +// +// Structure representing PSF port in PSF topology +// If port is of PsfToPsfPort type Child will point to the first +// port of sub PSF segment. +// +typedef struct PSF_TOPOLOGY { + PSF_TOPO_PORT PsfPort; + PSF_TOPO_PORT_TYPE PortType; + CONST struct PSF_TOPOLOGY *Child; + PSF_TOPO_PORT_DATA PortData; +} PSF_TOPOLOGY; + +// +// Tag for identifying last element of PSF_TOPOLOGY type array +// +#define PSF_TOPOLOGY_END {{0, 0}, PsfNullPort, NULL} + +/** + Get PSF Pcie Tree topology + + @param[in] PsfTopology PSF Port from PSF PCIe tree topology + + @retval PsfTopology PSF PCIe tree topology +**/ +CONST PSF_TOPOLOGY* +PsfGetRootPciePsfTopology ( + VOID + ); + +// +// Structure for storing data on PCIe controller to PSF assignment and Gra= ntCount register offsets +// +typedef struct { + PCH_SBI_PID PsfPid; + UINT16 DevGntCnt0Base; + UINT16 TargetGntCntPg1Tgt0Base; +} PSF_GRANT_COUNT_REG; + +/** + Grant count regs data for PSF that is directly connected to PCIe Root Po= rts + + @param[in] Controller PCIe Root Port Controller index (0 based) + @param[out] GrantCountReg Structure with PSF Grant Count register data +**/ +VOID +PsfPcieGrantCountBaseReg ( + IN UINT8 Controller, + OUT PSF_GRANT_COUNT_REG *GrantCountReg + ); + +/** + Get Grant Count number (Device Grant Count and Target Grant Count) + for PSF that is directly connected to PCIe Root Ports + + @param[in] Controller PCIe Root Port Controller index + @param[in] Channel PCIe Root Port Channel index + @param[out] DgcrNo Device Grant Count number + @param[out] PgTgtNo Target Grant Count number +**/ +VOID +PsfPcieGrantCountNumber ( + IN UINT8 Controller, + IN UINT8 Channel, + OUT UINT8 *DgcrNo, + OUT UINT8 *PgTgtNo + ); + +/** + Grant count regs data for a given PSF-to-PSF port. + + @param[in] PsfTopoPort PSF-to-PSF port + + @param[out] GrantCountReg Structure with PSF Grant Count register d= ata +**/ +VOID +PsfSegmentGrantCountBaseReg ( + IN PSF_TOPO_PORT PsfTopoPort, + OUT PSF_GRANT_COUNT_REG *GrantCountReg + ); + +/** + Grant Count number (Device Grant Count and Target Grant Count) for a giv= en PSF-to-PSF port. + + @param[in] PsfTopoPort PSF-to-PSF port + @param[out] DgcrNo Device Grant Count number + @param[out] PgTgtNo Target Grant Count number +**/ +VOID +PsfSegmentGrantCountNumber ( + IN PSF_TOPO_PORT PsfTopoPort, + OUT UINT8 *DgcrNo, + OUT UINT8 *PgTgtNo + ); + +// +// Do not override PSF Grant Count value and leave HW default setting +// +#define DEFAULT_PCIE_GRANT_COUNT 0xFF + +typedef struct { + UINT32 Id; + PCH_SBI_PID SbPid; +} PSF_SEGMENT; + +/** + Get list of supported PSF segments. + + @param[out] PsfTable Array of supported PSF segments + @param[out] PsfTableLength Length of PsfTable +**/ +VOID +PsfSegments ( + OUT PSF_SEGMENT **PsfTable, + OUT UINT32 *PsfTableLength + ); + +/** + Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...) + + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) + + @retval PSF SideBand Port ID +**/ +PCH_SBI_PID +PsfSbPortId ( + UINT32 PsfId + ); + +/** + Get EOI register data for given PSF ID + + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) + @param[out] EoiTargetBase EOI Target register + @param[out] EoiControlBase EOI Control register + + @retval MaxTargets Number of supported targets + +**/ +UINT8 +PsfEoiRegData ( + UINT32 PsfId, + UINT16 *EoiTargetBase, + UINT16 *EoiControlBase + ); + +/** + Get MCTP register data for given PSF ID + + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) + @param[out] MctpTargetBase MCTP Target register + @param[out] MctpControlBase MCTP Control register + + @retval MaxTargets Number of supported targets + +**/ +UINT8 +PsfMctpRegData ( + UINT32 PsfId, + UINT16 *MctpTargetBase, + UINT16 *MctpControlBase + ); + +/** + P2SB PSF port Destination ID (psf_id:port_group_id:port_id:channel_id) + + @retval P2SB Destination ID +**/ +PSF_PORT_DEST_ID +PsfP2sbDestinationId ( + VOID + ); + +/** + DMI PSF port Destination ID (psf_id:port_group_id:port_id:channel_id) + + @retval DMI Destination ID +**/ +PSF_PORT_DEST_ID +PsfDmiDestinationId ( + VOID + ); + +/** + Check if MCTP is supported + + @retval TRUE MCTP is supported + FALSE MCTP is not supported +**/ +BOOLEAN +PsfIsMctpSupported ( + VOID + ); + +/** + Return the PSF (Root level) Function Config PSF_PORT for PCIe Root Port + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval PsfPort PSF PORT structure for PCIe Function Config +**/ +PSF_PORT +PsfRootPcieFunctionConfigPort ( + IN UINT32 RpIndex + ); + +/** + Return the PSF (Root level) RS3 Function Config PSF_PORT for PCIe Root P= ort + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval PsfPort PSF PORT structure for PCIe Function Config +**/ +PSF_PORT +PsfRootRs3PcieFunctionConfigPort ( + IN UINT32 RpIndex + ); + +/** + Return the PSF Function Config Second Level PSF_PORT for PCIe Root Port + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval PsfPort PSF PORT structure for PCIe Function Config +**/ +PSF_PORT +PsfPcieFunctionConfigSecondLevelPort ( + IN UINT32 RpIndex + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PmcPrivateLibInternal.h b/Silicon/Intel/CoffeelakeSiliconPk= g/Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PmcPrivateLibInternal.h new file mode 100644 index 0000000000..c08d1cf10d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PmcPrivateLibInternal.h @@ -0,0 +1,47 @@ +/** @file + Internal header file for PMC Private library + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PMC_PRIVATE_LIB_INTERNAL_H_ +#define _PMC_PRIVATE_LIB_INTERNAL_H_ + +/** + Check if MODPHY SUS PG is supported + + @retval Status of MODPHY SUS PG support +**/ +BOOLEAN +PmcIsModPhySusPgSupported ( + VOID + ); + +/** + This function is part of PMC init and configures which clock wake signal= s should + set the SLOW_RING, SA, FAST_RING_CF and SLOW_RING_CF indication sent up = to the CPU/PCH +**/ +VOID +PmcInitClockWakeEnable ( + VOID + ); + +/** + This function configures PWRMBASE + 0x1E00 register +**/ +VOID +PmcConfigureRegPwrm1E00 ( + VOID + ); + +/** + This function configures Misc PM_SYNC events settings +**/ +VOID +PmcConfigurePmSyncEventsSettings ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmGpioPrivateLib/GpioNamesCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Li= brary/Private/PeiDxeSmmGpioPrivateLib/GpioNamesCnl.c new file mode 100644 index 0000000000..5a4876bfeb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioP= rivateLib/GpioNamesCnl.c @@ -0,0 +1,166 @@ +/** @file + This file contains GPIO name library implementation + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +STATIC CONST CHAR8* mGpioGppaNames[] =3D { + "ESPI_CLK_LOOPBK" +}; + +STATIC CONST CHAR8* mGpioGppbNames[] =3D { + "GSPI0_CLK_LOOPBK", + "GSPI1_CLK_LOOPBK" +}; + +STATIC CONST CHAR8* mGpioGpdNames[] =3D { + "SLP_LANB", + "SLP_SUSB", + "SLP_WAKEB", + "SLP_DRAM_RESETB" +}; + +STATIC CONST CHAR8* mGpioGppiNames[] =3D { + "SYS_PWROK", + "SYS_RESETB", + "MLK_RSTB" +}; + +STATIC CONST CHAR8* mGpioSpiNames[] =3D { + "SPI0_IO_2", + "SPI0_IO_3", + "SPI0_MOSI_IO_0", + "SPI0_MOSI_IO_1", + "SPI0_TPM_CSB", + "SPI0_FLASH_0_CSB", + "SPI0_FLASH_1_CSB", + "SPI0_CLK", + "SPI0_CLK_LOOPBK" +}; + +STATIC CONST CHAR8* mGpioAzaNames[] =3D { + "HDA_BCLK", + "HDA_RSTB", + "HDA_SYNC", + "HDA_SDO", + "HDA_SDI_0", + "HDA_SDI_1", + "SSP1_SFRM", + "SSP1_TXD" +}; + +STATIC CONST CHAR8* mGpioJtagNames[] =3D { + "JTAG_TDO", + "JTAGX", + "PRDYB", + "PREQB", + "CPU_TRSTB", + "JTAG_TDI", + "JTAG_TMS", + "JTAG_TCK", + "ITP_PMODE" +}; + +STATIC CONST CHAR8* mGpioHvmosNames[] =3D { + "HVMOS_L_BKLTEN", + "HVMOS_L_BKLCTL", + "HVMOS_L_VDDEN", + "HVMOS_SYS_PWROK", + "HVMOS_SYS_RESETB", + "HVMOS_MLK_RSTB" +}; + +STATIC CONST CHAR8* mGpioCpuNames[] =3D { + "HDACPU_SDI", + "HDACPU_SDO", + "HDACPU_SCLK", + "PM_SYNC", + "PECI", + "CPUPWRGD", + "THRMTRIPB", + "PLTRST_CPUB", + "PM_DOWN", + "TRIGGER_IN", + "TRIGGER_OUT" +}; + +STATIC CONST GPIO_GROUP_NAME_INFO mPchLpGroupDescriptors[] =3D { + GPIO_GROUP_NAME("GPP_A", GPIO_CNL_LP_ESPI_CLK_LOOPBK, mGpioGppaNames), + GPIO_GROUP_NAME("GPP_B", GPIO_CNL_LP_GSPI0_CLK_LOOPBK, mGpioGppbNames), + GPIO_GROUP_NAME_BASIC("GPP_C"), + GPIO_GROUP_NAME_BASIC("GPP_D"), + GPIO_GROUP_NAME_BASIC("GPP_E"), + GPIO_GROUP_NAME_BASIC("GPP_F"), + GPIO_GROUP_NAME_BASIC("GPP_G"), + GPIO_GROUP_NAME_BASIC("GPP_H"), + GPIO_GROUP_NAME("GPD", GPIO_CNL_LP_SLP_LANB, mGpioGpdNames), + GPIO_GROUP_NAME_BASIC("VGPIO"), + GPIO_GROUP_NAME("SPI", GPIO_CNL_LP_SPI0_IO_2, mGpioSpiNames), + GPIO_GROUP_NAME("AZA", GPIO_CNL_LP_HDA_BCLK, mGpioAzaNames), + GPIO_GROUP_NAME("CPU", GPIO_CNL_LP_HDACPU_SDI, mGpioCpuNames), + GPIO_GROUP_NAME("JTAG", GPIO_CNL_LP_JTAG_TDO, mGpioJtagNames), + GPIO_GROUP_NAME("HVMOS", GPIO_CNL_LP_HVMOS_L_BKLTEN, mGpioHvmosNames) +}; + +STATIC CONST GPIO_GROUP_NAME_INFO mPchHGroupDescriptors[] =3D { + GPIO_GROUP_NAME("GPP_A", GPIO_CNL_H_ESPI_CLK_LOOPBK, mGpioGppaNames), + GPIO_GROUP_NAME("GPP_B", GPIO_CNL_H_GSPI0_CLK_LOOPBK, mGpioGppbNames), + GPIO_GROUP_NAME_BASIC("GPP_C"), + GPIO_GROUP_NAME_BASIC("GPP_D"), + GPIO_GROUP_NAME_BASIC("GPP_E"), + GPIO_GROUP_NAME_BASIC("GPP_F"), + GPIO_GROUP_NAME_BASIC("GPP_G"), + GPIO_GROUP_NAME_BASIC("GPP_H"), + GPIO_GROUP_NAME("GPP_I", GPIO_CNL_H_SYS_PWROK, mGpioGppiNames), + GPIO_GROUP_NAME_BASIC("GPP_J"), + GPIO_GROUP_NAME_BASIC("GPP_K"), + GPIO_GROUP_NAME("GPD", GPIO_CNL_H_SLP_LANB, mGpioGpdNames), + GPIO_GROUP_NAME_BASIC("VGPIO"), + GPIO_GROUP_NAME("SPI", GPIO_CNL_H_SPI0_IO_2, mGpioSpiNames), + GPIO_GROUP_NAME("AZA", GPIO_CNL_H_HDA_BCLK, mGpioAzaNames), + GPIO_GROUP_NAME("CPU", GPIO_CNL_H_HDACPU_SDI, mGpioCpuNames), + GPIO_GROUP_NAME("JTAG", GPIO_CNL_H_JTAG_TDO, mGpioJtagNames), +}; + +/** + Returns GPIO_GROUP_NAME_INFO corresponding to the given GpioPad + + @param[in] GroupIndex Group index + + @retval GPIO_GROUP_NAME_INFO* Pointer to the GPIO_GROUP_NAME_INFO + @reval NULL If no group descriptor was found +**/ +CONST +GPIO_GROUP_NAME_INFO* +GpioGetGroupNameInfo ( + IN UINT32 GroupIndex + ) +{ + if (IsPchLp ()) { + if (GroupIndex < ARRAY_SIZE (mPchLpGroupDescriptors)) { + return &mPchLpGroupDescriptors[GroupIndex]; + } else { + ASSERT (FALSE); + return NULL; + } + } else { + if (GroupIndex < ARRAY_SIZE (mPchHGroupDescriptors)) { + return &mPchHGroupDescriptors[GroupIndex]; + } else { + ASSERT (FALSE); + return NULL; + } + } +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmGpioPrivateLib/GpioNativePrivateLib.c b/Silicon/Intel/CoffeelakeSiliconPk= g/Pch/Library/Private/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLib.c new file mode 100644 index 0000000000..affecf9ec0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioP= rivateLib/GpioNativePrivateLib.c @@ -0,0 +1,1304 @@ +/** @file + This file contains routines for GPIO native and chipset specific purpose + used by Reference Code only. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "GpioNativePrivateLibInternal.h" +#include +#include +#include + +/** + This function sets SerialIo I2C controller pins into native mode + + @param[in] SerialIoI2cControllerNumber I2C controller + @param[in] GpioTermination GPIO termination type + + @retval Status +**/ +EFI_STATUS +GpioEnableSerialIoI2c ( + IN UINT32 SerialIoI2cControllerNumber, + IN GPIO_ELECTRICAL_CONFIG GpioTermination + ) +{ + EFI_STATUS Status; + UINT32 Index; + GPIO_PAD_NATIVE_FUNCTION *I2cGpio; + GPIO_CONFIG GpioConfig; + + GpioGetSerialIoI2cPins ( + SerialIoI2cControllerNumber, + &I2cGpio + ); + + if (I2cGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + ZeroMem(&GpioConfig, sizeof(GPIO_CONFIG)); + GpioConfig.ElectricalConfig =3D GpioTermination; + + for (Index =3D 0; Index < PCH_SERIAL_IO_PINS_PER_I2C_CONTROLLER; Index++= ) { + GpioConfig.PadMode =3D I2cGpio[Index].Mode; + + Status =3D GpioSetPadConfig(I2cGpio[Index].Pad, &GpioConfig); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function sets SerialIo UART controller pins into native mode + + @param[in] SerialIoUartControllerNumber UART controller + @param[in] HardwareFlowControl Hardware Flow control + @param[in] PinMuxing UART controller pin muxing + + @retval Status +**/ +EFI_STATUS +GpioEnableSerialIoUart ( + IN UINT32 SerialIoUartControllerNumber, + IN BOOLEAN HardwareFlowControl, + IN UINT32 PinMuxing + ) +{ + EFI_STATUS Status; + UINT32 Index; + UINT32 PinsUsed; + GPIO_PAD_NATIVE_FUNCTION *UartGpio; + + GpioGetSerialIoUartPins ( + SerialIoUartControllerNumber, + HardwareFlowControl, + PinMuxing, + &UartGpio, + &PinsUsed + ); + + if (UartGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PinsUsed; Index++) { + Status =3D GpioSetPadMode (UartGpio[Index].Pad, UartGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + GpioSetInputInversion (UartGpio[Index].Pad, 0); + } + return EFI_SUCCESS; +} + +/** + This function sets SerialIo SPI controller pins into native mode + + @param[in] SerialIoSpiControllerNumber SPI controller + + @retval Status +**/ +EFI_STATUS +GpioEnableSerialIoSpi ( + IN UINT32 SerialIoSpiControllerNumber + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *SpiGpio; + UINT32 NumOfSpiPins; + + GpioGetSerialIoSpiPins ( + SerialIoSpiControllerNumber, + &SpiGpio, + &NumOfSpiPins + ); + + if (SpiGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < NumOfSpiPins; Index++) { + Status =3D GpioSetPadMode (SpiGpio[Index].Pad, SpiGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + GpioSetInputInversion (SpiGpio[Index].Pad, 0); + } + return EFI_SUCCESS; +} + +/** + This function sets ISH I2C controller pins into native mode + + @param[in] IshI2cControllerNumber I2C controller + + @retval Status +**/ +EFI_STATUS +GpioEnableIshI2c ( + IN UINT32 IshI2cControllerNumber + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *I2cGpio; + + GpioGetIshI2cPins ( + IshI2cControllerNumber, + &I2cGpio + ); + + if (I2cGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_ISH_PINS_PER_I2C_CONTROLLER; Index++) { + Status =3D GpioSetPadMode (I2cGpio[Index].Pad, I2cGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function sets ISH UART controller pins into native mode + + @param[in] IshUartControllerNumber UART controller + + @retval Status +**/ +EFI_STATUS +GpioEnableIshUart ( + IN UINT32 IshUartControllerNumber + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *UartGpio; + + GpioGetIshUartPins ( + IshUartControllerNumber, + &UartGpio + ); + + if (UartGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_ISH_PINS_PER_UART_CONTROLLER; Index++) { + Status =3D GpioSetPadMode (UartGpio[Index].Pad, UartGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function sets ISH SPI controller pins into native mode + + @param[in] IshSpiControllerNumber SPI controller + + @retval Status +**/ +EFI_STATUS +GpioEnableIshSpi ( + IN UINT32 IshSpiControllerNumber + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *SpiGpio; + UINT32 NumOfSpiPins; + + GpioGetIshSpiPins ( + IshSpiControllerNumber, + &SpiGpio, + &NumOfSpiPins + ); + + if (SpiGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < NumOfSpiPins; Index++) { + Status =3D GpioSetPadMode (SpiGpio[Index].Pad, SpiGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function sets ISH GP pin into native mode + + @param[in] IshGpPinNumber ISH GP pin number + + @retval Status +**/ +EFI_STATUS +GpioEnableIshGpPin ( + IN UINT32 IshGpPinNumber + ) +{ + EFI_STATUS Status; + GPIO_PAD_NATIVE_FUNCTION IshGp; + + GpioGetIshGpPin ( + IshGpPinNumber, + &IshGp + ); + + Status =3D GpioSetPadMode (IshGp.Pad, IshGp.Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + This function sets SCS SD card controller pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableScsSdCard ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *SdCardGpio; + UINT32 NumOfSdCardPins; + GPIO_CONFIG PwrEnConfig; + + GpioGetScsSdCardPins ( + &SdCardGpio, + &NumOfSdCardPins + ); + + if (SdCardGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + // + // We need to leave the PWREN# + // GPIO pad unlocked since it is controlled at runtime + // by ACPI code. It is a work around for our SD card + // controller not respecting PWREN# invertion settings + // during D3. Since this pad will be in GPIO mode when + // SD controller is in D3 we need to set correct pad config. + // + GpioUnlockPadCfg (SdCardGpio[0].Pad); + GpioGetPadConfig (SdCardGpio[0].Pad, &PwrEnConfig); + PwrEnConfig.PadMode =3D SdCardGpio[0].Mode; + PwrEnConfig.Direction =3D GpioDirOut; + PwrEnConfig.HostSoftPadOwn =3D GpioHostOwnAcpi; + PwrEnConfig.InterruptConfig =3D GpioIntDis; + PwrEnConfig.PowerConfig =3D GpioHostDeepReset; + PwrEnConfig.LockConfig =3D GpioPadUnlock; + GpioSetPadConfig (SdCardGpio[0].Pad, &PwrEnConfig); + + for (Index =3D 1; Index < NumOfSdCardPins; Index++) { + Status =3D GpioSetPadMode (SdCardGpio[Index].Pad, SdCardGpio[Index].Mo= de); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + + // + // SD Card Pins GPP_G0 - G4 require Native Termination + // Index in mPch[Lp/H]ScsSdCardGpio (depends on mPch[Lp/H]ScsSdCardGpi= o internal organization): + // GPP_G0 =3D 1 + // GPP_G4 =3D 5 + // + if (Index >=3D 1 && Index <=3D 5) { + Status =3D GpioSetPadElectricalConfig (SdCardGpio[Index].Pad, GpioTe= rmNative); + ASSERT_EFI_ERROR (Status); + } + } + return EFI_SUCCESS; +} + +/** + This function enables SCS Sd Card controller card detect pin + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableScsSdCardDetect ( + VOID + ) +{ + GPIO_CONFIG PadConfig; + GPIO_PAD GpioPad; + + ZeroMem (&PadConfig, sizeof (PadConfig)); + + /// + /// vSD3_CD_B line is driven by GPPC_G_5_SD3_CDB + /// and is used for interrupt for card detect event. + /// GPPC_G_5_SD3_CDB cannot be used for interrupt because this pin + /// is in native mode. + /// + GpioPad =3D GpioGetScsSdCardDetectPin (); + PadConfig.PadMode =3D GpioPadModeGpio; + PadConfig.Direction =3D GpioDirIn; + PadConfig.HostSoftPadOwn =3D GpioHostOwnGpio; + PadConfig.InterruptConfig =3D GpioIntBothEdge; + PadConfig.PowerConfig =3D GpioHostDeepReset; + + // Unlock GPIO pad due to Host Software Pad Ownership is GPIO Driver mod= e. + GpioUnlockPadCfg (GpioPad); + + return GpioSetPadConfig (GpioPad, &PadConfig); +} + +/** + This function sets SCS eMMC controller pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableScsEmmc ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *EmmcGpio; + UINT32 NumOfEmmcPins; + + GpioGetScsEmmcPins ( + &EmmcGpio, + &NumOfEmmcPins + ); + + if (EmmcGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < NumOfEmmcPins; Index++) { + Status =3D GpioSetPadMode (EmmcGpio[Index].Pad, EmmcGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function sets HDA Link pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaLink ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *HdaLinkGpio; + UINT32 NumOfHdaLinkPins; + + GpioGetHdAudioLinkPins ( + &HdaLinkGpio, + &NumOfHdaLinkPins + ); + + if (HdaLinkGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < NumOfHdaLinkPins; Index++) { + Status =3D GpioSetPadMode (HdaLinkGpio[Index].Pad, HdaLinkGpio[Index].= Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function sets HDA DMIC pins into native mode + + @param[in] DmicNumber DMIC number + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaDmic ( + IN UINT32 DmicNumber + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *DmicGpio; + + GpioGetHdaDmicPins ( + DmicNumber, + &DmicGpio + ); + + if (DmicGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_GPIO_HDA_DMIC_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (DmicGpio[Index].Pad, DmicGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function sets HDA SSP interface pins into native mode + + @param[in] SspInterfaceNumber SSPx interface number + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaSsp ( + IN UINT32 SspInterfaceNumber + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *SspGpio; + + GpioGetHdaSspPins ( + SspInterfaceNumber, + &SspGpio + ); + + if (SspGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_GPIO_HDA_SSP_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (SspGpio[Index].Pad, SspGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + + return EFI_SUCCESS; +} + +/** + This function sets HDA SoundWire interface pins into native mode + + @param[in] SndwInterfaceNumber SNDWx interface number + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaSndw ( + IN UINT32 SndwInterfaceNumber + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *SndwGpio; + + GpioGetHdaSndwPins ( + SndwInterfaceNumber, + &SndwGpio + ); + + if (SndwGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_GPIO_HDA_SNDW_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (SndwGpio[Index].Pad, SndwGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + + return EFI_SUCCESS; +} + +/** + This function sets SMBUS controller pins into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableSmbus ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *SmbusGpio; + + GpioGetSmbusPins (&SmbusGpio); + + if (SmbusGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_GPIO_SMBUS_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (SmbusGpio[Index].Pad, SmbusGpio[Index].Mode= ); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + + return EFI_SUCCESS; +} + +/** + This function sets SATA DevSlp pins into native mode + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + + @retval Status +**/ +EFI_STATUS +GpioEnableSataDevSlpPin ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort + ) +{ + GPIO_PAD_NATIVE_FUNCTION DevSlpGpio; + + GpioGetSataDevSlpPin ( + SataCtrlIndex, + SataPort, + &DevSlpGpio + ); + + GpioSetPadResetConfig (DevSlpGpio.Pad, GpioResumeReset); + + return GpioSetPadMode (DevSlpGpio.Pad, DevSlpGpio.Mode); +} + +/** + This function checks if SataDevSlp pin is in native mode + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port + @param[out] DevSlpPad DevSlpPad + This is an optional parameter and may be= NULL. + + @retval TRUE DevSlp is in native mode + FALSE DevSlp is not in native mode +**/ +BOOLEAN +GpioIsSataDevSlpPinEnabled ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort, + OUT GPIO_PAD *DevSlpPad OPTIONAL + ) +{ + GPIO_PAD_NATIVE_FUNCTION DevSlpNativePad; + GPIO_PAD_MODE GpioMode; + EFI_STATUS Status; + + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + GpioGetSataDevSlpPin ( + SataCtrlIndex, + SataPort, + &DevSlpNativePad + ); + + Status =3D GpioGetPadMode (DevSlpNativePad.Pad, &GpioMode); + + if (EFI_ERROR (Status) || (GpioMode !=3D DevSlpNativePad.Mode)) { + if (DevSlpPad !=3D NULL) { + *DevSlpPad =3D GPIO_PAD_NONE; + } + return FALSE; + } else { + if (DevSlpPad !=3D NULL) { + *DevSlpPad =3D DevSlpNativePad.Pad; + } + return TRUE; + } +} + +/** + This function sets SATAGPx pin into native mode + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + + @retval Status +**/ +EFI_STATUS +GpioEnableSataGpPin ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort + ) +{ + GPIO_PAD_NATIVE_FUNCTION SataGpGpio; + + GpioGetSataGpPin ( + SataCtrlIndex, + SataPort, + &SataGpGpio + ); + + DEBUG_CODE_BEGIN (); + GPIO_PAD_MODE PadMode; + GpioGetPadMode (SataGpGpio.Pad, &PadMode); + if (PadMode =3D=3D GpioPadModeNative1) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Cannot enable SATAGP%d, %a already u= sed for SATAXPCIE_%d\n", + SataPort, + GpioName (SataGpGpio.Pad), + SataPort)); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + DEBUG_CODE_END (); + + return GpioSetPadMode (SataGpGpio.Pad, SataGpGpio.Mode); +} + +/** + Returns a pad for given CLKREQ# index. + + @param[in] ClkreqIndex CLKREQ# number + + @return CLKREQ# pad. +**/ +GPIO_PAD +GpioGetClkreqPad ( + IN UINT32 ClkreqIndex + ) +{ + GPIO_PAD_NATIVE_FUNCTION ClkReqGpio; + + GpioGetPcieClkReqPin ( + ClkreqIndex, + &ClkReqGpio + ); + + return ClkReqGpio.Pad; +} + +/** + Enables CLKREQ# pad in native mode. + + @param[in] ClkreqIndex CLKREQ# number + + @return none +**/ +VOID +GpioEnableClkreq ( + IN UINT32 ClkreqIndex + ) +{ + GPIO_CONFIG PadConfig; + GPIO_PAD_NATIVE_FUNCTION ClkReqGpio; + + ZeroMem (&PadConfig, sizeof (PadConfig)); + + GpioGetPcieClkReqPin ( + ClkreqIndex, + &ClkReqGpio + ); + + PadConfig.PadMode =3D ClkReqGpio.Mode; + PadConfig.Direction =3D GpioDirNone; + PadConfig.PowerConfig =3D GpioHostDeepReset; + DEBUG ((DEBUG_INFO, "Enabling CLKREQ%d\n", ClkreqIndex)); + GpioSetPadConfig (ClkReqGpio.Pad, &PadConfig); +} + + +/** + This function sets HPD, VDDEN, BKLTEN and BKLTCTL pins into native mode = for eDP Panel + + @retval Status +**/ +EFI_STATUS +GpioEnableEdpPins ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 Index; + GPIO_PAD_NATIVE_FUNCTION *EdpPins; + UINT32 EdpPinsNumber; + + GpioGetEdpPins ( + &EdpPins, + &EdpPinsNumber + ); + + if (EdpPins =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + // + // Configure HPD, VDD and BKLT Pins for eDP panel + // + for (Index =3D 0; Index < EdpPinsNumber; Index++) { + Status =3D GpioSetPadMode (EdpPins[Index].Pad, EdpPins[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function sets DDP pins into native mode + + @param[in] DdpInterface DDPx interface + + @retval Status +**/ +EFI_STATUS +GpioEnableDpInterface ( + IN GPIO_DDP DdpInterface + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *DdpGpio; + + GpioGetDdpPins ( + DdpInterface, + &DdpGpio + ); + + if (DdpGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_GPIO_DDP_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (DdpGpio[Index].Pad, DdpGpio[Index].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + + return EFI_SUCCESS; +} + +/** + This function configures GPIO connection between CNVi and CRF + @param[in] None + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviCrfConnection ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 Index; + GPIO_PAD_NATIVE_FUNCTION *CnviBriRgiExternalPad; + + GpioGetCnvBriRgiPins (&CnviBriRgiExternalPad); + + if (CnviBriRgiExternalPad =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + // + // Configure CNVi BRI and RGI buses for high speed communication with CRF + // + for (Index =3D 0; Index < PCH_GPIO_CNVI_BRI_RGI_NUMBER_OF_PINS; Index++)= { + Status =3D GpioSetPadMode (CnviBriRgiExternalPad[Index].Pad, CnviBriRg= iExternalPad[Index].Mode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + This function configures virtual GPIO connection for CNVi Bluetooth UART + + @param[in] ConnectionType + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviBtUartConnection ( + IN VGPIO_CNVI_BT_UART_CONNECTION_TYPE ConnectionType + ) +{ + EFI_STATUS Status; + UINT32 Index; + GPIO_PAD *VCnviBtUartPad; + GPIO_PAD_MODE VCnviBtUartPadMode; + GPIO_PAD *VUartForCnviBtPad; + GPIO_PAD_MODE VUartForCnviBtPadMode; + GPIO_PAD_NATIVE_FUNCTION *CnviBtUartExternalPad; + + GpioGetCnviBtUartPins ( + ConnectionType, + &VCnviBtUartPad, + &VCnviBtUartPadMode, + &VUartForCnviBtPad, + &VUartForCnviBtPadMode + ); + + if ((VCnviBtUartPad =3D=3D NULL) || + (VUartForCnviBtPad =3D=3D NULL)) { + return EFI_UNSUPPORTED; + } + + // + // Configure CNVi Bluetooth UART for certain connection + // + for (Index =3D 0; Index < PCH_GPIO_CNVI_UART_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (VCnviBtUartPad[Index], VCnviBtUartPadMode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + + // + // Enable virtual connection for UART for Bluetooth + // + for (Index =3D 0; Index < PCH_GPIO_CNVI_UART_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (VUartForCnviBtPad[Index], VUartForCnviBtPad= Mode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + + // + // Enable CNVi BT UART on external pads + // + if (ConnectionType =3D=3D GpioCnviBtUartToExternalPads) { + + GpioGetCnviBtUartExternalPins (&CnviBtUartExternalPad); + + if (CnviBtUartExternalPad =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_GPIO_CNVI_UART_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (CnviBtUartExternalPad[Index].Pad, CnviBtU= artExternalPad[Index].Mode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + } + return EFI_SUCCESS; +} + +/** + This function configures virtual GPIO connection for CNVi Bluetooth I2S + + @param[in] ConnectionType + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviBtI2sConnection ( + IN VGPIO_CNVI_BT_I2S_CONNECTION_TYPE ConnectionType + ) +{ + EFI_STATUS Status; + UINT32 Index; + GPIO_PAD *VCnviBtI2sPad; + GPIO_PAD_MODE VCnviBtI2sPadMode; + GPIO_PAD *VSspForCnviBtPad; + GPIO_PAD_MODE VSspForCnviBtPadMode; + GPIO_PAD_NATIVE_FUNCTION *CnviBtI2sExternalPad; + + GpioGetCnviBtI2sPins ( + ConnectionType, + &VCnviBtI2sPad, + &VCnviBtI2sPadMode, + &VSspForCnviBtPad, + &VSspForCnviBtPadMode + ); + + if ((VCnviBtI2sPad =3D=3D NULL) || + (VSspForCnviBtPad =3D=3D NULL)) { + return EFI_UNSUPPORTED; + } + + // + // Configure CNVi Bluetooth I2S for certain connection + // + for (Index =3D 0; Index < PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (VCnviBtI2sPad[Index], VCnviBtI2sPadMode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + + // + // Enable virtual connection for SSP for Bluetooth + // + for (Index =3D 0; Index < PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (VSspForCnviBtPad[Index], VSspForCnviBtPadMo= de); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + + // + // Enable CNV BT I2S on external pads + // + if (ConnectionType =3D=3D (VGPIO_CNVI_BT_I2S_CONNECTION_TYPE) GpioCnviBt= I2sToExternalPads) { + + GpioGetCnviBtI2sExternalPins (&CnviBtI2sExternalPad); + + if (CnviBtI2sExternalPad =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (CnviBtI2sExternalPad[Index].Pad, CnviBtI2= sExternalPad[Index].Mode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + } + return EFI_SUCCESS; +} + +/** + This function configures virtual GPIO connection for CNVi MFUART1 + + @param[in] ConnectionType + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviMfUart1Connection ( + IN VGPIO_CNVI_MF_UART1_CONNECTION_TYPE ConnectionType + ) +{ + EFI_STATUS Status; + UINT32 Index; + GPIO_PAD *VCnviMfUart1Pad; + GPIO_PAD_MODE VCnviMfUart1PadMode; + GPIO_PAD *VUartForCnviMfUart1Pad; + GPIO_PAD_MODE VUartForCnviMfUart1PadMode; + GPIO_PAD_NATIVE_FUNCTION *CnviMfUart1ExternalPad; + + GpioGetCnviMfUart1Pins ( + ConnectionType, + &VCnviMfUart1Pad, + &VCnviMfUart1PadMode, + &VUartForCnviMfUart1Pad, + &VUartForCnviMfUart1PadMode + ); + + if ((VCnviMfUart1Pad =3D=3D NULL) || + (VUartForCnviMfUart1Pad =3D=3D NULL)) { + return EFI_UNSUPPORTED; + } + + // + // Configure CNVi MFUART1 for certain connection + // + for (Index =3D 0; Index < PCH_GPIO_CNVI_UART_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (VCnviMfUart1Pad[Index], VCnviMfUart1PadMode= ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + + // + // Enable virtual connection for MFUART1 + // + for (Index =3D 0; Index < PCH_GPIO_CNVI_UART_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (VUartForCnviMfUart1Pad[Index], VUartForCnvi= MfUart1PadMode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + + // + // Enable CNV MFUART1 on external pads + // + if (ConnectionType =3D=3D GpioCnviMfUart1ToExternalPads) { + + GpioGetCnviMfUart1ExternalPins (&CnviMfUart1ExternalPad); + + if (CnviMfUart1ExternalPad =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < PCH_GPIO_CNVI_UART_NUMBER_OF_PINS; Index++) { + Status =3D GpioSetPadMode (CnviMfUart1ExternalPad[Index].Pad, CnviMf= Uart1ExternalPad[Index].Mode); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return EFI_UNSUPPORTED; + } + } + } + return EFI_SUCCESS; +} + + +/** + This function sets CNVi Bluetooth Enable value + + @param[in] Value CNVi BT enable value + 0: Disable, 1: Enable + @retval Status +**/ +EFI_STATUS +GpioSetCnviBtEnState ( + IN UINT32 Value + ) +{ + EFI_STATUS Status; + GPIO_PAD CnviBtEnPad; + GPIO_CONFIG PadConfig; + + ZeroMem (&PadConfig, sizeof (PadConfig)); + + PadConfig.PadMode =3D GpioPadModeGpio; + PadConfig.HostSoftPadOwn =3D GpioHostOwnGpio; + PadConfig.Direction =3D GpioDirOut; + if (Value =3D=3D 1) { + PadConfig.OutputState =3D GpioOutHigh; + } else { + PadConfig.OutputState =3D GpioOutLow; + } + CnviBtEnPad =3D GpioGetCnviBtEnablePin (); + + // Unlock GPIO pad due to Host Software Pad Ownership is GPIO Driver mod= e and it is GPO + GpioUnlockPadCfg (CnviBtEnPad); + GpioUnlockPadCfgTx (CnviBtEnPad); + Status =3D GpioSetPadConfig (CnviBtEnPad, &PadConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + This function sets CNVi Bluetooth main host interface + + @param[in] BtInterface CNVi BT Interface Select value + GpioCnviBtIfUart: UART, GpioCnviBtIfUsb:= USB + @retval Status +**/ +EFI_STATUS +GpioSetCnviBtInterface ( + IN VGPIO_CNVI_BT_INTERFACE BtInterface + ) +{ + EFI_STATUS Status; + GPIO_CONFIG PadConfig; + + ZeroMem (&PadConfig, sizeof (PadConfig)); + + PadConfig.PadMode =3D GpioPadModeGpio; + PadConfig.Direction =3D GpioDirOut; + if (BtInterface =3D=3D GpioCnviBtIfUsb) { + PadConfig.OutputState =3D GpioOutHigh; + } else { + PadConfig.OutputState =3D GpioOutLow; + } + + Status =3D GpioSetPadConfig (GpioGetCnviBtIfSelectPin (), &PadConfig); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + This function sets CNVi Bluetooth Wireless Charging support + + @param[in] BtWirelessCharging CNVi BT Wireless Charging support + 0: Normal BT operation (no Wireless Char= ging support) + 1: Enable BT Wireless Charging + @retval Status +**/ +EFI_STATUS +GpioSetCnviBtWirelessCharging ( + IN UINT32 BtWirelessCharging + ) +{ + EFI_STATUS Status; + GPIO_CONFIG CnviBtChargingPadConfig; + GPIO_PAD_NATIVE_FUNCTION A4WpPad; + + ZeroMem (&CnviBtChargingPadConfig, sizeof (CnviBtChargingPadConfig)); + + CnviBtChargingPadConfig.PadMode =3D GpioPadModeGpio; + CnviBtChargingPadConfig.Direction =3D GpioDirOut; + + if (BtWirelessCharging =3D=3D 1) { + CnviBtChargingPadConfig.OutputState =3D GpioOutHigh; + + GpioGetCnviA4WpPin (&A4WpPad); + + Status =3D GpioSetPadMode (A4WpPad.Pad, A4WpPad.Mode); + ASSERT_EFI_ERROR (Status); + + } else { + CnviBtChargingPadConfig.OutputState =3D GpioOutLow; + } + + Status =3D GpioSetPadConfig (GpioGetCnviBtChargingPin (), &CnviBtChargin= gPadConfig); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + This function enables and configures CNVi Bluetooth Host wake-up interru= pt + + @param[in] None + + @retval Status +**/ +EFI_STATUS +GpioConfigureCnviBtHostWakeInt ( + VOID + ) +{ + EFI_STATUS Status; + GPIO_PAD CnviBtHostWakeIntPad; + GPIO_CONFIG PadConfig; + + ZeroMem (&PadConfig, sizeof (PadConfig)); + + PadConfig.PadMode =3D GpioPadModeGpio; + PadConfig.Direction =3D GpioDirIn; + PadConfig.HostSoftPadOwn =3D GpioHostOwnGpio; + PadConfig.InterruptConfig =3D GpioIntEdge; + PadConfig.PowerConfig =3D GpioHostDeepReset; + CnviBtHostWakeIntPad =3D GpioGetCnviBtHostWakeIntPin (); + + // Unlock GPIO pad due to Host Software Pad Ownership is GPIO Driver mod= e. + GpioUnlockPadCfg (CnviBtHostWakeIntPad); + Status =3D GpioSetPadConfig (CnviBtHostWakeIntPad, &PadConfig); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + This function enables IMGU CLKOUT native pin + + @param[in] None + + @retval Status +**/ +EFI_STATUS +GpioEnableImguClkOut ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + GPIO_PAD_NATIVE_FUNCTION *ImguClkOutGpio; + UINT32 NoOfNativePins; + + GpioGetImgClkOutPins ( + &ImguClkOutGpio, + &NoOfNativePins + ); + + if (ImguClkOutGpio =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + for (Index =3D 0; Index < NoOfNativePins; Index++) { + Status =3D GpioSetPadMode (ImguClkOutGpio[Index].Pad, ImguClkOutGpio[I= ndex].Mode); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + } + return EFI_SUCCESS; +} + +/** + Power button debounce configuration + Debounce time can be specified in microseconds. Only certain values acco= rding + to below formula are supported: + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period). + RTC clock with f =3D 32 KHz is used for glitch filter. + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us). + Supported DebounceTime values are following: + DebounceTime =3D 0 -> Debounce feature disabled + DebounceTime > 0 && < 250us -> Not supported + DebounceTime =3D 250us - 1024000us -> Supported range (DebounceTime =3D= 250us * 2^n) + For values not supported by HW, they will be rounded down to closest sup= ported one + + @param[in] DebounceTime Debounce Time in microseconds + If Debounce Time =3D 0, Debouncer feature wil= l be disabled + Function will set DebounceTime argument to ro= unded supported value +**/ +VOID +GpioSetPwrBtnDebounceTimer ( + IN UINT32 DebounceTime + ) +{ + GpioSetDebounceTimer (GpioGetPwrBtnPin (), &DebounceTime); +} + +/** + Configure LPC GPIO +**/ +VOID +LpcConfigureGpio ( + VOID + ) +{ + GPIO_PAD GpioPad; + GpioPad =3D GpioGetLpcPin(); + + if (GpioPad =3D=3D 0) { + return; + } else { + GpioSetPadElectricalConfig (GpioPad, GpioTermWpu20K); + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmGpioPrivateLib/GpioNativePrivateLibCnl.c b/Silicon/Intel/CoffeelakeSilico= nPkg/Pch/Library/Private/PeiDxeSmmGpioPrivateLib/GpioNativePrivateLibCnl.c new file mode 100644 index 0000000000..4cff00c27b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioP= rivateLib/GpioNativePrivateLibCnl.c @@ -0,0 +1,2275 @@ +/** @file + This file contains specific GPIO information + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "GpioNativePrivateLibInternal.h" + +// +// I2C controller pins +// I2C[controller number][pin: SDA/SCL] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpI2cGpio [][PC= H_SERIAL_IO_PINS_PER_I2C_CONTROLLER]=3D +{ + {{GPIO_CNL_LP_GPP_C16, GpioPadModeNative1}, {GPIO_CNL_LP_GPP_C17, GpioPa= dModeNative1}}, + {{GPIO_CNL_LP_GPP_C18, GpioPadModeNative1}, {GPIO_CNL_LP_GPP_C19, GpioPa= dModeNative1}}, + {{GPIO_CNL_LP_GPP_H4, GpioPadModeNative1}, {GPIO_CNL_LP_GPP_H5 , GpioPa= dModeNative1}}, + {{GPIO_CNL_LP_GPP_H6, GpioPadModeNative1}, {GPIO_CNL_LP_GPP_H7 , GpioPa= dModeNative1}}, + {{GPIO_CNL_LP_GPP_H8, GpioPadModeNative1}, {GPIO_CNL_LP_GPP_H9 , GpioPa= dModeNative1}}, + {{GPIO_CNL_LP_GPP_H10, GpioPadModeNative1}, {GPIO_CNL_LP_GPP_H11, GpioPa= dModeNative1}} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHI2cGpio [][PC= H_SERIAL_IO_PINS_PER_I2C_CONTROLLER]=3D +{ + {{GPIO_CNL_H_GPP_C16, GpioPadModeNative1}, {GPIO_CNL_H_GPP_C17, GpioPadM= odeNative1}}, // I2C0 + {{GPIO_CNL_H_GPP_C18, GpioPadModeNative1}, {GPIO_CNL_H_GPP_C19, GpioPadM= odeNative1}}, // I2C1 + {{GPIO_CNL_H_GPP_D13, GpioPadModeNative3}, {GPIO_CNL_H_GPP_D14, GpioPadM= odeNative3}}, // I2C2 + {{GPIO_CNL_H_GPP_D4, GpioPadModeNative2}, {GPIO_CNL_H_GPP_D23, GpioPadM= odeNative2}} // I2C3 +}; + + +/** + This function provides SerialIo I2C controller pins + + @param[in] SerialIoI2cControllerNumber I2C controller + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetSerialIoI2cPins ( + IN UINT32 SerialIoI2cControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + if (SerialIoI2cControllerNumber < ARRAY_SIZE (mPchLpI2cGpio)) { + *NativePinsTable =3D mPchLpI2cGpio[SerialIoI2cControllerNumber]; + return; + } + } else { + if (SerialIoI2cControllerNumber < ARRAY_SIZE (mPchHI2cGpio)) { + *NativePinsTable =3D mPchHI2cGpio[SerialIoI2cControllerNumber]; + return; + } + } + *NativePinsTable =3D NULL; + ASSERT (FALSE); +} +// +// UART controller pins +// UART[controller number][pin: RXD/TXD/RTSB/CTSB] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpUartGpio [][P= CH_SERIAL_IO_PINS_PER_UART_CONTROLLER]=3D +{ + { // UART0 + {GPIO_CNL_LP_GPP_C8, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C9, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C10, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C11, GpioPadModeNative1} + }, + { // UART1 + {GPIO_CNL_LP_GPP_C12, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C13, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C14, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C15, GpioPadModeNative1} + }, + { // UART2 + {GPIO_CNL_LP_GPP_C20, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C21, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C22, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_C23, GpioPadModeNative1}, + }, + { // UART0 (2nd pin set) + {GPIO_CNL_LP_GPP_F5, GpioPadModeNative2}, + {GPIO_CNL_LP_GPP_F6, GpioPadModeNative2}, + {GPIO_CNL_LP_GPP_F4, GpioPadModeNative2}, + {GPIO_CNL_LP_GPP_F7, GpioPadModeNative2} + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHUartGpio [][PC= H_SERIAL_IO_PINS_PER_UART_CONTROLLER]=3D +{ + { // UART0 + {GPIO_CNL_H_GPP_C8, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C9, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C10, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C11, GpioPadModeNative1} + }, + { // UART1 + {GPIO_CNL_H_GPP_C12, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C13, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C14, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C15, GpioPadModeNative1} + }, + { // UART2 + {GPIO_CNL_H_GPP_C20, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C21, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C22, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_C23, GpioPadModeNative1} + }, + { // UART0 (2nd pin set) + {GPIO_CNL_H_GPP_J5, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_J6, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_J4, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_J7, GpioPadModeNative2} + } +}; + +/** + This function provides SerialIo UART controller pins + + @param[in] SerialIoUartControllerNumber UART controller + @param[in] HardwareFlowControl Hardware Flow control + @param[in] PinMuxing UART controller pin muxing + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetSerialIoUartPins ( + IN UINT32 SerialIoUartControllerNumber, + IN BOOLEAN HardwareFlowControl, + IN UINT32 PinMuxing, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ) +{ + UINTN UartGpioIndex; + + UartGpioIndex =3D SerialIoUartControllerNumber; + + if ((SerialIoUartControllerNumber =3D=3D 0) && (PinMuxing =3D=3D 1)) { + // Last record is for UART0 second pin set + if (IsPchLp ()) { + UartGpioIndex =3D ARRAY_SIZE (mPchLpUartGpio) - 1; + } else { + UartGpioIndex =3D ARRAY_SIZE (mPchHUartGpio) - 1; + } + } + + if (HardwareFlowControl) { + *NoOfNativePins =3D PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER; + } else { + *NoOfNativePins =3D PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTR= L; + } + + if (IsPchLp ()) { + if (UartGpioIndex < ARRAY_SIZE (mPchLpUartGpio)) { + *NativePinsTable =3D mPchLpUartGpio[UartGpioIndex]; + return; + } + } else { + if (UartGpioIndex < ARRAY_SIZE (mPchHUartGpio)) { + *NativePinsTable =3D mPchHUartGpio[UartGpioIndex]; + return; + } + } + + *NativePinsTable =3D NULL; + *NoOfNativePins =3D 0; + ASSERT (FALSE); +} + +// +// SPI controller pins +// SPI[controller number][pin: CSB/CLK/MISO/MOSI] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpSpiGpio [][PC= H_SERIAL_IO_PINS_PER_SPI_CONTROLLER]=3D +{ + { // SPI0 + {GPIO_CNL_LP_GPP_B15, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B16, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B17, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B18, GpioPadModeNative1} + }, + { // SPI1 + {GPIO_CNL_LP_GPP_B19, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B20, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B21, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B22, GpioPadModeNative1} + }, + { // SPI2 + {GPIO_CNL_LP_GPP_D9, GpioPadModeNative3}, + {GPIO_CNL_LP_GPP_D10, GpioPadModeNative3}, + {GPIO_CNL_LP_GPP_D11, GpioPadModeNative3}, + {GPIO_CNL_LP_GPP_D12, GpioPadModeNative3} + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHSpiGpio [][PCH= _SERIAL_IO_PINS_PER_SPI_CONTROLLER]=3D +{ + { // SPI0 + {GPIO_CNL_H_GPP_B15, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B16, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B17, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B18, GpioPadModeNative1} + }, + { // SPI1 + {GPIO_CNL_H_GPP_B19, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B20, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B21, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B22, GpioPadModeNative1} + }, + { // SPI2 + {GPIO_CNL_H_GPP_D9, GpioPadModeNative3}, + {GPIO_CNL_H_GPP_D10, GpioPadModeNative3}, + {GPIO_CNL_H_GPP_D11, GpioPadModeNative3}, + {GPIO_CNL_H_GPP_D12, GpioPadModeNative3} + } +}; + +/** + This function provides SerialIo SPI controller pins + + @param[in] SerialIoSpiControllerNumber SPI controller + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetSerialIoSpiPins ( + IN UINT32 SerialIoSpiControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ) +{ + if (IsPchLp ()) { + if (SerialIoSpiControllerNumber < ARRAY_SIZE (mPchLpSpiGpio)) { + *NativePinsTable =3D mPchLpSpiGpio[SerialIoSpiControllerNumber]; + *NoOfNativePins =3D ARRAY_SIZE (mPchLpSpiGpio[SerialIoSpiController= Number]); + return; + } + } else { + if (SerialIoSpiControllerNumber < ARRAY_SIZE (mPchHSpiGpio)) { + *NativePinsTable =3D mPchHSpiGpio[SerialIoSpiControllerNumber]; + *NoOfNativePins =3D ARRAY_SIZE (mPchHSpiGpio[SerialIoSpiControllerN= umber]); + return; + } + } + *NativePinsTable =3D NULL; + *NoOfNativePins =3D 0; + ASSERT (FALSE); +} + +// +// ISH GP pin +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpIshGPGpio[] = =3D +{ + {GPIO_CNL_LP_GPP_A18, GpioPadModeNative1},// ISH_GP_0 + {GPIO_CNL_LP_GPP_A19, GpioPadModeNative1},// ISH_GP_1 + {GPIO_CNL_LP_GPP_A20, GpioPadModeNative1},// ISH_GP_2 + {GPIO_CNL_LP_GPP_A21, GpioPadModeNative1},// ISH_GP_3 + {GPIO_CNL_LP_GPP_A22, GpioPadModeNative1},// ISH_GP_4 + {GPIO_CNL_LP_GPP_A23, GpioPadModeNative1},// ISH_GP_5 + {GPIO_CNL_LP_GPP_A12, GpioPadModeNative2},// ISH_GP_6 + {GPIO_CNL_LP_GPP_A17, GpioPadModeNative2} // ISH_GP_7 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHIshGPGpio[] = =3D +{ + {GPIO_CNL_H_GPP_A18, GpioPadModeNative1},// ISH_GP_0 + {GPIO_CNL_H_GPP_A19, GpioPadModeNative1},// ISH_GP_1 + {GPIO_CNL_H_GPP_A20, GpioPadModeNative1},// ISH_GP_2 + {GPIO_CNL_H_GPP_A21, GpioPadModeNative1},// ISH_GP_3 + {GPIO_CNL_H_GPP_A22, GpioPadModeNative1},// ISH_GP_4 + {GPIO_CNL_H_GPP_A23, GpioPadModeNative1},// ISH_GP_5 + {GPIO_CNL_H_GPP_A12, GpioPadModeNative2},// ISH_GP_6 + {GPIO_CNL_H_GPP_A17, GpioPadModeNative2} // ISH_GP_7 +}; + +/** + This function provides ISH GP pin data + + @param[in] IshGpPinNumber ISH GP pin number + @param[out] NativePin ISH GP pin +**/ +VOID +GpioGetIshGpPin ( + IN UINT32 IshGpPinNumber, + OUT GPIO_PAD_NATIVE_FUNCTION *NativePin + ) +{ + if (IsPchLp ()) { + if (IshGpPinNumber < ARRAY_SIZE (mPchLpIshGPGpio)) { + *NativePin =3D mPchLpIshGPGpio[IshGpPinNumber]; + return; + } + } else { + if (IshGpPinNumber < ARRAY_SIZE (mPchHIshGPGpio)) { + *NativePin =3D mPchHIshGPGpio[IshGpPinNumber]; + return; + } + } + *NativePin =3D (GPIO_PAD_NATIVE_FUNCTION){0}; + ASSERT (FALSE); +} + +// +// ISH UART controller pins +// ISH UART[controller number][pin: RXD/TXD/RTSB/CTSB] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpIshUartGpio[]= [PCH_ISH_PINS_PER_UART_CONTROLLER] =3D +{ + { // UART0 + {GPIO_CNL_LP_GPP_D13, GpioPadModeNative1},// ISH_UART0_RXD + {GPIO_CNL_LP_GPP_D14, GpioPadModeNative1},// ISH_UART0_TXD + {GPIO_CNL_LP_GPP_D15, GpioPadModeNative1},// ISH_UART0_RTS + {GPIO_CNL_LP_GPP_D16, GpioPadModeNative1} // ISH_UART0_CTS + }, + { // UART1 + {GPIO_CNL_LP_GPP_C12, GpioPadModeNative2},// ISH_UART1_RXD + {GPIO_CNL_LP_GPP_C13, GpioPadModeNative2},// ISH_UART1_TXD + {GPIO_CNL_LP_GPP_C14, GpioPadModeNative2},// ISH_UART1_RTSB + {GPIO_CNL_LP_GPP_C15, GpioPadModeNative2} // ISH_UART1_CTSB + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHIshUartGpio[][= PCH_ISH_PINS_PER_UART_CONTROLLER] =3D +{ + { // UART0 + {GPIO_CNL_H_GPP_D13, GpioPadModeNative1},// ISH_UART0_RXD + {GPIO_CNL_H_GPP_D14, GpioPadModeNative1},// ISH_UART0_TXD + {GPIO_CNL_H_GPP_D15, GpioPadModeNative1},// ISH_UART0_RTS + {GPIO_CNL_H_GPP_D16, GpioPadModeNative1} // ISH_UART0_CTS + }, + { // UART1 + {GPIO_CNL_H_GPP_C12, GpioPadModeNative2},// ISH_UART1_RXD + {GPIO_CNL_H_GPP_C13, GpioPadModeNative2},// ISH_UART1_TXD + {GPIO_CNL_H_GPP_C14, GpioPadModeNative2},// ISH_UART1_RTS + {GPIO_CNL_H_GPP_C15, GpioPadModeNative2} // ISH_UART1_CTS + } +}; + +/** + This function provides ISH UART controller pins + + @param[in] IshUartControllerNumber ISH UART controller + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetIshUartPins ( + IN UINT32 IshUartControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + if (IshUartControllerNumber < ARRAY_SIZE (mPchLpIshUartGpio)) { + *NativePinsTable =3D mPchLpIshUartGpio[IshUartControllerNumber]; + return; + } + } else { + if (IshUartControllerNumber < ARRAY_SIZE (mPchHIshUartGpio)) { + *NativePinsTable =3D mPchHIshUartGpio[IshUartControllerNumber]; + return; + } + } + *NativePinsTable =3D NULL; + ASSERT (FALSE); +} + +// +// ISH I2C controller pins +// ISH I2C[controller number][pin: SDA/SCL] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpIshI2cGpio[][= PCH_ISH_PINS_PER_I2C_CONTROLLER] =3D +{ + { // I2C0 + {GPIO_CNL_LP_GPP_D5, GpioPadModeNative1},// ISH_I2C0_SDA + {GPIO_CNL_LP_GPP_D6, GpioPadModeNative1} // ISH_I2C0_SCL + }, + { // I2C1 + {GPIO_CNL_LP_GPP_D7, GpioPadModeNative1},// ISH_I2C1_SDA + {GPIO_CNL_LP_GPP_D8, GpioPadModeNative1} // ISH_I2C1_SCL + }, + { // I2C2 + {GPIO_CNL_LP_GPP_H10, GpioPadModeNative2},// ISH_I2C2_SDA + {GPIO_CNL_LP_GPP_H11, GpioPadModeNative2} // ISH_I2C2_SCL + }, + { // I2C3 + {GPIO_CNL_LP_GPP_H4, GpioPadModeNative2},// ISH_I2C3_SDA + {GPIO_CNL_LP_GPP_H5, GpioPadModeNative2} // ISH_I2C3_SCL + }, + { // I2C4 + {GPIO_CNL_LP_GPP_H6, GpioPadModeNative2},// ISH_I2C4_SDA + {GPIO_CNL_LP_GPP_H7, GpioPadModeNative2} // ISH_I2C4_SCL + }, + { // I2C5 + {GPIO_CNL_LP_GPP_H8, GpioPadModeNative2},// ISH_I2C5_SDA + {GPIO_CNL_LP_GPP_H9, GpioPadModeNative2} // ISH_I2C5_SCL + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHIshI2cGpio[][P= CH_ISH_PINS_PER_I2C_CONTROLLER] =3D +{ + { // I2C0 + {GPIO_CNL_H_GPP_H19, GpioPadModeNative1},// ISH_I2C0_SDA + {GPIO_CNL_H_GPP_H20, GpioPadModeNative1} // ISH_I2C0_SCL + }, + { // I2C1 + {GPIO_CNL_H_GPP_H21, GpioPadModeNative1},// ISH_I2C1_SDA + {GPIO_CNL_H_GPP_H22, GpioPadModeNative1} // ISH_I2C1_SCL + }, + { // I2C2 + {GPIO_CNL_H_GPP_D4, GpioPadModeNative1},// ISH_I2C2_SDA + {GPIO_CNL_H_GPP_D23, GpioPadModeNative1} // ISH_I2C2_SCL + } +}; + +/** + This function provides ISH I2C controller pins + + @param[in] IshI2cControllerNumber ISH I2C controller + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetIshI2cPins ( + IN UINT32 IshI2cControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + if (IshI2cControllerNumber < ARRAY_SIZE (mPchLpIshI2cGpio)) { + *NativePinsTable =3D mPchLpIshI2cGpio[IshI2cControllerNumber]; + return; + } + } else { + if (IshI2cControllerNumber < ARRAY_SIZE (mPchHIshI2cGpio)) { + *NativePinsTable =3D mPchHIshI2cGpio[IshI2cControllerNumber]; + return; + } + } + *NativePinsTable =3D NULL; + ASSERT (FALSE); +} + +// +// ISH SPI controller pins +// ISH SPI[pin: CSB/CLK/MISO/MOSI] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpIshSpiGpio[PC= H_ISH_PINS_PER_SPI_CONTROLLER] =3D +{ + {GPIO_CNL_LP_GPP_D9, GpioPadModeNative1},// ISH_SPI_CSB + {GPIO_CNL_LP_GPP_D10, GpioPadModeNative1},// ISH_SPI_CLK + {GPIO_CNL_LP_GPP_D11, GpioPadModeNative1},// ISH_SPI_MISO + {GPIO_CNL_LP_GPP_D12, GpioPadModeNative1} // ISH_SPI_MOSI +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHIshSpiGpio[PCH= _ISH_PINS_PER_SPI_CONTROLLER] =3D +{ + {GPIO_CNL_H_GPP_D9, GpioPadModeNative1},// ISH_SPI_CSB + {GPIO_CNL_H_GPP_D10, GpioPadModeNative1},// ISH_SPI_CLK + {GPIO_CNL_H_GPP_D11, GpioPadModeNative1},// ISH_SPI_MISO + {GPIO_CNL_H_GPP_D12, GpioPadModeNative1} // ISH_SPI_MOSI +}; + +/** + This function provides ISH SPI controller pins + + @param[in] IshSpiControllerNumber SPI controller + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetIshSpiPins ( + IN UINT32 IshSpiControllerNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ) +{ + if (IsPchLp ()) { + if (IshSpiControllerNumber < ARRAY_SIZE (mPchLpIshSpiGpio)) { + *NativePinsTable =3D mPchLpIshSpiGpio; + *NoOfNativePins =3D ARRAY_SIZE (mPchLpIshSpiGpio); + return; + } + } else { + if (IshSpiControllerNumber < ARRAY_SIZE (mPchHIshSpiGpio)) { + *NativePinsTable =3D mPchHIshSpiGpio; + *NoOfNativePins =3D ARRAY_SIZE (mPchHIshSpiGpio); + return; + } + } + + *NoOfNativePins =3D 0; + *NativePinsTable =3D NULL; + ASSERT (FALSE); +} + +// +// GPIO pins for SD controller +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpScsSdCardGpio= [9] =3D +{ + {GPIO_CNL_LP_GPP_A17, GpioPadModeNative1},// SD_PWR_EN_B + {GPIO_CNL_LP_GPP_G0, GpioPadModeNative1},// SD_CMD + {GPIO_CNL_LP_GPP_G1, GpioPadModeNative1},// SD_DATA_0 + {GPIO_CNL_LP_GPP_G2, GpioPadModeNative1},// SD_DATA_1 + {GPIO_CNL_LP_GPP_G3, GpioPadModeNative1},// SD_DATA_2 + {GPIO_CNL_LP_GPP_G4, GpioPadModeNative1},// SD_DATA_3 + {GPIO_CNL_LP_GPP_G5, GpioPadModeNative1},// SD_CDB + {GPIO_CNL_LP_GPP_G6, GpioPadModeNative1},// SD_CLK + {GPIO_CNL_LP_GPP_G7, GpioPadModeNative1} // SD_WP +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHScsSdCardGpio[= 9] =3D +{ + {GPIO_CNL_H_GPP_A17, GpioPadModeNative1},// SD_PWR_EN_B + {GPIO_CNL_H_GPP_G0, GpioPadModeNative1},// SD_CMD + {GPIO_CNL_H_GPP_G1, GpioPadModeNative1},// SD_DATA_0 + {GPIO_CNL_H_GPP_G2, GpioPadModeNative1},// SD_DATA_1 + {GPIO_CNL_H_GPP_G3, GpioPadModeNative1},// SD_DATA_2 + {GPIO_CNL_H_GPP_G4, GpioPadModeNative1},// SD_DATA_3 + {GPIO_CNL_H_GPP_G5, GpioPadModeNative1},// SD_CDB + {GPIO_CNL_H_GPP_G6, GpioPadModeNative1},// SD_CLK + {GPIO_CNL_H_GPP_G7, GpioPadModeNative1} // SD_WP +}; + +/** + This function provides SCS SD CARD controller pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetScsSdCardPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpScsSdCardGpio; + *NoOfNativePins =3D ARRAY_SIZE (mPchLpScsSdCardGpio); + } else { + *NativePinsTable =3D mPchHScsSdCardGpio; + *NoOfNativePins =3D ARRAY_SIZE (mPchHScsSdCardGpio); + } +} + +/** + This function provides SCS SD CARD detect pin + + @retval GpioPin SD CARD Detect pin +**/ +GPIO_PAD +GpioGetScsSdCardDetectPin ( + VOID + ) +{ + if (IsPchLp ()) { + return GPIO_CNL_LP_VGPIO39; + } else { + return GPIO_CNL_H_VGPIO6; + } +} + +// +// GPIO pins for eMMC controller +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpScsEmmcGpio[1= 2] =3D +{ + {GPIO_CNL_LP_GPP_F11, GpioPadModeNative1},// EMMC_CMD + {GPIO_CNL_LP_GPP_F12, GpioPadModeNative1},// EMMC_DATA_0 + {GPIO_CNL_LP_GPP_F13, GpioPadModeNative1},// EMMC_DATA_1 + {GPIO_CNL_LP_GPP_F14, GpioPadModeNative1},// EMMC_DATA_2 + {GPIO_CNL_LP_GPP_F15, GpioPadModeNative1},// EMMC_DATA_3 + {GPIO_CNL_LP_GPP_F16, GpioPadModeNative1},// EMMC_DATA_4 + {GPIO_CNL_LP_GPP_F17, GpioPadModeNative1},// EMMC_DATA_5 + {GPIO_CNL_LP_GPP_F18, GpioPadModeNative1},// EMMC_DATA_6 + {GPIO_CNL_LP_GPP_F19, GpioPadModeNative1},// EMMC_DATA_7 + {GPIO_CNL_LP_GPP_F20, GpioPadModeNative1},// EMMC_RCLK + {GPIO_CNL_LP_GPP_F21, GpioPadModeNative1},// EMMC_CLK + {GPIO_CNL_LP_GPP_F22, GpioPadModeNative1} // EMMC_RESETB +}; + +/** + This function provides SCS eMMC controller pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetScsEmmcPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpScsEmmcGpio; + *NoOfNativePins =3D ARRAY_SIZE (mPchLpScsEmmcGpio); + } else { + ASSERT (FALSE); + return; + } +} + +// +// GPIO pins for HD Audio Link [pin: BCLK/RSTB/SYNC/SDO/SDIx] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpHdaLinkGpio[P= CH_GPIO_HDA_LINK_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_HDA_BCLK, GpioPadModeNative1},// HDA_BCLK + {GPIO_CNL_LP_HDA_RSTB, GpioPadModeNative1},// HDA_RSTB + {GPIO_CNL_LP_HDA_SYNC, GpioPadModeNative1},// HDA_SYNC + {GPIO_CNL_LP_HDA_SDO, GpioPadModeNative1},// HDA_SDO + {GPIO_CNL_LP_HDA_SDI_0, GpioPadModeNative1},// HDA_SDI_0 + {GPIO_CNL_LP_HDA_SDI_1, GpioPadModeNative1} // HDA_SDI_1 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHHdaLinkGpio[PC= H_GPIO_HDA_LINK_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_HDA_BCLK, GpioPadModeNative1},// HDA_BCLK + {GPIO_CNL_H_HDA_RSTB, GpioPadModeNative1},// HDA_RSTB + {GPIO_CNL_H_HDA_SYNC, GpioPadModeNative1},// HDA_SYNC + {GPIO_CNL_H_HDA_SDO, GpioPadModeNative1},// HDA_SDO + {GPIO_CNL_H_HDA_SDI_0, GpioPadModeNative1},// HDA_SDI_0 + {GPIO_CNL_H_HDA_SDI_1, GpioPadModeNative1} // HDA_SDI_1 +}; + +/** + This function provides HD Audio Link pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetHdAudioLinkPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpHdaLinkGpio; + *NoOfNativePins =3D ARRAY_SIZE (mPchLpHdaLinkGpio); + } else { + *NativePinsTable =3D mPchHHdaLinkGpio; + *NoOfNativePins =3D ARRAY_SIZE (mPchHHdaLinkGpio); + } +} + +// +// GPIO pins for HD Audio DMIC [DMIC number][pin: CLK/DATA] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpHdaDmicGpio[]= [PCH_GPIO_HDA_DMIC_NUMBER_OF_PINS] =3D +{ + { // DMIC0 + {GPIO_CNL_LP_GPP_D19, GpioPadModeNative1},// DMIC_CLK_0 + {GPIO_CNL_LP_GPP_D20, GpioPadModeNative1} // DMIC_DATA_0 + }, + { // DMIC1 + {GPIO_CNL_LP_GPP_D17, GpioPadModeNative1},// DMIC_CLK_1 + {GPIO_CNL_LP_GPP_D18, GpioPadModeNative1} // DMIC_DATA_1 + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHHdaDmicGpio[][= PCH_GPIO_HDA_DMIC_NUMBER_OF_PINS] =3D +{ + { // DMIC0 + {GPIO_CNL_H_GPP_D19, GpioPadModeNative1},// DMIC_CLK_0 + {GPIO_CNL_H_GPP_D20, GpioPadModeNative1} // DMIC_DATA_0 + }, + { // DMIC1 + {GPIO_CNL_H_GPP_D17, GpioPadModeNative1},// DMIC_CLK_1 + {GPIO_CNL_H_GPP_D18, GpioPadModeNative1} // DMIC_DATA_1 + } +}; + +/** + This function provides DMIC interface pins + + @param[in] DmicNumber DMIC interface + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetHdaDmicPins ( + IN UINT32 DmicNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + if (DmicNumber < ARRAY_SIZE (mPchLpHdaDmicGpio)) { + *NativePinsTable =3D mPchLpHdaDmicGpio[DmicNumber]; + return; + } + } else { + if (DmicNumber < ARRAY_SIZE (mPchHHdaDmicGpio)) { + *NativePinsTable =3D mPchHHdaDmicGpio[DmicNumber]; + return; + } + } + *NativePinsTable =3D NULL; + ASSERT (FALSE); +} + +// +// GPIO pins for HD Audio SSPx/I2Sx interface [SSP number][pin: SCLK/SFRM/= TXD/RXD] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpHdaSspInterfa= ceGpio[][PCH_GPIO_HDA_SSP_NUMBER_OF_PINS] =3D +{ + { // SSP0/I2S0 + {GPIO_CNL_LP_HDA_BCLK, GpioPadModeNative2},// SSP0_SCLK + {GPIO_CNL_LP_HDA_SYNC, GpioPadModeNative2},// SSP0_SFRM + {GPIO_CNL_LP_HDA_SDO, GpioPadModeNative2},// SSP0_TXD + {GPIO_CNL_LP_HDA_SDI_0, GpioPadModeNative2} // SSP0_RXD + }, + { // SSP1/I2S1 + {GPIO_CNL_LP_HDA_RSTB, GpioPadModeNative2},// SSP1_SCLK + {GPIO_CNL_LP_SSP1_SFRM, GpioPadModeNative1},// SSP1_SFRM + {GPIO_CNL_LP_SSP1_TXD, GpioPadModeNative1},// SSP1_TXD + {GPIO_CNL_LP_HDA_SDI_1, GpioPadModeNative2} // SSP1_RXD + }, + { // SSP2/I2S2 + {GPIO_CNL_LP_GPP_H0, GpioPadModeNative1},// SSP2_SCLK + {GPIO_CNL_LP_GPP_H1, GpioPadModeNative1},// SSP2_SFRM + {GPIO_CNL_LP_GPP_H2, GpioPadModeNative1},// SSP2_TXD + {GPIO_CNL_LP_GPP_H3, GpioPadModeNative1} // SSP2_RXD + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHHdaSspInterfac= eGpio[][PCH_GPIO_HDA_SSP_NUMBER_OF_PINS] =3D +{ + { // SSP0/I2S0 + {GPIO_CNL_H_HDA_BCLK, GpioPadModeNative2},// SSP0_SCLK + {GPIO_CNL_H_HDA_SYNC, GpioPadModeNative2},// SSP0_SFRM + {GPIO_CNL_H_HDA_SDO, GpioPadModeNative2},// SSP0_TXD + {GPIO_CNL_H_HDA_SDI_0, GpioPadModeNative2} // SSP0_RXD + }, + { // SSP1/I2S1 + {GPIO_CNL_H_HDA_RSTB, GpioPadModeNative2},// SSP1_SCLK + {GPIO_CNL_H_SSP1_SFRM, GpioPadModeNative1},// SSP1_SFRM + {GPIO_CNL_H_SSP1_TXD, GpioPadModeNative1},// SSP1_TXD + {GPIO_CNL_H_HDA_SDI_1, GpioPadModeNative2} // SSP1_RXD + }, + { // SSP2/I2S2 + {GPIO_CNL_H_GPP_D5, GpioPadModeNative1}, // SSP2_SFRM + {GPIO_CNL_H_GPP_D6, GpioPadModeNative1}, // SSP2_TXD + {GPIO_CNL_H_GPP_D7, GpioPadModeNative1}, // SSP2_RXD + {GPIO_CNL_H_GPP_D8, GpioPadModeNative1} // SSP2_SCLK + } +}; + +/** + This function provides SSP/I2S interface pins + + @param[in] SspInterfaceNumber SSP/I2S interface + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetHdaSspPins ( + IN UINT32 SspInterfaceNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + if (SspInterfaceNumber < ARRAY_SIZE (mPchLpHdaSspInterfaceGpio)) { + *NativePinsTable =3D mPchLpHdaSspInterfaceGpio[SspInterfaceNumber]; + return; + } + } else { + if (SspInterfaceNumber < ARRAY_SIZE (mPchHHdaSspInterfaceGpio)) { + *NativePinsTable =3D mPchHHdaSspInterfaceGpio[SspInterfaceNumber]; + return; + } + } + *NativePinsTable =3D NULL; + ASSERT (FALSE); +} + +// +// GPIO Pin for HD Audio SSP_MCLK/I2S_MCLK +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpHdaSspMasterC= lockGpio =3D {GPIO_CNL_LP_GPP_D23, GpioPadModeNative1}; +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHHdaSspMasterCl= ockGpio =3D {GPIO_CNL_H_GPP_B11, GpioPadModeNative1}; + +/** + This function sets HDA SSP Master Clock into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableHdaSspMasterClock ( + VOID + ) +{ + if (IsPchLp ()) { + return GpioSetPadMode (mPchLpHdaSspMasterClockGpio.Pad, mPchLpHdaSspMa= sterClockGpio.Mode); + } else { + return GpioSetPadMode (mPchHHdaSspMasterClockGpio.Pad, mPchHHdaSspMast= erClockGpio.Mode); + } +} + +// +// GPIO pins for HD Audio SoundWire interface [SNDW number][pin: CLK/DATA] +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpHdaSndwGpio[]= [PCH_GPIO_HDA_SNDW_NUMBER_OF_PINS] =3D +{ + { // SNDW1 + {GPIO_CNL_LP_HDA_RSTB, GpioPadModeNative3},// SNDW1_CLK + {GPIO_CNL_LP_HDA_SDI_1, GpioPadModeNative3} // SNDW1_DATA + }, + { // SNDW2 + {GPIO_CNL_LP_SSP1_SFRM, GpioPadModeNative2},// SNDW2_CLK + {GPIO_CNL_LP_SSP1_TXD, GpioPadModeNative2} // SNDW2_DATA + }, + { // SNDW3 + {GPIO_CNL_LP_GPP_D17, GpioPadModeNative2},// SNDW3_CLK + {GPIO_CNL_LP_GPP_D18, GpioPadModeNative2} // SNDW3_DATA + }, + { // SNDW4 + {GPIO_CNL_LP_GPP_D19, GpioPadModeNative2},// SNDW4_CLK + {GPIO_CNL_LP_GPP_D20, GpioPadModeNative2} // SNDW4_DATA + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHHdaSndwGpio[][= PCH_GPIO_HDA_SNDW_NUMBER_OF_PINS] =3D +{ + { // SNDW1 + {GPIO_CNL_H_HDA_RSTB, GpioPadModeNative3},// SNDW1_CLK + {GPIO_CNL_H_HDA_SDI_1, GpioPadModeNative3} // SNDW1_DATA + }, + { // SNDW2 + {GPIO_CNL_H_SSP1_SFRM, GpioPadModeNative2},// SNDW2_CLK + {GPIO_CNL_H_SSP1_TXD, GpioPadModeNative2} // SNDW2_DATA + }, + { // SNDW3 + {GPIO_CNL_H_GPP_D17, GpioPadModeNative2},// SNDW3_CLK + {GPIO_CNL_H_GPP_D18, GpioPadModeNative2} // SNDW3_DATA + }, + { // SNDW4 + {GPIO_CNL_H_GPP_D19, GpioPadModeNative2},// SNDW4_CLK + {GPIO_CNL_H_GPP_D20, GpioPadModeNative2} // SNDW4_DATA + } +}; + +/** + This function provides SNDW interface pins + + @param[in] SndwInterfaceNumber SNDWx interface number + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetHdaSndwPins ( + IN UINT32 SndwInterfaceNumber, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + if (SndwInterfaceNumber < ARRAY_SIZE (mPchLpHdaSndwGpio)) { + *NativePinsTable =3D mPchLpHdaSndwGpio[SndwInterfaceNumber]; + return; + } + } else { + if (SndwInterfaceNumber < ARRAY_SIZE (mPchHHdaSndwGpio)) { + *NativePinsTable =3D mPchHHdaSndwGpio[SndwInterfaceNumber]; + return; + } + } + *NativePinsTable =3D NULL; + ASSERT (FALSE); +} + +// +// GPIO pins for SMBUS +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpSmbusGpio[PCH= _GPIO_SMBUS_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_GPP_C0, GpioPadModeNative1},// SMB_CLK + {GPIO_CNL_LP_GPP_C1, GpioPadModeNative1} // SMB_DATA +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHSmbusGpio[PCH_= GPIO_SMBUS_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_GPP_C0, GpioPadModeNative1}, // SMB_CLK + {GPIO_CNL_H_GPP_C1, GpioPadModeNative1} // SMB_DATA +}; + +/** + This function provides SMBUS interface pins + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetSmbusPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpSmbusGpio; + } else { + *NativePinsTable =3D mPchHSmbusGpio; + } +} + +// +// SMBUS Alert pin +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpSmbusAlertGpi= o =3D {GPIO_CNL_LP_GPP_C2, GpioPadModeNative1}; +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHSmbusAlertGpio= =3D {GPIO_CNL_H_GPP_C2, GpioPadModeNative1}; + +/** + This function sets SMBUS ALERT pin into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableSmbusAlert ( + VOID + ) +{ + GPIO_PAD_NATIVE_FUNCTION SmbusAlertGpio; + + if (IsPchLp ()) { + SmbusAlertGpio =3D mPchLpSmbusAlertGpio; + } else { + SmbusAlertGpio =3D mPchHSmbusAlertGpio; + } + + return GpioSetPadMode (SmbusAlertGpio.Pad, SmbusAlertGpio.Mode); +} + +// +// SATADevSlpPin to GPIO pin mapping +// SATA_DEVSLP_x -> GPIO pin y +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpSataDevSlpPin= ToGpioMap[] =3D +{ + {GPIO_CNL_LP_GPP_E4, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_E5, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_E6, GpioPadModeNative1} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHSataDevSlpPinT= oGpioMap[] =3D +{ + {GPIO_CNL_H_GPP_E4, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_E5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_E6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F7, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F8, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F9, GpioPadModeNative1} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mCdfPchSata1DevSlpP= inToGpioMap[] =3D +{ +/// @todo SERVER- update for SATA 1 + {GPIO_CNL_H_GPP_E4, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_E5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_E6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F7, GpioPadModeNative1} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mCdfPchSata2DevSlpP= inToGpioMap[] =3D +{ +/// @todo SERVER- update for SATA 2 + {GPIO_CNL_H_GPP_E4, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_E5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_E6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F7, GpioPadModeNative1} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mCdfPchSata3DevSlpP= inToGpioMap[] =3D +{ +/// @todo SERVER- update for SATA 3 + {GPIO_CNL_H_GPP_E4, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_E5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_E6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_F7, GpioPadModeNative1} +}; + +/** + This function provides SATA DevSlp pin data + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + @param[out] NativePin SATA DevSlp pin +**/ +VOID +GpioGetSataDevSlpPin ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort, + OUT GPIO_PAD_NATIVE_FUNCTION *NativePin + ) +{ + if (IsCdfPch ()) { + if (SataCtrlIndex =3D=3D SATA_1_CONTROLLER_INDEX) { + if (SataPort < ARRAY_SIZE (mCdfPchSata1DevSlpPinToGpioMap)) { + *NativePin =3D mCdfPchSata1DevSlpPinToGpioMap[SataPort]; + return; + } + } else if (SataCtrlIndex =3D=3D SATA_2_CONTROLLER_INDEX) { + if (SataPort < ARRAY_SIZE (mCdfPchSata2DevSlpPinToGpioMap)) { + *NativePin =3D mCdfPchSata2DevSlpPinToGpioMap[SataPort]; + return; + } + } else if (SataCtrlIndex =3D=3D SATA_3_CONTROLLER_INDEX) { + if (SataPort < ARRAY_SIZE (mCdfPchSata3DevSlpPinToGpioMap)) { + *NativePin =3D mCdfPchSata3DevSlpPinToGpioMap[SataPort]; + return; + } + } + } else { + if (IsPchLp ()) { + if (SataPort < ARRAY_SIZE (mPchLpSataDevSlpPinToGpioMap)) { + *NativePin =3D mPchLpSataDevSlpPinToGpioMap[SataPort]; + return; + } + } else { + if (SataPort < ARRAY_SIZE (mPchHSataDevSlpPinToGpioMap)) { + *NativePin =3D mPchHSataDevSlpPinToGpioMap[SataPort]; + return; + } + } + } + *NativePin =3D (GPIO_PAD_NATIVE_FUNCTION){0}; + ASSERT (FALSE); +} + +// +// SATA reset port to GPIO pin mapping +// SATAGP_x -> GPIO pin y +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpSataGpToGpioM= ap[] =3D +{ + {GPIO_CNL_LP_GPP_E0, GpioPadModeNative2}, + {GPIO_CNL_LP_GPP_E1, GpioPadModeNative2}, + {GPIO_CNL_LP_GPP_E2, GpioPadModeNative2} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHSataGpToGpioMa= p[] =3D +{ + {GPIO_CNL_H_GPP_E0, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_E1, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_E2, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F0, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F1, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F2, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F3, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F4, GpioPadModeNative2} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mCdfPchSata1GpToGpi= oMap[] =3D +{ +/// @todo SERVER- update for SATA 1 + {GPIO_CNL_H_GPP_E0, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_E1, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_E2, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F0, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F1, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F2, GpioPadModeNative2} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mCdfPchSata2GpToGpi= oMap[] =3D +{ +/// @todo SERVER- update for SATA 2 + {GPIO_CNL_H_GPP_E0, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_E1, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_E2, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F0, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F1, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F2, GpioPadModeNative2} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mCdfPchSata3GpToGpi= oMap[] =3D +{ +/// @todo SERVER- update for SATA 3 + {GPIO_CNL_H_GPP_E0, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_E1, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_E2, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F0, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F1, GpioPadModeNative2}, + {GPIO_CNL_H_GPP_F2, GpioPadModeNative2} +}; + +/** + This function provides SATA GP pin data + + @param[in] SataCtrlIndex SATA controller index + @param[in] SataPort SATA port number + @param[out] NativePin SATA GP pin +**/ +VOID +GpioGetSataGpPin ( + IN UINT32 SataCtrlIndex, + IN UINTN SataPort, + OUT GPIO_PAD_NATIVE_FUNCTION *NativePin + ) +{ + if (IsCdfPch ()) { + if (SataCtrlIndex =3D=3D SATA_1_CONTROLLER_INDEX) { + if (SataPort < ARRAY_SIZE (mCdfPchSata1GpToGpioMap)) { + *NativePin =3D mCdfPchSata1GpToGpioMap[SataPort]; + return; + } + } else if (SataCtrlIndex =3D=3D SATA_2_CONTROLLER_INDEX) { + if (SataPort < ARRAY_SIZE (mCdfPchSata2GpToGpioMap)) { + *NativePin =3D mCdfPchSata2GpToGpioMap[SataPort]; + return; + } + } else if (SataCtrlIndex =3D=3D SATA_3_CONTROLLER_INDEX) { + if (SataPort < ARRAY_SIZE (mCdfPchSata3GpToGpioMap)) { + *NativePin =3D mCdfPchSata3GpToGpioMap[SataPort]; + return; + } + } + } else { + if (IsPchLp ()) { + if (SataPort < ARRAY_SIZE (mPchLpSataGpToGpioMap)) { + *NativePin =3D mPchLpSataGpToGpioMap[SataPort]; + return; + } + } else { + if (SataPort < ARRAY_SIZE (mPchHSataGpToGpioMap)) { + *NativePin =3D mPchHSataGpToGpioMap[SataPort]; + return; + } + } + } + *NativePin =3D (GPIO_PAD_NATIVE_FUNCTION){0}; + ASSERT (FALSE); +} + +// +// SATA LED pin +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpSataLedGpio = =3D {GPIO_CNL_LP_GPP_E8, GpioPadModeNative1}; +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHSataLedGpio = =3D {GPIO_CNL_H_GPP_E8, GpioPadModeNative1}; + +/** + This function sets SATA LED pin into native mode. SATA LED indicates + SATA controller activity + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableSataLed ( + VOID + ) +{ + GPIO_PAD_NATIVE_FUNCTION SataLedGpio; + + if (IsPchLp ()) { + SataLedGpio =3D mPchLpSataLedGpio; + } else { + SataLedGpio =3D mPchHSataLedGpio; + } + + return GpioSetPadMode (SataLedGpio.Pad, SataLedGpio.Mode); +} + +// +// USB2 OC pins +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpUsbOcGpioPins= [] =3D +{ + {GPIO_CNL_LP_GPP_E9, GpioPadModeNative1},// USB_OC_0 + {GPIO_CNL_LP_GPP_E10, GpioPadModeNative1},// USB_OC_1 + {GPIO_CNL_LP_GPP_E11, GpioPadModeNative1},// USB_OC_2 + {GPIO_CNL_LP_GPP_E12, GpioPadModeNative1} // USB_OC_3 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHUsbOcGpioPins[= ] =3D +{ + {GPIO_CNL_H_GPP_E9, GpioPadModeNative1},// USB_OC_0 + {GPIO_CNL_H_GPP_E10, GpioPadModeNative1},// USB_OC_1 + {GPIO_CNL_H_GPP_E11, GpioPadModeNative1},// USB_OC_2 + {GPIO_CNL_H_GPP_E12, GpioPadModeNative1},// USB_OC_3 + {GPIO_CNL_H_GPP_F15, GpioPadModeNative1},// USB_OC_4 + {GPIO_CNL_H_GPP_F16, GpioPadModeNative1},// USB_OC_5 + {GPIO_CNL_H_GPP_F17, GpioPadModeNative1},// USB_OC_6 + {GPIO_CNL_H_GPP_F18, GpioPadModeNative1} // USB_OC_7 +}; + +/** + This function enables USB OverCurrent pins by setting + USB2 OCB pins into native mode + + @param[in] OcPinNumber USB OC pin number + + @retval Status +**/ +EFI_STATUS +GpioEnableUsbOverCurrent ( + IN UINTN OcPinNumber + ) +{ + GPIO_PAD_NATIVE_FUNCTION OcGpio; + + if (IsPchLp ()) { + if (OcPinNumber >=3D ARRAY_SIZE (mPchLpUsbOcGpioPins)) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + OcGpio =3D mPchLpUsbOcGpioPins[OcPinNumber]; + } else { + if (OcPinNumber >=3D ARRAY_SIZE (mPchHUsbOcGpioPins)) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + OcGpio =3D mPchHUsbOcGpioPins[OcPinNumber]; + } + + return GpioSetPadMode (OcGpio.Pad, OcGpio.Mode); +} + +// +// GPIO pin for PCIE SCRCLKREQB +// SCRCLKREQB_x -> GPIO pin y +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpPcieSrcClkReq= bPinToGpioMap[] =3D +{ + {GPIO_CNL_LP_GPP_B5, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B6, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B7, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B8, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B9, GpioPadModeNative1}, + {GPIO_CNL_LP_GPP_B10, GpioPadModeNative1} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHPcieSrcClkReqb= PinToGpioMap[] =3D +{ + {GPIO_CNL_H_GPP_B5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B7, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B8, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B9, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_B10, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H0, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H1, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H2, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H3, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H4, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H5, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H6, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H7, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H8, GpioPadModeNative1}, + {GPIO_CNL_H_GPP_H9, GpioPadModeNative1} +}; + +/** + This function provides PCIe CLKREQ pin data + + @param[in] ClkreqIndex CLKREQ# number + @param[out] NativePin Native pin data +**/ +VOID +GpioGetPcieClkReqPin ( + IN UINT32 ClkreqIndex, + OUT GPIO_PAD_NATIVE_FUNCTION *NativePin + ) +{ + if (IsPchLp ()) { + if (ClkreqIndex < ARRAY_SIZE (mPchLpPcieSrcClkReqbPinToGpioMap)) { + *NativePin =3D mPchLpPcieSrcClkReqbPinToGpioMap[ClkreqIndex]; + return; + } + } else { + if (ClkreqIndex < ARRAY_SIZE (mPchHPcieSrcClkReqbPinToGpioMap)) { + *NativePin =3D mPchHPcieSrcClkReqbPinToGpioMap[ClkreqIndex]; + return; + } + } + *NativePin =3D (GPIO_PAD_NATIVE_FUNCTION){0}; + ASSERT (FALSE); +} + +// +// PCHHOTB pin +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpPchHotbPin = =3D {GPIO_CNL_LP_GPP_B23, GpioPadModeNative2}; +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHPchHotbPin =3D= {GPIO_CNL_H_GPP_B23, GpioPadModeNative2}; + +/** + This function sets PCHHOT pin into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnablePchHot ( + VOID + ) +{ + GPIO_PAD_NATIVE_FUNCTION PchHotbPin; + + if (IsPchLp ()) { + PchHotbPin =3D mPchLpPchHotbPin; + } else { + PchHotbPin =3D mPchHPchHotbPin; + } + + return GpioSetPadMode (PchHotbPin.Pad, PchHotbPin.Mode); +} + +// +// VRALERTB pin +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpVrAlertbPin = =3D {GPIO_CNL_LP_GPP_B2, GpioPadModeNative1}; +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHVrAlertbPin = =3D {GPIO_CNL_H_GPP_B2, GpioPadModeNative1}; + +// +// CPU_C10_GATE pin +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpCpuC10GatePin= =3D {GPIO_CNL_LP_GPP_H18, GpioPadModeNative1}; +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHCpuC10GatePin = =3D {GPIO_CNL_H_GPP_J1, GpioPadModeNative2}; + +/** + This function sets VRALERTB pin into native mode + + @param[in] none + + @retval Status +**/ +EFI_STATUS +GpioEnableVrAlert ( + VOID + ) +{ + GPIO_PAD_NATIVE_FUNCTION VrAlertGpio; + + if (IsPchLp ()) { + VrAlertGpio =3D mPchLpVrAlertbPin; + } else { + VrAlertGpio =3D mPchHVrAlertbPin; + } + + return GpioSetPadMode (VrAlertGpio.Pad, VrAlertGpio.Mode); +} + +/** +This function sets CPU C10 Gate pins into native mode + +@retval Status +**/ +EFI_STATUS +GpioEnableCpuC10GatePin ( + VOID + ) +{ + GPIO_PAD_NATIVE_FUNCTION CpuC10GateGpio; + + if (IsPchLp ()) { + CpuC10GateGpio =3D mPchLpCpuC10GatePin; + } else { + CpuC10GateGpio =3D mPchHCpuC10GatePin; + } + + return GpioSetPadMode (CpuC10GateGpio.Pad, CpuC10GateGpio.Mode); +} + +// +// CPU GP pins +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpCpuGpPinMap[P= CH_GPIO_CPU_GP_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_GPP_E3, GpioPadModeNative1}, // CPU_GP_0 + {GPIO_CNL_LP_GPP_E7, GpioPadModeNative1}, // CPU_GP_1 + {GPIO_CNL_LP_GPP_B3, GpioPadModeNative1}, // CPU_GP_2 + {GPIO_CNL_LP_GPP_B4, GpioPadModeNative1}, // CPU_GP_3 +}; +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHCpuGpPinMap[PC= H_GPIO_CPU_GP_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_GPP_E3, GpioPadModeNative1}, // CPU_GP_0 + {GPIO_CNL_H_GPP_E7, GpioPadModeNative1}, // CPU_GP_1 + {GPIO_CNL_H_GPP_B3, GpioPadModeNative1}, // CPU_GP_2 + {GPIO_CNL_H_GPP_B4, GpioPadModeNative1}, // CPU_GP_3 +}; + +/** + This function sets CPU GP pins into native mode + + @param[in] CpuGpPinNum CPU GP pin number + + @retval Status +**/ +EFI_STATUS +GpioEnableCpuGpPin ( + IN UINT32 CpuGpPinNum + ) +{ + GPIO_PAD_NATIVE_FUNCTION CpuGpPin; + + if (IsPchLp ()) { + if (CpuGpPinNum >=3D ARRAY_SIZE (mPchLpCpuGpPinMap)) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + CpuGpPin =3D mPchLpCpuGpPinMap[CpuGpPinNum]; + } else { + if (CpuGpPinNum >=3D ARRAY_SIZE (mPchHCpuGpPinMap)) { + ASSERT(FALSE); + return EFI_UNSUPPORTED; + } + CpuGpPin =3D mPchHCpuGpPinMap[CpuGpPinNum]; + } + + return GpioSetPadMode (CpuGpPin.Pad, CpuGpPin.Mode); +} + +// +// DDSP_HPD pins +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpDdspHpdPins[]= =3D +{ + {GPIO_CNL_LP_GPP_E13, GpioPadModeNative1},// DDSP_HPD_0 + {GPIO_CNL_LP_GPP_E14, GpioPadModeNative1},// DDSP_HPD_1 + {GPIO_CNL_LP_GPP_E15, GpioPadModeNative1},// DDSP_HPD_2 + {GPIO_CNL_LP_GPP_E16, GpioPadModeNative1} // DDSP_HPD_3 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHDdspHpdPins[] = =3D +{ + {GPIO_CNL_H_GPP_I0, GpioPadModeNative1},// DDSP_HPD_0 + {GPIO_CNL_H_GPP_I1, GpioPadModeNative1},// DDSP_HPD_1 + {GPIO_CNL_H_GPP_I2, GpioPadModeNative1},// DDSP_HPD_2 + {GPIO_CNL_H_GPP_I3, GpioPadModeNative1} // DDSP_HPD_3 +}; + +/** + This function sets DDSP_HPDx pin into native mode + + @param[in] DdspHpdPin DDSP_HPDx pin + + @retval Status +**/ +EFI_STATUS +GpioEnableDpHotPlugDetect ( + IN GPIO_DDSP_HPD DdspHpdPin + ) +{ + GPIO_PAD_NATIVE_FUNCTION DdspHpdGpio; + UINT32 DdspHpdPinIndex; + + if (DdspHpdPin > GpioDdspHpd3) { + return EFI_UNSUPPORTED; + } + + DdspHpdPinIndex =3D DdspHpdPin - GpioDdspHpd0; + + if (IsPchLp ()) { + if (DdspHpdPinIndex >=3D ARRAY_SIZE (mPchLpDdspHpdPins)) { + goto Error; + } + DdspHpdGpio =3D mPchLpDdspHpdPins[DdspHpdPinIndex]; + } else { + if (DdspHpdPinIndex >=3D ARRAY_SIZE (mPchHDdspHpdPins)) { + goto Error; + } + DdspHpdGpio =3D mPchHDdspHpdPins[DdspHpdPinIndex]; + } + + return GpioSetPadMode (DdspHpdGpio.Pad, DdspHpdGpio.Mode); +Error: + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +// +// EDP HPD, VDD and BKLT pins +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpEdpPins[PCH_G= PIO_EDP_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_GPP_E17, GpioPadModeNative1},// EDP_HPD + {GPIO_CNL_LP_HVMOS_L_VDDEN, GpioPadModeNative1},// VDDEN + {GPIO_CNL_LP_HVMOS_L_BKLTEN, GpioPadModeNative1},// BKLTEN + {GPIO_CNL_LP_HVMOS_L_BKLTCTL, GpioPadModeNative1} // BKLTCTL +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHEdpPins[PCH_GP= IO_EDP_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_GPP_I4, GpioPadModeNative1},// EDP_HPD + {GPIO_CNL_H_GPP_F19, GpioPadModeNative1},// VDDEN + {GPIO_CNL_H_GPP_F20, GpioPadModeNative1},// BKLTEN + {GPIO_CNL_H_GPP_F21, GpioPadModeNative1} // BKLTCTL +}; + +/** + This function provides eDP pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetEdpPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpEdpPins; + *NoOfNativePins =3D ARRAY_SIZE (mPchLpEdpPins); + } else { + *NativePinsTable =3D mPchHEdpPins; + *NoOfNativePins =3D ARRAY_SIZE (mPchHEdpPins); + } +} + +// +// DDPB/C/D/F CTRLCLK and CTRLDATA pins +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpDdpInterfaceP= ins[PCH_GPIO_DDP_NUMBER_OF_INTERFACES][PCH_GPIO_DDP_NUMBER_OF_PINS] =3D +{ + {// DDPB + {GPIO_CNL_LP_GPP_E18, GpioPadModeNative1},// DDPB_CTRLCLK + {GPIO_CNL_LP_GPP_E19, GpioPadModeNative1} // DDPB_CTRLDATA + }, + {// DDPC + {GPIO_CNL_LP_GPP_E20, GpioPadModeNative1},// DDPC_CTRLCLK + {GPIO_CNL_LP_GPP_E21, GpioPadModeNative1} // DDPC_CTRLDATA + }, + {// DDPD + {GPIO_CNL_LP_GPP_E22, GpioPadModeNative1},// DDPD_CTRLCLK + {GPIO_CNL_LP_GPP_E23, GpioPadModeNative1} // DDPD_CTRLDATA + }, + {// DDPF + {GPIO_CNL_LP_GPP_H16, GpioPadModeNative1},// DDPF_CTRLCLK + {GPIO_CNL_LP_GPP_H17, GpioPadModeNative1} // DDPF_CTRLDATA + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHDdpInterfacePi= ns[PCH_GPIO_DDP_NUMBER_OF_INTERFACES][PCH_GPIO_DDP_NUMBER_OF_PINS] =3D +{ + {// DDPB + {GPIO_CNL_H_GPP_I5, GpioPadModeNative1}, // DDPB_CTRLCLK + {GPIO_CNL_H_GPP_I6, GpioPadModeNative1}, // DDPB_CTRLDATA + }, + {// DDPC + {GPIO_CNL_H_GPP_I7, GpioPadModeNative1}, // DDPC_CTRLCLK + {GPIO_CNL_H_GPP_I8, GpioPadModeNative1}, // DDPC_CTRLDATA + }, + {// DDPD + {GPIO_CNL_H_GPP_I9, GpioPadModeNative1}, // DDPD_CTRLCLK + {GPIO_CNL_H_GPP_I10, GpioPadModeNative1}, // DDPD_CTRLDATA + }, + {// DDPF + {GPIO_CNL_H_GPP_F22, GpioPadModeNative1}, // DDPF_CTRLCLK + {GPIO_CNL_H_GPP_F23, GpioPadModeNative1}, // DDPF_CTRLDATA + } +}; + +/** + This function provides DDPx interface pins + + @param[in] DdpInterface DDPx interface + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetDdpPins ( + IN GPIO_DDP DdpInterface, + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + UINT32 DdpInterfaceIndex; + + switch (DdpInterface) { + case GpioDdpB: + case GpioDdpC: + case GpioDdpD: + DdpInterfaceIndex =3D DdpInterface - GpioDdpB; + break; + case GpioDdpF: + DdpInterfaceIndex =3D 3; + break; + default: + goto Error; + } + + if (IsPchLp ()) { + if (DdpInterfaceIndex < ARRAY_SIZE (mPchLpDdpInterfacePins)) { + *NativePinsTable =3D mPchLpDdpInterfacePins[DdpInterfaceIndex]; + return; + } + } else { + if (DdpInterfaceIndex < ARRAY_SIZE (mPchHDdpInterfacePins)) { + *NativePinsTable =3D mPchHDdpInterfacePins[DdpInterfaceIndex]; + return; + } + } +Error: + *NativePinsTable =3D NULL; + ASSERT(FALSE); +} + +/** + This function enables CNVi RF Reset pin +**/ +VOID +GpioEnableCnviRfResetPin ( + VOID + ) +{ + EFI_STATUS Status; + GPIO_PAD GpioPad; + GPIO_PAD_MODE PadMode; + + if (IsPchLp ()) { + GpioPad =3D GPIO_CNL_LP_GPP_H1; + PadMode =3D GpioPadModeNative3; + } else { + GpioPad =3D GPIO_CNL_H_GPP_D5; + PadMode =3D GpioPadModeNative3; + } + + Status =3D GpioSetPadMode (GpioPad, PadMode); + ASSERT_EFI_ERROR (Status); +} + +/** + This function enables CNVi MODEM CLKREQ pin +**/ +VOID +GpioEnableCnviModemClkReqPin ( + VOID + ) +{ + EFI_STATUS Status; + GPIO_PAD GpioPad; + GPIO_PAD_MODE PadMode; + + if (IsPchLp ()) { + GpioPad =3D GPIO_CNL_LP_GPP_H2; + PadMode =3D GpioPadModeNative3; + } else { + GpioPad =3D GPIO_CNL_H_GPP_D6; + PadMode =3D GpioPadModeNative3; + } + + Status =3D GpioSetPadMode (GpioPad, PadMode); + ASSERT_EFI_ERROR (Status); +} + + +/** + This function provides CNVi BT interface select pin + + @retval GpioPad GPIO pad for CNVi BT interface select +**/ +GPIO_PAD +GpioGetCnviBtIfSelectPin ( + VOID + ) +{ + if (IsPchLp ()) { + return GPIO_CNL_LP_VGPIO5; + } else { + return GPIO_CNL_H_VGPIO7; + } +} + +/** + This function provides CNVi BT Charging pin + + @retval GpioPad GPIO pad for CNVi BT Charging select +**/ +GPIO_PAD +GpioGetCnviBtChargingPin ( + VOID + ) +{ + if (IsPchLp ()) { + return GPIO_CNL_LP_VGPIO3; + } else { + return GPIO_CNL_H_VGPIO3; + } +} + +/** + This function provides CNVi A4WP pin + + @param[out] GpioNativePad GPIO native pad for CNVi A4WP +**/ +VOID +GpioGetCnviA4WpPin ( + OUT GPIO_PAD_NATIVE_FUNCTION *GpioNativePad + ) +{ + GpioNativePad->Mode =3D GpioPadModeNative1; + if (IsPchLp ()) { + GpioNativePad->Pad =3D GPIO_CNL_LP_GPP_F23; + } else { + GpioNativePad->Pad =3D GPIO_CNL_H_GPP_J11; + } +} + +/** + This function provides CNVi BT host wake int pin + + @retval GpioPad GPIO pad BT host wake int +**/ +GPIO_PAD +GpioGetCnviBtHostWakeIntPin ( + VOID + ) +{ + if (IsPchLp ()) { + return GPIO_CNL_LP_VGPIO4; + } else { + return GPIO_CNL_H_VGPIO4; + } +} + +// +// CNVi Bluetooth UART pads +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchLpVCnviBtUartGpioPad[PCH_GPIO_C= NVI_UART_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_LP_VGPIO6, // vCNV_BT_UART_TXD + GPIO_CNL_LP_VGPIO7, // vCNV_BT_UART_RXD + GPIO_CNL_LP_VGPIO8, // vCNV_BT_UART_CTS_B + GPIO_CNL_LP_VGPIO9 // vCNV_BT_UART_RTS_B +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchHVCnviBtUartGpioPad[PCH_GPIO_CN= VI_UART_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_H_VGPIO8, // vCNV_BT_UART_TXD + GPIO_CNL_H_VGPIO9, // vCNV_BT_UART_RXD + GPIO_CNL_H_VGPIO10,// vCNV_BT_UART_CTS_B + GPIO_CNL_H_VGPIO11 // vCNV_BT_UART_RTS_B +}; + +// +// vUART for Bluetooth +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchLpVUartForCnviBtGpioPad[PCH_GPI= O_CNVI_UART_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_LP_VGPIO18, // vUART0_TXD + GPIO_CNL_LP_VGPIO19, // vUART0_RXD + GPIO_CNL_LP_VGPIO20, // vUART0_CTS_B + GPIO_CNL_LP_VGPIO21 // vUART0_RTS_B +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchHVUartForCnviBtGpioPad[PCH_GPIO= _CNVI_UART_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_H_VGPIO20, // vUART0_TXD + GPIO_CNL_H_VGPIO21, // vUART0_RXD + GPIO_CNL_H_VGPIO22, // vUART0_CTS_B + GPIO_CNL_H_VGPIO23 // vUART0_RTS_B +}; + +/** + This function provides CNVi BT UART pins + + @param[in] ConnectionType CNVi BT UART connection type + @param[out] VCnviBtUartPad Table with vCNV_BT_UARTx pads + @param[out] VCnviBtUartPadMode vCNV_BT_UARTx pad mode + @param[out] VUartForCnviBtPad Table with vUART0 pads + @param[out] VUartForCnviBtPadMode vUART0 pad mode +**/ +VOID +GpioGetCnviBtUartPins ( + IN VGPIO_CNVI_BT_UART_CONNECTION_TYPE ConnectionType, + OUT GPIO_PAD **VCnviBtUartPad, + OUT GPIO_PAD_MODE *VCnviBtUartPadMode, + OUT GPIO_PAD **VUartForCnviBtPad, + OUT GPIO_PAD_MODE *VUartForCnviBtPadMode + ) +{ + if (IsPchLp ()) { + *VCnviBtUartPad =3D mPchLpVCnviBtUartGpioPad; + *VUartForCnviBtPad =3D mPchLpVUartForCnviBtGpioPad; + } else { + *VCnviBtUartPad =3D mPchHVCnviBtUartGpioPad; + *VUartForCnviBtPad =3D mPchHVUartForCnviBtGpioPad; + } + + switch (ConnectionType) { + case GpioCnviBtUartToSerialIoUart0: + *VCnviBtUartPadMode =3D GpioPadModeNative1; + *VUartForCnviBtPadMode =3D GpioPadModeNative1; + break; + case GpioCnviBtUartToIshUart0: + *VCnviBtUartPadMode =3D GpioPadModeNative2; + *VUartForCnviBtPadMode =3D GpioPadModeNative1; + break; + case GpioCnviBtUartNotConnected: + case GpioCnviBtUartToExternalPads: + *VCnviBtUartPadMode =3D GpioPadModeGpio; + *VUartForCnviBtPadMode =3D GpioPadModeGpio; + break; + default: + ASSERT (FALSE); + return; + } +} + +// +// CNVi Bluetooth UART external pads +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpCnviBtUartExt= ernalPads[PCH_GPIO_CNVI_UART_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_GPP_C8, GpioPadModeNative2}, // CNV_BT_UART_0_RXD + {GPIO_CNL_LP_GPP_C9, GpioPadModeNative2}, // CNV_BT_UART_0_TXD + {GPIO_CNL_LP_GPP_C10, GpioPadModeNative2}, // CNV_BT_UART_0_RTS + {GPIO_CNL_LP_GPP_C11, GpioPadModeNative2} // CNV_BT_UART_0_CTS +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHCnviBtUartExte= rnalPads[PCH_GPIO_CNVI_UART_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_GPP_C8, GpioPadModeNative2}, // CNV_BT_UART_0_RXD + {GPIO_CNL_H_GPP_C9, GpioPadModeNative2}, // CNV_BT_UART_0_TXD + {GPIO_CNL_H_GPP_C10, GpioPadModeNative2}, // CNV_BT_UART_0_RTS + {GPIO_CNL_H_GPP_C11, GpioPadModeNative2} // CNV_BT_UART_0_CTS +}; + +/** + This function provides CNVi BT UART external pads + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnviBtUartExternalPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpCnviBtUartExternalPads; + } else { + *NativePinsTable =3D mPchHCnviBtUartExternalPads; + } +} + +// +// CNVi Bluetooth I2S pads +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchLpVCnviBtI2sGpioPad[PCH_GPIO_CN= VI_SSP_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_LP_VGPIO30, // vCNV_BT_I2S_BCLK + GPIO_CNL_LP_VGPIO31, // vCNV_BT_I2S_WS_SYNC + GPIO_CNL_LP_VGPIO32, // vCNV_BT_I2S_SDO + GPIO_CNL_LP_VGPIO33 // vCNV_BT_I2S_SDI +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchHVCnviBtI2sGpioPad[PCH_GPIO_CNV= I_SSP_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_H_VGPIO32, // vCNV_BT_I2S_BCLK + GPIO_CNL_H_VGPIO33, // vCNV_BT_I2S_WS_SYNC + GPIO_CNL_H_VGPIO34, // vCNV_BT_I2S_SDO + GPIO_CNL_H_VGPIO35 // vCNV_BT_I2S_SDI +}; + +// +// vSSP for Bluetooth +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchLpVSspForCnviBtGpioPad[PCH_GPIO= _CNVI_SSP_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_LP_VGPIO34, // vSSP2_SCLK + GPIO_CNL_LP_VGPIO35, // vSSP2_SFRM + GPIO_CNL_LP_VGPIO36, // vSSP2_TXD + GPIO_CNL_LP_VGPIO37 // vSSP2_RXD +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchHVSspForCnviBtGpioPad[PCH_GPIO_= CNVI_SSP_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_H_VGPIO36, // vSSP2_SCLK + GPIO_CNL_H_VGPIO37, // vSSP2_SFRM + GPIO_CNL_H_VGPIO38, // vSSP2_TXD + GPIO_CNL_H_VGPIO39 // vSSP2_RXD +}; + +/** + This function provides CNVi BT I2S pins + + @param[in] ConnectionType CNVi BT I2S connection type + @param[out] VCnviBtI2sPad Table with vCNV_BT_I2Sx pads + @param[out] VCnviBtI2sPadMode vCNV_BT_I2Sx pad mode + @param[out] VSspForCnviBtPad Table with vSSP2 pads + @param[out] VSspForCnviBtPadMode vSSP2 pad mode +**/ +VOID +GpioGetCnviBtI2sPins ( + IN VGPIO_CNVI_BT_I2S_CONNECTION_TYPE ConnectionType, + OUT GPIO_PAD **VCnviBtI2sPad, + OUT GPIO_PAD_MODE *VCnviBtI2sPadMode, + OUT GPIO_PAD **VSspForCnviBtPad, + OUT GPIO_PAD_MODE *VSspForCnviBtPadMode + ) +{ + if (IsPchLp ()) { + *VCnviBtI2sPad =3D mPchLpVCnviBtI2sGpioPad; + *VSspForCnviBtPad =3D mPchLpVSspForCnviBtGpioPad; + } else { + *VCnviBtI2sPad =3D mPchHVCnviBtI2sGpioPad; + *VSspForCnviBtPad =3D mPchHVSspForCnviBtGpioPad; + } + + switch (ConnectionType) { + case GpioCnviBtI2sToSsp0: + *VCnviBtI2sPadMode =3D GpioPadModeNative1; + *VSspForCnviBtPadMode =3D GpioPadModeNative1; + break; + case GpioCnviBtI2sToSsp1: + *VCnviBtI2sPadMode =3D GpioPadModeNative2; + *VSspForCnviBtPadMode =3D GpioPadModeNative1; + break; + case GpioCnviBtI2sToSsp2: + *VCnviBtI2sPadMode =3D GpioPadModeNative3; + *VSspForCnviBtPadMode =3D GpioPadModeNative1; + break; + case GpioCnviBtI2sNotConnected: + case GpioCnviBtI2sToExternalPads: + *VCnviBtI2sPadMode =3D GpioPadModeGpio; + *VSspForCnviBtPadMode =3D GpioPadModeGpio; + break; + default: + ASSERT (FALSE); + return; + } +} + +// +// CNVi Bluetooth I2S external pads +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpCnviBtI2sExte= rnalPads[PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_GPP_H0, GpioPadModeNative2}, // CNV_BT_I2S_WS_SYNC + {GPIO_CNL_LP_GPP_H1, GpioPadModeNative2}, // CNV_BT_I2S_BCLK + {GPIO_CNL_LP_GPP_H2, GpioPadModeNative2}, // CNV_BT_I2S_SDI + {GPIO_CNL_LP_GPP_H3, GpioPadModeNative2} // CNV_BT_I2S_SDO +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHCnviBtI2sExter= nalPads[PCH_GPIO_CNVI_SSP_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_GPP_D8, GpioPadModeNative2}, // CNV_BT_I2S_WS_SYNC + {GPIO_CNL_H_GPP_D5, GpioPadModeNative2}, // CNV_BT_I2S_BCLK + {GPIO_CNL_H_GPP_D6, GpioPadModeNative2}, // CNV_BT_I2S_SDI + {GPIO_CNL_H_GPP_D7, GpioPadModeNative2} // CNV_BT_I2S_SDO +}; + +/** + This function provides CNVi BT I2S external pads + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnviBtI2sExternalPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpCnviBtI2sExternalPads; + } else { + *NativePinsTable =3D mPchHCnviBtI2sExternalPads; + } +} + +// +// CNVi MFUART1 pads +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchLpVCnviMfUart1GpioPad[PCH_GPIO_= CNVI_UART_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_LP_VGPIO10, // vCNV_MFUART1_TXD + GPIO_CNL_LP_VGPIO11, // vCNV_MFUART1_RXD + GPIO_CNL_LP_VGPIO12, // vCNV_MFUART1_CTS_B + GPIO_CNL_LP_VGPIO13 // vCNV_MFUART1_RTS_B +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchHVCnviMfUart1GpioPad[PCH_GPIO_C= NVI_UART_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_H_VGPIO12, // vCNV_MFUART1_TXD + GPIO_CNL_H_VGPIO13, // vCNV_MFUART1_RXD + GPIO_CNL_H_VGPIO14, // vCNV_MFUART1_CTS_B + GPIO_CNL_H_VGPIO15 // vCNV_MFUART1_RTS_B +}; + +// +// vUART for MFUART1 +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchLpVUartForCnviMfUart1GpioPad[PC= H_GPIO_CNVI_UART_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_LP_VGPIO22, // vISH_UART0_TXD + GPIO_CNL_LP_VGPIO23, // vISH_UART0_RXD + GPIO_CNL_LP_VGPIO24, // vISH_UART0_CTS_B + GPIO_CNL_LP_VGPIO25 // vISH_UART0_RTS_B +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD mPchHVUartForCnviMfUart1GpioPad[PCH= _GPIO_CNVI_UART_NUMBER_OF_PINS] =3D +{ + GPIO_CNL_H_VGPIO24, // vISH_UART0_TXD + GPIO_CNL_H_VGPIO25, // vISH_UART0_RXD + GPIO_CNL_H_VGPIO26, // vISH_UART0_CTS_B + GPIO_CNL_H_VGPIO27 // vISH_UART0_RTS_B +}; + +/** + This function provides CNVi MFUART1 pins + + @param[in] ConnectionType CNVi MFUART1 connection type + @param[out] VCnviBtI2sPad Table with vCNV_MFUART1x pads + @param[out] VCnviBtI2sPadMode vCNV_MFUART1x pad mode + @param[out] VSspForCnviBtPad Table with vISH_UART0 pads + @param[out] VSspForCnviBtPadMode vISH_UART0 pad mode +**/ +VOID +GpioGetCnviMfUart1Pins ( + IN VGPIO_CNVI_MF_UART1_CONNECTION_TYPE ConnectionType, + OUT GPIO_PAD **VCnviMfUart1Pad, + OUT GPIO_PAD_MODE *VCnviMfUart1PadMode, + OUT GPIO_PAD **VUartForCnviMfUart1Pad, + OUT GPIO_PAD_MODE *VUartForCnviMfUart1PadMode + ) +{ + if (IsPchLp ()) { + *VCnviMfUart1Pad =3D mPchLpVCnviMfUart1GpioPad; + *VUartForCnviMfUart1Pad =3D mPchLpVUartForCnviMfUart1GpioPad; + } else { + *VCnviMfUart1Pad =3D mPchHVCnviMfUart1GpioPad; + *VUartForCnviMfUart1Pad =3D mPchHVUartForCnviMfUart1GpioPad; + } + + switch (ConnectionType) { + case GpioCnviMfUart1ToSerialIoUart2: + *VCnviMfUart1PadMode =3D GpioPadModeNative2; + *VUartForCnviMfUart1PadMode =3D GpioPadModeNative1; + break; + case GpioCnviMfUart1ToIshUart0: + *VCnviMfUart1PadMode =3D GpioPadModeNative1; + *VUartForCnviMfUart1PadMode =3D GpioPadModeNative1; + break; + case GpioCnviMfUart1NotConnected: + case GpioCnviMfUart1ToExternalPads: + *VCnviMfUart1PadMode =3D GpioPadModeGpio; + *VUartForCnviMfUart1PadMode =3D GpioPadModeGpio; + break; + default: + ASSERT (FALSE); + return; + } +} + +// +// CNVi MFUART1 external pads +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpCnviMfUart1Ex= ternalPads[PCH_GPIO_CNVI_UART_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_GPP_C12, GpioPadModeNative3}, // CNV_MFUART1_RXD + {GPIO_CNL_LP_GPP_C13, GpioPadModeNative3}, // CNV_MFUART1_TXD + {GPIO_CNL_LP_GPP_C14, GpioPadModeNative3}, // CNV_MFUART1_RTS + {GPIO_CNL_LP_GPP_C15, GpioPadModeNative3} // CNV_MFUART1_CTS +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHCnviMfUart1Ext= ernalPads[PCH_GPIO_CNVI_UART_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_GPP_C12, GpioPadModeNative3}, // CNV_MFUART1_RXD + {GPIO_CNL_H_GPP_C13, GpioPadModeNative3}, // CNV_MFUART1_TXD + {GPIO_CNL_H_GPP_C14, GpioPadModeNative3}, // CNV_MFUART1_RTS + {GPIO_CNL_H_GPP_C15, GpioPadModeNative3} // CNV_MFUART1_CTS +}; + +/** + This function provides CNVi MFUART1 external pads + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnviMfUart1ExternalPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpCnviMfUart1ExternalPads; + } else { + *NativePinsTable =3D mPchHCnviMfUart1ExternalPads; + } +} + +/** + This function provides CNVi Bluetooth Enable pad + + @retval GpioPad CNVi Bluetooth Enable pad +**/ +GPIO_PAD +GpioGetCnviBtEnablePin ( + VOID + ) +{ + if (IsPchLp ()) { + return GPIO_CNL_LP_VGPIO0; + } else { + return GPIO_CNL_H_VGPIO0; + } +} + +// +// CNVi BRI (Bluetooth Radio Interface) and RGI (Radio Generic Interface) = buses from Pulsar to CRF (Companion RF) +// +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpCnviBriRgiGpi= oPad[PCH_GPIO_CNVI_BRI_RGI_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_GPP_F4, GpioPadModeNative1}, // CNV_BRI_DT + {GPIO_CNL_LP_GPP_F5, GpioPadModeNative1}, // CNV_BRI_RSP + {GPIO_CNL_LP_GPP_F6, GpioPadModeNative1}, // CNV_RGI_DT + {GPIO_CNL_LP_GPP_F7, GpioPadModeNative1} // CNV_RGI_RSP +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHCnviBriRgiGpio= Pad[PCH_GPIO_CNVI_BRI_RGI_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_GPP_J4, GpioPadModeNative1}, // CNV_BRI_DT + {GPIO_CNL_H_GPP_J5, GpioPadModeNative1}, // CNV_BRI_RSP + {GPIO_CNL_H_GPP_J6, GpioPadModeNative1}, // CNV_RGI_DT + {GPIO_CNL_H_GPP_J7, GpioPadModeNative1} // CNV_RGI_RSP +}; + +/** + This function provides CNVi BRI RGI GPIO pads + + @param[out] NativePinsTable Table with pins +**/ +VOID +GpioGetCnvBriRgiPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpCnviBriRgiGpioPad; + } else { + *NativePinsTable =3D mPchHCnviBriRgiGpioPad; + } +} + + +/** + This function sets CNVi WiFi mode + + @param[in] Value CNVi WiFi Mode value + GpioCnviWiFiAuto: WiFi is automatically = enabled/disabled by WiFi core + GpioCnviWiFiEnabled: WiFi is enabled reg= ardless of WiFi core decision + @retval Status +**/ +EFI_STATUS +GpioSetCnviWifiMode ( + IN VGPIO_CNVI_WIFI_MODE WiFiMode + ) +{ + EFI_STATUS Status; + GPIO_PAD CnviWifiModePad; + GPIO_CONFIG PadConfig; + + ZeroMem (&PadConfig, sizeof (PadConfig)); + + PadConfig.PadMode =3D GpioPadModeGpio; + PadConfig.Direction =3D GpioDirOut; + if (WiFiMode =3D=3D GpioCnviWiFiEnabled) { + PadConfig.OutputState =3D GpioOutHigh; + } else { + PadConfig.OutputState =3D GpioOutLow; + } + + if (IsPchLp ()) { + CnviWifiModePad =3D GPIO_CNL_LP_VGPIO2; + } else { + CnviWifiModePad =3D GPIO_CNL_H_VGPIO2; + } + + Status =3D GpioSetPadConfig (CnviWifiModePad, &PadConfig); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchLpImguClkOutGpi= oPad[SA_GPIO_IMGUCLK_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_LP_GPP_D4, GpioPadModeNative1}, // IMGCLKOUT_0 + {GPIO_CNL_LP_GPP_H20, GpioPadModeNative1}, // IMGCLKOUT_1 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_PAD_NATIVE_FUNCTION mPchHImguClkOutGpio= Pad[SA_GPIO_IMGUCLK_NUMBER_OF_PINS] =3D +{ + {GPIO_CNL_H_GPP_K22, GpioPadModeNative1}, // IMGCLKOUT_0 + {GPIO_CNL_H_GPP_K23, GpioPadModeNative1}, // IMGCLKOUT_1 +}; + +/** + This function provides IMGCLKOUT pins + + @param[out] NativePinsTable Table with pins + @param[out] NoOfNativePins Number of pins +**/ +VOID +GpioGetImgClkOutPins ( + OUT GPIO_PAD_NATIVE_FUNCTION **NativePinsTable, + OUT UINT32 *NoOfNativePins + ) +{ + if (IsPchLp ()) { + *NativePinsTable =3D mPchLpImguClkOutGpioPad; + *NoOfNativePins =3D ARRAY_SIZE (mPchLpImguClkOutGpioPad); + } else { + *NativePinsTable =3D mPchHImguClkOutGpioPad; + *NoOfNativePins =3D ARRAY_SIZE (mPchHImguClkOutGpioPad); + } +} + +/** + This function provides PWRBTN pin + + @retval GpioPad PWRTBTN pin +**/ +GPIO_PAD +GpioGetPwrBtnPin ( + VOID + ) +{ + if (IsPchLp ()) { + return GPIO_CNL_LP_GPD3; + } else { + return GPIO_CNL_H_GPD3; + } +} + +/** + This function provides LPC pin + + @retval GpioPad LPC pin +**/ +GPIO_PAD +GpioGetLpcPin ( + VOID + ) +{ + if (PchGetLpcDid () =3D=3D V_CNL_PCH_H_LPC_CFG_DEVICE_ID_A305_SKU) { + return GPIO_CNL_H_GPP_A8; + } else { + return 0; + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmGpioPrivateLib/GpioPrivateLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/= Library/Private/PeiDxeSmmGpioPrivateLib/GpioPrivateLib.c new file mode 100644 index 0000000000..2cf11c6da2 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioP= rivateLib/GpioPrivateLib.c @@ -0,0 +1,752 @@ +/** @file + This file contains GPIO routines for RC usage + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "GpioNativePrivateLibInternal.h" + +/** + This procedure is used to check if GpioPad is valid for certain chipset + + @param[in] GpioPad GPIO pad + + @retval TRUE This pin is valid on this chipset + FALSE Incorrect pin +**/ +BOOLEAN +GpioIsCorrectPadForThisChipset ( + IN GPIO_PAD GpioPad + ) +{ + return ((GPIO_GET_CHIPSET_ID (GpioPad) =3D=3D GpioGetThisChipsetId ()) && + (GpioGetGroupIndexFromGpioPad (GpioPad) < GpioGetNumberOfGroups (= ))); +} + +/** + This procedure will get value of selected gpio register + + @param[in] Group GPIO group number + @param[in] Offset GPIO register offset + @param[out] RegVal Value of gpio register + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetReg ( + IN GPIO_GROUP Group, + IN UINT32 Offset, + OUT UINT32 *RegVal + ) +{ + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 GroupIndex; + + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN) GroupIndex >=3D GpioGroupInfoLength) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + *RegVal =3D MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Commu= nity, Offset)); + + return EFI_SUCCESS; +} + +/** + This procedure will set value of selected gpio register + + @param[in] Group GPIO group number + @param[in] Offset GPIO register offset + @param[in] RegVal Value of gpio register + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetReg ( + IN GPIO_GROUP Group, + IN UINT32 Offset, + IN UINT32 RegVal + ) +{ + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 GroupIndex; + + GroupIndex =3D GpioGetGroupIndexFromGroup (Group); + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + // + // Check if group argument exceeds GPIO GROUP INFO array + // + if ((UINTN) GroupIndex >=3D GpioGroupInfoLength) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + MmioWrite32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, Offse= t), RegVal); + + return EFI_SUCCESS; +} + +/** + This procedure is used by PchSmiDispatcher and will return information + needed to register GPI SMI. + + @param[in] Index GPI SMI number + @param[out] GpioPin GPIO pin + @param[out] GpiSmiBitOffset GPI SMI bit position within GpiSmi R= egisters + @param[out] GpiHostSwOwnRegAddress Address of HOSTSW_OWN register + @param[out] GpiSmiStsRegAddress Address of GPI SMI status register + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioGetPadAndSmiRegs ( + IN UINT32 Index, + OUT GPIO_PAD *GpioPin, + OUT UINT8 *GpiSmiBitOffset, + OUT UINT32 *GpiHostSwOwnRegAddress, + OUT UINT32 *GpiSmiStsRegAddress + ) +{ + UINT32 GroupIndex; + UINT32 PadNumber; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + GPIO_GROUP GpioGroup; + UINT32 GpioGroupInfoLength; + UINT32 SmiStsRegOffset; + UINT32 HostSwOwnRegOffset; + GPIO_PAD_OWN PadOwnVal; + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + PadNumber =3D 0; + GroupIndex =3D 0; + for (GroupIndex =3D 0; GroupIndex < GpioGroupInfoLength; GroupIndex++) { + PadNumber =3D Index; + if (PadNumber < GpioGroupInfo[GroupIndex].PadPerGroup) { + // + // Found group and pad number + // + break; + } + Index =3D Index - GpioGroupInfo[GroupIndex].PadPerGroup; + } + + // + // Check if legal pad number + // + if (PadNumber >=3D GpioGroupInfo[GroupIndex].PadPerGroup){ + return EFI_INVALID_PARAMETER; + } + + // + // Check if selected group has GPI SMI Enable and Status registers + // + if (GpioGroupInfo[GroupIndex].SmiEnOffset =3D=3D NO_REGISTER_FOR_PROPERT= Y) { + return EFI_INVALID_PARAMETER; + } + + GpioGroup =3D GpioGetGroupFromGroupIndex (GroupIndex); + *GpioPin =3D GpioGetGpioPadFromGroupAndPadNumber (GpioGroup, PadNumber); + + DEBUG_CODE_BEGIN (); + // + // Check if selected GPIO Pad is not owned by CSME/ISH/IE + // + GpioGetPadOwnership (*GpioPin, &PadOwnVal); + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: %a not owned by host!\n", GpioName (= *GpioPin))); + return EFI_INVALID_PARAMETER; + } + DEBUG_CODE_END (); + + *GpiSmiBitOffset =3D (UINT8)(PadNumber % 32); + + HostSwOwnRegOffset =3D GpioGroupInfo[GroupIndex].HostOwnOffset + (PadNum= ber / 32) * 0x4; + *GpiHostSwOwnRegAddress =3D PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].C= ommunity, HostSwOwnRegOffset); + + SmiStsRegOffset =3D GpioGroupInfo[GroupIndex].SmiStsOffset + (PadNumber = / 32) * 0x4; + *GpiSmiStsRegAddress =3D PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Comm= unity, SmiStsRegOffset); + + return EFI_SUCCESS; +} + +/** + This procedure will set GPIO Driver IRQ number + + @param[in] Irq Irq number + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid IRQ number +**/ +EFI_STATUS +GpioSetIrq ( + IN UINT8 Irq + ) +{ + UINT32 Data32And; + UINT32 Data32Or; + PCH_SBI_PID *GpioComSbiIds; + UINT32 NoOfGpioComs; + UINT32 GpioComIndex; + + Data32And =3D (UINT32)~(B_GPIO_PCR_MISCCFG_IRQ_ROUTE); + Data32Or =3D (UINT32)Irq << N_GPIO_PCR_MISCCFG_IRQ_ROUTE; + + NoOfGpioComs =3D GpioGetComSbiPortIds (&GpioComSbiIds); + + // + // Program MISCCFG register for each community + // + for (GpioComIndex =3D 0; GpioComIndex < NoOfGpioComs; GpioComIndex++) { + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioComSbiIds[GpioComIndex], R_GPIO_PCR_MISCCFG), + Data32And, + Data32Or + ); + } + + return EFI_SUCCESS; +} + +/** + This procedure will return Port ID of GPIO Community from GpioPad + + @param[in] GpioPad GpioPad + + @retval GpioCommunityPortId Port ID of GPIO Community +**/ +UINT8 +GpioGetGpioCommunityPortIdFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 GroupIndex; + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + return GpioGroupInfo[GroupIndex].Community; +} + +/** + This procedure will return PadCfg address from GpioPad + + @param[in] GpioPad GpioPad + + @retval GpioPadCfgAddress PadCfg Address of GpioPad +**/ +UINT32 +GpioGetGpioPadCfgAddressFromGpioPad ( + IN GPIO_PAD GpioPad + ) +{ + UINT32 PadCfgRegAddress; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 GroupIndex; + UINT32 PadNumber; + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Create Pad Configuration register offset + // + PadCfgRegAddress =3D GpioGroupInfo[GroupIndex].PadCfgOffset + S_GPIO_PCR= _PADCFG * PadNumber; + + return PadCfgRegAddress; +} + + +/** + This procedure will check if GpioPad is owned by host. + + @param[in] GpioPad GPIO pad + + @retval TRUE GPIO pad is owned by host + @retval FALSE GPIO pad is not owned by host and should not be= used with GPIO lib API +**/ +BOOLEAN +GpioIsPadHostOwned ( + IN GPIO_PAD GpioPad + ) +{ + GPIO_PAD_OWN PadOwnVal; + + // + // Check if selected GPIO Pad is not owned by CSME/ISH + // If GPIO is not owned by Host all access to PadCfg will be dropped + // + GpioGetPadOwnership (GpioPad, &PadOwnVal); + if (PadOwnVal !=3D GpioPadOwnHost) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: %a is not owned by host!\n", GpioNam= e (GpioPad))); + return FALSE; + } + + return TRUE; +} + +/** + This procedure will check if GpioPad argument is valid. + Function will check below conditions: + - GpioPad represents a pad for current PCH + - GpioPad belongs to valid GpioGroup + - GPIO PadNumber is not greater than number of pads for this group + + @param[in] GpioPad GPIO pad + + @retval TRUE GPIO pad is valid and can be used with GPIO lib= API + @retval FALSE GPIO pad is invalid and cannot be used with GPI= O lib API +**/ +BOOLEAN +GpioIsPadValid ( + IN GPIO_PAD GpioPad + ) +{ + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 PadNumber; + + if (!GpioIsCorrectPadForThisChipset (GpioPad)) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Incorrect GpioPad (0x%08x) used on t= his chipset!\n", GpioPad)); + goto Error; + } + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Check if legal pin number + // + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + if (PadNumber >=3D GpioGroupInfo[GpioGetGroupIndexFromGpioPad (GpioPad)]= .PadPerGroup) { + DEBUG ((DEBUG_ERROR, "GPIO ERROR: Pin number (%d) exceeds possible ran= ge for this group\n", PadNumber)); + goto Error; + } + + return TRUE; +Error: + ASSERT (FALSE); + return FALSE; +} + +/** + This procedure will read GPIO Pad Configuration register + + @param[in] GpioPad GPIO pad + @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1 + + @retval PadCfgRegValue PADCFG_DWx value +**/ +UINT32 +GpioReadPadCfgReg ( + IN GPIO_PAD GpioPad, + IN UINT8 DwReg + ) +{ + UINT32 PadCfgReg; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 GroupIndex; + UINT32 PadNumber; + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Create Pad Configuration register offset + // + PadCfgReg =3D GpioGroupInfo[GroupIndex].PadCfgOffset + S_GPIO_PCR_PADCFG= * PadNumber + 0x4 * DwReg; + + return MmioRead32 (PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community,= PadCfgReg)); +} + +/** + This procedure will write or read GPIO Pad Configuration register + + @param[in] GpioPad GPIO pad + @param[in] DwReg Choose PADCFG register: 0:DW0, 1:DW1 + @param[in] PadCfgAndMask Mask to be AND'ed with PADCFG reg value + @param[in] PadCfgOrMask Mask to be OR'ed with PADCFG reg value + + @retval none +**/ +VOID +GpioWritePadCfgReg ( + IN GPIO_PAD GpioPad, + IN UINT8 DwReg, + IN UINT32 PadCfgAndMask, + IN UINT32 PadCfgOrMask + ) +{ + UINT32 PadCfgReg; + CONST GPIO_GROUP_INFO *GpioGroupInfo; + UINT32 GpioGroupInfoLength; + UINT32 GroupIndex; + UINT32 PadNumber; + UINT32 PadCfgLock; + UINT32 PadCfgLockTx; + + PadCfgLock =3D 0; + PadCfgLockTx =3D 0; + + // + // Check if Pad Configuration (except output state) is to be changed. + // If AND and OR masks will indicate that configuration fields (other th= an output control) + // are to be modified it means that there is a need to perform an unlock= (if set) + // + if ((~PadCfgAndMask | PadCfgOrMask) & (UINT32)~B_GPIO_PCR_TX_STATE) { + GpioGetPadCfgLock (GpioPad, &PadCfgLock); + if (PadCfgLock) { + GpioUnlockPadCfg (GpioPad); + } + } + + // + // Check if Pad Output state is to be changed + // If AND and OR masks will indicate that output control + // is to be modified it means that there is a need to perform an unlock = (if set) + // + if ((~PadCfgAndMask | PadCfgOrMask) & B_GPIO_PCR_TX_STATE) { + GpioGetPadCfgLockTx (GpioPad, &PadCfgLockTx); + if (PadCfgLockTx) { + GpioUnlockPadCfgTx (GpioPad); + } + } + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + + GpioGroupInfo =3D GpioGetGroupInfoTable (&GpioGroupInfoLength); + + // + // Create Pad Configuration register offset + // + PadCfgReg =3D GpioGroupInfo[GroupIndex].PadCfgOffset + S_GPIO_PCR_PADCFG= * PadNumber + 0x4 * DwReg; + + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioGroupInfo[GroupIndex].Community, PadCfgReg), + PadCfgAndMask, + PadCfgOrMask + ); + + if (PadCfgLock) { + GpioLockPadCfg (GpioPad); + } + if (PadCfgLockTx) { + GpioLockPadCfgTx (GpioPad); + } +} + +/** + This procedure will set GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid group or pad number +**/ +EFI_STATUS +GpioSetPadMode ( + IN GPIO_PAD GpioPad, + IN GPIO_PAD_MODE PadModeValue + ) +{ + UINT32 PadCfgOrMask; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + if (PadModeValue !=3D (GPIO_PAD_MODE)GpioHardwareDefault) { + + PadCfgOrMask =3D (((PadModeValue & B_GPIO_PAD_MODE_MASK) >> (N_GPIO_PA= D_MODE_BIT_POS + 1)) << N_GPIO_PCR_PAD_MODE); + + GpioWritePadCfgReg ( + GpioPad, + 0, + (UINT32)~B_GPIO_PCR_PAD_MODE, + PadCfgOrMask + ); + } + + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO mode + + @param[in] GpioPad GPIO pad + @param[out] PadModeValue GPIO pad mode value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad +**/ +EFI_STATUS +GpioGetPadMode ( + IN GPIO_PAD GpioPad, + OUT GPIO_PAD_MODE *PadModeValue + ) +{ + UINT32 PadCfgRegValue; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + PadCfgRegValue =3D GpioReadPadCfgReg (GpioPad, 0); + + *PadModeValue =3D (GPIO_PAD_MODE)(((PadCfgRegValue & B_GPIO_PCR_PAD_MODE= ) >> (N_GPIO_PCR_PAD_MODE - (N_GPIO_PAD_MODE_BIT_POS + 1))) | (0x1 << N_GPI= O_PAD_MODE_BIT_POS)); + + return EFI_SUCCESS; +} + +/** + The function performs GPIO Power Management programming. +**/ +VOID +GpioConfigurePm ( + VOID + ) +{ + UINT32 Data32Or; + UINT32 Data32And; + PCH_SBI_PID *GpioComSbiIds; + UINT32 NoOfGpioComs; + UINT32 GpioComIndex; + + Data32And =3D (UINT32)~0, + // + // Enable MISCCFG.GPSIDEDPCGEn, MISCCFG.GPRCOMPCDLCGEn, MISCCFG.GPRTCDLC= GEn, + // MISCCFG.GPDLCGEn and MISCCFG.GPDPCGEn for GPIO communities + // + Data32Or =3D (B_GPIO_PCR_MISCCFG_GPSIDEDPCGEN | + B_GPIO_PCR_MISCCFG_GPRCOMPCDLCGEN | + B_GPIO_PCR_MISCCFG_GPRTCDLCGEN | + B_GPIO_PCR_MISCCFG_GPDLCGEN | + B_GPIO_PCR_MISCCFG_GPDPCGEN); + + NoOfGpioComs =3D GpioGetComSbiPortIds (&GpioComSbiIds); + + // + // Configure Clock Gating in each community + // + for (GpioComIndex =3D 0; GpioComIndex < NoOfGpioComs; GpioComIndex++) { + MmioAndThenOr32 ( + PCH_PCR_ADDRESS (GpioComSbiIds[GpioComIndex], R_GPIO_PCR_MISCCFG), + Data32And, + Data32Or + ); + } +} + +/** + This procedure is used to unlock all GPIO pads. + This function can only be called when platform is still in HOSTIA_BOOT_S= AI. +**/ +VOID +GpioUnlockAllPads ( + VOID + ) +{ + UINT32 DwNum; + UINT32 GroupIndex; + UINT32 NumberOfGroups; + GPIO_GROUP Group; + UINT32 LockValue; + EFI_STATUS Status; + + NumberOfGroups =3D GpioGetNumberOfGroups (); + + for (GroupIndex =3D 0; GroupIndex < NumberOfGroups; GroupIndex++) { + Group =3D GpioGetGroupFromGroupIndex (GroupIndex); + for (DwNum =3D 0; DwNum <=3D GPIO_GET_DW_NUM (GpioGetPadPerGroup (Grou= p)); DwNum++) { + + GpioGetPadCfgLockForGroupDw (Group, DwNum, &LockValue); + + if (LockValue) { + Status =3D GpioUnlockPadCfgForGroupDw (Group, DwNum, ~0u); + ASSERT_EFI_ERROR (Status); + } + + GpioGetPadCfgLockTxForGroupDw (Group, DwNum, &LockValue); + + if (LockValue) { + Status =3D GpioUnlockPadCfgTxForGroupDw (Group, DwNum, ~0u); + ASSERT_EFI_ERROR (Status); + } + } + } +} + +/** + Generates GPIO name from GpioPad + This function returns pointer to the static buffer + + @param[in] GpioPad GpioPad + + @retval CHAR8* Pointer to the gpio name string +**/ +CHAR8* +GpioName ( + IN GPIO_PAD GpioPad + ) +{ + return GpioGetPadName (GpioPad, GpioGetStaticNameBuffer (), GPIO_NAME_LE= NGTH_MAX); +} + + +// +// For GPIO debounce feature glitch filter clock is used +// which is driven by RTC clock with f =3D 32kHz (T =3D 31.25us) +// +#define GPIO_DEB_CLK_PERIOD_IN_NS 31250 + +/** + This procedure enables debounce feature on a selected pad configured in = input mode + Debounce time can be specified in microseconds. GPIO HW supports only ce= rtain values + according to below formula: + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock period). + RTC clock with f =3D 32 KHz is used for glitch filter. + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us). + Supported DebounceTime values are following: + DebounceTime =3D 0 -> Debounce feature disabled + DebounceTime > 0 && < 250us -> Not supported + DebounceTime =3D 250us - 1024000us -> Supported range (DebounceTime =3D= 250us * 2^n) + For values not supported by GPIO HW, function will round down + to closest supported + + @param[in] GpioPad GPIO pad + @param[in, out] DebounceTime Debounce Time in microseconds + If Debounce Time =3D 0, Debouncer featur= e will be disabled + Function will set DebounceTime argument = to rounded supported value + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_INVALID_PARAMETER Invalid GpioPad or unsupported DebounceD= uration value + @retval EFI_UNSUPPORTED GpioPad is not owned by host +**/ +EFI_STATUS +GpioSetDebounceTimer ( + IN GPIO_PAD GpioPad, + IN OUT UINT32 *DebounceTime + ) +{ + UINT32 DebounceEnable; + UINT32 DebounceValue; + UINT32 InRangeDebounceTime; + UINT32 SupportedDebounceTime; + UINT32 Temp; + BOOLEAN SupportedValue; + + if (!GpioIsPadValid (GpioPad)) { + return EFI_INVALID_PARAMETER; + } + + if (!GpioIsPadHostOwned (GpioPad)) { + return EFI_UNSUPPORTED; + } + + if (*DebounceTime > 1024000) { + InRangeDebounceTime =3D 1024000; + SupportedValue =3D FALSE; + } else if ((*DebounceTime < 250) && (*DebounceTime > 0)) { + InRangeDebounceTime =3D 0; + SupportedValue =3D FALSE; + } else { + InRangeDebounceTime =3D *DebounceTime; + SupportedValue =3D TRUE; + } + + // + // DebounceValue =3D log2 (InRangeDebounceTime * f_deb_clk) + // + DebounceValue =3D 0; + Temp =3D InRangeDebounceTime * 1000 / GPIO_DEB_CLK_PERIOD_IN_NS; + + // + // Check if any rounding occurred + // + if (InRangeDebounceTime !=3D (Temp * GPIO_DEB_CLK_PERIOD_IN_NS / 1000)) { + SupportedValue =3D FALSE; + } + + // + // Check if value is power of 2 + // + if ((Temp !=3D 0) && ((Temp & (Temp - 1)) !=3D 0)) { + SupportedValue =3D FALSE; + } + + // + // DebounceValue =3D log2 (Temp) + // + while (Temp > 1) { + Temp >>=3D 1; + DebounceValue++; + } + + if (DebounceValue > 0) { + DebounceEnable =3D B_GPIO_PCR_DEBEN; + SupportedDebounceTime =3D (1 << DebounceValue) * GPIO_DEB_CLK_PERIOD_I= N_NS / 1000; + } else { + DebounceEnable =3D 0; + SupportedDebounceTime =3D 0; + } + + GpioWritePadCfgReg ( + GpioPad, + 2, + (UINT32)~(B_GPIO_PCR_DEBOUNCE | B_GPIO_PCR_DEBEN), + (DebounceValue << N_GPIO_PCR_DEBOUNCE) | DebounceEnable + ); + + if (!SupportedValue) { + DEBUG ((DEBUG_WARN, "GPIO WARNING: %a %dus debounce time rounded down = to %dus\n", + GpioName (GpioPad), + *DebounceTime, + SupportedDebounceTime)); + } + + *DebounceTime =3D SupportedDebounceTime; + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmGpioPrivateLib/GpioPrivateLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/P= ch/Library/Private/PeiDxeSmmGpioPrivateLib/GpioPrivateLibCnl.c new file mode 100644 index 0000000000..a6d260f4ad --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmGpioP= rivateLib/GpioPrivateLibCnl.c @@ -0,0 +1,225 @@ +/** @file + This file contains specific GPIO information + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchLpGpioGroupInfo[] =3D { + {PID_GPIOCOM0, R_CNL_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPP_A_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPP_A_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPP_A_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPP_A_PAD_MAX}, //CNL PCH-LP GPP_A + {PID_GPIOCOM0, R_CNL_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPP_B_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPP_B_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_B_GPI_GPE_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_B_SMI_STS, R_CNL_PCH_LP_GP= IO_PCR_GPP_B_SMI_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_B_NMI_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_B_NMI_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPP_B_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPP_B_PAD_MAX}, //CNL PCH-LP GPP_B + {PID_GPIOCOM4, R_CNL_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPP_C_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPP_C_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_C_GPI_GPE_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_C_SMI_STS, R_CNL_PCH_LP_GP= IO_PCR_GPP_C_SMI_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_C_NMI_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_C_NMI_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPP_C_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPP_C_PAD_MAX}, //CNL PCH-LP GPP_C + {PID_GPIOCOM1, R_CNL_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPP_D_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPP_D_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_D_GPI_GPE_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_D_SMI_STS, R_CNL_PCH_LP_GP= IO_PCR_GPP_D_SMI_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_D_NMI_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_D_NMI_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPP_D_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPP_D_PAD_MAX}, //CNL PCH-LP GPP_D + {PID_GPIOCOM4, R_CNL_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPP_E_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPP_E_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_E_GPI_GPE_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_E_SMI_STS, R_CNL_PCH_LP_GP= IO_PCR_GPP_E_SMI_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_E_NMI_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_E_NMI_EN, R_CNL_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPP_E_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPP_E_PAD_MAX}, //CNL PCH-LP GPP_E + {PID_GPIOCOM1, R_CNL_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPP_F_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPP_F_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPP_F_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPP_F_PAD_MAX}, //CNL PCH-LP GPP_F + {PID_GPIOCOM0, R_CNL_PCH_LP_GPIO_PCR_GPP_G_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPP_G_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPP_G_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPP_G_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_G_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_GPP_G_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPP_G_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPP_G_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPP_G_PAD_MAX}, //CNL PCH-LP GPP_G + {PID_GPIOCOM1, R_CNL_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPP_H_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPP_H_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPP_H_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPP_H_PAD_MAX}, //CNL PCH-LP GPP_H + {PID_GPIOCOM2, R_CNL_PCH_LP_GPIO_PCR_GPD_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_GPD_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_GPD_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_GPD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_GPD_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_GPD_PAD_MAX}, //CNL PCH-LP GPD + {PID_GPIOCOM1, R_CNL_PCH_LP_GPIO_PCR_VGPIO_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_VGPIO_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_VGPIO_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_VGPIO_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_VGPIO_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_VGPIO_0_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_VGPIO_0_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_VGPIO_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_VGPIO_PAD_MAX}, //CNL PCH-LP vGPIO + {PID_GPIOCOM0, R_CNL_PCH_LP_GPIO_PCR_SPI_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_SPI_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_SPI_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_SPI_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_SPI_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_SPI_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_SPI_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_SPI_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_SPI_PAD_MAX}, //CNL PCH-LP SPI + {PID_GPIOCOM3, R_CNL_PCH_LP_GPIO_PCR_AZA_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_AZA_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_AZA_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_AZA_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_AZA_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_AZA_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_AZA_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_AZA_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_AZA_PAD_MAX}, //CNL PCH-LP AZA + {PID_GPIOCOM3, R_CNL_PCH_LP_GPIO_PCR_CPU_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_CPU_HOSTSW_OWN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PRO= PERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_CPU_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_CPU_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_CPU_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_CPU_PAD_MAX}, //CNL PCH-LP CPU + {PID_GPIOCOM4, R_CNL_PCH_LP_GPIO_PCR_JTAG_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_JTAG_HOSTSW_OWN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PRO= PERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_JTAG_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_JTAG_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_JTAG_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_JTAG_PAD_MAX}, //CNL PCH-LP JTAG + {PID_GPIOCOM4, R_CNL_PCH_LP_GPIO_PCR_HVMOS_PAD_OWN, R_CNL_PCH_LP_GPIO_PC= R_HVMOS_HOSTSW_OWN, R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_IS, R_CNL_PCH_LP_GPIO_P= CR_HVMOS_GPI_IE, R_CNL_PCH_LP_GPIO_PCR_HVMOS_GPI_GPE_STS, R_CNL_PCH_LP_GPIO= _PCR_HVMOS_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR= _PROPERTY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_P= ROPERTY, R_CNL_PCH_LP_GPIO_PCR_HVMOS_PADCFGLOCK, R_CNL_PCH_LP_G= PIO_PCR_HVMOS_PADCFGLOCKTX, R_CNL_PCH_LP_GPIO_PCR_HVMOS_PADCFG_OFFSET, CN= L_PCH_LP_GPIO_HVMOS_PAD_MAX} //CNL PCH-LP HVMOS +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_INFO mPchHGpioGroupInfo[] =3D { + {PID_GPIOCOM0, R_CNL_PCH_H_GPIO_PCR_GPP_A_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_A_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_A_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_A_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_A_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_GPP_A_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= A_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_A_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_A_PAD_MAX}, //CNL PCH-H GPP_A + {PID_GPIOCOM0, R_CNL_PCH_H_GPIO_PCR_GPP_B_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_B_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_B_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_B_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_B_GPI_GPE_EN, R_CNL_PCH_H_GPIO_PCR_GPP_B_SMI_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_B_SMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_B_NMI_STS, R_CNL_PCH_H_GPIO_PCR_GPP_B= _NMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_B_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= B_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_B_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_B_PAD_MAX}, //CNL PCH-H GPP_B + {PID_GPIOCOM1, R_CNL_PCH_H_GPIO_PCR_GPP_C_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_C_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_C_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_C_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_C_GPI_GPE_EN, R_CNL_PCH_H_GPIO_PCR_GPP_C_SMI_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_C_SMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_C_NMI_STS, R_CNL_PCH_H_GPIO_PCR_GPP_C= _NMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_C_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= C_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_C_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_C_PAD_MAX}, //CNL PCH-H GPP_C + {PID_GPIOCOM1, R_CNL_PCH_H_GPIO_PCR_GPP_D_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_D_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_D_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_D_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_D_GPI_GPE_EN, R_CNL_PCH_H_GPIO_PCR_GPP_D_SMI_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_D_SMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_D_NMI_STS, R_CNL_PCH_H_GPIO_PCR_GPP_D= _NMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_D_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= D_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_D_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_D_PAD_MAX}, //CNL PCH-H GPP_D + {PID_GPIOCOM3, R_CNL_PCH_H_GPIO_PCR_GPP_E_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_E_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_E_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_E_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_E_GPI_GPE_EN, R_CNL_PCH_H_GPIO_PCR_GPP_E_SMI_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_E_SMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_E_NMI_STS, R_CNL_PCH_H_GPIO_PCR_GPP_E= _NMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_E_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= E_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_E_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_E_PAD_MAX}, //CNL PCH-H GPP_E + {PID_GPIOCOM3, R_CNL_PCH_H_GPIO_PCR_GPP_F_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_F_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_F_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_F_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_F_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_GPP_F_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= F_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_F_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_F_PAD_MAX}, //CNL PCH-H GPP_F + {PID_GPIOCOM1, R_CNL_PCH_H_GPIO_PCR_GPP_G_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_G_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_G_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_G_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_G_GPI_GPE_EN, R_CNL_PCH_H_GPIO_PCR_GPP_G_SMI_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_G_SMI_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_GPP_G_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= G_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_G_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_G_PAD_MAX}, //CNL PCH-H GPP_G + {PID_GPIOCOM3, R_CNL_PCH_H_GPIO_PCR_GPP_H_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_H_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_H_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_H_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_H_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_GPP_H_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= H_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_H_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_H_PAD_MAX}, //CNL PCH-H GPP_H + {PID_GPIOCOM4, R_CNL_PCH_H_GPIO_PCR_GPP_I_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_I_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_I_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_I_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_I_GPI_GPE_EN, R_CNL_PCH_H_GPIO_PCR_GPP_I_SMI_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_I_SMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_I_NMI_STS, R_CNL_PCH_H_GPIO_PCR_GPP_I= _NMI_EN, R_CNL_PCH_H_GPIO_PCR_GPP_I_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= I_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_I_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_I_PAD_MAX}, //CNL PCH-H GPP_I + {PID_GPIOCOM4, R_CNL_PCH_H_GPIO_PCR_GPP_J_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_J_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_J_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_J_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_J_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_GPP_J_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= J_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_J_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_J_PAD_MAX}, //CNL PCH-H GPP_J + {PID_GPIOCOM3, R_CNL_PCH_H_GPIO_PCR_GPP_K_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPP_K_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PP_K_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPP_K_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PP_K_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_GPP_K_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPP_= K_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPP_K_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPP_K_PAD_MAX}, //CNL PCH-H GPP_K + {PID_GPIOCOM2, R_CNL_PCH_H_GPIO_PCR_GPD_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= GPD_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_GPD_GPI_IS, R_CNL_PCH_H_GPIO_PCR_G= PD_GPI_IE, R_CNL_PCH_H_GPIO_PCR_GPD_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_G= PD_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_GPD_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_GPD_= PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_GPD_PADCFG_OFFSET, CNL_PCH_H_GPIO_= GPD_PAD_MAX}, //CNL PCH-H GPD + {PID_GPIOCOM1, R_CNL_PCH_H_GPIO_PCR_VGPIO_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= VGPIO_HOSTSW_OWN, R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_IS, R_CNL_PCH_H_GPIO_PCR_V= GPIO_GPI_IE, R_CNL_PCH_H_GPIO_PCR_VGPIO_GPI_GPE_STS, R_CNL_PCH_H_GPIO_PCR_V= GPIO_GPI_GPE_EN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_VGPIO_0_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_VGPI= O_0_PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_VGPIO_PADCFG_OFFSET, CNL_PCH_H_GPIO_= VGPIO_PAD_MAX}, //CNL PCH-H vGPIO + {PID_GPIOCOM3, R_CNL_PCH_H_GPIO_PCR_SPI_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= SPI_HOSTSW_OWN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_SPI_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_SPI_= PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_SPI_PADCFG_OFFSET, CNL_PCH_H_GPIO_= SPI_PAD_MAX}, //CNL PCH-H SPI + {PID_GPIOCOM1, R_CNL_PCH_H_GPIO_PCR_AZA_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= AZA_HOSTSW_OWN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_AZA_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_AZA_= PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_AZA_PADCFG_OFFSET, CNL_PCH_H_GPIO_= AZA_PAD_MAX}, //CNL PCH-H AZA + {PID_GPIOCOM4, R_CNL_PCH_H_GPIO_PCR_CPU_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= CPU_HOSTSW_OWN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_CPU_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_CPU_= PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_CPU_PADCFG_OFFSET, CNL_PCH_H_GPIO_= CPU_PAD_MAX}, //CNL PCH-H CPU + {PID_GPIOCOM4, R_CNL_PCH_H_GPIO_PCR_JTAG_PAD_OWN, R_CNL_PCH_H_GPIO_PCR_= JTAG_HOSTSW_OWN, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPER= TY, NO_REGISTER_FOR_PROPERTY, NO_REGISTER_FOR_PROPERTY, = R_CNL_PCH_H_GPIO_PCR_JTAG_PADCFGLOCK, R_CNL_PCH_H_GPIO_PCR_JTAG= _PADCFGLOCKTX, R_CNL_PCH_H_GPIO_PCR_JTAG_PADCFG_OFFSET, CNL_PCH_H_GPIO_= JTAG_PAD_MAX} //CNL PCH-H JTAG +}; + +/** + This procedure will retrieve address and length of GPIO info table + + @param[out] GpioGroupInfoTableLength Length of GPIO group table + + @retval Pointer to GPIO group table + +**/ +CONST GPIO_GROUP_INFO* +GpioGetGroupInfoTable ( + OUT UINT32 *GpioGroupInfoTableLength + ) +{ + if (IsPchLp ()) { + *GpioGroupInfoTableLength =3D ARRAY_SIZE (mPchLpGpioGroupInfo); + return mPchLpGpioGroupInfo; + } else { + *GpioGroupInfoTableLength =3D ARRAY_SIZE (mPchHGpioGroupInfo); + return mPchHGpioGroupInfo; + } +} + +/** + Get GPIO Chipset ID specific to PCH generation and series +**/ +UINT32 +GpioGetThisChipsetId ( + VOID + ) +{ + if (IsPchLp ()) { + return GPIO_CNL_LP_CHIPSET_ID; + } else { + return GPIO_CNL_H_CHIPSET_ID; + } +} + +/** + This internal procedure will check if group is within DeepSleepWell. + + @param[in] Group GPIO Group + + @retval GroupWell TRUE: This is DSW Group + FALSE: This is not DSW Group +**/ +BOOLEAN +GpioIsDswGroup ( + IN GPIO_GROUP Group + ) +{ + if ((Group =3D=3D GPIO_CNL_LP_GROUP_GPD) || (Group =3D=3D GPIO_CNL_H_GRO= UP_GPD)) { + return TRUE; + } else { + return FALSE; + } +} + +/** + This procedure will perform special handling of GPP_A_12. + + @param[in] None + + @retval None +**/ +VOID +GpioA12SpecialHandling ( + VOID + ) +{ + GPIO_PAD_OWN PadOwnVal; + GPIO_PAD GpioPad; + + // + // PCH BWG 16.6. GPP_A_12 Special Handling + // + if (IsPchLp ()) { + GpioPad =3D GPIO_CNL_LP_GPP_A12; + } else { + GpioPad =3D GPIO_CNL_H_GPP_A12; + } + GpioGetPadOwnership (GpioPad, &PadOwnVal); + + // + // If the pad is host-own, BIOS has to always lock this pad after being = initialized + // + if (PadOwnVal =3D=3D GpioPadOwnHost) { + // + // Set PadCfgLock for GPP_A_12 + // + GpioLockPadCfg (GpioPad); + } +} + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_SBI_PID mGpioComSbiIds[] =3D +{ + PID_GPIOCOM0, PID_GPIOCOM1, PID_GPIOCOM2, PID_GPIOCOM3, PID_GPIOCOM4 +}; + +/** + This function provides GPIO Community PortIDs + + @param[out] NativePinsTable Table with GPIO COMMx SBI Por= tIDs + + @retval Number of communities +**/ +UINT32 +GpioGetComSbiPortIds ( + OUT PCH_SBI_PID **GpioComSbiIds + ) +{ + *GpioComSbiIds =3D mGpioComSbiIds; + return ARRAY_SIZE (mGpioComSbiIds); +} + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_TO_GPE_MAPPING mPchLpGpioGroupToG= peMapping[] =3D { + {GPIO_CNL_LP_GROUP_GPP_A, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_A, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_A}, + {GPIO_CNL_LP_GROUP_GPP_B, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_B, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_B}, + {GPIO_CNL_LP_GROUP_GPP_C, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_C, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_C}, + {GPIO_CNL_LP_GROUP_GPP_D, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_D, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_D}, + {GPIO_CNL_LP_GROUP_GPP_E, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_E, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_E}, + {GPIO_CNL_LP_GROUP_GPP_F, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_F, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_F}, + {GPIO_CNL_LP_GROUP_GPP_G, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_G, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_G}, + {GPIO_CNL_LP_GROUP_GPP_H, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_H, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPP_H}, + {GPIO_CNL_LP_GROUP_GPD, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_GPD, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_GPD}, + {GPIO_CNL_LP_GROUP_VGPIO , 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_VGPIO, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_VGPIO}, + {GPIO_CNL_LP_GROUP_SPI, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_SPI, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_SPI}, + {GPIO_CNL_LP_GROUP_AZA, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_AZA, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_AZA}, + {GPIO_CNL_LP_GROUP_JTAG, 0, V_CNL_PCH_LP_PMC_PWRM_GPIO_CFG_JTAG, V_CN= L_PCH_LP_GPIO_PCR_MISCCFG_GPE0_JTAG} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_GROUP_TO_GPE_MAPPING mPchHGpioGroupToGp= eMapping[] =3D { + {GPIO_CNL_H_GROUP_GPP_A, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_A, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_A}, + {GPIO_CNL_H_GROUP_GPP_B, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_B, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_B}, + {GPIO_CNL_H_GROUP_GPP_C, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_C, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_C}, + {GPIO_CNL_H_GROUP_GPP_D, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_D, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_D}, + {GPIO_CNL_H_GROUP_GPP_E, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_E, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_E}, + {GPIO_CNL_H_GROUP_GPP_F, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_F, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_F}, + {GPIO_CNL_H_GROUP_GPP_G, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_G, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_G}, + {GPIO_CNL_H_GROUP_GPP_H, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_H, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_H}, + {GPIO_CNL_H_GROUP_GPP_I, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_I, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_I}, + {GPIO_CNL_H_GROUP_GPP_J, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_J, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_J}, + {GPIO_CNL_H_GROUP_GPP_K, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPP_K, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPP_K}, + {GPIO_CNL_H_GROUP_GPD, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_GPD, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_GPD}, + {GPIO_CNL_H_GROUP_VGPIO, 0, V_CNL_PCH_H_PMC_PWRM_GPIO_CFG_VGPIO, V_CNL_= PCH_H_GPIO_PCR_MISCCFG_GPE0_VGPIO} +}; + +/** + Get information for GPIO Group required to program GPIO and PMC for desi= red 1-Tier GPE mapping + + @param[out] GpioGroupToGpeMapping Table with GPIO Group to GPE ma= pping + @param[out] GpioGroupToGpeMappingLength GPIO Group to GPE mapping table= length +**/ +VOID +GpioGetGroupToGpeMapping ( + OUT GPIO_GROUP_TO_GPE_MAPPING **GpioGroupToGpeMapping, + OUT UINT32 *GpioGroupToGpeMappingLength + ) +{ + if (IsPchLp ()) { + *GpioGroupToGpeMapping =3D mPchLpGpioGroupToGpeMapping; + *GpioGroupToGpeMappingLength =3D ARRAY_SIZE (mPchLpGpioGroupToGpeMappi= ng); + } else { + *GpioGroupToGpeMapping =3D mPchHGpioGroupToGpeMapping; + *GpioGroupToGpeMappingLength =3D ARRAY_SIZE (mPchHGpioGroupToGpeMappin= g); + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchDmiLib/PchDmi14.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pri= vate/PeiDxeSmmPchDmiLib/PchDmi14.c new file mode 100644 index 0000000000..2f9b6a7e6f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PchDmi14.c @@ -0,0 +1,67 @@ +/** @file + This file contains functions for PCH DMI SIP14 + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + This function checks if DMI SIP14 Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmi14Locked ( + VOID + ) +{ + return ((PchPcrRead32 (PID_DMI, R_PCH_DMI14_PCR_DMIC) & B_PCH_DMI14_PCR_= DMIC_SRL) !=3D 0); +} + +/** + Enable PCIe Relaxed Order for DMI SIP14 +**/ +VOID +PchDmi14EnablePcieRelaxedOrder ( + VOID + ) +{ + // + // Enable Forced Relaxed Ordering to always allow downstream completions= to pass posted writes. + // Set Completion Relaxed Ordering Attribute Override Value + // and Completion Relaxed Ordering Attribute Override Enable + // + PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI14_PCR_2314, ~0u, (BIT31 | BIT7)); +} + +/** + Secure Register Lock data + + @param[out] SrlRegOffset Register offset holding Secure Register L= ock setting + @param[out] SrlRegMask Mask for Secure Register Lock setting +**/ +VOID +PchDmi14SrlRegData ( + OUT UINT16 *SrlRegOffset, + OUT UINT32 *SrlRegMask + ) +{ + *SrlRegMask =3D B_PCH_DMI14_PCR_DMIC_SRL; + *SrlRegOffset =3D R_PCH_DMI14_PCR_DMIC; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchDmiLib/PchDmi15.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pri= vate/PeiDxeSmmPchDmiLib/PchDmi15.c new file mode 100644 index 0000000000..c711b3de39 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PchDmi15.c @@ -0,0 +1,113 @@ +/** @file + This file contains functions for PCH DMI SIP15 + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + This function checks if DMI SIP15 Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmi15Locked ( + VOID + ) +{ + return ((PchPcrRead32 (PID_DMI, R_PCH_DMI15_PCR_MPC) & B_PCH_DMI15_PCR_M= PC_SRL) !=3D 0); +} + +/** + Set DMI thermal throttling to recommended configuration. + It's intended only for P-DMI SIP15. +**/ +VOID +PchDmi15SetRecommendedThermalThrottling ( + VOID + ) +{ + UINT32 Data32And; + UINT32 Data32Or; + /// + /// DMI recommended Thermal Sensor Target Width + /// is the HW default configuration: + /// - Thermal Sensor 3 Target Width: 0 (x1) + /// - Thermal Sensor 2 Target Width: 1 (x2) + /// - Thermal Sensor 1 Target Width: 2 (x4) + /// - Thermal Sensor 0 Target Width: 3 (x8) + /// Enable Thermal Sensor Autonomous Width + /// + Data32And =3D (UINT32)~(B_PCH_DMI15_PCR_UPHWAWC_TS3TW | B_PCH_DMI15_PCR_= UPHWAWC_TS2TW | + B_PCH_DMI15_PCR_UPHWAWC_TS1TW | B_PCH_DMI15_PCR_UP= HWAWC_TS0TW); + Data32Or =3D (0 << N_PCH_DMI15_PCR_UPHWAWC_TS3TW) | + (1 << N_PCH_DMI15_PCR_UPHWAWC_TS2TW) | + (2 << N_PCH_DMI15_PCR_UPHWAWC_TS1TW) | + (3 << N_PCH_DMI15_PCR_UPHWAWC_TS0TW) | + B_PCH_DMI15_PCR_UPHWAWC_TSAWEN; + + PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI15_PCR_UPHWAWC, Data32And, Data32Or= ); +} + +/** + Set DMI thermal throttling to custom configuration. + This function will configure Thermal Sensor 0/1/2/3 TargetWidth and set + DMI Thermal Sensor Autonomous Width Enable. + It's intended only for P-DMI SIP15. + + @param[in] DmiThermalThrottling DMI Thermal Throttling structure. +**/ +VOID +PchDmi15SetCustomThermalThrottling ( + IN DMI_THERMAL_THROTTLING DmiThermalThrottling + ) +{ + UINT32 Data32And; + UINT32 Data32Or; + + /// + /// DMI Throttling action + /// + Data32And =3D (UINT32)~(B_PCH_DMI15_PCR_UPHWAWC_TS3TW | B_PCH_DMI15_PCR_= UPHWAWC_TS2TW | + B_PCH_DMI15_PCR_UPHWAWC_TS1TW | B_PCH_DMI15_PCR_UP= HWAWC_TS0TW); + Data32Or =3D (DmiThermalThrottling.ThermalSensor3TargetWidth << N_PCH_D= MI15_PCR_UPHWAWC_TS3TW) | + (DmiThermalThrottling.ThermalSensor2TargetWidth << N_PCH_DMI= 15_PCR_UPHWAWC_TS2TW) | + (DmiThermalThrottling.ThermalSensor1TargetWidth << N_PCH_DMI= 15_PCR_UPHWAWC_TS1TW) | + (DmiThermalThrottling.ThermalSensor0TargetWidth << N_PCH_DMI= 15_PCR_UPHWAWC_TS0TW) | + B_PCH_DMI15_PCR_UPHWAWC_TSAWEN; + + PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI15_PCR_UPHWAWC, Data32And, Data32Or= ); +} + + +/** + Secure Register Lock data + + @param[out] SrlRegOffset Register offset holding Secure Register L= ock setting + @param[out] SrlRegMask Mask for Secure Register Lock setting +**/ +VOID +PchDmi15SrlRegData ( + OUT UINT16 *SrlRegOffset, + OUT UINT32 *SrlRegMask + ) +{ + *SrlRegMask =3D B_PCH_DMI15_PCR_MPC_SRL; + *SrlRegOffset =3D R_PCH_DMI15_PCR_MPC; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchDmiLib/PchDmiLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Pr= ivate/PeiDxeSmmPchDmiLib/PchDmiLib.c new file mode 100644 index 0000000000..f1b2867659 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PchDmiLib.c @@ -0,0 +1,569 @@ +/** @file + PCH DMI library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PchDmi14.h" +#include "PchDmi15.h" + +/** + This function checks if DMI Secured Register Lock (SRL) is set + + @retval SRL state +**/ +BOOLEAN +IsPchDmiLocked ( + VOID + ) +{ + if (IsPchWithPdmi ()) { + return IsPchDmi15Locked (); + } else { + return IsPchDmi14Locked (); + } +} + +/** + Backward DMI library API compatibility + ACPI base address programming is done in PSF + + @param[in] Address Address for ACPI base. + + @retval EFI_UNSUPPORTED NOT supported programming. +**/ +EFI_STATUS +PchDmiSetAcpiBase ( + IN UINT16 Address + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Backward DMI library API compatibility + PWRMBASE is a standard BAR and doesn't require + additional DMI base decoding programming + + @param[in] Address Address for PWRM base. + + @retval EFI_UNSUPPORTED NOT supported programming. +**/ +EFI_STATUS +PchDmiSetPwrmBase ( + IN UINT32 Address + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Set PCH TCO base address decoding in DMI + + @param[in] Address Address for TCO base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetTcoBase ( + IN UINT16 Address + ) +{ + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] to [SMBUS PCI of= fset 50h[15:5], 1]. + // + PchPcrWrite16 ( + PID_DMI, R_PCH_DMI_PCR_TCOBASE, + (Address | BIT1) + ); + + return EFI_SUCCESS; +} + +/** + Get PCH TCO base address. + + @retval Address Address of TCO base address. +**/ +UINT16 +PchDmiGetTcoBase ( + VOID + ) +{ + // + // Read "TCO Base Address" PCR[DMI] + 2778h[15:5] + // + return (PchPcrRead16 (PID_DMI, R_PCH_DMI_PCR_TCOBASE) & B_PCH_DMI_PCR_TC= OBASE_TCOBA); +} + +/** + Set PCH LPC/eSPI generic IO range decoding in DMI + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + @param[in] RangeIndex Index of choosen range + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcGenIoRange ( + IN UINT32 Address, + IN UINT32 Length, + IN UINT32 RangeIndex + ) +{ + UINT32 Data32; + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Data32 =3D (UINT32) (((Length - 1) << 16) & B_LPC_CFG_GENX_DEC_IODRA); + Data32 |=3D (UINT32) Address; + Data32 |=3D B_LPC_CFG_GENX_DEC_EN; + // + // Program LPC Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same = value programmed in LPC/eSPI PCI Offset 84h~93h. + // + PchPcrWrite32 ( + PID_DMI, (UINT16) (R_PCH_DMI_PCR_LPCLGIR1 + RangeIndex * 4), + Data32 + ); + + return EFI_SUCCESS; +} + +/** + Set PCH eSPI eSPI CS1# generic IO range decoding in DMI + + @param[in] Address Address for generic IO range base = address. + @param[in] Length Length of generic IO range. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1GenIoRange ( + IN UINT32 Address, + IN UINT32 Length + ) +{ + UINT32 Data32; + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Data32 =3D (UINT32) (((Length - 1) << 16) & B_LPC_CFG_GENX_DEC_IODRA); + Data32 |=3D (UINT32) Address; + Data32 |=3D B_LPC_CFG_GENX_DEC_EN; + // + // Program eSPI Generic IO Range #, PCR[DMI] + 27BCh to the same value p= rogrammed in eSPI PCI Offset A4h. + // + PchPcrWrite32 (PID_DMI, R_PCH_DMI_PCR_SEGIR, Data32); + + return EFI_SUCCESS; +} + +/** + Clear PCH LPC/eSPI generic IO range decoding in DMI + + @param[in] RangeIndex Index of chosen range + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiClearLpcGenIoRange ( + IN UINTN RangeIndex + ) +{ + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // Program LPC Generic IO Range #, PCR[DMI] + 2730h ~ 273Fh to the same = value programmed in LPC/eSPI PCI Offset 84h~93h. + // + PchPcrWrite32 ( + PID_DMI, (UINT16) (R_PCH_DMI_PCR_LPCLGIR1 + RangeIndex * 4), + 0 + ); + + return EFI_SUCCESS; +} + +/** + Clear PCH eSPI CS1# generic IO range decoding in DMI + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiClearEspiCs1GenIoRange ( + VOID + ) +{ + // + // This cycle decoding is only allowed to set when DMIC.SRL is 0. + // + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + // + // Program LPC Generic IO Range #, PCR[DMI] + 27BCh to the same value pr= ogrammed in eSPI PCI Offset A4h. + // + PchPcrWrite32 (PID_DMI, R_PCH_DMI_PCR_SEGIR, 0); + + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI memory range decoding in DMI + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcMemRange ( + IN UINT32 Address + ) +{ + if (IsPchDmiLocked ()) { + DEBUG ((DEBUG_ERROR, "PchDmiSetLpcMemRange Error. DMI is locked.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // Program LPC Memory Range, PCR[DMI] + 2740h to the same value programm= ed in LPC/eSPI PCI Offset 98h. + // + PchPcrWrite32 ( + PID_DMI, R_PCH_DMI_PCR_LPCGMR, + (Address | B_LPC_CFG_LGMR_LMRD_EN) + ); + + return EFI_SUCCESS; +} + +/** + Set PCH eSPI CS1# memory range decoding in DMI + + @param[in] Address Address for memory base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetEspiCs1MemRange ( + IN UINT32 Address + ) +{ + if (IsPchDmiLocked ()) { + DEBUG ((DEBUG_ERROR, "PchLpcMemRange2Set Error. DMI is locked.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // Program LPC Memory Range, PCR[DMI] + 27C0h to the same value programm= ed in eSPI PCI Offset A8h. + // + PchPcrWrite32 ( + PID_DMI, R_PCH_DMI_PCR_SEGMR, + (Address | B_LPC_CFG_LGMR_LMRD_EN) + ); + + return EFI_SUCCESS; +} + +/** + Check if Boot BIOS Strap is set for SPI. + + @retval TRUE Boot BIOS Strap set for SPI + @retval FALSE Boot BIOS Strap set for LPC/eSPI +**/ +BOOLEAN +PchDmiIsBootBiosStrapSetForSpi ( + VOID + ) +{ + // + // Check General Control and Status (GCS) [10] + // '0': SPI + // '1': LPC/eSPI + // + return ((PchPcrRead32 (PID_DMI, R_PCH_DMI_PCR_GCS) & B_PCH_DMI_PCR_BBS) = !=3D B_PCH_DMI_PCR_BBS); +} + +/** + Set PCH BIOS range decoding in DMI + Please check EDS for detail of BiosDecodeEnable bit definition. + bit 15: F8-FF Enable + bit 14: F0-F8 Enable + bit 13: E8-EF Enable + bit 12: E0-E8 Enable + bit 11: D8-DF Enable + bit 10: D0-D7 Enable + bit 9: C8-CF Enable + bit 8: C0-C7 Enable + bit 7: Legacy F Segment Enable + bit 6: Legacy E Segment Enable + bit 5: Reserved + bit 4: Reserved + bit 3: 70-7F Enable + bit 2: 60-6F Enable + bit 1: 50-5F Enable + bit 0: 40-4F Enable + + @param[in] BiosDecodeEnable Bios decode enable setting. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetBiosDecodeEnable ( + IN UINT16 BiosDecodeEnable + ) +{ + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program LPC BIOS Decode Enable, PCR[DMI] + 2744h to the same value pr= ogrammed in LPC or SPI Offset D8h. + // + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCBDE, BiosDecodeEnable); + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO decode ranges in DMI + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition. + Bit 12: FDD range + Bit 9:8: LPT range + Bit 6:4: ComB range + Bit 2:0: ComA range + + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcIoDecodeRanges ( + IN UINT16 LpcIoDecodeRanges + ) +{ + // + // This cycle decoding is only allowed to set when DMI is not locked. + // + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same val= ue programmed in LPC/eSPI PCI offset 80h. + // + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOD, LpcIoDecodeRanges); + return EFI_SUCCESS; +} + +/** + Set PCH LPC/eSPI IO enable decoding in DMI + + @param[in] LpcIoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PchDmiSetLpcIoEnable ( + IN UINT16 LpcIoEnableDecoding + ) +{ + // + // This cycle decoding is only allowed to set when DMI is not locked. + // + if (IsPchDmiLocked ()) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // program LPC I/O Decode Ranges, PCR[DMI] + 2774h[15:0] to the same val= ue programmed in LPC/eSPI PCI offset 82h. + // + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_LPCIOE, LpcIoEnableDecoding); + return EFI_SUCCESS; +} + + +/** + Set PCH IO port 80h cycle decoding to PCIE root port in DMI + + @param[in] RpNumber PCIE root port physical number. + + @retval EFI_SUCCESS Successfully completed. +**/ +EFI_STATUS +PchDmiSetIoPort80Decode ( + IN UINTN RpNumber + ) +{ + UINT16 DmiRpDestinationId; + PSF_PORT_DEST_ID PsfRpDestinationId; + + if (IsPchDmiLocked ()) { + DEBUG ((DEBUG_ERROR, "PchIoPort80DecodeSet Error. DMI is locked.\n")); + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + /// + /// IO port 80h is typically used by decoder/LED hardware for debug purp= oses. + /// By default PCH will forward IO port 80h cycles to LPC bus. The Reser= ved Page Route (RPR) bit + /// of General Control and Status register, located at PCR[DMI] + 274Ch[= 11] , allows software to + /// re-direct IO port 80h cycles to PCIe bus so that a target (for examp= le, a debug card) on + /// PCIe bus can receive and claim these cycles. + /// The "RPR Destination ID", PCR[DMI] + 274Ch[31:16] need to be set acc= ordingly to point + /// to the root port that decode this range. Reading from Port 80h may n= ot return valid values + /// if the POST-card itself do not shadow the writes. Unlike LPC, PCIe d= oes not shadow the Port 80 writes. + /// + PsfRpDestinationId =3D PsfPcieDestinationId ((UINT32)RpNumber); + + DmiRpDestinationId =3D (UINT16)((0x2 << 12) | + (PsfRpDestinationId.Fields.PsfId << 8) | + (PsfRpDestinationId.Fields.PortGroupId << = 7) | + (PsfRpDestinationId.Fields.PortId << 3) | + PsfRpDestinationId.Fields.ChannelId); + + // + // Program "RPR Destination ID", PCR[DMI] + 274Ch[31:16] to the Dest ID = of RP. + // + PchPcrWrite16 (PID_DMI, R_PCH_DMI_PCR_GCS + 2, DmiRpDestinationId); + // + // Program "Reserved Page Route", PCR[DMI] + 274Ch[11] to '1'. + // Use byte write on GCS+1 and leave the BILD bit which is RWO. + // + PchPcrAndThenOr8 (PID_DMI, R_PCH_DMI_PCR_GCS + 1, 0xFF, (B_PCH_DMI_PCR_R= PR >> 8)); + + return EFI_SUCCESS; +} + +/** + Set DMI thermal throttling to recommended configuration. + It's intended only for P-DMI. +**/ +VOID +PchDmiSetRecommendedThermalThrottling ( + VOID + ) +{ + if (IsPchWithPdmi ()) { + PchDmi15SetRecommendedThermalThrottling (); + } +} + +/** + Set DMI thermal throttling to custom configuration. + This function will configure Thermal Sensor 0/1/2/3 TargetWidth and set + DMI Thermal Sensor Autonomous Width Enable. + It's intended only for P-DMI. + + @param[in] DmiThermalThrottling DMI Thermal Throttling structure. +**/ +VOID +PchDmiSetCustomThermalThrottling ( + IN DMI_THERMAL_THROTTLING DmiThermalThrottling + ) +{ + if (IsPchWithPdmi ()) { + PchDmi15SetCustomThermalThrottling (DmiThermalThrottling); + } +} + +/** + Determines where to send the reserved page registers + Accesses to the I/O ranges 80h - 8Fh will be forwarded to PCIe Root Port + with the destination ID specified in GCS.RPRDID using DMI source decode. +**/ +VOID +PchDmiSetReservedPageRegToPcieRootPort ( + VOID + ) +{ + PchPcrAndThenOr8 ( + PID_DMI, R_PCH_DMI_PCR_GCS + 1, + (UINT8) ~0, + (UINT8) (B_PCH_DMI_PCR_RPR >> 8) + ); +} + +/** + Determines where to send the reserved page registers + DMI will not perform source decode on the I/O ranges 80h - 8Fh. The cycl= es hitting these ranges will + end up in P2SB which will then forward the cycle to LPC or eSPI through = IOSF Sideband. +**/ +VOID +PchDmiSetReservedPageRegToLpc ( + VOID + ) +{ + PchPcrAndThenOr8 ( + PID_DMI, R_PCH_DMI_PCR_GCS + 1, + (UINT8) (~(B_PCH_DMI_PCR_RPR >> 8)), + 0 + ); +} + +/** + uCode Patch Region Enable (UPRE). Enables memory access targeting the uC= ode patch region (0xFEF00000 to 0xFEFFFFFF) + to be forwarded to SPI Flash. This can only be set if the boot flash is = on SPI. +**/ +VOID +PchDmiEnableUCodePatchRegion ( + VOID + ) +{ + /// + /// Setup "uCode Patch Region Enable", PCR [DMI] + 2748h[0] to '0b' + /// + PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI_PCR_UCPR, (UINT32) ~B_PCH_DMI_PCR_= UCPR_UPRE, 0); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchDmiLib/PchDmiWithS3Lib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Libr= ary/Private/PeiDxeSmmPchDmiLib/PchDmiWithS3Lib.c new file mode 100644 index 0000000000..9778c9a252 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PchDmiWithS3Lib.c @@ -0,0 +1,79 @@ +/** @file + PCH DMI library with S3 boot script support. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PchDmi14.h" +#include "PchDmi15.h" + +/** + Configure PCH DMI Lock +**/ +VOID +PchDmiSetLockWithS3BootScript ( + VOID + ) +{ + UINT32 Data32Or; + UINT32 Data32And; + UINT16 Address; + + Data32And =3D 0xFFFFFFFF; + if (IsPchWithPdmi ()) { + PchDmi15SrlRegData (&Address, &Data32Or); + } else { + PchDmi14SrlRegData (&Address, &Data32Or); + } + + PchPcrAndThenOr32 ( + PID_DMI, Address, + Data32And, + Data32Or + ); + PCH_PCR_BOOT_SCRIPT_READ_WRITE ( + S3BootScriptWidthUint32, + PID_DMI, Address, + &Data32Or, + &Data32And + ); +} + +/** + Set BIOS interface Lock-Down +**/ +VOID +PchDmiSetBiosLockDownWithS3BootScript ( + VOID + ) +{ + UINT32 Data32Or; + UINT32 Data32And; + + // + // Set BIOS Lock-Down (BILD) + // When set, prevents GCS.BBS from being changed + // + Data32And =3D 0xFFFFFFFF; + Data32Or =3D B_PCH_DMI_PCR_BILD; + PchPcrAndThenOr32 (PID_DMI, R_PCH_DMI_PCR_GCS, Data32And, Data32Or); + PCH_PCR_BOOT_SCRIPT_READ_WRITE ( + S3BootScriptWidthUint32, + PID_DMI, R_PCH_DMI_PCR_GCS, + &Data32Or, + &Data32And + ); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchInitCommonLib/PchInitCommon.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch= /Library/Private/PeiDxeSmmPchInitCommonLib/PchInitCommon.c new file mode 100644 index 0000000000..14bd51ec43 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchIn= itCommonLib/PchInitCommon.c @@ -0,0 +1,221 @@ +/** @file + Pch common library for PCH INIT PEI/DXE/SMM modules + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern CONST PCH_PCIE_CONTROLLER_INFO mPchPcieControllerInfo[]; +extern CONST UINT32 mPchPcieControllerInfoSize; + +#define PORT_PLS_TIMEOUT 100 ///< 100 * 10 us =3D 1ms timeout for USB3 = PortSC PLS polling + +/** + This function returns PID according to PCIe controller index + + @param[in] ControllerIndex PCIe controller index + + @retval PCH_SBI_PID Returns PID for SBI Access +**/ +PCH_SBI_PID +PchGetPcieControllerSbiPid ( + IN UINT32 ControllerIndex + ) +{ + ASSERT (ControllerIndex < mPchPcieControllerInfoSize); + return mPchPcieControllerInfo[ControllerIndex].Pid; +} + +/** + This function returns PID according to Root Port Number + + @param[in] RpIndex Root Port Index (0-based) + + @retval PCH_SBI_PID Returns PID for SBI Access +**/ +PCH_SBI_PID +GetRpSbiPid ( + IN UINTN RpIndex + ) +{ + return PchGetPcieControllerSbiPid ((UINT32) (RpIndex / PCH_PCIE_CONTROLL= ER_PORTS)); +} + +/** + Calculate root port device number based on physical port index. + + @param[in] RpIndex Root port index (0-based). + + @retval Root port device number. +**/ +UINT32 +PchGetPcieRpDevice ( + IN UINT32 RpIndex + ) +{ + UINTN ControllerIndex; + ControllerIndex =3D RpIndex / PCH_PCIE_CONTROLLER_PORTS; + ASSERT (ControllerIndex < mPchPcieControllerInfoSize); + return mPchPcieControllerInfo[ControllerIndex].DevNum; +} + +/** + This function reads Pci Config register via SBI Access + + @param[in] RpIndex Root Port Index (0-based) + @param[in] Offset Offset of Config register + @param[out] *Data32 Value of Config register + + @retval EFI_SUCCESS SBI Read successful. +**/ +EFI_STATUS +PchSbiRpPciRead32 ( + IN UINT32 RpIndex, + IN UINT32 Offset, + OUT UINT32 *Data32 + ) +{ + EFI_STATUS Status; + UINT32 RpDevice; + UINT8 Response; + UINT16 Fid; + + RpDevice =3D PchGetPcieRpDevice (RpIndex); + Fid =3D (UINT16) ((RpDevice << 3) | (RpIndex % 4 )); + Status =3D PchSbiExecutionEx ( + GetRpSbiPid (RpIndex), + Offset, + PciConfigRead, + FALSE, + 0xF, + 0, + Fid, + Data32, + &Response + ); + if (Status !=3D EFI_SUCCESS) { + DEBUG((DEBUG_ERROR,"Sideband Read Failed of RpIndex %d Offset 0x%x. De= vice =3D %d Fid =3D 0x%x\n",RpIndex, Offset, RpDevice, Fid)); + ASSERT (FALSE); + } + return Status; +} + +/** + This function And then Or Pci Config register via SBI Access + + @param[in] RpIndex Root Port Index (0-based) + @param[in] Offset Offset of Config register + @param[in] Data32And Value of Config register to be And-ed + @param[in] Data32AOr Value of Config register to be Or-ed + + @retval EFI_SUCCESS SBI Read and Write successful. +**/ +EFI_STATUS +PchSbiRpPciAndThenOr32 ( + IN UINT32 RpIndex, + IN UINT32 Offset, + IN UINT32 Data32And, + IN UINT32 Data32Or + ) +{ + EFI_STATUS Status; + UINT32 RpDevice; + UINT32 Data32; + UINT8 Response; + UINT16 Fid; + + RpDevice =3D PchGetPcieRpDevice (RpIndex); + Status =3D PchSbiRpPciRead32 (RpIndex, Offset, &Data32); + if (Status =3D=3D EFI_SUCCESS) { + Data32 &=3D Data32And; + Data32 |=3D Data32Or; + Fid =3D (UINT16) ((RpDevice << 3) | (RpIndex % 4 )); + Status =3D PchSbiExecutionEx ( + GetRpSbiPid (RpIndex), + Offset, + PciConfigWrite, + FALSE, + 0xF, + 0, + Fid, + &Data32, + &Response + ); + if (Status !=3D EFI_SUCCESS) { + DEBUG((DEBUG_ERROR,"Sideband Write Failed of RpIndex %d Offset 0x%x.= Device =3D %d Fid =3D 0x%x\n",RpIndex, Offset, RpDevice, Fid)); + ASSERT (FALSE); + } + } else { + ASSERT (FALSE); + } + return Status; +} + +/** + Print registers value + + @param[in] PrintMmioBase Mmio base address + @param[in] PrintSize Number of registers + @param[in] OffsetFromBase Offset from mmio base address + + @retval None +**/ +VOID +PrintRegisters ( + IN UINTN PrintMmioBase, + IN UINT32 PrintSize, + IN UINT32 OffsetFromBase + ) +{ + UINT32 Offset; + DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D= 0E 0F")); + for (Offset =3D 0; Offset < PrintSize; Offset++) { + if ((Offset % 16) =3D=3D 0) { + DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFF= F0)); + } + DEBUG ((DEBUG_VERBOSE, "%02X ", MmioRead8 (PrintMmioBase + Offset))); + } + DEBUG ((DEBUG_VERBOSE, "\n")); +} + +/** + Print registers value + + @param[in] PrintPciSegmentBase Pci segment base address + @param[in] PrintSize Number of registers + @param[in] OffsetFromBase Offset from mmio base address + + @retval None +**/ +VOID +PrintPciRegisters ( + IN UINT64 PrintPciSegmentBase, + IN UINT32 PrintSize, + IN UINT32 OffsetFromBase + ) +{ + UINT32 Offset; + DEBUG ((DEBUG_VERBOSE, " 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D= 0E 0F")); + for (Offset =3D 0; Offset < PrintSize; Offset++) { + if ((Offset % 16) =3D=3D 0) { + DEBUG ((DEBUG_VERBOSE, "\n %04X: ", (Offset + OffsetFromBase) & 0xFF= F0)); + } + DEBUG ((DEBUG_VERBOSE, "%02X ", PciSegmentRead8 (PrintPciSegmentBase += Offset))); + } + DEBUG ((DEBUG_VERBOSE, "\n")); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchPciExpressHelpersLib/PchPciExpressHelpersLibrary.c b/Silicon/Intel/Cof= feelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPciExpressHelpersLib/PchP= ciExpressHelpersLibrary.c new file mode 100644 index 0000000000..dcb43285b7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPc= iExpressHelpersLib/PchPciExpressHelpersLibrary.c @@ -0,0 +1,2407 @@ +/** @file + This file contains routines that support PCI Express initialization + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchPciExpressHelpersLibrary.h" +#include + +#define ASPM_L1_NO_LIMIT 0xFF +#define ASPM_L0s_NO_LIMIT 0x7 + +#define LINK_RETRAIN_WAIT_TIME 1000 // microseconds +// +// This structure conveniently keeps segment:bus:device:function coordinat= es of a PCIe device +// in a single variable. PcieCap is offset to PCI Express capabilities. Ha= ving it cached together +// with coordinates is an optimization feature, because code in this file = uses it a lot +// +typedef struct { + UINT32 Seg : 8; + UINT32 Bus : 8; + UINT32 Dev : 5; + UINT32 Func : 3; + UINT32 PcieCap : 8; +} SBDF; + +typedef struct { + UINT32 MaxSnoopLatencyValue : 10; + UINT32 MaxSnoopLatencyScale : 3; + UINT32 MaxSnoopLatencyRequirement : 1; + UINT32 MaxNoSnoopLatencyValue : 10; + UINT32 MaxNoSnoopLatencyScale : 3; + UINT32 MaxNoSnoopLatencyRequirement : 1; + UINT32 ForceOverride : 1; +} LTR_OVERRIDE; + +typedef struct { + UINT32 MaxSnoopLatencyValue : 10; + UINT32 MaxSnoopLatencyScale : 3; + UINT32 MaxNoSnoopLatencyValue : 10; + UINT32 MaxNoSnoopLatencyScale : 3; +} LTR_LIMIT; + +#define MSLV_BIT_OFFSET 0 +#define MSLS_BIT_OFFSET 10 +#define MNSLV_BIT_OFFSET 13 +#define MNSLS_BIT_OFFSET 23 + + +typedef struct { + UINT32 Size; + const PCH_PCIE_DEVICE_OVERRIDE* Table; +} OVERRIDE_TABLE; + +typedef enum { + DevTypePci, + DevTypePcieEndpoint, + DevTypePcieUpstream, + DevTypePcieDownstream, + DevTypeMax +} PCI_DEV_TYPE; + +// +// This structure keeps in one place all data relevant to enabling L0s and= L1. +// L0s latencies are encoded in the same way as in hardware registers. The= only operation +// that will be performed on them is comparison +// L1 latencies are decoded to microseconds, because they will be used in = subtractions and additions +// +typedef struct { + UINT32 L0sSupported : 1; + UINT32 L1Supported : 1; + UINT32 L0sAcceptableLatency : 3; // encoded as in hardware register + UINT32 L1AcceptableLatencyUs : 8; // decoded to microseconds + UINT32 LinkL0sExitLatency : 3; // encoded as in hardware register + UINT32 LinkL1ExitLatencyUs : 8; // decoded to microseconds +} ASPM_CAPS; + +typedef struct { + UINT32 AspmL11 : 1; + UINT32 AspmL12 : 1; + UINT32 PmL11 : 1; + UINT32 PmL12 : 1; + UINT32 Cmrt : 8; // Common Mode Restore Time + UINT32 TpoScale : 2; // T power_on scale + UINT32 TpoValue : 6; // T power_on value +} L1SS_CAPS; + +#define MAX_SBDF_TABLE_SIZE 50 //arbitrary table size; big enough to accom= odate even full length TBT chain. + +typedef struct { + UINT32 Count; + SBDF Entry [MAX_SBDF_TABLE_SIZE]; +} SBDF_TABLE; + +/** + Converts device's segment:bus:device:function coordinates to flat address + + @param[in] Sbdf device's segment:bus:device:function coordinates + @retval address of device's PCI cfg space +**/ +STATIC +UINT64 +SbdfToBase ( + SBDF Sbdf + ) +{ + return PCI_SEGMENT_LIB_ADDRESS (Sbdf.Seg, Sbdf.Bus, Sbdf.Dev, Sbdf.Func,= 0); +} + +/** + Get PCIe port number for enabled port. + @param[in] RpBase Root Port pci segment base address + @retval Root Port number (1 based) +**/ +UINT32 +PciePortNum ( + IN UINT64 RpBase + ) +{ + return PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_LCAP) >> N_PCH_PCIE_CFG= _LCAP_PN; +} + +/** + Get PCIe root port index + @param[in] RpBase Root Port pci segment base address + @retval Root Port index (0 based) +**/ +UINT32 +PciePortIndex ( + IN UINT64 RpBase + ) +{ + return PciePortNum (RpBase) - 1; +} + +/** + Translate PCIe Port/Lane pair to 0-based PCIe lane number. + + @param[in] RpIndex Root Port index + @param[in] RpLane Root Port Lane (0-3) + + @retval PCIe lane number (0-based) +**/ +UINT32 +PchPciePhysicalLane ( + UINT32 RpIndex, + UINT32 RpLane + ) +{ + UINT32 ControllerIndex; + UINT32 ControllerLane; + + ASSERT (RpIndex < GetPchMaxPciePortNum ()); + ASSERT (((RpIndex % 4) + RpLane) < 4); + + ControllerIndex =3D (RpIndex / 4); + ControllerLane =3D (RpIndex % 4) + RpLane; + if (IsPcieLaneReversalEnabled (RpIndex)) { + ControllerLane =3D 3 - ControllerLane; + } + return (ControllerIndex * 4) + ControllerLane; +} + +/** + Checks if lane reversal is enabled on a given root port + + @param[in] RpIndex Root port index (0-based) + + @retval TRUE if lane reversal is enbabled, FALSE otherwise +**/ +BOOLEAN +IsPcieLaneReversalEnabled ( + IN UINT32 RpIndex + ) +{ + UINT32 Data32; + PchSbiRpPciRead32 (PchGetPcieFirstPortIndex (RpIndex), R_PCH_PCIE_CFG_PC= IEDBG, &Data32); + return !! (Data32 & B_PCH_PCIE_CFG_PCIEDBG_LR); +} + +/** + Calculates the index of the first port on the same controller. + + @param[in] RpIndex Root Port Number (0-based) + + @retval Index of the first port on the first controller. +**/ +UINT32 +PchGetPcieFirstPortIndex ( + IN UINT32 RpIndex + ) +{ + UINT32 ControllerIndex; + + ControllerIndex =3D RpIndex / PCH_PCIE_CONTROLLER_PORTS; + return ControllerIndex * PCH_PCIE_CONTROLLER_PORTS; +} + +/* + Returns Tpower_on capability of device + + @param[in] DeviceBase device's PCI segment base address + @param[in] L1ssCapOffset offset to L1substates capability in device's= extended config space + + @retval structure containing Tpoweron scale and value +*/ +T_POWER_ON +GetTpoCapability ( + UINT64 DeviceBase, + UINT32 L1ssCapOffset + ) +{ + T_POWER_ON Tpo; + UINT32 L1ssCapabilities; + + L1ssCapabilities =3D PciSegmentRead32 (DeviceBase + L1ssCapOffset + R_PC= IE_EX_L1SCAP_OFFSET); + Tpo.Scale =3D (L1ssCapabilities & B_PCIE_EX_L1SCAP_PTPOS) >> N_PCIE_EX_L= 1SCAP_PTPOS; + Tpo.Value =3D (L1ssCapabilities & B_PCIE_EX_L1SCAP_PTV) >> N_PCIE_EX_L1S= CAP_PTV; + return Tpo; +} + +/* + Converts Tpower_on from value:scale notation to microseconds + + @param[in] TpoScale T power on scale + @param[in] TpoValue T power on value + + @retval number of microseconds +*/ +UINT32 +TpoToUs ( + UINT32 TpoScale, + UINT32 TpoValue + ) +{ + static const UINT8 TpoScaleMultiplier[] =3D {2, 10, 100}; + + ASSERT (TpoScale < TpoScaleMax); + if (TpoScale >=3D TpoScaleMax) { + return 0; + } + return (TpoScaleMultiplier[TpoScale] * TpoValue); +} + +/** + Finds the Offset to a given Capabilities ID + Each capability has an ID and a pointer to next Capability, so they form= a linked list. + This function walks the list of Capabilities present in device's pci cfg= . If requested capability + can be found, its offset is returned. + If the capability can't be found or if device doesn't exist, function re= turns 0 + CAPID list: + 0x01 =3D PCI Power Management Interface + 0x04 =3D Slot Identification + 0x05 =3D MSI Capability + 0x10 =3D PCI Express Capability + + @param[in] DeviceBase device's base address + @param[in] CapId CAPID to search for + + @retval 0 CAPID not found (this includes situation= where device doesn't exit) + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT8 +PcieBaseFindCapId ( + IN UINT64 DeviceBase, + IN UINT8 CapId + ) +{ + UINT8 CapHeaderOffset; + UINT8 CapHeaderId; + UINT16 Data16; + // + // We do not explicitly check if device exists to save time and avoid un= necessary PCI access + // If the device doesn't exist, check for CapHeaderId !=3D 0xFF will fai= l and function will return offset 0 + // + if ((PciSegmentRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) & EFI_PCI_= STATUS_CAPABILITY) =3D=3D 0x00) { + /// + /// Function has no capability pointer + /// + return 0; + } else { + /// + /// Check the header layout to determine the Offset of Capabilities Po= inter Register + /// + if ((PciSegmentRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_LA= YOUT_CODE) =3D=3D (HEADER_TYPE_CARDBUS_BRIDGE)) { + /// + /// If CardBus bridge, start at Offset 0x14 + /// + CapHeaderOffset =3D EFI_PCI_CARDBUS_BRIDGE_CAPABILITY_PTR; + } else { + /// + /// Otherwise, start at Offset 0x34 + /// + CapHeaderOffset =3D PCI_CAPBILITY_POINTER_OFFSET; + } + /// + /// Get Capability Header, A pointer value of 00h is used to indicate = the last capability in the list. + /// + CapHeaderId =3D 0; + CapHeaderOffset =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset) & (= (UINT8) ~(BIT0 | BIT1)); + while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D 0xFF) { + Data16 =3D PciSegmentRead16 (DeviceBase + CapHeaderOffset); + CapHeaderId =3D (UINT8)(Data16 & 0xFF); + if (CapHeaderId =3D=3D CapId) { + if (CapHeaderOffset > PCI_MAXLAT_OFFSET) { + /// + /// Return valid capability offset + /// + DEBUG ((DEBUG_INFO,"CapId %x,%x->%02x\n", ((UINT32)(DeviceBase&0= xFFFFF000)>>12), CapId, CapHeaderOffset)); + return CapHeaderOffset; + } else { + ASSERT ((FALSE)); + return 0; + } + } + /// + /// Each capability must be DWORD aligned. + /// The bottom two bits of all pointers (including the initial point= er at 34h) are reserved + /// and must be implemented as 00b although software must mask them = to allow for future uses of these bits. + /// + CapHeaderOffset =3D (UINT8)(Data16 >> 8); + } + return 0; + } +} + +/** + Find the Offset to a given Capabilities ID + CAPID list: + 0x01 =3D PCI Power Management Interface + 0x04 =3D Slot Identification + 0x05 =3D MSI Capability + 0x10 =3D PCI Express Capability + + @param[in] Segment Pci Segment Number + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT8 +PcieFindCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 CapId + ) +{ + UINT64 DeviceBase; + + DEBUG ((DEBUG_INFO,"PcieFindCapId () SBDF %0x: %0x: %0x :%0x, CapId =3D = %0x \n", Segment, Bus, Device, Function, CapId)); + DeviceBase =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, = 0); + return PcieBaseFindCapId (DeviceBase, CapId); +} + +/** + Search and return the offset of desired Pci Express Capability ID + CAPID list: + 0x0001 =3D Advanced Error Reporting Capability + 0x0002 =3D Virtual Channel Capability + 0x0003 =3D Device Serial Number Capability + 0x0004 =3D Power Budgeting Capability + + @param[in] DeviceBase device base address + @param[in] CapId Extended CAPID to search for + + @retval 0 CAPID not found, this includes situation= where device doesn't exist + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT16 +PcieBaseFindExtendedCapId ( + IN UINT64 DeviceBase, + IN UINT16 CapId + ) +{ + UINT16 CapHeaderOffset; + UINT16 CapHeaderId; + /// + /// Start to search at Offset 0x100 + /// Get Capability Header, A pointer value of 00h is used to indicate th= e last capability in the list. + /// + CapHeaderId =3D 0; + CapHeaderOffset =3D R_PCH_PCIE_CFG_EXCAP_OFFSET; + while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D MAX_UINT16) { + CapHeaderId =3D PciSegmentRead16 (DeviceBase + CapHeaderOffset); + if (CapHeaderId =3D=3D CapId) { + return CapHeaderOffset; + } + /// + /// Each capability must be DWORD aligned. + /// The bottom two bits of all pointers are reserved and must be imple= mented as 00b + /// although software must mask them to allow for future uses of these= bits. + /// + CapHeaderOffset =3D (PciSegmentRead16 (DeviceBase + CapHeaderOffset + = 2) >> 4) & ((UINT16) ~(BIT0 | BIT1)); + } + + return 0; +} + +/** + Search and return the offset of desired Pci Express Capability ID + CAPID list: + 0x0001 =3D Advanced Error Reporting Capability + 0x0002 =3D Virtual Channel Capability + 0x0003 =3D Device Serial Number Capability + 0x0004 =3D Power Budgeting Capability + + @param[in] Segment Pci Segment Number + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId Extended CAPID to search for + + @retval 0 CAPID not found, this includes situation= where device doesn't exist + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT16 +PcieFindExtendedCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT16 CapId + ) +{ + UINT64 DeviceBase; + + DeviceBase =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, = 0); + return PcieBaseFindExtendedCapId (DeviceBase, CapId); +} + +/** + This function checks whether PHY lane power gating is enabled on the por= t. + + @param[in] RpBase Root Port base address + + @retval TRUE PHY power gating is enabled + @retval FALSE PHY power gating disabled +**/ +STATIC +BOOLEAN +PcieIsPhyLanePgEnabled ( + IN UINT64 RpBase + ) +{ + UINT32 Data32; + Data32 =3D PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_PCIEPMECTL); + return (Data32 & B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE) !=3D 0; +} + +/** + Get current PCIe link speed. + + @param[in] RpBase Root Port base address + @retval Link speed +**/ +UINT32 +GetLinkSpeed ( + UINT64 RpBase + ) +{ + return PciSegmentRead16 (RpBase + R_PCH_PCIE_CFG_LSTS) & B_PCIE_LSTS_CLS; +} + +/** + Get max PCIe link speed supported by the root port. + + @param[in] RpBase Root Port base address + @retval Max link speed +**/ +UINT32 +GetMaxLinkSpeed ( + UINT64 RpBase + ) +{ + return PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_LCAP) & B_PCIE_LCAP_MLS; +} + +/** + Get max payload size supported by device. + + @param[in] Sbdf device's segment:bus:device:function coordinates + @retval Max payload size, encoded in the same way as in register (0= =3D128b, 1=3D256b, etc) +**/ +STATIC +UINT8 +GetMps ( + SBDF Sbdf + ) +{ + return (PciSegmentRead16 (SbdfToBase (Sbdf) + Sbdf.PcieCap + R_PCIE_DCAP= _OFFSET) & B_PCIE_DCAP_MPS); +} + +/** + Sets Maximum Payload Size to be used by device + + @param[in] Sbdf device's segment:bus:device:function coordinates + @param[in] Mps Max payload size, encoded in the same way as in regist= er (0=3D128b, 1=3D256b, etc) +**/ +STATIC +VOID +SetMps ( + SBDF Sbdf, + UINT8 Mps + ) +{ + PciSegmentAndThenOr16 (SbdfToBase (Sbdf) + Sbdf.PcieCap + R_PCIE_DCTL_OF= FSET, (UINT16) ~B_PCIE_DCTL_MPS, Mps << N_PCIE_DCTL_MPS); +} + +/** + Checks if given PCI device is capable of Latency Tolerance Reporting + + @param[in] Sbdf device's segment:bus:device:function coordina= tes + + @retval TRUE if yes +**/ +STATIC +BOOLEAN +IsLtrCapable ( + SBDF Sbdf + ) +{ + if (Sbdf.PcieCap =3D=3D 0) { + return FALSE; + } + return !!(PciSegmentRead32 (SbdfToBase (Sbdf) + Sbdf.PcieCap + R_PCIE_DC= AP2_OFFSET) & B_PCIE_DCAP2_LTRMS); +} + +/** + Enables LTR feature in given device + + @param[in] Sbdf device's segment:bus:device:function coordina= tes +**/ +STATIC +VOID +EnableLtr ( + SBDF Sbdf + ) +{ + if (Sbdf.PcieCap =3D=3D 0) { + return; + } + PciSegmentOr32 (SbdfToBase (Sbdf) + Sbdf.PcieCap + R_PCIE_DCTL2_OFFSET, = B_PCIE_DCTL2_LTREN); +} + +/** + Checks if PCI device at given address exists + + @param[in] Base device's base address + + @retval TRUE if exists +**/ +BOOLEAN +IsDevicePresent ( + UINT64 Base + ) +{ + if (PciSegmentRead16 (Base) =3D=3D 0xFFFF) { + return FALSE; + } + return TRUE; +} + +/** + Returns information about type of device. + + @param[out] Sbdf device's segment:bus:device:function coordin= ates + @retval one of: not a PCIe device (legacy PCI), PCIe endpoint, PCIe = upstream port or PCIe downstream port (including rootport) +**/ +STATIC +PCI_DEV_TYPE +GetDeviceType ( + SBDF Sbdf + ) +{ + UINT8 DeviceType; + + if (Sbdf.PcieCap =3D=3D 0) { + return DevTypePci; + } + DeviceType =3D (UINT8) ((PciSegmentRead16 (SbdfToBase (Sbdf) + Sbdf.Pcie= Cap + R_PCIE_XCAP_OFFSET) & B_PCIE_XCAP_DT) >> N_PCIE_XCAP_DT); + if (DeviceType =3D=3D PCIE_DEVICE_PORT_TYPE_UPSTREAM_PORT) { + return DevTypePcieUpstream; + } else if (DeviceType =3D=3D PCIE_DEVICE_PORT_TYPE_DOWNSTREAM_PORT || De= viceType =3D=3D PCIE_DEVICE_PORT_TYPE_ROOT_PORT) { + return DevTypePcieDownstream; + } else { + return DevTypePcieEndpoint; + } +} + +/** + Initializes Dev:Func numbers for use in FindNextPcieChild or FindNextLeg= alSbdf functions. + + @param[out] Sbdf device's segment:bus:device:function coordin= ates +**/ +STATIC +VOID +InitChildFinder ( + OUT SBDF *Sbdf + ) +{ + // + // Initialize Dev/Func to maximum values, so that when FindNextLegalSbdf= () + // is called on those input parameters, it will return 1st legal address= (Dev 0 Func 0). + // + Sbdf->Dev =3D PCI_MAX_DEVICE; + Sbdf->Func =3D PCI_MAX_FUNC; +} + +/** + Checks the device is a bridge and has non-zero secondary bus number assi= gned. + If so, it returns TRUE and initializes ChildSbdf with such values that + allow searching for devices on the secondary bus. + ChildSbdf will be mangled even if this function returns FALSE. + + Legal bus assignment is assumed. This function doesn't check subordinate= bus numbers of + the the device it was called on or any bridges between it and root compl= ex + + @param[in] Sbdf device's segment:bus:device:function coordinates + @param[out] ChildSbdf SBDF initialized in such way that calling FindNex= tPcieChild( ) on it will find all children devices + + @retval TRUE if device is a bridge and has a bus behind it; FALSE otherw= ise +**/ +STATIC +BOOLEAN +HasChildBus ( + SBDF Sbdf, + SBDF *ChildSbdf + ) +{ + UINT32 Data32; + UINT64 Base; + UINT8 SecondaryBus; + + ChildSbdf->Seg =3D Sbdf.Seg; + InitChildFinder (ChildSbdf); + + Base =3D SbdfToBase (Sbdf); + + if (PciSegmentRead8 (Base + R_PCI_BCC_OFFSET) !=3D PCI_CLASS_BRIDGE) { + DEBUG ((DEBUG_INFO, "HasChildBus%02:%02:%02: no\n", Sbdf.Bus, Sbdf.Dev= , Sbdf.Func)); + return FALSE; + } + Data32 =3D PciSegmentRead32 (Base + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFS= ET); + SecondaryBus =3D (UINT8)((Data32 & B_PCI_BRIDGE_BNUM_SCBN) >> 8); + ChildSbdf->Bus =3D SecondaryBus; + if (SecondaryBus =3D=3D 0) { + DEBUG ((DEBUG_INFO, "HasChildBus%02x:%02x:%02x: no\n", Sbdf.Bus, Sbdf.= Dev, Sbdf.Func)); + return FALSE; + } else { + DEBUG ((DEBUG_INFO, "HasChildBus%02x:%02x:%02x: yes, %x\n", Sbdf.Bus, = Sbdf.Dev, Sbdf.Func, SecondaryBus)); + return TRUE; + } +} + +/** + Checks if device is a multifunction device + Besides comparing Multifunction bit (BIT7) it checks if contents of HEAD= ER_TYPE register + make sense (header !=3D 0xFF) to prevent false positives when called on = devices which do not exist + + @param[in] Base device's base address + + @retval TRUE if multifunction; FALSE otherwise +**/ +BOOLEAN +IsMultifunctionDevice ( + UINT64 Base + ) +{ + UINT8 HeaderType; + HeaderType =3D PciSegmentRead8(Base + PCI_HEADER_TYPE_OFFSET); + if ((HeaderType =3D=3D 0xFF) || ((HeaderType & HEADER_TYPE_MULTI_FUNCTIO= N) =3D=3D 0)) { + return FALSE; + } + return TRUE; +} + +/** + Returns combination of two LTR override values + The resulting LTR override separately chooses stricter limits for snoop = and nosnoop + + @param[in] LtrA LTR override values to be combined + @param[in] LtrB LTR override values to be combined + + @retval LTR override value +**/ +STATIC +LTR_OVERRIDE +CombineLtr ( + LTR_OVERRIDE LtrA, + LTR_OVERRIDE LtrB + ) +{ + UINT64 DecodedLatencyA; + UINT64 DecodedLatencyB; + LTR_OVERRIDE Result; + static UINT32 ScaleEncoding [8] =3D {1, 32, 1024, 32768, 1048576, 335544= 32, 0, 0}; + + DecodedLatencyA =3D ScaleEncoding[LtrA.MaxSnoopLatencyScale] * LtrA.MaxS= noopLatencyValue; + DecodedLatencyB =3D ScaleEncoding[LtrB.MaxSnoopLatencyScale] * LtrB.MaxS= noopLatencyValue; + if ((!LtrB.MaxSnoopLatencyRequirement) || ((DecodedLatencyA < DecodedLat= encyB) && LtrA.MaxSnoopLatencyRequirement)) { + Result.MaxSnoopLatencyValue =3D LtrA.MaxSnoopLatencyValue; + Result.MaxSnoopLatencyScale =3D LtrA.MaxSnoopLatencyScale; + Result.MaxSnoopLatencyRequirement =3D LtrA.MaxSnoopLatencyRequirement; + } else { + Result.MaxSnoopLatencyValue =3D LtrB.MaxSnoopLatencyValue; + Result.MaxSnoopLatencyScale =3D LtrB.MaxSnoopLatencyScale; + Result.MaxSnoopLatencyRequirement =3D LtrB.MaxSnoopLatencyRequirement; + } + DecodedLatencyA =3D ScaleEncoding[LtrA.MaxNoSnoopLatencyScale] * LtrA.Ma= xNoSnoopLatencyValue; + DecodedLatencyB =3D ScaleEncoding[LtrB.MaxNoSnoopLatencyScale] * LtrB.Ma= xNoSnoopLatencyValue; + if ((!LtrB.MaxNoSnoopLatencyRequirement) || ((DecodedLatencyA < DecodedL= atencyB) && LtrA.MaxNoSnoopLatencyRequirement)) { + Result.MaxNoSnoopLatencyValue =3D LtrA.MaxNoSnoopLatencyValue; + Result.MaxNoSnoopLatencyScale =3D LtrA.MaxNoSnoopLatencyScale; + Result.MaxNoSnoopLatencyRequirement =3D LtrA.MaxNoSnoopLatencyRequirem= ent; + } else { + Result.MaxNoSnoopLatencyValue =3D LtrB.MaxNoSnoopLatencyValue; + Result.MaxNoSnoopLatencyScale =3D LtrB.MaxNoSnoopLatencyScale; + Result.MaxNoSnoopLatencyRequirement =3D LtrB.MaxNoSnoopLatencyRequirem= ent; + } + Result.ForceOverride =3D FALSE; + if (LtrA.ForceOverride || LtrB.ForceOverride) { + Result.ForceOverride =3D TRUE; + } + DEBUG ((DEBUG_INFO, "CombineLtr: A(V%d S%d E%d : V%d S%d E%d, F%d)\n", + LtrA.MaxSnoopLatencyValue, LtrA.MaxSnoopLatencyScale, LtrA.MaxSnoopLat= encyRequirement, + LtrA.MaxNoSnoopLatencyValue, LtrA.MaxNoSnoopLatencyScale, LtrA.MaxNoSn= oopLatencyRequirement, + LtrA.ForceOverride + )); + DEBUG ((DEBUG_INFO, " : B(V%d S%d E%d : V%d S%d E%d, F%d)\n", + LtrB.MaxSnoopLatencyValue, LtrB.MaxSnoopLatencyScale, LtrB.MaxSnoopLat= encyRequirement, + LtrB.MaxNoSnoopLatencyValue, LtrB.MaxNoSnoopLatencyScale, LtrB.MaxNoSn= oopLatencyRequirement, + LtrB.ForceOverride + )); + DEBUG ((DEBUG_INFO, " : R(V%d S%d E%d : V%d S%d E%d, F%d)\n", + Result.MaxSnoopLatencyValue, Result.MaxSnoopLatencyScale, Result.MaxSn= oopLatencyRequirement, + Result.MaxNoSnoopLatencyValue, Result.MaxNoSnoopLatencyScale, Result.M= axNoSnoopLatencyRequirement, + Result.ForceOverride + )); + return Result; +} + +/** + Returns LTR override value for given device + The value is extracted from Device Override table. If the device is not = found, + the returned value will have Requirement bits clear + + @param[in] Base device's base address + @param[in] Override device override table + + @retval LTR override value +**/ +STATIC +LTR_OVERRIDE +GetOverrideLtr ( + UINT64 Base, + OVERRIDE_TABLE *Override + ) +{ + UINT16 DevId; + UINT16 VenId; + UINT16 RevId; + UINT32 Index; + LTR_OVERRIDE ReturnValue =3D {0}; + + VenId =3D PciSegmentRead16 (Base + PCI_VENDOR_ID_OFFSET); + DevId =3D PciSegmentRead16 (Base + PCI_DEVICE_ID_OFFSET); + RevId =3D PciSegmentRead16 (Base + PCI_REVISION_ID_OFFSET); + + for (Index =3D 0; Index < Override->Size; Index++) { + if (((Override->Table[Index].OverrideConfig & PchPcieLtrOverride) =3D= =3D PchPcieLtrOverride) && + (Override->Table[Index].VendorId =3D=3D VenId) && + ((Override->Table[Index].DeviceId =3D=3D DevId) || (Override->Tabl= e[Index].DeviceId =3D=3D 0xFFFF)) && + ((Override->Table[Index].RevId =3D=3D RevId) || (Override->Table[I= ndex].RevId =3D=3D 0xFF))) { + if (Override->Table[Index].SnoopLatency & 0x8000) { + ReturnValue.MaxSnoopLatencyRequirement =3D 1; + ReturnValue.MaxSnoopLatencyValue =3D Override->Table[Index].SnoopL= atency & 0x3FF; + ReturnValue.MaxSnoopLatencyScale =3D (Override->Table[Index].Snoop= Latency & 0x1C00) >> 10; + } + if (Override->Table[Index].NonSnoopLatency & 0x8000) { + ReturnValue.MaxNoSnoopLatencyRequirement =3D 1; + ReturnValue.MaxNoSnoopLatencyValue =3D Override->Table[Index].NonS= noopLatency & 0x3FF; + ReturnValue.MaxNoSnoopLatencyScale =3D (Override->Table[Index].Non= SnoopLatency & 0x1C00) >> 10; + } + ReturnValue.ForceOverride =3D Override->Table[Index].ForceLtrOverrid= e; + break; + } + } + return ReturnValue; +} + +/** + Sets LTR limit in a device. + + @param[in] Base device's base address + @param[in] Ltr LTR limit +**/ +STATIC +VOID +SetLtrLimit ( + UINT64 Base, + LTR_LIMIT Ltr + ) +{ + UINT16 LtrCapOffset; + UINT16 Data16; + + LtrCapOffset =3D PcieBaseFindExtendedCapId (Base, R_PCH_PCIE_LTRECH_CID); + if (LtrCapOffset =3D=3D 0) { + return; + } + Data16 =3D (UINT16)((Ltr.MaxSnoopLatencyValue << N_PCH_PCIE_LTRECH_MSLR_= VALUE) | (Ltr.MaxSnoopLatencyScale << N_PCH_PCIE_LTRECH_MSLR_SCALE)); + PciSegmentWrite16(Base + LtrCapOffset + R_PCH_PCIE_LTRECH_MSLR_OFFSET, D= ata16); + + Data16 =3D (UINT16)((Ltr.MaxNoSnoopLatencyValue << N_PCH_PCIE_LTRECH_MNS= LR_VALUE) | (Ltr.MaxNoSnoopLatencyScale << N_PCH_PCIE_LTRECH_MNSLR_SCALE)); + PciSegmentWrite16(Base + LtrCapOffset + R_PCH_PCIE_LTRECH_MNSLR_OFFSET, = Data16); +} + +/** + Checks if device at given address exists and is a PCI Express device. + PCI express devices are distinguished from PCI by having Capability ID 0= x10 + If the device is PCI express then its SDBF structure gets updated with p= ointer to + the PCIe Capability. This is an optimization feature. It greatly decreas= es the number + of bus accesses, since most features configured by this library depend o= n registers + whose location is relative to PCIe capability. + + @param[in,out] Sbdf on entry, segment:bus:device:function coordinates + on exit, PcieCap offset is updated + @retval TRUE when PCIe device exists; FALSE if it's not PC= Ie or there's no device at all +**/ +STATIC +BOOLEAN +IsPcieDevice ( + SBDF *Sbdf + ) +{ + UINT8 PcieCapOffset; + UINT64 Base; + + Base =3D SbdfToBase (*Sbdf); + + if (PciSegmentRead16 (Base) =3D=3D 0xFFFF) { + return FALSE; + } + + + PcieCapOffset =3D PcieBaseFindCapId (Base, EFI_PCI_CAPABILITY_ID_PCIEXP); + if (PcieCapOffset =3D=3D 0) { + DEBUG ((DEBUG_INFO, "IsPcieDevice %02x:%02x:%02x - legacy\n", Sbdf->Bu= s, Sbdf->Dev, Sbdf->Func)); + return FALSE; + } else { + Sbdf->PcieCap =3D PcieCapOffset; + DEBUG ((DEBUG_INFO, "IsPcieDevice %02x:%02x:%02x - yes\n", Sbdf->Bus, = Sbdf->Dev, Sbdf->Func)); + return TRUE; + } +} + +/** + Returns TRUE and Dev:Func numbers where a PCIe device could legally be l= ocated, or FALSE if there + no such coordinates left. + + Segment and Bus fields of SBDF structure are input only and determine wh= ich bus will be scanned. + This function should be called in a while() loop. It replaces the less e= fficient method of + using nested FOR loops that iterate over all device and function numbers= . It is optimized for + the amount of bus access. If function0 doesn't exist or doesn't have Mul= tifunction bit set, + then higher function numbers are skipped. If parent of this bus is a dow= nstream port, then + Device numbers 1-31 get skipped too (there can be only Dev0 behind downs= tream ports) + If device/function number =3D=3D 0x1F/0x7, this function returns first p= ossible address, that is 0:0 + Any other device number means Dev:Func contain address of last found chi= ld device + and this function should search for next one + + @param[in] ParentDevType type of bridge who's partent of this bus + @param[in,out] Sbdf On entry: location returned previously fro= m this function + Dev:Func value of 1F:07 means se= arch should start from the beginning + On exit: if legal Dev:Func combination wa= s found, that Dev:Func is returned + otherwise, Dev:Func are initiali= zed to 1F:07 for convenience + @retval TRUE when next legal Dev:Func address was found; FALSE otherwise +**/ +STATIC +BOOLEAN +FindNextLegalSbdf ( + IN PCI_DEV_TYPE ParentDevType, + IN OUT SBDF *Sbdf + ) +{ + UINT8 MaxDev; + UINT64 Func0Base; + + if (ParentDevType =3D=3D DevTypePcieEndpoint) { + return FALSE; + } + if (ParentDevType =3D=3D DevTypePcieUpstream) { + MaxDev =3D PCI_MAX_DEVICE; + } else { + MaxDev =3D 0; + } + Func0Base =3D PCI_SEGMENT_LIB_ADDRESS (Sbdf->Seg, Sbdf->Bus, Sbdf->Dev, = 0, 0); + if ((Sbdf->Dev =3D=3D PCI_MAX_DEVICE) && Sbdf->Func =3D=3D PCI_MAX_FUNC)= { + Sbdf->Dev =3D 0; + Sbdf->Func =3D 0; + return TRUE; + } else if ((Sbdf->Func =3D=3D PCI_MAX_FUNC) || (Sbdf->Func =3D=3D 0 && != IsMultifunctionDevice (Func0Base))) { + // + // if it's the last function of a device, then return Func0 of new devic= e or FALSE in case there are no more devices + // + if (Sbdf->Dev =3D=3D MaxDev) { + InitChildFinder (Sbdf); + return FALSE; + } + (Sbdf->Dev)++; + Sbdf->Func =3D 0; + return TRUE; + } else { + (Sbdf->Func)++; + return TRUE; + } +} + +/** + Finds next PCIe (not legacy PCI) device behind given device + If device/function number =3D=3D 0x1F/0x7, this function searches for ch= ildren from scratch + Any other device number means Dev:Func contain address of last found chi= ld device + and this function should search for next one + + @param[in] ParentDevType type of bridge who's partent of this bus + @param[in,out] Sbdf On entry: location returned previously fro= m this function + Dev:Func value of 0x1F:0x07 mean= s search should start from the beginning + On exit: if PCIe device was found, its SB= DF coordinates are returned + otherwise, Dev:Func are initiali= zed to 0x1F:0x07 for convenience + @retval TRUE when next PCIe device was found; FALSE otherwise +**/ +STATIC +BOOLEAN +FindNextPcieChild ( + IN PCI_DEV_TYPE ParentDevType, + IN OUT SBDF *Sbdf + ) +{ + while ( FindNextLegalSbdf (ParentDevType, Sbdf)) { + if (IsPcieDevice (Sbdf)) { + return TRUE; + } + } + return FALSE; +} + +/** + Checks device's Slot Clock Configuration + + @param[in] Base device's base address + + @retval TRUE when device uses slot clock, FALSE otherwise +**/ +BOOLEAN +GetScc ( + UINT64 Base, + UINT8 PcieCapOffset + ) +{ + return !!(PciSegmentRead16 (Base + PcieCapOffset + R_PCIE_LSTS_OFFSET) &= B_PCIE_LSTS_SCC); +} + +/** + Sets Common Clock Configuration bit for given device. + + @param[in] Base device's base address +**/ +VOID +EnableCcc ( + UINT64 Base, + UINT8 PcieCapOffset + ) +{ + PciSegmentOr8 (Base + PcieCapOffset + R_PCIE_LCTL_OFFSET, B_PCIE_LCTL_CC= C); +} + +/** + Retrains link behind given device. + It only makes sense to call it for downstream ports. If called for upstr= eam port nothing will happen. + If WaitUntilDone is TRUE function will wait until link retrain had finis= hed, otherwise it will return immediately. + Link must finish retrain before software can access the device on the ot= her side. If it's not going to access it + then considerable time can be saved by not waiting here. + + @param[in] Sbdf Device's Segment:Bus:Device:Function coordinat= es + @param[in] WaitUntilDone when TRUE, function waits until link has retra= ined +**/ +VOID +RetrainLink ( + UINT64 Base, + UINT8 PcieCapOffset, + BOOLEAN WaitUntilDone + ) +{ + UINT16 LinkTraining; + UINT32 TimeoutUs; + + TimeoutUs =3D LINK_RETRAIN_WAIT_TIME; + // + // Before triggering link retrain make sure it's not already retraining.= Otherwise + // settings recently entered in LCTL register might go unnoticed + // + do { + LinkTraining =3D (PciSegmentRead16 (Base + PcieCapOffset + R_PCIE_LSTS= _OFFSET) & B_PCIE_LSTS_LT); + TimeoutUs--; + } while (LinkTraining && (TimeoutUs !=3D 0)); + + PciSegmentOr8 (Base + PcieCapOffset + R_PCIE_LCTL_OFFSET, B_PCIE_LCTL_RL= ); + + TimeoutUs =3D LINK_RETRAIN_WAIT_TIME; + if (WaitUntilDone) { + do { + LinkTraining =3D (PciSegmentRead16 (Base + PcieCapOffset + R_PCIE_LS= TS_OFFSET) & B_PCIE_LSTS_LT); + TimeoutUs--; + } while (LinkTraining && (TimeoutUs !=3D 0)); + } +} + +/** + Checks if given device supports Clock Power Management + + @param[in] Sbdf segment:bus:device:function coordinates of a device + + @retval TRUE when device supports it, FALSE otherwise +**/ +STATIC +BOOLEAN +IsCpmSupported ( + SBDF Sbdf + ) +{ + return !!(PciSegmentRead32 (SbdfToBase (Sbdf) + Sbdf.PcieCap + R_PCIE_LC= AP_OFFSET) & B_PCIE_LCAP_CPM); +} + +/** + Sets Enable Clock Power Management bit for given device + + @param[in] Base device's base address +**/ +STATIC +VOID +EnableCpm ( + SBDF Sbdf + ) +{ + PciSegmentOr16 (SbdfToBase (Sbdf) + Sbdf.PcieCap + R_PCIE_LCTL_OFFSET, B= _PCIE_LCTL_ECPM); +} + +/** + Checks if given device is an IoAPIC + + @param[in] Base device's base address + + @retval TRUE if it's an IoAPIC +**/ +BOOLEAN +IsIoApicDevice ( + UINT64 Base + ) +{ + UINT8 BaseClassCode; + UINT8 SubClassCode; + UINT8 ProgInterface; + + BaseClassCode =3D PciSegmentRead8 (Base + PCI_CLASSCODE_OFFSET + 2); + SubClassCode =3D PciSegmentRead8 (Base + PCI_CLASSCODE_OFFSET + 1); + ProgInterface =3D PciSegmentRead8 (Base + PCI_CLASSCODE_OFFSET); + if ((BaseClassCode =3D=3D PCI_CLASS_SYSTEM_PERIPHERAL) && + (SubClassCode =3D=3D PCI_SUBCLASS_PIC) && + ((ProgInterface =3D=3D PCI_IF_APIC_CONTROLLER) || + (ProgInterface =3D=3D PCI_IF_APIC_CONTROLLER2))) { + return TRUE; + } + return FALSE; +} + +/** + There are some devices which support L1 substates, but due to silicon bu= gs the corresponding register + cannot be found by scanning PCIe capabilities. This function checks list= of such devices and if one + is found, returns its L1ss capability register offset + + @param[in] Base base address of device + @param[in] Override table of devices that need override + @retval offset to L1ss capability register +**/ +UINT16 +GetOverrideL1ssCapsOffset ( + UINT64 Base, + OVERRIDE_TABLE *Override + ) +{ + UINT16 DeviceId; + UINT16 VendorId; + UINT8 Revision; + UINT32 Index; + + VendorId =3D PciSegmentRead16 (Base + PCI_VENDOR_ID_OFFSET); + DeviceId =3D PciSegmentRead16 (Base + PCI_DEVICE_ID_OFFSET); + Revision =3D PciSegmentRead8 (Base + PCI_REVISION_ID_OFFSET); + + for (Index =3D 0; Index < Override->Size; Index++) { + if (((Override->Table[Index].OverrideConfig & PchPcieL1SubstatesOverri= de) =3D=3D PchPcieL1SubstatesOverride) && + (Override->Table[Index].VendorId =3D=3D VendorId) && + (Override->Table[Index].DeviceId =3D=3D DeviceId) && + (Override->Table[Index].RevId =3D=3D Revision || Override->Table[I= ndex].RevId =3D=3D 0xFF)) { + return Override->Table[Index].L1SubstatesCapOffset; + } + } + return 0; +} + +/** + There are some devices whose implementation of L1 substates is partially= broken. This function checks + list of such devices and if one is found, overrides their L1ss-related c= apabilities + + @param[in] Base base address of device + @param[in] Override table of devices that need override + @param[in,out] L1ss on entry, capabilities read from register; on = exit, capabilities modified according ot override table +**/ +STATIC +VOID +OverrideL1ssCaps ( + UINT64 Base, + OVERRIDE_TABLE *Override, + L1SS_CAPS *L1ss + ) +{ + UINT16 DeviceId; + UINT16 VendorId; + UINT8 Revision; + UINT32 Index; + + VendorId =3D PciSegmentRead16 (Base + PCI_VENDOR_ID_OFFSET); + DeviceId =3D PciSegmentRead16 (Base + PCI_DEVICE_ID_OFFSET); + Revision =3D PciSegmentRead8 (Base + PCI_REVISION_ID_OFFSET); + + for (Index =3D 0; Index < Override->Size; Index++) { + if (((Override->Table[Index].OverrideConfig & PchPcieL1SubstatesOverri= de) =3D=3D PchPcieL1SubstatesOverride) && + (Override->Table[Index].VendorId =3D=3D VendorId) && + (Override->Table[Index].DeviceId =3D=3D DeviceId) && + (Override->Table[Index].RevId =3D=3D Revision || Override->Table[I= ndex].RevId =3D=3D 0xFF)) { + L1ss->PmL12 &=3D !!(Override->Table[Index].L1SubstatesCapMask & B_= PCIE_EX_L1SCAP_PPL12S); + L1ss->PmL11 &=3D !!(Override->Table[Index].L1SubstatesCapMask & B_= PCIE_EX_L1SCAP_PPL11S); + L1ss->AspmL12 &=3D !!(Override->Table[Index].L1SubstatesCapMask & B_= PCIE_EX_L1SCAP_AL12S); + L1ss->AspmL11 &=3D !!(Override->Table[Index].L1SubstatesCapMask & B_= PCIE_EX_L1SCAP_AL1SS); + if (Override->Table[Index].L1sTpowerOnValue !=3D 0) { + L1ss->Cmrt =3D Override->Table[Index].L1sCommonModeRestoreTime; + L1ss->TpoScale =3D Override->Table[Index].L1sTpowerOnScale; + L1ss->TpoValue =3D Override->Table[Index].L1sTpowerOnValue; + } + return; + } + } +} + +/** + Returns L1 sub states capabilities of a device + + @param[in] Base base address of a device + + @retval L1SS_CAPS structure filled with device's capabilities +**/ +STATIC +L1SS_CAPS +GetL1ssCaps ( + UINT64 Base, + OVERRIDE_TABLE *Override + ) +{ + L1SS_CAPS Capabilities =3D {0}; + UINT16 PcieCapOffset; + UINT32 CapsRegister; + + PcieCapOffset =3D GetOverrideL1ssCapsOffset (Base, Override); + if (PcieCapOffset =3D=3D 0) { + PcieCapOffset =3D PcieBaseFindExtendedCapId (Base, V_PCIE_EX_L1S_CID); + } + if (PcieCapOffset =3D=3D 0) { + return Capabilities; + } + CapsRegister =3D PciSegmentRead32 (Base + PcieCapOffset + R_PCIE_EX_L1SC= AP_OFFSET); + if (CapsRegister & B_PCIE_EX_L1SCAP_L1PSS) { + Capabilities.PmL11 =3D !!(CapsRegister & B_PCIE_EX_L1SCAP_PPL11S); + Capabilities.PmL12 =3D !!(CapsRegister & B_PCIE_EX_L1SCAP_PPL12S); + Capabilities.AspmL12 =3D !!(CapsRegister & B_PCIE_EX_L1SCAP_AL12S); + Capabilities.AspmL11 =3D !!(CapsRegister & B_PCIE_EX_L1SCAP_AL1SS); + Capabilities.Cmrt =3D (CapsRegister & B_PCIE_EX_L1SCAP_CMRT) >> N_PCIE= _EX_L1SCAP_CMRT; + Capabilities.TpoValue =3D (CapsRegister & B_PCIE_EX_L1SCAP_PTV) >> N_P= CIE_EX_L1SCAP_PTV; + Capabilities.TpoScale =3D (CapsRegister & B_PCIE_EX_L1SCAP_PTPOS) >> N= _PCIE_EX_L1SCAP_PTPOS; + } + OverrideL1ssCaps (Base, Override, &Capabilities); + return Capabilities; +} + +/** + Returns combination of two sets of L1 substate capabilities + Given feature is supported by the link only if both sides support it + Time parameters for link (Cmrt and Tpo) depend on the bigger value betwe= en two sides + + @param[in] L1ssA L1 substate capabilities of first device + @param[in] L1ssB L1 substate capabilities of second device + + @retval Link's L1 substate capabilities +**/ +STATIC +L1SS_CAPS +CombineL1ss ( + L1SS_CAPS L1ssA, + L1SS_CAPS L1ssB + ) +{ + L1SS_CAPS Combined; + + Combined.PmL12 =3D L1ssA.PmL12 && L1ssB.PmL12; + Combined.PmL11 =3D L1ssA.PmL11 && L1ssB.PmL11; + Combined.AspmL12 =3D L1ssA.AspmL12 && L1ssB.AspmL12; + Combined.AspmL11 =3D L1ssA.AspmL11 && L1ssB.AspmL11; + Combined.Cmrt =3D MAX (L1ssA.Cmrt, L1ssB.Cmrt); + if (TpoToUs (L1ssA.TpoScale, L1ssA.TpoValue) > TpoToUs (L1ssB.TpoScale, = L1ssB.TpoValue)) { + Combined.TpoScale =3D L1ssA.TpoScale; + Combined.TpoValue =3D L1ssA.TpoValue; + } else { + Combined.TpoScale =3D L1ssB.TpoScale; + Combined.TpoValue =3D L1ssB.TpoValue; + } + return Combined; +} + +/** + Configures L1 substate feature in a device + + @param[in] Sbdf segment:bus:device:function coordinates of a device + @param[in] L1ss configuration to be programmed + @param[in] Override table of devices that require special handling +**/ +STATIC +VOID +SetL1ss ( + SBDF Sbdf, + L1SS_CAPS L1ss, + OVERRIDE_TABLE *Override + ) +{ + UINT16 PcieCapOffset; + UINT32 Ctrl1Register; + UINT32 Ctrl2Register; + UINT64 Base; + + Base =3D SbdfToBase(Sbdf); + Ctrl1Register =3D 0; + Ctrl2Register =3D 0; + + PcieCapOffset =3D GetOverrideL1ssCapsOffset (Base, Override); + if (PcieCapOffset =3D=3D 0) { + PcieCapOffset =3D PcieBaseFindExtendedCapId (Base, V_PCIE_EX_L1S_CID); + } + if (PcieCapOffset =3D=3D 0) { + return; + } + Ctrl1Register |=3D (L1ss.PmL12 ? B_PCIE_EX_L1SCAP_PPL12S : 0); + Ctrl1Register |=3D (L1ss.PmL11 ? B_PCIE_EX_L1SCAP_PPL11S : 0); + Ctrl1Register |=3D (L1ss.AspmL12 ? B_PCIE_EX_L1SCAP_AL12S : 0); + Ctrl1Register |=3D (L1ss.AspmL11 ? B_PCIE_EX_L1SCAP_AL1SS : 0); + if (GetDeviceType (Sbdf) =3D=3D DevTypePcieDownstream) { + Ctrl1Register |=3D (L1ss.Cmrt << N_PCIE_EX_L1SCAP_CMRT); + } + /// + /// Set L1.2 LTR threshold to 80us (value =3D 0x50, scale =3D 0x2 =3D 1= 024ns), in accordance to BWG + /// BUG BUG BUG It shouldn't be hardcoded, it should consider Tpoweron= , otherwise we risk situation where + /// BUG BUG BUG threshold is lower than Tpo, and every L1 entry turns = into L1.2 entry with no possibility + /// BUG BUG BUG to exit before LTR elapses, because exit can take no l= ess than Tpo + /// + Ctrl1Register |=3D (0x50 << N_PCIE_EX_L1SCTL1_L12LTRTLV); + Ctrl1Register |=3D (2 << N_PCIE_EX_L1SCTL1_L12LTRTLSV); + + Ctrl2Register |=3D (L1ss.TpoScale); + Ctrl2Register |=3D (L1ss.TpoValue << N_PCIE_EX_L1SCTL2_POWT); + + PciSegmentWrite32 (Base + PcieCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, 0); + PciSegmentWrite32 (Base + PcieCapOffset + R_PCIE_EX_L1SCTL2_OFFSET, Ctrl= 2Register); + PciSegmentWrite32 (Base + PcieCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, Ctrl= 1Register); +} + +/** + Converts L1 latency from enumerated register value to microseconds + + @param[in] L1Latency latency value retrieved from register; see PCIE= specification for encoding + @retval L1 latency converted to microseconds +**/ +UINT32 +L1LatencyToUs ( + UINT32 L1Latency + ) +{ + if (L1Latency < 7) { + return 1 * (BIT0 << L1Latency); + } else { + return ASPM_L1_NO_LIMIT; + } +} + +/** + Modifies L1 latency by provided value + + @param[in] Aspm Structure that contains ASPM capabilities of a link,= including L1 acceptable latency + @param[in] Value Value, in microseconds, to be added to L1 acceptable= latency. Can be negative. + @retval Aspm structure with modified L1 acceptable latency +**/ +STATIC +ASPM_CAPS +PatchL1AcceptableLatency ( + ASPM_CAPS Aspm, + INT8 Value + ) +{ + if (Aspm.L1AcceptableLatencyUs !=3D ASPM_L1_NO_LIMIT) { + if (Value > 0) { + Aspm.L1AcceptableLatencyUs +=3D Value; + } else { + if (Aspm.L1AcceptableLatencyUs > (UINT32)(-1*Value)) { + Aspm.L1AcceptableLatencyUs =3D Aspm.L1AcceptableLatencyUs + Value; + } else { + Aspm.L1AcceptableLatencyUs =3D 0; + } + } + } + return Aspm; +} + +/** + Reads ASPM capabilities of a device + + @param[in] Sbdf segment:bus:device:function coordinates of a device + +@retval structure containing device's ASPM capabilities +**/ +STATIC +ASPM_CAPS +GetAspmCaps ( + SBDF Sbdf + ) +{ + + UINT32 LinkCapRegister; + UINT32 DevCapRegister; + UINT64 Base; + ASPM_CAPS Aspm =3D {0}; + + Base =3D SbdfToBase (Sbdf); + + LinkCapRegister =3D PciSegmentRead32 (Base + Sbdf.PcieCap + R_PCIE_LCAP_= OFFSET); + DevCapRegister =3D PciSegmentRead32 (Base + Sbdf.PcieCap + R_PCIE_DCAP_O= FFSET); + + /// + /// Check endpoint for pre-1.1 devices based on the Role based Error Rep= orting Capability bit. Don't report L0s support for old devices + /// + if (DevCapRegister & B_PCIE_DCAP_RBER) { + Aspm.L0sSupported =3D !!(LinkCapRegister & B_PCIE_LCAP_APMS_L0S); + } + Aspm.L1Supported =3D !!(LinkCapRegister & B_PCIE_LCAP_APMS_L1); + + Aspm.LinkL0sExitLatency =3D (LinkCapRegister & B_PCIE_LCAP_EL0) >> N_PCI= E_LCAP_EL0; + Aspm.LinkL1ExitLatencyUs =3D L1LatencyToUs( (LinkCapRegister & B_PCIE_LC= AP_EL1) >> N_PCIE_LCAP_EL1); + + if (GetDeviceType (Sbdf) =3D=3D DevTypePcieEndpoint) { + Aspm.L0sAcceptableLatency =3D (DevCapRegister & B_PCIE_DCAP_E0AL) >> N= _PCIE_DCAP_E0AL; + Aspm.L1AcceptableLatencyUs =3D L1LatencyToUs( (DevCapRegister & B_PCIE= _DCAP_E1AL) >> N_PCIE_DCAP_E1AL); + DEBUG ((DEBUG_INFO, "GetAspmCaps %02x:%02x:%02x L0s%c %d:%d L1%c %d:%d= \n", Sbdf.Bus, Sbdf.Dev, Sbdf.Func, + = Aspm.L0sSupported?'+':'-', Aspm.LinkL0sExitLatency, Aspm.L0sAcceptableLate= ncy, + = Aspm.L1Supported?'+':'-', Aspm.LinkL1ExitLatencyUs, Aspm.L1AcceptableLaten= cyUs)); + } else { + Aspm.L0sAcceptableLatency =3D ASPM_L0s_NO_LIMIT; + Aspm.L1AcceptableLatencyUs =3D ASPM_L1_NO_LIMIT; + DEBUG ((DEBUG_INFO, "GetAspmCaps %02x:%02x:%02x L0s%c %d:x L1%c %d:x\n= ", Sbdf.Bus, Sbdf.Dev, Sbdf.Func, + = Aspm.L0sSupported?'+':'-', Aspm.LinkL0sExitLatency, + = Aspm.L1Supported?'+':'-', Aspm.LinkL1ExitLatencyUs)); + } + return Aspm; +} + +/** + Get ASPM L0s and L1 override of given device. + + @param[in] Sbdf Segment,Bus,Device,Function address of cu= rrently visited PCIe device + @param[in,out] MyAspm Current device's ASPM capabilities struct= ure + @param[in] Override Pch Pcie devices OverrideTable +**/ +STATIC +VOID +GetOverrideAspm ( + SBDF Sbdf, + ASPM_CAPS *MyAspm, + OVERRIDE_TABLE *Override + ) +{ + UINT16 DeviceId; + UINT16 VendorId; + UINT8 Revision; + UINT32 Index; + UINT64 Base; + + Base =3D SbdfToBase (Sbdf); + + VendorId =3D PciSegmentRead16 (Base + PCI_VENDOR_ID_OFFSET); + DeviceId =3D PciSegmentRead16 (Base + PCI_DEVICE_ID_OFFSET); + Revision =3D PciSegmentRead8 (Base + PCI_REVISION_ID_OFFSET); + + for (Index =3D 0; Index < Override->Size; Index++) { + if (((Override->Table[Index].OverrideConfig & PchPcieL1L2Override) =3D= =3D PchPcieL1L2Override) && + (Override->Table[Index].VendorId =3D=3D VendorId) && + (Override->Table[Index].DeviceId =3D=3D DeviceId) && + (Override->Table[Index].RevId =3D=3D Revision || Override->Table[I= ndex].RevId =3D=3D 0xFF)) { + DEBUG ((DEBUG_INFO, "GetOverrideAspm %02x:%02x:%02x, original L0sSup= ported =3D 0x%x, L1Supported =3D 0x%x\n", + Sbdf.Bus, Sbdf.Dev, Sbdf.Func, MyAspm->L0sSupported, MyAspm-= >L1Supported)); + if (MyAspm->L0sSupported) { + // + // If L0s is supported in capability, apply platform override. + // + MyAspm->L0sSupported =3D Override->Table[Index].EndPointAspm & BIT= 0; + } + if (MyAspm->L1Supported) { + // + // If L1 is supported in capability, apply platform override. + // + MyAspm->L1Supported =3D (Override->Table[Index].EndPointAspm & BIT= 1) >> 1; + } + DEBUG ((DEBUG_INFO, "GetOverrideAspm %02x:%02x:%02x, override L0sSup= ported =3D 0x%x, L1Supported =3D 0x%x\n", + Sbdf.Bus, Sbdf.Dev, Sbdf.Func, MyAspm->L0sSupported, MyAspm-= >L1Supported)); + } + } +} + +/** + Combines ASPM capabilities of two devices on both ends of a link to dete= rmine link's ASPM capabilities + + @param[in] AspmA, AspmB ASPM capabilities of two devices + +@retval ASPM_CAPS structure containing combined ASPM capabilities +**/ +STATIC +ASPM_CAPS +CombineAspm ( + ASPM_CAPS AspmA, + ASPM_CAPS AspmB, + BOOLEAN DownstreamPort + ) +{ + ASPM_CAPS Combined; + + if (DownstreamPort) { + // + // When combining ASPM in downstream ports, combination must reflect s= tate of link just below + // and consider all acceptable latencies of all endpoints anywhere dow= n below that port + // + Combined.L0sSupported =3D AspmA.L0sSupported & AspmB.L0sSupported; + Combined.L1Supported =3D AspmA.L1Supported & AspmB.L1Supported; + Combined.LinkL0sExitLatency =3D MAX (AspmA.LinkL0sExitLatency, AspmB.L= inkL0sExitLatency); + Combined.LinkL1ExitLatencyUs =3D MAX (AspmA.LinkL1ExitLatencyUs, AspmB= .LinkL1ExitLatencyUs); + Combined.L0sAcceptableLatency =3D MIN (AspmA.L0sAcceptableLatency, Asp= mB.L0sAcceptableLatency); + Combined.L1AcceptableLatencyUs =3D MIN (AspmA.L1AcceptableLatencyUs, A= spmB.L1AcceptableLatencyUs); + } else { + // + // When combining ASPM in switch upstream ports, + // Supported and ExitLatency must only reflect capabilities of upstrea= m port itself + // But acceptable latencies must consider all endpoints anywhere below + // + Combined.L0sSupported =3D AspmA.L0sSupported; + Combined.L1Supported =3D AspmA.L1Supported; + Combined.LinkL0sExitLatency =3D AspmA.LinkL0sExitLatency; + Combined.LinkL1ExitLatencyUs =3D AspmA.LinkL1ExitLatencyUs; + Combined.L0sAcceptableLatency =3D MIN (AspmA.L0sAcceptableLatency, Asp= mB.L0sAcceptableLatency); + Combined.L1AcceptableLatencyUs =3D MIN (AspmA.L1AcceptableLatencyUs, A= spmB.L1AcceptableLatencyUs); + } + DEBUG ((DEBUG_INFO, "CombineAspm %x:%x -> %x\n", AspmA.L1AcceptableLaten= cyUs, AspmB.L1AcceptableLatencyUs, Combined.L1AcceptableLatencyUs)); + return Combined; +} + +/** + Checks if L1 can be enabled on given link, according to ASPM parameters = of that link + + @param[in] Aspm set of parameters describing this link and en= dpoint devices below it + @retval TRUE if L1 can be enabled +**/ +STATIC +BOOLEAN +IsL1Allowed ( + ASPM_CAPS Aspm + ) +{ + return (Aspm.L1Supported && (Aspm.L1AcceptableLatencyUs >=3D Aspm.LinkL1= ExitLatencyUs)); +} + +/** + Checks if L0s can be enabled on given link, according to ASPM parameters= of that link + + @param[in] Aspm set of parameters describing this link and en= dpoint devices below it + @retval TRUE if L0s can be enabled +**/ +STATIC +BOOLEAN +IsL0sAllowed ( + ASPM_CAPS Aspm + ) +{ + return (Aspm.L0sSupported && (Aspm.L0sAcceptableLatency >=3D Aspm.LinkL0= sExitLatency)); +} + +/** + Enables L0s and L1 for given port, if possible. + L0s/L1 can be enabled if it's supported on both sides of a link and if l= ink's latency doesn't exceed + acceptable latency of any endpoint below this link + + @param[in] Base device's base address + @param[in] Aspm set of parameters describing this link and en= dpoint devices below it +**/ +STATIC +VOID +SetAspm ( + SBDF Sbdf, + ASPM_CAPS Aspm + ) +{ + UINT16 DataOr; + + DataOr =3D 0; + if (IsL0sAllowed (Aspm)) { + DataOr |=3D V_PCIE_LCTL_ASPM_L0S; + } + if (IsL1Allowed (Aspm)) { + DataOr |=3D V_PCIE_LCTL_ASPM_L1; + } + DEBUG ((DEBUG_INFO, "SetAspm on %02x:%02x:%02x to %d\n", Sbdf.Bus,Sbdf.D= ev,Sbdf.Func, DataOr)); + PciSegmentAndThenOr16 (SbdfToBase (Sbdf) + Sbdf.PcieCap + R_PCIE_LCTL_OF= FSET, (UINT16)~B_PCIE_LCTL_ASPM, DataOr); +} + +/** + Adds device entry to a list of devices. + + @param[in,out] Table array of devices + @param[in] Sbdf segment:bus:device:function coordinates of devic= e to be added to table +**/ +STATIC +VOID +AddToDeviceTable ( + SBDF_TABLE *Table, + SBDF Sbdf + ) +{ + if (Table->Count < MAX_SBDF_TABLE_SIZE) { + Table->Entry[Table->Count++] =3D Sbdf; + } else { + ASSERT (FALSE); + } +} + +/** + Remove device entry from a list and clear its bus assignment + + @param[in,out] Table array of devices +**/ +STATIC +VOID +ClearBusFromTable ( + SBDF_TABLE *Table + ) +{ + while (Table->Count > 0) { + PciSegmentWrite32 (SbdfToBase (Table->Entry[Table->Count - 1]) + PCI_B= RIDGE_PRIMARY_BUS_REGISTER_OFFSET, 0); + Table->Count--; + } +} + +/** + Attempts to assign secondary and subordinate bus numbers to uninitialize= d bridges in PCIe tree + If the device is a bridge and already has bus numbers assigned, they won= 't be changed + Otherwise new bus number will be assigned below this bridge. + This function can be called from SMM, where BIOS must not modify bus num= bers to prevent + conflict with OS enumerator. To prevent this, this function returns list= of bridges whose + bus numbers were changed. All devices from that list must have buses cle= ared afterwards. + + @param[in] Sbdf segment:bus:device:function coordinates o= f device to be added to table + @param[in] MinBus minimum Bus number that can be assigned b= elow this port + @param[in] MaxBus maximum Bus number that can be assigned b= elow this port + @param[in] BridgeCleanupList list of bridges where bus numbers were mo= dified + + @retval maximum bus number assigned anywhere below this device +**/ +STATIC +UINT8 +RecursiveBusAssignment ( + SBDF Sbdf, + UINT8 MinBus, + UINT8 MaxBus, + SBDF_TABLE *BridgeCleanupList + ) +{ + UINT64 Base; + SBDF ChildSbdf; + PCI_DEV_TYPE DevType; + UINT32 Data32; + UINT8 BelowBus; + UINT8 SecondaryBus; + UINT8 SubordinateBus; + + ChildSbdf.Seg =3D Sbdf.Seg; + InitChildFinder (&ChildSbdf); + Base =3D SbdfToBase (Sbdf); + + // + // On way down: + // assign secondary bus, then increase it by one before stepping down;= temporarily assign max subordinate bus + // On way up: + // fix subordinate bus assignment to equal max bus number assigned any= where below; return that number + // + DevType =3D GetDeviceType (Sbdf); + if ((Sbdf.Bus >=3D MaxBus) || (DevType =3D=3D DevTypePcieEndpoint) || (D= evType =3D=3D DevTypePci)) { + return (UINT8) Sbdf.Bus; + } else { + Data32 =3D PciSegmentRead32 (Base + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OF= FSET); + SecondaryBus =3D (UINT8)((Data32 & B_PCI_BRIDGE_BNUM_SCBN) >> 8); + SubordinateBus =3D (UINT8)((Data32 & B_PCI_BRIDGE_BNUM_SBBN) >> 16); + if (SecondaryBus !=3D 0) { + ChildSbdf.Bus =3D SecondaryBus; + MinBus =3D SecondaryBus + 1; + DEBUG ((DEBUG_INFO, "RecursiveBusAssignmentP %x:%x:%x -> %x,%x,%x \n= ", Sbdf.Bus, Sbdf.Dev, Sbdf.Func, Sbdf.Bus, MinBus, SubordinateBus)); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + BelowBus =3D RecursiveBusAssignment (ChildSbdf, MinBus, Subordinat= eBus, BridgeCleanupList); + MinBus =3D BelowBus + 1; + } + return SubordinateBus; + } else { + Data32 =3D Sbdf.Bus + (MinBus << 8) + (MaxBus << 16); + PciSegmentWrite32(Base + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, Dat= a32); + AddToDeviceTable (BridgeCleanupList, Sbdf); + DEBUG ((DEBUG_INFO, "RecursiveBusAssignmentE %x:%x:%x -> %x,%x,%x \n= ", Sbdf.Bus, Sbdf.Dev, Sbdf.Func, Sbdf.Bus, MinBus, MaxBus)); + BelowBus =3D MinBus; + ChildSbdf.Bus =3D MinBus; + MinBus++; + while (FindNextPcieChild (DevType, &ChildSbdf)) { + BelowBus =3D RecursiveBusAssignment (ChildSbdf, MinBus, MaxBus, Br= idgeCleanupList); + MinBus =3D BelowBus + 1; + } + Data32 &=3D ~B_PCI_BRIDGE_BNUM_SBBN; + Data32 |=3D (BelowBus << 16); + PciSegmentWrite32 (Base + PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET, Da= ta32); + DEBUG ((DEBUG_INFO, "RecursiveBusAssignmentL %x:%x:%x -> %x,%x,%x \n= ", Sbdf.Bus, Sbdf.Dev, Sbdf.Func, Sbdf.Bus, (Data32&0xFF00)>>8, BelowBus)); + return BelowBus; + } + } +} + +/** + Enables L0s and/or L1 for PCIE links in the hierarchy below + L0s/L1 can be enabled when both sides of a link support it and link late= ncy is smaller than acceptable latency + ASPM of a given link is independend from any other link (except 1ms L1 a= djustment, read below), so it's possible to + have a hierarchy when RP link has no ASPM but links below do. + + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + @param[in] Depth How many links there are betwe= en this port and root complex + @param[in] Override Pch Pcie devices OverrideTable + + @retval structure that describes acceptable latencies of all endpoints b= elow plus ASPM parameters of last link +**/ +STATIC +ASPM_CAPS +RecursiveAspmConfiguration ( + SBDF Sbdf, + UINT8 Depth, + OVERRIDE_TABLE *Override + ) +{ + SBDF ChildSbdf; + ASPM_CAPS MyAspm; + ASPM_CAPS ChildAspm; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveAspmConfiguration %x:%x:%x\n", Sbdf.Bus, S= bdf.Dev, Sbdf.Func)); + + // + // On way down: + // pass number of links traversed; increase it per upstream port visit= ed (not endpoint) + // On way up: + // EndPoint: read Acceptable Latencies; subtract Depth From L1Acceptab= leLat to account for "1us per switch additional delay" + // Downstreamport: AND L0s/L1 caps; calculate LinkLatency; enable L0s/= L1 if supported and if acceptable latency is bigger than link latency; + // if L1 not enabled, add back 1us to Acceptable Latency to cancel e= arlier Depth subtraction + // UpstreamPort: calculate minimum of below Acceptable Latencies; retu= rn that, with upper link's Latency and L0s/L1 support + // + DevType =3D GetDeviceType(Sbdf); + if (DevType =3D=3D DevTypePcieUpstream) { + Depth++; + } + MyAspm =3D GetAspmCaps (Sbdf); + // + // Get ASPM L0s and L1 override + // + GetOverrideAspm (Sbdf, &MyAspm, Override); + if (DevType =3D=3D DevTypePcieEndpoint) { + // + // Every switch between endpoint and CPU introduces 1us additional lat= ency on L1 exit. This is reflected by + // subtracting 1us per switch from endpoint's acceptable L1 latency. + // In case L1 doesn't get enabled in one of switches, that 1us will be= added back. + // This calculation is not precise. It ignores that some switches' add= ed delay may be shadowed by + // other links' exit latency. But it guarantees that acceptable latenc= y won't be exceeded and is simple + // enough to perform in a single iteration without backtracking. + // + return PatchL1AcceptableLatency (MyAspm, (-1 * Depth)); + } + if (HasChildBus (Sbdf, &ChildSbdf)) { + while (FindNextPcieChild (DevType, &ChildSbdf)) { + ChildAspm =3D RecursiveAspmConfiguration (ChildSbdf, Depth, Override= ); + MyAspm =3D CombineAspm (MyAspm, ChildAspm, (DevType =3D=3D DevTypePc= ieDownstream)); + } + if (DevType =3D=3D DevTypePcieDownstream) { + SetAspm (Sbdf, MyAspm); + // + // ASPM config must be consistent across all functions of a device. = That's why there's while loop. + // + while (FindNextPcieChild (DevType, &ChildSbdf)) { + SetAspm (ChildSbdf, MyAspm); + } + if (!IsL1Allowed (MyAspm)) { + MyAspm =3D PatchL1AcceptableLatency (MyAspm, 1); + } + } + } + return MyAspm; +} + +/** + Enables L1 substates for PCIE links in the hierarchy below + L1.1 / L1.2 can be enabled if both sides of a link support it. + + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + + @retval structure that describes L1ss capabilities of the device +**/ +STATIC +L1SS_CAPS +RecursiveL1ssConfiguration ( + SBDF Sbdf, + OVERRIDE_TABLE *Override + ) +{ + UINT64 Base; + SBDF ChildSbdf; + L1SS_CAPS CombinedCaps; + L1SS_CAPS ChildCaps; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveL1ssConfiguration %x:%x:%x\n", Sbdf.Bus, S= bdf.Dev, Sbdf.Func)); + + Base =3D SbdfToBase (Sbdf); + // + // On way down: + // do nothing + // On way up: + // In downstream ports, combine L1ss capabilities of that port and dev= ice behind it, then enable L1.1 and/or L1.2 if possible + // Return L1ss capabilities + // + if (HasChildBus (Sbdf, &ChildSbdf)) { + DevType =3D GetDeviceType (Sbdf); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + ChildCaps =3D RecursiveL1ssConfiguration (ChildSbdf, Override); + if (DevType =3D=3D DevTypePcieDownstream && ChildSbdf.Func =3D=3D 0)= { + CombinedCaps =3D CombineL1ss (GetL1ssCaps (Base, Override), ChildC= aps); + SetL1ss (Sbdf, CombinedCaps, Override); + SetL1ss (ChildSbdf, CombinedCaps, Override); + } + } + } + return GetL1ssCaps (Base, Override); +} + +/** + Checks if there is an IoAPIC device in the PCIe hierarchy. + If one is found, this function doesn't check for more and returns + + @param[in] BusLimit maximum Bus number that can be= assigned below this port + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + + @retval TRUE if IoAPIC device was found +**/ +STATIC +BOOLEAN +RecursiveIoApicCheck ( + SBDF Sbdf + ) +{ + SBDF ChildSbdf; + UINT8 IoApicPresent; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveIoApicCheck %x:%x:%x\n", Sbdf.Bus, Sbdf.De= v, Sbdf.Func)); + + IoApicPresent =3D FALSE; + + if (IsIoApicDevice (SbdfToBase (Sbdf))) { + DEBUG ((DEBUG_INFO, "IoApicFound @%x:%x:%x:%x\n", Sbdf.Bus, Sbdf.Dev, = Sbdf.Func)); + return TRUE; + } + if (HasChildBus (Sbdf, &ChildSbdf)) { + DevType =3D GetDeviceType (Sbdf); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + IoApicPresent =3D RecursiveIoApicCheck (ChildSbdf); + if (IoApicPresent) { + break; + } + } + } + DEBUG ((DEBUG_INFO, "IoApic status %d @%x:%x:%x:%x\n", IoApicPresent, Sb= df.Seg, Sbdf.Bus, Sbdf.Dev, Sbdf.Func)); + return IoApicPresent; +} + +/** + Calculates Maximum Payload Size supported by PCIe hierarchy. + Starting from a device, it finds the minimum MPS supported by devices be= low it. + There are many valid strategies for setting MPS. This implementation cho= oses + one that is safest, but doesn't guarantee maximum performance: + Find minimum MPS under given rootport, then program that minimum value= everywhere below that rootport + + @param[in] BusLimit maximum Bus number that can be= assigned below this port + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + + @retval MPS supported by PCIe hierarchy, calculated as MIN(MPS of all d= evices below) +**/ +STATIC +UINT8 +RecursiveMpsCheck ( + SBDF Sbdf + ) +{ + SBDF ChildSbdf; + UINT8 MyMps; + UINT8 SubtreeMps; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveMpsCheck %x:%x:%x\n", Sbdf.Bus, Sbdf.Dev, = Sbdf.Func)); + + MyMps =3D GetMps (Sbdf); + if (MyMps =3D=3D 0) { + return MyMps; + } + if (HasChildBus (Sbdf, &ChildSbdf)) { + DevType =3D GetDeviceType (Sbdf); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + SubtreeMps =3D RecursiveMpsCheck (ChildSbdf); + MyMps =3D MIN(MyMps, SubtreeMps); + } + } + return MyMps; +} + +/** + Sets Maximum Payload Size in PCIe hierarchy. + Starting from a device, it programs the same MPS value to it and all dev= ices below it. + There are many valid strategies for setting MPS. This implementation cho= oses + one that is safest, but doesn't guarantee maximum performance: + Find minimum MPS under given rootport, then program that minimum value= everywhere below that rootport + + @param[in] BusLimit maximum Bus number that can be= assigned below this port + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + @param[in] Mps Maximum Payload Size to be pro= grammed +**/ +STATIC +VOID +RecursiveMpsConfiguration ( + SBDF Sbdf, + UINT8 Mps + ) +{ + SBDF ChildSbdf; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveMpsConfiguration %x:%x:%x\n", Sbdf.Bus, Sb= df.Dev, Sbdf.Func)); + + if (HasChildBus (Sbdf, &ChildSbdf)) { + DevType =3D GetDeviceType (Sbdf); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + RecursiveMpsConfiguration (ChildSbdf, Mps); + } + } + SetMps (Sbdf, Mps); +} + +/** + Sets Enable Clock Power Management bit for devices that support it. + A device supports CPM only if all function of this device report CPM sup= port. + Downstream ports never report CPM capability, so it's only relevant for = upstream ports. + When this function executes on upstream component, it will check CPM & s= et ECPM of downstream component + When this function executes on downstream component, all devices below i= t are guaranteed to + return CPM=3D0 so it will do nothing + + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + + @retval TRUE =3D this device supports CPM, FALSE =3D it doesn't +**/ +STATIC +BOOLEAN +RecursiveCpmConfiguration ( + SBDF Sbdf + ) +{ + SBDF ChildSbdf; + BOOLEAN ChildCpm; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveCpmConfiguration %x:%x:%x\n", Sbdf.Bus, Sb= df.Dev, Sbdf.Func)); + + ChildCpm =3D FALSE; + + if (HasChildBus (Sbdf, &ChildSbdf)) { + ChildCpm =3D TRUE; + DevType =3D GetDeviceType (Sbdf); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + ChildCpm &=3D RecursiveCpmConfiguration (ChildSbdf); + } + if (ChildCpm) { + while (FindNextPcieChild (DevType, &ChildSbdf)) { + EnableCpm (ChildSbdf); + } + } + } + return IsCpmSupported (Sbdf); +} + +/** + Sets Common Clock Configuration bit for devices that share common clock = across link + Devices on both sides of a PCIE link share common clock if both upstream= component + and function 0 of downstream component report Slot Clock Configuration b= it =3D 1. + When this function executes on upstream component, it checks SCC of both= sides of the link + If they both support it, sets CCC for both sides (this means all functio= ns of downstream component) + When this function executes on downstream component, it only returns SCC= capability + + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + @param[in] WaitForRetrain decides if this function shoul= d busy-wait for link retrain + + @retval TRUE =3D this device supports SCC, FALSE =3D it doesn't +**/ +STATIC +BOOLEAN +RecursiveCccConfiguration ( + SBDF Sbdf, + BOOLEAN WaitForRetrain + ) +{ + UINT64 Base; + SBDF ChildSbdf; + BOOLEAN MyScc; + BOOLEAN ChildScc; + BOOLEAN LinkScc; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveCccConfiguration %x:%x:%x\n", Sbdf.Bus, Sb= df.Dev, Sbdf.Func)); + + ChildScc =3D 0; + Base =3D SbdfToBase(Sbdf); + MyScc =3D GetScc (SbdfToBase(Sbdf), (UINT8)Sbdf.PcieCap); + if (HasChildBus (Sbdf, &ChildSbdf)) { + DevType =3D GetDeviceType (Sbdf); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + ChildScc |=3D RecursiveCccConfiguration (ChildSbdf, WaitForRetrain); + } + if (DevType =3D=3D DevTypePcieDownstream) { + LinkScc =3D MyScc & ChildScc; + if (LinkScc) { + EnableCcc (SbdfToBase(Sbdf), (UINT8)Sbdf.PcieCap); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + EnableCcc (SbdfToBase(ChildSbdf), (UINT8)ChildSbdf.PcieCap); + } + RetrainLink(Base, (UINT8)Sbdf.PcieCap, WaitForRetrain); + } + } + } + return MyScc; +} + +/** + Configures Latency Tolerance Reporting in given device and in PCIe tree = below it. + This function configures Maximum LTR and enables LTR mechanism. It visit= s devices using depth-first search + and skips branches behind devices which do not support LTR. + Maximum LTR: + This function will set LTR's upper bound for every visited device. Max= LTR value is provided as a parameter + Enable LTR: + LTR should be enabled top-to-bottom in every visited device that suppo= rts LTR. This function does not + iterate down behind devices with no LTR support. In effect, LTR will b= e enabled in given device if that device + and all devices above it on the way to RootComplex do support LTR. + + This function expects that bridges have bus numbers already configured + + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + @param[in] LtrLimit Ltr to be programmed to every = endpoint + + @retval MaxLTR programmed in this device +**/ +STATIC +VOID +RecursiveLtrConfiguration ( + SBDF Sbdf, + LTR_LIMIT LtrLimit + ) +{ + UINT64 Base; + SBDF ChildSbdf; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveLtrConfiguration %x:%x:%x\n", Sbdf.Bus, Sb= df.Dev, Sbdf.Func)); + + Base =3D SbdfToBase(Sbdf); + + if (!IsLtrCapable (Sbdf)) { + DEBUG ((DEBUG_INFO, "Not LtrCapable %02x:%02x:%02x\n", Sbdf.Bus, Sbdf.= Dev, Sbdf.Func)); + return; + } + EnableLtr (Sbdf); + if (HasChildBus (Sbdf, &ChildSbdf)) { + DevType =3D GetDeviceType (Sbdf); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + RecursiveLtrConfiguration (ChildSbdf, LtrLimit); + } + } + SetLtrLimit (Base, LtrLimit); +} + +/** + In accordance with PCIe spec, devices with no LTR support are considered= to have no LTR requirements + which means infinite latency tolerance. This was found to cause problems= with HID and Audio devices without LTR + support placed behind PCIe switches with LTR support, as Switch's upstre= am link would be allowed to enter L1.2 + and cause large latency downstream. To work around such issues and to fi= x some devices with broken + LTR reporting, Device Override table was introduced. + This function scans PCIe tree for devices mentioned in override table an= d calculates the strictest + LTR requirement between them. That value will be programmed into rootpor= t's LTR override register + + This function expects that bridges have bus numbers already configured + + @param[in] BusLimit maximum Bus number that can be= assigned below this port + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + @param[in] AspmOverride Device specific ASPM policy ov= erride items + + @retval MaxLTR programmed in this device +**/ +STATIC +LTR_OVERRIDE +RecursiveLtrOverrideCheck ( + SBDF Sbdf, + OVERRIDE_TABLE *AspmOverride + ) +{ + UINT64 Base; + SBDF ChildSbdf; + LTR_OVERRIDE MyLtrOverride; + LTR_OVERRIDE ChildLtr; + PCI_DEV_TYPE DevType; + + DEBUG ((DEBUG_INFO, "RecursiveLtrOverrideCheck %x:%x:%x\n", Sbdf.Bus, Sb= df.Dev, Sbdf.Func)); + + Base =3D SbdfToBase(Sbdf); + + MyLtrOverride =3D GetOverrideLtr (Base, AspmOverride); + if (HasChildBus (Sbdf, &ChildSbdf)) { + DevType =3D GetDeviceType (Sbdf); + while (FindNextPcieChild (DevType, &ChildSbdf)) { + ChildLtr =3D RecursiveLtrOverrideCheck (ChildSbdf, AspmOverride); + MyLtrOverride =3D CombineLtr (MyLtrOverride, ChildLtr); + } + } + return MyLtrOverride; +} + +/** + Configures rootport packet split. + + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + @param[in] Mps maximum packet size +**/ +STATIC +VOID +ConfigureRpPacketSplit ( + SBDF RpSbdf, + UINT8 Mps + ) +{ + UINT64 RpBase; + + RpBase =3D SbdfToBase (RpSbdf); + PciSegmentAndThenOr32 (RpBase + R_PCH_PCIE_CFG_CCFG, (UINT32) ~(B_PCH_PC= IE_CFG_CCFG_UNRS), Mps << N_PCH_PCIE_CFG_CCFG_UNRS); +} + +/** + Configures LTR override in rootport's proprietary registers. + + @param[in] Segment,Bus,Device,Function address of currently visited P= CIe device + @param[in] RpConfig rootport configuration + @param[in] TreeLtr combination of LTR override va= lues from all devices under this rootport +**/ +STATIC +VOID +ConfigureRpLtrOverride ( + SBDF RpSbdf, + PCH_PCIE_ROOT_PORT_CONFIG *RpConfig, + OVERRIDE_TABLE *AspmOverride + ) +{ + UINT64 RpBase; + UINT32 OvrEn; + UINT32 OvrVal; + LTR_OVERRIDE TreeLtr; + + OvrEn =3D 0; + OvrVal =3D 0; + RpBase =3D SbdfToBase (RpSbdf); + // + // LTR settings from LTROVR register only get acknowledged on rising edg= e of LTROVR2[1:0] + // If those bits were already set (that can happen on a plug-hotUnplug-h= otPlug scenario), + // they need to be toggled + // + if (PciSegmentRead32 (RpBase + R_PCH_PCIE_CFG_LTROVR2) !=3D 0) { + PciSegmentWrite32 (RpBase + R_PCH_PCIE_CFG_LTROVR2, 0); + } + // + // (*)LatencyOverrideMode =3D 0 -> no override + // 1 -> override with RP policy values + // 2 -> override with endpoint's override values + // + + TreeLtr =3D RecursiveLtrOverrideCheck (RpSbdf, AspmOverride); + + if (RpConfig->ForceLtrOverride || TreeLtr.ForceOverride) { + OvrEn |=3D B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE; + } + if (RpConfig->LtrConfigLock =3D=3D TRUE) { + OvrEn |=3D B_PCH_PCIE_CFG_LTROVR2_LOCK; + } + + if (RpConfig->SnoopLatencyOverrideMode =3D=3D 1) { + OvrEn |=3D B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN; + OvrVal |=3D RpConfig->SnoopLatencyOverrideValue; + OvrVal |=3D RpConfig->SnoopLatencyOverrideMultiplier << 10; + OvrVal |=3D B_PCH_PCIE_CFG_LTROVR_LTRSROVR; + } else if (RpConfig->SnoopLatencyOverrideMode =3D=3D 2) { + if (TreeLtr.MaxSnoopLatencyRequirement) { + OvrEn |=3D B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN; + OvrVal |=3D TreeLtr.MaxSnoopLatencyValue; + OvrVal |=3D TreeLtr.MaxSnoopLatencyScale << 10; + OvrVal |=3D B_PCH_PCIE_CFG_LTROVR_LTRSROVR; + } + } + if (RpConfig->NonSnoopLatencyOverrideMode =3D=3D 1) { + OvrEn |=3D B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN; + OvrVal |=3D RpConfig->NonSnoopLatencyOverrideValue << 16; + OvrVal |=3D RpConfig->NonSnoopLatencyOverrideMultiplier << 26; + OvrVal |=3D B_PCH_PCIE_CFG_LTROVR_LTRNSROVR; + } else if (RpConfig->NonSnoopLatencyOverrideMode =3D=3D 2) { + if (TreeLtr.MaxNoSnoopLatencyRequirement) { + OvrEn |=3D B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN; + OvrVal |=3D TreeLtr.MaxNoSnoopLatencyValue << 16; + OvrVal |=3D TreeLtr.MaxNoSnoopLatencyScale << 26; + OvrVal |=3D B_PCH_PCIE_CFG_LTROVR_LTRNSROVR; + } + } + PciSegmentWrite32 (RpBase + R_PCH_PCIE_CFG_LTROVR, OvrVal); + PciSegmentWrite32 (RpBase + R_PCH_PCIE_CFG_LTROVR2, OvrEn); + DEBUG ((DEBUG_INFO, "ConfigureRpLtrOverride %x:%x Val %x En %x\n", RpSbd= f.Dev, RpSbdf.Func, OvrVal, OvrEn)); +} + +/** + This function configures EOI message forwarding for PCIe port. + If there's an IoAPIC behind this port, forwarding will be enabled + Otherwise it will be disabled to minimize bus traffic + + @param[in] RpSegment address of rootport on PCIe + @param[in] RpBus address of rootport on PCIe + @param[in] RpDevice address of rootport on PCIe + @param[in] RpFunction address of rootport on PCIe + @param[in] IoApicPresent TRUE if there's IoAPIC behind this rootprot +**/ +VOID +ConfigureEoiForwarding ( + UINT8 RpSegment, + UINT8 RpBus, + UINT8 RpDevice, + UINT8 RpFunction, + BOOLEAN IoApicPresent + ) +{ + UINT64 RpBase; + UINT32 RpIndex; + + RpBase =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFuncti= on, 0); + RpIndex =3D PciePortIndex (RpBase); + + if (IoApicPresent =3D=3D FALSE) { + PciSegmentOr32 (RpBase + R_PCH_PCIE_CFG_MPC2, B_PCH_PCIE_CFG_MPC2_EOIFD= ); + } else { + /// + /// If there is an IOAPIC discovered behind root port program PSF Mult= icast registers + /// accordingly to PCH BWG PSF EOI Multicast Configuration + /// + PciSegmentAnd32 (RpBase + R_PCH_PCIE_CFG_MPC2, (UINT32)~B_PCH_PCIE_CFG= _MPC2_EOIFD); + PsfConfigurEoiForPciePort (RpIndex); + } +} + +/** + Configures proprietary parts of L1 substates configuration in rootport + + @param[in] RpSbdf segment:bus:device:function coordinates of rootport +**/ +STATIC +VOID +L1ssProprietaryConfiguration ( + SBDF RpSbdf + ) +{ + BOOLEAN ClkreqSupported; + BOOLEAN L1ssEnabled; + UINT16 PcieCapOffset; + UINT32 Data32; + BOOLEAN L1LowSupported; + UINT64 RpBase; + + RpBase =3D SbdfToBase (RpSbdf); + ClkreqSupported =3D PcieIsPhyLanePgEnabled (RpBase); + + PcieCapOffset =3D PcieBaseFindExtendedCapId (RpBase, V_PCIE_EX_L1S_CID); + if (PcieCapOffset =3D=3D 0) { + L1ssEnabled =3D FALSE; + } else { + Data32 =3D PciSegmentRead32 (RpBase + PcieCapOffset + R_PCIE_EX_L1SCTL= 1_OFFSET); + L1ssEnabled =3D Data32 & (B_PCIE_EX_L1SCAP_AL1SS | B_PCIE_EX_L1SCAP_AL= 12S | B_PCIE_EX_L1SCAP_PPL11S |B_PCIE_EX_L1SCAP_PPL12S); + } + L1LowSupported =3D ClkreqSupported && IsLtrCapable (RpSbdf) && !L1ssEnab= led; + + /// + /// If L1.SNOOZ and L1.OFF (L1 Sub-States) are not supported and per-por= t CLKREQ# is supported, and LTR is supported: + /// Enable L1.LOW by setting Dxx:Fn:420[17] =3D 1b + /// + if (L1LowSupported) { + PciSegmentOr32 (RpBase + R_PCH_PCIE_CFG_PCIEPMECTL, (UINT32) B_PCH_PCI= E_CFG_PCIEPMECTL_L1LE); + } else { + PciSegmentAnd32 (RpBase + R_PCH_PCIE_CFG_PCIEPMECTL, (UINT32) ~B_PCH_P= CIE_CFG_PCIEPMECTL_L1LE); + } + + if (L1LowSupported || L1ssEnabled) { + /// + /// f. Set Dxx:Fn:420h[0] to 1b prior to L1 enabling if any L1substat= e is enabled (including L1LOW) + /// + PciSegmentOr32 (RpBase + R_PCH_PCIE_CFG_PCIEPMECTL, B_PCH_PCIE_CFG_PCI= EPMECTL_L1FSOE); + } +} + +/** + Initializes the following features in rootport and devices behind it: + Maximum Payload Size (generic) + Rootport packet split (proprietary) + EonOfInterrupt forwarding (proprietary) + Common Clock Configuration (generic) + + Generic: any code written according to PCIE Express base specification c= an do that. + Proprietary: code uses registers and features that are specific to Intel= silicon + and probably only this Reference Code knows how to handle that. + + If OEM implemented generic feature enabling in his platform code or trus= ts Operating System + to do it, then those features can be deleted from here. + + CCC requires link retrain, which takes a while. CCC must happen before L= 0s/L1 programming. + If there was guarantee no code would access PCI while links retrain, it = would be possible to skip this waiting + + @param[in] RpSegment address of rootport on PCIe + @param[in] RpBus address of rootport on PCIe + @param[in] RpDevice address of rootport on PCIe + @param[in] RpFunction address of rootport on PCIe + @param[in] BusMin minimum Bus number that can be assigned below this= rootport + @param[in] BusMax maximum Bus number that can be assigned below this= rootport +**/ +VOID +RootportDownstreamConfiguration ( + UINT8 RpSegment, + UINT8 RpBus, + UINT8 RpDevice, + UINT8 RpFunction, + UINT8 BusMin, + UINT8 BusMax + ) +{ + UINT8 Mps; + BOOLEAN IoApicPresent; + UINT64 RpBase; + SBDF RpSbdf; + SBDF_TABLE BridgeCleanupList; + + RpBase =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFuncti= on, 0); + if (!(IsDevicePresent (RpBase))) { + return; + } + RpSbdf.Seg =3D RpSegment; + RpSbdf.Bus =3D RpBus; + RpSbdf.Dev =3D RpDevice; + RpSbdf.Func =3D RpFunction; + RpSbdf.PcieCap =3D PcieBaseFindCapId (RpBase, EFI_PCI_CAPABILITY_ID_PCIE= XP); + + DEBUG ((DEBUG_INFO, "RootportDownstreamConfiguration %x:%x\n", RpDevice,= RpFunction)); + BridgeCleanupList.Count =3D 0; + RecursiveBusAssignment (RpSbdf, BusMin, BusMax, &BridgeCleanupList); + + Mps =3D RecursiveMpsCheck (RpSbdf); + RecursiveMpsConfiguration (RpSbdf, Mps); + ConfigureRpPacketSplit (RpSbdf, Mps); + IoApicPresent =3D RecursiveIoApicCheck (RpSbdf); + ConfigureEoiForwarding (RpSegment, RpBus, RpDevice, RpFunction, IoApicPr= esent); + RecursiveCccConfiguration (RpSbdf, TRUE); + + ClearBusFromTable (&BridgeCleanupList); +} + +/** + Configures the following power-management related features in rootport a= nd devices behind it: + LTR limit (generic) + LTR override (proprietary) + Clock Power Management (generic) + L1 substates (generic except for the override table) + L1.LOW substate (proprietary) + L0s and L1 (generic) + + Generic: any code written according to PCIE Express base specification c= an do that. + Proprietary: code uses registers and features that are specific to Intel= silicon + and probably only this Reference Code knows how to handle that. + + If OEM implemented generic feature enabling in his platform code or trus= ts Operating System + to do it, then those features can be deleted from here. + + @param[in] RpSegment address of rootport on PCIe + @param[in] RpBus address of rootport on PCIe + @param[in] RpDevice address of rootport on PCIe + @param[in] RpFunction address of rootport on PCIe + @param[in] BusLimit maximum Bus number that can be assig= ned below this rootport + @param[in] AspmOverrideTableSize size of override array + @param[in] AspmOverrideTable array of device that need exceptions= in configuration + @param[in] PerformAspmConfiguration enables/disables ASPM programming +**/ +VOID +RootportDownstreamPmConfiguration ( + UINT8 RpSegment, + UINT8 RpBus, + UINT8 RpDevice, + UINT8 RpFunction, + UINT8 BusMin, + UINT8 BusMax, + PCH_PCIE_ROOT_PORT_CONFIG *RpConfig, + UINT32 AspmOverrideTableSize, + PCH_PCIE_DEVICE_OVERRIDE *AspmOverrideTable + ) +{ + LTR_LIMIT PolicyLtr; + OVERRIDE_TABLE PmOverrideTable; + UINT64 RpBase; + SBDF RpSbdf; + SBDF_TABLE BridgeCleanupList; + + RpBase =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDevice, RpFuncti= on, 0); + if (!(IsDevicePresent (RpBase))) { + return; + } + PmOverrideTable.Size =3D AspmOverrideTableSize; + PmOverrideTable.Table =3D AspmOverrideTable; + + DEBUG ((DEBUG_INFO, "RootportDownstreamPmConfiguration %x:%x\n", RpDevic= e, RpFunction)); + PolicyLtr.MaxNoSnoopLatencyScale =3D (RpConfig->LtrMaxNoSnoopLatency & 0= x1c00) >> 10; + PolicyLtr.MaxNoSnoopLatencyValue =3D RpConfig->LtrMaxNoSnoopLatency & 0x= 3FF; + PolicyLtr.MaxSnoopLatencyScale =3D (RpConfig->LtrMaxSnoopLatency & 0x1= c00) >> 10; + PolicyLtr.MaxSnoopLatencyValue =3D RpConfig->LtrMaxSnoopLatency & 0x3F= F; + + RpSbdf.Seg =3D RpSegment; + RpSbdf.Bus =3D RpBus; + RpSbdf.Dev =3D RpDevice; + RpSbdf.Func =3D RpFunction; + RpSbdf.PcieCap =3D PcieBaseFindCapId (RpBase, EFI_PCI_CAPABILITY_ID_PCIE= XP); + // + // This code could execute either before or after enumeration. If before= , then buses would not yet be assigned to bridges, + // making devices deeper in the hierarchy inaccessible. + // RecursiveBusAssignment will scan whole PCie tree and assign bus numbe= rs to uninitialized bridges, if there are any + // List of such bridges will be kept in CleanupList, so that after PM pr= ogramming is done, bus numbers can brought to original state + // + BridgeCleanupList.Count =3D 0; + RecursiveBusAssignment(RpSbdf, BusMin, BusMax, &BridgeCleanupList); + // + // The 'Recursive...' functions below expect bus numbers to be already a= ssigned + // + RecursiveLtrConfiguration (RpSbdf, PolicyLtr); + ConfigureRpLtrOverride (RpSbdf, RpConfig, &PmOverrideTable); + if (RpConfig->EnableCpm) { + RecursiveCpmConfiguration (RpSbdf); + } + // + // L1 substates can be modified only when L1 is disabled, so this functi= on must execute + // before Aspm configuration which enables L1 + // + RecursiveL1ssConfiguration (RpSbdf, &PmOverrideTable); + L1ssProprietaryConfiguration (RpSbdf); + RecursiveAspmConfiguration (RpSbdf, 0, &PmOverrideTable); + ClearBusFromTable (&BridgeCleanupList); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchPsfPrivateLib/PchPsfPrivateLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/= Pch/Library/Private/PeiDxeSmmPchPsfPrivateLib/PchPsfPrivateLib.c new file mode 100644 index 0000000000..f2d20c625a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPs= fPrivateLib/PchPsfPrivateLib.c @@ -0,0 +1,542 @@ +/** @file + This file contains PSF routines for RC usage + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PchPsfPrivateLibInternal.h" + +/** + Disable device at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfDisableDevice ( + IN PSF_PORT PsfPort + ) +{ + if (PSF_IS_PORT_NULL (PsfPort)) { + ASSERT (FALSE); + return; + } + + // + // Read back is needed to enforce the sideband and primary ordering. + // + PchPcrAndThenOr32WithReadback ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN, + ~0u, + B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS + ); +} + +/** + Hide PciCfgSpace of device at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfHideDevice ( + IN PSF_PORT PsfPort + ) +{ + if (PSF_IS_PORT_NULL (PsfPort)) { + ASSERT (FALSE); + return; + } + + // + // Read back is needed to enforce the sideband and primary ordering. + // If there is PCI access right after the PSF hide device, the device mi= ght + // still be accessible since the PSF cycle is not completed yet, and cau= ses + // the race condition between sideband and primary cycles. + // + PchPcrAndThenOr32WithReadback ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_CFG_DIS, + ~0u, + B_PCH_PSFX_PCR_T0_SHDW_CFG_DIS_CFGDIS + ); +} + +/** + Unhide PciCfgSpace of device at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfUnhideDevice ( + IN PSF_PORT PsfPort + ) +{ + if (PSF_IS_PORT_NULL (PsfPort)) { + ASSERT (FALSE); + return; + } + + // + // Read back is needed to enforce the sideband and primary ordering. + // + PchPcrAndThenOr32WithReadback ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_CFG_DIS, + (UINT32) ~(B_PCH_PSFX_PCR_T0_SHDW_CFG_DIS_CFGDIS), + 0 + ); +} + +/** + Disable device BARs at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure + @param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,... + Mask corresponds to 32bit wide BARs +**/ +VOID +PsfDisableDeviceBar ( + IN PSF_PORT PsfPort, + IN UINT32 BarDisMask + ) +{ + if (PSF_IS_PORT_NULL (PsfPort)) { + ASSERT (FALSE); + return; + } + + // + // BAR0-5 supported + // + ASSERT (BarDisMask < BIT6); + + // + // Read back is needed to enforce the sideband and primary ordering. + // + PchPcrAndThenOr32WithReadback ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN, + ~0u, + BarDisMask << N_PCH_PSFX_PCR_T0_SHDW_PCIEN_BARXDIS + ); +} + +/** + Enable device BARs at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure + @param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,... + Mask corresponds to 32bit wide BARs +**/ +VOID +PsfEnableDeviceBar ( + IN PSF_PORT PsfPort, + IN UINT32 BarEnMask + ) +{ + if (PSF_IS_PORT_NULL (PsfPort)) { + ASSERT (FALSE); + return; + } + + // + // BAR0-5 supported + // + ASSERT (BarEnMask < BIT6); + + // + // Read back is needed to enforce the sideband and primary ordering. + // + PchPcrAndThenOr32WithReadback ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN, + (UINT32)~(BarEnMask << N_PCH_PSFX_PCR_T0_SHDW_PCIEN_BARXDIS), + 0 + ); +} + +/** + Disable device IOSpace at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfDisableDeviceIoSpace ( + IN PSF_PORT PsfPort + ) +{ + if (PSF_IS_PORT_NULL (PsfPort)) { + ASSERT (FALSE); + return; + } + + // + // Read back is needed to enforce the sideband and primary ordering. + // + PchPcrAndThenOr32WithReadback ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN, + ~(UINT32)(B_PCH_PSFX_PCR_T0_SHDW_PCIEN_IOEN), + 0 + ); +} + +/** + Enable device IOSpace at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure +**/ +VOID +PsfEnableDeviceIoSpace ( + IN PSF_PORT PsfPort + ) +{ + if (PSF_IS_PORT_NULL (PsfPort)) { + ASSERT (FALSE); + return; + } + + // + // Read back is needed to enforce the sideband and primary ordering. + // + PchPcrAndThenOr32WithReadback ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_PCIEN, + ~0u, + B_PCH_PSFX_PCR_T0_SHDW_PCIEN_IOEN + ); +} + +/** + Set device BARx address at PSF level + Method not for bridges (e.g. PCIe Root Port) + + @param[in] PsfPort PSF PORT data structure + @param[in] BarNum BAR Number (0:BAR0, 1:BAR1, ...) + @param[in] BarValue 32bit BAR value +**/ +VOID +PsfSetDeviceBarValue ( + IN PSF_PORT PsfPort, + IN UINT8 BarNum, + IN UINT32 BarValue + ) +{ + ASSERT (BarNum < 6); + + if (PSF_IS_PORT_NULL (PsfPort)) { + ASSERT (FALSE); + return; + } + + // + // Read back is needed to enforce the sideband and primary ordering. + // + PchPcrAndThenOr32WithReadback ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_BAR0 + BarNum * 0x4, + 0, + BarValue + ); +} + +/** + Hide PMC device at PSF level +**/ +VOID +PsfHidePmcDevice ( + VOID + ) +{ + PsfHideDevice (PsfPmcPort ()); +} + +/** + Set PMC ABASE value in PSF + + @param[in] Address Address for ACPI base address. +**/ +VOID +PsfSetPmcAbase ( + IN UINT16 Address + ) +{ + PSF_PORT PsfPort; + + PsfPort =3D PsfPmcPort (); + + ASSERT (PchPcrRead32 (PsfPort.PsfPid, PsfPort.RegBase + R_PCH_PSFX_PCR_T= 0_SHDW_BAR4) !=3D 0xFFFFFFFF); + + // + // Disable IOSpace before changing the address + // + PsfDisableDeviceIoSpace (PsfPort); + + // + // Program ABASE in PSF PMC space BAR4 + // + PsfSetDeviceBarValue (PsfPort, 4, Address); + + // + // Enable IOSpace + // + PsfEnableDeviceIoSpace (PsfPort); +} + +/** + Get PMC ABASE value from PSF + + @retval Address Address for ACPI base. +**/ +UINT16 +PsfGetPmcAbase ( + VOID + ) +{ + UINT16 Address; + PSF_PORT PsfPort; + + PsfPort =3D PsfPmcPort (); + // + // Read ABASE from PSF PMC space BAR4 + // + Address =3D PchPcrRead16 ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_BAR4 + ); + + ASSERT (Address !=3D 0xFFFF); + + return Address; +} + +/** + Get PMC PWRMBASE value from PSF + + @retval Address Address for PWRM base. +**/ +UINT32 +PsfGetPmcPwrmBase ( + VOID + ) +{ + UINT32 Address; + PSF_PORT PsfPort; + + PsfPort =3D PsfPmcPort (); + // + // Read PWRMBASE from PSF PMC space BAR0 + // + Address =3D PchPcrRead32 ( + PsfPort.PsfPid, + PsfPort.RegBase + R_PCH_PSFX_PCR_T0_SHDW_BAR0 + ); + + ASSERT (Address !=3D 0xFFFFFFFF); + + return Address; +} + +/** + Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...) + + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) + + @retval PSF SideBand Port ID +**/ +PCH_SBI_PID +PsfSbPortId ( + UINT32 PsfId + ) +{ + UINT32 PsfTableIndex; + PSF_SEGMENT *PsfTable; + UINT32 PsfTableSize; + + PsfSegments (&PsfTable, &PsfTableSize); + + for (PsfTableIndex =3D 0; PsfTableIndex < PsfTableSize; PsfTableIndex++)= { + if (PsfTable[PsfTableIndex].Id =3D=3D PsfId) { + return PsfTable[PsfTableIndex].SbPid; + } + } + + ASSERT (FALSE); + return 0; +} + + +/** + Get PCH Root PSF ID. This is the PSF segment to which OPDMI/DMI is conne= cted. + + @retval PsfId Root PSF ID +**/ +UINT32 +PsfRootId ( + VOID + ) +{ + PSF_SEGMENT *PsfTable; + UINT32 PsfTableSize; + + PsfSegments (&PsfTable, &PsfTableSize); + + return PsfTable[0].Id; +} + +/** + Add EOI Target in a given PSF + + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) + @param[in] TargetId EOI Target ID +**/ +STATIC +VOID +PsfAddEoiTarget ( + UINT32 PsfId, + PSF_PORT_DEST_ID TargetId + ) +{ + UINT16 EoiTargetBase; + UINT16 EoiControlBase; + UINT8 NumOfEnabledTargets; + UINT8 MaximalNumberOfTargets; + PCH_SBI_PID PsfSbiPortId; + UINT32 Data32; + UINT8 TargetIndex; + + MaximalNumberOfTargets =3D PsfEoiRegData (PsfId, &EoiTargetBase, &EoiCon= trolBase); + PsfSbiPortId =3D PsfSbPortId (PsfId); + + // + // Get number of enabled agents from PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI= register + // + Data32 =3D PchPcrRead32 (PsfSbiPortId, EoiControlBase); + NumOfEnabledTargets =3D (UINT8) (Data32 >> N_PCH_PSFX_PCR_MC_CONTROL_MCA= STX_NUMMC); + + // + // Check if target was not already enabled + // Targets from a different PSF segment are aggregated into single desti= nation on + // current PSF segment. + // + for (TargetIndex =3D 0; TargetIndex < NumOfEnabledTargets; TargetIndex++= ) { + Data32 =3D PchPcrRead32 (PsfSbiPortId, EoiTargetBase + TargetIndex * 4= ); + // + // If target already added don't add it again + // + if (Data32 =3D=3D TargetId.RegVal) { + ASSERT (FALSE); + return; + } + // + // If target is from different PSF segment than currently being analyz= ed + // it is enough that its PsfID is matching + // + if ((Data32 & B_PCH_PSFX_PCR_TARGET_PSFID) >> N_PCH_PSFX_PCR_TARGET_PS= FID =3D=3D TargetId.Fields.PsfId) { + return; + } + } + + // + // Check if next one can be added + // + if (NumOfEnabledTargets >=3D MaximalNumberOfTargets) { + ASSERT (FALSE); + return; + } + + // + // Add next target + // Configure Multicast Destination ID register with target device on PSF. + // Configuration must be done in next available PSF_MC_AGENT_MCAST0_RS0_= TGT_EOI register + // so that other targets are not overridden. is known from the numb= er of multicast agents + // in Multicast Control Register. Value programmed is based on + // PsfID, PortGroupID, PortID and ChannelID of the target + // + PchPcrWrite32 (PsfSbiPortId, EoiTargetBase + NumOfEnabledTargets * 4, Ta= rgetId.RegVal); + + // + // Enable new target + // Configure PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI, increase NumMc and set= MultCEn + // + NumOfEnabledTargets++; + Data32 =3D (NumOfEnabledTargets << N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMM= C) | B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN; + PchPcrWrite32 (PsfSbiPortId, EoiControlBase, Data32); +} + +/** + Enable EOI Target + + @param[in] TargetId Target ID +**/ +STATIC +VOID +PsfEnableEoiTarget ( + PSF_PORT_DEST_ID TargetId + ) +{ + UINT32 RootLevelPsf; + + RootLevelPsf =3D PsfRootId (); + + // + // Enable EOI target in root PSF + // + PsfAddEoiTarget (RootLevelPsf, TargetId); + + // + // Enable EOI target on other PSF segment if target + // is not located on root PSF + // + if (TargetId.Fields.PsfId !=3D RootLevelPsf) { + PsfAddEoiTarget (TargetId.Fields.PsfId, TargetId); + } +} + +/** + This function enables EOI message forwarding in PSF for PCIe ports + for cases where IOAPIC is present behind this root port. + + @param[in] RpIndex Root port index (0 based) + + @retval Status +**/ +EFI_STATUS +PsfConfigurEoiForPciePort ( + IN UINT32 RpIndex + ) +{ + ASSERT (RpIndex < GetPchMaxPciePortNum ()); + + // + // If there is an IOAPIC discovered behind root port program PSF Multica= st registers + // accordingly to PCH BWG PSF EOI Multicast Configuration + // Since there is a device behind RootPort to which EOI needs to be forw= arded + // enable multicast (MULTCEN) and increase the number of multicast agent= s (NUMMC) + // in Multicast Control Register. + // + PsfEnableEoiTarget (PsfPcieDestinationId (RpIndex)); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPchPsfPrivateLib/PchPsfPrivateLibCnl.c b/Silicon/Intel/CoffeelakeSiliconP= kg/Pch/Library/Private/PeiDxeSmmPchPsfPrivateLib/PchPsfPrivateLibCnl.c new file mode 100644 index 0000000000..d1c87a9e84 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPchPs= fPrivateLib/PchPsfPrivateLibCnl.c @@ -0,0 +1,338 @@ +/** @file + This file contains internal PSF routines for PCH PSF lib usage + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PchPsfPrivateLibInternal.h" + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoI2cPsfRegs[] =3D +{ + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C0_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C1_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C2_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C3_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C4_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_I2C5_REG_BASE +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchHSerialIoI2cPsfRegs[] =3D +{ + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C0_REG_BASE, + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C1_REG_BASE, + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C2_REG_BASE, + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_I2C3_REG_BASE +}; + +/** + Return PSF_PORT for SerialIO I2C device + + @param[in] I2cNum Serial IO I2C device (I2C0, I2C1, ....) + + @retval PsfPort PSF PORT structure for SerialIO I2C device +**/ +PSF_PORT +PsfSerialIoI2cPort ( + IN UINT32 I2cNum + ) +{ + PSF_PORT PsfPort; + + PsfPort.PsfPid =3D PID_PSF3; + + if (IsPchLp ()) { + if (I2cNum < ARRAY_SIZE(mPchLpSerialIoI2cPsfRegs)) { + PsfPort.RegBase =3D mPchLpSerialIoI2cPsfRegs[I2cNum]; + return PsfPort; + } + } else { + if (I2cNum < ARRAY_SIZE(mPchHSerialIoI2cPsfRegs)) { + PsfPort.RegBase =3D mPchHSerialIoI2cPsfRegs[I2cNum]; + return PsfPort; + } + } + + ASSERT(FALSE); + return PSF_PORT_NULL; +} + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoSpiPsfRegs[] =3D +{ + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI0_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI1_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_SPI2_REG_BASE +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchHSerialIoSpiPsfRegs[] =3D +{ + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI0_REG_BASE, + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI1_REG_BASE, + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_SPI2_REG_BASE +}; + +/** + Return PSF_PORT for SerialIO SPI device + + @param[in] SpiNum Serial IO SPI device (SPI0, SPI1, ....) + + @retval PsfPort PSF PORT structure for SerialIO SPI device +**/ +PSF_PORT +PsfSerialIoSpiPort ( + IN UINT32 SpiNum + ) +{ + PSF_PORT PsfPort; + + PsfPort.PsfPid =3D PID_PSF3; + + if (IsPchLp ()) { + if (SpiNum < ARRAY_SIZE(mPchLpSerialIoSpiPsfRegs)) { + PsfPort.RegBase =3D mPchLpSerialIoSpiPsfRegs[SpiNum]; + return PsfPort; + } + } else { + if (SpiNum < ARRAY_SIZE(mPchHSerialIoSpiPsfRegs)) { + PsfPort.RegBase =3D mPchHSerialIoSpiPsfRegs[SpiNum]; + return PsfPort; + } + } + + ASSERT(FALSE); + return PSF_PORT_NULL; +} + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoUartPsfRegs[] =3D +{ + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART0_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART1_REG_BASE, + R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_UART2_REG_BASE +}; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchHSerialIoUartPsfRegs[] =3D +{ + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART0_REG_BASE, + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART1_REG_BASE, + R_CNL_PCH_H_PSF3_PCR_T0_SHDW_UART2_REG_BASE +}; + +/** + Return PSF_PORT for SerialIO UART device + + @param[in] UartNum Serial IO UART device (UART0, UART1, ....) + + @retval PsfPort PSF PORT structure for SerialIO UART device +**/ +PSF_PORT +PsfSerialIoUartPort ( + IN UINT32 UartNum + ) +{ + PSF_PORT PsfPort; + + PsfPort.PsfPid =3D PID_PSF3; + + if (IsPchLp ()) { + if (UartNum < ARRAY_SIZE(mPchLpSerialIoUartPsfRegs)) { + PsfPort.RegBase =3D mPchLpSerialIoUartPsfRegs[UartNum]; + return PsfPort; + } + } else { + if (UartNum < ARRAY_SIZE(mPchHSerialIoUartPsfRegs)) { + PsfPort.RegBase =3D mPchHSerialIoUartPsfRegs[UartNum]; + return PsfPort; + } + } + + ASSERT(FALSE); + return PSF_PORT_NULL; +} + +/** + Get EOI register data for given PSF ID + + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...) + @param[out] EoiTargetBase EOI Target register + @param[out] EoiControlBase EOI Control register + + @retval MaxTargets Number of supported targets + +**/ +UINT8 +PsfEoiRegData ( + UINT32 PsfId, + UINT16 *EoiTargetBase, + UINT16 *EoiControlBase + ) +{ + UINT8 MaxTargets; + + MaxTargets =3D 0; + *EoiTargetBase =3D 0; + *EoiControlBase =3D 0; + + switch (PsfId) { + case 1: + if (IsPchLp ()) { + *EoiTargetBase =3D R_CNL_PCH_LP_PSF1_PCR_PSF_MC_AGENT_MCAST0_TGT0_= EOI; + *EoiControlBase =3D R_CNL_PCH_LP_PSF1_PCR_PSF_MC_CONTROL_MCAST0_EO= I; + MaxTargets =3D 17; + } else { + *EoiTargetBase =3D R_CNL_PCH_H_PSF1_PCR_PSF_MC_AGENT_MCAST0_TGT0_E= OI; + *EoiControlBase =3D R_CNL_PCH_H_PSF1_PCR_PSF_MC_CONTROL_MCAST0_EOI; + MaxTargets =3D 7; + } + break; + + case 3: + *EoiTargetBase =3D R_CNL_PCH_PSF3_PCR_PSF_MC_AGENT_MCAST0_TGT0_EOI; + *EoiControlBase =3D R_CNL_PCH_PSF3_PCR_PSF_MC_CONTROL_MCAST0_EOI; + MaxTargets =3D 1; + break; + + case 6: + if (IsPchH ()) { + *EoiTargetBase =3D R_CNL_PCH_H_PSF6_PCR_PSF_MC_AGENT_MCAST0_TGT0_E= OI; + *EoiControlBase =3D R_CNL_PCH_H_PSF6_PCR_PSF_MC_CONTROL_MCAST0_EOI; + MaxTargets =3D 8; + } + break; + + case 7: + if (IsPchH ()) { + *EoiTargetBase =3D R_CNL_PCH_H_PSF7_PCR_PSF_MC_AGENT_MCAST0_TGT0_E= OI; + *EoiControlBase =3D R_CNL_PCH_H_PSF7_PCR_PSF_MC_CONTROL_MCAST0_EOI; + MaxTargets =3D 8; + } + break; + + case 8: + if (IsPchH ()) { + *EoiTargetBase =3D R_CNL_PCH_H_PSF8_PCR_PSF_MC_AGENT_MCAST0_TGT0_E= OI; + *EoiControlBase =3D R_CNL_PCH_H_PSF8_PCR_PSF_MC_CONTROL_MCAST0_EOI; + MaxTargets =3D 8; + } + break; + } + return MaxTargets; +} + +GLOBAL_REMOVE_IF_UNREFERENCED PSF_PORT_DEST_ID PchLpRpDestId[] =3D +{ + {0x18000}, {0x18001}, {0x18002}, {0x18003}, // SPA: PSF1, PortID =3D 0 + {0x18200}, {0x18201}, {0x18202}, {0x18203}, // SPB: PSF1, PortID =3D 2 + {0x18400}, {0x18401}, {0x18402}, {0x18403}, // SPC: PSF1, PortID =3D 4 + {0x18600}, {0x18601}, {0x18602}, {0x18603} // SPD: PSF1, PortID =3D 6 +}; + +GLOBAL_REMOVE_IF_UNREFERENCED PSF_PORT_DEST_ID PchHRpDestId[] =3D +{ + {0x68000}, {0x68001}, {0x68002}, {0x68003}, // SPA: PSF6, PortID =3D 0 + {0x88000}, {0x88001}, {0x88002}, {0x88003}, // SPB: PSF8, PortID =3D 0 + {0x68100}, {0x68101}, {0x68102}, {0x68103}, // SPC: PSF6, PortID =3D 1 + {0x78000}, {0x78001}, {0x78002}, {0x78003}, // SPD: PSF7, PortID =3D 0 + {0x78100}, {0x78101}, {0x78102}, {0x78103}, // SPE: PSF7, PortID =3D 1 + {0x88100}, {0x88101}, {0x88102}, {0x88103} // SPF: PSF8, PortID =3D 1 +}; + +/** + PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id) + + @param[in] RpIndex PCIe Root Port Index (0 based) + + @retval Destination ID +**/ +PSF_PORT_DEST_ID +PsfPcieDestinationId ( + IN UINT32 RpIndex + ) +{ + if (IsPchLp ()) { + if (RpIndex < ARRAY_SIZE(PchLpRpDestId)) { + return PchLpRpDestId[RpIndex]; + } + } else { + if (RpIndex < ARRAY_SIZE(PchHRpDestId)) { + return PchHRpDestId[RpIndex]; + } + } + ASSERT (FALSE); + return (PSF_PORT_DEST_ID){0}; +} + + +/** + Return PSF_PORT for PMC device + + @retval PsfPort PSF PORT structure for PMC device +**/ +PSF_PORT +PsfPmcPort ( + VOID + ) +{ + PSF_PORT PsfPort; + + PsfPort.PsfPid =3D PID_PSF3; + + if (IsPchLp ()) { + PsfPort.RegBase =3D R_CNL_PCH_LP_PSF3_PCR_T0_SHDW_PMC_REG_BASE; + } else { + PsfPort.RegBase =3D R_CNL_PCH_H_PSF3_PCR_T0_SHDW_PMC_REG_BASE; + } + return PsfPort; +} + +GLOBAL_REMOVE_IF_UNREFERENCED PSF_SEGMENT mPchLpPsfTable[] =3D +{ + {1, PID_PSF1}, + {2, PID_PSF2}, + {3, PID_PSF3}, + {4, PID_PSF4}, + {5, PID_CSME_PSF} +}; + +GLOBAL_REMOVE_IF_UNREFERENCED PSF_SEGMENT mPchHPsfTable[] =3D +{ + {1, PID_PSF1}, + {2, PID_PSF2}, + {3, PID_PSF3}, + {4, PID_PSF4}, + {5, PID_CSME_PSF}, + {6, PID_PSF6}, + {7, PID_PSF7}, + {8, PID_PSF8} +}; + +/** + Get list of supported PSF segments. + + @param[out] PsfTable Array of supported PSF segments + @param[out] PsfTableLength Length of PsfTable +**/ +VOID +PsfSegments ( + OUT PSF_SEGMENT **PsfTable, + OUT UINT32 *PsfTableLength + ) +{ + if (IsPchLp ()) { + *PsfTable =3D mPchLpPsfTable; + *PsfTableLength =3D ARRAY_SIZE(mPchLpPsfTable); + } else { + *PsfTable =3D mPchHPsfTable; + *PsfTableLength =3D ARRAY_SIZE(mPchHPsfTable); + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PeiPmcPrivateLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch= /Library/Private/PeiDxeSmmPmcPrivateLib/PeiPmcPrivateLib.c new file mode 100644 index 0000000000..f88febfa48 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PeiPmcPrivateLib.c @@ -0,0 +1,92 @@ +/** @file + PCH private PEI PMC Library for all PCH generations. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PmcPrivateLibInternal.h" + +/** + Check if PCH PM Timer enabled based on platform policy + + @retval TRUE PCH PM Timer is enabled. + @retval FALSE PCH PM Timer is disabled. +**/ +BOOLEAN +PmcIsPchPmTimerEnabled ( + VOID + ) +{ + BOOLEAN PchPmTimerEnabled; + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicy; + PCH_PM_CONFIG *PmConfig; + + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicy + ); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &= PmConfig); + ASSERT_EFI_ERROR (Status); + + PchPmTimerEnabled =3D TRUE; + if (!PmConfig->EnableTcoTimer) { + PchPmTimerEnabled =3D FALSE; + } + + DEBUG ((DEBUG_INFO, "PmcIsPchPmTimerEnabled () =3D %x\n", PchPmTimerEnab= led)); + + return PchPmTimerEnabled; +} + +/** + Lock down PMC settings + + @param[in] SiPolicy The SI Policy PPI instance +**/ +VOID +PmcLockSettings ( + IN SI_POLICY_PPI *SiPolicy + ) +{ + + UINT32 PchPwrmBase; + PchPwrmBase =3D PmcGetPwrmBase (); + + /// + /// Set PWRMBASE Offset 0x1048 [24] + /// + MmioOr32 (PchPwrmBase + R_PMC_PWRM_ETR3, BIT24); + + /// + /// PM_SYNC_LOCK + /// Set PWRMBASE Offset 0x18C8 [15] + /// + MmioOr32 (PchPwrmBase + R_PMC_PWRM_PMSYNC_MISC_CFG, B_PMC_PWRM_PMSYNC_PM= _SYNC_LOCK); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PmcPrivateLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Li= brary/Private/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c new file mode 100644 index 0000000000..a6ccf4b96b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PmcPrivateLib.c @@ -0,0 +1,1033 @@ +/** @file + PCH private PMC Library for all PCH generations. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PmcPrivateLibInternal.h" + +/** + Send PMC IPC1 Normal Read/Write command + + @param[in] Command Command to be issued to PMC IPC 1 interface + @param[in] SubCmdId SUB_CMD_ID for provided Command + @param[in] CmdSize Total size in byte to be sent via PMC IPC = 1 interface + @param[in] WriteBufPtr Pointer to Structure of 4 DWORDs to be iss= ued to PMC IPC 1 interface + @param[out] ReadBufPtr Pointer to Structure of 4 DWORDs to be fil= led by PMC IPC 1 interface + + @retval EFI_SUCCESS Command was executed successfully + @retval EFI_INVALID_PARAMETER Invalid command size + @retval EFI_DEVICE_ERROR IPC command failed with an error + @retval EFI_TIMEOUT IPC command did not complete after 1s +**/ +EFI_STATUS +PmcSendCommand ( + IN UINT8 Command, + IN UINT8 SubCmdId, + IN UINT8 CmdSize, + IN PMC_IPC_COMMAND_BUFFER *WriteBufPtr, + OUT PMC_IPC_COMMAND_BUFFER *ReadBufPtr + ) +{ + EFI_STATUS Status; + UINT32 PchPwrmBase; + UINT32 IpcSts; + UINTN Timeout; + + DEBUG ((DEBUG_INFO, "PmcSendCommand(): IPC_COMMAND=3D0x%02X, IPC_SUB_CMD= =3D 0x%02X, IPC_SIZE=3D0x%02X \n", Command, SubCmdId, CmdSize)); + DEBUG ((DEBUG_INFO, "WBUF0=3D0x%08X, WBUF1=3D0x%08X, WBUF2=3D0x%08X, WBU= F3=3D0x%08X \n", WriteBufPtr->Buf0, WriteBufPtr->Buf1, WriteBufPtr->Buf2, W= riteBufPtr->Buf3)); + + if (CmdSize > 16) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Program the Write Buffer 0 with the Data that needs to be written to = PMC + // + PchPwrmBase =3D PmcGetPwrmBase (); + MmioWrite32 ((PchPwrmBase + R_PMC_PWRM_IPC_WBUF0), WriteBufPtr->Buf0); + MmioWrite32 ((PchPwrmBase + R_PMC_PWRM_IPC_WBUF1), WriteBufPtr->Buf1); + MmioWrite32 ((PchPwrmBase + R_PMC_PWRM_IPC_WBUF2), WriteBufPtr->Buf2); + MmioWrite32 ((PchPwrmBase + R_PMC_PWRM_IPC_WBUF3), WriteBufPtr->Buf3); + // + // Program the command register with command and size + // + MmioWrite32 ( + PchPwrmBase + R_PMC_PWRM_IPC_CMD, + (UINT32) ((CmdSize << N_PMC_PWRM_IPC_CMD_SIZE) | + (SubCmdId << N_PMC_PWRM_IPC_CMD_CMD_ID) | + (Command << N_PMC_PWRM_IPC_CMD_COMMAND)) + ); + + // + // Read the IPC_STS register to get BUSY or Error status + // + Timeout =3D 0; + Status =3D EFI_SUCCESS; + while (TRUE) { + IpcSts =3D MmioRead32 (PchPwrmBase + R_PMC_PWRM_IPC_STS); + if ((IpcSts & B_PMC_PWRM_IPC_STS_BUSY) =3D=3D 0) { + break; + } + + if (Timeout > (1000 * 100)) { + Status =3D EFI_TIMEOUT; + break; + } + MicroSecondDelay (10); + Timeout++; + } + + if ((IpcSts & B_PMC_PWRM_IPC_STS_ERROR) !=3D 0) { + Status =3D EFI_DEVICE_ERROR; + } + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "PmcSendCommand() Error: IPC_STS=3D0x%08X\n", Ipc= Sts)); + return Status; + } + + if (ReadBufPtr !=3D NULL) { + // + // Fill the ReadBuffer contents with the Data that needs to be read f= rom PMC + // + ReadBufPtr->Buf0 =3D MmioRead32(PchPwrmBase + R_PMC_PWRM_IPC_RBUF0); + ReadBufPtr->Buf1 =3D MmioRead32(PchPwrmBase + R_PMC_PWRM_IPC_RBUF1); + ReadBufPtr->Buf2 =3D MmioRead32(PchPwrmBase + R_PMC_PWRM_IPC_RBUF2); + ReadBufPtr->Buf3 =3D MmioRead32(PchPwrmBase + R_PMC_PWRM_IPC_RBUF3); + + DEBUG ((DEBUG_INFO, "RBUF0=3D0x%08X, RBUF1=3D0x%08X, RBUF2=3D0x%08X, R= BUF3=3D0x%08X \n", ReadBufPtr->Buf0, ReadBufPtr->Buf1, ReadBufPtr->Buf2, Re= adBufPtr->Buf3)); + } + + return Status; +} + +/** + This function checks if SCI interrupt is enabled + + @retval SCI Enable state +**/ +BOOLEAN +PmcIsSciEnabled ( + VOID + ) +{ + return ((IoRead8 (PmcGetAcpiBase () + R_ACPI_IO_PM1_CNT) & B_ACPI_IO_PM1= _CNT_SCI_EN) !=3D 0); +} + +/** + This function triggers Software GPE +**/ +VOID +PmcTriggerSwGpe ( + VOID + ) +{ + IoOr32 (PmcGetAcpiBase () + R_ACPI_IO_GPE_CNTL, B_ACPI_IO_GPE_CNTL_SWGPE= _CTRL); +} + +/** + Set PCH ACPI base address. + The Address should not be 0 and should be 256 bytes aligned. It is IO sp= ace, so must not exceed 0xFFFF. + Only address matching PcdAcpiBaseAddress is the acceptable value for ACP= I IO Base + + @param[in] Address Address for ACPI base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_INVALID_PARAMETER Invalid base address passed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PmcSetAcpiBase ( + IN UINT16 Address + ) +{ + + if (Address !=3D PcdGet16 (PcdAcpiBaseAddress)) { + DEBUG ((DEBUG_ERROR, "PmcSetAcpiBase Error. Invalid Address: %x.\n", A= ddress)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PsfSetPmcAbase (Address); + return EFI_SUCCESS; +} + +/** + Set PCH PWRM base address. + Only 0xFE000000 (PCH_PWRM_BASE_ADDRESS) is the acceptable value for PWRM= BASE + + @param[in] Address Address for PWRM base address. + + @retval EFI_SUCCESS Successfully completed. + @retval EFI_UNSUPPORTED DMIC.SRL is set. +**/ +EFI_STATUS +PmcSetPwrmBase ( + IN UINT32 Address + ) +{ + UINT64 PmcBase; + + if (Address !=3D PCH_PWRM_BASE_ADDRESS) { + DEBUG ((DEBUG_ERROR, "PmcSetPwrmBase Error. Invalid Address: %x.\n", A= ddress)); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PmcBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_PMC, + PCI_FUNCTION_NUMBER_PCH_PMC, + 0 + ); + if (PciSegmentRead16 (PmcBase) =3D=3D 0xFFFF) { + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + // + // Disable PWRMBASE in PMC Device first before changing PWRM base addres= s. + // + PciSegmentAnd16 ( + PmcBase + PCI_COMMAND_OFFSET, + (UINT16) ~EFI_PCI_COMMAND_MEMORY_SPACE + ); + + // + // Program PWRMBASE in PMC Device + // + PciSegmentAndThenOr32 ( + PmcBase + R_PMC_CFG_BASE, + (UINT32) (~B_PMC_CFG_PWRM_BASE_MASK), + Address + ); + + // + // Enable PWRMBASE in PMC Device + // + PciSegmentOr16 ( + PmcBase + PCI_COMMAND_OFFSET, + EFI_PCI_COMMAND_MEMORY_SPACE + ); + return EFI_SUCCESS; +} + +/** + This function checks if function disable (static and non-static power ga= ting) + configuration is locked + + @retval lock state +**/ +BOOLEAN +PmcIsFunctionDisableConfigLocked ( + VOID + ) +{ + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_1) & = B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK) !=3D 0); +} + +/** + Check if MODPHY SUS PG is supported + + @retval Status of MODPHY SUS PG support +**/ +BOOLEAN +PmcIsModPhySusPgSupported ( + VOID + ) +{ + if (IsPchLp ()) { + // + // MPHY SUS PG supported on PCH-LP only: + // + return TRUE; + } + return FALSE; +} + +/** + This function checks if ISH is function disabled + by static power gating + + @retval ISH device state +**/ +BOOLEAN +PmcIsIshFunctionDisabled ( + VOID + ) +{ + // + // Get PG info from PWRMBASE + ST_PG_FDIS_PMC_1 + // + return ((MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_= PMC_1)) & B_PMC_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC) !=3D 0); +} + +/** + This function checks if ISH device is supported (not disabled by fuse) + + @retval ISH support state +**/ +BOOLEAN +PmcIsIshSupported ( + VOID + ) +{ + // + // Get fuse info from PWRMBASE + FUSE_DIS_RD_2 + // + return ((MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD= _2)) & B_PMC_PWRM_FUSE_DIS_RD_2_ISH_FUSE_SS_DIS) =3D=3D 0); +} + +/** + This function disables ISH device by static power gating. + For static power gating to take place Global Reset, G3 or DeepSx transit= ion must happen. +**/ +VOID +PmcStaticDisableIsh ( + VOID + ) +{ + // + // Set PWRMBASE + ST_PG_FDIS_PMC_1[5] =3D 1b to statically disable ISH C= ontroller + // + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_1, B_PMC_PWRM_ST= _PG_FDIS_PMC_1_ISH_FDIS_PMC); +} + +/** + This function enables ISH device by disabling static power gating. + Static power gating disabling takes place after Global Reset, G3 or Deep= Sx transition. +**/ +VOID +PmcEnableIsh ( + VOID + ) +{ + // + // Set PWRMBASE + ST_PG_FDIS_PMC_1[5] =3D 0b to enable ISH controller + // + MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_1, (UINT32) (~B= _PMC_PWRM_ST_PG_FDIS_PMC_1_ISH_FDIS_PMC)); +} + +/** + This function checks if GbE is function disabled + by static power gating + + @retval GbE device state +**/ +BOOLEAN +PmcIsGbeFunctionDisabled ( + VOID + ) +{ + // + // Get PG info from PWRMBASE + ST_PG_FDIS_PMC_1 + // + return ((MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_= PMC_1)) & B_PMC_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC) !=3D 0); +} + +/** + This function disables GbE device by static power gating and enables Mod= PHY SPD gating (PCH-LP only). + For static power gating to take place Global Reset, G3 or DeepSx transit= ion must happen. +**/ +VOID +PmcStaticDisableGbe ( + VOID + ) +{ + UINT32 PchPwrmBase; + PchPwrmBase =3D PmcGetPwrmBase (); + // + // Set PWRMBASE + ST_PG_FDIS_PMC_1[0] =3D 1b to statically disable GbE C= ontroller + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_ST_PG_FDIS_PMC_1, B_PMC_PWRM_ST_PG_FD= IS_PMC_1_GBE_FDIS_PMC); + + if (PmcIsModPhySusPgSupported ()) { + // + // Set MSPDRTREQ: + // PWRMBASE + R_PWRM_MODPHY_PM_CFG5[13] =3D 1 to enable ASL code trigg= er request for ModPHY SPD gating. + // + PmcGbeModPhyPowerGating (); + } +} + +/** + This function enables GbE device by disabling static power gating. + Static power gating disabling takes place after Global Reset, G3 or Deep= Sx transition. +**/ +VOID +PmcEnableGbe ( + VOID + ) +{ + // + // Set PWRMBASE + ST_PG_FDIS_PMC_1[0] =3D 0b to enable GbE controller + // + MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_1, (UINT32) ~B_= PMC_PWRM_ST_PG_FDIS_PMC_1_GBE_FDIS_PMC); +} + +/** + This function checks if GbE device is supported (not disabled by fuse) + + @retval GbE support state +**/ +BOOLEAN +PmcIsGbeSupported ( + VOID + ) +{ + // + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS) =3D=3D 0); +} + +/** + This function disables (non-static power gating) HDA device +**/ +VOID +PmcDisableHda ( + VOID + ) +{ + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_NST_PG_FDIS_1, B_PMC_PWRM_NST_P= G_FDIS_1_ADSP_FDIS_PMC); +} + +/** + This function checks if Cnvi device is supported (not disabled by fuse) + + @retval Cnvi support state +**/ +BOOLEAN +PmcIsCnviSupported ( + VOID + ) +{ + // + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_CNVI_FUSE_SS_DIS) =3D=3D 0); +} + +/** + This function checks if CNVi is function disabled + by static power gating + + @retval GbE device state +**/ +BOOLEAN +PmcIsCnviFunctionDisabled ( + VOID + ) +{ + // + // Get PG info from PWRMBASE + ST_PG_FDIS_PMC_1 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_1) & = B_PMC_PWRM_ST_PG_FDIS_PMC_1_CNVI_FDIS_PMC) !=3D 0); +} + +/** + This function enables CNVi device by disabling static power gating. + Static power gating disabling takes place after Global Reset, G3 or Deep= Sx transition. +**/ +VOID +PmcEnableCnvi ( + VOID + ) +{ + // + // Set PWRMBASE + ST_PG_FDIS_PMC_1 to enable CNVi controller + // + MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_1, (UINT32) ~B_= PMC_PWRM_ST_PG_FDIS_PMC_1_CNVI_FDIS_PMC); +} + +/** + This function disables CNVi device by static power gating. + For static power gating to take place Global Reset, G3 or DeepSx transit= ion must happen. +**/ +VOID +PmcStaticDisableCnvi ( + VOID + ) +{ + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_1, B_PMC_PWRM_ST= _PG_FDIS_PMC_1_CNVI_FDIS_PMC); +} + +/** + This function disables (non-static power gating) PCIe Root Port and enab= les ModPHY SPD gating (PCH-LP only). + + @param[in] RpIndex PCIe Root Port Index (0 based) +**/ +VOID +PmcDisablePcieRootPort ( + IN UINT32 RpIndex + ) +{ + UINT32 NstPgFdis1Mask; + UINT32 PchPwrmBase; + + PchPwrmBase =3D PmcGetPwrmBase (); + // + // Set PchPwrmBase + NST_PG_FDIS_1 to function disable PCIE port in PMC + // + if (IsPchH () && RpIndex >=3D 20) { + NstPgFdis1Mask =3D B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_PCIE_F0_FDIS_PMC << = (RpIndex % 20); + } else { + NstPgFdis1Mask =3D B_PMC_PWRM_NST_PG_FDIS_1_PCIE_A0_FDIS_PMC << RpInde= x; + } + MmioOr32 (PchPwrmBase + R_PMC_PWRM_NST_PG_FDIS_1, NstPgFdis1Mask); + + if (PmcIsModPhySusPgSupported ()) { + // + // Set MSPDRTREQ: + // PWRMBASE + R_PWRM_MODPHY_PM_CFG5[26:0] =3D 1 to enable ASL code tri= gger request for ModPHY SPD gating. + // + if (RpIndex <=3D 11) { + MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY= _PM_CFG5_MSPDRTREQ_A0 << RpIndex); + } else { + MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY= _PM_CFG5_MSPDRTREQ_D0 << (RpIndex - 12)); + } + } +} + +/** + This function disables (non-static power gating) xHCI and enables ModPHY= SPD gating (PCH-LP only). +**/ +VOID +PmcDisableXhci ( + VOID + ) +{ + UINT32 PchPwrmBase; + PchPwrmBase =3D PmcGetPwrmBase (); + + // + // Set PWRMBASE + NST_PG_FDIS_1 [0] =3D 1b + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_NST_PG_FDIS_1, B_PMC_PWRM_NST_PG_FDIS= _1_XHCI_FDIS_PMC); + + if (PmcIsModPhySusPgSupported ()) { + // + // Set MSPDRTREQ: + // PchPwrmBase + R_PWRM_MODPHY_PM_CFG5[14] =3D 1 to enable ASL code tr= igger request for ModPHY SPD gating. + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY_P= M_CFG5_MSPDRTREQ_XHCI); + } +} + +/** + This function disables (non-static power gating) XDCI and enables ModPHY= SPD gating (PCH-LP only). +**/ +VOID +PmcDisableXdci ( + VOID + ) +{ + UINT32 PchPwrmBase; + PchPwrmBase =3D PmcGetPwrmBase (); + + // + // Set PWRMBASE + NST_PG_FDIS_1 [26] =3D 1b to disable XDCI Controller i= n PMC + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_NST_PG_FDIS_1, B_PMC_PWRM_NST_PG_FDIS= _1_XDCI_FDIS_PMC); + + if (PmcIsModPhySusPgSupported ()) { + // + // Set MSPDRTREQ: + // PWRMBASE + R_PWRM_MODPHY_PM_CFG5[15] =3D 1 to enable ASL code trigg= er request for ModPHY SPD gating. + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY_P= M_CFG5_MSPDRTREQ_XDCI); + } +} + +/** + This function checks if XDCI device is supported (not disabled by fuse) + + @retval XDCI support state +**/ +BOOLEAN +PmcIsXdciSupported ( + VOID + ) +{ + // + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_OTG_FUSE_SS_DIS) =3D=3D 0); +} + +/** + This function locks HOST SW power gating control +**/ +VOID +PmcLockHostSwPgCtrl ( + VOID + ) +{ + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_HSWPGCR1, B_PMC_PWRM_SW_PG_CTRL= _LOCK); +} + +/** + This function checks if HOST SW Power Gating Control is locked + + @retval lock state +**/ +BOOLEAN +PmcIsHostSwPgCtrlLocked ( + VOID + ) +{ + // + // Get lock info from PWRMBASE + HSWPGCR1 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_HSWPGCR1) & B_PMC_PW= RM_SW_PG_CTRL_LOCK) !=3D 0); +} + +/** + This function checks if LAN wake from DeepSx is enabled + + @retval Lan Wake state +**/ +BOOLEAN +PmcIsLanDeepSxWakeEnabled ( + VOID + ) +{ + // + // Get wake info from PWRMBASE + DSX_CFG + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_DSX_CFG) & (UINT32) = B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN) !=3D 0); +} + +/** + Disables USB2 Core PHY PowerGating during power on for Chipsetinit table= update +**/ +VOID +PmcUsb2CorePhyPowerGatingDisable ( + VOID + ) +{ + MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_CFG, (UINT32) ~B_PMC_PWRM_CFG_= ALLOW_USB2_CORE_PG); +} + + +/** + This function reads CPU Early Power-on Configuration (EPOC) + + @retval CPU EPOC value +**/ +UINT32 +PmcGetCpuEpoc ( + VOID + ) +{ + return MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_CPU_EPOC); +} + +/** + This function sets CPU Early Power-on Configuration (EPOC) + + @param[in] CpuEpocValue CPU EPOC value +**/ +VOID +PmcSetCpuEpoc ( + IN UINT32 CpuEpocValue + ) +{ + MmioWrite32 (PmcGetPwrmBase () + R_PMC_PWRM_CPU_EPOC, CpuEpocValue); +} + +/** + This function sets DRAM_RESET# Control Pin value + + @param[in] DramResetVal 0: Pin output is low + 1: Pin output is tri-stated +**/ +VOID +PmcSetDramResetCtlState ( + IN UINT32 DramResetVal + ) +{ + ASSERT (DramResetVal < 2); + + MmioAndThenOr32 ( + PmcGetPwrmBase () + R_PMC_PWRM_CFG2, + (UINT32)~B_PMC_PWRM_CFG2_DRAM_RESET_CTL, + DramResetVal << N_PMC_PWRM_CFG2_DRAM_RESET_CTL + ); +} + +/** + This function enables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh +**/ +VOID +PmcEnableCf9GlobalReset ( + VOID + ) +{ + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_ETR3, (UINT32) (B_PMC_PWRM_ETR3= _CF9GR)); +} + +/** + This function disables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh. +**/ +VOID +PmcDisableCf9GlobalReset ( + VOID + ) +{ + MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_ETR3, (UINT32) ~B_PMC_PWRM_ETR= 3_CF9GR); +} + +/** + This function disables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh. + Global Reset configuration is locked after programming +**/ +VOID +PmcDisableCf9GlobalResetWithLock ( + VOID + ) +{ + MmioAndThenOr32 ( + PmcGetPwrmBase () + R_PMC_PWRM_ETR3, + (UINT32) ~B_PMC_PWRM_ETR3_CF9GR, + (UINT32) B_PMC_PWRM_ETR3_CF9LOCK + ); +} + +/** + This function disables CF9 reset without Resume Well reset. + Cf9 0x6/0xE reset will also reset resume well logic. +**/ +VOID +PmcDisableCf9ResetWithoutResumeWell ( + VOID + ) +{ + + MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_ETR3, (UINT32) ~B_PMC_PWRM_ETR= 3_CWORWRE); +} + +/** + This function clears RTC Power Failure status (RTC_PWR_FLR) +**/ +VOID +PmcClearRtcPowerFailureStatus ( + VOID + ) +{ + // + // Set B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS to 0 to clear it. + // + MmioAnd8 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B), (UINT8) = (~B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS)); +} + +/** + This function enables PCI Express* PME events +**/ +VOID +PmcEnablePciExpressPmeEvents ( + VOID + ) +{ + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B, B_PMC_PWRM_GEN_PMC= ON_B_BIOS_PCI_EXP_EN); +} + +/** + This function sets eSPI SMI Lock +**/ +VOID +PmcLockEspiSmi ( + VOID + ) +{ + MmioAndThenOr8 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1, + (UINT8) ~((B_PMC_PWRM_GEN_PMCON_A_PWR_FLR | B_PMC_PWRM_GEN_PMCON_A_HOS= T_RST_STS) >> 8), + B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK >> 8 + ); +} + +/** + This function checks if eSPI SMI Lock is set + + @retval eSPI SMI Lock state +**/ +BOOLEAN +PmcIsEspiSmiLockSet ( + VOID + ) +{ + return ((MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A= )) & B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK) !=3D 0); +} + +/** + This function sets SW SMI Rate. + + @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values +**/ +VOID +PmcSetSwSmiRate ( + IN PMC_SWSMI_RATE SwSmiRate + ) +{ + UINT32 PchPwrmBase; + STATIC UINT8 SwSmiRateRegVal[4] =3D { + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS, + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS, + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS, + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS + }; + + ASSERT (SwSmiRate <=3D PmcSwSmiRate64ms); + + PchPwrmBase =3D PmcGetPwrmBase (); + + // + // SWSMI_RATE_SEL BIT (PWRMBASE offset 1020h[7:6]) bits are in RTC well + // + MmioAndThenOr8 ( + PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, + (UINT8)~B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL, + SwSmiRateRegVal[SwSmiRate] + ); +} + +/** + This function sets Periodic SMI Rate. + + @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for pos= sible values +**/ +VOID +PmcSetPeriodicSmiRate ( + IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate + ) +{ + UINT32 PchPwrmBase; + STATIC UINT8 PeriodicSmiRateRegVal[4] =3D { + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S, + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S, + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S, + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S + }; + + ASSERT (PeriodicSmiRate <=3D PmcPeriodicSmiRate64s); + + PchPwrmBase =3D PmcGetPwrmBase (); + + MmioAndThenOr8 ( + PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, + (UINT8)~B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL, + PeriodicSmiRateRegVal[PeriodicSmiRate] + ); +} + +/** + This function reads Power Button Level + + @retval State of PWRBTN# signal (0: Low, 1: High) +**/ +UINT8 +PmcGetPwrBtnLevel ( + VOID + ) +{ + if (MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_PWRM= _GEN_PMCON_B_PWRBTN_LVL) { + return 1; + } else { + return 0; + } +} + +/** + This function gets Group to GPE0 configuration + + @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment + @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment + @param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment +**/ +VOID +PmcGetGpioGpe ( + OUT UINT32 *GpeDw0Value, + OUT UINT32 *GpeDw1Value, + OUT UINT32 *GpeDw2Value + ) +{ + UINT32 Data32; + + Data32 =3D MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GPIO_CFG)= ); + + *GpeDw0Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW0) >> N_PMC_PWRM_= GPIO_CFG_GPE0_DW0); + *GpeDw1Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW1) >> N_PMC_PWRM_= GPIO_CFG_GPE0_DW1); + *GpeDw2Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW2) >> N_PMC_PWRM_= GPIO_CFG_GPE0_DW2); +} + +/** + This function sets Group to GPE0 configuration + + @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment + @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment + @param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment +**/ +VOID +PmcSetGpioGpe ( + IN UINT32 GpeDw0Value, + IN UINT32 GpeDw1Value, + IN UINT32 GpeDw2Value + ) +{ + UINT32 Data32Or; + UINT32 Data32And; + + // + // Program GPIO_CFG register + // + Data32And =3D (UINT32) ~(B_PMC_PWRM_GPIO_CFG_GPE0_DW2 | B_PMC_PWRM_GPIO_= CFG_GPE0_DW1 | B_PMC_PWRM_GPIO_CFG_GPE0_DW0); + Data32Or =3D (UINT32) ((GpeDw2Value << N_PMC_PWRM_GPIO_CFG_GPE0_DW2) | + (GpeDw1Value << N_PMC_PWRM_GPIO_CFG_GPE0_DW1) | + (GpeDw0Value << N_PMC_PWRM_GPIO_CFG_GPE0_DW0)); + + MmioAndThenOr32 ( + (PmcGetPwrmBase () + R_PMC_PWRM_GPIO_CFG), + Data32And, + Data32Or + ); +} + +/** + Disable SLP_S0# assertion when system is in debug mode +**/ +VOID +PmcDisableSlpS0AssertionInDebugMode ( + VOID + ) +{ + EFI_STATUS Status; + PMC_IPC_COMMAND_BUFFER Wbuf; + + ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER)); + + Status =3D PmcSendCommand (V_PMC_PWRM_IPC_CMD_COMMAND_SLP_CTRL, 0, 4, &W= buf, NULL); + ASSERT_EFI_ERROR (Status); +} + +/** + Enable SLP_S0# assertion even when system is in debug mode +**/ +VOID +PmcEnableSlpS0AssertionInDebugMode ( + VOID + ) +{ + EFI_STATUS Status; + PMC_IPC_COMMAND_BUFFER Wbuf; + + ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER)); + + Wbuf.Buf0 =3D 1; + Status =3D PmcSendCommand (V_PMC_PWRM_IPC_CMD_COMMAND_SLP_CTRL, 0, 4, &W= buf, NULL); + ASSERT_EFI_ERROR (Status); +} + +/** + This function gets NMI regsiter. + + @retval NMI register setting +**/ +UINT32 +PmcGetNmiControl ( + VOID + ) +{ + EFI_STATUS Status; + PMC_IPC_COMMAND_BUFFER Wbuf; + PMC_IPC_COMMAND_BUFFER Rbuf; + + ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER)); + ZeroMem (&Rbuf, sizeof (PMC_IPC_COMMAND_BUFFER)); + // + // WBUF0 =3D 2 for NMI delivery control and status register (entire regi= ster PCR[ITSS] 0x3330) + // + Wbuf.Buf0 =3D V_PMC_PWRM_IPC_CMD_WBUF0_PROXY_NMI; + Status =3D PmcSendCommand ( + V_PMC_PWRM_IPC_CMD_COMMAND_PROXY, + V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_READ, + 4, + &Wbuf, + &Rbuf + ); + ASSERT_EFI_ERROR (Status); + return Rbuf.Buf0; +} + +/** + This function sets the NMI register + + @param[in] NmiRegister The whole NMI register +**/ +VOID +PmcSetNmiControl ( + UINT32 NmiRegister + ) +{ + EFI_STATUS Status; + PMC_IPC_COMMAND_BUFFER Wbuf; + + ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER)); + // + // WBUF0 =3D 2 for NMI delivery control and status register (entire regi= ster PCR[ITSS] 0x3330) + // + Wbuf.Buf0 =3D V_PMC_PWRM_IPC_CMD_WBUF0_PROXY_NMI; + Wbuf.Buf1 =3D NmiRegister; + Status =3D PmcSendCommand ( + V_PMC_PWRM_IPC_CMD_COMMAND_PROXY, + V_PMC_PWRM_IPC_CMD_CMD_ID_PROXY_WRITE, + 8, + &Wbuf, + NULL + ); + ASSERT_EFI_ERROR (Status); +} + +/** + This function enables GBE ModPHY SPD gating. +**/ +VOID +PmcGbeModPhyPowerGating ( + VOID + ) +{ + if (PmcIsModPhySusPgSupported ()) { + // + // Set B_PCH_PWRM_MODPHY_PM_CFG5_MSPDRTREQ_GBE ModPHY SPD RT Request + // + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MO= DPHY_PM_CFG5_MSPDRTREQ_GBE); + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PmcPrivateLibClient.c b/Silicon/Intel/CoffeelakeSiliconPkg/= Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PmcPrivateLibClient.c new file mode 100644 index 0000000000..2411a2be23 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PmcPrivateLibClient.c @@ -0,0 +1,73 @@ +/** @file + PCH PMC Private Library implementation for Cannon Lake PCH. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PmcPrivateLibInternal.h" + +/** + This function disables (non-static power gating) SATA and enables ModPHY= SPD gating (PCH-LP only). + + @param[in] SataCtrlIndex SATA controller index +**/ +VOID +PmcDisableSata ( + IN UINT32 SataCtrlIndex + ) +{ + UINT32 PchPwrmBase; + PchPwrmBase =3D PmcGetPwrmBase (); + + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + // + // Set PWRMBASE + NST_PG_FDIS_1 [22] =3D 1b to disable SATA Controller i= n PMC + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_NST_PG_FDIS_1, B_PMC_PWRM_NST_PG_FDIS= _1_SATA_FDIS_PMC); + + if (PmcIsModPhySusPgSupported ()) { + // + // MPHY SUS PG supported on PCH-LP only: + // + // Set MSPDRTREQ: + // PWRMBASE + R_PWRM_MODPHY_PM_CFG5[12] =3D 1 to enable ASL code trigg= er request for ModPHY SPD gating. + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY_P= M_CFG5_MSPDRTREQ_SATA); + } +} + +/** + This function checks if SATA device is supported (not disabled by fuse) + + @param[in] SataCtrlIndex SATA controller index + + @retval SATA support state +**/ +BOOLEAN +PmcIsSataSupported ( + UINT32 SataCtrlIndex + ) +{ + ASSERT (SataCtrlIndex < GetPchMaxSataControllerNum ()); + + // + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_SATA_FUSE_SS_DIS) =3D=3D 0); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PmcPrivateLibCnl.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch= /Library/Private/PeiDxeSmmPmcPrivateLib/PmcPrivateLibCnl.c new file mode 100644 index 0000000000..847be42937 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PmcPrivateLibCnl.c @@ -0,0 +1,360 @@ +/** @file + PCH PMC Private Library implementation for Cannon Lake PCH. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PmcPrivateLibInternal.h" + +/** + This function disables Trace Hub by enabling power gating +**/ +VOID +PmcDisableTraceHub ( + VOID + ) +{ + EFI_STATUS Status; + PMC_IPC_COMMAND_BUFFER Wbuf; + + ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER)); + + Wbuf.Buf0 =3D BIT0; + Status =3D PmcSendCommand (V_PMC_PWRM_IPC_CMD_COMMAND_NPK_STATE, 0, 4, &= Wbuf, NULL); + ASSERT_EFI_ERROR (Status); +} + +/** + This function enables Trace Hub by disabling power gating +**/ +VOID +PmcEnableTraceHub ( + VOID + ) +{ + EFI_STATUS Status; + PMC_IPC_COMMAND_BUFFER Wbuf; + + ZeroMem (&Wbuf, sizeof (PMC_IPC_COMMAND_BUFFER)); + + Wbuf.Buf0 =3D BIT1; + Status =3D PmcSendCommand (V_PMC_PWRM_IPC_CMD_COMMAND_NPK_STATE, 0, 4, &= Wbuf, NULL); + ASSERT_EFI_ERROR (Status); +} + +/** + This function is part of PMC init and configures which clock wake signal= s should + set the SLOW_RING, SA, FAST_RING_CF and SLOW_RING_CF indication sent up = to the CPU/PCH +**/ +VOID +PmcInitClockWakeEnable ( + VOID + ) +{ + UINT32 PchPwrmBase; + + PchPwrmBase =3D PmcGetPwrmBase (); + if (IsPchLp () && (PchStepping () < PCH_B0)) { + /// + /// PWRMBASE + 0x1880 =3D 0x0 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING, 0x0); + } else { + /// + /// PWRMBASE + 0x1880 =3D 0x2F8FBB01 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING, 0x2F8FBB01); + } + + if (IsPchLp ()) { + if (PchStepping () < PCH_B0) { + /// + /// PWRMBASE + 0x1884 =3D 0x0 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0); + } else { + /// + /// PWRMBASE + 0x1884 + /// PCH-LP: 0x0280C7E1 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0280C7E1); + } + } else { + /// + /// PWRMBASE + 0x1884 + /// PCH-H: 0x0280D7E1 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING2, 0x0280D7E1); + } + + if (IsPchLp () && (PchStepping () < PCH_B0)) { + /// + /// PWRMBASE + 0x1888 =3D 0x0 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA, 0x0); + /// + /// PWRMBASE + 0x188C =3D 0x0 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0); + } else { + /// + /// PWRMBASE + 0x1888 =3D 0x2F8FAB01 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA, 0x2F8FAB01); + + /// + /// PWRMBASE + 0x188C + /// PCH-LP: 0x0280C7E1 + /// PCH-H: 0x0280D7E1 + /// + if (IsPchLp ()) { + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0280C7E1); + } else { + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SA2, 0x0280D7E1); + } + } + + if (IsPchLp () && (PchStepping () < PCH_B0)) { + /// + /// PWRMBASE + 0x1898 =3D 0x0 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING_CF, 0x0); + } else { + /// + /// PWRMBASE + 0x1898 =3D 0x00018000 + /// + MmioWrite32 (PchPwrmBase + R_PMC_PWRM_EN_CW_SLOW_RING_CF, 0x00018000); + } +} + +/** + This function configures PWRMBASE + 0x1E00 register +**/ +VOID +PmcConfigureRegPwrm1E00 ( + VOID + ) +{ + /// + /// PWRMBASE + 0x1E00[31,30] =3D 1,1 + /// PWRMBASE + 0x1E00[29] =3D 0 + /// PWRMBASE + 0x1E00[10:6] =3D 0 + /// PWRMBASE + 0x1E00[3:0] =3D 2 + /// + MmioAndThenOr32 ( + PmcGetPwrmBase () + R_PMC_PWRM_1E00, + (UINT32) ~(BIT29 | (0x1F << 6) | 0xF), + BIT31 | BIT30 | 2 + ); +} + +/** + This function configures Misc PM_SYNC events settings +**/ +VOID +PmcConfigurePmSyncEventsSettings ( + VOID + ) +{ + /// + /// PWRMBASE + 0x18C0 =3D 0x00000A20 + /// + MmioWrite32 (PmcGetPwrmBase () + R_PMC_PWRM_EN_MISC_EVENT, 0x00000A20); +} + +/** + This function enables all SerailIo devices. + Static power gating disabling takes place after Global Reset, G3 or Deep= Sx transition. +**/ +VOID +PmcEnableSerialIo ( + VOID + ) +{ + // + // Set PWRMBASE + ST_PG_FDIS_PMC_2 + // + MmioAnd32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2, (UINT32)~B_P= MC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO); +} + +/** + This function disables (static power gating) all SerailIo devices. + For SerialIo controllers they can be power gated only if all of them are= to be disabled. + They cannot be statically power gated separately. + For static power gating to take place Global Reset, G3 or DeepSx transit= ion must happen. +**/ +VOID +PmcStaticDisableSerialIo ( + VOID + ) +{ + // + // Set PWRMBASE + ST_PG_FDIS_PMC_2 + // + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2, B_PMC_PWRM_ST= _PG_FDIS_PMC_2_SERIALIO); +} + +/** + This function checks if all SerialIo devices are statically disabled (st= atic power gating) + + @retval SerialIo disable state +**/ +BOOLEAN +PmcIsSerialIoStaticallyDisabled ( + VOID + ) +{ + // + // Check if all SerialIo controllers are statically disabled in PMC + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_ST_PG_FDIS_PMC_2) & = B_PMC_PWRM_ST_PG_FDIS_PMC_2_SERIALIO) =3D=3D B_PMC_PWRM_ST_PG_FDIS_PMC_2_SE= RIALIO); +} + +/** + This function checks if SerialIo device is supported (not disabled by fu= se) + + @retval SerialIo support state +**/ +BOOLEAN +PmcIsSerialIoSupported ( + VOID + ) +{ + // + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_SERIALIO_FUSE_SS_DIS) =3D=3D 0); +} + +/** + This function disables (non-static power gating) SCS eMMC controller and= enables ModPHY SPD gating (PCH-LP only). +**/ +VOID +PmcDisableScsEmmc ( + VOID + ) +{ + ASSERT (IsPchLp ()); + + // + // Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC + // + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_NST_PG_FDIS_1, B_PCH_LP_PMC_PWR= M_NST_PG_FDIS_1_EMMC_FDIS_PMC); +} + +/** + This function disables (non-static power gating) SCS SD Card controller = and enables ModPHY SPD gating (PCH-LP only). +**/ +VOID +PmcDisableScsSdCard ( + VOID + ) +{ + UINT32 ScsDevicePgMask; + + if (IsPchLp ()) { + ScsDevicePgMask =3D B_PCH_LP_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC; + } else { + ScsDevicePgMask =3D B_PCH_H_PMC_PWRM_NST_PG_FDIS_1_SDCARD_FDIS_PMC; + } + + // + // Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC + // + MmioOr32 (PmcGetPwrmBase () + R_PMC_PWRM_NST_PG_FDIS_1, ScsDevicePgMask); +} + +/** + This function disables (non-static power gating) SCS UFS controller and = enables ModPHY SPD gating (PCH-LP only). + + @param[in] UfsNum SCS UFS Device +**/ +VOID +PmcDisableScsUfs ( + IN UINT32 UfsNum + ) +{ + UINT32 PchPwrmBase; + + ASSERT ((UfsNum =3D=3D 0) && IsPchLp ()); + + PchPwrmBase =3D PmcGetPwrmBase (); + + // + // Set PWRMBASE + NST_PG_FDIS_1 to disable SCS Controller in PMC + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_NST_PG_FDIS_1, B_PCH_LP_PMC_PWRM_NST_= PG_FDIS_1_UFS_FDIS_PMC); + + if (PmcIsModPhySusPgSupported ()) { + // + // Set MSPDRTREQ: + // PchPwrmBase + R_PWRM_MODPHY_PM_CFG5[16] =3D 1 to enable ASL code tr= igger request for ModPHY SPD gating. + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_MODPHY_PM_CFG5, B_PMC_PWRM_MODPHY_P= M_CFG5_MSPDRTREQ_UFS2); + } +} + +/** + This function checks if SCS eMMC device is supported (not disabled by fu= se) + + @retval SCS device support state +**/ +BOOLEAN +PmcIsScsEmmcSupported ( + VOID + ) +{ + // + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_EMMC_FUSE_SS_DIS) =3D=3D 0); +} + +/** + This function checks if SCS SD Card device is supported (not disabled by= fuse) + + @retval SCS device support state +**/ +BOOLEAN +PmcIsScsSdCardSupported ( + VOID + ) +{ + // + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_SDX_FUSE_SS_DIS) =3D=3D 0); +} + +/** + This function checks if SCS UFS device is supported (not disabled by fus= e) + + @param[in] UfsNum SCS UFS Device + + @retval SCS device support state +**/ +BOOLEAN +PmcIsScsUfsSupported ( + IN UINT32 UfsNum + ) +{ + // + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2 + // + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_UFSX2_FUSE_SS_DIS) =3D=3D 0); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeS= mmPmcPrivateLib/PmcPrivateLibWithS3.c b/Silicon/Intel/CoffeelakeSiliconPkg/= Pch/Library/Private/PeiDxeSmmPmcPrivateLib/PmcPrivateLibWithS3.c new file mode 100644 index 0000000000..bbe944da5c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiDxeSmmPmcPr= ivateLib/PmcPrivateLibWithS3.c @@ -0,0 +1,194 @@ +/** @file + PCH private PMC Library. + All function in this library is available for PEI, DXE, and SMM, + But do not support UEFI RUNTIME environment call. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + This function locks down PMC (DebugModeLock) +**/ +VOID +PmcLockWithS3BootScript ( + VOID + ) +{ + + UINT32 PchPwrmBase; + + PchPwrmBase =3D PmcGetPwrmBase (); + + // + // Set PWRM_CFG[27] prior to OS. + // + MmioOr32 (PchPwrmBase + R_PMC_PWRM_CFG, B_PMC_PWRM_CFG_DBG_MODE_LOCK); + + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (PchPwrmBase + R_PMC_PWRM_CFG), + 1, + (VOID *) ((UINTN) PchPwrmBase + R_PMC_PWRM_CFG) + ); + +} + +/** + This S3 BootScript only function disables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh. +**/ +VOID +PmcDisableCf9GlobalResetInS3BootScript ( + VOID + ) +{ + UINT32 Data; + + UINT32 PchPwrmBase; + PchPwrmBase =3D PmcGetPwrmBase (); + + Data =3D MmioRead32 (PchPwrmBase + R_PMC_PWRM_ETR3); + + Data &=3D (UINT32) ~B_PMC_PWRM_ETR3_CF9GR; + + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) PchPwrmBase + + R_PMC_PWRM_ETR3, + 1, + &Data + ); +} + +/** + This S3 BootScript only function disables triggering Global Reset of both + the Host and the ME partitions after CF9h write of 6h or Eh. + Global Reset configuration is locked after programming +**/ +VOID +PmcDisableCf9GlobalResetWithLockInS3BootScript ( + VOID + ) +{ + UINT32 Data; + + UINT32 PchPwrmBase; + PchPwrmBase =3D PmcGetPwrmBase (); + + Data =3D MmioRead32 (PchPwrmBase + R_PMC_PWRM_ETR3); + + Data &=3D (UINT32) ~B_PMC_PWRM_ETR3_CF9GR; + Data |=3D (UINT32) B_PMC_PWRM_ETR3_CF9LOCK; + + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) PchPwrmBase + + R_PMC_PWRM_ETR3, + 1, + &Data + ); +} + +/** + This function sets SLP_SX Stretching Policy and adds + lock setting to S3 Boot Script +**/ +VOID +PmcLockSlpSxStretchingPolicyWithS3BootScript ( + VOID + ) +{ + UINT32 PchPwrmBase; + + PchPwrmBase =3D PmcGetPwrmBase (); + + MmioOr8 ( + (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B + 2), + (UINT8) ((B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK) >> 16) + ); + + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint8, + (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B + 2), + 1, + (VOID *) ((UINTN) PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B + 2) + ); +} + +/** + This function sets SMI Lock with S3 Boot Script programming +**/ +VOID +PmcLockSmiWithS3BootScript ( + VOID + ) +{ + UINT32 PchPwrmBase; + + PchPwrmBase =3D PmcGetPwrmBase (); + + MmioOr8 ((PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B), B_PMC_PWRM_GEN_PMCON_B_= SMI_LOCK); + + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint8, + (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B), + 1, + (VOID *) ((UINTN) PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B) + ); +} + +/** + This function locks static power gating configuration with S3 Boot Scrip= t programming +**/ +VOID +PmcLockFunctionDisableConfigWithS3BootScript ( + VOID + ) +{ + UINT32 PchPwrmBase; + + PchPwrmBase =3D PmcGetPwrmBase (); + + MmioOr32 (PchPwrmBase + R_PMC_PWRM_ST_PG_FDIS_PMC_1, (UINT32) (B_PMC_PWR= M_ST_PG_FDIS_PMC_1_ST_FDIS_LK)); + + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint8, + (UINTN) (PchPwrmBase + R_PMC_PWRM_ST_PG_FDIS_PMC_1), + 1, + (VOID *) (UINTN) (PchPwrmBase + R_PMC_PWRM_ST_PG_FDIS_PMC_1) + ); +} + +/** + This function locks PMC Set Strap Message interface with S3 Boot Script = programming +**/ +VOID +PmcLockSetStrapMsgInterfaceWithS3BootScript ( + VOID + ) +{ + UINT32 PchPwrmBase; + + PchPwrmBase =3D PmcGetPwrmBase (); + + MmioOr32 ((UINTN) (PchPwrmBase + R_PMC_PWRM_SSML), B_PMC_PWRM_SSML_SSL); + + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint8, + (UINTN) (PchPwrmBase + R_PMC_PWRM_SSML), + 1, + (VOID *) (UINTN) (PchPwrmBase + R_PMC_PWRM_SSML) + ); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpio= HelpersLib/PeiGpioHelpersLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Lib= rary/Private/PeiGpioHelpersLib/PeiGpioHelpersLib.c new file mode 100644 index 0000000000..9c722bce07 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpioHelpers= Lib/PeiGpioHelpersLib.c @@ -0,0 +1,356 @@ +/** @file + This file contains routines for PEI GPIO Helpers Lib + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern EFI_GUID gGpioLibUnlockHobGuid; + +// +// GPIO Lock HOB +// Stores information on GPIO pads that should be left unlocked +// +typedef struct { + // + // GPIO PadConfig unlock data + // + UINT32 PadConfig; + // + // GPIO Output unlock data + // + UINT32 OutputState; +} GPIO_UNLOCK_HOB_DATA; + +/** + This procedure will get index of GPIO Unlock HOB structure for selected = GroupIndex and DwNum. + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + + @retval GpioUnlockHobIndex +**/ +STATIC +UINT32 +GpioUnlockDataIndex ( + IN UINT32 GroupIndex, + IN UINT32 DwNum + ) +{ + UINT32 GpioUnlockDataIndex; + UINT32 Index; + + GpioUnlockDataIndex =3D 0; + + for (Index =3D 0; Index < GroupIndex; Index++) { + GpioUnlockDataIndex +=3D GPIO_GET_DW_NUM (GpioGetPadPerGroup (GpioGetG= roupFromGroupIndex (Index))) + 1; + } + + GpioUnlockDataIndex +=3D DwNum; + return GpioUnlockDataIndex; +} + +/** + This procedure will create GPIO HOB for storing unlock data + + @retval Pointer to GPIO Unlock data structure +**/ +STATIC +GPIO_UNLOCK_HOB_DATA* +GpioCreateUnlockData ( + VOID + ) +{ + VOID *HobData; + GPIO_GROUP Group; + GPIO_GROUP GroupMin; + GPIO_GROUP GroupMax; + UINT32 GpioUnlockDataRecords; + + GroupMin =3D GpioGetLowestGroup (); + GroupMax =3D GpioGetHighestGroup (); + GpioUnlockDataRecords =3D 0; + + for (Group =3D GroupMin; Group <=3D GroupMax; Group++) { + GpioUnlockDataRecords +=3D GPIO_GET_DW_NUM (GpioGetPadPerGroup (Group)= ) + 1; + } + + HobData =3D BuildGuidHob (&gGpioLibUnlockHobGuid, GpioUnlockDataRecords = * sizeof (GPIO_UNLOCK_HOB_DATA)); + if (HobData =3D=3D NULL) { + return NULL; + } + + ZeroMem (HobData, GpioUnlockDataRecords * sizeof (GPIO_UNLOCK_HOB_DATA)); + + return (GPIO_UNLOCK_HOB_DATA*)HobData; +} + +/** + This procedure will Get GPIO Unlock data structure for storing unlock da= ta. + If HOB doesn't exist it will be created. + + @param[out] GpioUnlockData pointer to GPIO Unlock data structure + + @retval Length number of GPIO unlock data records +**/ +STATIC +UINT32 +GpioGetUnlockData ( + GPIO_UNLOCK_HOB_DATA **GpioUnlockData + ) +{ + VOID *Hob; + + Hob =3D GetFirstGuidHob (&gGpioLibUnlockHobGuid); + if (Hob =3D=3D NULL) { + // + // It is the first time this function is used so create the HOB + // + *GpioUnlockData =3D GpioCreateUnlockData (); + if (*GpioUnlockData =3D=3D NULL) { + return 0; + } + Hob =3D GetFirstGuidHob (&gGpioLibUnlockHobGuid); + } else { + *GpioUnlockData =3D (GPIO_UNLOCK_HOB_DATA*) GET_GUID_HOB_DATA (Hob); + } + return GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (GPIO_UNLOCK_HOB_DATA); +} + +/** + This procedure will get pointer to GPIO Unlock data structure. + + @param[out] GpioUnlockData pointer to GPIO Unlock data structure + + @retval Length number of GPIO unlock data records +**/ +STATIC +UINT32 +GpioLocateUnlockData ( + GPIO_UNLOCK_HOB_DATA **GpioUnlockData + ) +{ + VOID *Hob; + + Hob =3D GetFirstGuidHob (&gGpioLibUnlockHobGuid); + if (Hob =3D=3D NULL) { + *GpioUnlockData =3D NULL; + return 0; + } + + *GpioUnlockData =3D (GPIO_UNLOCK_HOB_DATA*) GET_GUID_HOB_DATA (Hob); + return GET_GUID_HOB_DATA_SIZE (Hob) / sizeof (GPIO_UNLOCK_HOB_DATA); +} + +/** + This procedure stores GPIO pad unlock information + + @param[in] GpioPad GPIO pad + @param[in] GpioLockConfig GPIO Lock Configuration + + @retval Status +**/ +EFI_STATUS +GpioStoreUnlockData ( + IN GPIO_PAD GpioPad, + IN GPIO_LOCK_CONFIG GpioLockConfig + ) +{ + GPIO_UNLOCK_HOB_DATA *GpioUnlockData; + UINT32 Length; + UINT32 GroupIndex; + UINT32 PadNumber; + UINT32 Index; + + if (GpioLockConfig =3D=3D GpioLockDefault) { + return EFI_SUCCESS; + } + + Length =3D GpioGetUnlockData (&GpioUnlockData); + if (Length =3D=3D 0) { + return EFI_NOT_FOUND; + } + + GroupIndex =3D GpioGetGroupIndexFromGpioPad (GpioPad); + PadNumber =3D GpioGetPadNumberFromGpioPad (GpioPad); + Index =3D GpioUnlockDataIndex (GroupIndex, GPIO_GET_DW_NUM (PadNumber)); + + if (Index >=3D Length) { + return EFI_INVALID_PARAMETER; + } + + if ((GpioLockConfig & B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK) =3D=3D Gpio= PadConfigUnlock) { + GpioUnlockData[Index].PadConfig |=3D 1 << (GpioGetPadNumberFromGpioPad= (GpioPad) % 32); + } + + if ((GpioLockConfig & B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK) =3D=3D GpioOu= tputStateUnlock) { + GpioUnlockData[Index].OutputState |=3D 1 << (GpioGetPadNumberFromGpioP= ad (GpioPad) % 32); + } + + return EFI_SUCCESS; +} + +/** + This procedure stores GPIO group data about pads which PadConfig needs t= o be unlocked. + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: Skip, 1: Leave unlocked + + @retval Status +**/ +EFI_STATUS +GpioStoreGroupDwUnlockPadConfigData ( + IN UINT32 GroupIndex, + IN UINT32 DwNum, + IN UINT32 UnlockedPads + ) +{ + GPIO_UNLOCK_HOB_DATA *GpioUnlockData; + UINT32 Length; + UINT32 Index; + + if (UnlockedPads =3D=3D 0) { + // + // No pads to be left unlocked + // + return EFI_SUCCESS; + } + + Length =3D GpioGetUnlockData (&GpioUnlockData); + if (Length =3D=3D 0) { + return EFI_NOT_FOUND; + } + + Index =3D GpioUnlockDataIndex (GroupIndex, DwNum); + if (Index >=3D Length) { + return EFI_INVALID_PARAMETER; + } + + GpioUnlockData[Index].PadConfig |=3D UnlockedPads; + return EFI_SUCCESS; +} + +/** + This procedure stores GPIO group data about pads which Output state need= s to be unlocked. + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @param[in] UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: Skip, 1: Leave unlocked + @retval Status +**/ +EFI_STATUS +GpioStoreGroupDwUnlockOutputData ( + IN UINT32 GroupIndex, + IN UINT32 DwNum, + IN UINT32 UnlockedPads + ) +{ + GPIO_UNLOCK_HOB_DATA *GpioUnlockData; + UINT32 Length; + UINT32 Index; + + if (UnlockedPads =3D=3D 0) { + // + // No pads to be left unlocked + // + return EFI_SUCCESS; + } + + Length =3D GpioGetUnlockData (&GpioUnlockData); + if (Length =3D=3D 0) { + return EFI_NOT_FOUND; + } + + Index =3D GpioUnlockDataIndex (GroupIndex, DwNum); + if (Index >=3D Length) { + return EFI_INVALID_PARAMETER; + } + + GpioUnlockData[Index].OutputState |=3D UnlockedPads; + return EFI_SUCCESS; +} + +/** + This procedure will get GPIO group data with pads, which PadConfig is su= pposed to be left unlock + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @retval UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: to be locked, 1: Leave un= locked +**/ +UINT32 +GpioGetGroupDwUnlockPadConfigMask ( + IN UINT32 GroupIndex, + IN UINT32 DwNum + ) +{ + GPIO_UNLOCK_HOB_DATA *GpioUnlockData; + UINT32 Length; + UINT32 Index; + + Length =3D GpioLocateUnlockData (&GpioUnlockData); + if (Length =3D=3D 0) { + return 0; + } + + Index =3D GpioUnlockDataIndex (GroupIndex, DwNum); + if (Index >=3D Length) { + return 0; + } + + return GpioUnlockData[Index].PadConfig; +} + +/** + This procedure will get GPIO group data with pads, which Output is suppo= sed to be left unlock + + @param[in] GroupIndex GPIO group index + @param[in] DwNum DWORD index for a group. + For group which has less then 32 pads pe= r group DwNum must be 0. + @retval UnlockedPads DWORD bitmask for pads which are going t= o be left unlocked + Bit position - PadNumber + Bit value - 0: to be locked, 1: Leave un= locked +**/ +UINT32 +GpioGetGroupDwUnlockOutputMask ( + IN UINT32 GroupIndex, + IN UINT32 DwNum + ) +{ + GPIO_UNLOCK_HOB_DATA *GpioUnlockData; + UINT32 Length; + UINT32 Index; + + Length =3D GpioLocateUnlockData (&GpioUnlockData); + if (Length =3D=3D 0) { + return 0; + } + + Index =3D GpioUnlockDataIndex (GroupIndex, DwNum); + if (Index >=3D Length) { + return 0; + } + + return GpioUnlockData[Index].OutputState; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpio= NameBufferLib/GpioNameBufferPei.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/= Library/Private/PeiGpioNameBufferLib/GpioNameBufferPei.c new file mode 100644 index 0000000000..1b05378799 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/PeiGpioNameBuf= ferLib/GpioNameBufferPei.c @@ -0,0 +1,68 @@ +/** @file + This file contains GpioMemLib implementation for PEI phase + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include + +STATIC CONST EFI_GUID mGpioNamesPrivateHobGuid =3D {0x9AE3138D, 0x4EBF, 0x= 4E90, {0x87, 0x96, 0x11, 0xD3, 0x10, 0x04, 0x60, 0x0A}}; + +STATIC volatile BOOLEAN mGlobalMemoryWorking =3D FALSE; + +STATIC CHAR8 mGpioNameBuffer[GPIO_NAME_LENGTH_MAX]; + +/** + Returns pointer to the buffer taken from GpioLib private HOB + + @retval CHAR8* Pointer to the buffer +**/ +STATIC +CHAR8* +GetBufferFromHob ( + VOID + ) +{ + VOID *Hob; + CHAR8 *GpioNameBuffer; + + Hob =3D NULL; + GpioNameBuffer =3D NULL; + + Hob =3D GetFirstGuidHob (&mGpioNamesPrivateHobGuid); + if (Hob !=3D NULL){ + GpioNameBuffer =3D (CHAR8*) GET_GUID_HOB_DATA (Hob); + } else { + GpioNameBuffer =3D (CHAR8*) BuildGuidHob (&mGpioNamesPrivateHobGuid, G= PIO_NAME_LENGTH_MAX); + if (GpioNameBuffer =3D=3D NULL){ + DEBUG ((DEBUG_ERROR, "Failed to setup HOB for GPIO names lib\n")); + ASSERT (FALSE); + } + } + return GpioNameBuffer; +} + +/** + Returns pointer to the global buffer to be used by GpioNamesLib + + @retval CHAR8* Pointer to the buffer +**/ +CHAR8* +GpioGetStaticNameBuffer ( + VOID + ) +{ + mGlobalMemoryWorking =3D TRUE; + + if (mGlobalMemoryWorking) { + return mGpioNameBuffer; + } else { + return GetBufferFromHob (); + } +} + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45900): https://edk2.groups.io/g/devel/message/45900 Mute This Topic: https://groups.io/mt/32918193/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45901+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45901+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001018; cv=none; d=zoho.com; s=zohoarc; b=dOy00StVcr5sZYYWr/pLdCxcgiwF9dcMK6qUJtSaPSxcmP0HGFjAOBZiKlGN3TU5MwWwjQXgFIVDMB17Hz92E2aUJDBP+z1XJsImzgyMXQFup3prBYd5QQAgjU1MOhagg7ve+58AQFTXgDDzZCtwD4s8NN6p6lLxAorwHYFAH34= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001018; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=JcsIMwNHShivd02IVed9MyrHqhvCJ11sLcxHwgyL3Ng=; b=NeyAqvGhjPNvxRM26jCQBiPM+HmEJs3kY+B+fKWrjiYkTmiKu3NvR3FB4jhjK8bUK3AKkLheVBG14zJlY387/kfy+ogzcWn55sF1YvaetgrGw6AszJuc4tXrXx8IpyTiBT+jEzLnkBH5ZJ+mHWrWIOQxWbYA7KGBde4OsbuMGWA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45901+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001018320485.8569927325524; Fri, 16 Aug 2019 17:16:58 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319308" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:54 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 24/37] CoffeelakeSiliconPkg/Pch: Add SMM private library instances Date: Fri, 16 Aug 2019 17:15:50 -0700 Message-Id: <20190817001603.30632-25-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001017; bh=ezL4CkCnXD4zJjNsR7fhHdOmAKKTWVmnsaiETUnpLyU=; h=Cc:Date:From:Reply-To:Subject:To; b=HczHqVI+zkuNDjyABnEjzQvC6KH6BCmkYuYKYyLNrvcLY+60+7AzufNQ8sIe2qxqaRu NbXm8YYtEAx/TzHZdQQKijuLHAoRM51Pl/SX7cIy3l9XhMiTzokuHMF2sn/YQvDsCIous vrC0MNXuNX+gzddQPSTB8+pZQzzchF5M6No= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds PCH SMM private library class instances. * SmmPchPrivateLib Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/Sm= mPchPrivateLib.inf | 32 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateLib/Sm= mPchPrivateLib.c | 58 ++++++++++++++++++++ 2 files changed, 90 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchP= rivateLib/SmmPchPrivateLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Lib= rary/Private/SmmPchPrivateLib/SmmPchPrivateLib.inf new file mode 100644 index 0000000000..5cbad21fa5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateL= ib/SmmPchPrivateLib.inf @@ -0,0 +1,32 @@ +## @file +# PCH SMM private lib. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D SmmPchPrivateLib +FILE_GUID =3D FE6495FB-7AA9-4A24-BF3E-4698F7BCE0EE +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_SMM_DRIVER +LIBRARY_CLASS =3D SmmPchPrivateLib + + +[LibraryClasses] +BaseLib +IoLib +DebugLib +CpuPlatformLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +SmmPchPrivateLib.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchP= rivateLib/SmmPchPrivateLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Libra= ry/Private/SmmPchPrivateLib/SmmPchPrivateLib.c new file mode 100644 index 0000000000..85a3086874 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/Private/SmmPchPrivateL= ib/SmmPchPrivateLib.c @@ -0,0 +1,58 @@ +/** @file + PCH SMM private lib. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +/** + Set InSmm.Sts bit +**/ +VOID +PchSetInSmmSts ( + VOID + ) +{ + UINT32 Data32; + + /// + /// Read memory location FED30880h OR with 00000001h, place the result i= n EAX, + /// and write data to lower 32 bits of MSR 1FEh (sample code available) + /// + Data32 =3D MmioRead32 (0xFED30880); + AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE_ADDR, Data32 | BIT0); + /// + /// Read FED30880h back to ensure the setting went through. + /// + Data32 =3D MmioRead32 (0xFED30880); +} + +/** + Clear InSmm.Sts bit +**/ +VOID +PchClearInSmmSts ( + VOID + ) +{ + UINT32 Data32; + + /// + /// Read memory location FED30880h AND with FFFFFFFEh, place the result = in EAX, + /// and write data to lower 32 bits of MSR 1FEh (sample code available) + /// + Data32 =3D MmioRead32 (0xFED30880); + AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE_ADDR, Data32 & (UINT32) (~BIT0)); + /// + /// Read FED30880h back to ensure the setting went through. + /// + Data32 =3D MmioRead32 (0xFED30880); +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45901): https://edk2.groups.io/g/devel/message/45901 Mute This Topic: https://groups.io/mt/32918194/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45902+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45902+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001018; cv=none; d=zoho.com; s=zohoarc; b=fZB1h3rqyS/MNOZfinTEtntD+3D6LgXDxsffkF/rEKOz13neMwjyjrjgbI8+gwJxANe62ixBzQHDUtzRflYRxEV1YNC9KZzqAuA67XB737ca7DA3bWurbkfAeY+Cy8B873BOpiB8w6Sl+DKO8H9t4SWakXGS0yjgDrwtszuCim4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001018; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=BQ1FREnaS3tka/nvb7IfyiSh1CeeOCDYGpbJNNv8NDU=; b=aXdq7JlNvs6s/aOb/7yJbYUQS9dYiCtZPtt/TiCJez89xSGDGmGpTMhgVQ/EO2AsG1+xoyx6WNaSL8momnzxdY/Z29JbpDkwMMMpFTIO8cYSpIWai1fMaNQnRaXzo2p9OmuksvrStbMN/pb+sZcpIED2TR99um1kwwVjjnucFfU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45902+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156600101880554.74677850199532; Fri, 16 Aug 2019 17:16:58 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319310" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:55 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 25/37] CoffeelakeSiliconPkg/SystemAgent: Add library instances Date: Fri, 16 Aug 2019 17:15:51 -0700 Message-Id: <20190817001603.30632-26-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001018; bh=2MHVCeBZDCD3pivf8iG00n5WzXOWyeHXdX68I6RH3EQ=; h=Cc:Date:From:Reply-To:Subject:To; b=m5p/+KmH63VR3lpXp3fTbyJT7cSqJAATE4YmwtieGUUAqZubF2TnKx/yTCu4gr2dEVZ mqTJtsI+hGaF+NqQK9rzuLBSHXNnejJXEzbdJPg038Baj5Lcb83baUN93SMoUf7CQ5Z26 nghXnGPt/sNQ+QSa9UK/Y//q+ADRoT8m2qA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds System Agent (SA) library class instances. * DxeSaPolicyLib - DXE SA policy configuration services. * PeiDxeSmmSaPlatformLib - SA platform generation services. * PeiSaPolicyLib - PEI SA policy configuration services. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeS= aPolicyLib.inf | 43 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatform= Lib/PeiDxeSmmSaPlatformLib.inf | 38 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS= aPolicyLib.inf | 74 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeS= aPolicyLibrary.h | 37 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatform= Lib/SaPlatformLibrary.h | 21 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/MrcO= emPlatform.h | 323 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS= aPolicyLibrary.h | 39 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeS= aPolicyLib.c | 473 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatform= Lib/SaPlatformLibrary.c | 128 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/MrcO= emPlatform.c | 745 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS= aPolicyLib.c | 656 +++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiS= aPolicyLibSample.c | 284 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/SaPr= intPolicy.c | 559 +++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32= /MrcOemPlatform.S | 114 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32= /MrcOemPlatform.asm | 126 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/Ia32= /MrcOemPlatform.nasm | 118 ++++ 16 files changed, 3778 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPo= licyLib/DxeSaPolicyLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent= /Library/DxeSaPolicyLib/DxeSaPolicyLib.inf new file mode 100644 index 0000000000..8a5092e199 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib= /DxeSaPolicyLib.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for the PeiSaPolicy library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeSaPolicyLib +FILE_GUID =3D B402A3A4-4B82-410E-B79C-5914880A05E7 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D DxeSaPolicyLib + +[LibraryClasses] +BaseMemoryLib +UefiRuntimeServicesTableLib +UefiBootServicesTableLib +DebugLib +PostCodeLib +ConfigBlockLib +HobLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] +DxeSaPolicyLib.c +DxeSaPolicyLibrary.h + +[Guids] +gGraphicsDxeConfigGuid +gMiscDxeConfigGuid +gPcieDxeConfigGuid +gMemoryDxeConfigGuid +gVbiosDxeConfigGuid + +[Protocols] +gSaPolicyProtocolGuid ## PRODUCES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeS= mmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf b/Silicon/Intel/CoffeelakeSilico= nPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf new file mode 100644 index 0000000000..ffc4043e7a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPla= tformLib/PeiDxeSmmSaPlatformLib.inf @@ -0,0 +1,38 @@ +## @file +# Component description file for SA Platform Lib +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiDxeSmmSaPlatformLib +FILE_GUID =3D 9DB5ACB4-DB23-43AE-A283-2ABEF365CBE0 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D SaPlatformLib + + +[LibraryClasses] +BaseLib +BaseMemoryLib +DebugLib +IoLib +CpuPlatformLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + +[Sources] +SaPlatformLibrary.h +SaPlatformLibrary.c diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/PeiSaPolicyLib.inf b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent= /Library/PeiSaPolicyLib/PeiSaPolicyLib.inf new file mode 100644 index 0000000000..22d0f0c945 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /PeiSaPolicyLib.inf @@ -0,0 +1,74 @@ +## @file +# Component description file for the PeiSaPolicy library. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiSaPolicyLib +FILE_GUID =3D d7022865-ef1b-449d-8c3f-ac36488c408b +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D PeiSaPolicyLib + + +[LibraryClasses] +DebugLib +IoLib +PeiServicesLib +BaseMemoryLib +MemoryAllocationLib +ConfigBlockLib +CpuMailboxLib +SiConfigBlockLib +RngLib +PmcPrivateLib +GpioLib +PchInfoLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress +gSiPkgTokenSpaceGuid.PcdTsegSize +gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress +gSiPkgTokenSpaceGuid.PcdIpuEnable ## CONSUMES + +[Sources] +PeiSaPolicyLib.c +PeiSaPolicyLibrary.h +MrcOemPlatform.c +MrcOemPlatform.h +SaPrintPolicy.c +PeiSaPolicyLibSample.c + +[Sources.IA32] +Ia32/MrcOemPlatform.nasm +Ia32/MrcOemPlatform.S + +[Ppis] +gSiPreMemPolicyPpiGuid ## CONSUMES +gSiPolicyPpiGuid ## CONSUMES + +[Guids] +gSaMiscPeiPreMemConfigGuid ## PRODUCES +gSaMiscPeiConfigGuid ## PRODUCES +gSaPciePeiPreMemConfigGuid ## PRODUCES +gSaPciePeiConfigGuid ## PRODUCES +gGraphicsPeiPreMemConfigGuid ## CONSUMES +gGraphicsPeiConfigGuid ## CONSUMES +gSwitchableGraphicsConfigGuid ## PRODUCES +gCpuTraceHubConfigGuid ## PRODUCES +gMemoryConfigGuid ## PRODUCES +gMemoryConfigNoCrcGuid ## PRODUCES +gIpuPreMemConfigGuid ## PRODUCES +gGnaConfigGuid ## PRODUCES +gVtdConfigGuid ## PRODUCES +gSaOverclockingPreMemConfigGuid ## PRODUCES diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPo= licyLib/DxeSaPolicyLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAge= nt/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h new file mode 100644 index 0000000000..449b67798c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib= /DxeSaPolicyLibrary.h @@ -0,0 +1,37 @@ +/** @file + Header file for the DxeSaPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SA_POLICY_LIBRARY_H_ +#define _DXE_SA_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define WORD_FIELD_VALID_BIT BIT15 +/// +/// DIMM SMBus addresses +/// +#define DIMM_SMB_SPD_P0C0D0 0xA0 +#define DIMM_SMB_SPD_P0C0D1 0xA2 +#define DIMM_SMB_SPD_P0C1D0 0xA4 +#define DIMM_SMB_SPD_P0C1D1 0xA6 +#define DIMM_SMB_SPD_P0C0D2 0xA8 +#define DIMM_SMB_SPD_P0C1D2 0xAA + +#endif // _DXE_SA_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeS= mmSaPlatformLib/SaPlatformLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/Sy= stemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.h new file mode 100644 index 0000000000..07d4c6e666 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPla= tformLib/SaPlatformLibrary.h @@ -0,0 +1,21 @@ +/** @file + Header file for SA Platform Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_PLATFORM_LIBRARY_IMPLEMENTATION_H_ +#define _SA_PLATFORM_LIBRARY_IMPLEMENTATION_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/MrcOemPlatform.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/L= ibrary/PeiSaPolicyLib/MrcOemPlatform.h new file mode 100644 index 0000000000..61a6e2a691 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /MrcOemPlatform.h @@ -0,0 +1,323 @@ +/** @file + This file contains functions that read the SPD data for each DIMM slot o= ver + the SMBus interface. + This file is SampleCode for Intel SA PEI Policy initialization. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyLibrary.h" +#include "MrcInterface.h" + +#define RTC_INDEX_REGISTER (0x70) +#define RTC_TARGET_REGISTER (0x71) + +#define RTC_INDEX_MASK (0x7F) +#define RTC_BANK_SIZE (0x80) + +#define RTC_SECONDS (0x00) +#define RTC_MINUTES (0x02) +#define RTC_HOURS (0x04) +#define RTC_DAY_OF_MONTH (0x07) +#define RTC_MONTH (0x08) +#define RTC_YEAR (0x09) +#define CMOS_REGA (0x0A) +#define CMOS_REGB (0x0B) +#define CMOS_REGC (0x0C) +#define CMOS_REGD (0x0D) + +#define RTC_UPDATE_IN_PROGRESS (0x80) +#define RTC_HOLD (0x80) +#define RTC_MODE_24HOUR (0x02) +#define RTC_CLOCK_DIVIDER (0x20) +#define RTC_RATE_SELECT (0x06) + +#define BCD2BINARY(A) (((((A) >> 4) & 0xF) * 10) + ((A) & 0xF)) +#define CENTURY_OFFSET (2000) + +/** + Read the SPD data over the SMBus, at the given SmBus SPD address and cop= y the data to the data structure. + The SPD data locations read is controlled by the current boot mode. + + @param[in] BootMode - The current MRC boot mode. + @param[in] Address - SPD SmBus address offset. + @param[in] Buffer - Buffer that contains the data read from = the SPD. + @param[in] SpdDdr3Table - Indicates which SPD bytes to read. + @param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes. + @param[in] SpdDdr4Table - Indicates which SPD bytes to read. + @param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes. + @param[in] SpdLpddrTable - Indicates which SPD bytes to read. + @param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes. + + @retval TRUE if the read is successful, otherwise FALSE on error. +**/ +BOOLEAN +GetSpdData ( + IN SPD_BOOT_MODE BootMode, + IN UINT8 Address, + IN OUT UINT8 *Buffer, + IN UINT8 *SpdDdr3Table, + IN UINT32 SpdDdr3TableSize, + IN UINT8 *SpdDdr4Table, + IN UINT32 SpdDdr4TableSize, + IN UINT8 *SpdLpddrTable, + IN UINT32 SpdLpddrTableSize + ); + +/** + Output a string to the debug stream/device. + + @param[in] String - The string to output. +**/ +VOID +SaDebugPrint ( + VOID *String + ); + +/** + Calculate the PCI device address for the given Bus/Device/Function/Offse= t. + + @param[in] Bus - PCI bus + @param[in] Device - PCI device + @param[in] Function - PCI function + @param[in] Offset - Offset + + @retval The PCI device address. +**/ +UINT32 +GetPciDeviceAddress ( + IN const UINT8 Bus, + IN const UINT8 Device, + IN const UINT8 Function, + IN const UINT8 Offset + ); + +/** + Calculate the PCIE device address for the given Bus/Device/Function/Offs= et. + + @param[in] Bus - PCI bus + @param[in] Device - PCI device + @param[in] Function - PCI function + @param[in] Offset - Offset + + The PCIE device address. + + @retval The PCIe device address +**/ +UINT32 +GetPcieDeviceAddress ( + IN const UINT8 Bus, + IN const UINT8 Device, + IN const UINT8 Function, + IN const UINT8 Offset + ); + +/** + Read specific RTC/CMOS RAM + + @param[in] Location Point to RTC/CMOS RAM offset for read + + @retval The data of specific location in RTC/CMOS RAM. +**/ +UINT8 +PeiRtcRead ( + IN const UINT8 Location + ); + +/** + Returns the current time, as determined by reading the Real Time Clock (= RTC) on the platform. + Since RTC time is stored in BCD, convert each value to binary. + + @param[out] Seconds - The current second (0-59). + @param[out] Minutes - The current minute (0-59). + @param[out] Hours - The current hour (0-23). + @param[out] DayOfMonth - The current day of the month (1-31). + @param[out] Month - The current month (1-12). + @param[out] Year - The current year (2000-2099). +**/ +VOID +GetRtcTime ( + OUT UINT8 *const Seconds, + OUT UINT8 *const Minutes, + OUT UINT8 *const Hours, + OUT UINT8 *const DayOfMonth, + OUT UINT8 *const Month, + OUT UINT16 *const Year + ); + +/** + Gets CPU current time. + + @param[in] GlobalData - Pointer to global MRC data struct. + + @retval The current CPU time in milliseconds. +**/ +UINT64 +GetCpuTime ( + IN VOID *GlobalData + ); + +/** + Sets the specified number of memory words, a word at a time, at the + specified destination. + + @param[in, out] Dest - Destination pointer. + @param[in] NumWords - The number of dwords to set. + @param[in] Value - The value to set. + + @retval Pointer to the buffer. +**/ +VOID * +SetMemWord ( + IN OUT VOID *Dest, + IN UINTN NumWords, + IN const UINT16 Value + ); + +/** + Sets the specified number of memory dwords, a dword at a time, at the + specified destination. + + @param[in, out] Dest - Destination pointer. + @param[in] NumDwords - The number of dwords to set. + @param[in] Value - The value to set. + + @retval Pointer to the buffer. +**/ +VOID * +SetMemDword ( + IN OUT VOID *Dest, + IN UINT32 NumDwords, + IN const UINT32 Value + ); + +/** + Read 64 bits from the Memory Mapped I/O space. + Use MMX instruction for atomic access, because some MC registers have si= de effect. + + @param[in] Address - Memory mapped I/O address. +**/ +UINT64 +SaMmioRead64 ( + IN UINTN Address + ); + +/** + Write 64 bits to the Memory Mapped I/O space. + Use MMX instruction for atomic access, because some MC registers have si= de effect. + + @param[in] Address - Memory mapped I/O address. + @param[in] Value - The value to write. +**/ +UINT64 +SaMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ); + +/** + Intel Silicon View Technology check point interface based on IO port rea= ding + + @param CheckPoint Check point AH value. + AH =3D 0x10: End of MRC State + AH =3D 0x20: End of DXE State + AH =3D 0x30: Ready to boot before INT-19h or U= EFI boot + AH =3D 0x40: After OS booting, need a timer SM= I trigger to implement (TBD) + + @param PortReading IO port reading address used for breakpoints +**/ +VOID +EFIAPI +IsvtCheckPoint ( + IN UINT32 CheckPoint, + IN UINT32 PortReading + ); + +/** + Gets the current memory voltage (VDD). + + @param[in] GlobalData - Pointer to global MRC data struct. + @param[in] DefaultVdd - Default Vdd for the given platform. + + @retval The current memory voltage (VDD), in millivolts. 0 means platfor= m default. +**/ +UINT32 +GetMemoryVdd ( + IN VOID *GlobalData, + IN UINT32 DefaultVdd + ); + +/** + Sets the memory voltage (VDD) to the specified value. + + @param[in] GlobalData - Pointer to global MRC data struct. + @param[in] DefaultVdd - Default Vdd for the given platform. + @param[in] Voltage - The new memory voltage to set. + + @retval The actual memory voltage (VDD), in millivolts, that is closest = to what the caller passed in. +**/ +UINT32 +SetMemoryVdd ( + IN VOID *GlobalData, + IN UINT32 DefaultVdd, + IN UINT32 Voltage + ); + +/** + Check point that is called at various points in the MRC. + + @param[in] GlobalData - MRC global data. + @param[in] Command - OEM command. + @param[in] Pointer - Command specific data. + + @retval MrcStatus value. +**/ +UINT32 +CheckPoint ( + VOID *GlobalData, + UINT32 Command, + VOID *Pointer + ); + +/** + Typically used to display to the I/O port 80h. + + @param[in] GlobalData - Mrc Global Data + @param[in] DisplayDebugNumber - the number to display on port 80. + + @retval Nothing. +**/ +VOID +DebugHook ( + VOID *GlobalData, + UINT16 DisplayDebugNumber + ); + +/** + Hook to take any action after returning from MrcStartMemoryConfiguration= () + and prior to taking any action regarding MrcStatus. Pre-populated with = issuing + Intel Silicon View Technology (ISVT) checkpoint 0x01. + + @param[in] GlobalData - Mrc Global Data + @param[in] MrcStatus - Mrc status variable +**/ +VOID +ReturnFromSmc ( + VOID *GlobalData, + UINT32 MrcStatus + ); + +/** + Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset. + + @param[in] PciEBaseAddress - PCI express base address. + @param[in] ResetValue - desired value of DRAM_RESET#. 1 - reset de= asserted, 0 - reset asserted. +**/ +VOID +SaDramReset ( + IN UINT32 PciEBaseAddress, + IN UINT32 ResetValue + ); + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/PeiSaPolicyLibrary.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAge= nt/Library/PeiSaPolicyLib/PeiSaPolicyLibrary.h new file mode 100644 index 0000000000..124ca6a57f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /PeiSaPolicyLibrary.h @@ -0,0 +1,39 @@ +/** @file + Header file for the PeiSaPolicy library. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SA_POLICY_LIBRARY_H_ +#define _PEI_SA_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + SaLoadSamplePolicyPreMem - Load some policy default for reference board. + + @param[in] ConfigBlockTableAddress The pointer for SA config blocks + +**/ +VOID +SaLoadSamplePolicyPreMem ( + IN VOID *ConfigBlockTableAddress + ); +#endif // _PEI_SA_POLICY_LIBRARY_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPo= licyLib/DxeSaPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/L= ibrary/DxeSaPolicyLib/DxeSaPolicyLib.c new file mode 100644 index 0000000000..0e8d518fe7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib= /DxeSaPolicyLib.c @@ -0,0 +1,473 @@ +/** @file + This file provide services for DXE phase policy default initialization + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "DxeSaPolicyLibrary.h" + + +GLOBAL_REMOVE_IF_UNREFERENCED PCIE_ASPM_OVERRIDE_LIST mPcieAspmDevsOverrid= e[] =3D { + {0x8086, 0x108b, 0xff, 2, 2}, ///< Tekoa w/o iAMT + {0x8086, 0x108c, 0x00, 0, 0}, ///< Tekoa A2 + {0x8086, 0x108c, 0xff, 2, 2}, ///< Tekoa others + {0x8086, 0x109a, 0xff, 2, 2}, ///< Vidalia + {0x8086, 0x4222, 0xff, 2, 3}, ///< 3945ABG + {0x8086, 0x4227, 0xff, 2, 3}, ///< 3945ABG + {0x8086, 0x4228, 0xff, 2, 3}, ///< 3945ABG + /// + /// Place structures for known bad OEM/IHV devices here + /// + {SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0} ///< End of table +}; + +GLOBAL_REMOVE_IF_UNREFERENCED PCIE_LTR_DEV_INFO mPcieLtrDevsOverride[] =3D= { + /// + /// Place holder for PCIe devices with correct LTR requirements + /// + {SA_PCIE_DEV_END_OF_TABLE, 0, 0, 0, 0} ///< End of table +}; + +extern EFI_GUID gGraphicsDxeConfigGuid; +extern EFI_GUID gMemoryDxeConfigGuid; +extern EFI_GUID gMiscDxeConfigGuid; +extern EFI_GUID gPcieDxeConfigGuid; +extern EFI_GUID gVbiosDxeConfigGuid; + +/** + This function prints the SA DXE phase policy. + + @param[in] SaPolicy - SA DXE Policy protocol +**/ +VOID +SaPrintPolicyProtocol ( + IN SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + PCIE_DXE_CONFIG *PcieDxeConfig; + MISC_DXE_CONFIG *MiscDxeConfig; + MEMORY_DXE_CONFIG *MemoryDxeConfig; + VBIOS_DXE_CONFIG *VbiosDxeConfig; + + // + // Get requisite IP Config Blocks which needs to be used here + // + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gMiscDxeConfigGuid, (VOID= *)&MiscDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gPcieDxeConfigGuid, (VOID= *)&PcieDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gMemoryDxeConfigGuid, (VO= ID *)&MemoryDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gVbiosDxeConfigGuid, (VOI= D *)&VbiosDxeConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG_CODE_BEGIN (); + INTN i; + + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BE= GIN -----------------\n")); + DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revi= sion)); + ASSERT (SaPolicy->TableHeader.Header.Revision =3D=3D SA_POLICY_PROTOCOL_= REVISION); + + DEBUG ((DEBUG_INFO, "------------------------ SA_MEMORY_CONFIGURATION --= ---------------\n")); + DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS)); + for (i =3D 0; i < SA_MC_MAX_SOCKETS; i++) { + DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i])); + } + DEBUG ((DEBUG_INFO, "\n")); + + DEBUG ((DEBUG_INFO, " ChannelASlotMap : %x\n", MemoryDxeConfig->ChannelA= SlotMap)); + DEBUG ((DEBUG_INFO, " ChannelBSlotMap : %x\n", MemoryDxeConfig->ChannelB= SlotMap)); + DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n", MemoryDxeConfig->MrcTimeM= easure)); + DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n", MemoryDxeConfig->MrcFastB= oot)); + + DEBUG ((DEBUG_INFO, "------------------------ SA_PCIE_CONFIGURATION ----= -------------\n")); + DEBUG ((DEBUG_INFO, " PegAspm[%d] :", SA_PEG_MAX_FUN)); + for (i =3D 0; i < SA_PEG_MAX_FUN; i++) { + DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegAspm[i])); + } + DEBUG ((DEBUG_INFO, "\n")); + + DEBUG ((DEBUG_INFO, " PegAspmL0s[%d] :", SA_PEG_MAX_FUN)); + for (i =3D 0; i < SA_PEG_MAX_FUN; i++) { + DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegAspmL0s[i])); + } + DEBUG ((DEBUG_INFO, "\n")); + + DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :", SA_PEG_MAX_FUN)); + for (i =3D 0; i < SA_PEG_MAX_FUN; i++) { + DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegRootPortHPE[i])); + } + DEBUG ((DEBUG_INFO, "\n")); + + if (PcieDxeConfig->PcieAspmDevsOverride !=3D NULL) { + DEBUG ((DEBUG_INFO, "------------------------ PCIE_ASPM_OVERRIDE_LIST = -----------------\n")); + DEBUG ((DEBUG_INFO, " VendorId DeviceId RevId RootApmcMask EndpointApm= cMask\n")); + i =3D 0; + while ((PcieDxeConfig->PcieAspmDevsOverride[i].VendorId !=3D SA_PCIE_D= EV_END_OF_TABLE) && + (i < MAX_PCIE_ASPM_OVERRIDE)) { + DEBUG ((DEBUG_INFO, " %04x %04x %02x %01x %01x= \n", + PcieDxeConfig->PcieAspmDevsOverride[i].VendorId, + PcieDxeConfig->PcieAspmDevsOverride[i].DeviceId, + PcieDxeConfig->PcieAspmDevsOverride[i].RevId, + PcieDxeConfig->PcieAspmDevsOverride[i].RootApmcMask, + PcieDxeConfig->PcieAspmDevsOverride[i].EndpointApmcMask)); + i++; + } + DEBUG ((DEBUG_INFO, "------------------------ END_OF_TABLE -----------= ------------\n")); + } + if (PcieDxeConfig->PcieLtrDevsOverride !=3D NULL) { + DEBUG ((DEBUG_INFO, "------------------------ PCIE_LTR_DEV_INFO ------= -----------\n")); + DEBUG ((DEBUG_INFO, " VendorId DeviceId RevId SnoopLatency NonSnoopLat= ency\n")); + i =3D 0; + while ((PcieDxeConfig->PcieLtrDevsOverride[i].VendorId !=3D SA_PCIE_DE= V_END_OF_TABLE) && + (i < MAX_PCIE_LTR_OVERRIDE)) { + DEBUG ((DEBUG_INFO, " %04x %04x %02x %01x %01x= \n", + PcieDxeConfig->PcieLtrDevsOverride[i].VendorId, + PcieDxeConfig->PcieLtrDevsOverride[i].DeviceId, + PcieDxeConfig->PcieLtrDevsOverride[i].RevId, + PcieDxeConfig->PcieLtrDevsOverride[i].SnoopLatency, + PcieDxeConfig->PcieLtrDevsOverride[i].NonSnoopLatency)); + i++; + } + DEBUG ((DEBUG_INFO, "------------------------ END_OF_TABLE -----------= -----------\n")); + } + + for (i =3D 0; i < SA_PEG_MAX_FUN; i++) { + DEBUG ((DEBUG_INFO, " PegPwrOpt[%d].LtrEnable : %x\n", i, P= cieDxeConfig->PegPwrOpt[i].LtrEnable)); + DEBUG ((DEBUG_INFO, " PegPwrOpt[%d].LtrMaxSnoopLatency : %x\n", i, P= cieDxeConfig->PegPwrOpt[i].LtrMaxSnoopLatency)); + DEBUG ((DEBUG_INFO, " PegPwrOpt[%d].ObffEnable : %x\n", i, P= cieDxeConfig->PegPwrOpt[i].ObffEnable)); + DEBUG ((DEBUG_INFO, " PegPwrOpt[%d].LtrMaxNoSnoopLatency : %x\n", i, P= cieDxeConfig->PegPwrOpt[i].LtrMaxNoSnoopLatency)); + } + + + if (VbiosDxeConfig !=3D NULL) { + DEBUG ((DEBUG_INFO, "------------------------ SA_SG_VBIOS_CONFIGURATIO= N -----------------\n")); + DEBUG ((DEBUG_INFO, " LoadVbios : %x\n", VbiosDxeConfig->LoadVbios)= ); + DEBUG ((DEBUG_INFO, " ExecuteVbios : %x\n", VbiosDxeConfig->ExecuteVbi= os)); + DEBUG ((DEBUG_INFO, " VbiosSource : %x\n", VbiosDxeConfig->VbiosSourc= e)); + } + + + DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION ----= -------------\n")); + DEBUG ((DEBUG_INFO, " EnableAbove4GBMmio : %x\n", MiscDxeConfig->EnableA= bove4GBMmio)); + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print EN= D -----------------\n")); + DEBUG_CODE_END (); + + return; +} + +EFI_STATUS +EFIAPI +LoadIgdDxeDefault ( + IN VOID *ConfigBlockPointer + ) +{ + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + + GraphicsDxeConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Name =3D %g\n", &= GraphicsDxeConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", GraphicsDxeConfig->Header.GuidHob.Header.HobLength)); + /// + /// Initialize the Graphics configuration + /// + GraphicsDxeConfig->PlatformConfig =3D 1; + GraphicsDxeConfig->AlsEnable =3D 2; + GraphicsDxeConfig->BacklightControlSupport =3D 2; + GraphicsDxeConfig->IgdBlcConfig =3D 2; + GraphicsDxeConfig->IgdDvmtMemSize =3D 1; + GraphicsDxeConfig->GfxTurboIMON =3D 31; + /// + /// Create a static Backlight Brightness Level Duty cycle Mapp= ing Table + /// Possible 20 entries (example used 11), each 16 bits as follows: + /// [15] =3D Field Valid bit, [14:08] =3D Level in Percentage (0-64h), [= 07:00] =3D Desired duty cycle (0 - FFh). + /// + GraphicsDxeConfig->BCLM[0] =3D (0x0000 + WORD_FIELD_VALID_BIT); ///< 0% + GraphicsDxeConfig->BCLM[1] =3D (0x0A19 + WORD_FIELD_VALID_BIT); ///< 10% + GraphicsDxeConfig->BCLM[2] =3D (0x1433 + WORD_FIELD_VALID_BIT); ///< 20% + GraphicsDxeConfig->BCLM[3] =3D (0x1E4C + WORD_FIELD_VALID_BIT); ///< 30% + GraphicsDxeConfig->BCLM[4] =3D (0x2866 + WORD_FIELD_VALID_BIT); ///< 40% + GraphicsDxeConfig->BCLM[5] =3D (0x327F + WORD_FIELD_VALID_BIT); ///< 50% + GraphicsDxeConfig->BCLM[6] =3D (0x3C99 + WORD_FIELD_VALID_BIT); ///< 60% + GraphicsDxeConfig->BCLM[7] =3D (0x46B2 + WORD_FIELD_VALID_BIT); ///< 70% + GraphicsDxeConfig->BCLM[8] =3D (0x50CC + WORD_FIELD_VALID_BIT); ///< 80% + GraphicsDxeConfig->BCLM[9] =3D (0x5AE5 + WORD_FIELD_VALID_BIT); ///< 90% + GraphicsDxeConfig->BCLM[10] =3D (0x64FF + WORD_FIELD_VALID_BIT); ///< 1= 00% + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +LoadPcieDxeDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINT8 pegFn; + UINT8 Index; + PCIE_DXE_CONFIG *PcieDxeConfig; + + PcieDxeConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Name =3D %g\n", &Pcie= DxeConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", PcieDxeConfig->Header.GuidHob.Header.HobLength)); + /// + /// Initialize the PCIE Configuration + /// PEG ASPM per port configuration. 4 PEG controllers i.e. 0,1,2,3 + /// + for (pegFn =3D 0; pegFn < SA_PEG_MAX_FUN; pegFn++) { + PcieDxeConfig->PegAspm[pegFn] =3D PcieAspmAutoConfig; + PcieDxeConfig->PegAspmL0s[pegFn] =3D 0; + } + + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + PcieDxeConfig->PegPwrOpt[Index].LtrEnable =3D 1; + PcieDxeConfig->PegPwrOpt[Index].LtrMaxSnoopLatency =3D V_SA_LTR_MAX_= SNOOP_LATENCY_VALUE; + PcieDxeConfig->PegPwrOpt[Index].LtrMaxNoSnoopLatency =3D V_SA_LTR_MAX_= NON_SNOOP_LATENCY_VALUE; + PcieDxeConfig->PegPwrOpt[Index].ObffEnable =3D 1; + } + + PcieDxeConfig->PcieAspmDevsOverride =3D mPcieAspmDevsOverride; + PcieDxeConfig->PcieLtrDevsOverride =3D mPcieLtrDevsOverride; + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +LoadMiscDxeDefault ( + IN VOID *ConfigBlockPointer + ) +{ + MISC_DXE_CONFIG *MiscDxeConfig; + + MiscDxeConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "MiscDxeConfig->Header.GuidHob.Name =3D %g\n", &Misc= DxeConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "MiscDxeConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", MiscDxeConfig->Header.GuidHob.Header.HobLength)); + /// + /// RMRR Base and Limit Address for USB + /// + MiscDxeConfig->RmrrUsbBaseAddress =3D AllocateZeroPool (sizeof (EFI_PHYS= ICAL_ADDRESS) * 2); + ASSERT (MiscDxeConfig->RmrrUsbBaseAddress !=3D NULL); + if (MiscDxeConfig->RmrrUsbBaseAddress !=3D NULL) { + /// + /// BIOS must update USB RMRR base address + /// + MiscDxeConfig->RmrrUsbBaseAddress[0] =3D 0; + MiscDxeConfig->RmrrUsbBaseAddress[1] =3D 0; + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +LoadMemoryDxeDefault ( + IN VOID *ConfigBlockPointer + ) +{ + MEMORY_DXE_CONFIG *MemoryDxeConfig; + + MemoryDxeConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Name =3D %g\n", &Me= moryDxeConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", MemoryDxeConfig->Header.GuidHob.Header.HobLength)); + /// + /// Initialize the Memory Configuration + /// + /// + /// DIMM SMBus addresses info + /// Refer to the SpdAddressTable[] mapping rule in DxeSaPolicyLibrary.h + /// + MemoryDxeConfig->SpdAddressTable =3D AllocateZeroPool (sizeof (UINT8) * = 4); + ASSERT (MemoryDxeConfig->SpdAddressTable !=3D NULL); + if (MemoryDxeConfig->SpdAddressTable !=3D NULL) { + MemoryDxeConfig->SpdAddressTable[0] =3D DIMM_SMB_SPD_P0C0D0; + MemoryDxeConfig->SpdAddressTable[1] =3D DIMM_SMB_SPD_P0C0D1; + MemoryDxeConfig->SpdAddressTable[2] =3D DIMM_SMB_SPD_P0C1D0; + MemoryDxeConfig->SpdAddressTable[3] =3D DIMM_SMB_SPD_P0C1D1; + } + MemoryDxeConfig->ChannelASlotMap =3D 0x01; + MemoryDxeConfig->ChannelBSlotMap =3D 0x01; + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +LoadVbiosDxeDefault ( + IN VOID *ConfigBlockPointer + ) +{ + VBIOS_DXE_CONFIG *VbiosDxeConfig; + + VbiosDxeConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "VbiosDxeConfig->Header.GuidHob.Name =3D %g\n", &Vbi= osDxeConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "VbiosDxeConfig->Header.GuidHob.Header.HobLength =3D= 0x%x\n", VbiosDxeConfig->Header.GuidHob.Header.HobLength)); + /// + /// Initialize the SG VBIOS DXE Policies + /// + /// + /// 1 =3D secondary display device VBIOS Source is PCI Card + /// 0 =3D secondary display device VBIOS Source is FW Volume + /// + VbiosDxeConfig->VbiosSource =3D 1; + return EFI_SUCCESS; +} + +/** + LoadSaDxeConfigBlockDefault - Initialize default settings for each SA Co= nfig block + + @param[in] ConfigBlockPointer The buffer pointer that will be in= itialized as specific config block + @param[in] BlockId Request to initialize defaults of = specified config block by given Block ID + + @retval EFI_SUCCESS The given buffer has contained the= defaults of requested config block + @retval EFI_NOT_FOUND Block ID is not defined so no defa= ult Config block will be initialized +**/ +EFI_STATUS +EFIAPI +LoadSaDxeConfigBlockDefault ( + IN VOID *ConfigBlockPointer, + IN EFI_GUID BlockGuid + ) +{ + if (CompareGuid (&BlockGuid, &gGraphicsDxeConfigGuid)) { + LoadIgdDxeDefault (ConfigBlockPointer); + } else if (CompareGuid (&BlockGuid, &gMiscDxeConfigGuid)) { + LoadMiscDxeDefault (ConfigBlockPointer); + } else if (CompareGuid (&BlockGuid, &gPcieDxeConfigGuid)) { + LoadPcieDxeDefault (ConfigBlockPointer); + } else if (CompareGuid (&BlockGuid, &gMemoryDxeConfigGuid)) { + LoadMemoryDxeDefault (ConfigBlockPointer); + } else if (CompareGuid (&BlockGuid, &gVbiosDxeConfigGuid)) { + LoadVbiosDxeDefault (ConfigBlockPointer); + } else { + return EFI_NOT_FOUND; + } + return EFI_SUCCESS; +} + + +/** + CreateSaDxeConfigBlocks generates the config blocksg of SA DXE Policy. + It allocates and zero out buffer, and fills in the Intel default setting= s. + + @param[out] SaPolicy The pointer to get SA DXE Protocol i= nstance + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +CreateSaDxeConfigBlocks ( + IN OUT SA_POLICY_PROTOCOL **SaPolicy + ) +{ + UINT16 TotalBlockSize; + UINT16 TotalBlockCount; + UINT16 BlockCount; + VOID *ConfigBlockPointer; + EFI_STATUS Status; + SA_POLICY_PROTOCOL *SaInitPolicy; + UINT16 RequiredSize; + STATIC CONFIG_BLOCK_HEADER SaDxeIpBlocks [] =3D { + {{{0, sizeof (GRAPHICS_DXE_CONFIG), 0}, {0}}, GRAPHICS_DXE_= CONFIG_REVISION, 0, {0, 0}}, + {{{0, sizeof (MEMORY_DXE_CONFIG), 0}, {0}}, MEMORY_DXE_CONFIG_= REVISION, 0, {0, 0}}, + {{{0, sizeof (MISC_DXE_CONFIG), 0}, {0}}, MISC_DXE_CONFIG_RE= VISION, 0, {0, 0}}, + {{{0, sizeof (PCIE_DXE_CONFIG), 0}, {0}}, PCIE_DXE_CONFIG_RE= VISION, 0, {0, 0}}, + {{{0, sizeof (VBIOS_DXE_CONFIG), 0}, {0}}, VBIOS_DXE_CONFIG_R= EVISION, 0, {0, 0}} + }; + + SaInitPolicy =3D NULL; + TotalBlockCount =3D sizeof (SaDxeIpBlocks) / sizeof (CONFIG_BLOCK_HEADER= ); + DEBUG ((DEBUG_INFO, "TotalBlockCount =3D 0x%x\n", TotalBlockCount)); + + TotalBlockSize =3D 0; + for (BlockCount =3D 0 ; BlockCount < TotalBlockCount; BlockCount++) { + TotalBlockSize +=3D (UINT32) SaDxeIpBlocks[BlockCount].GuidHob.Header.= HobLength; + DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]=3D 0x%x\= n", BlockCount, TotalBlockSize)); + } + + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize; + + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *)&SaInitPolicy); + ASSERT_EFI_ERROR (Status); + // + // Initalize SklSaIpBlocks table GUID + // + CopyMem (&SaDxeIpBlocks[0].GuidHob.Name, &gGraphicsDxeConfigGuid, sizeo= f (EFI_GUID)); + CopyMem (&SaDxeIpBlocks[1].GuidHob.Name, &gMemoryDxeConfigGuid, sizeo= f (EFI_GUID)); + CopyMem (&SaDxeIpBlocks[2].GuidHob.Name, &gMiscDxeConfigGuid, sizeo= f (EFI_GUID)); + CopyMem (&SaDxeIpBlocks[3].GuidHob.Name, &gPcieDxeConfigGuid, sizeo= f (EFI_GUID)); + CopyMem (&SaDxeIpBlocks[4].GuidHob.Name, &gVbiosDxeConfigGuid, sizeo= f (EFI_GUID)); + + // + // Initialize Policy Revision + // + SaInitPolicy->TableHeader.Header.Revision =3D SA_POLICY_PROTOCOL_REVISIO= N; + // + // Initialize ConfigBlockPointer to NULL + // + ConfigBlockPointer =3D NULL; + // + // Loop to identify each config block from SaDxeIpBlocks[] Table and add= each of them + // + for (BlockCount =3D 0 ; BlockCount < TotalBlockCount; BlockCount++) { + ConfigBlockPointer =3D (VOID *)&SaDxeIpBlocks[BlockCount]; + Status =3D AddConfigBlock ((VOID *) SaInitPolicy, (VOID *)&ConfigBlock= Pointer); + ASSERT_EFI_ERROR (Status); + LoadSaDxeConfigBlockDefault ((VOID *) ConfigBlockPointer, SaDxeIpBlock= s[BlockCount].GuidHob.Name); + } + // + // Assignment for returning SaPolicy config block base address + // + *SaPolicy =3D SaInitPolicy; + return EFI_SUCCESS; +} + + +/** + SaInstallPolicyProtocol installs SA Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SaPolicy The pointer to SA Policy Protocol = instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +SaInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + + /// + /// Print SA DXE Policy + /// + SaPrintPolicyProtocol (SaPolicy); + + /// + /// Install protocol to to allow access to this Policy. + /// + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gSaPolicyProtocolGuid, + SaPolicy, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeS= mmSaPlatformLib/SaPlatformLibrary.c b/Silicon/Intel/CoffeelakeSiliconPkg/Sy= stemAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.c new file mode 100644 index 0000000000..fc6e469ae3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPla= tformLib/SaPlatformLibrary.c @@ -0,0 +1,128 @@ +/** @file + SA Platform Lib implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SaPlatformLibrary.h" +#include +#include +#include + +/** + Determine if PCH Link is DMI/OPI + + @param[in] CpuModel CPU model + + @retval TRUE DMI + @retval FALSE OPI +**/ +BOOLEAN +IsPchLinkDmi ( + IN CPU_FAMILY CpuModel + ) +{ + if ((CpuModel =3D=3D EnumCpuCflDtHalo) || (CpuModel =3D=3D EnumCpuCnlDtH= alo)) { + return TRUE; // DMI + } + return FALSE; // OPI +} + + +/** + Returns the number of DMI lanes for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxDmiLanes ( + ) +{ + return SA_DMI_CFL_MAX_LANE; +} + + +/** + Returns the number of DMI bundles for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxDmiBundles ( + ) +{ + return SA_DMI_CFL_MAX_BUNDLE; +} + + +/** + Returns the function numbers for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegFuncs ( + ) +{ + if (GetCpuFamily() =3D=3D EnumCpuCnlDtHalo) { + return SA_PEG_CNL_H_MAX_FUN; + } else { + return SA_PEG_NON_CNL_H_MAX_FUN; + } +} + + +/** + Returns the number of PEG lanes for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegLanes ( + ) +{ + if (GetCpuFamily() =3D=3D EnumCpuCnlDtHalo) { + return SA_PEG_CNL_H_MAX_LANE; + } else { + return SA_PEG_NON_CNL_H_MAX_LANE; + } +} + + +/** + Returns the number of PEG bundles for current CPU + + @retval UINT8 +**/ +UINT8 +GetMaxPegBundles ( + ) +{ + if (GetCpuFamily() =3D=3D EnumCpuCnlDtHalo) { + return SA_PEG_CNL_H_MAX_BUNDLE; + } else { + return SA_PEG_NON_CNL_H_MAX_BUNDLE; + } +} + +/** + Checks if PEG port is present + + @retval TRUE PEG is presented + @retval FALSE PEG is not presented +**/ +BOOLEAN +IsPegPresent ( + VOID + ) +{ + UINT64 PegBaseAddress; + + PegBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_PEG_BUS_NUM,= SA_PEG_DEV_NUM, 0, 0); + if (PciSegmentRead16 (PegBaseAddress) !=3D 0xFFFF) { + return TRUE; + } + return FALSE; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/MrcOemPlatform.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/L= ibrary/PeiSaPolicyLib/MrcOemPlatform.c new file mode 100644 index 0000000000..b7aec77842 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /MrcOemPlatform.c @@ -0,0 +1,745 @@ +/** @file + This file is SampleCode for Intel SA PEI Policy initialization. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "MrcOemPlatform.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#pragma pack (push, 1) +typedef union { + struct { + UINT32 : 8; + UINT32 MAX_NON_TURBO_LIM_RATIO : 8; + UINT32 : 16; + UINT32 : 32; + } Bits; + UINT64 Data; + UINT32 Data32[2]; + UINT16 Data16[4]; + UINT8 Data8[8]; +} PCU_CR_PLATFORM_INFO_STRUCT; + +#pragma pack (pop) + +#define SA_SYSTEM_BCLK (100) +#define PCU_CR_PLATFORM_INFO (0xCE) +#define MRC_POST_CODE_LOW_BYTE_ADDR (0x48) +#define MRC_POST_CODE_HIGH_BYTE_ADDR (0x49) +#define MAX_SPD_PAGE_COUNT (2) +#define MAX_SPD_PAGE_SIZE (256) +#define MAX_SPD_DDR3_SIZE (MAX_SPD_PAGE_SIZE * 1) +#define MAX_SPD_DDR4_SIZE (MAX_SPD_PAGE_SIZE * 2) +#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_CO= UNT) +#define SPD_PAGE_ADDRESS_0 (0x6C) +#define SPD_PAGE_ADDRESS_1 (0x6E) +#define SPD_DDR3_XMP_OFFSET (176) +#define SPD_DDR4_XMP_OFFSET (384) +#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02) +#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B) +#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C) +#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0x0F) +#define SPD_LPDDR4_SDRAM_TYPE_NUMBER (0x10) +#define SPD_LPDDR4X_SDRAM_TYPE_NUMBER (0x11) +#define ISVT_END_OF_MRC_STATE (0x10) + +/** + Read the SPD data over the SMBus, at the specified SPD address, starting= at + the specified starting offset and read the given amount of data. + + @param[in] SpdAddress - SPD SMBUS address + @param[in, out] Buffer - Buffer to store the data. + @param[in] Start - Starting SPD offset + @param[in] Size - The number of bytes of data to read and also th= e size of the buffer. + @param[in, out] Page - The final page that is being pointed to. + + @retval RETURN_SUCCESS if the read is successful, otherwise error status. +**/ +static +RETURN_STATUS +DoSpdRead ( + IN const UINT8 SpdAddress, + IN OUT UINT8 *const Buffer, + IN const UINT16 Start, + IN UINT16 Size, + IN OUT UINT8 *const Page + ) +{ + RETURN_STATUS EfiStatus; + BOOLEAN PageUpdate; + UINT16 Count; + UINT16 Index; + + EfiStatus =3D RETURN_DEVICE_ERROR; + if ((Buffer !=3D NULL) && (Start < MAX_SPD_SIZE) && ((Start + Size) < MA= X_SPD_SIZE)) { + Count =3D 0; + PageUpdate =3D FALSE; + while (Size--) { + Index =3D Start + Count; + if ((Index / MAX_SPD_PAGE_SIZE) !=3D *Page) { + *Page =3D (UINT8) (Index / MAX_SPD_PAGE_SIZE); + PageUpdate =3D TRUE; + } + Index %=3D MAX_SPD_PAGE_SIZE; + if (PageUpdate =3D=3D TRUE) { + PageUpdate =3D FALSE; + SmBusWriteDataByte ((*Page =3D=3D 0) ? SPD_PAGE_ADDRESS_0 : SPD_PA= GE_ADDRESS_1, 0, &EfiStatus); + } + Buffer[Count] =3D SmBusReadDataByte (SpdAddress | ((UINT32) Index <<= 8), &EfiStatus); + if (RETURN_SUCCESS !=3D EfiStatus) { + Buffer[Count] =3D 0; + break; + } + Count++; + } + EfiStatus =3D RETURN_SUCCESS; + } + return (EfiStatus); +} + +/** + See if there is valid XMP SPD data. + + @param[in] Debug - Mrc debug structure. + @param[in, out] Spd - Mrc SPD structure. + @param[in] XmpStart - The current offset in the SPD. + + @retval TRUE if valid, FALSE in not. +**/ +static +BOOLEAN +VerifyXmp ( + IN OUT MrcSpd *const Spd, + IN const UINT16 XmpStart + ) +{ + SPD_EXTREME_MEMORY_PROFILE_HEADER *Header1; + SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 *Header2; + BOOLEAN Xmp; + + Xmp =3D FALSE; + + switch (((UINT8 *) Spd) [2]) { + case SPD_DDR3_SDRAM_TYPE_NUMBER: + Header1 =3D &Spd->Ddr3.Xmp.Header; + if (XmpStart =3D=3D ((UINT32) (Header1) - (UINT32) Spd)) { + Xmp =3D TRUE; + if ((Header1->XmpRevision.Data & 0xFE) =3D=3D 0x12) { + return (TRUE); + } else { + Header1->XmpId =3D 0; + Header1->XmpOrgConf.Data =3D 0; + Header1->XmpRevision.Data =3D 0; + } + } + break; + case SPD_DDR4_SDRAM_TYPE_NUMBER: + Header2 =3D &Spd->Ddr4.EndUser.Xmp.Header; + if (XmpStart =3D=3D ((UINT32) (Header2) - (UINT32) Spd)) { + Xmp =3D TRUE; + if ((Header2->XmpRevision.Data) =3D=3D 0x20) { + return (TRUE); + } else { + Header2->XmpId =3D 0; + Header2->XmpOrgConf.Data =3D 0; + Header2->XmpRevision.Data =3D 0; + } + } + break; + case SPD_LPDDR3_SDRAM_TYPE_NUMBER: + case SPD_LPDDR4_SDRAM_TYPE_NUMBER: + case SPD_LPDDR4X_SDRAM_TYPE_NUMBER: + return (TRUE); + default: + return (FALSE); + } + if (!Xmp) { + return (TRUE); + } + return (FALSE); +} + +/** + Read the SPD data over the SMBus, at the given SmBus SPD address and cop= y the data to the data structure. + The SPD data locations read is controlled by the current boot mode. + + @param[in] BootMode - The current MRC boot mode. + @param[in] Address - SPD SmBus address offset. + @param[in] Buffer - Buffer that contains the data read from = the SPD. + @param[in] SpdDdr3Table - Indicates which SPD bytes to read. + @param[in] SpdDdr3TableSize - Size of SpdDdr3Table in bytes. + @param[in] SpdDdr4Table - Indicates which SPD bytes to read. + @param[in] SpdDdr4TableSize - Size of SpdDdr4Table in bytes. + @param[in] SpdLpddrTable - Indicates which SPD bytes to read. + @param[in] SpdLpddrTableSize - Size of SpdLpddrTable in bytes. + + @retval TRUE if the read is successful, otherwise FALSE on error. +**/ +BOOLEAN +GetSpdData ( + IN SPD_BOOT_MODE BootMode, + IN UINT8 Address, + IN OUT UINT8 *Buffer, + IN UINT8 *SpdDdr3Table, + IN UINT32 SpdDdr3TableSize, + IN UINT8 *SpdDdr4Table, + IN UINT32 SpdDdr4TableSize, + IN UINT8 *SpdLpddrTable, + IN UINT32 SpdLpddrTableSize + ) +{ + const SPD_OFFSET_TABLE *Tbl; + const SPD_OFFSET_TABLE *TableSelect; + RETURN_STATUS Status; + UINT32 Byte; + UINT32 Stop; + UINT8 Page; + + Page =3D (UINT8) (~0); + Status =3D DoSpdRead (Address, &Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET], 2, 1= , &Page); + if (RETURN_SUCCESS =3D=3D Status) { + switch (Buffer[SPD_DDR3_SDRAM_TYPE_OFFSET]) { + case SPD_DDR3_SDRAM_TYPE_NUMBER: + default: + TableSelect =3D (SPD_OFFSET_TABLE *) SpdDdr3Table; + Stop =3D (SpdDdr3TableSize / sizeof (SPD_OFFSET_TABLE)); + break; + case SPD_DDR4_SDRAM_TYPE_NUMBER: + TableSelect =3D (SPD_OFFSET_TABLE *) SpdDdr4Table; + Stop =3D (SpdDdr4TableSize / sizeof (SPD_OFFSET_TABLE)); + break; + case SPD_LPDDR3_SDRAM_TYPE_NUMBER: + case SPD_LPDDR4_SDRAM_TYPE_NUMBER: + case SPD_LPDDR4X_SDRAM_TYPE_NUMBER: + TableSelect =3D (SPD_OFFSET_TABLE *) SpdLpddrTable; + Stop =3D (SpdLpddrTableSize / sizeof (SPD_OFFSET_TABLE)); + break; + } + for (Byte =3D 0; (RETURN_SUCCESS =3D=3D Status) && (Byte < Stop); Byte= ++) { + Tbl =3D &TableSelect[Byte]; + if ((1 << BootMode) & Tbl->BootMode) { + Status =3D DoSpdRead (Address, &Buffer[Tbl->Start], Tbl->Start, Tb= l->End - Tbl->Start + 1, &Page); + if (Status =3D=3D RETURN_SUCCESS) { + if (SpdCold =3D=3D BootMode) { + if (FALSE =3D=3D VerifyXmp ((MrcSpd *) Buffer, Tbl->Start)) { + break; + } + } + } else { + break; + } + } + } + } + + return ((RETURN_SUCCESS =3D=3D Status) ? TRUE : FALSE); +} + +// +// This is from MdeModulePkg\Include\Guid\StatusCodeDataTypeDebug.h +// Might need to be adjusted for a particular BIOS core +// +#ifndef EFI_STATUS_CODE_DATA_MAX_SIZE +#define EFI_STATUS_CODE_DATA_MAX_SIZE 200 +#endif + +/** + Output a string to the debug stream/device. + If there is a '%' sign in the string, convert it to '%%', so that DEBUG(= ) macro will print it properly. + + @param[in] String - The string to output. + + @retval Nothing. +**/ +VOID +SaDebugPrint ( + VOID *String + ) +{ + CHAR8 Str[EFI_STATUS_CODE_DATA_MAX_SIZE]; + CHAR8 *InputStr; + CHAR8 *OutputStr; + UINT32 i; + + InputStr =3D (CHAR8 *) String; + OutputStr =3D Str; + i =3D 0; + while (*InputStr !=3D 0) { + if (i < (EFI_STATUS_CODE_DATA_MAX_SIZE - 2)) { + *OutputStr++ =3D *InputStr; + i++; + if (*InputStr++ =3D=3D '%') { + *OutputStr++ =3D '%'; + i++; + } + } + } + *OutputStr =3D 0; // Terminating NULL + DEBUG ((DEBUG_INFO, Str)); + return; +} + +/** + Calculate the PCI device address for the given Bus/Device/Function/Offse= t. + + @param[in] Bus - PCI bus + @param[in] Device - PCI device + @param[in] Function - PCI function + @param[in] Offset - Offset + + @retval The PCI device address. +**/ +UINT32 +GetPciDeviceAddress ( + IN const UINT8 Bus, + IN const UINT8 Device, + IN const UINT8 Function, + IN const UINT8 Offset + ) +{ + return ( + ((UINT32) ((Bus) & 0xFF) << 16) | + ((UINT32) ((Device) & 0x1F) << 11) | + ((UINT32) ((Function) & 0x07) << 8) | + ((UINT32) ((Offset) & 0xFF) << 0) | + (1UL << 31)); +} + +/** + Calculate the PCIE device address for the given Bus/Device/Function/Offs= et. + + @param[in] Bus - PCI bus + @param[in] Device - PCI device + @param[in] Function - PCI function + @param[in] Offset - Offset + + The PCIE device address. + + @retval The PCIe device address +**/ +UINT32 +GetPcieDeviceAddress ( + IN const UINT8 Bus, + IN const UINT8 Device, + IN const UINT8 Function, + IN const UINT8 Offset + ) +{ + return ( + ((UINT32) Bus << 20) + + ((UINT32) Device << 15) + + ((UINT32) Function << 12) + + ((UINT32) Offset << 0)); +} + +/** + Read specific RTC/CMOS RAM + + @param[in] Location Point to RTC/CMOS RAM offset for read + + @retval The data of specific location in RTC/CMOS RAM. +**/ +UINT8 +PeiRtcRead ( + IN const UINT8 Location + ) +{ + UINT8 RtcIndexPort; + UINT8 RtcDataPort; + + // + // CMOS access registers (using alternative access not to handle NMI bit) + // + if (Location < RTC_BANK_SIZE) { + // + // First bank + // + RtcIndexPort =3D R_RTC_IO_INDEX_ALT; + RtcDataPort =3D R_RTC_IO_TARGET_ALT; + } else { + // + // Second bank + // + RtcIndexPort =3D R_RTC_IO_EXT_INDEX_ALT; + RtcDataPort =3D R_RTC_IO_EXT_TARGET_ALT; + } + + IoWrite8 (RtcIndexPort, Location & RTC_INDEX_MASK); + return IoRead8 (RtcDataPort); +} + +/** + Returns the current time, as determined by reading the Real Time Clock (= RTC) on the platform. + Since RTC time is stored in BCD, convert each value to binary. + + @param[out] Seconds - The current second (0-59). + @param[out] Minutes - The current minute (0-59). + @param[out] Hours - The current hour (0-23). + @param[out] DayOfMonth - The current day of the month (1-31). + @param[out] Month - The current month (1-12). + @param[out] Year - The current year (2000-2099). + + @retval Nothing. +**/ +VOID +GetRtcTime ( + OUT UINT8 *const Seconds, + OUT UINT8 *const Minutes, + OUT UINT8 *const Hours, + OUT UINT8 *const DayOfMonth, + OUT UINT8 *const Month, + OUT UINT16 *const Year + ) +{ + UINT32 Timeout; + + // + // Wait until RTC "update in progress" bit goes low. + // + Timeout =3D 0x0FFFFF; + do { + IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGA); + if ((IoRead8 (RTC_TARGET_REGISTER) & RTC_UPDATE_IN_PROGRESS) !=3D RTC_= UPDATE_IN_PROGRESS) { + break; + } + } while (--Timeout > 0); + + if (0 =3D=3D Timeout) { + IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGB); + IoWrite8 (RTC_TARGET_REGISTER, RTC_HOLD | RTC_MODE_24HOUR); + + IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGA); + IoWrite8 (RTC_TARGET_REGISTER, RTC_CLOCK_DIVIDER | RTC_RATE_SELECT); + + IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGC); + IoRead8 (RTC_TARGET_REGISTER); + + IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGD); + IoRead8 (RTC_TARGET_REGISTER); + + IoWrite8 (RTC_INDEX_REGISTER, CMOS_REGB); + IoWrite8 (RTC_TARGET_REGISTER, RTC_MODE_24HOUR); + } + // + // Read seconds + // + IoWrite8 (RTC_INDEX_REGISTER, RTC_SECONDS); + *Seconds =3D IoRead8 (RTC_TARGET_REGISTER); + + // + // Read minutes + // + IoWrite8 (RTC_INDEX_REGISTER, RTC_MINUTES); + *Minutes =3D IoRead8 (RTC_TARGET_REGISTER); + + // + // Read hours + // + IoWrite8 (RTC_INDEX_REGISTER, RTC_HOURS); + *Hours =3D IoRead8 (RTC_TARGET_REGISTER); + + // + // Read day of month + // + IoWrite8 (RTC_INDEX_REGISTER, RTC_DAY_OF_MONTH); + *DayOfMonth =3D IoRead8 (RTC_TARGET_REGISTER); + + // + // Read month + // + IoWrite8 (RTC_INDEX_REGISTER, RTC_MONTH); + *Month =3D IoRead8 (RTC_TARGET_REGISTER); + + // + // Read year and add current century. + // + IoWrite8 (RTC_INDEX_REGISTER, RTC_YEAR); + *Year =3D IoRead8 (RTC_TARGET_REGISTER); + + *Seconds =3D BCD2BINARY (*Seconds); + *Minutes =3D BCD2BINARY (*Minutes); + *Hours =3D BCD2BINARY (*Hours); + *DayOfMonth =3D BCD2BINARY (*DayOfMonth); + *Month =3D BCD2BINARY (*Month); + *Year =3D BCD2BINARY (*Year) + CENTURY_OFFSET; +} + +/** + Gets CPU current time. + + @param[in] GlobalData - Pointer to global MRC data struct. + + @retval The current CPU time in milliseconds. +**/ +UINT64 +GetCpuTime ( + IN VOID *GlobalData + ) +{ + MrcParameters *MrcData; + MrcInput *Inputs; + PCU_CR_PLATFORM_INFO_STRUCT Msr; + UINT32 TimeBase; + + MrcData =3D (MrcParameters *) GlobalData; + Inputs =3D &MrcData->Inputs; + + Msr.Data =3D AsmReadMsr64 (PCU_CR_PLATFORM_INFO); + TimeBase =3D (Inputs->BClkFrequency / 1000) * Msr.Bits.MAX_NON_TURBO_LIM= _RATIO; //In Millisec + return ((TimeBase =3D=3D 0) ? 0 : DivU64x32 (AsmReadTsc (), TimeBase)); +} + +/** + Sets the specified number of memory words, a word at a time, at the + specified destination. + + @param[in, out] Dest - Destination pointer. + @param[in] NumWords - The number of dwords to set. + @param[in] Value - The value to set. + + @retval Pointer to the buffer. +**/ +VOID * +SetMemWord ( + IN OUT VOID *Dest, + IN UINTN NumWords, + IN const UINT16 Value + ) +{ + UINT16 *Buffer; + + Buffer =3D (UINT16 *) Dest; + while (0 !=3D NumWords--) { + *Buffer++ =3D Value; + } + + return (Dest); +} + +/** + Sets the specified number of memory dwords, a dword at a time, at the + specified destination. + + @param[in, out] Dest - Destination pointer. + @param[in] NumDwords - The number of dwords to set. + @param[in] Value - The value to set. + + @retval Pointer to the buffer. +**/ +VOID * +SetMemDword ( + IN OUT VOID *Dest, + IN UINT32 NumDwords, + IN const UINT32 Value + ) +{ + UINT32 *Buffer; + + Buffer =3D (UINT32 *) Dest; + while (0 !=3D NumDwords--) { + *Buffer++ =3D Value; + } + + return (Dest); +} + + +/** + Gets the current memory voltage (VDD). + + @param[in] GlobalData - Pointer to global MRC data struct. + @param[in] DefaultVdd - Default Vdd for the given platform. + + @retval The current memory voltage (VDD), in millivolts. 0 means platfor= m default. +**/ +UINT32 +GetMemoryVdd ( + IN VOID *GlobalData, + IN UINT32 DefaultVdd + ) +{ + UINT32 CurrentVoltage; + + CurrentVoltage =3D DefaultVdd; + + return CurrentVoltage; +} + +/** + Sets the memory voltage (VDD) to the specified value. + + @param[in] GlobalData - Pointer to global MRC data struct. + @param[in] DefaultVdd - Default Vdd for the given platform. + @param[in] Voltage - The new memory voltage to set. + + @retval The actual memory voltage (VDD), in millivolts, that is closest = to what the caller passed in. +**/ +UINT32 +SetMemoryVdd ( + IN VOID *GlobalData, + IN UINT32 DefaultVdd, + IN UINT32 Voltage + ) +{ + + return Voltage; +} + +/** + This function is used by the OEM to do a dedicated task during the MRC. + + @param[in] GlobalData - include all the MRC data + @param[in] OemStatusCommand - A command that indicates the task to perf= orm. + @param[in] Pointer - general ptr for general use. + + @retval The status of the task. +**/ +MrcStatus +CheckPoint ( + IN VOID *GlobalData, + IN MrcOemStatusCommand OemStatusCommand, + IN VOID *Pointer + ) +{ + MrcParameters *MrcData; + MrcInput *Inputs; + MrcStatus Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + EFI_STATUS Status1; + + // + // Locate SiPreMemPolicyPpi to do a GetConfigBlock() to access platform = data + // + Status1 =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status1); + + Status1 =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNo= CrcGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status1); + MrcData =3D (MrcParameters *) GlobalData; + Inputs =3D &MrcData->Inputs; + SiPreMemPolicyPpi =3D (SI_PREMEM_POLICY_PPI *) Inputs->SiPreMemPolicyPpi; + Status =3D mrcSuccess; + + switch (OemStatusCommand) { + default: + break; + } + + return (Status); +} + +/** + Typically used to display to the I/O port 80h. + + @param[in] GlobalData - Mrc Global Data + @param[in] DisplayDebugNumber - the number to display on port 80. + + @retval Nothing. +**/ +VOID +DebugHook ( + IN VOID *GlobalData, + UINT16 DisplayDebugNumber + ) +{ + MrcParameters *MrcData; + MrcOutput *Outputs; + MrcDebug *Debug; + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + + MrcData =3D (MrcParameters *) GlobalData; + Outputs =3D &MrcData->Outputs; + Debug =3D &Outputs->Debug; + + Debug->PostCode[MRC_POST_CODE] =3D DisplayDebugNumber; + IoWrite16 (0x80, DisplayDebugNumber); + DEBUG ((DEBUG_INFO, "Post Code: %04Xh\n", DisplayDebugNumber)); + + // + // Locate SiPreMemPolicyPpi to do a GetConfigBlock() to access platform = data + // + Status =3D PeiServicesLocatePpi (&gSiPreMemPolicyPpiGuid, 0, NULL, (VOID= **) &SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + if (Status =3D=3D EFI_SUCCESS) { + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreM= emConfigGuid, (VOID *) &MiscPeiPreMemConfig); + if (Status =3D=3D EFI_SUCCESS) { + // + // Put the Port80 code also here: + // #define BIOS_POST_CODE_PCU_CNL_REG (0x00005824) + // + MmioWrite16 (MiscPeiPreMemConfig->MchBar + 0x5824, DisplayDebugNumbe= r); + } + } + return; +} + +/** + Hook to take any action after returning from MrcStartMemoryConfiguration= () + and prior to taking any action regarding MrcStatus. Pre-populated with = issuing + Intel Silicon View Technology (ISVT) checkpoint 0x10. + + @param[in] GlobalData - Mrc Global Data + @param[in] MrcStatus - Mrc status variable +**/ +void +ReturnFromSmc ( + IN VOID *GlobalData, + IN UINT32 MrcStatus + ) +{ + MrcInput *Inputs; + MrcParameters *MrcData; + UINT32 CheckPoint; + UINT32 PortReading; + + MrcData =3D (MrcParameters *) GlobalData; + Inputs =3D &MrcData->Inputs; + + DEBUG ((DEBUG_INFO, "Returned From MrcStartMemoryConfiguration(). MrcSta= tus =3D %08Xh\n", MrcStatus)); + + // + // Intel Silicon View Technology (ISVT) IO Reading port with EAX =3D 0x1= 0 for End of MRC + // + CheckPoint =3D ISVT_END_OF_MRC_STATE; + PortReading =3D (UINT32) Inputs->IsvtIoPort; + IsvtCheckPoint (CheckPoint, PortReading); + + return; +} + +/** + Assert or deassert DRAM_RESET# pin; this is used in JEDEC Reset. + + @param[in] PciEBaseAddress - PCI express base address. + @param[in] ResetValue - desired value of DRAM_RESET#. 1 - reset de= asserted, 0 - reset asserted. +**/ +VOID +SaDramReset ( + IN UINT32 PciEBaseAddress, + IN UINT32 ResetValue + ) +{ + PmcSetDramResetCtlState (ResetValue); + + return; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/PeiSaPolicyLib.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/L= ibrary/PeiSaPolicyLib/PeiSaPolicyLib.c new file mode 100644 index 0000000000..2ac3543f93 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /PeiSaPolicyLib.c @@ -0,0 +1,656 @@ +/** @file + This file provides services for PEI policy default initialization + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyLibrary.h" +#include +#include +#include "MrcInterface.h" +#include + +#define DEFAULT_OPTION_ROM_TEMP_BAR 0x80000000 +#define DEFAULT_OPTION_ROM_TEMP_MEM_LIMIT 0xC0000000 +// +// Need minimum of 48MB during PEI phase for IAG and some buffer for boot. +// +#define PEI_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) = // 80MB + 256MB + +// +// Function call to Load defaults for Individial IP Blocks +// +VOID +LoadSaMiscPeiPreMemDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + + MiscPeiPreMemConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Name =3D %g\n",= &MiscPeiPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->Header.GuidHob.Header.HobLengt= h =3D 0x%x\n", MiscPeiPreMemConfig->Header.GuidHob.Header.HobLength)); + // + // Policy initialization commented out here is because it's the same wit= h default 0 and no need to re-do again. + // + MiscPeiPreMemConfig->LockPTMregs =3D 1; + + // + // Initialize the Platform Configuration + // + MiscPeiPreMemConfig->MchBar =3D 0xFED10000; + MiscPeiPreMemConfig->DmiBar =3D 0xFED18000; + MiscPeiPreMemConfig->EpBar =3D 0xFED19000; + MiscPeiPreMemConfig->EdramBar =3D 0xFED80000; + MiscPeiPreMemConfig->SmbusBar =3D 0xEFA0; + MiscPeiPreMemConfig->TsegSize =3D PcdGet32 (PcdTsegSize); + MiscPeiPreMemConfig->GdxcBar =3D 0xFED84000; + + // + // Initialize the Switchable Graphics Default Configuration + // + MiscPeiPreMemConfig->SgDelayAfterHoldReset =3D 100; //100ms + MiscPeiPreMemConfig->SgDelayAfterPwrEn =3D 300; //300ms + + /// + /// Initialize the DataPtr for S3 resume + /// + MiscPeiPreMemConfig->S3DataPtr =3D NULL; + MiscPeiPreMemConfig->OpRomScanTempMmioBar =3D DEFAULT_OPTION_ROM_TE= MP_BAR; + MiscPeiPreMemConfig->OpRomScanTempMmioLimit =3D DEFAULT_OPTION_ROM_TE= MP_MEM_LIMIT; +} + +VOID +LoadSaMiscPeiDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SA_MISC_PEI_CONFIG *MiscPeiConfig; + + MiscPeiConfig =3D ConfigBlockPointer; + + DEBUG ((DEBUG_INFO, "MiscPeiConfig->Header.GuidHob.Name =3D %g\n", &Misc= PeiConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "MiscPeiConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", MiscPeiConfig->Header.GuidHob.Header.HobLength)); + + /// + /// EDRAM H/W Mode by default (0- EDRAM SW Disable, 1- EDRAM SW Enable, = 2- EDRAM HW Mode) + /// + MiscPeiConfig->EdramTestMode =3D 2; + + if (IsWhlCpu()) { + MiscPeiConfig->Device4Enable =3D 1; + } +} + +VOID +LoadVtdDefault ( + IN VOID *ConfigBlockPointer + ) +{ + VTD_CONFIG *Vtd; + + Vtd =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "Vtd->Header.GuidHob.Name =3D %g\n", &Vtd->Header.Gu= idHob.Name)); + DEBUG ((DEBUG_INFO, "Vtd->Header.GuidHob.Header.HobLength =3D 0x%x\n", V= td->Header.GuidHob.Header.HobLength)); + + // + // Initialize the Vtd Configuration + // + Vtd->VtdDisable =3D 0; + Vtd->BaseAddress[0] =3D 0xFED90000; + Vtd->BaseAddress[1] =3D 0xFED92000; + Vtd->BaseAddress[2] =3D 0xFED91000; +} + +VOID +LoadIpuPreMemDefault ( + IN VOID *ConfigBlockPointer + ) +{ + IPU_PREMEM_CONFIG *IpuPreMemPolicy; + + IpuPreMemPolicy =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "IpuPreMemPolicy->Header.GuidHob.Name =3D %g\n", &Ip= uPreMemPolicy->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "IpuPreMemPolicy->Header.GuidHob.Header.HobLength = =3D 0x%x\n", IpuPreMemPolicy->Header.GuidHob.Header.HobLength)); + +} + +VOID +LoadPciePeiPreMemDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINT8 Index; + PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig; + + PciePeiPreMemConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "PciePeiPreMemConfig->Header.GuidHob.Name =3D %g\n",= &PciePeiPreMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PciePeiPreMemConfig->Header.GuidHob.Header.HobLengt= h =3D 0x%x\n", PciePeiPreMemConfig->Header.GuidHob.Header.HobLength)); + // + // Initialize the PciExpress Configuration + // + PciePeiPreMemConfig->DmiGen3EqPh2Enable =3D 2; + PciePeiPreMemConfig->DmiGen3ProgramStaticEq =3D 1; + PciePeiPreMemConfig->Peg0Enable =3D 2; + PciePeiPreMemConfig->Peg1Enable =3D 2; + PciePeiPreMemConfig->Peg2Enable =3D 2; + PciePeiPreMemConfig->Peg3Enable =3D 2; + PciePeiPreMemConfig->Peg0PowerDownUnusedLanes =3D 1; + PciePeiPreMemConfig->Peg1PowerDownUnusedLanes =3D 1; + PciePeiPreMemConfig->Peg2PowerDownUnusedLanes =3D 1; + PciePeiPreMemConfig->Peg3PowerDownUnusedLanes =3D 1; + PciePeiPreMemConfig->Peg0Gen3EqPh2Enable =3D 2; + PciePeiPreMemConfig->Peg1Gen3EqPh2Enable =3D 2; + PciePeiPreMemConfig->Peg2Gen3EqPh2Enable =3D 2; + PciePeiPreMemConfig->Peg3Gen3EqPh2Enable =3D 2; + PciePeiPreMemConfig->PegGen3ProgramStaticEq =3D 1; + PciePeiPreMemConfig->Gen3SwEqNumberOfPresets =3D 2; + PciePeiPreMemConfig->Gen3SwEqEnableVocTest =3D 2; + + if (IsCnlPch() && IsPchH() && (PchStepping() =3D=3D PCH_A0)) { + PciePeiPreMemConfig->DmiMaxLinkSpeed =3D 1; + } + + for (Index =3D 0; Index < SA_DMI_MAX_LANE; Index++) { + PciePeiPreMemConfig->DmiGen3RootPortPreset[Index] =3D 4; + PciePeiPreMemConfig->DmiGen3EndPointPreset[Index] =3D 7; + PciePeiPreMemConfig->DmiGen3EndPointHint[Index] =3D 2; + } + for (Index =3D 0; Index < SA_DMI_MAX_BUNDLE; Index++) { + /// + /// Gen3 RxCTLE peaking default is 0 for DMI + /// + PciePeiPreMemConfig->DmiGen3RxCtlePeaking[Index] =3D 0; + } + for (Index =3D 0; Index < SA_PEG_MAX_LANE; Index++) { + PciePeiPreMemConfig->PegGen3RootPortPreset[Index] =3D 7; + PciePeiPreMemConfig->PegGen3EndPointPreset[Index] =3D 7; + PciePeiPreMemConfig->PegGen3EndPointHint[Index] =3D 2; + } + PciePeiPreMemConfig->DmiDeEmphasis =3D 1; + /// + /// Gen3 Software Equalization Jitter Dwell Time: 1 msec + /// Gen3 Software Equalization Jitter Error Target: 1 + /// Gen3 Software Equalization VOC Dwell Time: 10 msec + /// Gen3 Software Equalization VOC Error Target: 2 + /// + PciePeiPreMemConfig->Gen3SwEqJitterDwellTime =3D 3 * STALL_ONE_MI= LLI_SECOND; + PciePeiPreMemConfig->Gen3SwEqJitterErrorTarget =3D 2; + PciePeiPreMemConfig->Gen3SwEqVocDwellTime =3D 10 * STALL_ONE_M= ILLI_SECOND; + PciePeiPreMemConfig->Gen3SwEqVocErrorTarget =3D 2; + + /** + Parameters for PCIe Gen3 device reset + @note Refer to the Platform Design Guide (PDG) for additional informatio= n about this GPIO. + **/ + PciePeiPreMemConfig->PegGpioData.GpioSupport =3D FALSE; + PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.GpioPad =3D 0; + PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active =3D FALSE; + PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.GpioPad =3D 0; + PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active =3D FALSE; +} + +VOID +LoadPciePeiDefault ( + IN VOID *ConfigBlockPointer + ) +{ + UINT8 Index; + PCIE_PEI_CONFIG *PciePeiConfig; + + PciePeiConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "PciePeiConfig->Header.GuidHob.Name =3D %g\n", &Pcie= PeiConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "PciePeiConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", PciePeiConfig->Header.GuidHob.Header.HobLength)); + // + // Initialize the PciExpress Configuration + // + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + PciePeiConfig->PegDeEmphasis[Index] =3D 1; + PciePeiConfig->PegMaxPayload[Index] =3D 0xFF; + } + /// + /// Slot Power Limit Value: 75 W + /// Slot Power Limit Scale: 1.0x + /// Physical Slot Number: Peg Index + 1 (1,2,3) + /// + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + PciePeiConfig->PegSlotPowerLimitValue[Index] =3D 75; + PciePeiConfig->PegPhysicalSlotNumber[Index] =3D Index + 1; + } + +} + +VOID +LoadGraphichsPeiPreMemDefault ( + IN VOID *ConfigBlockPointer + ) +{ + GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig; + + GtPreMemConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "GtPreMemConfig->Header.GuidHob.Name =3D %g\n", &GtP= reMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "GtPreMemConfig->Header.GuidHob.Header.HobLength =3D= 0x%x\n", GtPreMemConfig->Header.GuidHob.Header.HobLength)); + + /// + /// Initialize Graphics Pre-Mem Configurations. + /// + GtPreMemConfig->GmAdr =3D 0xD0000000; + GtPreMemConfig->GttMmAdr =3D 0xCF000000; + GtPreMemConfig->GttSize =3D 3; + GtPreMemConfig->IgdDvmt50PreAlloc =3D 1; + GtPreMemConfig->InternalGraphics =3D 2; + GtPreMemConfig->PrimaryDisplay =3D 3; + GtPreMemConfig->ApertureSize =3D SA_GT_APERTURE_SIZE_256MB; + GtPreMemConfig->PanelPowerEnable =3D 1; +} + +VOID +LoadGraphichsPeiDefault ( + IN VOID *ConfigBlockPointer + ) +{ + GRAPHICS_PEI_CONFIG *GtConfig; + + GtConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "GtConfig->Header.GuidHob.Name =3D %g\n", &GtConfig-= >Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "GtConfig->Header.GuidHob.Header.HobLength =3D 0x%x\= n", GtConfig->Header.GuidHob.Header.HobLength)); + + // + // Initialize the Graphics configuration + // + GtConfig->RenderStandby =3D 1; + GtConfig->PavpEnable =3D 1; + GtConfig->PmSupport =3D 1; + GtConfig->CdynmaxClampEnable =3D 1; + GtConfig->GtFreqMax =3D 0xFF; + // + // Initialize the default VBT settings + // + GtConfig->DdiConfiguration.DdiPortEdp =3D 1; + GtConfig->DdiConfiguration.DdiPortBHpd =3D 1; + GtConfig->DdiConfiguration.DdiPortCHpd =3D 1; + GtConfig->DdiConfiguration.DdiPortDHpd =3D 1; + GtConfig->DdiConfiguration.DdiPortFHpd =3D 0; + GtConfig->DdiConfiguration.DdiPortBDdc =3D 1; + GtConfig->DdiConfiguration.DdiPortCDdc =3D 1; + GtConfig->DdiConfiguration.DdiPortDDdc =3D 1; + GtConfig->DdiConfiguration.DdiPortFDdc =3D 0; + + /// + /// Initialize the CdClock to 675 Mhz + /// + GtConfig->CdClock =3D 3; +} + +VOID +LoadSwitchableGraphichsDefault ( + IN VOID *ConfigBlockPointer + ) +{ + SWITCHABLE_GRAPHICS_CONFIG *SgConfig; + SgConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "SgConfig->Header.GuidHob.Name =3D %g\n", &SgConfig-= >Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "SgConfig->Header.GuidHob.Header.HobLength =3D 0x%x\= n", SgConfig->Header.GuidHob.Header.HobLength)); + SgConfig->SaRtd3Pcie0Gpio.GpioSupport =3D NotSupported; + SgConfig->SaRtd3Pcie1Gpio.GpioSupport =3D NotSupported; + SgConfig->SaRtd3Pcie2Gpio.GpioSupport =3D NotSupported; +} + +VOID +LoadMemConfigNoCrcDefault ( + IN VOID *ConfigBlockPointer + ) +{ + + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + + MemConfigNoCrc =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "MemConfigNoCrc->Header.GuidHob.Name =3D %g\n", &Mem= ConfigNoCrc->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "MemConfigNoCrc->Header.GuidHob.Header.HobLength =3D= 0x%x\n", MemConfigNoCrc->Header.GuidHob.Header.HobLength)); + // + // Allocating memory space for pointer structures inside MemConfigNoCrc + // + MemConfigNoCrc->SpdData =3D (SPD_DATA_BUFFER *) AllocateZeroPool (sizeof= (SPD_DATA_BUFFER)); + ASSERT (MemConfigNoCrc->SpdData !=3D NULL); + if (MemConfigNoCrc->SpdData =3D=3D NULL) { + return; + } + + MemConfigNoCrc->DqByteMap =3D (SA_MEMORY_DQ_MAPPING *) AllocateZeroPool = (sizeof (SA_MEMORY_DQ_MAPPING)); + ASSERT (MemConfigNoCrc->DqByteMap !=3D NULL); + if (MemConfigNoCrc->DqByteMap =3D=3D NULL) { + return; + } + + MemConfigNoCrc->DqsMap =3D (SA_MEMORY_DQS_MAPPING *) AllocateZeroPool (s= izeof (SA_MEMORY_DQS_MAPPING)); + ASSERT (MemConfigNoCrc->DqsMap !=3D NULL); + if (MemConfigNoCrc->DqsMap =3D=3D NULL) { + return; + } + + MemConfigNoCrc->RcompData =3D (SA_MEMORY_RCOMP *) AllocateZeroPool (size= of (SA_MEMORY_RCOMP)); + ASSERT (MemConfigNoCrc->RcompData !=3D NULL); + if (MemConfigNoCrc->RcompData =3D=3D NULL) { + return; + } + + // + // Set PlatformMemory Size + // + + MemConfigNoCrc->PlatformMemorySize =3D PEI_MIN_MEMORY_SIZE; + + MemConfigNoCrc->SerialDebugLevel =3D 3; //< Enable MRC debug message + + MemConfigNoCrc->MemTestOnWarmBoot =3D 1; //< Enable to run BaseMemoryTe= st on warm boot by default + +} + +VOID +LoadGnaDefault ( + IN VOID *ConfigBlockPointer + ) +{ + GNA_CONFIG *GnaConfig; + GnaConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "GnaConfig->Header.GuidHob.Name =3D %g\n", &GnaConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "GnaConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", GnaConfig->Header.GuidHob.Header.HobLength)); + GnaConfig->GnaEnable =3D TRUE; +} + +VOID +LoadMemConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + MEMORY_CONFIGURATION *MemConfig; + CPU_FAMILY CpuFamily; + UINT16 DeviceId; + + CPU_SKU CpuSku; + CpuSku =3D GetCpuSku (); + CpuFamily =3D GetCpuFamily (); + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, S= A_MC_BUS, 0, 0, R_SA_MC_DEVICE_ID)); + + MemConfig =3D ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "MemConfig->Header.GuidHob.Name =3D %g\n", &MemConfi= g->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "MemConfig->Header.GuidHob.Header.HobLength =3D 0x%x= \n", MemConfig->Header.GuidHob.Header.HobLength)); + // + // Initialize the Memory Configuration + // + MemConfig->EnBER =3D 1; + MemConfig->EccSupport =3D 1; + MemConfig->ScramblerSupport =3D 1; + MemConfig->PowerDownMode =3D 0xFF; + MemConfig->RankInterleave =3D TRUE; + MemConfig->EnhancedInterleave =3D TRUE; + MemConfig->EnCmdRate =3D 3; + MemConfig->AutoSelfRefreshSupport =3D TRUE; + MemConfig->ExtTemperatureSupport =3D TRUE; + MemConfig->WeaklockEn =3D 1; + MemConfig->Ddr4MixedUDimm2DpcLimit =3D 1; + + MemConfig->DualDimmPerChannelBoardType =3D (CpuFamily =3D=3D EnumCpuCflD= tHalo) ? TRUE : FALSE; + + // + // Channel Hash Configuration + // + MemConfig->ChHashEnable =3D TRUE; + MemConfig->ChHashMask =3D 0; + MemConfig->ChHashInterleaveBit =3D 2; + MemConfig->PerBankRefresh =3D TRUE; + // + // Options for Thermal settings + // + MemConfig->EnablePwrDn =3D 1; + MemConfig->EnablePwrDnLpddr =3D 1; + MemConfig->DdrThermalSensor =3D 1; + + MemConfig->EnergyScaleFact =3D 4; + MemConfig->IdleEnergyCh0Dimm0 =3D 0xA; + MemConfig->IdleEnergyCh0Dimm1 =3D 0xA; + MemConfig->IdleEnergyCh1Dimm0 =3D 0xA; + MemConfig->IdleEnergyCh1Dimm1 =3D 0xA; + MemConfig->PdEnergyCh0Dimm0 =3D 0x6; + MemConfig->PdEnergyCh0Dimm1 =3D 0x6; + MemConfig->PdEnergyCh1Dimm0 =3D 0x6; + MemConfig->PdEnergyCh1Dimm1 =3D 0x6; + MemConfig->ActEnergyCh0Dimm0 =3D 0xAC; + MemConfig->ActEnergyCh0Dimm1 =3D 0xAC; + MemConfig->ActEnergyCh1Dimm0 =3D 0xAC; + MemConfig->ActEnergyCh1Dimm1 =3D 0xAC; + MemConfig->RdEnergyCh0Dimm0 =3D 0xD4; + MemConfig->RdEnergyCh0Dimm1 =3D 0xD4; + MemConfig->RdEnergyCh1Dimm0 =3D 0xD4; + MemConfig->RdEnergyCh1Dimm1 =3D 0xD4; + MemConfig->WrEnergyCh0Dimm0 =3D 0xDD; + MemConfig->WrEnergyCh0Dimm1 =3D 0xDD; + MemConfig->WrEnergyCh1Dimm0 =3D 0xDD; + MemConfig->WrEnergyCh1Dimm1 =3D 0xDD; + MemConfig->WarmThresholdCh0Dimm0 =3D 0xFF; + MemConfig->WarmThresholdCh0Dimm1 =3D 0xFF; + MemConfig->WarmThresholdCh1Dimm0 =3D 0xFF; + MemConfig->WarmThresholdCh1Dimm1 =3D 0xFF; + MemConfig->HotThresholdCh0Dimm0 =3D 0xFF; + MemConfig->HotThresholdCh0Dimm1 =3D 0xFF; + MemConfig->HotThresholdCh1Dimm0 =3D 0xFF; + MemConfig->HotThresholdCh1Dimm1 =3D 0xFF; + MemConfig->WarmBudgetCh0Dimm0 =3D 0xFF; + MemConfig->WarmBudgetCh0Dimm1 =3D 0xFF; + MemConfig->WarmBudgetCh1Dimm0 =3D 0xFF; + MemConfig->WarmBudgetCh1Dimm1 =3D 0xFF; + MemConfig->HotBudgetCh0Dimm0 =3D 0xFF; + MemConfig->HotBudgetCh0Dimm1 =3D 0xFF; + MemConfig->HotBudgetCh1Dimm0 =3D 0xFF; + MemConfig->HotBudgetCh1Dimm1 =3D 0xFF; + + MemConfig->SrefCfgEna =3D 1; + MemConfig->SrefCfgIdleTmr =3D 0x200; + MemConfig->ThrtCkeMinTmr =3D 0x30; + MemConfig->ThrtCkeMinDefeatLpddr =3D 1; + MemConfig->ThrtCkeMinTmrLpddr =3D 0x40; + + MemConfig->RaplLim2WindX =3D 1; + MemConfig->RaplLim2WindY =3D 1; + MemConfig->RaplLim2Pwr =3D 0xDE; + + // + // CA Vref routing: board-dependent + // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L) + // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used) + // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4) + // + //MemConfig->CaVrefConfig =3D 0; + MemConfig->VttTermination =3D ((CpuSku =3D=3D EnumCpuUlx) || (CpuSku= =3D=3D EnumCpuUlt)); + MemConfig->VttCompForVsshi =3D 0; + +#ifdef UP_SERVER_FLAG + MemConfig->TsodTcritmax =3D 0x69; + MemConfig->TsodThigMax =3D 0x5D; +#endif + + + // + // MRC training steps + // + MemConfig->ECT =3D 1; + MemConfig->ERDMPRTC2D =3D 1; + MemConfig->SOT =3D 1; + MemConfig->RDMPRT =3D 1; + MemConfig->RCVET =3D 1; + MemConfig->JWRL =3D 1; + MemConfig->EWRTC2D =3D 1; + MemConfig->ERDTC2D =3D 1; + MemConfig->WRTC1D =3D 1; + MemConfig->WRVC1D =3D 1; + MemConfig->RDTC1D =3D 1; + MemConfig->DIMMODTT =3D 1; + MemConfig->DIMMRONT =3D 1; + MemConfig->WRSRT =3D 1; + MemConfig->RDODTT =3D 1; + MemConfig->RDAPT =3D 1; + MemConfig->WRTC2D =3D 1; + MemConfig->RDTC2D =3D 1; + MemConfig->CMDVC =3D 1; + MemConfig->WRVC2D =3D 1; + MemConfig->RDVC2D =3D 1; + MemConfig->LCT =3D 1; + MemConfig->RTL =3D 1; + MemConfig->TAT =3D 1; + MemConfig->ALIASCHK =3D 1; + MemConfig->RCVENC1D =3D 1; + MemConfig->RMC =3D 1; + MemConfig->CMDSR =3D 1; + MemConfig->CMDDSEQ =3D 1; + MemConfig->CMDNORM =3D 1; + MemConfig->EWRDSEQ =3D 1; + MemConfig->McLock =3D TRUE; + MemConfig->GdxcIotSize =3D 4; + MemConfig->GdxcMotSize =3D 12; + MemConfig->RDEQT =3D 1; + + MemConfig->MrcFastBoot =3D TRUE; + MemConfig->MrcTrainOnWarm =3D FALSE; + MemConfig->RemapEnable =3D TRUE; + MemConfig->BClkFrequency =3D 100 * 1000 * 1000; + +#ifdef EMBEDDED_FLAG + MemConfig->Force1Dpc =3D TRUE; +#endif + MemConfig->Vc1ReadMeter =3D TRUE; + MemConfig->Vc1ReadMeterTimeWindow =3D 0x320; + MemConfig->Vc1ReadMeterThreshold =3D 0x118; + MemConfig->StrongWkLeaker =3D 7; + + MemConfig->MobilePlatform =3D (IS_SA_DEVICE_ID_MOBILE (DeviceId)) ? = TRUE : FALSE; + MemConfig->PciIndex =3D 0xCF8; + MemConfig->PciData =3D 0xCFC; + MemConfig->CkeRankMapping =3D 0xAA; + + // This only affects ULX/ULT; otherwise SA GV is disabled. + // CFL SA GV: 0 - Disabled, 1 - FixedLow, 2 - FixedHigh, 3 - Enabled + MemConfig->SaGv =3D 3; + MemConfig->SimicsFlag =3D 0; + + MemConfig->Idd3n =3D 26; + MemConfig->Idd3p =3D 11; + + MemConfig->RhPrevention =3D TRUE; // Row Hammer prevention. + MemConfig->RhSolution =3D HardwareRhp; // Type of solution to b= e used for RHP - 0/1 =3D HardwareRhp/Refresh2x + MemConfig->RhActProbability =3D OneIn2To11; // Activation probabili= ty for Hardware RHP + + MemConfig->LpddrMemWriteLatencySet =3D 1; // Enable LPDDR3 WL Set B if = supported by DRAM + + MemConfig->DllBwEn1 =3D 1; + MemConfig->DllBwEn2 =3D 2; + MemConfig->DllBwEn3 =3D 2; + + MemConfig->RetrainOnFastFail =3D 1; // Restart MRC in Cold mode if SW = MemTest fails during Fast flow. 0 =3D Disabled, 1 =3D Enabled + MemConfig->Lp4DqsOscEn =3D 1; + MemConfig->IsvtIoPort =3D 0x99; +} + + +VOID +LoadOverClockConfigDefault ( + IN VOID *ConfigBlockPointer + ) +{ + OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig; + OcPreMemConfig =3D (OVERCLOCKING_PREMEM_CONFIG *)ConfigBlockPointer; + DEBUG ((DEBUG_INFO, "OcPreMemConfig->Header.GuidHob.Name =3D %g\n", &OcP= reMemConfig->Header.GuidHob.Name)); + DEBUG ((DEBUG_INFO, "OcPreMemConfig->Header.GuidHob.Header.HobLength =3D= 0x%x\n", OcPreMemConfig->Header.GuidHob.Header.HobLength)); +} + +static COMPONENT_BLOCK_ENTRY mSaIpBlocksPreMem [] =3D { + {&gSaMiscPeiPreMemConfigGuid, sizeof (SA_MISC_PEI_PREMEM_CONFIG), = SA_MISC_PEI_PREMEM_CONFIG_REVISION, LoadSaMiscPeiPreMemDefault}, + {&gSaPciePeiPreMemConfigGuid, sizeof (PCIE_PEI_PREMEM_CONFIG), = SA_PCIE_PEI_PREMEM_CONFIG_REVISION, LoadPciePeiPreMemDefault}, + {&gGraphicsPeiPreMemConfigGuid, sizeof (GRAPHICS_PEI_PREMEM_CONFIG),= GRAPHICS_PEI_PREMEM_CONFIG_REVISION, LoadGraphichsPeiPreMemDefault}, + {&gSwitchableGraphicsConfigGuid, sizeof (SWITCHABLE_GRAPHICS_CONFIG),= SWITCHABLE_GRAPHICS_CONFIG_REVISION, LoadSwitchableGraphichsDefault}, + {&gMemoryConfigGuid, sizeof (MEMORY_CONFIGURATION), = MEMORY_CONFIG_REVISION, LoadMemConfigDefault}, + {&gMemoryConfigNoCrcGuid, sizeof (MEMORY_CONFIG_NO_CRC), = MEMORY_CONFIG_REVISION, LoadMemConfigNoCrcDefault}, + {&gSaOverclockingPreMemConfigGuid, sizeof (OVERCLOCKING_PREMEM_CONFIG),= SA_OVERCLOCKING_CONFIG_REVISION, LoadOverClockConfigDefault}, + {&gVtdConfigGuid, sizeof (VTD_CONFIG), = VTD_CONFIG_REVISION, LoadVtdDefault}, + {&gIpuPreMemConfigGuid, sizeof (IPU_PREMEM_CONFIG), = IPU_PREMEM_CONFIG_REVISION, LoadIpuPreMemDefault} +}; + +static COMPONENT_BLOCK_ENTRY mSaIpBlocks [] =3D { + {&gSaMiscPeiConfigGuid, sizeof (SA_MISC_PEI_CONFIG), SA_MISC_PEI= _CONFIG_REVISION, LoadSaMiscPeiDefault}, + {&gSaPciePeiConfigGuid, sizeof (PCIE_PEI_CONFIG), SA_PCIE_PEI= _CONFIG_REVISION, LoadPciePeiDefault}, + {&gGraphicsPeiConfigGuid, sizeof (GRAPHICS_PEI_CONFIG), GRAPHICS_PE= I_CONFIG_REVISION, LoadGraphichsPeiDefault}, + {&gGnaConfigGuid, sizeof (GNA_CONFIG), GNA_CONFIG_= REVISION, LoadGnaDefault} +}; + +/** + Get SA config block table total size. + + @retval Size of SA config block table +**/ +UINT16 +EFIAPI +SaGetConfigBlockTotalSize ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mSaIpBlocks[0], sizeof (mSaIpB= locks) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + Get SA config block table total size. + + @retval Size of SA config block table +**/ +UINT16 +EFIAPI +SaGetConfigBlockTotalSizePreMem ( + VOID + ) +{ + return GetComponentConfigBlockTotalSize (&mSaIpBlocksPreMem[0], sizeof (= mSaIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY)); +} + +/** + SaAddConfigBlocksPreMem add all SA config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add SA config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +SaAddConfigBlocksPreMem ( + IN VOID *ConfigBlockTableAddress + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SA AddConfigBlocks. TotalBlockCount =3D 0x%x\n", s= izeof (mSaIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY))); + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress, &mSaIpBloc= ksPreMem[0], sizeof (mSaIpBlocksPreMem) / sizeof (COMPONENT_BLOCK_ENTRY)); + if (Status =3D=3D EFI_SUCCESS) { + SaLoadSamplePolicyPreMem (ConfigBlockTableAddress); + } + return Status; +} + +/** + SaAddConfigBlocks add all SA config blocks. + + @param[in] ConfigBlockTableAddress The pointer to add SA config blocks + + @retval EFI_SUCCESS The policy default is initialized. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer +**/ +EFI_STATUS +EFIAPI +SaAddConfigBlocks ( + IN VOID *ConfigBlockTableAddress + ) +{ + DEBUG ((DEBUG_INFO, "SA AddConfigBlocks. TotalBlockCount =3D 0x%x\n", s= izeof (mSaIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY))); + + return AddComponentConfigBlocks (ConfigBlockTableAddress, &mSaIpBlocks[0= ], sizeof (mSaIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY)); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/PeiSaPolicyLibSample.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemA= gent/Library/PeiSaPolicyLib/PeiSaPolicyLibSample.c new file mode 100644 index 0000000000..463e75702d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /PeiSaPolicyLibSample.c @@ -0,0 +1,284 @@ +/** @file + This file provides services for Sample PEI policy default initialization. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include "PeiSaPolicyLibrary.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include "MrcOemPlatform.h" +#include +#include +#include +#include + +// +// DQ byte mapping to CMD/CTL/CLK, from the CPU side +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapSkl[2][6][2] =3D { + // Channel 0: + { + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4] + { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4] + { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4] + { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0xFF, 0x00 } // CA Vref is one for all bytes + }, + // Channel 1: + { + { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4] + { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4] + { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4] + { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0xFF, 0x00 } // CA Vref is one for all bytes + } +}; + +// +// DQS byte swizzling between CPU and DRAM +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramSklRvp[2][8] =3D { + { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0 + { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1 +}; + +// +// Reference RCOMP resistors on motherboard +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mRcompResistorSklRvp1[SA_MRC_MA= X_RCOMP] =3D { 200, 81, 162 }; +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 mRcompTargetSklRvp1[SA_MRC_MAX_= RCOMP_TARGETS] =3D { 100, 40, 40, 23, 40 }; + +/** + Hynix H9CCNNN8JTMLAR-NTM_178b_DDP LPDDR3, 4Gb die (128Mx32), x32 + or Elpida EDF8132A1MC-GD-F + or Samsung K4E8E304EB-EGCE + 1600, 12-15-15-34 + 2 rank per channel, 2 SDRAMs per rank, 4x4Gb =3D 2GB total per channel +**/ +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mSkylakeRvp3Spd[] =3D { + 0x24, ///< 0 Number of Serial PD Bytes= Written / SPD Device Size + 0x20, ///< 1 SPD Revision + 0x0F, ///< 2 DRAM Device Type + 0x0E, ///< 3 Module Type + 0x14, ///< 4 SDRAM Density and Banks: = 8 Banks, 4 Gb SDRAM density + 0x11, ///< 5 SDRAM Addressing: 14 Rows= , 10 Columns + 0x90, ///< 6 SDRAM Package Type: Non-M= onolithic, DDP, 1 Channel per package + 0x00, ///< 7 SDRAM Optional Features + 0x00, ///< 8 SDRAM Thermal and Refresh= Options + 0x00, ///< 9 Other SDRAM Optional Feat= ures + 0x00, ///< 10 Reserved - must be coded = as 0x00 + 0x03, ///< 11 Module Nominal Voltage, V= DD + 0x0B, ///< 12 Module Organization, SDRA= M width: 32 bits, 2 Ranks + 0x03, ///< 13 Module Memory Bus Width: = 1 Channel, 64 bits channel width + 0x00, ///< 14 Module Thermal Sensor + 0x00, ///< 15 Extended Module Type + 0x00, ///< 16 Reserved - must be coded = as 0x00 + 0x00, ///< 17 Timebases + 0x0A, ///< 18 SDRAM Minimum Cycle Time = (tCKmin) + 0xFF, ///< 19 SDRAM Minimum Cycle Time = (tCKmax) + 0x54, ///< 20 CAS Latencies Supported, = First Byte (tCk): 12 10 8 + 0x00, ///< 21 CAS Latencies Supported, = Second Byte + 0x00, ///< 22 CAS Latencies Supported, = Third Byte + 0x00, ///< 23 CAS Latencies Supported, = Fourth Byte + 0x78, ///< 24 Minimum CAS Latency Time = (tAAmin) + 0x00, ///< 25 Read and Write Latency Se= t Options + 0x90, ///< 26 Minimum RAS# to CAS# Dela= y Time (tRCDmin) + 0xA8, ///< 27 Minimum Row Precharge Del= ay Time for all banks (tRPab) + 0x90, ///< 28 Minimum Row Precharge Del= ay Time per bank (tRPpb) + 0x10, ///< 29 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Least Significant Byte + 0x04, ///< 30 Minimum Refresh Recovery = Delay Time for all banks (tRFCab), Most Significant Byte + 0xE0, ///< 31 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Least Significant Byte + 0x01, ///< 32 Minimum Refresh Recovery = Delay Time for per bank (tRFCpb), Most Significant Byte + 0, 0, 0, 0, 0, 0, 0, ///< 33 - 39 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 40 - 49 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 50 - 59 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 60 - 69 Connector to SDRAM Bi= t Mapping + 0, 0, 0, 0, 0, 0, 0, 0, ///< 70 - 77 Connector to SDRAM Bi= t Mapping + 0, 0, ///< 78 - 79 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 80 - 89 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 90 - 99 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 100 - 109 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 110 - 119 + 0x00, ///< 120 Fine Offset for Minimum R= ow Precharge Delay Time per bank (tRPpb) + 0x00, ///< 121 Fine Offset for Minimum R= ow Precharge Delay Time for all banks (tRPab) + 0x00, ///< 122 Fine Offset for Minimum R= AS# to CAS# Delay Time (tRCDmin) + 0x00, ///< 123 Fine Offset for Minimum C= AS Latency Time (tAAmin) + 0x7F, ///< 124 Fine Offset for SDRAM Min= imum Cycle Time (tCKmax) + 0x00, ///< 125 Fine Offset for SDRAM Min= imum Cycle Time (tCKmin) + 0x00, ///< 126 CRC A + 0x00, ///< 127 CRC B + 0, 0, ///< 128 - 129 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 130 - 139 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 140 - 149 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 150 - 159 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 160 - 169 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 170 - 179 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 180 - 189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 190 - 199 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 200 - 209 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 210 - 219 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 220 - 229 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 230 - 239 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 240 - 249 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 250 - 259 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 260 - 269 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 270 - 279 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 280 - 289 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 290 - 299 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 300 - 309 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 310 - 319 + 0x00, ///< 320 Module Manufacturer ID Co= de, Least Significant Byte + 0x00, ///< 321 Module Manufacturer ID Co= de, Most Significant Byte + 0x00, ///< 322 Module Manufacturing Loca= tion + 0x00, ///< 323 Module Manufacturing Date= Year + 0x00, ///< 324 Module Manufacturing Date= Week + 0x55, ///< 325 Module Serial Number A + 0x00, ///< 326 Module Serial Number B + 0x00, ///< 327 Module Serial Number C + 0x00, ///< 328 Module Serial Number D + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 329 - 333 Module Part Number:= Unused bytes coded as ASCII Blanks (0x20) + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 334 - 338 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 339 - 343 Module Part Number + 0x20, 0x20, 0x20, 0x20, 0x20, ///< 344 - 348 Module Part Number + 0x00, ///< 349 Module Revision Code + 0x00, ///< 350 DRAM Manufacturer ID Code= , Least Significant Byte + 0x00, ///< 351 DRAM Manufacturer ID Code= , Most Significant Byte + 0x00, ///< 352 DRAM Stepping + 0, 0, 0, 0, 0, 0, 0, ///< 353 - 359 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 360 - 369 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 370 - 379 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 380 - 389 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 390 - 399 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 400 - 409 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 410 - 419 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 420 - 429 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 430 - 439 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 440 - 449 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 450 - 459 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 460 - 469 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 470 - 479 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 480 - 489 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 490 - 499 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ///< 500 - 509 + 0, 0 ///< 510 - 511 +}; + +#define SaIoRead8 IoRead8 +#define SaIoRead16 IoRead16 +#define SaIoRead32 IoRead32 +#define SaIoWrite8 IoWrite8 +#define SaIoWrite16 IoWrite16 +#define SaIoWrite32 IoWrite32 +#define SaCopyMem CopyMem +#define SaSetMem SetMem +#define SaLShiftU64 LShiftU64 +#define SaRShiftU64 RShiftU64 +#define SaMultU64x32 MultU64x32 + +/** + SaLoadSamplePolicyPreMem - Load some policy default for reference board. + + @param[in] ConfigBlockTableAddress The pointer for SA config blocks + +**/ +VOID +SaLoadSamplePolicyPreMem ( + IN VOID *ConfigBlockTableAddress + ) +{ + SA_FUNCTION_CALLS *MemCall; + EFI_STATUS Status; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + CPU_FAMILY CpuFamilyId; + UINT8 *DqByteMap; + BOOLEAN KblCpu; + + MemConfigNoCrc =3D NULL; + Status =3D GetConfigBlock (ConfigBlockTableAddress, &gMemoryConfigNoCrcG= uid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + + if (MemConfigNoCrc =3D=3D NULL) { + return; + } + CpuFamilyId =3D GetCpuFamily (); + KblCpu =3D ((CpuFamilyId =3D=3D EnumCpuCflUltUlx) || (CpuFamilyId =3D=3D= EnumCpuCflDtHalo)); + + DEBUG ((DEBUG_INFO, "Applying Sample policy defaults for RVP3\n")); + MemCall =3D &MemConfigNoCrc->SaCall; + MemCall->IoRead8 =3D &SaIoRead8; + MemCall->IoRead16 =3D &SaIoRead16; + MemCall->IoRead32 =3D &SaIoRead32; + MemCall->IoWrite8 =3D &SaIoWrite8; + MemCall->IoWrite16 =3D &SaIoWrite16; + MemCall->IoWrite32 =3D &SaIoWrite32; + MemCall->MmioRead8 =3D &MmioRead8; + MemCall->MmioRead16 =3D &MmioRead16; + MemCall->MmioRead32 =3D &MmioRead32; + MemCall->MmioRead64 =3D &SaMmioRead64; + MemCall->MmioWrite8 =3D &MmioWrite8; + MemCall->MmioWrite16 =3D &MmioWrite16; + MemCall->MmioWrite32 =3D &MmioWrite32; + MemCall->MmioWrite64 =3D &SaMmioWrite64; + MemCall->SmbusRead8 =3D &SmBusReadDataByte; + MemCall->SmbusRead16 =3D &SmBusReadDataWord; + MemCall->SmbusWrite8 =3D &SmBusWriteDataByte; + MemCall->SmbusWrite16 =3D &SmBusWriteDataWord; + MemCall->GetPciDeviceAddress =3D &GetPciDeviceAddress; + MemCall->GetPcieDeviceAddress =3D &GetPcieDeviceAddress; + MemCall->GetRtcTime =3D &GetRtcTime; + MemCall->GetCpuTime =3D &GetCpuTime; + MemCall->CopyMem =3D &SaCopyMem; + MemCall->SetMem =3D &SaSetMem; + MemCall->SetMemWord =3D &SetMemWord; + MemCall->SetMemDword =3D &SetMemDword; + MemCall->LeftShift64 =3D &SaLShiftU64; + MemCall->RightShift64 =3D &SaRShiftU64; + MemCall->MultU64x32 =3D &SaMultU64x32; + MemCall->DivU64x64 =3D &DivU64x64Remainder; + MemCall->GetSpdData =3D &GetSpdData; + MemCall->GetRandomNumber =3D &GetRandomNumber32; + MemCall->CpuMailboxRead =3D &MailboxRead; + MemCall->CpuMailboxWrite =3D &MailboxWrite; + MemCall->GetMemoryVdd =3D &GetMemoryVdd; + MemCall->SetMemoryVdd =3D &SetMemoryVdd; + MemCall->CheckPoint =3D &CheckPoint; + MemCall->DebugHook =3D &DebugHook; + MemCall->DebugPrint =3D &SaDebugPrint; + MemCall->GetRtcCmos =3D &PeiRtcRead; + MemCall->ReadMsr64 =3D &AsmReadMsr64; + MemCall->WriteMsr64 =3D &AsmWriteMsr64; + MemCall->MrcReturnFromSmc =3D &ReturnFromSmc; + MemCall->MrcDramReset =3D &SaDramReset; + + // + // RCOMP resistors and target values: board-dependent + // + if (KblCpu) { + CopyMem ((VOID *) MemConfigNoCrc->RcompData->RcompResistor, mRcompResi= storSklRvp1, sizeof (mRcompResistorSklRvp1)); + CopyMem ((VOID *) MemConfigNoCrc->RcompData->RcompTarget, mRcompTarg= etSklRvp1, sizeof (mRcompTargetSklRvp1)); + } + + CopyMem ((VOID *) MemConfigNoCrc->SpdData->SpdData[0][0], mSkylakeRvp3Sp= d, sizeof (mSkylakeRvp3Spd)); + CopyMem ((VOID *) MemConfigNoCrc->SpdData->SpdData[1][0], mSkylakeRvp3Sp= d, sizeof (mSkylakeRvp3Spd)); + + DqByteMap =3D (UINT8 *) mDqByteMapSkl; + + CopyMem ((VOID *) MemConfigNoCrc->DqByteMap, DqByteMap, sizeof (UINT8) *= SA_MC_MAX_CHANNELS * SA_MRC_ITERATION_MAX * 2); + CopyMem ((VOID *) MemConfigNoCrc->DqsMap, mDqsMapCpu2DramSklRvp, sizeof = (UINT8) * SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO_ECC); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/SaPrintPolicy.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Li= brary/PeiSaPolicyLib/SaPrintPolicy.c new file mode 100644 index 0000000000..ce3ef52733 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /SaPrintPolicy.c @@ -0,0 +1,559 @@ +/** @file + This file provides service for PEI phase policy printing + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyLibrary.h" +#include + +/** + This function prints the PEI phase PreMem policy. + + @param[in] SiPolicyPreMemPpi - Instance of SI_PREMEM_POLICY_PPI +**/ +VOID +EFIAPI +SaPrintPolicyPpiPreMem ( + IN SI_PREMEM_POLICY_PPI *SiPolicyPreMemPpi + ) +{ + DEBUG_CODE_BEGIN (); + INTN Index; + INTN Index2; + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig; + MEMORY_CONFIGURATION *MemConfig; + PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig; + SWITCHABLE_GRAPHICS_CONFIG *SgConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + VTD_CONFIG *Vtd; + OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig; + IPU_PREMEM_CONFIG *IpuPreMemPolicy; + + // + // Get requisite IP Config Blocks which needs to be used here + // + Status =3D GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gSaMiscPeiPreMemC= onfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gGraphicsPeiPreMe= mConfigGuid, (VOID *) &GtPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicyPreMemPpi, &gVtdConfigGuid, = (VOID *) &Vtd); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gMemoryConfigGuid= , (VOID *) &MemConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gSaPciePeiPreMemC= onfigGuid, (VOID *) &PciePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gSwitchableGraphi= csConfigGuid, (VOID *) &SgConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SiPolicyPreMemPpi, &gMemoryConfigNoCr= cGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPreMemPpi, &gSaOverclockingP= reMemConfigGuid, (VOID *) &OcPreMemConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPreMemPpi, &gIpuPreMemConfig= Guid, (VOID *) &IpuPreMemPolicy); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) P= rint BEGIN -----------------\n")); + DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPreMemPpi->TableHeader.= Header.Revision)); + ASSERT (SiPolicyPreMemPpi->TableHeader.Header.Revision =3D=3D SI_PREMEM_= POLICY_REVISION); + + DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_PEI_PREMEM_CONFIG = -----------------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiPreMemConfig->Header.Revi= sion)); + ASSERT (MiscPeiPreMemConfig->Header.Revision =3D=3D SA_MISC_PEI_PREMEM_C= ONFIG_REVISION); + DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", SA_MC_MAX_SOCKETS)); + for (Index =3D 0; Index < SA_MC_MAX_SOCKETS; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", MiscPeiPreMemConfig->SpdAddressTable[Inde= x])); + } + + DEBUG ((DEBUG_INFO, "\n MchBar : 0x%x\n", MiscPeiPreMemConfig->MchBar)); + DEBUG ((DEBUG_INFO, " DmiBar : 0x%x\n", MiscPeiPreMemConfig->DmiBar)); + DEBUG ((DEBUG_INFO, " EpBar : 0x%x\n", MiscPeiPreMemConfig->EpBar)); + DEBUG ((DEBUG_INFO, " SmbusBar : 0x%x\n", MiscPeiPreMemConfig->SmbusBar)= ); + DEBUG ((DEBUG_INFO, " GdxcBar : 0x%x\n", MiscPeiPreMemConfig->GdxcBar)); + DEBUG ((DEBUG_INFO, " TsegSize : 0x%x\n", MiscPeiPreMemConfig->TsegSize)= ); + DEBUG ((DEBUG_INFO, " UserBd : 0x%x\n", MiscPeiPreMemConfig->UserBd)); + DEBUG ((DEBUG_INFO, " EdramBar : 0x%x\n", MiscPeiPreMemConfig->EdramBar)= ); + DEBUG ((DEBUG_INFO, " MmioSize : %d MB\n", MiscPeiPreMemConfig->MmioSize= )); + DEBUG ((DEBUG_INFO, " MmioSizeAdjustment : %d MB\n", MiscPeiPreMemConfig= ->MmioSizeAdjustment)); + DEBUG ((DEBUG_INFO, " SkipExtGfxScan: 0x%x\n", MiscPeiPreMemConfig->Skip= ExtGfxScan)); + DEBUG ((DEBUG_INFO, " S3DataPtr : 0x%x\n", MiscPeiPreMemConfig->S3DataPt= r)); + DEBUG ((DEBUG_INFO, "------------------------ SG_DELAY_OPTIMIZATION_DATA= -----------------\n")); + DEBUG ((DEBUG_INFO, " SaRtd3.SgDelayAfterHoldReset : 0x%x\n", MiscPeiPre= MemConfig->SgDelayAfterHoldReset)); + DEBUG ((DEBUG_INFO, " SaRtd3.SgDelayAfterPwrEn : 0x%x\n", MiscPeiPre= MemConfig->SgDelayAfterPwrEn)); + + DEBUG ((DEBUG_INFO, " ScanExtGfxForLegacyOpRom : 0x%x\n", MiscPeiPreMemC= onfig->ScanExtGfxForLegacyOpRom)); + DEBUG ((DEBUG_INFO, " AcpiReservedMemoryBase : 0x%x\n", MiscPeiPreMemCon= fig->AcpiReservedMemoryBase)); + DEBUG ((DEBUG_INFO, " AcpiReservedMemorySize : 0x%x\n", MiscPeiPreMemCon= fig->AcpiReservedMemorySize)); + DEBUG ((DEBUG_INFO, " SystemMemoryLength : 0x%x\n", MiscPeiPreMemConfig-= >SystemMemoryLength)); + DEBUG ((DEBUG_INFO, " OpRomScanTempMmioBar : 0x%x\n", MiscPeiPreMemConfi= g->OpRomScanTempMmioBar)); + DEBUG ((DEBUG_INFO, " OpRomScanTempMmioLimit : 0x%x\n", MiscPeiPreMemCon= fig->OpRomScanTempMmioLimit)); + + DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_PREMEM_CONFIG= -----------------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", GtPreMemConfig->Header.Revision)= ); + ASSERT (GtPreMemConfig->Header.Revision =3D=3D GRAPHICS_PEI_PREMEM_CONFI= G_REVISION); + DEBUG ((DEBUG_INFO, " PanelPowerEnable : 0x%x\n", GtPreMemConfig->PanelP= owerEnable)); + DEBUG ((DEBUG_INFO, " GttSize : %d MB\n", GtPreMemConfig->GttSize)); + DEBUG ((DEBUG_INFO, " IgdDvmt50PreAlloc : 0x%x\n", GtPreMemConfig->IgdDv= mt50PreAlloc)); + DEBUG ((DEBUG_INFO, " InternalGraphics : 0x%x\n", GtPreMemConfig->Intern= alGraphics)); + DEBUG ((DEBUG_INFO, " PrimaryDisplay : 0x%x\n", GtPreMemConfig->PrimaryD= isplay)); + DEBUG ((DEBUG_INFO, " ApertureSize : 0x%x\n", GtPreMemConfig->ApertureSi= ze)); + DEBUG ((DEBUG_INFO, " GtPsmiSupport : 0x%x\n", GtPreMemConfig->GtPsmiSup= port)); + DEBUG ((DEBUG_INFO, " PsmiRegionSize : 0x%x\n", GtPreMemConfig->PsmiRegi= onSize)); + DEBUG ((DEBUG_INFO, " GttMmAdr : 0x%x\n", GtPreMemConfig->GttMmAdr)); + DEBUG ((DEBUG_INFO, " GmAdr : 0x%x\n", GtPreMemConfig->GmAdr)); + DEBUG ((DEBUG_INFO, " DeltaT12PowerCycleDelayPreMem : 0x%x\n", GtPreMemC= onfig->DeltaT12PowerCycleDelayPreMem)); + + DEBUG ((DEBUG_INFO, "------------------------ PCIE_PEI_PREMEM_CONFIG ---= --------------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", PciePeiPreMemConfig->Header.Revi= sion)); + ASSERT (PciePeiPreMemConfig->Header.Revision =3D=3D SA_PCIE_PEI_PREMEM_C= ONFIG_REVISION); + DEBUG ((DEBUG_INFO, " DmiMaxLinkSpeed : 0x%x\n", PciePeiPreMemConfig->Dm= iMaxLinkSpeed)); + DEBUG ((DEBUG_INFO, " DmiGen3EqPh2Enable : 0x%x\n", PciePeiPreMemConfig-= >DmiGen3EqPh2Enable)); + DEBUG ((DEBUG_INFO, " DmiGen3EqPh3Method : 0x%x\n", PciePeiPreMemConfig-= >DmiGen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " DmiGen3ProgramStaticEq : 0x%x\n", PciePeiPreMemCon= fig->DmiGen3ProgramStaticEq)); + DEBUG ((DEBUG_INFO, " Peg0Enable : 0x%x\n", PciePeiPreMemConfig->Peg0Ena= ble)); + DEBUG ((DEBUG_INFO, " Peg1Enable : 0x%x\n", PciePeiPreMemConfig->Peg1Ena= ble)); + DEBUG ((DEBUG_INFO, " Peg2Enable : 0x%x\n", PciePeiPreMemConfig->Peg2Ena= ble)); + DEBUG ((DEBUG_INFO, " Peg3Enable : 0x%x\n", PciePeiPreMemConfig->Peg3Ena= ble)); + DEBUG ((DEBUG_INFO, " Peg0MaxLinkSpeed : 0x%x\n", PciePeiPreMemConfig->P= eg0MaxLinkSpeed)); + DEBUG ((DEBUG_INFO, " Peg1MaxLinkSpeed : 0x%x\n", PciePeiPreMemConfig->P= eg1MaxLinkSpeed)); + DEBUG ((DEBUG_INFO, " Peg2MaxLinkSpeed : 0x%x\n", PciePeiPreMemConfig->P= eg2MaxLinkSpeed)); + DEBUG ((DEBUG_INFO, " Peg3MaxLinkSpeed : 0x%x\n", PciePeiPreMemConfig->P= eg3MaxLinkSpeed)); + DEBUG ((DEBUG_INFO, " Peg0MaxLinkWidth : 0x%x\n", PciePeiPreMemConfig->P= eg0MaxLinkWidth)); + DEBUG ((DEBUG_INFO, " Peg1MaxLinkWidth : 0x%x\n", PciePeiPreMemConfig->P= eg1MaxLinkWidth)); + DEBUG ((DEBUG_INFO, " Peg2MaxLinkWidth : 0x%x\n", PciePeiPreMemConfig->P= eg2MaxLinkWidth)); + DEBUG ((DEBUG_INFO, " Peg3MaxLinkWidth : 0x%x\n", PciePeiPreMemConfig->P= eg3MaxLinkWidth)); + DEBUG ((DEBUG_INFO, " Peg0PowerDownUnusedLanes : 0x%x\n", PciePeiPreMemC= onfig->Peg0PowerDownUnusedLanes)); + DEBUG ((DEBUG_INFO, " Peg1PowerDownUnusedLanes : 0x%x\n", PciePeiPreMemC= onfig->Peg1PowerDownUnusedLanes)); + DEBUG ((DEBUG_INFO, " Peg2PowerDownUnusedLanes : 0x%x\n", PciePeiPreMemC= onfig->Peg2PowerDownUnusedLanes)); + DEBUG ((DEBUG_INFO, " Peg3PowerDownUnusedLanes : 0x%x\n", PciePeiPreMemC= onfig->Peg3PowerDownUnusedLanes)); + DEBUG ((DEBUG_INFO, " Peg0Gen3EqPh2Enable : 0x%x\n", PciePeiPreMemConfig= ->Peg0Gen3EqPh2Enable)); + DEBUG ((DEBUG_INFO, " Peg1Gen3EqPh2Enable : 0x%x\n", PciePeiPreMemConfig= ->Peg1Gen3EqPh2Enable)); + DEBUG ((DEBUG_INFO, " Peg2Gen3EqPh2Enable : 0x%x\n", PciePeiPreMemConfig= ->Peg2Gen3EqPh2Enable)); + DEBUG ((DEBUG_INFO, " Peg3Gen3EqPh2Enable : 0x%x\n", PciePeiPreMemConfig= ->Peg3Gen3EqPh2Enable)); + DEBUG ((DEBUG_INFO, " Peg0Gen3EqPh3Method : 0x%x\n", PciePeiPreMemConfig= ->Peg0Gen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " Peg1Gen3EqPh3Method : 0x%x\n", PciePeiPreMemConfig= ->Peg1Gen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " Peg2Gen3EqPh3Method : 0x%x\n", PciePeiPreMemConfig= ->Peg2Gen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " Peg3Gen3EqPh3Method : 0x%x\n", PciePeiPreMemConfig= ->Peg3Gen3EqPh3Method)); + DEBUG ((DEBUG_INFO, " PegGen3ProgramStaticEq : 0x%x\n", PciePeiPreMemCon= fig->PegGen3ProgramStaticEq)); + DEBUG ((DEBUG_INFO, " Gen3SwEqAlwaysAttempt : 0x%x\n", PciePeiPreMemConf= ig->Gen3SwEqAlwaysAttempt)); + DEBUG ((DEBUG_INFO, " Gen3SwEqNumberOfPresets : 0x%x\n", PciePeiPreMemCo= nfig->Gen3SwEqNumberOfPresets)); + DEBUG ((DEBUG_INFO, " Gen3SwEqEnableVocTest : 0x%x\n", PciePeiPreMemConf= ig->Gen3SwEqEnableVocTest)); + DEBUG ((DEBUG_INFO, " InitPcieAspmAfterOprom : 0x%x\n", PciePeiPreMemCon= fig->InitPcieAspmAfterOprom)); + DEBUG ((DEBUG_INFO, " PegRxCemTestingMode : 0x%x\n", PciePeiPreMemConfig= ->PegRxCemTestingMode)); + DEBUG ((DEBUG_INFO, " PegRxCemLoopbackLane : 0x%x\n", PciePeiPreMemConfi= g->PegRxCemLoopbackLane)); + DEBUG ((DEBUG_INFO, " PegRxCemNonProtocolAwareness : 0x%x\n", PciePeiPre= MemConfig->PegRxCemNonProtocolAwareness)); + DEBUG ((DEBUG_INFO, " PegDisableSpreadSpectrumClocking : 0x%x\n", PciePe= iPreMemConfig->PegDisableSpreadSpectrumClocking)); + DEBUG ((DEBUG_INFO, " PegGenerateBdatMarginTable : 0x%x\n", PciePeiPreMe= mConfig->PegGenerateBdatMarginTable)); + DEBUG ((DEBUG_INFO, " DmiGen3RootPortPreset[%d] :", SA_DMI_MAX_LANE)); + for (Index =3D 0; Index < SA_DMI_MAX_LANE; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->DmiGen3RootPortPrese= t[Index])); + } + DEBUG ((DEBUG_INFO, "\n DmiGen3EndPointPreset[%d] :", SA_DMI_MAX_LANE)); + for (Index =3D 0; Index < SA_DMI_MAX_LANE; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->DmiGen3EndPointPrese= t[Index])); + } + DEBUG ((DEBUG_INFO, "\n DmiGen3EndPointHint[%d] :", SA_DMI_MAX_LANE)); + for (Index =3D 0; Index < SA_DMI_MAX_LANE; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->DmiGen3EndPointHint[= Index])); + } + DEBUG ((DEBUG_INFO, "\n DmiGen3RxCtlePeaking[%d] :", SA_DMI_MAX_BUNDLE)); + for (Index =3D 0; Index < SA_DMI_MAX_BUNDLE; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->DmiGen3RxCtlePeaking= [Index])); + } + DEBUG ((DEBUG_INFO, "\n PegGen3RootPortPreset[%d] :", SA_PEG_MAX_LANE)); + for (Index =3D 0; Index < SA_PEG_MAX_LANE; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->PegGen3RootPortPrese= t[Index])); + } + DEBUG ((DEBUG_INFO, "\n PegRootPortHPE[%d] :", SA_PEG_MAX_FUN)); + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->PegRootPortHPE[Index= ])); + } + DEBUG ((DEBUG_INFO, "\n PegGen3EndPointPreset[%d] :", SA_PEG_MAX_LANE)); + for (Index =3D 0; Index < SA_PEG_MAX_LANE; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->PegGen3EndPointPrese= t[Index])); + } + DEBUG ((DEBUG_INFO, "\n PegGen3EndPointHint[%d] :", SA_PEG_MAX_LANE)); + for (Index =3D 0; Index < SA_PEG_MAX_LANE; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->PegGen3EndPointHint[= Index])); + } + DEBUG ((DEBUG_INFO, "\n PegGen3RxCtlePeaking[%d] :", SA_PEG_MAX_BUNDLE)); + for (Index =3D 0; Index < SA_PEG_MAX_BUNDLE; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiPreMemConfig->PegGen3RxCtlePeaking= [Index])); + } + DEBUG ((DEBUG_INFO, "\n PegGen3RxCtleOverride : 0x%x\n", PciePeiPreMemCo= nfig->PegGen3RxCtleOverride)); + DEBUG ((DEBUG_INFO, " DmiDeEmphasis : 0x%x\n", PciePeiPreMemConfig->DmiD= eEmphasis)); + DEBUG ((DEBUG_INFO, "\n Gen3SwEqJitterDwellTime : 0x%x\n", PciePeiPreMem= Config->Gen3SwEqJitterDwellTime)); + DEBUG ((DEBUG_INFO, " Gen3SwEqJitterErrorTarget : 0x%x\n", PciePeiPreMem= Config->Gen3SwEqJitterErrorTarget)); + DEBUG ((DEBUG_INFO, " Gen3SwEqVocDwellTime : 0x%x\n", PciePeiPreMemConfi= g->Gen3SwEqVocDwellTime)); + DEBUG ((DEBUG_INFO, " Gen3SwEqVocErrorTarget : 0x%x\n", PciePeiPreMemCon= fig->Gen3SwEqVocErrorTarget)); + DEBUG ((DEBUG_INFO, " PegDataPtr : %p\n", PciePeiPreMemConfig->PegDataPt= r)); + DEBUG ((DEBUG_INFO, " PegGpioData->GpioSupport : 0x%x\n", PciePeiPreMemC= onfig->PegGpioData.GpioSupport)); + DEBUG ((DEBUG_INFO, " PegGpioData.SaPeg0ResetGpio.GpioPad Group:%d, PadN= umber:%d\n", GpioGetGroupIndexFromGpioPad (PciePeiPreMemConfig->PegGpioData= .SaPeg0ResetGpio.GpioPad), GpioGetPadNumberFromGpioPad (PciePeiPreMemConfig= ->PegGpioData.SaPeg0ResetGpio.GpioPad))); + DEBUG ((DEBUG_INFO, " PegGpioData.SaPeg0ResetGpio.Active : 0x%x\n", Pcie= PeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active)); + DEBUG ((DEBUG_INFO, " PegGpioData.SaPeg3ResetGpio.GpioPad Group:%d, PadN= umber:%d\n", GpioGetGroupIndexFromGpioPad (PciePeiPreMemConfig->PegGpioData= .SaPeg3ResetGpio.GpioPad), GpioGetPadNumberFromGpioPad (PciePeiPreMemConfig= ->PegGpioData.SaPeg3ResetGpio.GpioPad))); + DEBUG ((DEBUG_INFO, " PegGpioData.SaPeg3ResetGpio.Active : 0x%x\n", Pcie= PeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active)); + + DEBUG ((DEBUG_INFO, "------------------------ VTD_CONFIG ---------------= --\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", Vtd->Header.Revision)); + ASSERT (Vtd->Header.Revision =3D=3D VTD_CONFIG_REVISION); + DEBUG ((DEBUG_INFO, " VtdDisable : 0x%x\n", Vtd->VtdDisable)); + DEBUG ((DEBUG_INFO, " X2ApicOptOut : 0x%x\n", Vtd->X2ApicOptOut)); + DEBUG ((DEBUG_INFO, " VtdBaseAddress[%d] :", SA_VTD_ENGINE_NUMBER)); + for (Index =3D 0; Index < SA_VTD_ENGINE_NUMBER; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", Vtd->BaseAddress[Index])); + } + DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, "------------------------ SWITCHABLE_GRAPHICS_CONFIG= -----------------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", SgConfig->Header.Revision)); + ASSERT (SgConfig->Header.Revision =3D=3D SWITCHABLE_GRAPHICS_CONFIG_REVI= SION); + DEBUG ((DEBUG_INFO, " SgConfig->SaRtd3Pcie0Gpio.GpioSupport : 0x%x\n", S= gConfig->SaRtd3Pcie0Gpio.GpioSupport)); + + DEBUG ((DEBUG_INFO, "------------------------ IPU_PREMEM_CONFIG --------= ---------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", IpuPreMemPolicy->Header.Revision= )); + ASSERT (IpuPreMemPolicy->Header.Revision =3D=3D IPU_PREMEM_CONFIG_REVISI= ON); + DEBUG ((DEBUG_INFO, " SaIpuEnable : 0x%x\n", IpuPreMemPolicy->SaIpuEnabl= e)); + DEBUG ((DEBUG_INFO, " SaIpuImrConfiguration : 0x%x\n", IpuPreMemPolicy->= SaIpuImrConfiguration)); + + DEBUG ((DEBUG_INFO, "------------------------ MEMORY_CONFIG ------------= ------------------\n")); + DEBUG ((DEBUG_INFO, " Guid : %g\n", &MemConfig->Header= .GuidHob.Name)); + DEBUG ((DEBUG_INFO, " Revision : %d\n", MemConfig->Heade= r.Revision)); + ASSERT (MemConfig->Header.Revision =3D=3D MEMORY_CONFIG_REVISION); + DEBUG ((DEBUG_INFO, " Size : 0x%x\n", MemConfig->Heade= r.GuidHob.Header.HobLength)); + DEBUG ((DEBUG_INFO, " HobBufferSize : 0x%x\n", MemConfig->HobBu= fferSize)); + DEBUG ((DEBUG_INFO, " EccSupport : 0x%x\n", MemConfig->EccSu= pport)); + DEBUG ((DEBUG_INFO, " DdrFreqLimit : %d\n", MemConfig->DdrFr= eqLimit)); + DEBUG ((DEBUG_INFO, " SpdProfileSelected : 0x%x\n", MemConfig->SpdPr= ofileSelected)); + DEBUG ((DEBUG_INFO, " tCL : 0x%x\n", MemConfig->tCL)); + DEBUG ((DEBUG_INFO, " tRCDtRP : 0x%x\n", MemConfig->tRCDt= RP)); + DEBUG ((DEBUG_INFO, " tRAS : 0x%x\n", MemConfig->tRAS)= ); + DEBUG ((DEBUG_INFO, " tWR : 0x%x\n", MemConfig->tWR)); + DEBUG ((DEBUG_INFO, " tRFC : 0x%x\n", MemConfig->tRFC)= ); + DEBUG ((DEBUG_INFO, " tRRD : 0x%x\n", MemConfig->tRRD)= ); + DEBUG ((DEBUG_INFO, " tWTR : 0x%x\n", MemConfig->tWTR)= ); + DEBUG ((DEBUG_INFO, " tRTP : 0x%x\n", MemConfig->tRTP)= ); + DEBUG ((DEBUG_INFO, " tFAW : 0x%x\n", MemConfig->tFAW)= ); + DEBUG ((DEBUG_INFO, " tCWL : 0x%x\n", MemConfig->tCWL)= ); + DEBUG ((DEBUG_INFO, " tREFI : 0x%x\n", MemConfig->tREFI= )); + DEBUG ((DEBUG_INFO, " NModeSupport : 0x%x\n", MemConfig->NMode= Support)); + DEBUG ((DEBUG_INFO, " VddVoltage : %d\n", MemConfig->VddVolt= age)); + + DEBUG ((DEBUG_INFO, " DisableDimmChannel[%d] :", SA_MC_MAX_CHANNELS)); + for (Index =3D 0; Index < SA_MC_MAX_CHANNELS; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", MemConfig->DisableDimmChannel[Index])); + } + DEBUG ((DEBUG_INFO, "\n RemapEnable : 0x%x\n", MemConfig->Rem= apEnable)); + DEBUG ((DEBUG_INFO, " ScramblerSupport : 0x%x\n", MemConfig->Scram= blerSupport)); + DEBUG ((DEBUG_INFO, " SerialDebug : 0x%x\n", MemConfigNoCrc->= SerialDebugLevel)); + DEBUG ((DEBUG_INFO, " ProbelessTrace : 0x%x\n", MemConfig->Probeles= sTrace)); + DEBUG ((DEBUG_INFO, " ECT : 0x%x\n", MemConfig->ECT)); + DEBUG ((DEBUG_INFO, " SOT : 0x%x\n", MemConfig->SOT)); + DEBUG ((DEBUG_INFO, " ERDMPRTC2D : 0x%x\n", MemConfig->ERDMP= RTC2D)); + DEBUG ((DEBUG_INFO, " RDMPRT : 0x%x\n", MemConfig->RDMPR= T)); + DEBUG ((DEBUG_INFO, " RCVET : 0x%x\n", MemConfig->RCVET= )); + DEBUG ((DEBUG_INFO, " JWRL : 0x%x\n", MemConfig->JWRL)= ); + DEBUG ((DEBUG_INFO, " EWRTC2D : 0x%x\n", MemConfig->EWRTC= 2D)); + DEBUG ((DEBUG_INFO, " ERDTC2D : 0x%x\n", MemConfig->ERDTC= 2D)); + DEBUG ((DEBUG_INFO, " WRTC1D : 0x%x\n", MemConfig->WRTC1= D)); + DEBUG ((DEBUG_INFO, " WRVC1D : 0x%x\n", MemConfig->WRVC1= D)); + DEBUG ((DEBUG_INFO, " RDTC1D : 0x%x\n", MemConfig->RDTC1= D)); + DEBUG ((DEBUG_INFO, " DIMMODTT : 0x%x\n", MemConfig->DIMMO= DTT)); + DEBUG ((DEBUG_INFO, " DIMMRONT : 0x%x\n", MemConfig->DIMMR= ONT)); + DEBUG ((DEBUG_INFO, " WRDSEQT : 0x%x\n", MemConfig->WRDSE= QT)); + DEBUG ((DEBUG_INFO, " WRSRT : 0x%x\n", MemConfig->WRSRT= )); + DEBUG ((DEBUG_INFO, " RDODTT : 0x%x\n", MemConfig->RDODT= T)); + DEBUG ((DEBUG_INFO, " RDEQT : 0x%x\n", MemConfig->RDEQT= )); + DEBUG ((DEBUG_INFO, " RDAPT : 0x%x\n", MemConfig->RDAPT= )); + DEBUG ((DEBUG_INFO, " WRTC2D : 0x%x\n", MemConfig->WRTC2= D)); + DEBUG ((DEBUG_INFO, " RDTC2D : 0x%x\n", MemConfig->RDTC2= D)); + DEBUG ((DEBUG_INFO, " WRVC2D : 0x%x\n", MemConfig->WRVC2= D)); + DEBUG ((DEBUG_INFO, " RDVC2D : 0x%x\n", MemConfig->RDVC2= D)); + DEBUG ((DEBUG_INFO, " CMDVC : 0x%x\n", MemConfig->CMDVC= )); + DEBUG ((DEBUG_INFO, " LCT : 0x%x\n", MemConfig->LCT)); + DEBUG ((DEBUG_INFO, " RTL : 0x%x\n", MemConfig->RTL)); + DEBUG ((DEBUG_INFO, " TAT : 0x%x\n", MemConfig->TAT)); + DEBUG ((DEBUG_INFO, " RMT : 0x%x\n", MemConfig->RMT)); + DEBUG ((DEBUG_INFO, " MEMTST : 0x%x\n", MemConfig->MEMTS= T)); + DEBUG ((DEBUG_INFO, " ALIASCHK : 0x%x\n", MemConfig->ALIAS= CHK)); + DEBUG ((DEBUG_INFO, " RCVENC1D : 0x%x\n", MemConfig->RCVEN= C1D)); + DEBUG ((DEBUG_INFO, " RMC : 0x%x\n", MemConfig->RMC)); + DEBUG ((DEBUG_INFO, " WRDSUDT : 0x%x\n", MemConfig->WRDSU= DT)); + + DEBUG ((DEBUG_INFO, " VddSettleWaitTime : 0x%x\n", MemConfig->VddSe= ttleWaitTime)); + DEBUG ((DEBUG_INFO, " RefClk : 0x%x\n", MemConfig->RefCl= k)); + DEBUG ((DEBUG_INFO, " Ratio : 0x%x\n", MemConfig->Ratio= )); + DEBUG ((DEBUG_INFO, " OddRatioMode : 0x%x\n", MemConfig->OddRa= tioMode)); + DEBUG ((DEBUG_INFO, " MrcTimeMeasure : 0x%x\n", MemConfig->MrcTi= meMeasure)); + DEBUG ((DEBUG_INFO, " MrcFastBoot : 0x%x\n", MemConfig->MrcFa= stBoot)); + DEBUG ((DEBUG_INFO, " DqPinsInterleaved : 0x%x\n", MemConfig->DqPin= sInterleaved)); + DEBUG ((DEBUG_INFO, " MrcSafeConfig : 0x%x\n", MemConfig->MrcSa= feConfig)); + DEBUG ((DEBUG_INFO, " SafeMode : 0x%x\n", MemConfig->SafeM= ode)); + DEBUG ((DEBUG_INFO, " Lp4DqsOscEn : 0x%x\n", MemConfig->Lp4Dq= sOscEn)); + DEBUG ((DEBUG_INFO, " EnBER : 0x%x\n", MemConfig->EnBER= )); + DEBUG ((DEBUG_INFO, " Ddr4MixedUDimm2DpcLimit: 0x%x\n", MemConfig->Ddr4M= ixedUDimm2DpcLimit)); + DEBUG ((DEBUG_INFO, " PowerDownMode : 0x%x\n", MemConfig->Power= DownMode)); + DEBUG ((DEBUG_INFO, " PwdwnIdleCounter : 0x%x\n", MemConfig->Pwdwn= IdleCounter)); + DEBUG ((DEBUG_INFO, " RankInterleave : 0x%x\n", MemConfig->RankI= nterleave)); + DEBUG ((DEBUG_INFO, " EnhancedInterleave : 0x%x\n", MemConfig->Enhan= cedInterleave)); + DEBUG ((DEBUG_INFO, " WeaklockEn : 0x%x\n", MemConfig->Weakl= ockEn)); + DEBUG ((DEBUG_INFO, " EnCmdRate : 0x%x\n", MemConfig->EnCmd= Rate)); + DEBUG ((DEBUG_INFO, " CmdTriStateDis : 0x%x\n", MemConfig->CmdTr= iStateDis)); + DEBUG ((DEBUG_INFO, " BClkFrequency : 0x%x\n", MemConfig->BClkF= requency)); + DEBUG ((DEBUG_INFO, " MemoryTrace : 0x%x\n", MemConfig->Memor= yTrace)); + DEBUG ((DEBUG_INFO, " ChHashEnable : 0x%x\n", MemConfig->ChHas= hEnable)); + DEBUG ((DEBUG_INFO, " ChHashMask : 0x%x\n", MemConfig->ChHas= hMask)); + DEBUG ((DEBUG_INFO, " ChHashInterleaveBit : 0x%x\n", MemConfig->ChHas= hInterleaveBit)); + DEBUG ((DEBUG_INFO, " PerBankRefresh : 0x%x\n", MemConfig->PerBa= nkRefresh)); + DEBUG ((DEBUG_INFO, " EnableExtts : 0x%x\n", MemConfig->Enabl= eExtts)); + DEBUG ((DEBUG_INFO, " EnableCltm : 0x%x\n", MemConfig->Enabl= eCltm)); + DEBUG ((DEBUG_INFO, " EnableOltm : 0x%x\n", MemConfig->Enabl= eOltm)); + DEBUG ((DEBUG_INFO, " EnablePwrDn : 0x%x\n", MemConfig->Enabl= ePwrDn)); + DEBUG ((DEBUG_INFO, " EnablePwrDnLpddr : 0x%x\n", MemConfig->Enabl= ePwrDnLpddr)); + DEBUG ((DEBUG_INFO, " Refresh2X : 0x%x\n", MemConfig->Refre= sh2X)); + DEBUG ((DEBUG_INFO, " DdrThermalSensor : 0x%x\n", MemConfig->DdrTh= ermalSensor)); + DEBUG ((DEBUG_INFO, " LockPTMregs : 0x%x\n", MemConfig->LockP= TMregs)); + DEBUG ((DEBUG_INFO, " UserPowerWeightsEn : 0x%x\n", MemConfig->UserP= owerWeightsEn)); + DEBUG ((DEBUG_INFO, " EnergyScaleFact : 0x%x\n", MemConfig->Energ= yScaleFact)); + DEBUG ((DEBUG_INFO, " RaplPwrFlCh1 : 0x%x\n", MemConfig->RaplP= wrFlCh1)); + DEBUG ((DEBUG_INFO, " RaplPwrFlCh0 : 0x%x\n", MemConfig->RaplP= wrFlCh0)); + DEBUG ((DEBUG_INFO, " RaplLim2Lock : 0x%x\n", MemConfig->RaplL= im2Lock)); + DEBUG ((DEBUG_INFO, " RaplLim2WindX : 0x%x\n", MemConfig->RaplL= im2WindX)); + DEBUG ((DEBUG_INFO, " RaplLim2WindY : 0x%x\n", MemConfig->RaplL= im2WindY)); + DEBUG ((DEBUG_INFO, " RaplLim2Ena : 0x%x\n", MemConfig->RaplL= im2Ena)); + DEBUG ((DEBUG_INFO, " RaplLim2Pwr : 0x%x\n", MemConfig->RaplL= im2Pwr)); + DEBUG ((DEBUG_INFO, " RaplLim1WindX : 0x%x\n", MemConfig->RaplL= im1WindX)); + DEBUG ((DEBUG_INFO, " RaplLim1WindY : 0x%x\n", MemConfig->RaplL= im1WindY)); + DEBUG ((DEBUG_INFO, " RaplLim1Ena : 0x%x\n", MemConfig->RaplL= im1Ena)); + DEBUG ((DEBUG_INFO, " RaplLim1Pwr : 0x%x\n", MemConfig->RaplL= im1Pwr)); + DEBUG ((DEBUG_INFO, " WarmThresholdCh0Dimm0 : 0x%x\n", MemConfig->WarmT= hresholdCh0Dimm0)); + DEBUG ((DEBUG_INFO, " WarmThresholdCh0Dimm1 : 0x%x\n", MemConfig->WarmT= hresholdCh0Dimm1)); + DEBUG ((DEBUG_INFO, " WarmThresholdCh1Dimm0 : 0x%x\n", MemConfig->WarmT= hresholdCh1Dimm0)); + DEBUG ((DEBUG_INFO, " WarmThresholdCh1Dimm1 : 0x%x\n", MemConfig->WarmT= hresholdCh1Dimm1)); + DEBUG ((DEBUG_INFO, " HotThresholdCh0Dimm0 : 0x%x\n", MemConfig->HotTh= resholdCh0Dimm0)); + DEBUG ((DEBUG_INFO, " HotThresholdCh0Dimm1 : 0x%x\n", MemConfig->HotTh= resholdCh0Dimm1)); + DEBUG ((DEBUG_INFO, " HotThresholdCh1Dimm0 : 0x%x\n", MemConfig->HotTh= resholdCh1Dimm0)); + DEBUG ((DEBUG_INFO, " HotThresholdCh1Dimm1 : 0x%x\n", MemConfig->HotTh= resholdCh1Dimm1)); + DEBUG ((DEBUG_INFO, " WarmBudgetCh0Dimm0 : 0x%x\n", MemConfig->WarmB= udgetCh0Dimm0)); + DEBUG ((DEBUG_INFO, " WarmBudgetCh0Dimm1 : 0x%x\n", MemConfig->WarmB= udgetCh0Dimm1)); + DEBUG ((DEBUG_INFO, " WarmBudgetCh1Dimm0 : 0x%x\n", MemConfig->WarmB= udgetCh1Dimm0)); + DEBUG ((DEBUG_INFO, " WarmBudgetCh1Dimm1 : 0x%x\n", MemConfig->WarmB= udgetCh1Dimm1)); + DEBUG ((DEBUG_INFO, " HotBudgetCh0Dimm0 : 0x%x\n", MemConfig->HotBu= dgetCh0Dimm0)); + DEBUG ((DEBUG_INFO, " HotBudgetCh0Dimm1 : 0x%x\n", MemConfig->HotBu= dgetCh0Dimm1)); + DEBUG ((DEBUG_INFO, " HotBudgetCh1Dimm0 : 0x%x\n", MemConfig->HotBu= dgetCh1Dimm0)); + DEBUG ((DEBUG_INFO, " HotBudgetCh1Dimm1 : 0x%x\n", MemConfig->HotBu= dgetCh1Dimm1)); + DEBUG ((DEBUG_INFO, " IdleEnergyCh0Dimm0 : 0x%x\n", MemConfig->IdleE= nergyCh0Dimm0)); + DEBUG ((DEBUG_INFO, " IdleEnergyCh0Dimm1 : 0x%x\n", MemConfig->IdleE= nergyCh0Dimm1)); + DEBUG ((DEBUG_INFO, " IdleEnergyCh1Dimm0 : 0x%x\n", MemConfig->IdleE= nergyCh1Dimm0)); + DEBUG ((DEBUG_INFO, " IdleEnergyCh1Dimm1 : 0x%x\n", MemConfig->IdleE= nergyCh1Dimm1)); + DEBUG ((DEBUG_INFO, " PdEnergyCh0Dimm0 : 0x%x\n", MemConfig->PdEne= rgyCh0Dimm0)); + DEBUG ((DEBUG_INFO, " PdEnergyCh0Dimm1 : 0x%x\n", MemConfig->PdEne= rgyCh0Dimm1)); + DEBUG ((DEBUG_INFO, " PdEnergyCh1Dimm0 : 0x%x\n", MemConfig->PdEne= rgyCh1Dimm0)); + DEBUG ((DEBUG_INFO, " PdEnergyCh1Dimm1 : 0x%x\n", MemConfig->PdEne= rgyCh1Dimm1)); + DEBUG ((DEBUG_INFO, " ActEnergyCh0Dimm0 : 0x%x\n", MemConfig->ActEn= ergyCh0Dimm0)); + DEBUG ((DEBUG_INFO, " ActEnergyCh0Dimm1 : 0x%x\n", MemConfig->ActEn= ergyCh0Dimm1)); + DEBUG ((DEBUG_INFO, " ActEnergyCh1Dimm0 : 0x%x\n", MemConfig->ActEn= ergyCh1Dimm0)); + DEBUG ((DEBUG_INFO, " ActEnergyCh1Dimm1 : 0x%x\n", MemConfig->ActEn= ergyCh1Dimm1)); + DEBUG ((DEBUG_INFO, " RdEnergyCh0Dimm0 : 0x%x\n", MemConfig->RdEne= rgyCh0Dimm0)); + DEBUG ((DEBUG_INFO, " RdEnergyCh0Dimm1 : 0x%x\n", MemConfig->RdEne= rgyCh0Dimm1)); + DEBUG ((DEBUG_INFO, " RdEnergyCh1Dimm0 : 0x%x\n", MemConfig->RdEne= rgyCh1Dimm0)); + DEBUG ((DEBUG_INFO, " RdEnergyCh1Dimm1 : 0x%x\n", MemConfig->RdEne= rgyCh1Dimm1)); + DEBUG ((DEBUG_INFO, " WrEnergyCh0Dimm0 : 0x%x\n", MemConfig->WrEne= rgyCh0Dimm0)); + DEBUG ((DEBUG_INFO, " WrEnergyCh0Dimm1 : 0x%x\n", MemConfig->WrEne= rgyCh0Dimm1)); + DEBUG ((DEBUG_INFO, " WrEnergyCh1Dimm0 : 0x%x\n", MemConfig->WrEne= rgyCh1Dimm0)); + DEBUG ((DEBUG_INFO, " WrEnergyCh1Dimm1 : 0x%x\n", MemConfig->WrEne= rgyCh1Dimm1)); + DEBUG ((DEBUG_INFO, " SrefCfgEna : 0x%x\n", MemConfig->SrefC= fgEna)); + DEBUG ((DEBUG_INFO, " SrefCfgIdleTmr : 0x%x\n", MemConfig->SrefC= fgIdleTmr)); + DEBUG ((DEBUG_INFO, " ThrtCkeMinDefeat : 0x%x\n", MemConfig->ThrtC= keMinDefeat)); + DEBUG ((DEBUG_INFO, " ThrtCkeMinTmr : 0x%x\n", MemConfig->ThrtC= keMinTmr)); + DEBUG ((DEBUG_INFO, " ThrtCkeMinDefeatLpddr : 0x%x\n", MemConfig->ThrtC= keMinDefeatLpddr)); + DEBUG ((DEBUG_INFO, " ThrtCkeMinTmrLpddr : 0x%x\n", MemConfig->ThrtC= keMinTmrLpddr)); + DEBUG ((DEBUG_INFO, " AutoSelfRefreshSupport : 0x%x\n", MemConfig->AutoS= elfRefreshSupport)); + DEBUG ((DEBUG_INFO, " ExtTemperatureSupport : 0x%x\n", MemConfig->ExtTe= mperatureSupport)); + DEBUG ((DEBUG_INFO, " MaxRttWr : 0x%x\n", MemConfig->MaxRt= tWr)); + DEBUG ((DEBUG_INFO, " MobilePlatform : 0x%x\n", MemConfig->Mobil= ePlatform)); + DEBUG ((DEBUG_INFO, " Force1Dpc : 0x%x\n", MemConfig->Force= 1Dpc)); + + + DEBUG ((DEBUG_INFO, " ForceSingleRank : 0x%x\n", MemConfig->Force= SingleRank)); + DEBUG ((DEBUG_INFO, " PciIndex : 0x%x\n", MemConfig->PciIn= dex)); + DEBUG ((DEBUG_INFO, " PciData : 0x%x\n", MemConfig->PciDa= ta)); + DEBUG ((DEBUG_INFO, " CkeRankMapping : 0x%x\n", MemConfig->CkeRa= nkMapping)); + DEBUG ((DEBUG_INFO, " RhPrevention : 0x%x\n", MemConfig->RhPre= vention)); + DEBUG ((DEBUG_INFO, " RhSolution : 0x%x\n", MemConfig->RhSol= ution)); + DEBUG ((DEBUG_INFO, " RhActProbability : 0x%x\n", MemConfig->RhAct= Probability)); + DEBUG ((DEBUG_INFO, " VttTermination : 0x%x\n", MemConfig->VttTe= rmination)); + DEBUG ((DEBUG_INFO, " VttCompForVsshi : 0x%x\n", MemConfig->VttCo= mpForVsshi)); + DEBUG ((DEBUG_INFO, " BerEnable : 0x%x\n", MemConfig->BerEn= able)); + for (Index =3D 0; Index < 4; Index++) { + DEBUG ((DEBUG_INFO, " BerAddress[%d] : 0x%x\n",Index , MemConfig-= >BerAddress[Index])); + } + DEBUG ((DEBUG_INFO, " CleanMemory : 0x%x\n", MemConfigNoCrc->= CleanMemory)); + DEBUG ((DEBUG_INFO, " MemTestOnWarmBoot : 0x%x\n", MemConfigNoCrc->= MemTestOnWarmBoot)); + DEBUG ((DEBUG_INFO, " ExitOnFailure : 0x%x\n", MemConfig->ExitO= nFailure)); + DEBUG ((DEBUG_INFO, " Vc1ReadMeter : 0x%x\n", MemConfig->Vc1Re= adMeter)); + DEBUG ((DEBUG_INFO, " SaGv : 0x%x\n", MemConfig->SaGv)= ); + DEBUG ((DEBUG_INFO, " FreqSaGvLow : 0x%x\n FreqSaGvMid = : 0x%x\n", + MemConfig->FreqSaGvLow, MemConfig->FreqSaGvMid)); + DEBUG ((DEBUG_INFO, " StrongWkLeaker : 0x%x\n", MemConfig->Stron= gWkLeaker)); + DEBUG ((DEBUG_INFO, " CaVrefConfig : 0x%x\n", MemConfig->CaVre= fConfig)); + DEBUG ((DEBUG_INFO, " SimicsFlag : 0x%x\n", MemConfig->Simic= sFlag)); + DEBUG ((DEBUG_INFO, " PlatformMemorySize : 0x%x\n", MemConfigNoCrc->= PlatformMemorySize)); + DEBUG ((DEBUG_INFO, " SmramMask : 0x%x\n", MemConfig->Smram= Mask)); + DEBUG ((DEBUG_INFO, " DllBwEn0: %d\n DllBwEn1: %d\n DllBwEn2: %d\n DllBw= En3: %d\n", + MemConfig->DllBwEn0, MemConfig->DllBwEn1, MemConfig->DllBwEn2, M= emConfig->DllBwEn3)); + DEBUG ((DEBUG_INFO, " RetrainOnFastFail: %d\n ForceOltmOrRefresh2x: %d\n= ", + MemConfig->RetrainOnFastFail, MemConfig->ForceOltmOrRefresh2x)); + DEBUG ((DEBUG_INFO, " RmtPerTask: %u\n TrainTrace: %u\n", MemConfig->Rmt= PerTask, MemConfig->TrainTrace)); + DEBUG ((DEBUG_INFO, " tRd2RdSG : 0x%x\n tRd2RdDG = : 0x%x\n", MemConfig->tRd2RdSG, MemConfig->tRd2RdDG)); + DEBUG ((DEBUG_INFO, " tRd2RdDR : 0x%x\n tRd2RdDD = : 0x%x\n", MemConfig->tRd2RdDR, MemConfig->tRd2RdDD)); + DEBUG ((DEBUG_INFO, " tRd2WrSG : 0x%x\n tRd2WrDG = : 0x%x\n", MemConfig->tRd2WrSG, MemConfig->tRd2WrDG)); + DEBUG ((DEBUG_INFO, " tRd2WrDR : 0x%x\n tRd2WrDD = : 0x%x\n", MemConfig->tRd2WrDR, MemConfig->tRd2WrDD)); + DEBUG ((DEBUG_INFO, " tWr2RdSG : 0x%x\n tWr2RdDG = : 0x%x\n", MemConfig->tWr2RdSG, MemConfig->tWr2RdDG)); + DEBUG ((DEBUG_INFO, " tWr2RdDR : 0x%x\n tWr2RdDD = : 0x%x\n", MemConfig->tWr2RdDR, MemConfig->tWr2RdDD)); + DEBUG ((DEBUG_INFO, " tWr2WrSG : 0x%x\n tWr2WrDG = : 0x%x\n", MemConfig->tWr2WrSG, MemConfig->tWr2WrDG)); + DEBUG ((DEBUG_INFO, " tWr2WrDR : 0x%x\n tWr2WrDD = : 0x%x\n", MemConfig->tWr2WrDR, MemConfig->tWr2WrDD)); + DEBUG ((DEBUG_INFO, "------------------------ OVERCLOCKING_CONFIG ------= -----------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", OcPreMemConfig->Header.Revision)= ); + ASSERT (OcPreMemConfig->Header.Revision =3D=3D SA_OVERCLOCKING_CONFIG_RE= VISION); + DEBUG ((DEBUG_INFO, " OcSupport : 0x%x\n", OcPreMemConfig->OcSupport)); + DEBUG ((DEBUG_INFO, " GtMaxOcRatio : 0x%x\n", OcPreMemConfig->GtMaxOcRat= io)); + DEBUG ((DEBUG_INFO, " GtVoltageMode : 0x%x\n", OcPreMemConfig->GtVoltage= Mode)); + DEBUG ((DEBUG_INFO, " GtVoltageOffset : 0x%x\n", OcPreMemConfig->GtVolta= geOffset)); + DEBUG ((DEBUG_INFO, " GtVoltageOverride : 0x%x\n", OcPreMemConfig->GtVol= tageOverride)); + DEBUG ((DEBUG_INFO, " GtExtraTurboVoltage : 0x%x\n", OcPreMemConfig->GtE= xtraTurboVoltage)); + DEBUG ((DEBUG_INFO, " SaVoltageOffset : 0x%x\n", OcPreMemConfig->SaVolta= geOffset)); + DEBUG ((DEBUG_INFO, " GtusMaxOcRatio : 0x%x\n", OcPreMemConfig->GtusMaxO= cRatio)); + DEBUG ((DEBUG_INFO, " GtusVoltageMode : 0x%x\n", OcPreMemConfig->GtusVol= tageMode)); + DEBUG ((DEBUG_INFO, " GtusVoltageOffset : 0x%x\n", OcPreMemConfig->GtusV= oltageOffset)); + DEBUG ((DEBUG_INFO, " GtusVoltageOverride : 0x%x\n", OcPreMemConfig->Gtu= sVoltageOverride)); + DEBUG ((DEBUG_INFO, " GtusExtraTurboVoltage : 0x%x\n", OcPreMemConfig->G= tusExtraTurboVoltage)); + for (Index =3D 0; Index < SA_MC_MAX_CHANNELS; Index++) { + DEBUG ((DEBUG_INFO, " DqByteMapCh%d : ", Index)); + for (Index2 =3D 0; Index2 < SA_MRC_ITERATION_MAX; Index2++) { + DEBUG ((DEBUG_INFO, "0x%02x ", MemConfigNoCrc->DqByteMap->DqByteMap[= Index][Index2][0])); + DEBUG ((DEBUG_INFO, "0x%02x ", MemConfigNoCrc->DqByteMap->DqByteMap[= Index][Index2][1])); + } + DEBUG ((DEBUG_INFO, "\n")); + } + for (Index =3D 0; Index < SA_MC_MAX_CHANNELS; Index++) { + DEBUG ((DEBUG_INFO, " DqsMapCpu2DramCh%d : ", Index)); + for (Index2 =3D 0; Index2 < SA_MC_MAX_BYTES_NO_ECC; Index2++) { + DEBUG ((DEBUG_INFO, "%d ", MemConfigNoCrc->DqsMap->DqsMapCpu2Dram[In= dex][Index2])); + } + DEBUG ((DEBUG_INFO, "\n")); + } + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI PreMem) P= rint END -----------------\n")); + DEBUG_CODE_END (); + return; +} + +/** + This function prints the PEI phase policy. + + @param[in] SiPolicyPpi - Instance of SI_POLICY_PPI +**/ +VOID +EFIAPI +SaPrintPolicyPpi ( + IN SI_POLICY_PPI *SiPolicyPpi + ) +{ + DEBUG_CODE_BEGIN (); + INTN Index; + EFI_STATUS Status; + GRAPHICS_PEI_CONFIG *GtConfig; + PCIE_PEI_CONFIG *PciePeiConfig; + SA_MISC_PEI_CONFIG *MiscPeiConfig; + // + // Get requisite IP Config Blocks which needs to be used here + // + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid= , (VOID *) &GtConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid, = (VOID *) &PciePeiConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid, = (VOID *) &MiscPeiConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print BE= GIN -----------------\n")); + DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", SiPolicyPpi->TableHeader.Header= .Revision)); + ASSERT (SiPolicyPpi->TableHeader.Header.Revision =3D=3D SI_POLICY_REVISI= ON); + + DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_PEI_CONFIG ------= -----------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", MiscPeiConfig->Header.Revision)); + ASSERT (MiscPeiConfig->Header.Revision =3D=3D SA_MISC_PEI_CONFIG_REVISIO= N); + DEBUG ((DEBUG_INFO, " ChapDeviceEnable : 0x%x\n", MiscPeiConfig->ChapDev= iceEnable)); + DEBUG ((DEBUG_INFO, " Device4Enable : 0x%x\n", MiscPeiConfig->Device4Ena= ble)); + DEBUG ((DEBUG_INFO, " CridEnable : 0x%x\n", MiscPeiConfig->CridEnable)); + DEBUG ((DEBUG_INFO, " SkipPamLock : 0x%x\n", MiscPeiConfig->SkipPamLock)= ); + DEBUG ((DEBUG_INFO, " EdramTestMode : 0x%x\n", MiscPeiConfig->EdramTestM= ode)); + + DEBUG ((DEBUG_INFO, "------------------------ GRAPHICS_PEI_CONFIG ------= -----------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", GtConfig->Header.Revision)); + ASSERT (GtConfig->Header.Revision =3D=3D GRAPHICS_PEI_CONFIG_REVISION); + DEBUG ((DEBUG_INFO, " RenderStandby : 0x%x\n", GtConfig->RenderStandby)); + DEBUG ((DEBUG_INFO, " PmSupport : 0x%x\n", GtConfig->PmSupport)); + DEBUG ((DEBUG_INFO, " PavpEnable : 0x%x\n", GtConfig->PavpEnable)); + DEBUG ((DEBUG_INFO, " CdClock : 0x%x\n", GtConfig->CdClock)); + DEBUG ((DEBUG_INFO, " PeiGraphicsPeimInit : 0x%x\n", GtConfig->PeiGraphi= csPeimInit)); + DEBUG ((DEBUG_INFO, " LogoPtr : 0x%x\n", GtConfig->LogoPtr)); + DEBUG ((DEBUG_INFO, " LogoSize : 0x%x\n", GtConfig->LogoSize)); + DEBUG ((DEBUG_INFO, " BltBufferAddress : 0x%x\n", GtConfig->BltBufferAdd= ress)); + DEBUG ((DEBUG_INFO, " BltBufferSize : 0x%x\n", GtConfig->BltBufferSize)); + DEBUG ((DEBUG_INFO, " GraphicsConfigPtr : 0x%x\n", GtConfig->GraphicsCon= figPtr)); + DEBUG ((DEBUG_INFO, " CdynmaxClampEnable : 0x%x\n", GtConfig->CdynmaxCla= mpEnable)); + DEBUG ((DEBUG_INFO, " GtFreqMax : 0x%x\n", GtConfig->GtFreqMax)); + DEBUG ((DEBUG_INFO, " DisableTurboGt : 0x%x\n", GtConfig->DisableTurboGt= )); + DEBUG ((DEBUG_INFO, " DdiPortEdp : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortEdp)); + DEBUG ((DEBUG_INFO, " DdiPortBHpd : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortBHpd)); + DEBUG ((DEBUG_INFO, " DdiPortCHpd : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortCHpd)); + DEBUG ((DEBUG_INFO, " DdiPortDHpd : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortDHpd)); + DEBUG ((DEBUG_INFO, " DdiPortFHpd : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortFHpd)); + DEBUG ((DEBUG_INFO, " DdiPortBDdc : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortBDdc)); + DEBUG ((DEBUG_INFO, " DdiPortCDdc : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortCDdc)); + DEBUG ((DEBUG_INFO, " DdiPortDDdc : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortDDdc)); + DEBUG ((DEBUG_INFO, " DdiPortFDdc : 0x%x\n", GtConfig->DdiConfiguration.= DdiPortFDdc)); + DEBUG ((DEBUG_INFO, " SkipS3CdClockInit : 0x%x\n", GtConfig->SkipS3CdClo= ckInit)); + + DEBUG ((DEBUG_INFO, "------------------------ PCIE_PEI_CONFIG ----------= -------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", PciePeiConfig->Header.Revision)); + ASSERT (PciePeiConfig->Header.Revision =3D=3D SA_PCIE_PEI_CONFIG_REVISIO= N); + DEBUG ((DEBUG_INFO, " DmiExtSync : 0x%x\n", PciePeiConfig->DmiExtSync)); + DEBUG ((DEBUG_INFO, " DmiIot : 0x%x\n", PciePeiConfig->DmiIot)); + DEBUG ((DEBUG_INFO, " DmiAspm : 0x%x\n", PciePeiConfig->DmiAspm)); + DEBUG ((DEBUG_INFO, "\n PegSlotPowerLimitValue[%d] :", SA_PEG_MAX_FUN)); + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiConfig->PegSlotPowerLimitValue[Ind= ex])); + } + DEBUG ((DEBUG_INFO, "\n PegSlotPowerLimitScale[%d] :", SA_PEG_MAX_FUN)); + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiConfig->PegSlotPowerLimitScale[Ind= ex])); + } + DEBUG ((DEBUG_INFO, "\n PegPhysicalSlotNumber[%d] :", SA_PEG_MAX_FUN)); + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiConfig->PegPhysicalSlotNumber[Inde= x])); + } + DEBUG ((DEBUG_INFO, "\n PegDeEmphasis[%d] :", SA_PEG_MAX_FUN)); + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiConfig->PegDeEmphasis[Index])); + } + DEBUG ((DEBUG_INFO, "\n PegMaxPayload[%d] :", SA_PEG_MAX_FUN)); + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + DEBUG ((DEBUG_INFO, " 0x%x", PciePeiConfig->PegMaxPayload[Index])); + } + DEBUG ((DEBUG_INFO, "\n")); + + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (PEI) Print EN= D -----------------\n")); + DEBUG_CODE_END (); + return; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/Ia32/MrcOemPlatform.S b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAg= ent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.S new file mode 100644 index 0000000000..97b58c460f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /Ia32/MrcOemPlatform.S @@ -0,0 +1,114 @@ +## @file +// +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +//------------------------------------------------------------------------= ----- +// +// Section: SaMmioRead64 +// +// Description: Read 64 bits from the Memory Mapped I/O space. +// Use MMX instruction for atomic access, because some MC registers have = side effect. +// +// @param[in] Address - Memory mapped I/O address. +// +//------------------------------------------------------------------------= ----- +//UINT64 +//SaMmioRead64 ( +// IN UINTN Address +// ) + +ASM_GLOBAL ASM_PFX(SaMmioRead64) +ASM_PFX(SaMmioRead64): + subl $16, %esp + movq %mm0, (%esp) //Save mm0 on stack + movl 20(%esp), %edx //edx =3D Address + movq (%edx), %mm0 //mm0 =3D [Address] + movq %mm0, 8(%esp) //Store mm0 on Stack + movq (%esp), %mm0 //Restore mm0 + emms + movl 8(%esp), %eax //eax =3D [Address][31:0] + movl 12(%esp), %edx //edx =3D [Address][64:32] + addl $16, %esp + ret + +//------------------------------------------------------------------------= ----- +// +// Section: SaMmioWrite64 +// +// Description: Write 64 bits to the Memory Mapped I/O space. +// Use MMX instruction for atomic access, because some MC registers have = side effect. +// +// @param[in] Address - Memory mapped I/O address. +// @param[in] Value - The value to write. +// +//------------------------------------------------------------------------= ----- + +//UINT64 +//SaMmioWrite64 ( +// IN UINTN Address, +// IN UINT64 Value +// ) + +ASM_GLOBAL ASM_PFX(SaMmioWrite64) +ASM_PFX(SaMmioWrite64): + subl $8, %esp + movq %mm0, (%esp) //Save mm0 on Stack + movl 12(%esp), %edx //edx =3D Address + movq 16(%esp), %mm0 //mm0 =3D Value + movq %mm0, (%edx) //[Address] =3D Value + movq (%esp), %mm0 //Restore mm0 + emms + movl 16(%esp), %eax //eax =3D Value[31:0] + movl 20(%esp), %edx //edx =3D Value[64:32] + addl $8, %esp + ret + +//------------------------------------------------------------------------= ----- +// Intel Silicon View Technology check point interface based on IO port r= eading +// +// @param CheckPoint Check point AH value. +// AH =3D 0x10: End of MRC State +// AH =3D 0x20: End of DXE State +// AH =3D 0x30: Ready to boot before INT-19h or= UEFI boot +// AH =3D 0x40: After OS booting, need a timer = SMI trigger to implement (TBD); +// +// @param PortReading IO port reading address used for breakpoints +//------------------------------------------------------------------------= ----- + +//VOID +//EFIAPI +//IsvtCheckPoint ( +// IN UINT32 CheckPoint, +// IN UINT32 PortReading +// ) + +ASM_GLOBAL ASM_PFX(IsvtCheckPoint) +ASM_PFX(IsvtCheckPoint): + pushl %eax + pushl %edx + + // Stack layout at this point: + //------------- + // PortReading ESP + 16 + //------------- + // CheckPoint ESP + 12 + //------------- + // EIP ESP + 8 + //------------- + // EAX ESP + 4 + //------------- + // EDX <-- ESP + //------------- + + mov 12(%esp), %ah // CheckPoint + mov 16(%esp), %dx // PortReading + in %dx, %al // signal debugger + + popl %edx + popl %eax + ret + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/Ia32/MrcOemPlatform.asm b/Silicon/Intel/CoffeelakeSiliconPkg/System= Agent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.asm new file mode 100644 index 0000000000..288fe7a2fe --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /Ia32/MrcOemPlatform.asm @@ -0,0 +1,126 @@ +; @file +; This file provides assembly 64-bit atomic reads/writes required for mem= ory initialization. +; +; Copyright (c) 2019 Intel Corporation. All rights reserved.
+; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; + +.686p +.xmm +.model small, c + +.CODE + +;-------------------------------------------------------------------------= ---- +; +; Section: SaMmioRead64 +; +; Description: Read 64 bits from the Memory Mapped I/O space. +; Use MMX instruction for atomic access, because some MC registers have s= ide effect. +; +; @param[in] Address - Memory mapped I/O address. +; +;-------------------------------------------------------------------------= ---- + +;UINT64 +;SaMmioRead64 ( +; IN UINTN Address +; ) + +SaMmioRead64 PROC NEAR PUBLIC + sub esp, 16 + movq [esp], mm0 ;Save mm0 on stack + mov edx, [esp + 20] ;edx =3D Address + movq mm0, [edx] ;mm0 =3D [Address] + movq [esp + 8], mm0 ;Store mm0 on Stack + movq mm0, [esp] ;Restore mm0 + emms + mov eax, [esp + 8] ;eax =3D [Address][31:0] + mov edx, [esp + 12] ;edx =3D [Address][64:32] + add esp, 16 + ret +SaMmioRead64 ENDP + +;-------------------------------------------------------------------------= ---- +; +; Section: SaMmioWrite64 +; +; Description: Write 64 bits to the Memory Mapped I/O space. +; Use MMX instruction for atomic access, because some MC registers have s= ide effect. +; +; @param[in] Address - Memory mapped I/O address. +; @param[in] Value - The value to write. +; +;-------------------------------------------------------------------------= ---- + +;UINT64 +;SaMmioWrite64 ( +; IN UINTN Address, +; IN UINT64 Value +; ) + +SaMmioWrite64 PROC NEAR PUBLIC + sub esp, 8 + movq [esp], mm0 ;Save mm0 on Stack + mov edx, [esp + 12] ;edx =3D Address + movq mm0, [esp + 16] ;mm0 =3D Value + movq [edx], mm0 ;[Address] =3D Value + movq mm0, [esp] ;Restore mm0 + emms + mov eax, [esp + 16] ;eax =3D Value[31:0] + mov edx, [esp + 20] ;edx =3D Value[64:32] + add esp, 8 + ret +SaMmioWrite64 ENDP + + +;-------------------------------------------------------------------------= ---- +; Intel Silicon View Technology check point interface based on IO port re= ading +; +; @param CheckPoint Check point AH value. +; AH =3D 0x10: End of MRC State +; AH =3D 0x20: End of DXE State +; AH =3D 0x30: Ready to boot before INT-19h or = UEFI boot +; AH =3D 0x40: After OS booting, need a timer S= MI trigger to implement (TBD); +; +; @param PortReading IO port reading address used for breakpoints +;-------------------------------------------------------------------------= ---- + +;VOID +;EFIAPI +;IsvtCheckPoint ( +; IN UINT32 CheckPoint, +; IN UINT32 PortReading +; ) + +IsvtCheckPoint PROC NEAR PUBLIC + push eax + push edx + + ; Stack layout at this point: + ;------------- + ; PortReading ESP + 16 + ;------------- + ; CheckPoint ESP + 12 + ;------------- + ; EIP ESP + 8 + ;------------- + ; EAX ESP + 4 + ;------------- + ; EDX <-- ESP + ;------------- + + mov ah, BYTE PTR [esp + 12] ; CheckPoint + mov dx, WORD PTR [esp + 16] ; PortReading + in al, dx ; signal debugger + + pop edx + pop eax + ret +IsvtCheckPoint ENDP + + +end + + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPo= licyLib/Ia32/MrcOemPlatform.nasm b/Silicon/Intel/CoffeelakeSiliconPkg/Syste= mAgent/Library/PeiSaPolicyLib/Ia32/MrcOemPlatform.nasm new file mode 100644 index 0000000000..da7ef004ad --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib= /Ia32/MrcOemPlatform.nasm @@ -0,0 +1,118 @@ +; @file +; This file provides assembly 64-bit atomic reads/writes required for mem= ory initialization. +; +; Copyright (c) 2019 Intel Corporation. All rights reserved.
+; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; + +SECTION .text + +;-------------------------------------------------------------------------= ---- +; +; Section: SaMmioRead64 +; +; Description: Read 64 bits from the Memory Mapped I/O space. +; Use MMX instruction for atomic access, because some MC registers have s= ide effect. +; +; @param[in] Address - Memory mapped I/O address. +; +;-------------------------------------------------------------------------= ---- + +;UINT64 +;SaMmioRead64 ( +; IN UINTN Address +; ) + +global ASM_PFX(SaMmioRead64) +ASM_PFX(SaMmioRead64): + sub esp, 16 + movq [esp], mm0 ;Save mm0 on stack + mov edx, [esp + 20] ;edx =3D Address + movq mm0, [edx] ;mm0 =3D [Address] + movq [esp + 8], mm0 ;Store mm0 on Stack + movq mm0, [esp] ;Restore mm0 + emms + mov eax, [esp + 8] ;eax =3D [Address][31:0] + mov edx, [esp + 12] ;edx =3D [Address][64:32] + add esp, 16 + ret + +;-------------------------------------------------------------------------= ---- +; +; Section: SaMmioWrite64 +; +; Description: Write 64 bits to the Memory Mapped I/O space. +; Use MMX instruction for atomic access, because some MC registers have s= ide effect. +; +; @param[in] Address - Memory mapped I/O address. +; @param[in] Value - The value to write. +; +;-------------------------------------------------------------------------= ---- + +;UINT64 +;SaMmioWrite64 ( +; IN UINTN Address, +; IN UINT64 Value +; ) + +global ASM_PFX(SaMmioWrite64) +ASM_PFX(SaMmioWrite64): + sub esp, 8 + movq [esp], mm0 ;Save mm0 on Stack + mov edx, [esp + 12] ;edx =3D Address + movq mm0, [esp + 16] ;mm0 =3D Value + movq [edx], mm0 ;[Address] =3D Value + movq mm0, [esp] ;Restore mm0 + emms + mov eax, [esp + 16] ;eax =3D Value[31:0] + mov edx, [esp + 20] ;edx =3D Value[64:32] + add esp, 8 + ret + +;-------------------------------------------------------------------------= ---- +; Intel Silicon View Technology check point interface based on IO port re= ading +; +; @param CheckPoint Check point AH value. +; AH =3D 0x10: End of MRC State +; AH =3D 0x20: End of DXE State +; AH =3D 0x30: Ready to boot before INT-19h or = UEFI boot +; AH =3D 0x40: After OS booting, need a timer S= MI trigger to implement (TBD); +; +; @param PortReading IO port reading address used for breakpoints +;-------------------------------------------------------------------------= ---- + +;VOID +;EFIAPI +;IsvtCheckPoint ( +; IN UINT32 CheckPoint, +; IN UINT32 PortReading +; ) + +global ASM_PFX(IsvtCheckPoint) +ASM_PFX(IsvtCheckPoint): + push eax + push edx + + ; Stack layout at this point: + ;------------- + ; PortReading ESP + 16 + ;------------- + ; CheckPoint ESP + 12 + ;------------- + ; EIP ESP + 8 + ;------------- + ; EAX ESP + 4 + ;------------- + ; EDX <-- ESP + ;------------- + + mov ah, BYTE [esp + 12] ; CheckPoint + mov dx, WORD [esp + 16] ; PortReading + in al, dx ; signal debugger + + pop edx + pop eax + ret + + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45902): https://edk2.groups.io/g/devel/message/45902 Mute This Topic: https://groups.io/mt/32918195/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45907+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45907+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001030; cv=none; d=zoho.com; s=zohoarc; b=ZeU4nBVuiBYhsQ2I6PjjfxbbLzlnqlj1c6E5EovUWNlSEfSP1IwbtSE5GHaR/gudochI3YCJ4NYZfzc1wmM7seHadRCoSeYDXp7yPDngexTOJyP7ghcjcpw0+Y+X9U4VdEo7jsR/SP0jQvInGxtKZsep6bQxGMvo6UTpUFBtrpE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001030; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=iX2ne400o69X4a10aJ5MCmf3R4FXgdKde3VoXZPh430=; b=g1JFR6lwJQKa2lvePd9TSmleaP+309+jw7ROB11XFjGjFDftJntrvTAU9bhrOPRX3cYHUdJaHUmawyzCpEvDhx6SdwtMix0PS3daY9bM1AdPfL4UJdrDD/3aRGrInWPXWUpmUJPAqCPDo4p4vXMtBXCQpkdcdK4BX8lCDNOXuYc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45907+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001030595278.32836497518304; Fri, 16 Aug 2019 17:17:10 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:09 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319315" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:55 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 26/37] CoffeelakeSiliconPkg/Pch: Add modules Date: Fri, 16 Aug 2019 17:15:52 -0700 Message-Id: <20190817001603.30632-27-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001030; bh=e8qkcggbdRHky7LrFkx4Kc+Qwh31v1p3Xy5ycCO0/Tk=; h=Cc:Date:From:Reply-To:Subject:To; b=BTXVXEEPc+d8cx5mH4MdllDAeJK0m0PVFNW8yNf/a/WOBXfN+wvlxiT1/EZ53mMX21V O7BNekrrKoAc0DtcuanQa12PUCiwuHe5AsP3FBd7CKx/AExQeFvt0Id9asdqiORWPjCx3 mXa4RCatzkq9brepzBfuhhkpvyzHRXM2dKE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 * PchInitDxeCnl - Generic DXE PCH initialization. * PchInitDxeFspCnl - Generic DXE PCH FSP initialization. * PchInitSmm - Generic SMM PCH initialization. * SmmControl - Produces an instance of EFI_SMM_CONTROL2_PROTOCOL. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeCnl.inf = | 99 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeFspCnl.inf = | 77 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.inf = | 101 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/SmmControl.in= f | 54 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpiSmm.inf = | 45 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInit.h = | 223 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h = | 187 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/SmmControlDri= ver.h | 132 +++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchAcpi.c = | 451 ++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchCnviAcpi.c = | 33 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchHdaAcpi.c = | 323 ++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInit.c = | 554 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxe.c = | 382 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitFsp.c = | 85 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSata.c = | 89 ++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSerialIo.c = | 57 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSerialIoDxe.c = | 156 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchBiosWriteProtect.c = | 156 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.c = | 179 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchLanSxSmm.c = | 298 +++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c = | 436 +++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchSpiAsync.c = | 69 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/SmmControlDri= ver.c | 399 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpi.c = | 310 +++++++++++ 24 files changed, 4895 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeC= nl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeCnl.i= nf new file mode 100644 index 0000000000..5e0cf06cb6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeCnl.inf @@ -0,0 +1,99 @@ +## @file +# Component description file for Pch Initialization driver +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PchInitDxe +FILE_GUID =3D DE23ACEE-CF55-4fb6-AA77-984AB53DE823 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_DRIVER +ENTRY_POINT =3D PchInitEntryPointDxe + + +[LibraryClasses] +S3BootScriptLib +PchCycleDecodingLib +PchPcieRpLib +PchPcrLib +PchInfoLib +PchPciExpressHelpersLib +UefiBootServicesTableLib +DebugLib +IoLib +TimerLib +HobLib +BaseMemoryLib +MemoryAllocationLib +UefiLib +DxeServicesTableLib +UefiDriverEntryPoint +UefiRuntimeServicesTableLib +AslUpdateLib +CpuPlatformLib +GpioLib +PchSerialIoLib +PchHdaLib +PchInitCommonLib +ConfigBlockLib +PmcLib +PmcPrivateLib +PmcPrivateLibWithS3 +SataLib +PchDmiWithS3Lib +PchGbeLib +SiScheduleResetLib +BiosLockLib +DxeSaPolicyLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr + + +[Sources] +PchInitDxe.c +PchInit.h +PchInit.c +PchSata.c +PchSerialIo.c +PchSerialIoDxe.c +PchHdaAcpi.c +PchCnviAcpi.c +PchAcpi.c + +[Protocols] +gPchNvsAreaProtocolGuid ## PRODUCES +gPchEmmcTuningProtocolGuid ## PRODUCES +gEfiPciIoProtocolGuid ## CONSUMES +gEfiAcpiTableProtocolGuid ## CONSUMES +gEfiBlockIoProtocolGuid ## CONSUMES +gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES +gPchPcieIoTrapProtocolGuid ## CONSUMES +gPchPolicyProtocolGuid ## CONSUMES + + +[Guids] +gEfiEndOfDxeEventGroupGuid +gEfiAcpiTableGuid +gSiConfigHobGuid ## CONSUMES +gPchConfigHobGuid ## CONSUMES +gPchRstHobGuid ## CONSUMES +gHdAudioDxeConfigGuid ## CONSUMES +gGpioDxeConfigGuid ## CONSUMES + + +[Depex] +gEfiPciHostBridgeResourceAllocationProtocolGuid ## This is to ensure that = PCI MMIO and IO resource has been prepared and available for this driver to= allocate. + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeF= spCnl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeFs= pCnl.inf new file mode 100644 index 0000000000..528cfd0296 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxeFspCnl.i= nf @@ -0,0 +1,77 @@ +## @file +# Component description file for Pch Initialization driver for FSP package +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010005 +BASE_NAME =3D PchInitDxe +FILE_GUID =3D 5AA5031E-4CB6-43D4-B219-FE50FF5D116C +MODULE_TYPE =3D PEIM +VERSION_STRING =3D 1.0 +ENTRY_POINT =3D PchInitEntryPointFsp + + +[LibraryClasses] +PeimEntryPoint +PchCycleDecodingLib +PchPcieRpLib +PchPcrLib +PchInfoLib +PchPciExpressHelpersLib +DebugLib +IoLib +TimerLib +HobLib +BaseMemoryLib +MemoryAllocationLib +CpuPlatformLib +GpioLib +PchSerialIoLib +PchInitCommonLib +S3BootScriptLib # NULL library +ConfigBlockLib +PmcLib +PmcPrivateLib +PmcPrivateLibWithS3 +UsbInitLib +PchDmiWithS3Lib +PchGbeLib +SiScheduleResetLib +BiosLockLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + +[Sources] +PchInitFsp.c +PchInit.h +PchInit.c +PchSata.c +PchSerialIo.c + + +[Protocols] +gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES + + +[Guids] +gEfiEventReadyToBootGuid +gSiConfigHobGuid ## CONSUMES +gPchConfigHobGuid ## CONSUMES + + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.= inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.inf new file mode 100644 index 0000000000..308da65385 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.inf @@ -0,0 +1,101 @@ +## @file +# Component description file for PchInitSmm driver +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PchInitSmm +FILE_GUID =3D D7B10D4E-67E6-4C74-83E9-F9AF0ACC33CC +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_SMM_DRIVER +PI_SPECIFICATION_VERSION =3D 1.10 +ENTRY_POINT =3D PchInitSmmEntryPoint +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + + +[LibraryClasses] +UefiBootServicesTableLib +UefiDriverEntryPoint +DxeServicesTableLib +IoLib +DebugLib +BaseLib +BaseMemoryLib +S3BootScriptLib +PchPciExpressHelpersLib +SmmServicesTableLib +PciSegmentLib +HobLib +GpioLib +GpioPrivateLib +ReportStatusCodeLib +DevicePathLib +PmcLib +PchPcieRpLib +PchInfoLib +TimerLib +ConfigBlockLib +PmcPrivateLib +SataLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize + + +[Sources] +PchInitSmm.c +PchPcieSmm.c +PchLanSxSmm.c +PchInitSmm.h +PchBiosWriteProtect.c +PchSpiAsync.c + + +[Protocols] +gEfiSmmIoTrapDispatch2ProtocolGuid ## CONSUMES +gEfiSmmSxDispatch2ProtocolGuid ## CONSUMES +gPchSmmIoTrapControlGuid ## CONSUMES +gEfiSmmCpuProtocolGuid ## CONSUMES +gPchNvsAreaProtocolGuid ## CONSUMES +gPchPcieSmiDispatchProtocolGuid ## CONSUMES +gPchTcoSmiDispatchProtocolGuid ## CONSUMES +gPchSmiDispatchProtocolGuid ## CONSUMES +gPchEspiSmiDispatchProtocolGuid ## CONSUMES +gPchPcieIoTrapProtocolGuid ## PRODUCES + + +[Guids] +gSiConfigHobGuid ## CONSUMES +gPchConfigHobGuid ## CONSUMES +gPchDeviceTableHobGuid + + +[Depex] +gEfiSmmIoTrapDispatch2ProtocolGuid AND +gEfiSmmSxDispatch2ProtocolGuid AND +gPchSmmIoTrapControlGuid AND +gPchPcieSmiDispatchProtocolGuid AND +gPchTcoSmiDispatchProtocolGuid AND +gEfiSmmCpuProtocolGuid AND +gPchNvsAreaProtocolGuid AND +gEfiPciHostBridgeResourceAllocationProtocolGuid AND # This is to ensure th= at PCI MMIO resource has been prepared and available for this driver to all= ocate. +gEfiSmmBase2ProtocolGuid # This is for SmmServicesTableLib + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/S= mmControl.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDx= e/SmmControl.inf new file mode 100644 index 0000000000..ff712f8635 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/SmmContr= ol.inf @@ -0,0 +1,54 @@ +## @file +# Component description file for SmmControl module +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D SmmControl +FILE_GUID =3D A0BAD9F7-AB78-491b-B583-C52B7F84B9E0 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_RUNTIME_DRIVER +ENTRY_POINT =3D SmmControlDriverEntryInit +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + + + +[LibraryClasses] +IoLib +UefiDriverEntryPoint +DebugLib +UefiBootServicesTableLib +UefiRuntimeServicesTableLib +PmcLib +GpioLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +SmmControlDriver.h +SmmControlDriver.c + + +[Protocols] +gEfiSmmControl2ProtocolGuid ## PRODUCES + + +[Guids] +gEfiEventVirtualAddressChangeGuid + + +[Depex] +TRUE diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpiSmm.inf b= /Silicon/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpiSmm.inf new file mode 100644 index 0000000000..77bd3ad72b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpiSmm.inf @@ -0,0 +1,45 @@ +## @file +# Component description file for the SPI SMM driver. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PchSpiSmm +FILE_GUID =3D 27F4917B-A707-4aad-9676-26DF168CBF0D +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_SMM_DRIVER +PI_SPECIFICATION_VERSION =3D 1.10 +ENTRY_POINT =3D InstallPchSpi + + +[LibraryClasses] +DebugLib +IoLib +UefiDriverEntryPoint +UefiBootServicesTableLib +BaseLib +SmmServicesTableLib +PchSpiCommonLib +SmmPchPrivateLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +PchSpi.c + + +[Protocols] +gPchSmmSpiProtocolGuid ## PRODUCES +gEfiSmmCpuProtocolGuid ## CONSUMES + +[Depex] +gEfiSmmBase2ProtocolGuid AND # This is for SmmServicesTableLib +gEfiSmmCpuProtocolGuid # This is for CpuSmmDisableBiosWriteProtect() diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInit.h b= /Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInit.h new file mode 100644 index 0000000000..b84c574a2e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInit.h @@ -0,0 +1,223 @@ +/** @file + Header file for PCH Initialization Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_INIT_DXE_H_ +#define _PCH_INIT_DXE_H_ + +#include +#include +#include +#include + +// +// Data definitions +// +extern EFI_HANDLE mImageHandle; + +// +// Pch NVS area definition +// +extern PCH_NVS_AREA_PROTOCOL mPchNvsAreaProtocol; + +extern PCH_CONFIG_HOB *mPchConfigHob; +extern SI_CONFIG_HOB_DATA *mSiConfigHobData; + +// +// Function Prototype +// + +// +// Local function prototypes +// +/** + Initialize the PCH device according to the PCH Policy HOB + and install PCH info instance. + +**/ +VOID +InitializePchDevice ( + VOID + ); + +/** + Common PchInit Module Entry Point +**/ +VOID +PchInitEntryPointCommon ( + VOID + ); + +/** + Common PCH initialization on PCI enumeration complete. +**/ +VOID +PchOnPciEnumCompleteCommon ( + VOID + ); + +/** + Configures Serial IO Controllers + +**/ +EFI_STATUS +ConfigureSerialIoAtBoot ( + VOID + ); + +/** + Creates device handles for SerialIo devices in ACPI mode + +**/ +VOID +CreateSerialIoHandles ( + VOID + ); + +/** + Mark memory used by SerialIo devices in ACPI mode as allocated + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +AllocateSerialIoMemory ( + VOID + ); + +/** + Puts all SerialIo controllers (except UARTs in debug mode) in D3. + Clears MemoryEnable for all PCI-mode controllers on S3 resume +**/ +VOID +ConfigureSerialIoAtS3Resume ( + VOID + ); + +/** + Update ASL definitions for SerialIo devices. + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +UpdateSerialIoAcpiData ( + VOID + ); + +/** + Initialize PCIE SRC clocks in ICC subsystem + + @param[in] GbePortNumber Number of PCIE rootport assigned to GbE = adapter + +**/ +VOID +ConfigurePchPcieClocks ( + IN UINTN GbePortNumber + ); + +/** + Initialize Intel High Definition Audio ACPI Tables + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_LOAD_ERROR ACPI table cannot be installed + @retval EFI_UNSUPPORTED ACPI table not set because DSP is disabl= ed +**/ +EFI_STATUS +PchHdAudioAcpiInit ( + VOID + ); + +/** + Configure eMMC in HS400 Mode + + @param[in] This A pointer to PCH_EMMC_TUNING_PRO= TOCOL structure + @param[in] Revision Revision parameter used to verif= y the layout of EMMC_INFO and TUNINGDATA. + @param[in] EmmcInfo A pointer to EMMC_INFO structure + @param[out] EmmcTuningData A pointer to EMMC_TUNING_DATA st= ructure + + @retval EFI_SUCCESS The function completed successfu= lly + @retval EFI_NOT_FOUND The item was not found + @retval EFI_OUT_OF_RESOURCES The request could not be complet= ed due to a lack of resources. + @retval EFI_INVALID_PARAMETER A parameter was incorrect. + @retval EFI_DEVICE_ERROR Hardware Error + @retval EFI_NO_MEDIA No media + @retval EFI_MEDIA_CHANGED Media Change + @retval EFI_BAD_BUFFER_SIZE Buffer size is bad + @retval EFI_CRC_ERROR Command or Data CRC Error +**/ +EFI_STATUS +EFIAPI +ConfigureEmmcHs400Mode ( + IN PCH_EMMC_TUNING_PROTOCOL *This, + IN UINT8 Revision, + IN EMMC_INFO *EmmcInfo, + OUT EMMC_TUNING_DATA *EmmcTuningData + ); + +/** + Get eMMC PCI cfg space address + + @return UINT64 PCI base address +**/ +UINT64 +ScsGetEmmcBaseAddress ( + VOID + ); + +/** + Perform the remaining configuration on PCH SATA to perform device detect= ion, + then set the SATA SPD and PxE corresponding, and set the Register Lock o= n PCH SATA + + @retval None +**/ +VOID +ConfigurePchSataOnEndOfDxe ( + VOID + ); + +/** + Update ASL data for CNVI Device. + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +UpdateCnviAcpiData ( + VOID + ); + +/** + Initialize Pch acpi + @param[in] ImageHandle Handle for the image of this driver + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +PchAcpiInit ( + IN EFI_HANDLE ImageHandle + ); + +/** + Update ASL object before Boot + + @retval EFI_STATUS + @retval EFI_NOT_READY The Acpi protocols are not ready. +**/ +EFI_STATUS +PchUpdateNvsArea ( + VOID + ); + +/** + Initialize PCH Nvs Area opeartion region. + +**/ +VOID +PatchPchNvsAreaAddress ( + VOID + ); + +#endif // _PCH_INIT_DXE_H_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.= h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h new file mode 100644 index 0000000000..693c5d3f50 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.h @@ -0,0 +1,187 @@ +/** @file + Header file for PCH Init SMM Handler + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_INIT_SMM_H_ +#define _PCH_INIT_SMM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *mPchIoTrap; +extern EFI_SMM_SX_DISPATCH2_PROTOCOL *mSxDispatch; + +extern PCH_NVS_AREA *mPchNvsArea; +extern UINT16 mAcpiBaseAddr; + +extern EFI_PHYSICAL_ADDRESS mResvMmioBaseAddr; +extern UINTN mResvMmioSize; + +// +// NOTE: The module variables of policy here are only valid in post time, = but not runtime time. +// +extern PCH_CONFIG_HOB *mPchConfigHob; +extern SI_CONFIG_HOB_DATA *mSiConfigHobData; + +/** + Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling + + @param[in] ImageHandle The image handle of this module + @param[in] SystemTable The EFI System Table + + @retval EFI_SUCCESS The function completes successfully +**/ +EFI_STATUS +EFIAPI +InitializePchPcieSmm ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + PCIE Hotplug SMI call back function for each Root port + + @param[in] DispatchHandle Handle of this dispatch function + @param[in] RpContext Rootport context, which contains R= ootPort Index, + and RootPort PCI BDF. +**/ +VOID +EFIAPI +PchPcieSmiRpHandlerFunction ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ); + +/** + PCIE Link Active State Change Hotplug SMI call back function for all Roo= t ports + + @param[in] DispatchHandle Handle of this dispatch function + @param[in] RpContext Rootport context, which contains R= ootPort Index, + and RootPort PCI BDF. +**/ +VOID +EFIAPI +PchPcieLinkActiveStateChange ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ); + +/** + PCIE Link Equalization Request SMI call back function for all Root ports + + @param[in] DispatchHandle Handle of this dispatch function + @param[in] RpContext Rootport context, which contains R= ootPort Index, + and RootPort PCI BDF. +**/ +VOID +EFIAPI +PchPcieLinkEqHandlerFunction ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ); + +/** + An IoTrap callback to config PCIE power management settings + + @param[in] DispatchHandle - The handle of this callback, obtained when = registering + @param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CAL= LBACK_CONTEXT + +**/ +VOID +EFIAPI +PchPcieIoTrapSmiCallback ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ); + +/** + Initializes the PCH SMM handler for PCH save and restore + + @param[in] ImageHandle - Handle for the image of this driver + @param[in] SystemTable - Pointer to the EFI System Table + + @retval EFI_SUCCESS - PCH SMM handler was installed +**/ +EFI_STATUS +EFIAPI +PchInitLateSmm ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + Register dispatch function to handle GPIO pads Sx isolation +**/ +VOID +InitializeGpioSxIsolationSmm ( + VOID + ); + +/** + Entry point for Pch Bios Write Protect driver. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. +**/ +EFI_STATUS +EFIAPI +InstallPchBiosWriteProtect ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + This fuction install SPI ASYNC SMI handler. + + @retval EFI_SUCCESS Initialization complete. +**/ +EFI_STATUS +EFIAPI +InstallPchSpiAsyncSmiHandler ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/S= mmControlDriver.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/Runti= meDxe/SmmControlDriver.h new file mode 100644 index 0000000000..08e64fa5a7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/SmmContr= olDriver.h @@ -0,0 +1,132 @@ +/** @file + Header file for SMM Control Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SMM_CONTROL_DRIVER_H_ +#define _SMM_CONTROL_DRIVER_H_ + +#include + + +#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4', 's', '= c') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_SMM_CONTROL2_PROTOCOL SmmControl; +} SMM_CONTROL_PRIVATE_DATA; + +#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) CR (a, SMM_CONTROL_PRIVATE_D= ATA, SmmControl, SMM_CONTROL_DEV_SIGNATURE) + +// +// Prototypes +// + +/** + SmmControl DXE RUNTIME Module Entry Point\n + - Introduction\n + The SmmControl module is a DXE RUNTIME driver that provides a standard= way + for other drivers to trigger software SMIs. + + - @pre + - PCH Power Management I/O space base address has already been program= med. + If SmmControl Runtime DXE driver is run before Status Code Runtime P= rotocol + is installed and there is the need to use Status code in the driver,= it will + be necessary to add EFI_STATUS_CODE_RUNTIME_PROTOCOL_GUID to the dep= endency file. + - EFI_SMM_BASE2_PROTOCOL + - Documented in the System Management Mode Core Interface Specificat= ion. + + - @result + The SmmControl driver produces the EFI_SMM_CONTROL_PROTOCOL documented= in + System Management Mode Core Interface Specification. + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_STATUS Results of the installation of the SMM C= ontrol Protocol +**/ +EFI_STATUS +EFIAPI +SmmControlDriverEntryInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + Trigger the software SMI + + @param[in] Data The value to be set on the software SMI = data port + + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +SmmTrigger ( + UINT8 Data + ); + +/** + Clear the SMI status + + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_DEVICE_ERROR Something error occurred +**/ +EFI_STATUS +EFIAPI +SmmClear ( + VOID + ); + +/** + This routine generates an SMI + + @param[in] This The EFI SMM Control protocol insta= nce + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic Periodic or not + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI Status Describing the result of the opera= tion + @retval EFI_INVALID_PARAMETER Some parameter value passed is not= supported +**/ +EFI_STATUS +EFIAPI +Activate ( + IN CONST EFI_SMM_CONTROL2_PROTOCOL *This, + IN OUT UINT8 *ArgumentBuffer OPTIONAL, + IN OUT UINT8 *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +/** + This routine clears an SMI + + @param[in] This The EFI SMM Control protocol instance + @param[in] Periodic Periodic or not + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted +**/ +EFI_STATUS +EFIAPI +Deactivate ( + IN CONST EFI_SMM_CONTROL2_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL + ); +/** + Disable all pending SMIs + +**/ +VOID +EFIAPI +DisablePendingSmis ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchAcpi.c b= /Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchAcpi.c new file mode 100644 index 0000000000..bcbdb12dc3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchAcpi.c @@ -0,0 +1,451 @@ +/** @file + This is the driver that initializes the Intel PCH. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +#include "PchInit.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Module variables +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_NVS_AREA_PROTOCOL mPchNvsAreaProtocol; + +/** + Retrieve interrupt information about a PCH device from policy + + @param[in] Device PCI device number + + @retval PCH_DEVICE_INTERRUPT_CONFIG structure with device's interrupt = information +**/ +PCH_DEVICE_INTERRUPT_CONFIG +GetInterruptPolicy ( + IN PCH_SERIAL_IO_CONTROLLER Device + ) +{ + PCH_DEVICE_INTERRUPT_CONFIG EmptyRecord; + UINT8 DevNum; + UINT8 FuncNum; + UINT8 Index; + + ZeroMem (&EmptyRecord, sizeof (PCH_DEVICE_INTERRUPT_CONFIG)); + DevNum =3D GetSerialIoDeviceNumber (Device); + FuncNum =3D GetSerialIoFunctionNumber (Device); + + for (Index =3D 0; Index < mPchConfigHob->Interrupt.NumOfDevIntConfig; In= dex++) { + if ((mPchConfigHob->Interrupt.DevIntConfig[Index].Device =3D=3D DevNum= ) && + (mPchConfigHob->Interrupt.DevIntConfig[Index].Function =3D=3D Func= Num)) { + return mPchConfigHob->Interrupt.DevIntConfig[Index]; + } + } + return EmptyRecord; +} + +/** + Update ASL definitions for SerialIo devices. + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +UpdateSerialIoAcpiData ( + VOID + ) +{ + PCH_SERIAL_IO_CONTROLLER Index; + + for (Index =3D 0; Index < GetPchMaxSerialIoControllersNum (); Index++) { + mPchNvsAreaProtocol.Area->SMD[Index] =3D mPchConfigHob->SerialIo.DevMo= de[Index]; + mPchNvsAreaProtocol.Area->SIR[Index] =3D (GetInterruptPolicy (Index)).= Irq; + mPchNvsAreaProtocol.Area->SB0[Index] =3D (UINT32) FindSerialIoBar (Ind= ex, 0); + mPchNvsAreaProtocol.Area->SB1[Index] =3D (UINT32) FindSerialIoBar (Ind= ex, 1); + } + if (IsPchH ()) { + mPchNvsAreaProtocol.Area->SMD[PchSerialIoIndexI2C4] =3D PchSerialIoDis= abled; + mPchNvsAreaProtocol.Area->SMD[PchSerialIoIndexI2C5] =3D PchSerialIoDis= abled; + } + + return EFI_SUCCESS; +} + +/** + Update NVS Area after RST PCIe Storage Remapping and before Boot +**/ +VOID +PchUpdateNvsAreaAfterRemapping ( + VOID + ) +{ + UINTN Index; + VOID *Hob; + PCH_RST_HOB *RstHob; + + Hob =3D GetFirstGuidHob (&gPchRstHobGuid); + if (Hob =3D=3D NULL) { + DEBUG (( DEBUG_INFO , "PchUpdateNvsAreaAfterRemapping: cannot fetch Rs= tHob" )); + return; + } + + RstHob =3D (PCH_RST_HOB *) GET_GUID_HOB_DATA (Hob); + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + mPchNvsAreaProtocol.Area->RstPcieStorageInterfaceType[Index] = =3D RstHob->RstCrConfiguration[Index].DeviceInterface; + mPchNvsAreaProtocol.Area->RstPcieStoragePmCapPtr[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].PmCapPtr; + mPchNvsAreaProtocol.Area->RstPcieStoragePcieCapPtr[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].PcieCapPtr; + mPchNvsAreaProtocol.Area->RstPcieStorageL1ssCapPtr[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].L1ssCapPtr; + mPchNvsAreaProtocol.Area->RstPcieStorageEpL1ssControl2[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointL1ssControl2; + mPchNvsAreaProtocol.Area->RstPcieStorageEpL1ssControl1[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointL1ssControl1; + mPchNvsAreaProtocol.Area->RstPcieStorageLtrCapPtr[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].LtrCapPtr; + mPchNvsAreaProtocol.Area->RstPcieStorageEpLtrData[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointLtrData; + mPchNvsAreaProtocol.Area->RstPcieStorageEpLctlData16[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointLctlData16; + mPchNvsAreaProtocol.Area->RstPcieStorageEpDctlData16[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointDctlData16; + mPchNvsAreaProtocol.Area->RstPcieStorageEpDctl2Data16[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].EndpointDctl2Data16; + mPchNvsAreaProtocol.Area->RstPcieStorageRpDctl2Data16[Index] = =3D RstHob->SavedRemapedDeviceConfigSpace[Index].RootPortDctl2Data16; + mPchNvsAreaProtocol.Area->RstPcieStorageUniqueTableBar[Index] = =3D RstHob->RstCrConfiguration[Index].EndPointUniqueMsixTableBar; + mPchNvsAreaProtocol.Area->RstPcieStorageUniqueTableBarValue[Index] = =3D RstHob->RstCrConfiguration[Index].EndPointUniqueMsixTableBarValue; + mPchNvsAreaProtocol.Area->RstPcieStorageUniquePbaBar[Index] = =3D RstHob->RstCrConfiguration[Index].EndPointUniqueMsixPbaBar; + mPchNvsAreaProtocol.Area->RstPcieStorageUniquePbaBarValue[Index] = =3D RstHob->RstCrConfiguration[Index].EndPointUniqueMsixPbaBarValue; + mPchNvsAreaProtocol.Area->RstPcieStorageRootPortNum[Index] = =3D RstHob->RstCrConfiguration[Index].RootPortNum; + } +} + +/** + PCH ACPI initialization before Boot Sript Table is closed + It update ACPI table and ACPI NVS area. + + @param[in] Event A pointer to the Event that triggered th= e callback. + @param[in] Context A pointer to private data registered wit= h the callback function. +**/ +VOID +EFIAPI +PchAcpiOnEndOfDxe ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "PchAcpiOnEndOfDxe() Start\n")); + + /// + /// Closed the event to avoid call twice when launch shell + /// + gBS->CloseEvent (Event); + + // + // Init HDA Audio ACPI tables + // + PchHdAudioAcpiInit (); + + // + // Update ASL definitions for SerialIo devices. + // + UpdateSerialIoAcpiData (); + UpdateCnviAcpiData (); + + // + // Update Pch Nvs Area + // + Status =3D PchUpdateNvsArea (); + if (EFI_ERROR (Status)) { + return; + } + + DEBUG ((DEBUG_INFO, "PchAcpiOnEndOfDxe() End\n")); + + return; +} + +/** + Initialize Pch acpi + @param[in] ImageHandle Handle for the image of this driver + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +PchAcpiInit ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + DEBUG ((DEBUG_INFO, "Install PCH NVS protocol\n")); + + Status =3D (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (PCH_NVS_AREA),= (VOID **) &mPchNvsAreaProtocol.Area); + ASSERT_EFI_ERROR (Status); + + ZeroMem ((VOID *) mPchNvsAreaProtocol.Area, sizeof (PCH_NVS_AREA)); + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gPchNvsAreaProtocolGuid, + &mPchNvsAreaProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update the NVS Area after RST PCIe Storage Remapping + /// + PchUpdateNvsAreaAfterRemapping (); + + // + // Register an end of DXE event for PCH ACPI to do tasks before invoking= any UEFI drivers, + // applications, or connecting consoles,... + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + PchAcpiOnEndOfDxe, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +/** + Update ASL object before Boot + + @retval EFI_STATUS + @retval EFI_NOT_READY The Acpi protocols are not ready. +**/ +EFI_STATUS +PchUpdateNvsArea ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + UINT32 HpetBaseAdress; + GPIO_GROUP GroupToGpeDwX[3]; + UINT32 GroupDw[3]; + UINTN RpDev; + UINTN RpFun; + UINT32 Data32; + PCH_POLICY_PROTOCOL *PchPolicy; + PCH_GPIO_DXE_CONFIG *GpioDxeConfig; + + /// + /// Get PCH Policy Protocol + /// + Status =3D gBS->LocateProtocol (&gPchPolicyProtocolGuid, NULL, (VOID **)= &PchPolicy); + ASSERT_EFI_ERROR (Status); + + /// + /// Get GPIO DXE Config Block + /// + Status =3D GetConfigBlock ((VOID *)PchPolicy, &gGpioDxeConfigGuid, (VOID= *)&GpioDxeConfig); + ASSERT_EFI_ERROR (Status); + + // + // Update ASL PCIE port address according to root port device and functi= on + // + for (Index =3D 0; Index < GetPchMaxPciePortNum (); Index++) { + Status =3D GetPchPcieRpDevFun (Index, &RpDev, &RpFun); + ASSERT_EFI_ERROR (Status); + + Data32 =3D ((UINT8) RpDev << 16) | (UINT8) RpFun; + mPchNvsAreaProtocol.Area->RpAddress[Index] =3D Data32; + + // + // Update Maximum Snoop Latency and Maximum No-Snoop Latency values fo= r PCIE + // + mPchNvsAreaProtocol.Area->PcieLtrMaxSnoopLatency[Index] =3D mPchConf= igHob->PcieRp.RootPort[Index].LtrMaxSnoopLatency; + mPchNvsAreaProtocol.Area->PcieLtrMaxNoSnoopLatency[Index] =3D mPchConf= igHob->PcieRp.RootPort[Index].LtrMaxNoSnoopLatency; + } + + // + // Update PCHS. + // + mPchNvsAreaProtocol.Area->PchSeries =3D PchSeries (); + // + // Update PCHG. + // + mPchNvsAreaProtocol.Area->PchGeneration =3D (UINT16) PchGeneration (); + // + // Update PSTP. + // + mPchNvsAreaProtocol.Area->PchStepping =3D (UINT16) PchStepping (); + // + // Update HPET base address. + // + PchHpetBaseGet (&HpetBaseAdress); + mPchNvsAreaProtocol.Area->HPTE =3D TRUE; // @todo remove the N= VS, since it's always enabled. + mPchNvsAreaProtocol.Area->HPTB =3D HpetBaseAdress; + // + // Update SBREG_BAR. + // + mPchNvsAreaProtocol.Area->SBRG =3D PCH_PCR_BASE_ADDRESS; + + // + // Update PMC ACPIBASE and PWRMBASE + // + mPchNvsAreaProtocol.Area->PMBS =3D PmcGetAcpiBase (); + + mPchNvsAreaProtocol.Area->PWRM =3D PmcGetPwrmBase (); + + // + // Update GPIO device ACPI variables + // + mPchNvsAreaProtocol.Area->SGIR =3D mPchConfigHob->Interrupt.GpioIrqRoute; + mPchNvsAreaProtocol.Area->GPHD =3D (UINT8)GpioDxeConfig->HideGpioAcpiDev= ice; + + // + // Update GPP_X to GPE_DWX mapping. + // + GpioGetGroupDwToGpeDwX ( + &GroupToGpeDwX[0], &GroupDw[0], + &GroupToGpeDwX[1], &GroupDw[1], + &GroupToGpeDwX[2], &GroupDw[2] + ); + + // + // GEI0/1/2 and GED0/1/2 are objects for informing how GPIO groups are m= apped to GPE0. + // If Group is mapped to 1-Tier GPE information is also stored on what G= roup DW + // is mapped to GPE_DWx. Because GPE_DWx register is 32 bits large if gr= oups have more than + // 32 pads only part of it can be mapped. + // + // GEIx - GroupIndex mapped to GPE0_DWx + // GEDx - DoubleWorld part of Group: 0 - pins 31-0, 1 - pins 63-32, ... + // + mPchNvsAreaProtocol.Area->GEI0 =3D (UINT8) GpioGetGroupIndexFromGroup (G= roupToGpeDwX[0]); + mPchNvsAreaProtocol.Area->GEI1 =3D (UINT8) GpioGetGroupIndexFromGroup (G= roupToGpeDwX[1]); + mPchNvsAreaProtocol.Area->GEI2 =3D (UINT8) GpioGetGroupIndexFromGroup (G= roupToGpeDwX[2]); + mPchNvsAreaProtocol.Area->GED0 =3D (UINT8) GroupDw[0]; + mPchNvsAreaProtocol.Area->GED1 =3D (UINT8) GroupDw[1]; + mPchNvsAreaProtocol.Area->GED2 =3D (UINT8) GroupDw[2]; + + // + // SCS Configuration + // + // Update eMMC HS400 mode enablement + // + mPchNvsAreaProtocol.Area->EMH4 =3D (UINT8) mPchConfigHob->Scs.ScsEmmcHs4= 00Enabled; + mPchNvsAreaProtocol.Area->EmmcEnabled =3D (UINT8) mPchConfigHob->Scs.Scs= EmmcEnabled; + + // + // Update eMMC Driver Strength + // Per eMMC 5.01 JEDEC Specification (JESD84-B50.1, Table 186) + // Nominal Impedance - Driver Type Values: + // 50 Ohm 0x0 + // 33 Ohm 0x1 + // 40 Ohm 0x4 + // + switch (mPchConfigHob->Scs.ScsEmmcHs400DriverStrength) { + case DriverStrength33Ohm: + mPchNvsAreaProtocol.Area->EMDS =3D 0x1; + break; + case DriverStrength40Ohm: + mPchNvsAreaProtocol.Area->EMDS =3D 0x4; + break; + case DriverStrength50Ohm: + default: + mPchNvsAreaProtocol.Area->EMDS =3D 0x0; + } + + mPchNvsAreaProtocol.Area->SdPowerEnableActiveHigh =3D (UINT8) mPchConfig= Hob->Scs.ScsSdPowerEnableActiveHigh; + mPchNvsAreaProtocol.Area->SdCardEnabled =3D (UINT8) mPchConfig= Hob->Scs.ScsSdCardEnabled; + + // + // SATA configuration. + // + if (PciSegmentRead16 (GetSataRegBase (SATA_1_CONTROLLER_INDEX) + PCI_DEV= ICE_ID_OFFSET) =3D=3D 0xFFFF) { + mPchNvsAreaProtocol.Area->SataPortPresence =3D 0; + } else { + mPchNvsAreaProtocol.Area->SataPortPresence =3D PciSegmentRead8 (GetSat= aRegBase (SATA_1_CONTROLLER_INDEX) + R_SATA_CFG_PCS + 2); + } + + // + // CPU SKU + // + mPchNvsAreaProtocol.Area->CpuSku =3D GetCpuSku (); + + mPchNvsAreaProtocol.Area->SlpS0VmRuntimeControl =3D (UINT8)mPchConfigHob= ->Pm.SlpS0VmRuntimeControl; + mPchNvsAreaProtocol.Area->SlpS0Vm070VSupport =3D (UINT8)mPchConfigHob= ->Pm.SlpS0Vm070VSupport; + mPchNvsAreaProtocol.Area->SlpS0Vm075VSupport =3D (UINT8)mPchConfigHob= ->Pm.SlpS0Vm075VSupport; + mPchNvsAreaProtocol.Area->PsOnEnable =3D (UINT8)mPchConfigHob= ->Pm.PsOnEnable; + + for (Index =3D 0; Index < GetPchMaxPciePortNum (); Index++) { + mPchNvsAreaProtocol.Area->LtrEnable[Index] =3D (UINT8)mPchConfigHob->= PcieRp.RootPort[Index].LtrEnable; + } + + mPchNvsAreaProtocol.Area->GBES =3D PchIsGbePresent (); + + // + // Update PCH Trace Hub Mode + // + mPchNvsAreaProtocol.Area->PchTraceHubMode =3D (UINT8) mPchConfigHob-= >PchTraceHub.PchTraceHubMode; + // + // if SCRPD0[24] is set, force TH to be host debugger mode. + // + if (MmioRead32 (PCH_TRACE_HUB_MTB_BASE_ADDRESS) !=3D 0xFFFFFFFF) { + if (MmioRead32 (PCH_TRACE_HUB_MTB_BASE_ADDRESS + R_TRACE_HUB_MEM_CSR_M= TB_SCRATCHPAD0) & BIT24) { + mPchNvsAreaProtocol.Area->PchTraceHubMode =3D TraceHubModeHostDebugg= er; + } + } + + // + // Update TWMB, Temp memory base address + // + mPchNvsAreaProtocol.Area->TempRsvdMemBase =3D (UINT32) PcdGet32 (PcdSili= conInitTempMemBaseAddr); + + return Status; +} + +/** + Initialize PCH Nvs Area opeartion region. + +**/ +VOID +PatchPchNvsAreaAddress ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 Address; + UINT16 Length; + + Status =3D InitializeAslUpdateLib (); + ASSERT_EFI_ERROR (Status); + + Address =3D (UINT32) (UINTN) mPchNvsAreaProtocol.Area; + Length =3D (UINT16) sizeof (PCH_NVS_AREA); + DEBUG ((DEBUG_INFO, "PatchPchNvsAreaAddress: PCH NVS Address %x Length %= x\n", Address, Length)); + Status =3D UpdateNameAslCode (SIGNATURE_32 ('P','N','V','B'), &Address,= sizeof (Address)); + ASSERT_EFI_ERROR (Status); + Status =3D UpdateNameAslCode (SIGNATURE_32 ('P','N','V','L'), &Length, = sizeof (Length)); + ASSERT_EFI_ERROR (Status); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchCnviAcpi= .c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchCnviAcpi.c new file mode 100644 index 0000000000..4e38db1027 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchCnviAcpi.c @@ -0,0 +1,33 @@ +/** @file + Initializes PCH CNVi device ACPI data. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include "PchInit.h" +#include + +/** + Update ASL definitions for CNVi device. + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +UpdateCnviAcpiData ( + VOID + ) +{ + + DEBUG ((DEBUG_INFO, "UpdateCnviAcpiData() Start\n")); + + mPchNvsAreaProtocol.Area->CnviMode =3D (UINT8) mPchConfigHob->Cnvi.Mode; + + DEBUG ((DEBUG_INFO, "UpdateCnviAcpiData() End\n")); + + return EFI_SUCCESS; +} + + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchHdaAcpi.= c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchHdaAcpi.c new file mode 100644 index 0000000000..57f2e1dca0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchHdaAcpi.c @@ -0,0 +1,323 @@ +/** @file + Initializes the PCH HD Audio ACPI Tables. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "PchInit.h" +#include +#include +#include +#include +#include +#include +#include +#include + +PCH_HDA_NHLT_ENDPOINTS mPchHdaNhltEndpoints[HdaEndpointMax] =3D +{ + {HdaDmicX1, B_HDA_DMIC_1CH_48KHZ_16BIT_FORMAT, = 0, FALSE}, + {HdaDmicX2, (B_HDA_DMIC_2CH_48KHZ_16BIT_FORMAT | B_HDA_DMIC_2CH_48KH= Z_32BIT_FORMAT), 0, FALSE}, + {HdaDmicX4, (B_HDA_DMIC_4CH_48KHZ_16BIT_FORMAT | B_HDA_DMIC_4CH_48KH= Z_32BIT_FORMAT), 0, FALSE}, + {HdaBtRender, (B_HDA_BT_NARROWBAND_FORMAT | B_HDA_BT_WIDEBAND_FORMAT |= B_HDA_BT_A2DP_FORMAT), 0, FALSE}, + {HdaBtCapture, (B_HDA_BT_NARROWBAND_FORMAT | B_HDA_BT_WIDEBAND_FORMAT),= 0, FALSE}, + {HdaI2sRender1, B_HDA_I2S_RTK274_RENDER_4CH_48KHZ_24BIT_FORMAT, B_HDA_I2= S_RENDER_DEVICE_INFO, FALSE}, + {HdaI2sRender2, B_HDA_I2S_RTK274_RENDER_4CH_48KHZ_24BIT_FORMAT, B_HDA_I2= S_RENDER_DEVICE_INFO, FALSE}, + {HdaI2sCapture, B_HDA_I2S_RTK274_CAPTURE_4CH_48KHZ_24BIT_FORMAT, B_HDA_I= 2S_CAPTURE_DEVICE_INFO, FALSE} +}; + +#define DSP_FW_STOLEN_MEMORY_SIZE 0x400000 //4MB +/** + Allocates 4MB of memory for DSP FW usage. + + @retval EFI_PHYSICAL_ADDRESS Allocated memory address +**/ +EFI_PHYSICAL_ADDRESS +AllocateAudioDspStolenMemory ( + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS DspStolenMemBaseAddress; + + DspStolenMemBaseAddress =3D 0; + + DEBUG ((DEBUG_INFO, "AllocateAudioDspStolenMemory()\n")); + + // + // Reserve memory to store Acpi Debug data. + // + DspStolenMemBaseAddress =3D 0xFFFFFFFF; + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiReservedMemoryType, + EFI_SIZE_TO_PAGES (DSP_FW_STOLEN_MEMORY_SIZE), + &DspStolenMemBaseAddress + ); + ASSERT_EFI_ERROR(Status); + + ZeroMem ((VOID *) (UINTN) DspStolenMemBaseAddress, DSP_FW_STOLEN_MEMORY_= SIZE); + + mPchNvsAreaProtocol.Area->DSPM =3D (UINT32) DspStolenMemBaseAddress; + DEBUG ((DEBUG_INFO, "mPchNvsAreaProtocol.Area->DSPM =3D 0x%016x\n", mPch= NvsAreaProtocol.Area->DSPM)); + + return DspStolenMemBaseAddress; +} + +/** + Retrieves address of NHLT table from XSDT/RSDT. + + @retval NHLT_ACPI_TABLE* Pointer to NHLT table if found + @retval NULL NHLT could not be found +**/ +NHLT_ACPI_TABLE * +LocateNhltAcpiTable ( + VOID + ) +{ + EFI_ACPI_3_0_ROOT_SYSTEM_DESCRIPTION_POINTER *Rsdp; + EFI_ACPI_DESCRIPTION_HEADER *Xsdt; + NHLT_ACPI_TABLE *Nhlt; + UINTN Index; + UINT64 Data64; + EFI_STATUS Status; + Rsdp =3D NULL; + Xsdt =3D NULL; + Nhlt =3D NULL; + + /// + /// Find the AcpiSupport protocol returns RSDP (or RSD PTR) address. + /// + DEBUG ((DEBUG_INFO, "LocateNhltAcpiTable() Start\n")); + + Status =3D EfiGetSystemConfigurationTable (&gEfiAcpiTableGuid, (VOID *) = &Rsdp); + if (EFI_ERROR (Status) || (Rsdp =3D=3D NULL)) { + DEBUG ((DEBUG_ERROR, "EFI_ERROR or Rsdp =3D=3D NULL\n")); + return NULL; + } + + Xsdt =3D (EFI_ACPI_DESCRIPTION_HEADER *) (UINTN) Rsdp->XsdtAddress; + if (Xsdt =3D=3D NULL || Xsdt->Signature !=3D EFI_ACPI_5_0_EXTENDED_SYSTE= M_DESCRIPTION_TABLE_SIGNATURE) { + // If XSDT has not been found, check RSDT + Xsdt =3D (EFI_ACPI_DESCRIPTION_HEADER *) (UINTN) Rsdp->RsdtAddress; + if (Xsdt =3D=3D NULL || Xsdt->Signature !=3D EFI_ACPI_5_0_ROOT_SYSTEM_= DESCRIPTION_TABLE_SIGNATURE) { + DEBUG ((DEBUG_ERROR, "XSDT/RSDT =3D=3D NULL or wrong signature\n")); + return NULL; + } + } + + for (Index =3D sizeof (EFI_ACPI_DESCRIPTION_HEADER); Index < Xsdt->Lengt= h; Index =3D Index + sizeof (UINT64)) { + Data64 =3D *(UINT64 *) ((UINT8 *) Xsdt + Index); + Nhlt =3D (NHLT_ACPI_TABLE *) (UINTN) Data64; + if (Nhlt->Header.Signature =3D=3D NHLT_ACPI_TABLE_SIGNATURE) { + break; + } + } + + if (Nhlt =3D=3D NULL || Nhlt->Header.Signature !=3D NHLT_ACPI_TABLE_SIGN= ATURE) { + DEBUG ((DEBUG_ERROR, "Nhlt =3D=3D NULL or wrong signature\n")); + return NULL; + } + + DEBUG ((DEBUG_INFO, "Found NhltTable, Address =3D 0x%016x\n", Nhlt)); + + return Nhlt; +} + +/** + Constructs and installs NHLT table. + + @retval EFI_SUCCESS ACPI Table installed successfully + @retval EFI_UNSUPPORTED ACPI Table protocol not found +**/ +EFI_STATUS +PublishNhltAcpiTable ( + VOID + ) +{ + UINTN AcpiTableKey; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + NHLT_ACPI_TABLE *NhltTable; + UINT32 TableLength; + EFI_STATUS Status; + + AcpiTable =3D NULL; + NhltTable =3D NULL; + AcpiTableKey =3D 0; + + DEBUG ((DEBUG_INFO, "PublishNhltAcpiTable() Start\n")); + + // + // Locate ACPI support protocol + // + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID = **) &AcpiTable); + if ( EFI_ERROR (Status) || AcpiTable =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + NhltConstructor (mPchHdaNhltEndpoints, &NhltTable, &TableLength); + NhltAcpiHeaderConstructor (NhltTable, TableLength); + + Status =3D AcpiTable->InstallAcpiTable (AcpiTable, NhltTable, NhltTable-= >Header.Length, &AcpiTableKey); + + DEBUG ((DEBUG_INFO, "PublishNhltAcpiTable() End\n")); + return Status; +} + +/** + Sets NVS ACPI variables for HDAS._DSM and SNDW._DSD accordingly to polic= y. + + @param[in] NhltAcpiTableAddress + @param[in] NhltAcpiTableLength + @param[in] *HdAudioConfigHob + @param[in] *HdAudioDxeConfig +**/ +VOID +UpdateHdaAcpiData ( + IN UINT64 NhltAcpiTableAddress, + IN UINT32 NhltAcpiTableLength, + IN CONST HDAUDIO_HOB *HdAudioConfigHob, + IN CONST PCH_HDAUDIO_DXE_CONFIG *HdAudioDxeConfig + ) +{ + DEBUG ((DEBUG_INFO, "UpdateHdaAcpiData():\n NHLT Address =3D 0x%016x, Le= ngth =3D 0x%08x\n", NhltAcpiTableAddress, NhltAcpiTableLength)); + DEBUG ((DEBUG_INFO, " FeatureMask =3D 0x%08x\n", HdAudioDxeConfig->DspFe= atureMask)); + + mPchNvsAreaProtocol.Area->NHLA =3D NhltAcpiTableAddress; + mPchNvsAreaProtocol.Area->NHLL =3D NhltAcpiTableLength; + mPchNvsAreaProtocol.Area->ADFM =3D HdAudioDxeConfig->DspFeatureMask; + mPchNvsAreaProtocol.Area->SWQ0 =3D HdAudioConfigHob->AudioLinkSndw1 ? 0 = : BIT1; + mPchNvsAreaProtocol.Area->SWQ1 =3D HdAudioConfigHob->AudioLinkSndw2 ? 0 = : BIT1; + mPchNvsAreaProtocol.Area->SWQ2 =3D HdAudioConfigHob->AudioLinkSndw3 ? 0 = : BIT1; + mPchNvsAreaProtocol.Area->SWQ3 =3D HdAudioConfigHob->AudioLinkSndw4 ? 0 = : BIT1; +} + +/** + Initialize and publish NHLT (Non-HDA Link Table), update NVS variables. + + @param[in] *HdAudioConfigHob + @param[in] *HdAudioDxeConfig + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +SetHdaAcpiTable ( + IN CONST HDAUDIO_HOB *HdAudioConfigHob, + IN CONST PCH_HDAUDIO_DXE_CONFIG *HdAudioDxeConfig + ) +{ + NHLT_ACPI_TABLE *NhltTable; + EFI_STATUS Status; + NhltTable =3D NULL; + + Status =3D EFI_SUCCESS; + + if (HdAudioDxeConfig->NhltDefaultFlow =3D=3D TRUE) { + switch (HdAudioDxeConfig->DspEndpointDmic) { + case PchHdaDmic1chArray: + mPchHdaNhltEndpoints[HdaDmicX1].Enable =3D TRUE; + break; + case PchHdaDmic2chArray: + mPchHdaNhltEndpoints[HdaDmicX2].Enable =3D TRUE; + break; + case PchHdaDmic4chArray: + mPchHdaNhltEndpoints[HdaDmicX4].Enable =3D TRUE; + break; + case PchHdaDmicDisabled: + default: + mPchHdaNhltEndpoints[HdaDmicX2].Enable =3D FALSE; + mPchHdaNhltEndpoints[HdaDmicX4].Enable =3D FALSE; + } + + if (HdAudioDxeConfig->DspEndpointBluetooth) { + mPchHdaNhltEndpoints[HdaBtRender].Enable =3D TRUE; + mPchHdaNhltEndpoints[HdaBtCapture].Enable =3D TRUE; + } + + if (HdAudioDxeConfig->DspEndpointI2s) { + mPchHdaNhltEndpoints[HdaI2sRender1].Enable =3D TRUE; + mPchHdaNhltEndpoints[HdaI2sRender2].Enable =3D TRUE; + mPchHdaNhltEndpoints[HdaI2sCapture].Enable =3D TRUE; + } + + Status =3D PublishNhltAcpiTable (); + } + NhltTable =3D LocateNhltAcpiTable (); + if (NhltTable =3D=3D NULL) { + return EFI_LOAD_ERROR; + } + + UpdateHdaAcpiData ((UINT64) (UINTN) NhltTable, (UINT32) (NhltTable->Head= er.Length), HdAudioConfigHob, HdAudioDxeConfig); + + if (IsPchLp () && (PchStepping () < PCH_B0)) { + AllocateAudioDspStolenMemory (); + } + + DEBUG_CODE ( NhltAcpiTableDump (NhltTable); ); + return Status; +} + +/** + Initialize Intel High Definition Audio ACPI Tables + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_LOAD_ERROR ACPI table cannot be installed + @retval EFI_UNSUPPORTED ACPI table not set because DSP is disabl= ed +**/ +EFI_STATUS +PchHdAudioAcpiInit ( + VOID + ) +{ + EFI_STATUS Status; + UINT64 HdaPciBase; + CONST HDAUDIO_HOB *HdAudioConfigHob; + PCH_POLICY_PROTOCOL *PchPolicy; + PCH_HDAUDIO_DXE_CONFIG *HdAudioDxeConfig; + + + DEBUG ((DEBUG_INFO, "PchHdAudioAcpiInit() Start\n")); + + HdAudioConfigHob =3D &mPchConfigHob->HdAudio; + + /// + /// Get PCH Policy Protocol + /// + Status =3D gBS->LocateProtocol (&gPchPolicyProtocolGuid, NULL, (VOID **)= &PchPolicy); + ASSERT_EFI_ERROR (Status); + + /// + /// Get HD Audio DXE Config Block + /// + Status =3D GetConfigBlock ((VOID *)PchPolicy, &gHdAudioDxeConfigGuid, (V= OID *)&HdAudioDxeConfig); + ASSERT_EFI_ERROR (Status); + + HdaPciBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_HDA, + PCI_FUNCTION_NUMBER_PCH_HDA, + 0 + ); + + if ((PciSegmentRead16 (HdaPciBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF)= || (HdAudioConfigHob->DspEnable =3D=3D FALSE)) { + // Do not set ACPI tables if HDAudio is Function disabled or DSP is di= sabled + DEBUG ((DEBUG_INFO, "AudioDSP: Non-HDAudio ACPI Table (NHLT) not set!\= n")); + return EFI_UNSUPPORTED; + } + + Status =3D SetHdaAcpiTable (HdAudioConfigHob, HdAudioDxeConfig); + + DEBUG ((DEBUG_INFO, "PchHdAudioAcpiInit() End - Status =3D %r\n", Status= )); + return Status; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInit.c b= /Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInit.c new file mode 100644 index 0000000000..55f1e086fb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInit.c @@ -0,0 +1,554 @@ +/** @file + This is the Common driver that initializes the Intel PCH. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +#include "PchInit.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Module variables +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_CONFIG_HOB *mPchConfigHob; +GLOBAL_REMOVE_IF_UNREFERENCED SI_CONFIG_HOB_DATA *mSiConfigHobData; + +// +// EFI_EVENT +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_EVENT mHeciEvent; + +/** + Common PchInit Module Entry Point +**/ +VOID +PchInitEntryPointCommon ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS HobPtr; + + DEBUG ((DEBUG_INFO, "PchInitEntryPointCommon() Start\n")); + + // + // Get PCH Config HOB. + // + HobPtr.Guid =3D GetFirstGuidHob (&gPchConfigHobGuid); + ASSERT (HobPtr.Guid !=3D NULL); + mPchConfigHob =3D (PCH_CONFIG_HOB *) GET_GUID_HOB_DATA (HobPtr.Guid); + + // + // Get Silicon Config data HOB + // + HobPtr.Guid =3D GetFirstGuidHob (&gSiConfigHobGuid); + ASSERT (HobPtr.Guid !=3D NULL); + mSiConfigHobData =3D (SI_CONFIG_HOB_DATA *) GET_GUID_HOB_DATA (HobPtr.Gu= id); + + DEBUG ((DEBUG_INFO, "PchInitEntryPointCommon() End\n")); + + return; +} + +/** + Lock SPI register before boot +**/ +VOID +LockSpiConfiguration ( + VOID + ) +{ + UINTN Index; + UINT16 Data16; + UINT16 Data16And; + UINT16 Data16Or; + UINT32 Data32; + UINT32 DlockValue; + UINT64 PciSpiRegBase; + UINT32 PchSpiBar0; + UINT32 Timer; + + PciSpiRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + + // + // Check for SPI controller presence before programming + // + if (PciSegmentRead32 (PciSpiRegBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFF= F) { + return; + } + + // + // Make sure SPI BAR0 has fixed address before writing to boot script. + // The same base address is set in PEI and will be used during resume. + // + PchSpiBar0 =3D PCH_SPI_BASE_ADDRESS; + + PciSegmentAnd8 (PciSpiRegBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_= COMMAND_MEMORY_SPACE); + PciSegmentWrite32 (PciSpiRegBase + R_SPI_CFG_BAR0, PchSpiBar0); + PciSegmentOr8 (PciSpiRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_M= EMORY_SPACE); + + // + // Program the Flash Protection Range Register based on policy + // + DlockValue =3D MmioRead32 (PchSpiBar0 + R_SPI_MEM_DLOCK); + for (Index =3D 0; Index < PCH_FLASH_PROTECTED_RANGES; ++Index) { + if ((mPchConfigHob->ProtectRange[Index].WriteProtectionEnable || + mPchConfigHob->ProtectRange[Index].ReadProtectionEnable) !=3D TRU= E) { + continue; + } + + // + // Proceed to program the register after ensure it is enabled + // + Data32 =3D 0; + Data32 |=3D (mPchConfigHob->ProtectRange[Index].WriteProtectionEnable = =3D=3D TRUE) ? B_SPI_MEM_PRX_WPE : 0; + Data32 |=3D (mPchConfigHob->ProtectRange[Index].ReadProtectionEnable = =3D=3D TRUE) ? B_SPI_MEM_PRX_RPE : 0; + Data32 |=3D ((UINT32) mPchConfigHob->ProtectRange[Index].ProtectedRang= eLimit << N_SPI_MEM_PRX_PRL) & B_SPI_MEM_PRX_PRL_MASK; + Data32 |=3D ((UINT32) mPchConfigHob->ProtectRange[Index].ProtectedRang= eBase << N_SPI_MEM_PRX_PRB) & B_SPI_MEM_PRX_PRB_MASK; + DEBUG ((DEBUG_INFO, "Protected range %d: 0x%08x \n", Index, Data32)); + + DlockValue |=3D (UINT32) (B_SPI_MEM_DLOCK_PR0LOCKDN << Index); + MmioWrite32 ((UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM= _PRX))), Data32); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM_PRX))), + 1, + (VOID *) (UINTN) (PchSpiBar0 + (R_SPI_MEM_PR0 + (Index * S_SPI_MEM_P= RX))) + ); + } + // + // Program DLOCK register + // + MmioWrite32 ((UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK), DlockValue); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK), + 1, + (VOID *) (UINTN) (PchSpiBar0 + R_SPI_MEM_DLOCK) + ); + + /// + /// PCH BIOS Spec Section 3.6 Flash Security Recommendation + /// In PCH SPI controller the BIOS should set the Flash Configuration Lo= ck-Down bit + /// (SPI_BAR0 + 04[15]) at end of post. When set to 1, those Flash Prog= ram Registers + /// that are locked down by this FLOCKDN bit cannot be written. + /// Please refer to the EDS for which program registers are impacted. + /// Additionally BIOS must program SPI_BAR0 + 0x04 BIT11 (WRSDIS) to dis= able Write Status in HW sequencing + /// + + // + // Ensure there is no pending SPI trasaction before setting lock bits + // + Timer =3D 0; + while (MmioRead16 (PchSpiBar0 + R_SPI_MEM_HSFSC) & B_SPI_MEM_HSFSC_SCIP)= { + if (Timer > SPI_WAIT_TIME) { + // + // SPI transaction is pending too long at this point, exit with erro= r. + // + DEBUG ((DEBUG_ERROR, "SPI Cycle timeout\n")); + ASSERT (FALSE); + break; + } + MicroSecondDelay (SPI_WAIT_PERIOD); + Timer +=3D SPI_WAIT_PERIOD; + } + + Data16And =3D B_SPI_MEM_HSFSC_SCIP; + Data16 =3D 0; + S3BootScriptSaveMemPoll ( + S3BootScriptWidthUint16, + PchSpiBar0 + R_SPI_MEM_HSFSC, + &Data16And, + &Data16, + SPI_WAIT_PERIOD, + SPI_WAIT_TIME / SPI_WAIT_PERIOD + ); + + // + // Clear any outstanding status + // + Data16Or =3D B_SPI_MEM_HSFSC_SAF_DLE + | B_SPI_MEM_HSFSC_SAF_ERROR + | B_SPI_MEM_HSFSC_AEL + | B_SPI_MEM_HSFSC_FCERR + | B_SPI_MEM_HSFSC_FDONE; + Data16And =3D 0xFFFF; + MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or); + S3BootScriptSaveMemReadWrite ( + S3BootScriptWidthUint16, + PchSpiBar0 + R_SPI_MEM_HSFSC, + &Data16Or, + &Data16And + ); + + // + // Set WRSDIS + // + Data16Or =3D B_SPI_MEM_HSFSC_WRSDIS; + Data16And =3D 0xFFFF; + MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or); + S3BootScriptSaveMemReadWrite ( + S3BootScriptWidthUint16, + PchSpiBar0 + R_SPI_MEM_HSFSC, + &Data16Or, + &Data16And + ); + + // + // Set FLOCKDN + // + Data16Or =3D B_SPI_MEM_HSFSC_FLOCKDN; + Data16And =3D 0xFFFF; + MmioAndThenOr16 (PchSpiBar0 + R_SPI_MEM_HSFSC, Data16And, Data16Or); + S3BootScriptSaveMemReadWrite ( + S3BootScriptWidthUint16, + PchSpiBar0 + R_SPI_MEM_HSFSC, + &Data16Or, + &Data16And + ); + + /// + /// SPI Flash Programming Guide Section 5.5.2 Vendor Component Lock + /// It is strongly recommended that BIOS sets the Vendor Component Lock = (VCL) bits. VCL applies + /// the lock to both VSCC0 and VSCC1 even if VSCC0 is not used. Without = the VCL bits set, it is + /// possible to make Host/GbE VSCC register(s) changes in that can cause= undesired host and + /// integrated GbE Serial Flash functionality. + /// + MmioOr32 ((UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0), B_SPI_MEM_SFDP0_= VSCC0_VCL); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0), + 1, + (VOID *) (UINTN) (PchSpiBar0 + R_SPI_MEM_SFDP0_VSCC0) + ); +} + +/** + Process all the lock downs +**/ +VOID +ProcessAllLocks ( + VOID + ) +{ + UINT8 Data8; + UINT16 Data16And; + UINT16 Data16Or; + UINT32 Data32And; + UINT32 Data32Or; + UINT64 PciLpcRegBase; + UINT16 TcoBase; + UINT64 PciSpiRegBase; + + PciLpcRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + PciSpiRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + + PchTcoBaseGet (&TcoBase); + + // + // Lock function disable (ST and NST PG) register fields. + // + PmcLockFunctionDisableConfigWithS3BootScript (); + + /// + /// PCH BWG Additional PCH DMI and OP-DMI Programming Steps + /// Lock DMI. + /// + PchDmiSetLockWithS3BootScript (); + + // + // Lock SPI register before boot. + // + LockSpiConfiguration (); + + /// + /// Additional Power Management Programming + /// Step 3 + /// Lock configuration after stretch and ACPI base programming completed. + /// + PmcLockSlpSxStretchingPolicyWithS3BootScript (); + + // + // Set BiosLock. + // + if (mPchConfigHob->LockDown.BiosLock =3D=3D TRUE) { + BiosLockEnable (); + } + + /// + /// PCH BIOS Spec Section 3.6 Flash Security Recommendation + /// BIOS also needs to set the BIOS Interface Lock Down bit in multiple = locations + /// (PCR[DMI] + 274Ch[0], LPC/eSPI PCI offset DCh[7] and SPI PCI offset = DCh[7]). + /// Setting these bits will prevent writes to the Top Swap bit (under th= eir respective locations) + /// and the Boot BIOS Straps. Enabling this bit will mitigate malicious = software + /// attempts to replace the system BIOS option ROM with its own code. + /// + if (mPchConfigHob->LockDown.BiosInterface =3D=3D TRUE) { + // + // LPC + // + PciSegmentOr8 ((UINT64) (PciLpcRegBase + R_LPC_CFG_BC), (UINT32) B_LPC= _CFG_BC_BILD); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint8, + PcdGet64 (PcdPciExpressBaseAddress) + PciLpcRegBase + R_LPC_CFG_BC, + 1, + (VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + PciLpcRegBas= e + R_LPC_CFG_BC) + ); + + // + // Reads back for posted write to take effect + // + Data8 =3D PciSegmentRead8 ((UINTN) (PciLpcRegBase + R_LPC_CFG_BC)); + S3BootScriptSaveMemPoll ( + S3BootScriptWidthUint8, + PcdGet64 (PcdPciExpressBaseAddress) + PciLpcRegBase + R_LPC_CFG_BC, + &Data8, // BitMask + &Data8, // BitValue + 1, // Duration + 1 // LoopTimes + ); + + // + // SPI + // + PciSegmentOr8 ((UINT64) (PciSpiRegBase + R_SPI_CFG_BC), (UINT32) B_SPI= _CFG_BC_BILD); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint8, + PcdGet64 (PcdPciExpressBaseAddress) + PciSpiRegBase + R_SPI_CFG_BC, + 1, + (VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + PciSpiRegBas= e + R_SPI_CFG_BC) + ); + + // + // Reads back for posted write to take effect + // + Data8 =3D PciSegmentRead8 ((UINT64) (PciSpiRegBase + R_SPI_CFG_BC)); + S3BootScriptSaveMemPoll ( + S3BootScriptWidthUint8, + PcdGet64 (PcdPciExpressBaseAddress) + PciSpiRegBase + R_SPI_CFG_BC, + &Data8, // BitMask + &Data8, // BitValue + 1, // Duration + 1 // LoopTimes + ); + + /// + /// Set BIOS interface Lock-Down + /// + PchDmiSetBiosLockDownWithS3BootScript (); + } + + /// + /// PCH BIOS Spec on using RTC RAM + /// Regardless of BUC.TS being updated or not, BIOS must set RC.BILD bit= PCR[RTC] + 3400h[31] before exit + /// For Data integrity protection, set RTC Memory locks (Upper 128 Byte = Lock and + /// Lower 128 Byte Lock) at PCR[RTC] + 3400h[4] and PCR[RTC] + 3400h[3]. + /// Note once locked bytes 0x38 - 0x3F in each of the Upper and Lower By= te blocks, respectively, + /// cannot be unlocked until next reset. + /// + Data32And =3D 0xFFFFFFFF; + Data32Or =3D 0x0; + + if (mPchConfigHob->LockDown.BiosInterface =3D=3D TRUE) { + Data32Or =3D B_RTC_PCR_CONF_BILD; + } + if (mPchConfigHob->LockDown.RtcMemoryLock =3D=3D TRUE) { + Data32Or |=3D (B_RTC_PCR_CONF_UCMOS_LOCK | B_RTC_PCR_CONF_LCMOS_LOCK); + } + PchPcrAndThenOr32 ( + PID_RTC_HOST, R_RTC_PCR_CONF, + Data32And, + Data32Or + ); + PCH_PCR_BOOT_SCRIPT_READ_WRITE ( + S3BootScriptWidthUint32, + PID_RTC_HOST, R_RTC_PCR_CONF, + &Data32Or, + &Data32And + ); + + /// + /// Remove access to RTC PCRs + /// + Data32And =3D (UINT32)~(BIT0); + Data32Or =3D 0; + PchPcrAndThenOr32 ( + PID_RTC_HOST, R_RTC_PCR_PG1_AC_LO, + Data32And, + Data32Or + ); + PCH_PCR_BOOT_SCRIPT_READ_WRITE ( + S3BootScriptWidthUint32, + PID_RTC_HOST, R_RTC_PCR_PG1_AC_LO, + &Data32Or, + &Data32And + ); + PchPcrAndThenOr32 ( + PID_RTC_HOST, R_RTC_PCR_PG1_CP_LO, + Data32And, + Data32Or + ); + PCH_PCR_BOOT_SCRIPT_READ_WRITE ( + S3BootScriptWidthUint32, + PID_RTC_HOST, R_RTC_PCR_PG1_CP_LO, + &Data32Or, + &Data32And + ); + + // + // Lock Down TCO + // + Data16And =3D 0xFFFF; + Data16Or =3D B_TCO_IO_TCO1_CNT_LOCK; + IoOr16 (TcoBase + R_TCO_IO_TCO1_CNT, Data16Or); + S3BootScriptSaveIoReadWrite ( + S3BootScriptWidthUint16, + (UINTN) (TcoBase + R_TCO_IO_TCO1_CNT), + &Data16Or, // Data to be ORed + &Data16And // Data to be ANDed + ); + + /// + /// PCH BIOS Spec Section 5.15.1 Additional Chipset Initialization + /// Step 1 + /// Lock PMC Set Strap Message Interface + /// + PmcLockSetStrapMsgInterfaceWithS3BootScript (); + // + // Lock Down PMC + // + PmcLockWithS3BootScript (); +} + +/** + Set eSPI BME bit +**/ +VOID +ConfigureEspiBme ( + VOID + ) +{ + UINT64 EspiPciBase; + + EspiPciBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + if (PciSegmentRead16 (EspiPciBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF)= { + return; + } + if ((PciSegmentRead32 (EspiPciBase + R_ESPI_CFG_PCBC) & B_ESPI_CFG_PCBC_= ESPI_EN) =3D=3D 0) { + return; + } + + // + // Refer to PCH BWG. + // To enable eSPI bus mastering BIOS must enable BME in eSPI controller + // and also set BME bit in the respective slave devices through Configur= ation + // and Capabilities register of each slave using Get_Configuration and S= et_Configuration functionality. + // + // NOTE: The setting is also done in PEI, but might be cleared by PCI bu= s during PCI enumeration. + // Therefore, reeable it after PCI enumeration done. + // + if (mPchConfigHob->Espi.BmeMasterSlaveEnabled =3D=3D TRUE) { + PciSegmentOr8 (EspiPciBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_BUS_M= ASTER); + } +} + +/** + Common PCH initialization before Boot Sript Table is closed + +**/ +VOID +PchOnPciEnumCompleteCommon ( + VOID + ) +{ + UINT32 Data32Or; + UINT32 Data32And; + BOOLEAN ResetStatus; + + DEBUG ((DEBUG_INFO, "PchOnPciEnumCompleteCommon() Start\n")); + + if (SiScheduleResetIsRequired ()) { + ResetStatus =3D SiScheduleResetPerformReset (); + ASSERT (!ResetStatus); + } + + ProcessAllLocks (); + + // + // Perform remaining configuration for PCH SATA on End of DXE + // + ConfigurePchSataOnEndOfDxe (); + // + // PSTHCTL (0xD00h[2]) =3D 1, PSTH IOSF Primary Trunk Clock Gating Enabl= e (PSTHIOSFPTCGE) + // + Data32And =3D 0xFFFFFFFF; + Data32Or =3D B_PSTH_PCR_PSTHIOSFPTCGE; + PchPcrAndThenOr32 (PID_PSTH, R_PSTH_PCR_PSTHCTL, Data32And, Data32Or); + PCH_PCR_BOOT_SCRIPT_READ_WRITE ( + S3BootScriptWidthUint32, + PID_PSTH, R_PSTH_PCR_PSTHCTL, + &Data32Or, + &Data32And + ); + + // + // Set eSPI BME after PCI enumeration + // + ConfigureEspiBme (); + + /// + /// Clear Global Reset Status, Power Failure and Host Reset Status bits + /// + PmcClearGlobalResetStatus (); + PmcClearPowerFailureStatus (); + PmcClearHostResetStatus (); + + DEBUG ((DEBUG_INFO, "PchOnPciEnumCompleteCommon() End\n")); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxe.= c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxe.c new file mode 100644 index 0000000000..b106c849e9 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitDxe.c @@ -0,0 +1,382 @@ +/** @file + This is the Uefi driver that initializes the Intel PCH. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +#include "PchInit.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_HANDLE mImageHandle; +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPcieIoTrapAddress; + +VOID +EFIAPI +PchOnBootToOs ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +VOID +EFIAPI +PchOnExitBootServices ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +VOID +EFIAPI +PchOnReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + Process all the lock downs +**/ +VOID +ProcessSmiLocks ( + VOID + ) +{ + UINT32 Data32And; + UINT32 Data32Or; + UINT16 ABase; + + /// + /// PCH BIOS Spec Section 3.6 Flash Security Recommendation + /// BIOS needs to enables SMI_LOCK (PMC PCI offset A0h[4] =3D 1b) which = prevent writes + /// to the Global SMI Enable bit (GLB_SMI_EN ABASE + 30h[0]). Enabling t= his bit will + /// mitigate malicious software attempts to gain system management mode = privileges. + /// + if (mPchConfigHob->LockDown.GlobalSmi =3D=3D TRUE) { + /// + /// Save Global SMI Enable bit setting before BIOS enables SMI_LOCK du= ring S3 resume + /// + ABase =3D PmcGetAcpiBase (); + Data32Or =3D IoRead32 ((UINTN) (ABase + R_ACPI_IO_SMI_EN)); + if ((Data32Or & B_ACPI_IO_SMI_EN_GBL_SMI) !=3D 0) { + Data32And =3D 0xFFFFFFFF; + Data32Or |=3D B_ACPI_IO_SMI_EN_GBL_SMI; + S3BootScriptSaveIoReadWrite ( + S3BootScriptWidthUint32, + (UINTN) (ABase + R_ACPI_IO_SMI_EN), + &Data32Or, // Data to be ORed + &Data32And // Data to be ANDed + ); + } + PmcLockSmiWithS3BootScript (); + } +} + +/** + Do PCIE power management while resume from S3 +**/ +VOID +ReconfigurePciePowerManagementForS3 ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 Data32; + PCH_PCIE_IOTRAP_PROTOCOL *PchPcieIoTrapProtocol; + + Status =3D gBS->LocateProtocol (&gPchPcieIoTrapProtocolGuid, NULL, (VOID= **) &PchPcieIoTrapProtocol); + if (EFI_ERROR (Status)) { + return; + } + mPcieIoTrapAddress =3D PchPcieIoTrapProtocol->PcieTrapAddress; + DEBUG ((DEBUG_INFO, "PcieIoTrapAddress: %0x\n", mPcieIoTrapAddress)); + + if (mPcieIoTrapAddress !=3D 0) { + // + // Save PCH PCIE IoTrap address to re-config PCIE power management set= ting after resume from S3 + // + Data32 =3D PciePmTrap; + S3BootScriptSaveIoWrite ( + S3BootScriptWidthUint32, + (UINTN) (mPcieIoTrapAddress), + 1, + &Data32 + ); + } else { + ASSERT (FALSE); + } +} + +/** + This is the callback function for PCI ENUMERATION COMPLETE. +**/ +VOID +EFIAPI +PchOnPciEnumComplete ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + VOID *ProtocolPointer; + UINT64 ThermalPciBase; + + /// + /// Check if this is first time called by EfiCreateProtocolNotifyEvent()= or not, + /// if it is, we will skip it until real event is triggered + /// + Status =3D gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid,= NULL, (VOID **) &ProtocolPointer); + if (EFI_SUCCESS !=3D Status) { + return; + } + gBS->CloseEvent (Event); + + // + // Enable Thermal MSE + // + ThermalPciBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_THERMAL, + PCI_FUNCTION_NUMBER_PCH_THERMAL, + 0 + ); + if (PciSegmentRead16 (ThermalPciBase + PCI_VENDOR_ID_OFFSET) !=3D 0xFFFF= ) { + if (((PciSegmentRead32 (ThermalPciBase + R_THERMAL_CFG_MEM_TBAR) & B_T= HERMAL_CFG_MEM_TBAR_MASK) !=3D 0) || + ((PciSegmentRead32 (ThermalPciBase + R_THERMAL_CFG_MEM_TBARH) !=3D= 0))) { + PciSegmentOr8 (ThermalPciBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_= MEMORY_SPACE); + } + } + + ReconfigurePciePowerManagementForS3 (); + ProcessSmiLocks (); +#ifndef FSP_WRAPPER_FLAG + PchOnPciEnumCompleteCommon (); +#endif + ConfigureSerialIoAtS3Resume (); +} + +/** + Register callback functions for PCH DXE. +**/ +VOID +PchRegisterNotifications ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT LegacyBootEvent; + EFI_EVENT ExitBootServicesEvent; + VOID *Registration; + + /// + /// Create PCI Enumeration Completed callback for PCH + /// + EfiCreateProtocolNotifyEvent ( + &gEfiPciEnumerationCompleteProtocolGuid, + TPL_CALLBACK, + PchOnPciEnumComplete, + NULL, + &Registration + ); + + // + // Create events for PCH to do the task before ExitBootServices/LegacyBo= ot. + // It is guaranteed that only one of two events below will be signalled + // + Status =3D gBS->CreateEvent ( + EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_CALLBACK, + PchOnExitBootServices, + NULL, + &ExitBootServicesEvent + ); + ASSERT_EFI_ERROR (Status); + + Status =3D EfiCreateEventLegacyBootEx ( + TPL_CALLBACK, + PchOnBootToOs, + NULL, + &LegacyBootEvent + ); + ASSERT_EFI_ERROR (Status); +} + +/** + Initialize the PCH device according to the PCH Policy HOB + and install PCH info instance. +**/ +VOID +InitializePchDevice ( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "InitializePchDevice() Start\n")); + + DEBUG ((DEBUG_INFO, "InitializePchDevice() End\n")); +} +/** + PchInit DXE Module Entry Point\n + - Introduction\n + The PchInit module is a DXE driver that initializes the Intel Platfo= rm Controller Hub + following the PCH BIOS specification and EDS requirements and recomm= endations. It consumes + the PCH_POLICY_HOB SI_POLICY_HOB for expected configurations per pol= icy. + This is the standard EFI driver point that detects whether there is = an supported PCH in + the system and if so, initializes the chipset. + + - Details\n + This module is required for initializing the Intel Platform Controller= Hub to + follow the PCH BIOS specification and EDS. + This includes some initialization sequences, enabling and disabling PC= H devices, + configuring clock gating, RST PCIe Storage Remapping, SATA controller,= ASPM of PCIE devices. Right before end of DXE, + it's responsible to lock down registers for security requirement. + + - @pre + - PCH PCR base address configured + - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + - This is to ensure that PCI MMIO and IO resource has been prepared = and available for this driver to allocate. + + - @result + - Publishes the @link _PCH_INFO_PROTOCOL PCH_INFO_PROTOCOL @endlink + - Publishes the @link _PCH_EMMC_TUNING_PROTOCOL PCH_EMMC_TUNING_PROTOC= OL @endlink + + - References\n + - @link _PCH_POLICY PCH_POLICY_HOB @endlink. + - @link _SI_POLICY_STRUCT SI_POLICY_HOB @endlink. + + - Integration Checklists\n + - Verify prerequisites are met. Porting Recommendations. + - No modification of this module should be necessary + - Any modification of this module should follow the PCH BIOS Specifica= tion and EDS + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +PchInitEntryPointDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "PchInitEntryPointDxe() Start\n")); + + mImageHandle =3D ImageHandle; + + PchInitEntryPointCommon (); + + InitializePchDevice (); + + Status =3D PchAcpiInit (ImageHandle); + + CreateSerialIoHandles (); + + PchRegisterNotifications (); + + DEBUG ((DEBUG_INFO, "PchInitEntryPointDxe() End\n")); + + return Status; +} + +/** + PCH initialization before ExitBootServices / LegacyBoot events + Useful for operations which must happen later than at EndOfPost event + + @param[in] Event A pointer to the Event that triggered th= e callback. + @param[in] Context A pointer to private data registered wit= h the callback function. +**/ +VOID +EFIAPI +PchOnBootToOs ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + /// + /// Closed the event to avoid call twice + /// + if (Event !=3D NULL) { + gBS->CloseEvent (Event); + } + + ConfigureSerialIoAtBoot (); + + return; +} + +/** + PCH initialization on ExitBootService. This event is used if only ExitBo= otService is used + and not in legacy boot + + @param[in] Event A pointer to the Event that triggered th= e callback. + @param[in] Context A pointer to private data registered wit= h the callback function. + + @retval None +**/ +VOID +EFIAPI +PchOnExitBootServices ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + PchOnBootToOs (NULL, NULL); + + return; +} + +/** + PCH initialization before boot to OS + + @param[in] Event A pointer to the Event that triggered th= e callback. + @param[in] Context A pointer to private data registered wit= h the callback function. +**/ +VOID +EFIAPI +PchOnReadyToBoot ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + DEBUG ((DEBUG_INFO, "Uefi PchOnReadyToBoot() Start\n")); + + if (Event !=3D NULL) { + gBS->CloseEvent (Event); + } + + // + // Trigger an Iotrap SMI to config PCIE power management setting after P= CI enumrate is done + // + if (mPcieIoTrapAddress !=3D 0) { + IoWrite32 ((UINTN) mPcieIoTrapAddress, PciePmTrap); + } else { + ASSERT (FALSE); + } + + DEBUG ((DEBUG_INFO, "Uefi PchOnReadyToBoot() End\n")); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitFsp.= c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitFsp.c new file mode 100644 index 0000000000..15fe4628fb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchInitFsp.c @@ -0,0 +1,85 @@ +/** @file + This is the FSP driver that initializes the Intel PCH. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include "PchInit.h" + +EFI_STATUS +EFIAPI +PchOnPciEnumCompleteFsp ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +STATIC +EFI_PEI_NOTIFY_DESCRIPTOR mPchOnPciEnumCompleteNotifyList[] =3D { + { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERM= INATE_LIST), + &gEfiPciEnumerationCompleteProtocolGuid, + PchOnPciEnumCompleteFsp + } +}; + +/** + FSP PchInit Module Entry Point for FSP\n + + @param[in] FileHandle PEIM's file handle + @param[in] PeiServices An indirect pointer to the EFI_PEI_SERVICES t= able published by the PEI Foundation + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +PchInitEntryPointFsp ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "PchInitEntryPointFsp() Start\n")); + + PchInitEntryPointCommon (); + + Status =3D PeiServicesNotifyPpi (mPchOnPciEnumCompleteNotifyList); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "PchInitEntryPointFsp() End\n")); + + return Status; +} + +/** + Fsp PCH initialization on PCI enumeration complete + + @param[in] PeiServices An indirect pointer to the EFI_PEI_SERVICE= S table published by the PEI Foundation + @param[in] NotifyDescriptor Address of the notification descriptor dat= a structure. + @param[in] Ppi Address of the PPI that was installed. + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +PchOnPciEnumCompleteFsp ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + DEBUG ((DEBUG_INFO, "PchOnPciEnumCompleteFsp() Start\n")); + + PchOnPciEnumCompleteCommon (); + + DEBUG ((DEBUG_INFO, "PchOnPciEnumCompleteFsp() End\n")); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSata.c b= /Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSata.c new file mode 100644 index 0000000000..6e30280fa7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSata.c @@ -0,0 +1,89 @@ +/** @file + Perform related functions for PCH Sata in DXE phase + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +#include "PchInit.h" +#include +#include + +/** + Perform the remaining configuration on PCH SATA to perform device detect= ion, + then set the SATA SPD and PxE corresponding, and set the Register Lock o= n PCH SATA + + @retval None +**/ +VOID +ConfigurePchSataOnEndOfDxe ( + VOID + ) +{ + UINT64 PciSataRegBase; + UINT16 SataPortsEnabled; + UINT32 DwordReg; + UINTN Index; + UINT32 SataCtrlIndex; + + for (SataCtrlIndex =3D 0; SataCtrlIndex < GetPchMaxSataControllerNum ();= SataCtrlIndex++) { + /// + /// SATA PCS: Enable the port in any of below condition: + /// i.) Hot plug is enabled + /// ii.) A device is attached + /// iii.) Test mode is enabled + /// iv.) Configured as eSATA port + /// + PciSataRegBase =3D GetSataRegBase (SataCtrlIndex); + SataPortsEnabled =3D 0; + + DwordReg =3D PciSegmentRead32 (PciSataRegBase + R_SATA_CFG_PCS); + for (Index =3D 0; Index < GetPchMaxSataPortNum (SataCtrlIndex); Index+= +) { + if ((mPchConfigHob->Sata[SataCtrlIndex].PortSettings[Index].HotPlug = =3D=3D TRUE) || + (DwordReg & (B_SATA_CFG_PCS_P0P << Index)) || + (mPchConfigHob->Sata[SataCtrlIndex].TestMode =3D=3D TRUE) || + (mPchConfigHob->Sata[SataCtrlIndex].PortSettings[Index].Extern= al =3D=3D TRUE)) { + SataPortsEnabled |=3D (mPchConfigHob->Sata[SataCtrlIndex].PortSe= ttings[Index].Enable << Index); + } + } + + /// + /// Set MAP."Sata PortX Disable", SATA PCI offset 90h[23:16] to 1b if = SATA Port 0/1/2/3/4/5/6/7 is disabled + /// + PciSegmentOr32 (PciSataRegBase + R_SATA_CFG_MAP, (~SataPortsEnabled <<= N_SATA_CFG_MAP_SPD)); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + PcdGet64 (PcdPciExpressBaseAddress) + PciSataRegBase + R_SATA_CFG_MA= P, + 1, + (VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + PciSataRegBa= se + R_SATA_CFG_MAP) + ); + + /// + /// Program PCS "Port X Enabled", SATA PCI offset 94h[7:0] =3D Port 0~= 7 Enabled bit as per SataPortsEnabled value. + /// + PciSegmentOr16 (PciSataRegBase + R_SATA_CFG_PCS, SataPortsEnabled); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint16, + PcdGet64 (PcdPciExpressBaseAddress) + PciSataRegBase + R_SATA_CFG_PC= S, + 1, + (VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + PciSataRegBa= se + R_SATA_CFG_PCS) + ); + + /// + /// Step 14 + /// Program SATA PCI offset 9Ch [31] to 1b + /// + PciSegmentOr32 ((UINTN) (PciSataRegBase + R_SATA_CFG_SATAGC), BIT31); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + PcdGet64 (PcdPciExpressBaseAddress) + PciSataRegBase + R_SATA_CFG_SA= TAGC, + 1, + (VOID *) (UINTN) (PcdGet64 (PcdPciExpressBaseAddress) + PciSataRegBa= se + R_SATA_CFG_SATAGC) + ); + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSerialIo= .c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSerialIo.c new file mode 100644 index 0000000000..d0f4b4fa56 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSerialIo.c @@ -0,0 +1,57 @@ +/** @file + Initializes Serial IO Controllers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include "PchInit.h" +#include +#include +#include + +/** + Puts all SerialIo controllers (except UARTs in debug mode) in D3 + Clears MemoryEnable for all PCI-mode controllers +**/ +EFI_STATUS +ConfigureSerialIoAtBoot ( + VOID + ) +{ + PCH_SERIAL_IO_CONTROLLER Index; + UINTN PciCfgBase; + + for (Index =3D 0; Index < PchSerialIoIndexMax; Index++) { + if (mPchConfigHob->SerialIo.DevMode[Index] =3D=3D PchSerialIoDisabled)= { + if (IsSerialIoFunctionZero (Index)) { + if (IsSerialIoDeviceEnabled (GetSerialIoDeviceNumber (Index), GetS= erialIoFunctionNumber (Index))) { + PciCfgBase =3D FindSerialIoBar (Index,1); + MmioOr32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, B_SERIAL_IO= _CFG_PME_CTRL_STS_PWR_ST); + } + } + continue; + } + if ((Index >=3D PchSerialIoIndexUart0) && + (mPchConfigHob->SerialIo.EnableDebugUartAfterPost) && + (mPchConfigHob->SerialIo.DebugUartNumber =3D=3D (UINT32) (Index - = PchSerialIoIndexUart0))) { + continue; + } + PciCfgBase =3D FindSerialIoBar (Index,1); + MmioOr32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, B_SERIAL_IO_CFG_P= ME_CTRL_STS_PWR_ST); + MmioRead32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS); + if (mPchConfigHob->SerialIo.DevMode[Index] =3D=3D PchSerialIoPci) { + MmioAnd32 (PciCfgBase + PCI_COMMAND_OFFSET, (UINT32)~(EFI_PCI_COMMAN= D_MEMORY_SPACE | EFI_PCI_COMMAND_BUS_MASTER) ); + if (mPchConfigHob->SerialIo.DebugUartNumber =3D=3D (UINT32) (Index -= PchSerialIoIndexUart0)) { + continue; + } + MmioWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_LOW, 0); + MmioWrite32 (PciCfgBase + R_SERIAL_IO_CFG_BAR0_HIGH, 0); + } + } + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSerialIo= Dxe.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSerialIoDxe.c new file mode 100644 index 0000000000..5563d82076 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Dxe/PchSerialIoDxe.c @@ -0,0 +1,156 @@ +/** @file + Initializes Serial IO Controllers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +#include "PchInit.h" +#include +#include +#include +#include + +typedef struct { + ACPI_HID_DEVICE_PATH RootPort; + ACPI_EXTENDED_HID_DEVICE_PATH AcpiDev; + CHAR8 HidString[8]; + CHAR8 UidString; + CHAR8 CidString; + EFI_DEVICE_PATH_PROTOCOL End; +} SERIALIO_DEVICE_PATH; + +#define gPciRootBridge {{ACPI_DEVICE_PATH, ACPI_DP, {(UINT8)(sizeof(ACPI_H= ID_DEVICE_PATH)), 0}}, EISA_PNP_ID (0x0A03), 0} +#define gAcpiDev {{ACPI_DEVICE_PATH,ACPI_EXTENDED_DP,{(UINT8)(sizeof(ACPI_= EXTENDED_HID_DEVICE_PATH)+SERIALIO_TOTAL_ID_LENGTH),0}},0,0,0} +#define gEndEntire {END_DEVICE_PATH_TYPE,END_ENTIRE_DEVICE_PATH_SUBTYPE,{E= ND_DEVICE_PATH_LENGTH,0}} + +GLOBAL_REMOVE_IF_UNREFERENCED SERIALIO_DEVICE_PATH gSerialIoPath =3D { + gPciRootBridge, + gAcpiDev, + "\0\0\0\0\0\0\0", + '\0', + '\0', + gEndEntire +}; + +/** +Mark memory used by SerialIo devices in ACPI mode as allocated + +@retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +AllocateSerialIoMemory ( + VOID + ) +{ + PCH_SERIAL_IO_CONTROLLER i; + UINT8 BarNumber; + UINTN Bar; + EFI_STATUS Status; + + for (i=3D0; iSerialIo.DevMode[i] =3D=3D PchSerialIoHidden || + mPchConfigHob->SerialIo.DevMode[i] =3D=3D PchSerialIoAcpi) { + for (BarNumber =3D 0; BarNumber<=3D1; BarNumber++) { + Bar =3D FindSerialIoBar (i,BarNumber); + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeReserved, + Bar, + V_SERIAL_IO_CFG_BAR_SIZE, + 0 + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + Status =3D gDS->AllocateMemorySpace ( + EfiGcdAllocateAddress, + EfiGcdMemoryTypeReserved, + N_SERIAL_IO_CFG_BAR_ALIGNMENT, + V_SERIAL_IO_CFG_BAR_SIZE, + &Bar, + mImageHandle, + NULL + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + } + } + } + return EFI_SUCCESS; +} + +VOID +CreateSerialIoHandles ( + VOID + ) +{ + EFI_HANDLE NewHandle; + EFI_DEVICE_PATH_PROTOCOL *NewPath; + UINT32 Controller; + + for (Controller =3D 0; Controller < PchSerialIoIndexMax; Controller++) { + if (mPchConfigHob->SerialIo.DevMode[Controller] =3D=3D PchSerialIoAcpi= ) { + NewHandle =3D NULL; + CopyMem (gSerialIoPath.HidString, GetSerialIoAcpiHid (Controller), S= ERIALIO_HID_LENGTH); + NewPath =3D DuplicateDevicePath ((EFI_DEVICE_PATH_PROTOCOL*)&gSerial= IoPath); + gBS->InstallMultipleProtocolInterfaces ( + &NewHandle, + &gEfiDevicePathProtocolGuid, + NewPath, + NULL ); + } + } +} + +/** + Puts all SerialIo controllers (except UARTs in debug mode) in D3. + Clears MemoryEnable for all PCI-mode controllers on S3 resume +**/ +VOID +ConfigureSerialIoAtS3Resume ( + VOID + ) +{ + PCH_SERIAL_IO_CONTROLLER Index; + UINTN PciCfgBase; + UINT32 Data32; + + for (Index =3D 0; Index < PchSerialIoIndexMax; Index++) { + if (mPchConfigHob->SerialIo.DevMode[Index] =3D=3D PchSerialIoDisabled)= { + if (IsSerialIoFunctionZero (Index)) { + if (IsSerialIoDeviceEnabled (GetSerialIoDeviceNumber (Index), GetS= erialIoFunctionNumber (Index))) { + PciCfgBase =3D FindSerialIoBar (Index,1); + Data32 =3D MmioRead32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS= ); + Data32 |=3D B_SERIAL_IO_CFG_PME_CTRL_STS_PWR_ST; + S3BootScriptSaveMemWrite (S3BootScriptWidthUint32, PciCfgBase + = R_SERIAL_IO_CFG_PME_CTRL_STS, 1, &Data32); + } + } + continue; + } + if ((Index >=3D PchSerialIoIndexUart0) && + (mPchConfigHob->SerialIo.EnableDebugUartAfterPost) && + (mPchConfigHob->SerialIo.DebugUartNumber =3D=3D (UINT32) (Index - = PchSerialIoIndexUart0))) { + continue; + } + PciCfgBase =3D FindSerialIoBar (Index,1); + Data32 =3D MmioRead32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS); + Data32 |=3D B_SERIAL_IO_CFG_PME_CTRL_STS_PWR_ST; + S3BootScriptSaveMemWrite (S3BootScriptWidthUint32, PciCfgBase + R_SERI= AL_IO_CFG_PME_CTRL_STS, 1, &Data32); + if (mPchConfigHob->SerialIo.DevMode[Index] =3D=3D PchSerialIoPci) { + Data32 =3D MmioRead32 (PciCfgBase + PCI_COMMAND_OFFSET); + Data32 &=3D (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND= _BUS_MASTER); + S3BootScriptSaveMemWrite (S3BootScriptWidthUint32, PciCfgBase + PCI_= COMMAND_OFFSET, 1, &Data32); + } + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchBiosWrit= eProtect.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchBiosWrit= eProtect.c new file mode 100644 index 0000000000..7fe1567c9f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchBiosWriteProtec= t.c @@ -0,0 +1,156 @@ +/** @file + PCH BIOS Write Protect Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchInitSmm.h" +#include +#include +#include + +// +// Global variables +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_TCO_SMI_DISPATCH_PROTOCOL *mPchTcoSm= iDispatchProtocol; +GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mSpiRegBas= e; +GLOBAL_REMOVE_IF_UNREFERENCED PCH_ESPI_SMI_DISPATCH_PROTOCOL *mEspiSmmD= ispatchProtocol; +GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mLpcRegBas= e; + +/** + This hardware SMI handler will be run every time the BIOS Write Enable b= it is set. + + @param[in] DispatchHandle Not used + +**/ +VOID +EFIAPI +PchSpiBiosWpCallback ( + IN EFI_HANDLE DispatchHandle + ) +{ + // + // Disable BIOSWE bit to protect BIOS + // + PciSegmentAnd8 ((UINTN) (mSpiRegBase + R_SPI_CFG_BC), (UINT8) ~B_SPI_CFG= _BC_WPD); +} + +/** + This hardware SMI handler will be run every time the BIOS Write Enable b= it is set. + + @param[in] DispatchHandle Not used + +**/ +VOID +EFIAPI +PchLpcBiosWpCallback ( + IN EFI_HANDLE DispatchHandle + ) +{ + // + // Disable BIOSWE bit to protect BIOS + // + PciSegmentAnd8 ((UINTN) (mLpcRegBase + R_LPC_CFG_BC), (UINT8) ~B_LPC_CFG= _BC_WPD); +} + +/** + Entry point for Pch Bios Write Protect driver. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. +**/ +EFI_STATUS +EFIAPI +InstallPchBiosWriteProtect ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + DEBUG ((DEBUG_INFO, "InstallPchBiosWriteProtect()\n")); + + if (mPchConfigHob->LockDown.BiosLock !=3D TRUE) { + return EFI_SUCCESS; + } + + mSpiRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + + mLpcRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + DEBUG ((DEBUG_INFO, "Installing BIOS Write Protect SMI handler\n")); + // + // Get the PCH TCO SMM dispatch protocol + // + mPchTcoSmiDispatchProtocol =3D NULL; + Status =3D gSmst->SmmLocateProtocol (&gPchTcoSmiDispatchProtocolGuid, NU= LL, (VOID **) &mPchTcoSmiDispatchProtocol); + ASSERT_EFI_ERROR (Status); + // + // Always register an SPI BiosWp callback function to handle TCO BIOSWR = SMI + // NOTE: No matter the BIOS resides behind SPI or not, it needs to handl= e the SPI BIOS WP SMI + // to avoid SMI deadloop on SPI WPD write. + // + Handle =3D NULL; + Status =3D mPchTcoSmiDispatchProtocol->SpiBiosWpRegister ( + mPchTcoSmiDispatchProtocol, + PchSpiBiosWpCallback, + &Handle + ); + ASSERT_EFI_ERROR (Status); + + // + // Always register an LPC/eSPI BiosWp callback function to handle TCO BI= OSWR SMI + // NOTE: No matter the BIOS resides behind LPC/eSPI or not, it needs to = handle the BIOS WP SMI + // to avoid SMI deadloop on LPC/eSPI WPD write. + // + if (IsEspiEnabled ()) { + // + // Get the PCH ESPI SMM dispatch protocol + // + mEspiSmmDispatchProtocol =3D NULL; + Status =3D gSmst->SmmLocateProtocol (&gPchEspiSmiDispatchProtocolGuid,= NULL, (VOID **) &mEspiSmmDispatchProtocol); + ASSERT_EFI_ERROR (Status); + + // + // Register an ESpiBiosWp callback function to handle BIOSWR SMI + // + Handle =3D NULL; + Status =3D mEspiSmmDispatchProtocol->BiosWrProtectRegister ( + mEspiSmmDispatchProtocol, + PchLpcBiosWpCallback, + &Handle + ); + ASSERT_EFI_ERROR (Status); + } else { + // + // Register an LPC BiosWp callback function to handle TCO BIOSWR SMI + // + Handle =3D NULL; + Status =3D mPchTcoSmiDispatchProtocol->LpcBiosWpRegister ( + mPchTcoSmiDispatchProtocol, + PchLpcBiosWpCallback, + &Handle + ); + ASSERT_EFI_ERROR (Status); + } + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.= c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.c new file mode 100644 index 0000000000..e9f4c91ed4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchInitSmm.c @@ -0,0 +1,179 @@ +/** @file + PCH Init Smm module for PCH specific SMI handlers. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchInitSmm.h" +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *m= PchIoTrap; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_SX_DISPATCH2_PROTOCOL *m= SxDispatch; + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_NVS_AREA *m= PchNvsArea; +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mA= cpiBaseAddr; + +// +// NOTE: The module variables of policy here are only valid in post time, = but not runtime time. +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_CONFIG_HOB *m= PchConfigHob; +GLOBAL_REMOVE_IF_UNREFERENCED SI_CONFIG_HOB_DATA *m= SiConfigHobData; + +// +// The reserved MMIO range to be used in Sx handler +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mR= esvMmioBaseAddr; +GLOBAL_REMOVE_IF_UNREFERENCED UINTN mR= esvMmioSize; + +/** + SMBUS Sx entry SMI handler. +**/ +VOID +SmbusSxCallback ( + VOID + ) +{ + UINT64 SmbusRegBase; + UINT16 SmbusIoBase; + + SmbusRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SMBUS, + PCI_FUNCTION_NUMBER_PCH_SMBUS, + 0 + ); + + if (PciSegmentRead32 (SmbusRegBase) =3D=3D 0xFFFFFFFF) { + return; + } + + SmbusIoBase =3D PciSegmentRead16 (SmbusRegBase + R_SMBUS_CFG_BASE) & B_S= MBUS_CFG_BASE_BAR; + if (SmbusIoBase =3D=3D 0) { + return; + } + + PciSegmentOr8 (SmbusRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_IO_SPA= CE); + // + // Clear SMBUS status and SMB_WAK_STS of GPE0 + // + IoWrite8 (SmbusIoBase + R_SMBUS_IO_HSTS, B_SMBUS_IO_SMBALERT_STS); + IoWrite32 (mAcpiBaseAddr + R_ACPI_IO_GPE0_STS_127_96, B_ACPI_IO_GPE0_STS= _127_96_SMB_WAK); +} + +/** + Allocates reserved MMIO for Sx SMI handler use. +**/ +VOID +AllocateReservedMmio ( + VOID + ) +{ + mResvMmioBaseAddr =3D PcdGet32 (PcdSiliconInitTempMemBaseAddr); + mResvMmioSize =3D PcdGet32 (PcdSiliconInitTempMemSize); + DEBUG ((DEBUG_INFO, "mResvMmioBaseAddr %x, mResvMmioSize %x\n", mResvMmi= oBaseAddr, mResvMmioSize)); +} + +/** + Initializes the PCH SMM handler for for PCIE hot plug support + PchInit SMM Module Entry Point\n + - Introduction\n + The PchInitSmm module is a SMM driver that initializes the Intel Pla= tform Controller Hub + SMM requirements and services. It consumes the PCH_POLICY_HOB and SI= _POLICY_HOB for expected + configurations per policy. + + - Details\n + This module provides SMI handlers to services PCIE HotPlug SMI, LinkAc= tive SMI, and LinkEq SMI. + And also provides port 0x61 emulation support, registers BIOS WP handl= er to process BIOSWP status, + and registers SPI Async SMI handler to handler SPI Async SMI. + This module also registers Sx SMI callback function to detail with GPI= O Sx Isolation and LAN requirement. + + - @pre + - PCH PCR base address configured + - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + - This is to ensure that PCI MMIO and IO resource has been prepared = and available for this driver to allocate. + - EFI_SMM_BASE2_PROTOCOL + - EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL + - EFI_SMM_SX_DISPATCH2_PROTOCOL + - EFI_SMM_CPU_PROTOCOL + - @link _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_PROT= OCOL @endlink + - @link _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCOL @endlink + - @link _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PROTOCOL= @endlink + - @link _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PROTOCOL @= endlink + - @link _PCH_ESPI_SMI_DISPATCH_PROTOCOL PCH_ESPI_SMI_DISPATCH_PROTOCOL= @endlink + + - References\n + - @link _PCH_POLICY PCH_POLICY_HOB @endlink. + - @link _SI_POLICY_STRUCT SI_POLICY_HOB @endlink. + + - Integration Checklists\n + - Verify prerequisites are met. Porting Recommendations. + - No modification of this module should be necessary + - Any modification of this module should follow the PCH BIOS Specifica= tion and EDS + + @param[in] ImageHandle - Handle for the image of this driver + @param[in] SystemTable - Pointer to the EFI System Table + + @retval EFI_SUCCESS - PCH SMM handler was installed +**/ +EFI_STATUS +EFIAPI +PchInitSmmEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + PCH_NVS_AREA_PROTOCOL *PchNvsAreaProtocol; + EFI_PEI_HOB_POINTERS HobPtr; + + DEBUG ((DEBUG_INFO, "PchInitSmmEntryPoint()\n")); + + Status =3D gSmst->SmmLocateProtocol ( + &gEfiSmmIoTrapDispatch2ProtocolGuid, + NULL, + (VOID **) &mPchIoTrap + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gSmst->SmmLocateProtocol ( + &gEfiSmmSxDispatch2ProtocolGuid, + NULL, + (VOID**) &mSxDispatch + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->LocateProtocol (&gPchNvsAreaProtocolGuid, NULL, (VOID **= ) &PchNvsAreaProtocol); + ASSERT_EFI_ERROR (Status); + mPchNvsArea =3D PchNvsAreaProtocol->Area; + + // + // Get PCH Data HOB. + // + HobPtr.Guid =3D GetFirstGuidHob (&gPchConfigHobGuid); + ASSERT (HobPtr.Guid !=3D NULL); + mPchConfigHob =3D (PCH_CONFIG_HOB *) GET_GUID_HOB_DATA (HobPtr.Guid); + + HobPtr.Guid =3D GetFirstGuidHob (&gSiConfigHobGuid); + ASSERT (HobPtr.Guid !=3D NULL); + mSiConfigHobData =3D (SI_CONFIG_HOB_DATA *) GET_GUID_HOB_DATA (HobPtr.Gu= id); + + mAcpiBaseAddr =3D PmcGetAcpiBase (); + + AllocateReservedMmio (); + + Status =3D InitializePchPcieSmm (ImageHandle, SystemTable); + ASSERT_EFI_ERROR (Status); + + Status =3D InstallPchBiosWriteProtect (ImageHandle, SystemTable); + ASSERT_EFI_ERROR (Status); + + Status =3D InstallPchSpiAsyncSmiHandler (); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchLanSxSmm= .c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchLanSxSmm.c new file mode 100644 index 0000000000..4a2d1f9cea --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchLanSxSmm.c @@ -0,0 +1,298 @@ +/** @file + PCH LAN Sx handler implementation. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include "PchInitSmm.h" +#include +#include +#include +#include + +/** + Checks if Lan is Enabled or Disabled + + @retval BOOLEAN TRUE if device is enabled, FALSE otherwise. +**/ +BOOLEAN +IsGbeEnabled ( + VOID + ) +{ + UINT64 GbePciBase; + + GbePciBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LAN, + PCI_FUNCTION_NUMBER_PCH_LAN, + 0 + ); + + if (PciSegmentRead32 (GbePciBase) !=3D 0xFFFFFFFF) { + return TRUE; + } + + return FALSE; +} + + +/** + Configure WOL during Sx entry. + + @param [in] GbeBar GbE MMIO space +**/ +VOID +GbeWolWorkaround ( + IN UINT32 GbeBar + ) +{ + UINT32 RAL0; + UINT32 RAH0; + UINT16 WUC; + EFI_STATUS Status; + UINT16 Data16; + + // + // 1. Set page to 769 Port Control Registers + // 2. Wait 4 mSec + // + Status =3D GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_769_PORT_CONTROL_REGISTER= S); + if (EFI_ERROR (Status)) return; + + // + // 3. Set registry to 17 Port General Configuration + // 4. Copy all settings from Port General Configuration + // + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT (= R_PHY_MDI_PAGE_769_REGISETER_17_PGC), &Data16); + if (EFI_ERROR (Status)) return; + + // + // 5. Modify BIT 4 and BIT 2 to disable host wake up and set MACPD + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT = (R_PHY_MDI_PAGE_769_REGISETER_17_PGC), (Data16 | B_PHY_MDI_PAGE_769_REGISET= ER_17_PGC_MACPD_ENABLE) & (~B_PHY_MDI_PAGE_769_REGISETER_17_PGC_HOST_WAKE_U= P)); + if (EFI_ERROR (Status)) return; + + // + // 6. Read Receive Address Low and Receive Address High from MMIO + // + RAL0 =3D MmioRead32 (GbeBar + R_LAN_MEM_CSR_RAL); + RAH0 =3D MmioRead32 (GbeBar + R_LAN_MEM_CSR_RAH); + + // + // 7. Set page to 800 Wake Up Registers + // 8. Wait 4 mSec + // + Status =3D GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_800_WAKE_UP_REGISTERS); + if (EFI_ERROR (Status)) return; + + // + // 9. Set registry to 16 Receive Address Low 1/2 + // + Status =3D GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_16_RA= L0); + if (EFI_ERROR (Status)) return; + + // + // 10. Program first 16 bits [0:15] out of 48 in Receive Address Low 1/2 + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_= REG_DATA_READ_WRITE, (RAL0 & 0xFFFF)); + if (EFI_ERROR (Status)) return; + + // + // 11. Set registry to 17 Receive Address Low 2/2 + // + Status =3D GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_17_RA= L1); + if (EFI_ERROR (Status)) return; + + // + // 12. Program second 16 bits [16:31] out of 48 in Receive Address Low 2= /2 + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_= REG_DATA_READ_WRITE, (RAL0 >> 16)); + if (EFI_ERROR (Status)) return; + + // + // 13. Set registry to 18 Receive Address High 1/2 + // + Status =3D GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_18_RA= H0); + if (EFI_ERROR (Status)) return; + + // + // 14. Program last 16 bits [32:47] out of 48 + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_= REG_DATA_READ_WRITE, (RAH0 & B_LAN_MEM_CSR_RAH_RAH)); + if (EFI_ERROR (Status)) return; + + // + // 15. Set registry to 19 Receive Address High 2/2 + // + Status =3D GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_19_RA= H1); + if (EFI_ERROR (Status)) return; + + // + // 16. Set Address Valid + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_= REG_DATA_READ_WRITE, B_PHY_MDI_PAGE_800_REGISETER_19_RAH1_ADDRESS_VALID); + if (EFI_ERROR (Status)) return; + + // + // 17. Set Wake Up Control Register 1 + // + Status =3D GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_800_REGISETER_1_WUC= ); + if (EFI_ERROR (Status)) return; + + // + // 18. Copy WakeUp Control from MAC MMIO + // + WUC =3D (UINT16) MmioRead32 (GbeBar + R_LAN_MEM_CSR_WUC); + + // + // 19. Store WakeUp Contorl into LCD + // Modify APME bit to enable APM wake up + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_= REG_DATA_READ_WRITE, (WUC & 0xFFFF)); + if (EFI_ERROR (Status)) return; + + // + // 20. Set page to 803 Host Wol Packet + // 21. Wait 4 mSec + // + Status =3D GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_803_HOST_WOL_PACKET); + if (EFI_ERROR (Status)) return; + + // + // 22. Set registry to 66 Host WoL Packet Clear + // + Status =3D GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_803_REGISETER_66_HW= PC); + if (EFI_ERROR (Status)) return; + + // + // 23. Clear WOL Packet + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, R_PHY_MDI_PHY_= REG_DATA_READ_WRITE, 0); + if (EFI_ERROR (Status)) return; + // + // 24. Set page to 769 Port Control Registers + // 25. Wait 4 mSec + // + Status =3D GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_769_PORT_CONTROL_REGISTER= S); + if (EFI_ERROR (Status)) return; + + // + // 26. Set registry to 17 Port General Configuration + // + Status =3D GbeMdiSetRegister (GbeBar, R_PHY_MDI_PAGE_769_REGISETER_17_PG= C); + if (EFI_ERROR (Status)) return; + + // + // 27. Copy all settings from Port General Configuration + // + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT (= R_PHY_MDI_PAGE_769_REGISETER_17_PGC), &Data16); + if (EFI_ERROR (Status)) return; + + // + // 28. Modify BIT 4 and BIT 2 to enable host wake up and clear MACPD + // + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT = (R_PHY_MDI_PAGE_769_REGISETER_17_PGC), (Data16 | B_PHY_MDI_PAGE_769_REGISET= ER_17_PGC_HOST_WAKE_UP) & (~B_PHY_MDI_PAGE_769_REGISETER_17_PGC_MACPD_ENABL= E)); + if (EFI_ERROR (Status)) return; +} + +/** + Additional Internal GbE Controller special cases WOL Support. + + System BIOS is required perform additional steps upon S0 to S3,4,5 trans= ition + when ME is off and GbE device in D0. This is needed to enable LAN wake + in particular when platform is shut-down from EFI. +**/ +VOID +GbeSxWorkaround ( + VOID + ) +{ + UINT64 LanRegBase; + UINT32 GbeBar; + EFI_STATUS Status; + + LanRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LAN, + PCI_FUNCTION_NUMBER_PCH_LAN, + 0 + ); + + if (PciSegmentRead16 (LanRegBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) { + return; + } + + // + // Check if GbE device is in D0 + // + if ((PciSegmentRead16 (LanRegBase + R_LAN_CFG_PMCS) & B_LAN_CFG_PMCS_PS)= !=3D V_LAN_CFG_PMCS_PS0) { + return; + } + + ASSERT (mResvMmioSize >=3D (1 << N_LAN_CFG_MBARA_ALIGN)); + GbeBar =3D (UINT32) mResvMmioBaseAddr; + if (GbeBar =3D=3D 0) { + ASSERT (FALSE); + return; + } + + // + // Enable MMIO decode using reserved range. + // + PciSegmentAnd16 (LanRegBase + PCI_COMMAND_OFFSET, (UINT16) ~EFI_PCI_COMM= AND_MEMORY_SPACE); + PciSegmentWrite32 (LanRegBase + R_LAN_CFG_MBARA, GbeBar); + PciSegmentOr16 (LanRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_= SPACE); + + // + // If MBARA offset 5800h [0] =3D 1b then proceed with the w/a + // + if (MmioRead32 (GbeBar + R_LAN_MEM_CSR_WUC) & B_LAN_MEM_CSR_WUC_APME) { + Status =3D GbeMdiAcquireMdio (GbeBar); + ASSERT_EFI_ERROR (Status); + if (!EFI_ERROR (Status)) { + GbeWolWorkaround (GbeBar); + GbeMdiReleaseMdio (GbeBar); + } + } + + // + // Disable MMIO decode. + // + PciSegmentAnd16 (LanRegBase + PCI_COMMAND_OFFSET, (UINT16) ~EFI_PCI_COMM= AND_MEMORY_SPACE); + PciSegmentWrite32 (LanRegBase + R_LAN_CFG_MBARA, 0); +} + +/** + Enable platform wake from LAN when in DeepSx if platform supports it. + Called upon Sx entry. +**/ +VOID +GbeConfigureDeepSxWake ( + VOID + ) +{ + if (PmcIsLanDeepSxWakeEnabled ()) { + IoOr32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96), (UINT32) B= _ACPI_IO_GPE0_EN_127_96_LAN_WAKE); + } +} + +/** + GbE Sx entry handler +**/ +VOID +PchLanSxCallback ( + VOID + ) +{ + if (IsGbeEnabled ()) { + GbeSxWorkaround (); + GbeConfigureDeepSxWake (); + + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.= c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c new file mode 100644 index 0000000000..eac2e1c3ec --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchPcieSmm.c @@ -0,0 +1,436 @@ +/** @file + PCH Pcie SMM Driver Entry + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchInitSmm.h" +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE *mDevAspmOverrid= e; +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mNumOfDevAspmOve= rride; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPchBusNumber; +// +// @note: +// These temp bus numbers cannot be used in runtime (hot-plug). +// These can be used only during boot. +// +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mTempRootPortBus= NumMin; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mTempRootPortBus= NumMax; + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_ROOT_PORT_CONFIG mPcieRootPortCon= fig[PCH_MAX_PCIE_ROOT_PORTS]; + +GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mPciePmTrapExecu= ted =3D FALSE; + +extern EFI_GUID gPchDeviceTableHobGuid; + +/** + Program Common Clock and ASPM of Downstream Devices + + @param[in] PortIndex Pcie Root Port Number + @param[in] RpDevice Pcie Root Pci Device Number + @param[in] RpFunction Pcie Root Pci Function Number +**/ +STATIC +VOID +PchPcieSmi ( + IN UINT8 PortIndex, + IN UINT8 RpDevice, + IN UINT8 RpFunction + ) +{ + UINT8 SecBus; + UINT8 SubBus; + UINT64 RpBase; + UINT64 EpBase; + UINT8 EpPcieCapPtr; + UINT8 EpMaxSpeed; + BOOLEAN DownstreamDevicePresent; + UINT32 Timeout; + + RpBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + mPchBusNumber, + (UINT32) RpDevice, + (UINT32) RpFunction, + 0 + ); + + if (PciSegmentRead16 (RpBase + PCI_VENDOR_ID_OFFSET) =3D=3D 0xFFFF) { + return; + } + // + // Check presence detect state. Here the endpoint must be detected using= PDS rather than + // the usual LinkActive check, because PDS changes immediately and LA ta= kes a few milliseconds to stabilize + // + DownstreamDevicePresent =3D !!(PciSegmentRead16 (RpBase + R_PCH_PCIE_CFG= _SLSTS) & B_PCIE_SLSTS_PDS); + + if (DownstreamDevicePresent) { + /// + /// Make sure the link is active before trying to talk to device behin= d it + /// Wait up to 100ms, according to PCIE spec chapter 6.7.3.3 + /// + Timeout =3D 100 * 1000; + while ((PciSegmentRead16 (RpBase + R_PCH_PCIE_CFG_LSTS) & B_PCIE_LSTS_= LA) =3D=3D 0 ) { + MicroSecondDelay (10); + Timeout-=3D10; + if (Timeout =3D=3D 0) { + return; + } + } + SecBus =3D PciSegmentRead8 (RpBase + PCI_BRIDGE_SECONDARY_BUS_REGISTE= R_OFFSET); + SubBus =3D PciSegmentRead8 (RpBase + PCI_BRIDGE_SUBORDINATE_BUS_REGIS= TER_OFFSET); + ASSERT (SecBus !=3D 0 && SubBus !=3D 0); + RootportDownstreamConfiguration ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + RpDevice, + RpFunction, + mTempRootPortBusNumMin, + mTempRootPortBusNumMax + ); + RootportDownstreamPmConfiguration ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + RpDevice, + RpFunction, + mTempRootPortBusNumMin, + mTempRootPortBusNumMax, + &mPcieRootPortConfig[PortIndex], + mNumOfDevAspmOverride, + mDevAspmOverride + ); + // + // Perform Equalization + // + EpBase =3D PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH, Se= cBus, 0, 0, 0); + EpPcieCapPtr =3D PcieFindCapId (DEFAULT_PCI_SEGMENT_NUMBER_PCH, SecBus= , 0, 0, EFI_PCI_CAPABILITY_ID_PCIEXP); + EpMaxSpeed =3D PciSegmentRead8 (EpBase + EpPcieCapPtr + R_PCIE_LCAP_OF= FSET) & B_PCIE_LCAP_MLS; + if (EpMaxSpeed >=3D 3) { + PciSegmentOr32 (RpBase + R_PCH_PCIE_CFG_EX_LCTL3, B_PCIE_EX_LCTL3_PE= ); + PciSegmentOr32 (RpBase + R_PCH_PCIE_CFG_LCTL, B_PCIE_LCTL_RL); + } + } +} + +/** + PCIE Hotplug SMI call back function for each Root port + + @param[in] DispatchHandle Handle of this dispatch function + @param[in] RpContext Rootport context, which contains R= ootPort Index, + and RootPort PCI BDF. +**/ +VOID +EFIAPI +PchPcieSmiRpHandlerFunction ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ) +{ + PchPcieSmi (RpContext->RpIndex, RpContext->DevNum, RpContext->FuncNum); +} + +/** + PCIE Link Active State Change Hotplug SMI call back function for all Roo= t ports + + @param[in] DispatchHandle Handle of this dispatch function + @param[in] RpContext Rootport context, which contains R= ootPort Index, + and RootPort PCI BDF. +**/ +VOID +EFIAPI +PchPcieLinkActiveStateChange ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ) +{ + return; +} + +/** + PCIE Link Equalization Request SMI call back function for all Root ports + + @param[in] DispatchHandle Handle of this dispatch function + @param[in] RpContext Rootport context, which contains R= ootPort Index, + and RootPort PCI BDF. +**/ +VOID +EFIAPI +PchPcieLinkEqHandlerFunction ( + IN EFI_HANDLE DispatchHandle, + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext + ) +{ + /// + /// From PCI Express specification, the PCIe device can request for Link= Equalization. When the + /// Link Equalization is requested by the device, an SMI will be generat= ed by PCIe RP when + /// enabled and the SMI subroutine would invoke the Software Preset/Coef= ficient Search + /// software to re-equalize the link. + /// + + return; + +} + +/** + An IoTrap callback to config PCIE power management settings +**/ +VOID +PchPciePmIoTrapSmiCallback ( + VOID + ) +{ + UINT32 PortIndex; + UINT64 RpBase; + UINT8 MaxPciePortNum; + UINTN RpDevice; + UINTN RpFunction; + + MaxPciePortNum =3D GetPchMaxPciePortNum (); + + for (PortIndex =3D 0; PortIndex < MaxPciePortNum; PortIndex++) { + GetPchPcieRpDevFun (PortIndex, &RpDevice, &RpFunction); + RpBase =3D PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH, DE= FAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction, 0); + + if (PciSegmentRead16 (RpBase) !=3D 0xFFFF) { + RootportDownstreamPmConfiguration ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + (UINT8)RpDevice, + (UINT8)RpFunction, + mTempRootPortBusNumMin, + mTempRootPortBusNumMax, + &mPcieRootPortConfig[PortIndex], + mNumOfDevAspmOverride, + mDevAspmOverride + ); + + } + } +} + +/** + An IoTrap callback to config PCIE power management settings + + @param[in] DispatchHandle - The handle of this callback, obtained when = registering + @param[in] DispatchContext - Pointer to the EFI_SMM_IO_TRAP_DISPATCH_CAL= LBACK_CONTEXT + +**/ +VOID +EFIAPI +PchPcieIoTrapSmiCallback ( + IN EFI_HANDLE DispatchHandle, + IN EFI_SMM_IO_TRAP_CONTEXT *CallbackContext, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ) +{ + if (CallbackContext->WriteData =3D=3D PciePmTrap) { + if (mPciePmTrapExecuted =3D=3D FALSE) { + PchPciePmIoTrapSmiCallback (); + mPciePmTrapExecuted =3D TRUE; + } + } else { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + } +} + +/** + This function clear the Io trap executed flag before enter S3 + + @param[in] Handle Handle of the callback + @param[in] Context The dispatch context + + @retval EFI_SUCCESS PCH register saved +**/ +EFI_STATUS +EFIAPI +PchPcieS3EntryCallBack ( + IN EFI_HANDLE Handle, + IN CONST VOID *Context OPTIONAL, + IN OUT VOID *CommBuffer OPTIONAL, + IN OUT UINTN *CommBufferSize OPTIONAL + ) +{ + mPciePmTrapExecuted =3D FALSE; + return EFI_SUCCESS; +} +/** + Register PCIE Hotplug SMI dispatch function to handle Hotplug enabling + + @param[in] ImageHandle The image handle of this module + @param[in] SystemTable The EFI System Table + + @retval EFI_SUCCESS The function completes successfully +**/ +EFI_STATUS +EFIAPI +InitializePchPcieSmm ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINT8 PortIndex; + UINT8 Data8; + UINT32 Data32Or; + UINT32 Data32And; + UINT64 RpBase; + UINTN RpDevice; + UINTN RpFunction; + EFI_HANDLE PcieHandle; + PCH_PCIE_SMI_DISPATCH_PROTOCOL *PchPcieSmiDispatchProtocol; + EFI_HOB_GUID_TYPE* Hob; + UINT32 DevTableSize; + EFI_HANDLE PchIoTrapHandle; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT PchIoTrapContext; + EFI_SMM_SX_REGISTER_CONTEXT SxDispatchContext; + PCH_PCIE_IOTRAP_PROTOCOL *PchPcieIoTrapProtocol; + EFI_HANDLE SxDispatchHandle; + UINT8 MaxPciePortNum; + + DEBUG ((DEBUG_INFO, "InitializePchPcieSmm () Start\n")); + + MaxPciePortNum =3D GetPchMaxPciePortNum (); + + // + // Locate Pch Pcie Smi Dispatch Protocol + // + Status =3D gSmst->SmmLocateProtocol (&gPchPcieSmiDispatchProtocolGuid, N= ULL, (VOID**)&PchPcieSmiDispatchProtocol); + ASSERT_EFI_ERROR (Status); + + mPchBusNumber =3D DEFAULT_PCI_BUS_NUMBER_PCH; + mTempRootPortBusNumMin =3D PcdGet8 (PcdSiliconInitTempPciBusMin); + mTempRootPortBusNumMax =3D PcdGet8 (PcdSiliconInitTempPciBusMax); + + ASSERT (sizeof mPcieRootPortConfig =3D=3D sizeof mPchConfigHob->PcieRp.R= ootPort); + CopyMem ( + mPcieRootPortConfig, + &(mPchConfigHob->PcieRp.RootPort), + sizeof (mPcieRootPortConfig) + ); + + mDevAspmOverride =3D NULL; + mNumOfDevAspmOverride =3D 0; + + Hob =3D GetFirstGuidHob (&gPchDeviceTableHobGuid); + if (Hob !=3D NULL) { + DevTableSize =3D GET_GUID_HOB_DATA_SIZE (Hob); + ASSERT ((DevTableSize % sizeof (PCH_PCIE_DEVICE_OVERRIDE)) =3D=3D 0); + mNumOfDevAspmOverride =3D DevTableSize / sizeof (PCH_PCIE_DEVICE_OVERR= IDE); + DEBUG ((DEBUG_INFO, "Found PcieDeviceTable HOB (%d entries)\n", mNumOf= DevAspmOverride)); + Status =3D gSmst->SmmAllocatePool ( + EfiRuntimeServicesData, + DevTableSize, + (VOID **) &mDevAspmOverride + ); + CopyMem (mDevAspmOverride, GET_GUID_HOB_DATA (Hob), DevTableSize); + } + + // + // Throught all PCIE root port function and register the SMI Handler for= enabled ports. + // + for (PortIndex =3D 0; PortIndex < MaxPciePortNum; PortIndex++) { + GetPchPcieRpDevFun (PortIndex, &RpDevice, &RpFunction); + RpBase =3D PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMBER_PCH, DE= FAULT_PCI_BUS_NUMBER_PCH, (UINT32) RpDevice, (UINT32) RpFunction, 0); + // + // Skip the root port function which is not enabled + // + if (PciSegmentRead32 (RpBase) =3D=3D 0xFFFFFFFF) { + continue; + } + + // + // Register SMI Handlers for Hot Plug and Link Active State Change + // + Data8 =3D PciSegmentRead8 (RpBase + R_PCH_PCIE_CFG_SLCAP); + if (Data8 & B_PCIE_SLCAP_HPC) { + PcieHandle =3D NULL; + Status =3D PchPcieSmiDispatchProtocol->HotPlugRegister ( + PchPcieSmiDispatchProtocol, + PchPcieSmiRpHandlerFunction, + PortIndex, + &PcieHandle + ); + ASSERT_EFI_ERROR (Status); + + Status =3D PchPcieSmiDispatchProtocol->LinkActiveRegister ( + PchPcieSmiDispatchProtocol, + PchPcieLinkActiveStateChange, + PortIndex, + &PcieHandle + ); + ASSERT_EFI_ERROR (Status); + + Data32Or =3D B_PCH_PCIE_CFG_MPC_HPME; + Data32And =3D (UINT32) ~B_PCH_PCIE_CFG_MPC_HPME; + S3BootScriptSaveMemReadWrite ( + S3BootScriptWidthUint32, + PcdGet64 (PcdPciExpressBaseAddress) + RpBase + R_PCH_PCIE_CFG_MPC, + &Data32Or, /// Data to be ORed + &Data32And /// Data to be ANDed + ); + } + + // + // Register SMI Handler for Link Equalization Request from Gen 3 Devic= es. + // + Data8 =3D PciSegmentRead8 (RpBase + R_PCH_PCIE_CFG_LCAP); + if ((Data8 & B_PCIE_LCAP_MLS) =3D=3D V_PCIE_LCAP_MLS_GEN3) { + Status =3D PchPcieSmiDispatchProtocol->LinkEqRegister ( + PchPcieSmiDispatchProtocol, + PchPcieLinkEqHandlerFunction, + PortIndex, + &PcieHandle + ); + ASSERT_EFI_ERROR (Status); + } + } + + ASSERT_EFI_ERROR (Status); + + PchIoTrapContext.Type =3D WriteTrap; + PchIoTrapContext.Length =3D 4; + PchIoTrapContext.Address =3D 0; + Status =3D mPchIoTrap->Register ( + mPchIoTrap, + (EFI_SMM_HANDLER_ENTRY_POINT2) PchPcieIoTrapSmiCa= llback, + &PchIoTrapContext, + &PchIoTrapHandle + ); + ASSERT_EFI_ERROR (Status); + + // + // Install the PCH Pcie IoTrap protocol + // + (gBS->AllocatePool) (EfiBootServicesData, sizeof (PCH_PCIE_IOTRAP_PROTOC= OL), (VOID **)&PchPcieIoTrapProtocol); + PchPcieIoTrapProtocol->PcieTrapAddress =3D PchIoTrapContext.Address; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gPchPcieIoTrapProtocolGuid, + PchPcieIoTrapProtocol, + NULL + ); + + // + // Register the callback for S3 entry + // + SxDispatchContext.Type =3D SxS3; + SxDispatchContext.Phase =3D SxEntry; + Status =3D mSxDispatch->Register ( + mSxDispatch, + PchPcieS3EntryCallBack, + &SxDispatchContext, + &SxDispatchHandle + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "InitializePchPcieSmm, IoTrap @ %x () End\n", PchIoT= rapContext.Address)); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchSpiAsync= .c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchSpiAsync.c new file mode 100644 index 0000000000..3c843616e4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchInit/Smm/PchSpiAsync.c @@ -0,0 +1,69 @@ +/** @file + PCH SPI Async SMI handler. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchInitSmm.h" + +/// +/// Global variables +/// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_SMI_DISPATCH_PROTOCOL *mPchSmiDispat= chProtocol; + +/** + This hardware SMI handler will be run every time the flash write/earse h= appens. + + @param[in] DispatchHandle Not used + +**/ +VOID +EFIAPI +PchSpiAsyncCallback ( + IN EFI_HANDLE DispatchHandle + ) +{ + // + // Dummy SMI handler + // +} + +/** + This fuction install SPI ASYNC SMI handler. + + @retval EFI_SUCCESS Initialization complete. +**/ +EFI_STATUS +EFIAPI +InstallPchSpiAsyncSmiHandler ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + DEBUG ((DEBUG_INFO, "InstallPchSpiAsyncSmiHandler()\n")); + + /// + /// Get the PCH SMM dispatch protocol + /// + mPchSmiDispatchProtocol =3D NULL; + Status =3D gSmst->SmmLocateProtocol (&gPchSmiDispatchProtocolGuid, NULL,= (VOID **) &mPchSmiDispatchProtocol); + ASSERT_EFI_ERROR (Status); + + /// + /// Register an SpiAsync callback function + /// + Handle =3D NULL; + Status =3D mPchSmiDispatchProtocol->SpiAsyncRegister ( + mPchSmiDispatchProtocol, + PchSpiAsyncCallback, + &Handle + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/S= mmControlDriver.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/Runti= meDxe/SmmControlDriver.c new file mode 100644 index 0000000000..d843de3ad8 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/SmmControl/RuntimeDxe/SmmContr= olDriver.c @@ -0,0 +1,399 @@ +/** @file + This is the driver that publishes the SMM Control Protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "SmmControlDriver.h" + +STATIC SMM_CONTROL_PRIVATE_DATA mSmmControl; +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mABase; + +VOID +EFIAPI +DisablePendingSmis ( + VOID + ); + +/** + Fixup internal data pointers so that the services can be called in virtu= al mode. + + @param[in] Event The event registered. + @param[in] Context Event context. + +**/ +VOID +EFIAPI +SmmControlVirtualAddressChangeEvent ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gRT->ConvertPointer (0, (VOID *) &(mSmmControl.SmmControl.Trigger)); + gRT->ConvertPointer (0, (VOID *) &(mSmmControl.SmmControl.Clear)); +} + +/** + SmmControl DXE RUNTIME Module Entry Point\n + - Introduction\n + The SmmControl module is a DXE RUNTIME driver that provides a standard= way + for other drivers to trigger software SMIs. + + - @pre + - PCH Power Management I/O space base address has already been program= med. + If SmmControl Runtime DXE driver is run before Status Code Runtime P= rotocol + is installed and there is the need to use Status code in the driver,= it will + be necessary to add EFI_STATUS_CODE_RUNTIME_PROTOCOL_GUID to the dep= endency file. + - EFI_SMM_BASE2_PROTOCOL + - Documented in the System Management Mode Core Interface Specificat= ion. + + - @result + The SmmControl driver produces the EFI_SMM_CONTROL_PROTOCOL documented= in + System Management Mode Core Interface Specification. + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_STATUS Results of the installation of the SMM C= ontrol Protocol +**/ +EFI_STATUS +EFIAPI +SmmControlDriverEntryInit ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + DEBUG ((DEBUG_INFO, "SmmControlDriverEntryInit() Start\n")); + + // + // Get the Power Management I/O space base address. We assume that + // this base address has already been programmed if this driver is + // being run. + // + mABase =3D PmcGetAcpiBase (); + + Status =3D EFI_SUCCESS; + if (mABase !=3D 0) { + // + // Install the instance of the protocol + // + mSmmControl.Signature =3D SMM_CONTROL_PRIVATE_DA= TA_SIGNATURE; + mSmmControl.Handle =3D ImageHandle; + + mSmmControl.SmmControl.Trigger =3D Activate; + mSmmControl.SmmControl.Clear =3D Deactivate; + mSmmControl.SmmControl.MinimumTriggerPeriod =3D 0; + + // + // Install our protocol interfaces on the device's handle + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mSmmControl.Handle, + &gEfiSmmControl2ProtocolGuid, + &mSmmControl.SmmControl, + NULL + ); + } else { + Status =3D EFI_DEVICE_ERROR; + return Status; + } + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + SmmControlVirtualAddressChangeEvent, + NULL, + &gEfiEventVirtualAddressChangeGuid, + &Event + ); + // + // Disable any PCH SMIs that, for whatever reason, are asserted after th= e boot. + // + DisablePendingSmis (); + + DEBUG ((DEBUG_INFO, "SmmControlDriverEntryInit() End\n")); + + return Status; +} + +/** + Trigger the software SMI + + @param[in] Data The value to be set on the software SMI = data port + + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +SmmTrigger ( + IN UINT8 Data + ) +{ + UINT32 OutputData; + UINT32 OutputPort; + + // + // Enable the APMC SMI + // + OutputPort =3D mABase + R_ACPI_IO_SMI_EN; + OutputData =3D IoRead32 ((UINTN) OutputPort); + OutputData |=3D (B_ACPI_IO_SMI_EN_APMC | B_ACPI_IO_SMI_EN_GBL_SMI); + DEBUG ( + (DEBUG_EVENT, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + OutputPort =3D R_PCH_IO_APM_CNT; + OutputData =3D Data; + + // + // Generate the APMC SMI + // + IoWrite8 ( + (UINTN) OutputPort, + (UINT8) (OutputData) + ); + + return EFI_SUCCESS; +} + +/** + Clear the SMI status + + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_DEVICE_ERROR Something error occurred +**/ +EFI_STATUS +EFIAPI +SmmClear ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 OutputData; + UINT32 OutputPort; + + Status =3D EFI_SUCCESS; + + // + // Clear the Power Button Override Status Bit, it gates EOS from being s= et. + // + OutputPort =3D mABase + R_ACPI_IO_PM1_STS; + OutputData =3D B_ACPI_IO_PM1_STS_PRBTNOR; + DEBUG ( + (DEBUG_EVENT, + "The PM1 Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite16 ( + (UINTN) OutputPort, + (UINT16) (OutputData) + ); + + // + // Clear the APM SMI Status Bit + // + OutputPort =3D mABase + R_ACPI_IO_SMI_STS; + OutputData =3D B_ACPI_IO_SMI_STS_APM; + DEBUG ( + (DEBUG_EVENT, + "The SMI Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + // + // Set the EOS Bit + // + OutputPort =3D mABase + R_ACPI_IO_SMI_EN; + OutputData =3D IoRead32 ((UINTN) OutputPort); + OutputData |=3D B_ACPI_IO_SMI_EN_EOS; + DEBUG ( + (DEBUG_EVENT, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + // + // There is no need to read EOS back and check if it is set. + // This can lead to a reading of zero if an SMI occurs right after the S= MI_EN port read + // but before the data is returned to the CPU. + // SMM Dispatcher should make sure that EOS is set after all SMI sources= are processed. + // + return Status; +} + +/** + This routine generates an SMI + + @param[in] This The EFI SMM Control protocol insta= nce + @param[in, out] CommandPort The buffer contains data to the co= mmand port + @param[in, out] DataPort The buffer contains data to the da= ta port + @param[in] Periodic Periodic or not + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI Status Describing the result of the opera= tion + @retval EFI_INVALID_PARAMETER Some parameter value passed is not= supported +**/ +EFI_STATUS +EFIAPI +Activate ( + IN CONST EFI_SMM_CONTROL2_PROTOCOL * This, + IN OUT UINT8 *CommandPort = OPTIONAL, + IN OUT UINT8 *DataPort = OPTIONAL, + IN BOOLEAN Periodic = OPTIONAL, + IN UINTN ActivationInterval= OPTIONAL + ) +{ + EFI_STATUS Status; + UINT8 Data; + + if (Periodic) { + DEBUG ((DEBUG_WARN, "Invalid parameter\n")); + return EFI_INVALID_PARAMETER; + } + + if (CommandPort =3D=3D NULL) { + Data =3D 0xFF; + } else { + Data =3D *CommandPort; + } + // + // Clear any pending the APM SMI + // + Status =3D SmmClear (); + if (EFI_ERROR (Status)) { + return Status; + } + + return SmmTrigger (Data); +} + +/** + This routine clears an SMI + + @param[in] This The EFI SMM Control protocol instance + @param[in] Periodic Periodic or not + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted +**/ +EFI_STATUS +EFIAPI +Deactivate ( + IN CONST EFI_SMM_CONTROL2_PROTOCOL *This, + IN BOOLEAN Periodic OPTIONAL + ) +{ + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + return SmmClear (); +} +/** + Disable all pending SMIs + +**/ +VOID +EFIAPI +DisablePendingSmis ( + VOID + ) +{ + UINT32 Data; + BOOLEAN SciEn; + + // + // Determine whether an ACPI OS is present (via the SCI_EN bit) + // + Data =3D IoRead16 ((UINTN) mABase + R_ACPI_IO_PM1_CNT); + SciEn =3D (BOOLEAN) ((Data & B_ACPI_IO_PM1_CNT_SCI_EN) =3D=3D B_ACPI= _IO_PM1_CNT_SCI_EN); + + if (!SciEn) { + // + // Clear any SMIs that double as SCIs (when SCI_EN=3D=3D0) + // + IoWrite16 ((UINTN) mABase + R_ACPI_IO_PM1_STS, 0xFFFF); + IoWrite16 ((UINTN) mABase + R_ACPI_IO_PM1_EN, 0); + IoWrite16 ((UINTN) mABase + R_ACPI_IO_PM1_CNT, 0); + IoWrite32 ( + (UINTN) mABase + R_ACPI_IO_GPE0_STS_127_96, + (UINT32)( B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS | + B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE | + B_ACPI_IO_GPE0_STS_127_96_PME_B0 | + B_ACPI_IO_GPE0_STS_127_96_PME | + B_ACPI_IO_GPE0_STS_127_96_BATLOW | + B_ACPI_IO_GPE0_STS_127_96_RI | + B_ACPI_IO_GPE0_STS_127_96_SWGPE) + ); + // + // Disable WADT_EN by default can avoid the WADT SMI during POST time = when the WADT_STS is set as a wake source. + // BIOS disable WADT_EN and keep WADT_STS into OS so OS can be aware o= f the wake source. + // + IoAnd32 ((UINTN) mABase + R_ACPI_IO_GPE0_EN_127_96, (UINT32) ~B_ACPI_I= O_GPE0_EN_127_96_WADT); + } + // + // Clear and disable all SMIs that are unaffected by SCI_EN + // + GpioDisableAllGpiSmi (); + + GpioClearAllGpiSmiSts (); + + IoWrite32 ((UINTN) mABase + R_ACPI_IO_DEVACT_STS, 0x0000FFFF); + + IoWrite32 ((UINTN) mABase + R_ACPI_IO_SMI_STS, ~0u); + + // + // (Make sure to write this register last -- EOS re-enables SMIs for the= PCH) + // + Data =3D IoRead32 ((UINTN) mABase + R_ACPI_IO_SMI_EN); + // + // clear all bits except those tied to SCI_EN + // + Data &=3D B_ACPI_IO_SMI_EN_BIOS_RLS; + // + // enable SMIs and specifically enable writes to APM_CNT. + // + Data |=3D B_ACPI_IO_SMI_EN_GBL_SMI | B_ACPI_IO_SMI_EN_APMC; + // + // NOTE: Default value of EOS is set in PCH, it will be automatically c= leared Once the PCH asserts SMI# low, + // we don't need to do anything to clear it + // + IoWrite32 ((UINTN) mABase + R_ACPI_IO_SMI_EN, Data); +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpi.c b/Sili= con/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpi.c new file mode 100644 index 0000000000..458d137e4f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Spi/Smm/PchSpi.c @@ -0,0 +1,310 @@ +/** @file + PCH SPI SMM Driver implements the SPI Host Controller Compatibility Inte= rface. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Global variables +// +GLOBAL_REMOVE_IF_UNREFERENCED SPI_INSTANCE *mSpiInstance; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_CPU_PROTOCOL *mSmmCpuProtocol; +// +// mPchSpiResvMmioAddr keeps the reserved MMIO range assiged to SPI. +// In SMM it always set back the reserved MMIO address to SPI BAR0 to ensu= re the MMIO range +// won't overlap with SMRAM range, and trusted. +// +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mSpiResvMmioAddr; + +/** + SPI Runtime SMM Module Entry Point\n + - Introduction\n + The SPI SMM module provide a standard way for other modules to use the= PCH SPI Interface in SMM. + + - @pre + - EFI_SMM_BASE2_PROTOCOL + - Documented in System Management Mode Core Interface Specification . + + - @result + The SPI SMM driver produces @link _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL @= endlink with GUID + gPchSmmSpiProtocolGuid which is different from SPI RUNTIME driver. + + - Integration Check List\n + - This driver supports Descriptor Mode only. + - This driver supports Hardware Sequence only. + - When using SMM SPI Protocol to perform flash access in an SMI handle= r, + and the SMI occurrence is asynchronous to normal mode code execution, + proper synchronization mechanism must be applied, e.g. disable SMI b= efore + the normal mode SendSpiCmd() starts and re-enable SMI after + the normal mode SendSpiCmd() completes. + @note The implementation of SendSpiCmd() uses GBL_SMI_EN in + SMI_EN register (ABase + 30h) to disable and enable SMIs. But this m= ay + not be effective as platform may well set the SMI_LOCK bit (i.e., PM= C PCI Offset A0h [4]). + So the synchronization at caller level is likely needed. + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this drive= r. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +InstallPchSpi ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Init PCH spi reserved MMIO address. + // + mSpiResvMmioAddr =3D PCH_SPI_BASE_ADDRESS; + + /// + /// Allocate pool for SPI protocol instance + /// + Status =3D gSmst->SmmAllocatePool ( + EfiRuntimeServicesData, /// MemoryType don't care + sizeof (SPI_INSTANCE), + (VOID **) &mSpiInstance + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if (mSpiInstance =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem ((VOID *) mSpiInstance, sizeof (SPI_INSTANCE)); + /// + /// Initialize the SPI protocol instance + /// + Status =3D SpiProtocolConstructor (mSpiInstance); + if (EFI_ERROR (Status)) { + return Status; + } + /// + /// Install the SMM PCH_SPI_PROTOCOL interface + /// + Status =3D gSmst->SmmInstallProtocolInterface ( + &(mSpiInstance->Handle), + &gPchSmmSpiProtocolGuid, + EFI_NATIVE_INTERFACE, + &(mSpiInstance->SpiProtocol) + ); + if (EFI_ERROR (Status)) { + gSmst->SmmFreePool (mSpiInstance); + return EFI_DEVICE_ERROR; + } + + return EFI_SUCCESS; +} + +/** + Acquire PCH spi mmio address. + If it is ever different from the preallocated address, reassign it back. + In SMM, it always override the BAR0 and returns the reserved MMIO range = for SPI. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval PchSpiBar0 return SPI MMIO address +**/ +UINTN +AcquireSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ) +{ + UINT32 SpiBar0; + // + // Save original SPI physical MMIO address + // + SpiBar0 =3D PciSegmentRead32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0) = & ~(B_SPI_CFG_BAR0_MASK); + + if (SpiBar0 !=3D mSpiResvMmioAddr) { + // + // Temporary disable MSE, and override with SPI reserved MMIO address,= then enable MSE. + // + PciSegmentAnd8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, (UINT8) = ~EFI_PCI_COMMAND_MEMORY_SPACE); + PciSegmentWrite32 (SpiInstance->PchSpiBase + R_SPI_CFG_BAR0, mSpiResvM= mioAddr); + PciSegmentOr8 (SpiInstance->PchSpiBase + PCI_COMMAND_OFFSET, EFI_PCI_C= OMMAND_MEMORY_SPACE); + } + // + // SPIBAR0 will be different before and after PCI enum so need to get it= from SPI BAR0 reg. + // + return mSpiResvMmioAddr; +} + +/** + Release pch spi mmio address. Do nothing. + + @param[in] SpiInstance Pointer to SpiInstance to initialize + + @retval None +**/ +VOID +ReleaseSpiBar0 ( + IN SPI_INSTANCE *SpiInstance + ) +{ +} + +/** + This function is a hook for Spi to disable BIOS Write Protect + + @retval EFI_SUCCESS The protocol instance was properly initi= alized + @retval EFI_ACCESS_DENIED The BIOS Region can only be updated in S= MM phase + +**/ +EFI_STATUS +EFIAPI +DisableBiosWriteProtect ( + VOID + ) +{ + UINT64 SpiBaseAddress; + + SpiBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + // Write clear BC_SYNC_SS prior to change WPD from 0 to 1. + // + PciSegmentOr8 ( + SpiBaseAddress + R_SPI_CFG_BC + 1, + (B_SPI_CFG_BC_SYNC_SS >> 8) + ); + /// + /// Set BIOSWE bit (SPI PCI Offset DCh [0]) =3D 1b + /// Enable the access to the BIOS space for both read and write cycles + /// + PciSegmentOr8 ( + SpiBaseAddress + R_SPI_CFG_BC, + B_SPI_CFG_BC_WPD + ); + + /// + /// PCH BIOS Spec Section 3.7 BIOS Region SMM Protection Enabling + /// If the following steps are implemented: + /// - Set the EISS bit (SPI PCI Offset DCh [5]) =3D 1b + /// - Follow the 1st recommendation in section 3.6 + /// the BIOS Region can only be updated by following the steps bellow: + /// - Once all threads enter SMM + /// - Read memory location FED30880h OR with 00000001h, place the resul= t in EAX, + /// and write data to lower 32 bits of MSR 1FEh (sample code availabl= e) + /// - Set BIOSWE bit (SPI PCI Offset DCh [0]) =3D 1b + /// - Modify BIOS Region + /// - Clear BIOSWE bit (SPI PCI Offset DCh [0]) =3D 0b + /// + if ((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC) & B_SPI_CFG_BC_EISS= ) !=3D 0) { + PchSetInSmmSts (); + } + + return EFI_SUCCESS; +} + +/** + This function is a hook for Spi to enable BIOS Write Protect + + +**/ +VOID +EFIAPI +EnableBiosWriteProtect ( + VOID + ) +{ + UINT64 SpiBaseAddress; + + SpiBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + /// + /// Clear BIOSWE bit (SPI PCI Offset DCh [0]) =3D 0b + /// Disable the access to the BIOS space for write cycles + /// + PciSegmentAnd8 ( + SpiBaseAddress + R_SPI_CFG_BC, + (UINT8) (~B_SPI_CFG_BC_WPD) + ); + + /// + /// Check if EISS bit is set + /// + if (((PciSegmentRead8 (SpiBaseAddress + R_SPI_CFG_BC)) & B_SPI_CFG_BC_EI= SS) =3D=3D B_SPI_CFG_BC_EISS) { + PchClearInSmmSts (); + } +} + +/** + Check if it's granted to do flash write. + + @retval TRUE It's secure to do flash write. + @retval FALSE It's not secure to do flash write. +**/ +BOOLEAN +IsSpiFlashWriteGranted ( + VOID + ) +{ + EFI_STATUS Status; + UINT32 CpuIndex; + UINT64 ProcessorId; + + if (mSmmCpuProtocol =3D=3D NULL) { + Status =3D gSmst->SmmLocateProtocol (&gEfiSmmCpuProtocolGuid, NULL, (V= OID **)&mSmmCpuProtocol); + ASSERT_EFI_ERROR (Status); + if (mSmmCpuProtocol =3D=3D NULL) { + return TRUE; + } + } + + for (CpuIndex =3D 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) { + Status =3D mSmmCpuProtocol->ReadSaveState ( + mSmmCpuProtocol, + sizeof (ProcessorId), + EFI_SMM_SAVE_STATE_REGISTER_PROCESSOR_ID, + CpuIndex, + &ProcessorId + ); + // + // If the processor is in SMM at the time the SMI occurred, + // it will return success. Otherwise, EFI_NOT_FOUND is returned. + // + if (EFI_ERROR (Status)) { + return FALSE; + } + } + + return TRUE; +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45907): https://edk2.groups.io/g/devel/message/45907 Mute This Topic: https://groups.io/mt/32918201/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45903+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45903+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001019; cv=none; d=zoho.com; s=zohoarc; b=FNelnxSyvolnkCZiVIRHgdr/TC42mhP5SgiYleIZR28NlVWwvJaFi8Z7PAv+LJcnCnPW5wA9U+fjrICoZgI5g4LxWtvX2VIWgZA/Yw+lIS6tSWNVwvqW+Eo8FdWygUmDBEEDHm8wrvo/m8ppAAh6bEWOEitW6saZt7X+BRdWRV0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001019; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=l/r1BeGErXiLn135iFu8SFy1/j11qbZO8OZNSLhUdMU=; b=Kll6PFolOZXp/eEWM+zCC29f4n8dnR8XzAJXYFtEq8DRdlfFJAX73A4fCv1on5rKCLlE008bNfV8BkG40IrppFmWJhk6+8iyFZABMMT5LFp2WSW8YFkZTE98K8qnxyPoL5MkzltoaKTO5lZRd6DtxJEHzcRStB29U04jVL8Vx5s= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45903+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001019271827.2886206310841; Fri, 16 Aug 2019 17:16:59 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:57 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319318" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:55 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 27/37] CoffeelakeSiliconPkg/Pch: Add PchSmiDispatcher Date: Fri, 16 Aug 2019 17:15:53 -0700 Message-Id: <20190817001603.30632-28-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001018; bh=XaA1PvBQVlFlMCCSKChgV0ccI4YxhkYKpNwh7fIhdSU=; h=Cc:Date:From:Reply-To:Subject:To; b=c+YUiIQhsw5puEYpq3pM22MZS3TMol4omA+lwyTU8O05S2E8AZWz91s59ZJ4HTdXenH SrSHh0Krs99rBWVGczMRw84XTYm4RzWLkz5FfE7ah3uFLHFC7eWUqdOtmBxjpeW0eNON5 iF/4vWbGqFDksHmBG1Th/8ZXSwl4WYF1uJU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Adds the PchSmiDispatcher module. Dispatches PCH SMIs to appropriate SMI handlers registered in various SMM modules. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiDispatch= er.inf | 109 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/IoTrap.h = | 228 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h = | 1031 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmEspi.h = | 342 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmHelpers.= h | 157 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchxSmmHelpers= .h | 105 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/IoTrap.c = | 1264 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiDispatch= .c | 2452 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCore.c = | 911 ++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmEspi.c = | 1595 +++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmGpi.c = | 254 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmHelpers.= c | 358 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmPeriodic= Timer.c | 675 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmPowerBut= ton.c | 83 + Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmSw.c = | 385 +++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmSx.c = | 229 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmUsb.c = | 231 ++ Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchxSmmHelpers= .c | 764 ++++++ 18 files changed, 11173 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmiDispatcher.inf b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatche= r/Smm/PchSmiDispatcher.inf new file mode 100644 index 0000000000..38d5dbeebf --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiDis= patcher.inf @@ -0,0 +1,109 @@ +## @file +# Component description file for the Pch SMI Dispatch Handlers module +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PchSmiDispatcher +FILE_GUID =3D B0D6ED53-B844-43f5-BD2F-61095264E77E +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_SMM_DRIVER +PI_SPECIFICATION_VERSION =3D 1.10 +ENTRY_POINT =3D InitializePchSmmDispatcher + + +[LibraryClasses] +UefiBootServicesTableLib +UefiDriverEntryPoint +IoLib +DebugLib +PcdLib +BaseLib +BaseMemoryLib +HobLib +DevicePathLib +PchCycleDecodingLib +PchPcieRpLib +PchPcrLib +SmmServicesTableLib +ReportStatusCodeLib +PerformanceLib +DxeServicesTableLib +GpioLib +GpioPrivateLib +PchEspiLib +S3BootScriptLib +ConfigBlockLib +PmcPrivateLib +PmcLib +SmiHandlerProfileLib + + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +# Progress Code for S3 Suspend end. +# PROGRESS_CODE_S3_SUSPEND_END =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_S= PECIFIC | 0x00000001)) =3D 0x03078001 +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd +gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType + + +[Sources] +PchSmm.h +PchSmmCore.c +PchSmmHelpers.h +PchSmmHelpers.c +PchxSmmHelpers.h +PchxSmmHelpers.c +PchSmmUsb.c +PchSmmGpi.c +PchSmmPowerButton.c +PchSmmSw.c +PchSmmSx.c +PchSmmPeriodicTimer.c +IoTrap.c +PchSmiDispatch.c +PchSmmEspi.c + + +[Protocols] +gEfiPciRootBridgeIoProtocolGuid ## CONSUMES +gEfiSmmGpiDispatch2ProtocolGuid ## PRODUCES +gEfiSmmSxDispatch2ProtocolGuid ## PRODUCES +gEfiSmmSwDispatch2ProtocolGuid ## PRODUCES +gEfiSmmUsbDispatch2ProtocolGuid ## PRODUCES +gEfiSmmPowerButtonDispatch2ProtocolGuid ## PRODUCES +gEfiSmmPeriodicTimerDispatch2ProtocolGuid ## PRODUCES +gEfiSmmBase2ProtocolGuid ## CONSUMES +gEfiSmmCpuProtocolGuid ## CONSUMES +gEfiSmmReadyToLockProtocolGuid ## CONSUMES +gEfiSmmIoTrapDispatch2ProtocolGuid ## PRODUCES +gPchSmmIoTrapControlGuid ## PRODUCES +gPchTcoSmiDispatchProtocolGuid ## PRODUCES +gPchPcieSmiDispatchProtocolGuid ## PRODUCES +gPchAcpiSmiDispatchProtocolGuid ## PRODUCES +gPchSmiDispatchProtocolGuid ## PRODUCES +gPchEspiSmiDispatchProtocolGuid ## PRODUCES +gPchSmmPeriodicTimerControlGuid ## PRODUCES +gIoTrapExDispatchProtocolGuid ## PRODUCES +gPchNvsAreaProtocolGuid ## CONSUMES + + +[Guids] + + +[Depex] +gEfiPciRootBridgeIoProtocolGuid AND +gEfiPciHostBridgeResourceAllocationProtocolGuid AND ## This is to ensure t= hat PCI MMIO resource has been prepared and available for this driver to al= locate. +gEfiSmmCpuProtocolGuid AND +gEfiSmmBase2ProtocolGuid AND ## This is for SmmServicesTableLib +gPchNvsAreaProtocolGuid + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Io= Trap.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/IoTrap= .h new file mode 100644 index 0000000000..9d6a459ff3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/IoTrap.h @@ -0,0 +1,228 @@ +/** @file + Defines and prototypes for the IoTrap SMM driver + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IO_TRAP_H_ +#define _IO_TRAP_H_ + +// +// Include files +// +#include +#include +#include +#include +#include + +#define IO_TRAP_HANDLER_NUM 4 + +// +// Driver private data +// +#define IO_TRAP_INSTANCE_SIGNATURE SIGNATURE_32 ('I', 'O', 'T', 'P') + +typedef struct { + EFI_HANDLE IoTrapHandle; + /** + The callback linked list for all "merged" IoTrap callbacks. + **/ + LIST_ENTRY CallbackDataBase; + /** + The IoTrap IO range used length tracking for "merged" IoTrap register. + **/ + UINT32 TrapUsedLength; + /** + Determine if IoTrap can be merged with other IoTrap callbacks. + If MergeDisable is TRUE, then there is only one callback function for = one IoTrap register. + If MergeDisable is FALSE, then there are multiple callbacks in the "Ca= llbackDataBase" for one IoTrap register. + **/ + BOOLEAN MergeDisable; + /** + Indicator of the resource tracking in ACPI. + If the registration address is not 0, it's caller's responsibility to = reserve the IO resource in ACPI. + **/ + BOOLEAN ReservedAcpiIoResource; + /** + Dispatcher for each IoTrap register. + **/ + PCH_SMI_DISPATCH_CALLBACK CallbackDispatcher; +} IO_TRAP_ENTRY_ATTRIBUTES; + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL EfiSmmIoTrapDispatchProtocol; + PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PchSmmIoTrapControlProtocol; = ///< Protocol for runtime control the IoTrap state + IO_TRAP_EX_DISPATCH_PROTOCOL IoTrapExDispatchProtocol; = ///< Protocol for IoTrap Extension + IO_TRAP_ENTRY_ATTRIBUTES Entry[IO_TRAP_HANDLER_NUM]; +} IO_TRAP_INSTANCE; + +#define IO_TRAP_INSTANCE_FROM_THIS(a) CR (a, IO_TRAP_INSTANCE, EfiSmmIoTra= pDispatchProtocol, IO_TRAP_INSTANCE_SIGNATURE) + +/// +/// "IOTRAP" RECORD +/// Linked list data structures +/// +#define IO_TRAP_RECORD_SIGNATURE SIGNATURE_32 ('I', 'T', 'R', 'C') + +typedef struct _IO_TRAP_RECORD { + UINT32 Signature; + LIST_ENTRY Link; + IO_TRAP_EX_REGISTER_CONTEXT Context; + /** + The callback function of IoTrap protocol. + This also indicate it's the record for IoTrapProtocol. + Only one of IoTrapCallback or IoTrapExCallback is valid at a time. + **/ + EFI_SMM_HANDLER_ENTRY_POINT2 IoTrapCallback; + /** + The callback function of IoTrapEx protocol + This also indicate it's the record for IoTrapExProtocol. + Only one of IoTrapCallback or IoTrapExCallback is valid at a time. + **/ + IO_TRAP_EX_DISPATCH_CALLBACK IoTrapExCallback; + UINT8 IoTrapNumber; +} IO_TRAP_RECORD; + +#define IO_TRAP_RECORD_FROM_LINK(_record) CR (_record, IO_TRAP_RECORD, Lin= k, IO_TRAP_RECORD_SIGNATURE) + +// +// Prototypes +// +/** + The IoTrap module abstracts PCH I/O trapping capabilities for other driv= ers. + This driver manages the limited I/O trap resources. + + @param[in] ImageHandle Image handle for this driver image + + @retval EFI_SUCCESS Driver initialization completed su= ccessfully +**/ +EFI_STATUS +EFIAPI +InstallIoTrap ( + IN EFI_HANDLE ImageHandle + ); + +/** + Register a new IO Trap SMI dispatch function with a parent SMM driver. + The caller will provide information about the IO trap characteristics via + the context. This includes base address, length, read vs. r/w, etc. + This function will autoallocate IO base address from a common pool if th= e base address is 0, + and the RegisterContext Address field will be updated. + The service will not perform GCD allocation if the base address is non-z= ero. + In this case, the caller is responsible for the existence and allocation= of the + specific IO range. + This function looks for the suitable handler and Register a new IoTrap h= andler + if the IO Trap handler is not used. It also enable the IO Trap Range to = generate + SMI. + + @param[in] This Pointer to the EFI_SMM_IO_TRAP_DISPATCH= 2_PROTOCOL instance. + @param[in] DispatchFunction Pointer to dispatch function to be invok= ed for + this SMI source. + @param[in, out] RegisterContext Pointer to the dispatch function's conte= xt. + The caller fills this context in before = calling + the register function to indicate to the= register + function the IO trap SMI source for whic= h the dispatch + function should be invoked. This may no= t be NULL. + If the registration address is not 0, it= 's caller's responsibility + to reserve the IO resource in ACPI. + @param[out] DispatchHandle Handle of dispatch function, for when in= terfacing + with the parent SMM driver, will be the = address of linked + list link in the call back record. This= may not be NULL. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + registered and the SMI source has been e= nabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI = source. + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available + @retval EFI_INVALID_PARAMETER Address requested is already in use. + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLo= ck event has been triggered +**/ +EFI_STATUS +EFIAPI +IoTrapRegister ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN OUT EFI_SMM_IO_TRAP_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver. + + @param[in] This Pointer to the EFI_SMM_IO_TRAP_DISPATCH= 2_PROTOCOL instance. + @param[in] DispatchHandle Handle of dispatch function to deregiste= r. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + unregistered and the SMI source has been= disabled + if there are no other registered child d= ispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLo= ck event has been triggered +**/ +EFI_STATUS +EFIAPI +IoTrapUnRegister ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + This I/O Trap SMI handler invokes the ACPI reference code to handle the = SMI. + It currently assumes it owns all of the IO trap SMI. + + @param[in] DispatchHandle Not used + +**/ +VOID +EFIAPI +IoTrapCallback ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Pause IoTrap callback function. + + This function disables the SMI enable of IoTrap according to the Dispatc= hHandle, + which is returned by IoTrap callback registration. It only supports the = DispatchHandle + with MergeDisable TRUE and address not zero. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_P= ROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change st= ate. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED. +**/ +EFI_STATUS +EFIAPI +IoTrapControlPause ( + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Resume IoTrap callback function. + + This function enables the SMI enable of IoTrap according to the Dispatch= Handle, + which is returned by IoTrap callback registration. It only supports the = DispatchHandle + with MergeDisable TRUE and address not zero. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_P= ROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change st= ate. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady RESUMED. +**/ +EFI_STATUS +EFIAPI +IoTrapControlResume ( + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This, + IN EFI_HANDLE DispatchHandle + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmm.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm= .h new file mode 100644 index 0000000000..1906e32b5a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmm.h @@ -0,0 +1,1031 @@ +/** @file + Prototypes and defines for the PCH SMM Dispatcher. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SMM_H_ +#define _PCH_SMM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "IoTrap.h" + +#define EFI_BAD_POINTER 0xAFAFAFAFAFAFAFAFULL + +extern BOOLEAN mReadyToLock; + +/// +/// Define an enumeration for all the supported protocols +/// +#define PCH_SMM_PROTOCOL_TYPE_MAX 6 + +typedef enum { + UsbType, + SxType, + SwType, + GpiType, + PowerButtonType, + PeriodicTimerType, + PchSmiDispatchType, + PchSmmProtocolTypeMax +} PCH_SMM_PROTOCOL_TYPE; + +/// +/// Define all the supported types of PCH SMI +/// +typedef enum { + PchTcoSmiMchType, + PchTcoSmiTcoTimeoutType, + PchTcoSmiOsTcoType, + PchTcoSmiNmiType, + PchTcoSmiIntruderDetectType, + PchTcoSmiSpiBiosWpType, + PchTcoSmiLpcBiosWpType, + PchTcoSmiNewCenturyType, + PchPcieSmiRpHotplugType, + PchPcieSmiRpLinkActiveType, + PchPcieSmiRpLinkEqType, + PchAcpiSmiPmeType, + PchAcpiSmiPmeB0Type, + PchAcpiSmiRtcAlarmType, + PchAcpiSmiTmrOverflowType, + PchEspiSmiEspiSlaveType, + PchSmiSerialIrqType, + PchSmiMcSmiType, + PchSmiSmBusType, + PchSmiSpiAsyncType, + PchIoTrapSmiType ///< internal SMI type +} PCH_SMI_TYPES; + +/// +/// Generic funciton pointer to cover all Pch SMI function pointer types +/// +typedef +VOID +(EFIAPI *PCH_SMI_CALLBACK_FUNCTIONS) ( + IN EFI_HANDLE DispatchHandle, + ... + ); + + +/// +/// SPECIFYING A REGISTER +/// We want a general way of referring to addresses. For this case, we'll= only +/// need addresses in the ACPI table (and the TCO entries within the ACPI = table). +/// However, it's interesting to consider what it would take to support ot= her types +/// of addresses. To address Will's concern, I think it prudent to accomm= odate it +/// early on in the design. +/// +/// Addresses we need to consider: +/// +/// Type: Required: +/// I/O Yes +/// ACPI (special case of I/O) Only if we want to +/// TCO (special case of I/O) Only if we want to +/// GPIO (special case of MMIO) Only if we want to +/// Memory (or Memory Mapped I/O) Only if we want to +/// PCIE Yes, for BiosWp +/// +typedef enum { + /// + /// IO_ADDR_TYPE, /// unimplemented + /// + ACPI_ADDR_TYPE, + TCO_ADDR_TYPE, + /// + /// MEMORY_ADDR_TYPE, /// unimplemented + /// + GPIO_ADDR_TYPE, + MEMORY_MAPPED_IO_ADDRESS_TYPE, + PCIE_ADDR_TYPE, + PCR_ADDR_TYPE, + NUM_ADDR_TYPES, ///< count of items in this enum + PCH_SMM_ADDR_TYPE_NULL =3D -1 ///< sentinel to indicate NULL or = to signal end of arrays +} ADDR_TYPE; + +// +// Assumption: 32-bits -- enum's evaluate to integer +// Assumption: This code will only run on IA-32. Justification: IA-64 doe= sn't have SMIs. +// We don't have to worry about 64-bit addresses. +// Typedef the size of addresses in case the numbers I'm using are wrong o= r in case +// this changes. This is a good idea because PCI_ADDR will change, for ex= ample, when +// we add support for PciExpress. +// +typedef UINT16 IO_ADDR; +typedef IO_ADDR ACPI_ADDR; ///< can omit +typedef IO_ADDR TCO_ADDR; ///< can omit +typedef UINTN MEM_ADDR; +typedef MEM_ADDR *MEMORY_MAPPED_IO_ADDRESS; +typedef MEM_ADDR *GPIO_ADDR; +typedef union { + UINT32 Raw; + struct { + UINT32 Reg: 16; + UINT32 Fnc: 3; + UINT32 Dev: 5; + UINT32 Bus: 8; + } Fields; +} PCIE_ADDR; + +typedef union { + UINT32 Raw; + struct { + UINT16 Offset; + UINT8 Pid; + UINT8 Base; + } Fields; +} PCR_ADDR; + +typedef struct { + ADDR_TYPE Type; + union { + /// + /// used to initialize during declaration/definition + /// + UINT32 raw; + + /// + /// used to access useful data + /// + IO_ADDR io; + ACPI_ADDR acpi; + TCO_ADDR tco; + GPIO_ADDR gpio; + MEM_ADDR mem; + MEMORY_MAPPED_IO_ADDRESS Mmio; + PCIE_ADDR pcie; + PCR_ADDR Pcr; + + } Data; + +} PCH_SMM_ADDRESS; + +/// +/// SPECIFYING BITS WITHIN A REGISTER +/// Here's a struct that helps us specify a source or enable bit. +/// +typedef struct { + PCH_SMM_ADDRESS Reg; + UINT8 SizeInBytes; ///< of the register + UINT8 Bit; +} PCH_SMM_BIT_DESC; + +// +// Sometimes, we'll have bit descriptions that are unused. It'd be great = to have a +// way to easily identify them: +// +#define IS_BIT_DESC_NULL(BitDesc) ((BitDesc).Reg.Type =3D=3D PCH_SMM_ADD= R_TYPE_NULL) ///< "returns" true when BitDesc is NULL +#define NULL_THIS_BIT_DESC(BitDesc) ((BitDesc).Reg.Type =3D PCH_SMM_ADDR_T= YPE_NULL) ///< will "return" an integer w/ value of 0 +#define NULL_BIT_DESC_INITIALIZER \ + { \ + { \ + PCH_SMM_ADDR_TYPE_NULL, \ + { \ + 0 \ + } \ + }, \ + 0, 0 \ + } +// +// I'd like a type to specify the callback's Sts & En bits because they'll +// be commonly used together: +// +#define NUM_EN_BITS 2 +#define NUM_STS_BITS 1 + +// +// Flags +// +typedef UINT8 PCH_SMM_SOURCE_FLAGS; + +// +// Flags required to describe the event source +// +#define PCH_SMM_NO_FLAGS 0 +#define PCH_SMM_SCI_EN_DEPENDENT 1 + +typedef struct { + PCH_SMM_SOURCE_FLAGS Flags; + PCH_SMM_BIT_DESC En[NUM_EN_BITS]; ///< Describes the enable bit(= s) for the SMI event + PCH_SMM_BIT_DESC Sts[NUM_STS_BITS]; ///< Describes the secondary s= tatus bit for the SMI event. Might be the same as TopLevelSmi + PCH_SMM_BIT_DESC PmcSmiSts; ///< Refereing to the top leve= l status bit in PMC SMI_STS, i.e. R_PCH_SMI_STS +} PCH_SMM_SOURCE_DESC; + +/// +/// Used to initialize null source descriptor +/// +#define NULL_SOURCE_DESC_INITIALIZER \ + { \ + PCH_SMM_NO_FLAGS, \ + { \ + NULL_BIT_DESC_INITIALIZER, NULL_BIT_DESC_INITIALIZER \ + }, \ + { \ + NULL_BIT_DESC_INITIALIZER \ + }, \ + NULL_BIT_DESC_INITIALIZER \ + } + +/// +/// CHILD CONTEXTS +/// To keep consistent w/ the architecture, we'll need to provide the cont= ext +/// to the child when we call its callback function. After talking with W= ill, +/// we agreed that we'll need functions to "dig" the context out of the ha= rdware +/// in many cases (Sx, Trap, Gpi, etc), and we'll need a function to compa= re those +/// contexts to prevent unnecessary dispatches. I'd like a general type f= or these +/// "GetContext" functions, so I'll need a union of all the protocol conte= xts for +/// our internal use: +/// +typedef union { + // + // (in no particular order) + // + EFI_SMM_SX_REGISTER_CONTEXT Sx; + EFI_SMM_PERIODIC_TIMER_REGISTER_CONTEXT PeriodicTimer; + EFI_SMM_SW_REGISTER_CONTEXT Sw; + EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT PowerButton; + EFI_SMM_USB_REGISTER_CONTEXT Usb; + EFI_SMM_GPI_REGISTER_CONTEXT Gpi; +} PCH_SMM_CONTEXT; + +/// +/// Misc data for PchDispatcher usage. +/// For PeriodicTimer, since the ElapsedTime is removed from EFI_SMM_PERIO= DIC_TIMER_REGISTER_CONTEXT of EDKII, +/// and PchDispatcher needs it for every record. Thus move it here to supp= ort ElapsedTime. +/// +typedef union { + UINTN ElapsedTime; +} PCH_SMM_MISC_DATA; + +// +// Assumption: PeriodicTimer largest at 3x64-bits or 24 bytes +// +typedef struct _DATABASE_RECORD DATABASE_RECORD; + +/// +/// Assumption: the GET_CONTEXT function will be as small and simple as po= ssible. +/// Assumption: We don't need to pass in an enumeration for the protocol b= ecause each +/// GET_CONTEXT function is written for only one protocol. +/// We also need a function to compare contexts to see if the child should= be dispatched +/// In addition, we need a function to acquire CommBuffer and CommBufferSi= ze for +/// dispatch callback function of EDKII native support. +/// +typedef +VOID +(EFIAPI *GET_CONTEXT) ( + IN DATABASE_RECORD * Record, + OUT PCH_SMM_CONTEXT * Context + ); + +typedef +BOOLEAN +(EFIAPI *CMP_CONTEXT) ( + IN PCH_SMM_CONTEXT * Context1, + IN PCH_SMM_CONTEXT * Context2 + ); + +typedef +VOID +(EFIAPI *GET_COMMBUFFER) ( + IN DATABASE_RECORD * Record, + OUT VOID **CommBuffer, + OUT UINTN * CommBufferSize + ); + +/// +/// Finally, every protocol will require a "Get Context" and "Compare Cont= ext" call, so +/// we may as well wrap that up in a table, too. +/// +typedef struct { + GET_CONTEXT GetContext; + CMP_CONTEXT CmpContext; + GET_COMMBUFFER GetCommBuffer; +} CONTEXT_FUNCTIONS; + +extern CONTEXT_FUNCTIONS ContextFunctions[PCH_SMM_PROTOCOL_TYPE_M= AX]; + +/// +/// MAPPING CONTEXT TO BIT DESCRIPTIONS +/// I'd like to have a general approach to mapping contexts to bit descrip= tions. +/// Sometimes, we'll find that we can use table lookups or constant assign= ments; +/// other times, we'll find that we'll need to use a function to perform t= he mapping. +/// If we define a macro to mask that process, we'll never have to change = the code. +/// I don't know if this is desirable or not -- if it isn't, then we can g= et rid +/// of the macros and just use function calls or variable assignments. Do= esn't matter +/// to me. +/// Mapping complex contexts requires a function +/// + +/** + Maps a USB context to a source description. + + @param[in] Context The context we need to map. Type must b= e USB. + @param[out] SrcDesc The source description that corresponds = to the given context. + +**/ +VOID +MapUsbToSrcDesc ( + IN PCH_SMM_CONTEXT *Context, + OUT PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + Figure out which timer the child is requesting and + send back the source description + + @param[in] DispatchContext The pointer to the Dispatch Context inst= ances + @param[out] SrcDesc The pointer to the source description + +**/ +VOID +MapPeriodicTimerToSrcDesc ( + IN PCH_SMM_CONTEXT *DispatchCon= text, + OUT PCH_SMM_SOURCE_DESC *SrcDesc + ); + +// +// Mapping simple contexts can be done by assignment or lookup table +// +extern CONST PCH_SMM_SOURCE_DESC mSxSourceDesc; +extern CONST PCH_SMM_SOURCE_DESC mPowerButtonSourceDesc; +extern CONST PCH_SMM_SOURCE_DESC mSrcDescNewCentury; +extern CONST PCH_SMM_SOURCE_DESC mGpiSourceDescTemplate; + +/// +/// For PCHx, APMC is UINT8 port, so the MAX SWI Value is 0xFF. +/// +#define MAXIMUM_SWI_VALUE 0xFF +/// +/// Open: Need to make sure this kind of type cast will actually work. +/// May need an intermediate form w/ two VOID* arguments. I'll figure +/// that out when I start compiling. +/// +typedef +VOID +(EFIAPI *PCH_SMM_CLEAR_SOURCE) ( + CONST PCH_SMM_SOURCE_DESC * SrcDesc + ); + +/// +/// "DATABASE" RECORD +/// Linked list data structures +/// +#define DATABASE_RECORD_SIGNATURE SIGNATURE_32 ('D', 'B', 'R', 'C') + +struct _DATABASE_RECORD { + UINT32 Signature; + LIST_ENTRY Link; + BOOLEAN Processed; + /// + /// Status and Enable bit description + /// + PCH_SMM_SOURCE_DESC SrcDesc; + + /// + /// Callback function + /// + EFI_SMM_HANDLER_ENTRY_POINT2 Callback; + PCH_SMM_CONTEXT ChildContext; + UINTN ContextSize; + + /// + /// Special handling hooks -- init them to NULL if unused/unneeded + /// + PCH_SMM_CLEAR_SOURCE ClearSource; + + /// + /// Functions required to make callback code general + /// + CONTEXT_FUNCTIONS ContextFunctions; + + /// + /// The protocol that this record dispatches + /// + PCH_SMM_PROTOCOL_TYPE ProtocolType; + + /// + /// Misc data for private usage + /// + PCH_SMM_MISC_DATA MiscData; + + /// + /// PCH SMI callback function + /// + PCH_SMI_CALLBACK_FUNCTIONS PchSmiCallback; + /// + /// Indicate the PCH SMI types. + /// + PCH_SMI_TYPES PchSmiType; +}; + +#define DATABASE_RECORD_FROM_LINK(_record) CR (_record, DATABASE_RECORD, = Link, DATABASE_RECORD_SIGNATURE) +#define DATABASE_RECORD_FROM_CHILDCONTEXT(_record) CR (_record, DATABASE_= RECORD, ChildContext, DATABASE_RECORD_SIGNATURE) + +/// +/// HOOKING INTO THE ARCHITECTURE +/// +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_GENERIC_REGISTER) ( + IN VOID **This, + IN VOID *DispatchFunction, + IN VOID *DispatchContext, + OUT EFI_HANDLE *DispatchHandle + ); +typedef +EFI_STATUS +(EFIAPI *PCH_SMM_GENERIC_UNREGISTER) ( + IN VOID **This, + IN EFI_HANDLE DispatchHandle + ); + +/// +/// Define a memory "stamp" equivalent in size and function to most of the= protocols +/// +typedef struct { + PCH_SMM_GENERIC_REGISTER Register; + PCH_SMM_GENERIC_UNREGISTER Unregister; + UINTN Extra1; + UINTN Extra2; ///< may not need this one +} PCH_SMM_GENERIC_PROTOCOL; + +/** + Register a child SMI dispatch function with a parent SMM driver. + + @param[in] This Pointer to the PCH_SMM_GENERIC_PROTOCOL = instance. + @param[in] DispatchFunction Pointer to dispatch function to be invok= ed for this SMI source. + @param[in] DispatchContext Pointer to the dispatch function's conte= xt. + @param[out] DispatchHandle Handle of dispatch function, for when in= terfacing + with the parent SMM driver, will be the = address of linked + list link in the call back record. + + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databas= e record + @retval EFI_INVALID_PARAMETER The input parameter is invalid + @retval EFI_SUCCESS The dispatch function has been successfu= lly + registered and the SMI source has been e= nabled. +**/ +EFI_STATUS +EFIAPI +PchPiSmmCoreRegister ( + IN PCH_SMM_GENERIC_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN PCH_SMM_CONTEXT *DispatchContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchPiSmmCoreUnRegister ( + IN PCH_SMM_GENERIC_PROTOCOL *This, + IN EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver. + + @param[in] This Pointer to the PCH_SMM_GENERIC_PROTOCOL = instance. + @param[in] DispatchHandle Handle of dispatch function to deregiste= r. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + unregistered and the SMI source has been= disabled + if there are no other registered child d= ispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. +**/ +EFI_STATUS +EFIAPI +PchSmmCoreUnRegister ( + IN PCH_SMM_GENERIC_PROTOCOL *This, + IN EFI_HANDLE *DispatchHandle + ); + +typedef union { + PCH_SMM_GENERIC_PROTOCOL Generic; + EFI_SMM_USB_DISPATCH2_PROTOCOL Usb; + EFI_SMM_SX_DISPATCH2_PROTOCOL Sx; + EFI_SMM_SW_DISPATCH2_PROTOCOL Sw; + EFI_SMM_GPI_DISPATCH2_PROTOCOL Gpi; + EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL PowerButton; + EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL PeriodicTimer; +} PCH_SMM_PROTOCOL; + +/// +/// Define a structure to help us identify the generic protocol +/// +#define PROTOCOL_SIGNATURE SIGNATURE_32 ('P', 'R', 'O', 'T') + +typedef struct { + UINTN Signature; + + PCH_SMM_PROTOCOL_TYPE Type; + EFI_GUID *Guid; + PCH_SMM_PROTOCOL Protocols; +} PCH_SMM_QUALIFIED_PROTOCOL; + +#define QUALIFIED_PROTOCOL_FROM_GENERIC(_generic) \ + CR ( \ + _generic, \ + PCH_SMM_QUALIFIED_PROTOCOL, \ + Protocols, \ + PROTOCOL_SIGNATURE \ + ) + +/// +/// Create private data for the protocols that we'll publish +/// +typedef struct { + LIST_ENTRY CallbackDataBase; + EFI_HANDLE SmiHandle; + EFI_HANDLE InstallMultProtHandle; + PCH_SMM_QUALIFIED_PROTOCOL Protocols[PCH_SMM_PROTOCOL_TYPE_MAX]; +} PRIVATE_DATA; + +extern PRIVATE_DATA mPrivateData; +extern UINT16 mAcpiBaseAddr; +extern UINT16 mTcoBaseAddr; + +/** + The internal function used to create and insert a database record + + @param[in] InsertRecord Record to insert to database. + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. +**/ +EFI_STATUS +SmmCoreInsertRecord ( + IN DATABASE_RECORD *NewRecord, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Get the Sleep type + + @param[in] Record No use + @param[out] Context The context that includes SLP_TYP bits t= o be filled +**/ +VOID +EFIAPI +SxGetContext ( + IN DATABASE_RECORD *Record, + OUT PCH_SMM_CONTEXT *Context + ); + +/** + Register a child SMI source dispatch function for the specified software= SMI. + + This service registers a function (DispatchFunction) which will be calle= d when the software + SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On r= eturn, + DispatchHandle contains a unique handle which may be used later to unreg= ister the function + using UnRegister(). + + @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PRO= TOCOL instance. + @param[in] DispatchFunction Function to register for handler when t= he specified software + SMI is generated. + @param[in, out] RegisterContext Pointer to the dispatch function's cont= ext. + The caller fills this context in before= calling + the register function to indicate to th= e register + function which Software SMI input value= the + dispatch function should be invoked for. + @param[out] DispatchHandle Handle generated by the dispatcher to t= rack the + function instance. + + @retval EFI_SUCCESS The dispatch function has been successful= ly + registered and the SMI source has been en= abled. + @retval EFI_DEVICE_ERROR The SW driver was unable to enable the SM= I source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The SW SMI in= put value + is not within a valid range or is already= in use. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or SMM= ) to manage this + child. + @retval EFI_OUT_OF_RESOURCES A unique software SMI value could not be = assigned + for this dispatch. +**/ +EFI_STATUS +EFIAPI +PchSwSmiRegister ( + IN EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN EFI_SMM_SW_REGISTER_CONTEXT *DispatchContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function for the specified softwa= re SMI. + + This service removes the handler associated with DispatchHandle so that = it will no longer be + called in response to a software SMI. + + @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PROTO= COL instance. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successful= ly unregistered. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +EFI_STATUS +EFIAPI +PchSwSmiUnRegister ( + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + Init required protocol for Pch Sw Dispatch protocol. +**/ +VOID +PchSwDispatchInit ( + VOID + ); + +/** + Check whether sleep type of two contexts match + + @param[in] Context1 Context 1 that includes sleep type 1 + @param[in] Context2 Context 2 that includes sleep type 2 + + @retval FALSE Sleep types match + @retval TRUE Sleep types don't match +**/ +BOOLEAN +EFIAPI +SxCmpContext ( + IN PCH_SMM_CONTEXT *Context1, + IN PCH_SMM_CONTEXT *Context2 + ); + +/** + Update the elapsed time from the Interval data of DATABASE_RECORD + + @param[in] Record The pointer to the DATABASE_RECORD. + @param[out] HwContext The Context to be updated. +**/ +VOID +EFIAPI +PeriodicTimerGetContext ( + IN DATABASE_RECORD *Record, + OUT PCH_SMM_CONTEXT *Context + ); + +/** + Check whether Periodic Timer of two contexts match + + @param[in] Context1 Context 1 that includes Periodic Timer 1 + @param[in] Context2 Context 2 that includes Periodic Timer 2 + + @retval FALSE Periodic Timer match + @retval TRUE Periodic Timer don't match +**/ +BOOLEAN +EFIAPI +PeriodicTimerCmpContext ( + IN PCH_SMM_CONTEXT *Context1, + IN PCH_SMM_CONTEXT *Context2 + ); + +/** + Gather the CommBuffer information of SmmPeriodicTimerDispatch2. + + @param[in] Record No use + @param[out] CommBuffer Point to the CommBuffer structure + @param[out] CommBufferSize Point to the Size of CommBuffer structure +**/ +VOID +EFIAPI +PeriodicTimerGetCommBuffer ( + IN DATABASE_RECORD *Record, + OUT VOID **CommBuffer, + OUT UINTN *CommBufferSize + ); + +/** + Get the power button status. + + @param[in] Record The pointer to the DATABASE_RECORD. + @param[out] Context Calling context from the hardware, will = be updated with the current power button status. +**/ +VOID +EFIAPI +PowerButtonGetContext ( + IN DATABASE_RECORD *Record, + OUT PCH_SMM_CONTEXT *Context + ); + +/** + Check whether Power Button status of two contexts match + + @param[in] Context1 Context 1 that includes Power Button sta= tus 1 + @param[in] Context2 Context 2 that includes Power Button sta= tus 2 + + @retval FALSE Power Button status match + @retval TRUE Power Button status don't match +**/ +BOOLEAN +EFIAPI +PowerButtonCmpContext ( + IN PCH_SMM_CONTEXT *Context1, + IN PCH_SMM_CONTEXT *Context2 + ); + +/** + This function is responsible for calculating and enabling any timers tha= t are required + to dispatch messages to children. The SrcDesc argument isn't acutally us= ed. + + @param[in] SrcDesc Pointer to the PCH_SMM_SOURCE_DESC insta= nce. +**/ +VOID +EFIAPI +PchSmmPeriodicTimerClearSource ( + IN CONST PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + This services returns the next SMI tick period that is supported by the = chipset. + The order returned is from longest to shortest interval period. + + @param[in] This Pointer to the EFI_SMM_PERIODIC_TIMER_DI= SPATCH2_PROTOCOL instance. + @param[in, out] SmiTickInterval Pointer to pointer of the next shorter S= MI interval period that is supported by the child. + + @retval EFI_SUCCESS The service returned successfully. + @retval EFI_INVALID_PARAMETER The parameter SmiTickInterval is invalid. +**/ +EFI_STATUS +PchSmmPeriodicTimerDispatchGetNextShorterInterval ( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN OUT UINT64 **SmiTickInterval + ); + +/** + Install PCH SMM periodic timer control protocol + + @param[in] Handle handle for this driver + + @retval EFI_SUCCESS Driver initialization completed su= ccessfully +**/ +EFI_STATUS +EFIAPI +InstallPchSmmPeriodicTimerControlProtocol ( + IN EFI_HANDLE Handle + ); + +/** + When we get an SMI that indicates that we are transitioning to a sleep s= tate, + we need to actually transition to that state. We do this by disabling t= he + "SMI on sleep enable" feature, which generates an SMI when the operating= system + tries to put the system to sleep, and then physically putting the system= to sleep. +**/ +VOID +PchSmmSxGoToSleep ( + VOID + ); + +/** + Install protocols of PCH specifics SMI types, including + PCH TCO SMI types, PCH PCIE SMI types, PCH ACPI SMI types, PCH MISC SMI = types. + + @retval the result of protocol installation +**/ +EFI_STATUS +InstallPchSmiDispatchProtocols ( + VOID + ); + +/** + The function to dispatch all callback function of PCH SMI types. + + @retval EFI_SUCCESS Function successfully completed + @retval EFI_UNSUPPORTED no +**/ +EFI_STATUS +PchSmiTypeCallbackDispatcher ( + IN DATABASE_RECORD *Record + ); + +/** + The register function used to register SMI handler of IoTrap event. + This is internal function and only used by Iotrap module. + + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[in] IoTrapIndex Index number of IOTRAP register + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. +**/ +EFI_STATUS +PchInternalIoTrapSmiRegister ( + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + IN UINTN IoTrapIndex, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. +**/ +EFI_STATUS +PchInternalIoTrapSmiUnRegister ( + IN EFI_HANDLE DispatchHandle + ); + +/** + Register an eSPI SMI handler based on the type + + @param[in] DispatchFunction Callback in an event of eSPI SMI + @param[in] PchSmiTypes The eSPI type published by PchSmiDis= patch + @param[out] DispatchHandle The callback handle + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descripti= on + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database r= ecord + @retval EFI_SUCCESS Registration is successful. +**/ +EFI_STATUS +PchInternalEspiSmiRegister ( + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + IN PCH_SMI_TYPES PchSmiTypes, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister an eSPI SMI handler + + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. +**/ +EFI_STATUS +PchInternalEspiSmiUnRegister ( + IN EFI_HANDLE DispatchHandle + ); + +/** + The internal function used to create and insert a database record + for SMI record of Pch Smi types. + + @param[in] SrcDesc The pointer to the SMI source desc= ription + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[in] PchSmiType Specific SMI type of PCH SMI + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. +**/ +EFI_STATUS +PchSmiRecordInsert ( + IN CONST PCH_SMM_SOURCE_DESC *SrcDesc, + IN PCH_SMI_CALLBACK_FUNCTIONS DispatchFunction, + IN PCH_SMI_TYPES PchSmiType, + OUT EFI_HANDLE *DispatchHandle + ); + +extern CONST PCH_SMM_SOURCE_DESC mSrcDescSerialIrq; +extern CONST PCH_SMM_SOURCE_DESC mSrcDescLpcBiosWp; + +/** + Clear the TCO SMI status bit and block after the SMI handling is done + + @param[in] SrcDesc Pointer to the PCH SMI source desc= ription table + +**/ +VOID +EFIAPI +PchTcoSmiClearSourceAndBlock ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + Clear the TCO SMI status bit after the SMI handling is done + + @param[in] SrcDesc Pointer to the PCH SMI source desc= ription table + +**/ +VOID +EFIAPI +PchTcoSmiClearSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + Initialize Source descriptor structure + + @param[in] SrcDesc Pointer to the PCH SMI source desc= ription table +**/ +VOID +EFIAPI +NullInitSourceDesc ( + PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + The register function used to register SMI handler of GPI SMI event. + + @param[in] This Pointer to the EFI_SMM_GPI_DISPATCH2_PROT= OCOL instance. + @param[in] DispatchFunction Function to register for handler when the= specified GPI causes an SMI. + @param[in] RegisterContext Pointer to the dispatch function's contex= t. + The caller fills this context in before c= alling + the register function to indicate to the = register + function the GPI(s) for which the dispatc= h function + should be invoked. + @param[out] DispatchHandle Handle generated by the dispatcher to tra= ck the + function instance. + + @retval EFI_SUCCESS The dispatch function has been successful= ly + registered and the SMI source has been en= abled. + @retval EFI_ACCESS_DENIED Register is not allowed + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The GPI input= value + is not within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or SMM= ) to manage this child. +**/ +EFI_STATUS +EFIAPI +PchGpiSmiRegister ( + IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN CONST EFI_SMM_GPI_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + Unregister a GPI SMI source dispatch function with a parent SMM driver + + @param[in] This Pointer to the EFI_SMM_GPI_DISPATCH2_PRO= TOCOL instance. + @param[in] DispatchHandle Handle of dispatch function to deregiste= r. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + unregistered and the SMI source has been= disabled + if there are no other registered child d= ispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. +**/ +EFI_STATUS +EFIAPI +PchGpiSmiUnRegister ( + IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmEspi.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmEspi.h new file mode 100644 index 0000000000..193eed6bac --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmEsp= i.h @@ -0,0 +1,342 @@ +/** @file + eSPI SMI Dispatch header + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_SMM_ESPI_H_ +#define _PCH_SMM_ESPI_H_ + +#include "PchSmmHelpers.h" + +#define ESPI_SMI_INSTANCE_SIGNATURE SIGNATURE_32 ('E', 'S', 'P', 'I') +#define ESPI_SMI_RECORD_SIGNATURE SIGNATURE_32 ('E', 'S', 'R', 'C') + +#define ESPI_INSTANCE_FROM_THIS(_this) CR (_this, ESPI_SMI_INSTANCE, = EfiEspiSmiDispatchProtocol, ESPI_SMI_INSTANCE_SIGNATURE) +#define ESPI_RECORD_FROM_LINK(_link) CR (_link, ESPI_SMI_RECORD, Li= nk, ESPI_SMI_RECORD_SIGNATURE) + +typedef enum { + EspiBiosWrProtect, ///< BIOS Write Protect + EspiSerialIrq, ///< eSPI Master Asserted SMI + EspiPmc, ///< eSPI PMC SMI + EspiTopLevelTypeMax +} ESPI_TOP_LEVEL_TYPE; + +typedef enum { + BiosWrProtect, ///< BIOS Write Protect + BiosWrReport, ///< Peripheral Channel BIOS Write Protect + PcNonFatalErr, ///< Peripheral Channel Non Fatal Error + PcFatalErr, ///< Peripheral Channel Fatal Error + VwNonFatalErr, ///< Virtual Wire Non Fatal Error + VwFatalErr, ///< Virtual Wire Fatal Error + FlashNonFatalErr, ///< Flash Channel Non Fatal Error + FlashFatalErr, ///< Flash Channel Fatal Error + LnkType1Err, ///< Link Error + EspiSlaveSmi, ///< Espi Slave SMI + EspiSmiTypeMax +} ESPI_SMI_TYPE; + +/// +/// This is used to classify ESPI_SMI_TYPE to ESPI_TOP_LEVEL_TYPE. +/// Used during dispatching and unregistering +/// +typedef struct { + ESPI_SMI_TYPE Start; + ESPI_SMI_TYPE End; +} ESPI_SMI_TYPE_BARRIER; + +typedef struct _ESPI_SMI_INSTANCE { + /// + /// Signature associated with this instance + /// + UINT32 Signature; + /// + /// EFI_HANDLE acquired when installing PchEspiSmiDispatchProtocol + /// + EFI_HANDLE Handle; + /// + /// The protocol to register or unregister eSPI SMI callbacks + /// + PCH_ESPI_SMI_DISPATCH_PROTOCOL PchEspiSmiDispatchProtocol; + /// + /// The handle acquired when registering eSPI SMI callback to PchSmiDisp= atch + /// + EFI_HANDLE PchSmiEspiHandle[EspiTopLevelTypeMax]; + /// + /// The linked list for record database. + /// + LIST_ENTRY CallbackDataBase[EspiSmiTypeMax]; + /// + /// This is an internal counter to track the number of eSPI master event= s have been registered. + /// When unregistering, we can disable the SMI if the counter is zero + /// + UINTN EspiSmiEventCounter[EspiSmiTypeMax]; + /// + /// Instance of barrier + /// + CONST ESPI_SMI_TYPE_BARRIER Barrier[EspiTopLevelTypeMax]; +} ESPI_SMI_INSTANCE; + +typedef struct _ESPI_DESCRIPTOR { + PCH_SMM_ADDRESS Address; + UINT32 SourceIsActiveAndMask; + UINT32 SourceIsActiveValue; + UINT32 ClearStatusAndMask; + UINT32 ClearStatusOrMask; +} ESPI_DESCRIPTOR; + +/// +/// A simple record to store the callbacks associated with an eSPI SMI sou= rce +/// +typedef struct _ESPI_SMI_RECORD { + UINT32 Signature; + LIST_ENTRY Link; + PCH_ESPI_SMI_DISPATCH_CALLBACK Callback; +} ESPI_SMI_RECORD; + +/** + Installs and initialize this protocol + + @param[in] ImageHandle Not used + + @retval EFI_SUCCESS Installation succeed + @retval others Installation failed +**/ +EFI_STATUS +EFIAPI +InstallEspiSmi ( + IN EFI_HANDLE ImageHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a BIOS Write Protect eve= nt + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +BiosWrProtectRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a BIOS Write Report event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +BiosWrReportRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a Peripheral Channel Non= Fatal Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +PcNonFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a Peripheral Channel Fat= al Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +PcFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a Virtual Wire Non Fatal= Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +VwNonFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a Virtual Wire Fatal Err= or event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +VwFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a Flash Channel Non Fata= l Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +FlashNonFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a Flash Channel Fatal Er= ror event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +FlashFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a Link Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +LnkType1ErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to register a eSPI slave SMI + NOTE: The register function is not available when the ESPI_SMI_LOCK bit = is set. + This runtine will also lock donw ESPI_SMI_LOCK bit after registrat= ion and + prevent this handler from unregistration. + On platform that supports more than 1 device through another chip select= (SPT-H), + the SMI handler itself needs to inspect both the eSPI devices' interrupt= status registers + (implementation specific for each Slave) in order to identify and servic= e the cause. + After servicing it, it has to clear the Slaves' internal SMI# status reg= isters + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback regis= tration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered + @retval EFI_ACCESS_DENIED The ESPI_SMI_LOCK is set and regis= ter is blocked. + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +EspiSlaveSmiRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ); + +/** + eSPI SMI Dispatch Protocol instance to unregister a callback based on ha= ndle + + @param[in] This Not used + @param[in] DispatchHandle Handle acquired during registration + + @retval EFI_SUCCESS Unregister successful + @retval EFI_INVALID_PARAMETER DispatchHandle is null + @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has ba= d pointer + @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in dat= abase + @retval EFI_ACCESS_DENIED Unregistration is done after end of = DXE + @retval EFI_ACCESS_DENIED DispatchHandle is not allowed to unr= egistered +**/ +EFI_STATUS +EFIAPI +EspiSmiUnRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ); + +/** + eSPI SMI handler for Fatal Error recovery flow + + @param[in] DispatchHandle Handle acquired during registration +**/ +VOID +EspiDefaultFatalErrorHandler ( + VOID + ); + + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmHelpers.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm= /PchSmmHelpers.h new file mode 100644 index 0000000000..24e0975025 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmHel= pers.h @@ -0,0 +1,157 @@ +/** @file + Helper functions for PCH SMM + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PCH_SMM_HELPERS_H +#define PCH_SMM_HELPERS_H + +#include "PchSmm.h" +#include "PchxSmmHelpers.h" +// +// ///////////////////////////////////////////////////////////////////////= //////////////////////////////////////////// +// SUPPORT / HELPER FUNCTIONS (PCH version-independent) +// + +/** + Publish SMI Dispatch protocols. + + +**/ +VOID +PchSmmPublishDispatchProtocols ( + VOID + ); + +/** + Compare 2 SMM source descriptors' enable settings. + + @param[in] Src1 Pointer to the PCH SMI source descriptio= n table 1 + @param[in] Src2 Pointer to the PCH SMI source descriptio= n table 2 + + @retval TRUE The enable settings of the 2 SMM source = descriptors are identical. + @retval FALSE The enable settings of the 2 SMM source = descriptors are not identical. +**/ +BOOLEAN +CompareEnables ( + CONST IN PCH_SMM_SOURCE_DESC *Src1, + CONST IN PCH_SMM_SOURCE_DESC *Src2 + ); + +/** + Compare a bit descriptor to the enables of source descriptor. Includes n= ull address type. + + @param[in] BitDesc Pointer to the PCH SMI bit descriptor + @param[in] Src Pointer to the PCH SMI source descriptio= n table 2 + + @retval TRUE The bit desc is equal to any of the enab= les in source descriptor + @retval FALSE The bid desc is not equal to all of the = enables in source descriptor +**/ +BOOLEAN +IsBitEqualToAnySourceEn ( + CONST IN PCH_SMM_BIT_DESC *BitDesc, + CONST IN PCH_SMM_SOURCE_DESC *Src + ); + +/** + Compare 2 SMM source descriptors' statuses. + + @param[in] Src1 Pointer to the PCH SMI source descriptio= n table 1 + @param[in] Src2 Pointer to the PCH SMI source descriptio= n table 2 + + @retval TRUE The statuses of the 2 SMM source descrip= tors are identical. + @retval FALSE The statuses of the 2 SMM source descrip= tors are not identical. +**/ +BOOLEAN +CompareStatuses ( + CONST IN PCH_SMM_SOURCE_DESC *Src1, + CONST IN PCH_SMM_SOURCE_DESC *Src2 + ); + +/** + Compare 2 SMM source descriptors, based on Enable settings and Status se= ttings of them. + + @param[in] Src1 Pointer to the PCH SMI source descriptio= n table 1 + @param[in] Src2 Pointer to the PCH SMI source descriptio= n table 2 + + @retval TRUE The 2 SMM source descriptors are identic= al. + @retval FALSE The 2 SMM source descriptors are not ide= ntical. +**/ +BOOLEAN +CompareSources ( + CONST IN PCH_SMM_SOURCE_DESC *Src1, + CONST IN PCH_SMM_SOURCE_DESC *Src2 + ); + +/** + Check if an SMM source is active. + + @param[in] Src Pointer to the PCH SMI source descriptio= n table + @param[in] SciEn Indicate if SCI is enabled or not + @param[in] SmiEnValue Value from R_PCH_SMI_EN + @param[in] SmiStsValue Value from R_PCH_SMI_STS + + @retval TRUE It is active. + @retval FALSE It is inactive. +**/ +BOOLEAN +SourceIsActive ( + CONST IN PCH_SMM_SOURCE_DESC *Src, + CONST IN BOOLEAN SciEn, + CONST IN UINT32 SmiEnValue, + CONST IN UINT32 SmiStsValue + ); + +/** + Enable the SMI source event by set the SMI enable bit, this function wou= ld also clear SMI + status bit to make initial state is correct + + @param[in] SrcDesc Pointer to the PCH SMI source descriptio= n table + +**/ +VOID +PchSmmEnableSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + Disable the SMI source event by clear the SMI enable bit + + @param[in] SrcDesc Pointer to the PCH SMI source descriptio= n table + +**/ +VOID +PchSmmDisableSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + Clear the SMI status bit by set the source bit of SMI status register + + @param[in] SrcDesc Pointer to the PCH SMI source descriptio= n table + +**/ +VOID +PchSmmClearSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + Sets the source to a 1 and then waits for it to clear. + Be very careful when calling this function -- it will not + ASSERT. An acceptable case to call the function is when + waiting for the NEWCENTURY_STS bit to clear (which takes + 3 RTCCLKs). + + @param[in] SrcDesc Pointer to the PCH SMI source descriptio= n table + +**/ +VOID +PchSmmClearSourceAndBlock ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hxSmmHelpers.h b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Sm= m/PchxSmmHelpers.h new file mode 100644 index 0000000000..ba7ad42c9d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchxSmmHe= lpers.h @@ -0,0 +1,105 @@ +/** @file + This driver is responsible for the registration of child drivers + and the abstraction of the PCH SMI sources. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCHX_SMM_HELPERS_H_ +#define _PCHX_SMM_HELPERS_H_ + +#include "PchSmm.h" + +/** + Initialize bits that aren't necessarily related to an SMI source. + + + @retval EFI_SUCCESS SMI source initialization completed. + @retval Asserts Global Smi Bit is not enabled successful= ly. +**/ +EFI_STATUS +PchSmmInitHardware ( + VOID + ); + +/** + Enables the PCH to generate SMIs. Note that no SMIs will be generated + if no SMI sources are enabled. Conversely, no enabled SMI source will + generate SMIs if SMIs are not globally enabled. This is the main + switchbox for SMI generation. + + + @retval EFI_SUCCESS Enable Global Smi Bit completed +**/ +EFI_STATUS +PchSmmEnableGlobalSmiBit ( + VOID + ); + +/** + Clears the SMI after all SMI source have been processed. + Note that this function will not work correctly (as it is + written) unless all SMI sources have been processed. + A revision of this function could manually clear all SMI + status bits to guarantee success. +**/ +VOID +PchSmmClearSmi ( + VOID + ); + +/** + Set the SMI EOS bit after all SMI source have been processed. + + + @retval FALSE EOS was not set to a 1; this is an error + @retval TRUE EOS was correctly set to a 1 +**/ +BOOLEAN +PchSmmSetAndCheckEos ( + VOID + ); + +/** + Determine whether an ACPI OS is present (via the SCI_EN bit) + + + @retval TRUE ACPI OS is present + @retval FALSE ACPI OS is not present +**/ +BOOLEAN +PchSmmGetSciEn ( + VOID + ); + +/** + Read a specifying bit with the register + + @param[in] BitDesc The struct that includes register addres= s, size in byte and bit number + + @retval TRUE The bit is enabled + @retval FALSE The bit is disabled +**/ +BOOLEAN +ReadBitDesc ( + CONST PCH_SMM_BIT_DESC *BitDesc + ); + +/** + Write a specifying bit with the register + + @param[in] BitDesc The struct that includes register addres= s, size in byte and bit number + @param[in] ValueToWrite The value to be wrote + @param[in] WriteClear If the rest bits of the register is writ= e clear + +**/ +VOID +WriteBitDesc ( + CONST PCH_SMM_BIT_DESC *BitDesc, + CONST BOOLEAN ValueToWrite, + CONST BOOLEAN WriteClear + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Io= Trap.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/IoTrap= .c new file mode 100644 index 0000000000..ddab2fc378 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/IoTrap.c @@ -0,0 +1,1264 @@ +/** @file + Main implementation source file for the Io Trap SMM driver + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmHelpers.h" +#include +#include +#include +#include +#include + +#define GENERIC_IOTRAP_SIZE 0x100 + +// +// Module global variables +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_HANDLE mDriverImage= Handle; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_HANDLE mIoTrapHandl= e; + +GLOBAL_REMOVE_IF_UNREFERENCED IO_TRAP_INSTANCE mIoTrapData; +GLOBAL_REMOVE_IF_UNREFERENCED IO_TRAP_RECORD *mIoTrapReco= rd; +GLOBAL_REMOVE_IF_UNREFERENCED PCH_NVS_AREA *mPchNvsArea; + + +static CONST UINT16 mLengthTable[10] =3D { 1, 2, 3, 4, 8, 16, = 32, 64, 128, 256 }; + +/** + Helper function that encapsulates IoTrap register access. + IO trap related register updates must be made in 2 registers, IOTRAP and= DMI source decode. + + @param[in] TrapHandlerNum trap number (0-3) + @param[in] Value value to be written in both registers + @param[in] SaveToBootscript if true, this register write will be saved = to bootscript + +**/ +VOID +SetIoTrapLowDword ( + IN UINT8 TrapHandlerNum, + IN UINT32 Value, + IN BOOLEAN SaveToBootscript + ) +{ + UINT32 BitMask; + UINT32 BitValue; + // + // To provide sequentially consistent programming model for IO trap + // all pending IO cycles must be flushed before enabling and before disa= bling a trap. + // Without this the trap may trigger due to IO cycle issued before the t= rap is enabled or a cycle issued before the trap is disabled might be misse= d. + // a. Issues a MemRd to PSTH IO Trap Enable bit -> This serves to flush = all previous IO cycles. + // b. Then only issues a MemWr to PSTH IO Trap Enable =3D=3D Value + // c. Issues another MemRd to PSTH IO Trap Enable bit -> This serves to = push the MemWr to PSTH and confirmed that IO Trap is in fact enabled + // + PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + TrapHandlerNum * 8); + PchPcrWrite32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + TrapHandlerNum * 8, Value); + PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + TrapHandlerNum * 8); + + PchPcrWrite32 (PID_DMI, R_PCH_DMI_PCR_IOT1 + TrapHandlerNum * 8, Value); + // + // Read back DMI IOTRAP register to enforce ordering so DMI write is com= pleted before any IO reads + // from other threads which may occur after this point (after SMI exit). + // + PchPcrRead32 (PID_DMI, R_PCH_DMI_PCR_IOT1 + TrapHandlerNum * 8); + if (SaveToBootscript) { + // + // Ignore the value check of PCH_PCR_BOOT_SCRIPT_READ + // + BitMask =3D 0; + BitValue =3D 0; + + PCH_PCR_BOOT_SCRIPT_READ (S3BootScriptWidthUint32, PID_PSTH, R_PSTH_PC= R_TRPREG0 + TrapHandlerNum * 8, &BitMask, &BitValue); + PCH_PCR_BOOT_SCRIPT_WRITE (S3BootScriptWidthUint32, PID_PSTH, R_PSTH_P= CR_TRPREG0 + TrapHandlerNum * 8, 1, &Value); + PCH_PCR_BOOT_SCRIPT_READ (S3BootScriptWidthUint32, PID_PSTH, R_PSTH_PC= R_TRPREG0 + TrapHandlerNum * 8, &BitMask, &BitValue); + PCH_PCR_BOOT_SCRIPT_WRITE (S3BootScriptWidthUint32, PID_DMI, R_PCH_DMI= _PCR_IOT1 + TrapHandlerNum * 8, 1, &Value); + } +} + +/** + Helper function that encapsulates IoTrap register access. + IO trap related register updates must be made in 2 registers, IOTRAP and= DMI source decode. + + @param[in] TrapHandlerNum trap number (0-3) + @param[in] Value value to be written in both registers + @param[in] SaveToBootscript if true, this register write will be saved = to bootscript + +**/ +VOID +SetIoTrapHighDword ( + IN UINT8 TrapHandlerNum, + IN UINT32 Value, + IN BOOLEAN SaveToBootscript + ) +{ + PchPcrWrite32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + TrapHandlerNum * 8 + 4, Va= lue); + PchPcrWrite32 (PID_DMI, R_PCH_DMI_PCR_IOT1 + TrapHandlerNum * 8 + 4, Val= ue); + if (SaveToBootscript) { + PCH_PCR_BOOT_SCRIPT_WRITE (S3BootScriptWidthUint32, PID_PSTH, R_PSTH_P= CR_TRPREG0 + TrapHandlerNum * 8 + 4, 1, &Value); + PCH_PCR_BOOT_SCRIPT_WRITE (S3BootScriptWidthUint32, PID_DMI, R_PCH_DMI= _PCR_IOT1 + TrapHandlerNum * 8 + 4, 1, &Value); + } +} + +/** + Clear pending IOTRAP status. + If IOTRAP status is pending and IOTRAP is disabled, then BIOS will not f= ind a match SMI source + and will not dispatch any SMI handler for it. The pending status will le= ad to SMI storm. + This prevents that IOTRAP gets triggered by pending IO cycles even after= it's disabled. + + @param[in] TrapHandlerNum trap number (0-3) + +**/ +VOID +ClearPendingIoTrapStatus ( + IN UINT8 TrapHandlerNum + ) +{ + PchPcrWrite32 (PID_PSTH, R_PSTH_PCR_TRPST, (UINT32)(1 << TrapHandlerNum)= ); +} + +/** + IO resources allocated to IO traps need to be reported to OS so that the= y don't get reused. + This function makes IO trap allocation data available to ACPI + + @param[in] TrapHandlerNum trap number (0-3) + @param[in] BaseAddress address of allocated IO resource + @param[in] Track TRUE =3D resource allocated, FALSE =3D resour= ce freed + +**/ +VOID +UpdateIoTrapAcpiResources ( + IN UINT8 TrapHandlerNum, + IN EFI_PHYSICAL_ADDRESS BaseAddress, + IN BOOLEAN Track + ) +{ + + if (Track =3D=3D TRUE) { + mPchNvsArea->IoTrapAddress[TrapHandlerNum] =3D (UINT16) BaseAddress; + mPchNvsArea->IoTrapStatus[TrapHandlerNum] =3D 1; + } else { + mPchNvsArea->IoTrapStatus[TrapHandlerNum] =3D 0; + } +} + +/** + Get address from IOTRAP low dword. + + @param[in] IoTrapRegLowDword IOTRAP register low dword + + @retval Address of IOTRAP setting. +**/ +STATIC +UINT16 +AddressFromLowDword ( + UINT32 IoTrapRegLowDword + ) +{ + return (UINT16) (IoTrapRegLowDword & B_PSTH_PCR_TRPREG_AD); +} + +/** + Get length from IOTRAP low dword. + + @param[in] IoTrapRegLowDword IOTRAP register low dword + + @retval Length of IOTRAP setting. +**/ +STATIC +UINT16 +LengthFromLowDword ( + UINT32 IoTrapRegLowDword + ) +{ + return (UINT16) (((IoTrapRegLowDword >> 16) & 0xFC) + 4); +} + +/** + Get ByteEnable from IOTRAP high dword. + + @param[in] IoTrapRegHighDword IOTRAP register high dword + + @retval ByteEnable of IOTRAP setting. +**/ +STATIC +UINT8 +ByteEnableFromHighDword ( + UINT32 IoTrapRegHighDword + ) +{ + return (UINT8) (IoTrapRegHighDword & 0x0F); +} + +/** + Get ByteEnableMask from IOTRAP high dword. + + @param[in] IoTrapRegHighDword IOTRAP register high dword + + @retval ByteEnableMask of IOTRAP setting. +**/ +STATIC +UINT8 +ByteEnableMaskFromHighDword ( + UINT32 IoTrapRegHighDword + ) +{ + return (UINT8) ((IoTrapRegHighDword & 0xF0) >> 4); +} + +/** + Check the IoTrap register matches the IOTRAP EX content. + + @param[in] IoTrapRecord IOTRAP registration record structure + @param[in] IoTrapRegLowDword IOTRAP register low dword + @param[in] IoTrapRegHighDword IOTRAP register high dword + + @retval TRUE Content matched + FALSE Content mismatched +**/ +STATIC +BOOLEAN +IsIoTrapExContentMatched ( + IO_TRAP_RECORD *IoTrapRecord, + UINT32 IoTrapRegLowDword, + UINT32 IoTrapRegHighDword + ) +{ + if ((IoTrapRecord->Context.Address =3D=3D AddressFromLowDword (IoTrapReg= LowDword)) && + (IoTrapRecord->Context.Length =3D=3D LengthFromLowDword (IoTrapRegLo= wDword)) && + (IoTrapRecord->Context.ByteEnable =3D=3D ByteEnableFromHighDword (Io= TrapRegHighDword)) && + (IoTrapRecord->Context.ByteEnableMask =3D=3D ByteEnableMaskFromHighD= word (IoTrapRegHighDword))) + { + return TRUE; + } + return FALSE; +} + + +/** + The helper function for IoTrap callback dispacther + + @param[in] TrapHandlerNum trap number (0-3) +**/ +VOID +IoTrapDispatcherHelper ( + UINTN TrapHandlerNum + ) +{ + IO_TRAP_RECORD *RecordInDb; + LIST_ENTRY *LinkInDb; + EFI_SMM_IO_TRAP_REGISTER_CONTEXT CurrentIoTrapRegisterData; + EFI_SMM_IO_TRAP_CONTEXT CurrentIoTrapContextData; + UINT16 BaseAddress; + UINT16 StartAddress; + UINT16 EndAddress; + UINT32 Data32; + UINT8 ActiveHighByteEnable; + BOOLEAN ReadCycle; + UINT32 WriteData; + + if (!IsListEmpty (&(mIoTrapData.Entry[TrapHandlerNum].CallbackDataBase))= ) { + Data32 =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPC); + WriteData =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPD); + + BaseAddress =3D (UINT16) (Data32 & B_PSTH_PCR_TRPC_IOA); + ActiveHighByteEnable =3D (UINT8)((Data32 & B_PSTH_PCR_TRPC_AHBE) >> 1= 6); + ReadCycle =3D (BOOLEAN) ((Data32 & B_PSTH_PCR_TRPC_RW) =3D= =3D B_PSTH_PCR_TRPC_RW); + // + // StartAddress and EndAddress will be equal if it's byte access + // + EndAddress =3D (UINT16) (HighBitSet32 ((UINT32) (ActiveHighByteEnab= le))) + BaseAddress; + StartAddress =3D (UINT16) (LowBitSet32 ((UINT32) (ActiveHighByteEnabl= e))) + BaseAddress; + + CurrentIoTrapRegisterData.Type =3D (EFI_SMM_IO_TRAP_DISPATCH_TYPE)Read= Cycle; + CurrentIoTrapContextData.WriteData =3D WriteData; + + LinkInDb =3D GetFirstNode (&(mIoTrapData.Entry[TrapHandlerNum].Callbac= kDataBase)); + + while (!IsNull (&(mIoTrapData.Entry[TrapHandlerNum].CallbackDataBase),= LinkInDb)) { + RecordInDb =3D IO_TRAP_RECORD_FROM_LINK (LinkInDb); + + // + // If MergeDisable is TRUE, no need to check the address range, disp= atch the callback function directly. + // + if (mIoTrapData.Entry[TrapHandlerNum].MergeDisable) { + if (RecordInDb->IoTrapCallback !=3D NULL) { + RecordInDb->IoTrapCallback (&RecordInDb->Link, &CurrentIoTrapCon= textData, NULL, NULL); + } + if (RecordInDb->IoTrapExCallback !=3D NULL) { + RecordInDb->IoTrapExCallback (BaseAddress, ActiveHighByteEnable,= !ReadCycle, WriteData); + } + // + // Expect only one callback available. So break immediately. + // + break; + // + // If MergeDisable is FALSE, check the address range and trap type. + // + } else { + if ((RecordInDb->Context.Address <=3D StartAddress) && + (RecordInDb->Context.Address + RecordInDb->Context.Length > En= dAddress)) { + if ((RecordInDb->Context.Type =3D=3D IoTrapExTypeReadWrite) || (= RecordInDb->Context.Type =3D=3D (IO_TRAP_EX_DISPATCH_TYPE) CurrentIoTrapReg= isterData.Type)) { + // + // Pass the IO trap context information + // + RecordInDb->IoTrapCallback (&RecordInDb->Link, &CurrentIoTrapC= ontextData, NULL, NULL); + } + // + // Break if the address is match + // + break; + } else { + LinkInDb =3D GetNextNode (&(mIoTrapData.Entry[TrapHandlerNum].Ca= llbackDataBase), &RecordInDb->Link); + if (IsNull (&(mIoTrapData.Entry[TrapHandlerNum].CallbackDataBase= ), LinkInDb)) { + // + // An IO access was trapped that does not have a handler regis= tered. + // This indicates an error condition. + // + ASSERT (FALSE); + } + } + } // end of if else block + } // end of while loop + } // end of if else block +} + +/** + IoTrap dispatcher for IoTrap register 0. + + @param[in] DispatchHandle Handle of dispatch function +**/ +VOID +EFIAPI +IoTrapDispatcher0 ( + IN EFI_HANDLE DispatchHandle + ) +{ + IoTrapDispatcherHelper (0); +} + +/** + IoTrap dispatcher for IoTrap register 1. + + @param[in] DispatchHandle Handle of dispatch function +**/ +VOID +EFIAPI +IoTrapDispatcher1 ( + IN EFI_HANDLE DispatchHandle + ) +{ + IoTrapDispatcherHelper (1); +} + +/** + IoTrap dispatcher for IoTrap register 2. + + @param[in] DispatchHandle Handle of dispatch function +**/ +VOID +EFIAPI +IoTrapDispatcher2 ( + IN EFI_HANDLE DispatchHandle + ) +{ + IoTrapDispatcherHelper (2); +} + +/** + IoTrap dispatcher for IoTrap register 3. + + @param[in] DispatchHandle Handle of dispatch function +**/ +VOID +EFIAPI +IoTrapDispatcher3 ( + IN EFI_HANDLE DispatchHandle + ) +{ + IoTrapDispatcherHelper (3); +} + +/** + IoTrap registratrion helper fucntion. + + @param[in] DispatchHandle Handle of dispatch function + @param[in] IoTrapDispatchFunction Dispatch function of IoTrapDispatc= h2Protocol. + This could be NULL if it's not fro= m IoTrapDispatch2Protocol. + @param[in] IoTrapExDispatchFunction Dispatch function of IoTrapExDispa= tchProtocol. + This could be NULL if it's not fro= m IoTrapExDispatchProtocol. + @param[in out] Address The pointer of IO Address. + If the input Addres is 0, it will = return the address assigned + by registration to this caller. + @param[in] Length Length of IO address range. + @param[in] Type Read/Write type of IO trap. + @param[in] ByteEnable Bitmap to enable trap for each byt= e of every dword alignment address. + @param[in] ByteEnableMask ByteEnableMask bitwise to ignore t= he ByteEnable setting. + + @retval EFI_INVALID_PARAMETER If Type is invalid, + If Length is invalid, + If Address is invalid, + EFI_ACCESS_DENIED If the SmmReadyToLock event has be= en triggered, + EFI_OUT_OF_RESOURCES If run out of IoTrap register reso= urce, + If run out of SMM memory pool, + EFI_SUCCESS IoTrap register successfully. +**/ +EFI_STATUS +IoTrapRegisterHelper ( + OUT EFI_HANDLE *DispatchHandle, + IN EFI_SMM_HANDLER_ENTRY_POINT2 IoTrapDispatchFunction, + IN IO_TRAP_EX_DISPATCH_CALLBACK IoTrapExDispatchFunctio= n, + IN OUT UINT16 *Address, + IN UINT16 Length, + IN IO_TRAP_EX_DISPATCH_TYPE Type, + IN UINT8 ByteEnable, + IN UINT8 ByteEnableMask + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT32 UsedLength; + UINT8 TrapHandlerNum; + UINT32 IoTrapRegLowDword; + UINT32 IoTrapRegHighDword; + BOOLEAN TempMergeDisable; + + DEBUG ((DEBUG_INFO, "IoTrapRegisterHelper\n")); + DEBUG ((DEBUG_INFO, "Address:%x \n", *Address)); + DEBUG ((DEBUG_INFO, "Length:%x \n", Length)); + DEBUG ((DEBUG_INFO, "Type:%x \n", Type)); + DEBUG ((DEBUG_INFO, "ByteEnable:%x \n", ByteEnable)); + DEBUG ((DEBUG_INFO, "ByteEnableMask:%x \n", ByteEnableMask)); + + // + // Return error if the type is invalid + // + if (Type >=3D IoTrapExTypeMaximum) { + DEBUG ((DEBUG_ERROR, "The Dispatch Type %0X is invalid! \n", Type)); + return EFI_INVALID_PARAMETER; + } + // + // Return error if the Length is invalid + // + if (Length < 1 || Length > GENERIC_IOTRAP_SIZE) { + DEBUG ((DEBUG_ERROR, "The Dispatch Length %0X is invalid! \n", Length)= ); + return EFI_INVALID_PARAMETER; + } + // + // Return error if the address is invalid + // PCH supports non-aligned address but (Address % 4 + Length) must not = be more than 4 + // + if (((Length & (Length - 1)) !=3D 0) && (Length !=3D 3)) { + DEBUG ((DEBUG_ERROR, "The Dispatch Length is not power of 2 \n")); + return EFI_INVALID_PARAMETER; + } + + if (((Length >=3D 4) && (*Address & 0x3)) || + ((Length < 4) && (((*Address & 0x3) + Length) > 4))) { + DEBUG ((DEBUG_ERROR, "PCH does not support Dispatch Address %0X and Le= ngth %0X combination \n", *Address, Length)); + return EFI_INVALID_PARAMETER; + } + + if ((Length >=3D 4) && ((*Address & (Length - 1)) !=3D 0)) { + DEBUG ((DEBUG_ERROR, "Dispatch Address %0X is not aligned to the Lengt= h %0X \n", *Address, Length)); + return EFI_INVALID_PARAMETER; + } + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + if (*Address) { + TempMergeDisable =3D TRUE; + }else { + TempMergeDisable =3D FALSE; + } + // + // Loop through the first IO Trap handler, looking for the suitable hand= ler + // + for (TrapHandlerNum =3D 0; TrapHandlerNum < IO_TRAP_HANDLER_NUM; TrapHan= dlerNum++) { + // + // Get information from Io Trap handler register + // + IoTrapRegLowDword =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + Tra= pHandlerNum * 8); + + // + // Check if the IO Trap handler is not used + // + if (AddressFromLowDword (IoTrapRegLowDword) =3D=3D 0) { + // + // Search available IO address and allocate it if the IO address is= 0 + // + BaseAddress =3D *Address; + if (BaseAddress =3D=3D 0) { + // + // Allocate 256 byte range from GCD for common pool usage + // + if ((PcdGet8 (PcdEfiGcdAllocateType) =3D=3D EfiGcdAllocateMaxAddre= ssSearchBottomUp) || (PcdGet8 (PcdEfiGcdAllocateType) =3D=3D EfiGcdAllocate= MaxAddressSearchTopDown)) { + BaseAddress =3D 0xFFFF; + } + Status =3D gDS->AllocateIoSpace ( + PcdGet8 (PcdEfiGcdAllocateType), + EfiGcdIoTypeIo, + 8, + GENERIC_IOTRAP_SIZE, + &BaseAddress, + mDriverImageHandle, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Can't find any available IO address! \n")); + return EFI_OUT_OF_RESOURCES; + } + + *Address =3D (UINT16) BaseAddress; + UsedLength =3D GENERIC_IOTRAP_SIZE; + mIoTrapData.Entry[TrapHandlerNum].TrapUsedLength =3D Length; + mIoTrapData.Entry[TrapHandlerNum].ReservedAcpiIoResource =3D TRUE; + UpdateIoTrapAcpiResources (TrapHandlerNum, BaseAddress, TRUE); + } else { + BaseAddress &=3D B_PSTH_PCR_TRPREG_AD; + UsedLength =3D Length; + } + + Status =3D PchInternalIoTrapSmiRegister ( + mIoTrapData.Entry[TrapHandlerNum].CallbackDispatcher, + TrapHandlerNum, + &mIoTrapHandle + ); + + ASSERT_EFI_ERROR (Status); + mIoTrapData.Entry[TrapHandlerNum].IoTrapHandle =3D mIoTrapHandle; + + // + // Fill in the Length, address and Enable the IO Trap SMI + // + IoTrapRegLowDword =3D (UINT32) (((UsedLength - 1) & ~(BIT1 + BIT0)) = << 16) | + (UINT16) BaseAddress | + B_PSTH_PCR_TRPREG_TSE; + + if (UsedLength < 4) { + // + // The 4 bits is the Byte Enable Mask bits to indicate which byte = that are trapped. + // The input ByteEnable and ByteEnableMask are ignored in this cas= e. + // + IoTrapRegHighDword =3D (((1 << UsedLength) - 1) << ((*Address & 0= x3) + (N_PSTH_PCR_TRPREG_BEM - 32))) | + (UINT32) (Type << N_PSTH_PCR_TRPREG_RWIO); + } else { + // + // Fill in the ByteEnable, ByteEnableMask, and Type of Io Trap reg= ister + // + IoTrapRegHighDword =3D ((ByteEnableMask & 0xF) << (N_PSTH_PCR_TRP= REG_BEM - 32)) | + ((ByteEnable & 0xF) << (N_PSTH_PCR_TRPREG_BE - 32)) | + (UINT32) (Type << N_PSTH_PCR_TRPREG_RWIO); + } + SetIoTrapHighDword (TrapHandlerNum, IoTrapRegHighDword, TRUE); + SetIoTrapLowDword (TrapHandlerNum, IoTrapRegLowDword, TRUE); + // + // Set MergeDisable flag of the registered IoTrap + // + mIoTrapData.Entry[TrapHandlerNum].MergeDisable =3D TempMergeDisable; + } else { + // + // Check next handler if MergeDisable is TRUE or the registered IoTr= ap if MergeDisable is TRUE + // If the Io Trap register is used by IoTrapEx protocol, then the Me= rgeDisable will be FALSE. + // + if ((TempMergeDisable =3D=3D TRUE) || (mIoTrapData.Entry[TrapHandler= Num].MergeDisable =3D=3D TRUE)) { + continue; + } + // + // The IO Trap handler is used, calculate the Length + // + UsedLength =3D LengthFromLowDword (IoTrapRegLowDword); + BaseAddress =3D AddressFromLowDword (IoTrapRegLowDword); + // + // Assign an addfress from common pool if the caller's address is 0 + // + if (*Address =3D=3D 0) { + // + // Check next handler if it's fully used + // + if (mIoTrapData.Entry[TrapHandlerNum].TrapUsedLength >=3D GENERIC_= IOTRAP_SIZE) { + continue; + } + // + // Check next handler if it's not for a common pool + // + if (UsedLength < GENERIC_IOTRAP_SIZE) { + continue; + } + // + // Check next handler if the size is too big + // + if (Length >=3D (UINT16) GENERIC_IOTRAP_SIZE - mIoTrapData.Entry[T= rapHandlerNum].TrapUsedLength) { + continue; + } + // + // For common pool, we don't need to change the BaseAddress and Us= edLength + // + *Address =3D (UINT16) (BaseAddress + mIoTrapData.Entry[TrapHandler= Num].TrapUsedLength); + mIoTrapData.Entry[TrapHandlerNum].TrapUsedLength +=3D Length; + } + // + // Only set RWM bit when we need both read and write cycles. + // + IoTrapRegHighDword =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + = TrapHandlerNum * 8 + 4); + if ((IoTrapRegHighDword & B_PSTH_PCR_TRPREG_RWM) =3D=3D 0 && + (UINT32) ((IoTrapRegHighDword & B_PSTH_PCR_TRPREG_RWIO) >> N_PST= H_PCR_TRPREG_RWIO) !=3D + (UINT32) Type) { + IoTrapRegHighDword =3D ((IoTrapRegHighDword | B_PSTH_PCR_TRPREG_RW= M) & ~B_PSTH_PCR_TRPREG_RWIO); + SetIoTrapHighDword (TrapHandlerNum, IoTrapRegHighDword, TRUE); + } + } + break; + } + + if (TrapHandlerNum >=3D IO_TRAP_HANDLER_NUM) { + DEBUG ((DEBUG_ERROR, "All IO Trap handler is used, no available IO Tra= p handler! \n")); + return EFI_OUT_OF_RESOURCES; + } + // + // Create database record and add to database + // + Status =3D gSmst->SmmAllocatePool ( + EfiRuntimeServicesData, + sizeof (IO_TRAP_RECORD), + (VOID **) &mIoTrapRecord + ); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to allocate memory for mIoTrapRecord! \n"= )); + return EFI_OUT_OF_RESOURCES; + } + // + // Gather information about the registration request + // + mIoTrapRecord->Signature =3D IO_TRAP_RECORD_SIGNATURE; + mIoTrapRecord->Context.Address =3D *Address; + mIoTrapRecord->Context.Length =3D Length; + mIoTrapRecord->Context.Type =3D Type; + mIoTrapRecord->Context.ByteEnable =3D ByteEnable; + mIoTrapRecord->Context.ByteEnableMask =3D ByteEnableMask; + mIoTrapRecord->IoTrapCallback =3D IoTrapDispatchFunction; + mIoTrapRecord->IoTrapExCallback =3D IoTrapExDispatchFunction; + mIoTrapRecord->IoTrapNumber =3D TrapHandlerNum; + + InsertTailList (&(mIoTrapData.Entry[TrapHandlerNum].CallbackDataBase), &= mIoTrapRecord->Link); + + // + // Child's handle will be the address linked list link in the record + // + *DispatchHandle =3D (EFI_HANDLE) (&mIoTrapRecord->Link); + + DEBUG ((DEBUG_INFO, "Result Address:%x \n", *Address)); + DEBUG ((DEBUG_INFO, "Result Length:%x \n", Length)); + + return EFI_SUCCESS; +} + +/** + IoTrap unregistratrion helper fucntion. + + @param[in] DispatchHandle Handle of dispatch function + + @retval EFI_INVALID_PARAMETER If DispatchHandle is invalid, + EFI_ACCESS_DENIED If the SmmReadyToLock event has be= en triggered, + EFI_SUCCESS IoTrap unregister successfully. +**/ +EFI_STATUS +IoTrapUnRegisterHelper ( + IN EFI_HANDLE DispatchHandle + ) +{ + EFI_STATUS Status; + IO_TRAP_RECORD *RecordToDelete; + UINT32 IoTrapRegLowDword; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT32 UsedLength; + UINT8 TrapHandlerNum; + UINT8 LengthIndex; + BOOLEAN RequireToDisableIoTrapHandler; + + if (DispatchHandle =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "UnRegister is not allowed if the SmmReadyToLock = event has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + RecordToDelete =3D IO_TRAP_RECORD_FROM_LINK (DispatchHandle); + // + // Take the entry out of the linked list + // + if (RecordToDelete->Link.ForwardLink =3D=3D (LIST_ENTRY *) EFI_BAD_POINT= ER) { + return EFI_INVALID_PARAMETER; + } + + RequireToDisableIoTrapHandler =3D FALSE; + // + // Loop through the first IO Trap handler, looking for the suitable hand= ler + // + TrapHandlerNum =3D RecordToDelete->IoTrapNumber; + + if (mIoTrapData.Entry[TrapHandlerNum].MergeDisable) { + // + // Disable the IO Trap handler if it's the only child of the Trap hand= ler + // + RequireToDisableIoTrapHandler =3D TRUE; + } else { + // + // Get information from Io Trap handler register + // + IoTrapRegLowDword =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + Tra= pHandlerNum * 8); + + // + // Check next Io Trap handler if the IO Trap handler is not used + // + if (AddressFromLowDword (IoTrapRegLowDword) !=3D 0) { + + UsedLength =3D LengthFromLowDword (IoTrapRegLowDword); + BaseAddress =3D AddressFromLowDword (IoTrapRegLowDword); + + // + // Check if it's the maximum address of the Io Trap handler + // + if ((UINTN)(BaseAddress + UsedLength) =3D=3D (UINTN)(RecordToDelete-= >Context.Address + RecordToDelete->Context.Length)) { + + if (BaseAddress =3D=3D RecordToDelete->Context.Address) { + // + // Disable the IO Trap handler if it's the only child of the Tra= p handler + // + RequireToDisableIoTrapHandler =3D TRUE; + } else { + // + // Calculate the new IO Trap handler Length + // + UsedLength =3D UsedLength - RecordToDelete->Context.Length; + // + // Check the alignment is dword * power of 2 or not + // + for (LengthIndex =3D 0; LengthIndex < sizeof (mLengthTable) / si= zeof (UINT16); LengthIndex++) { + if (UsedLength =3D=3D mLengthTable[LengthIndex]) { + break; + } + } + // + // Do not decrease the length if the alignment is not dword * po= wer of 2 + // + if (LengthIndex < sizeof (mLengthTable) / sizeof (UINT16)) { + // + // Decrease the length to prevent the IO trap SMI + // + IoTrapRegLowDword =3D (UINT32) ((((UsedLength - 1) &~(BIT1 + B= IT0)) << 16) | BaseAddress | B_PSTH_PCR_TRPREG_TSE); + } + SetIoTrapLowDword (TrapHandlerNum, IoTrapRegLowDword, TRUE); + } + } + } + } + + if (RequireToDisableIoTrapHandler) { + mIoTrapHandle =3D mIoTrapData.Entry[TrapHandlerNum].IoTrapHandle; + Status =3D PchInternalIoTrapSmiUnRegister (mIoTrapHandle); + ASSERT_EFI_ERROR (Status); + + SetIoTrapLowDword (TrapHandlerNum, 0, TRUE); + SetIoTrapHighDword (TrapHandlerNum, 0, TRUE); + // + // Also clear pending IOTRAP status. + // + ClearPendingIoTrapStatus (TrapHandlerNum); + + mIoTrapData.Entry[TrapHandlerNum].IoTrapHandle =3D 0; + mIoTrapData.Entry[TrapHandlerNum].MergeDisable =3D FALSE; + if (mIoTrapData.Entry[TrapHandlerNum].ReservedAcpiIoResource =3D=3D TR= UE) { + mIoTrapData.Entry[TrapHandlerNum].ReservedAcpiIoResource =3D FALSE; + UpdateIoTrapAcpiResources (TrapHandlerNum, 0, FALSE); + } + } + + RemoveEntryList (&RecordToDelete->Link); + Status =3D gSmst->SmmFreePool (RecordToDelete); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + Register a new IO Trap SMI dispatch function with a parent SMM driver. + The caller will provide information about the IO trap characteristics via + the context. This includes base address, length, read vs. r/w, etc. + This function will autoallocate IO base address from a common pool if th= e base address is 0, + and the RegisterContext Address field will be updated. + The service will not perform GCD allocation if the base address is non-z= ero. + In this case, the caller is responsible for the existence and allocation= of the + specific IO range. + This function looks for the suitable handler and Register a new IoTrap h= andler + if the IO Trap handler is not used. It also enable the IO Trap Range to = generate + SMI. + + @param[in] This Pointer to the EFI_SMM_IO_TRAP_DISPATCH2= _PROTOCOL instance. + @param[in] DispatchFunction Pointer to dispatch function to be invok= ed for + this SMI source. + @param[in, out] RegisterContext Pointer to the dispatch function's conte= xt. + The caller fills this context in before = calling + the register function to indicate to the= register + function the IO trap SMI source for whic= h the dispatch + function should be invoked. This may no= t be NULL. + If the registration address is not 0, it= 's caller's responsibility + to reserve the IO resource in ACPI. + @param[out] DispatchHandle Handle of dispatch function, for when in= terfacing + with the parent SMM driver, will be the = address of linked + list link in the call back record. This= may not be NULL. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + registered and the SMI source has been e= nabled. + @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI = source. + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available + @retval EFI_INVALID_PARAMETER Address requested is already in use. + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLo= ck event has been triggered +**/ +EFI_STATUS +EFIAPI +IoTrapRegister ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN OUT EFI_SMM_IO_TRAP_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "IoTrapRegister\n")); + Status =3D IoTrapRegisterHelper ( + DispatchHandle, + DispatchFunction, + NULL, + &(RegisterContext->Address), + RegisterContext->Length, + (IO_TRAP_EX_DISPATCH_TYPE) RegisterContext->Type, + 0x00, + 0x0F); + + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gEfiSmmIoTrapDispatch2ProtocolGuid,= DispatchFunction, (UINTN)RETURN_ADDRESS (0), NULL, 0); + } + return Status; +} + +/** + Unregister a child SMI source dispatch function with a parent SMM driver. + + @param[in] This Pointer to the EFI_SMM_IO_TRAP_DISPATCH2= _PROTOCOL instance. + @param[in] DispatchHandle Handle of dispatch function to deregiste= r. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + unregistered and the SMI source has been= disabled + if there are no other registered child d= ispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLo= ck event has been triggered +**/ +EFI_STATUS +EFIAPI +IoTrapUnRegister ( + IN CONST EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + IO_TRAP_RECORD *RecordToDelete; + + RecordToDelete =3D IO_TRAP_RECORD_FROM_LINK (DispatchHandle); + SmiHandlerProfileUnregisterHandler (&gEfiSmmIoTrapDispatch2ProtocolGuid,= RecordToDelete->IoTrapCallback, NULL, 0); + return IoTrapUnRegisterHelper (DispatchHandle); +} + +/** + Register a new IO Trap Ex SMI dispatch function. + + @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTO= COL instance. + @param[in] DispatchFunction Pointer to dispatch function to be invok= ed for + this SMI source. + @param[in] RegisterContext Pointer to the dispatch function's conte= xt. + The caller fills this context in before = calling + the register function to indicate to the= register + function the IO trap Ex SMI source for w= hich the dispatch + function should be invoked. This MUST n= ot be NULL. + @param[out] DispatchHandle Handle of dispatch function. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + registered and the SMI source has been e= nabled. + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available + @retval EFI_INVALID_PARAMETER Address requested is already in use. + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLo= ck event has been triggered +**/ +EFI_STATUS +EFIAPI +IoTrapExRegister ( + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, + IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction, + IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "PchSmmIoTrapExRegister\n")); + // + // Return error if length is less than 4 and not power of 2. + // + if ((RegisterContext->Length < 4) || ((RegisterContext->Length & (Regist= erContext->Length - 1)) !=3D 0)) { + DEBUG ((DEBUG_ERROR, "The Dispatch Length is not power of 2 \n")); + return EFI_INVALID_PARAMETER; + } + + Status =3D IoTrapRegisterHelper ( + DispatchHandle, + NULL, + DispatchFunction, + &(RegisterContext->Address), + RegisterContext->Length, + RegisterContext->Type, + RegisterContext->ByteEnable, + RegisterContext->ByteEnableMask); + + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gIoTrapExDispatchProtocolGuid, (EFI= _SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NULL= , 0); + } + return Status; +} + +/** + Unregister a SMI source dispatch function. + This function is unsupported. + + @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTO= COL instance. + @param[in] DispatchHandle Handle of dispatch function to deregiste= r. + + @retval EFI_UNSUPPORTED The function is unsupported. +**/ +EFI_STATUS +EFIAPI +IoTrapExUnRegister ( + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + IO_TRAP_RECORD *RecordToDelete; + + RecordToDelete =3D IO_TRAP_RECORD_FROM_LINK (DispatchHandle); + SmiHandlerProfileUnregisterHandler (&gIoTrapExDispatchProtocolGuid, Reco= rdToDelete->IoTrapCallback, NULL, 0); + return IoTrapUnRegisterHelper (DispatchHandle); +} + +/** + Pause IoTrap callback function. + + This function disables the SMI enable of IoTrap according to the Dispatc= hHandle, + which is returned by IoTrap callback registration. It only supports the = DispatchHandle + with MergeDisable TRUE and address not zero. + + NOTE: This call does not guarantee all pending IO cycles to be synchroni= zed + and pending IO cycles issued before this call might not be trapped. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_P= ROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change st= ate. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED. +**/ +EFI_STATUS +EFIAPI +IoTrapControlPause ( + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + IO_TRAP_RECORD *IoTrapRecord; + UINT32 IoTrapRegLowDword; + UINT32 IoTrapRegHighDword; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT32 UsedLength; + UINT8 TrapHandlerNum; + BOOLEAN TempMergeDisable; + BOOLEAN DisableIoTrap; + + if (DispatchHandle =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + IoTrapRecord =3D IO_TRAP_RECORD_FROM_LINK (DispatchHandle); + + if (IoTrapRecord->Context.Address) { + TempMergeDisable =3DTRUE; + }else { + TempMergeDisable =3D FALSE; + } + + if ((IoTrapRecord->Signature !=3D IO_TRAP_RECORD_SIGNATURE) || + (TempMergeDisable !=3D TRUE) || + (IoTrapRecord->Context.Address =3D=3D 0) || + (IoTrapRecord->Context.Length =3D=3D 0)) { + return EFI_INVALID_PARAMETER; + } + + for (TrapHandlerNum =3D 0; TrapHandlerNum < IO_TRAP_HANDLER_NUM; TrapHan= dlerNum++) { + // + // This IoTrap register should be merge disabled. + // + if (mIoTrapData.Entry[TrapHandlerNum].MergeDisable !=3D TRUE) { + continue; + } + IoTrapRegLowDword =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + Tra= pHandlerNum * 8); + IoTrapRegHighDword =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + Tr= apHandlerNum * 8 + 4); + // + // Depending on the usage, we will obtain the UsedLength and BaseAddre= ss differently + // If the registered trap length is less than 4, we obtain the length = from Byte Enable Mask + // In the other hand, we obtain the length from Address Mask + // + if (ByteEnableMaskFromHighDword (IoTrapRegHighDword) !=3D 0xF) { + UsedLength =3D (UINT32) (HighBitSet32 (IoTrapRegHighDword & 0xF0) - = LowBitSet32 (IoTrapRegHighDword & 0xF0) + 1); + BaseAddress =3D AddressFromLowDword (IoTrapRegLowDword) + LowBitSet3= 2 (ByteEnableMaskFromHighDword (IoTrapRegHighDword)); + } else { + UsedLength =3D LengthFromLowDword (IoTrapRegLowDword); + BaseAddress =3D AddressFromLowDword (IoTrapRegLowDword); + } + + // + // The address and length of record matches the IoTrap register's. + // + DisableIoTrap =3D FALSE; + if ((IoTrapRecord->IoTrapExCallback !=3D NULL) && + IsIoTrapExContentMatched (IoTrapRecord, IoTrapRegLowDword, IoTrapR= egHighDword)) { + DisableIoTrap =3D TRUE; + } else if ((BaseAddress =3D=3D IoTrapRecord->Context.Address) && + (UsedLength =3D=3D IoTrapRecord->Context.Length )) { + DisableIoTrap =3D TRUE; + } + + if (DisableIoTrap) { + // + // Check if status matched. + // If this is already Paused, return warning status. + // + if ((IoTrapRegLowDword & B_PSTH_PCR_TRPREG_TSE) =3D=3D 0) { + return EFI_ACCESS_DENIED; + } + // + // Clear IoTrap register SMI enable bit + // + IoTrapRegLowDword &=3D (~B_PSTH_PCR_TRPREG_TSE); + SetIoTrapLowDword (TrapHandlerNum, IoTrapRegLowDword, FALSE); + // + // Also clear pending IOTRAP status. + // + ClearPendingIoTrapStatus (TrapHandlerNum); + return EFI_SUCCESS; + } + } + return EFI_INVALID_PARAMETER; +} + +/** + Resume IoTrap callback function. + + This function enables the SMI enable of IoTrap according to the Dispatch= Handle, + which is returned by IoTrap callback registration. It only supports the = DispatchHandle + with MergeDisable TRUE and address not zero. + + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_P= ROTOCOL instance. + @param[in] DispatchHandle Handle of the child service to change st= ate. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. + @retval EFI_ACCESS_DENIED The SMI status is alrady RESUMED. +**/ +EFI_STATUS +EFIAPI +IoTrapControlResume ( + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + IO_TRAP_RECORD *IoTrapRecord; + UINT32 IoTrapRegLowDword; + UINT32 IoTrapRegHighDword; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT32 UsedLength; + UINT8 TrapHandlerNum; + BOOLEAN TempMergeDisable; + BOOLEAN EnableIoTrap; + + if (DispatchHandle =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + IoTrapRecord =3D IO_TRAP_RECORD_FROM_LINK (DispatchHandle); + + if (IoTrapRecord->Context.Address) { + TempMergeDisable =3D TRUE; + }else { + TempMergeDisable =3D FALSE; + } + + if ((IoTrapRecord->Signature !=3D IO_TRAP_RECORD_SIGNATURE) || + (TempMergeDisable !=3D TRUE) || + (IoTrapRecord->Context.Address =3D=3D 0) || + (IoTrapRecord->Context.Length =3D=3D 0)) { + return EFI_INVALID_PARAMETER; + } + + for (TrapHandlerNum =3D 0; TrapHandlerNum < IO_TRAP_HANDLER_NUM; TrapHan= dlerNum++) { + // + // This IoTrap register should be merge disabled. + // + if (mIoTrapData.Entry[TrapHandlerNum].MergeDisable !=3D TRUE) { + continue; + } + IoTrapRegLowDword =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + Tra= pHandlerNum * 8); + IoTrapRegHighDword =3D PchPcrRead32 (PID_PSTH, R_PSTH_PCR_TRPREG0 + Tr= apHandlerNum * 8 + 4); + // + // Depending on the usage, we will obtain the UsedLength and BaseAddre= ss differently + // If the registered trap length is less than 4, we obtain the length = from Byte Enable Mask + // In the other hand, we obtain the length from Address Mask + // + if (ByteEnableMaskFromHighDword (IoTrapRegHighDword) !=3D 0xF) { + UsedLength =3D (UINT32) (HighBitSet32 (IoTrapRegHighDword & 0xF0) -= LowBitSet32 (IoTrapRegHighDword & 0xF0) + 1); + BaseAddress =3D AddressFromLowDword (IoTrapRegLowDword) + LowBitSet3= 2 (ByteEnableMaskFromHighDword (IoTrapRegHighDword)); + } else { + UsedLength =3D LengthFromLowDword (IoTrapRegLowDword); + BaseAddress =3D AddressFromLowDword (IoTrapRegLowDword); + } + + // + // The address and length of record matches the IoTrap register's. + // + EnableIoTrap =3D FALSE; + if ((IoTrapRecord->IoTrapExCallback !=3D NULL) && + IsIoTrapExContentMatched (IoTrapRecord, IoTrapRegLowDword, IoTrapR= egHighDword)) { + EnableIoTrap =3D TRUE; + } else if ((BaseAddress =3D=3D IoTrapRecord->Context.Address) && + (UsedLength =3D=3D IoTrapRecord->Context.Length )) { + EnableIoTrap =3D TRUE; + } + + if (EnableIoTrap) { + // + // Check if status matched. + // If this is already Resume, return warning status. + // + if ((IoTrapRegLowDword & B_PSTH_PCR_TRPREG_TSE) !=3D 0) { + return EFI_ACCESS_DENIED; + } + // + // Set IoTrap register SMI enable bit + // + IoTrapRegLowDword |=3D (B_PSTH_PCR_TRPREG_TSE); + SetIoTrapLowDword (TrapHandlerNum, IoTrapRegLowDword, FALSE); + return EFI_SUCCESS; + } + } + return EFI_INVALID_PARAMETER; +} + +/** + The IoTrap module abstracts PCH I/O trapping capabilities for other driv= ers. + This driver manages the limited I/O trap resources. + + @param[in] ImageHandle Image handle for this driver image + + @retval EFI_SUCCESS Driver initialization completed su= ccessfully +**/ +EFI_STATUS +EFIAPI +InstallIoTrap ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + PCH_NVS_AREA_PROTOCOL *PchNvsAreaProtocol; + UINTN TrapHandlerNum; + + // + // Initialize the EFI SMM driver library + // + mDriverImageHandle =3D ImageHandle; + + // + // Initialize the IO TRAP protocol we produce + // + mIoTrapData.Signature =3D IO_TRAP_INSTANCE_SIGNATURE; + mIoTrapData.EfiSmmIoTrapDispatchProtocol.Register =3D IoTrapRegister; + mIoTrapData.EfiSmmIoTrapDispatchProtocol.UnRegister =3D IoTrapUnRegister; + + // + // Initialize the IO TRAP EX protocol + // + mIoTrapData.IoTrapExDispatchProtocol.Register =3D IoTrapExRegister; + mIoTrapData.IoTrapExDispatchProtocol.UnRegister =3D IoTrapExUnRegist= er; + + // + // Initialize the IO TRAP control protocol. + // + mIoTrapData.PchSmmIoTrapControlProtocol.Pause =3D IoTrapControlPau= se; + mIoTrapData.PchSmmIoTrapControlProtocol.Resume =3D IoTrapControlRes= ume; + + for (TrapHandlerNum =3D 0; TrapHandlerNum < IO_TRAP_HANDLER_NUM; TrapHan= dlerNum++) { + // + // Initialize IO TRAP Callback DataBase + // + InitializeListHead (&(mIoTrapData.Entry[TrapHandlerNum].CallbackDataBa= se)); + } + mIoTrapData.Entry[0].CallbackDispatcher =3D IoTrapDispatcher0; + mIoTrapData.Entry[1].CallbackDispatcher =3D IoTrapDispatcher1; + mIoTrapData.Entry[2].CallbackDispatcher =3D IoTrapDispatcher2; + mIoTrapData.Entry[3].CallbackDispatcher =3D IoTrapDispatcher3; + + // + // Get address of PchNvs structure for later use + // + Status =3D gBS->LocateProtocol (&gPchNvsAreaProtocolGuid, NULL, (VOID **= ) &PchNvsAreaProtocol); + ASSERT_EFI_ERROR (Status); + mPchNvsArea =3D PchNvsAreaProtocol->Area; + + // + // Install protocol interface + // + mIoTrapData.Handle =3D NULL; + Status =3D gSmst->SmmInstallProtocolInterface ( + &mIoTrapData.Handle, + &gEfiSmmIoTrapDispatch2ProtocolGuid, + EFI_NATIVE_INTERFACE, + &mIoTrapData.EfiSmmIoTrapDispatchProtocol + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gSmst->SmmInstallProtocolInterface ( + &mIoTrapData.Handle, + &gIoTrapExDispatchProtocolGuid, + EFI_NATIVE_INTERFACE, + &mIoTrapData.IoTrapExDispatchProtocol + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gSmst->SmmInstallProtocolInterface ( + &mIoTrapData.Handle, + &gPchSmmIoTrapControlGuid, + EFI_NATIVE_INTERFACE, + &mIoTrapData.PchSmmIoTrapControlProtocol + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmiDispatch.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Sm= m/PchSmiDispatch.c new file mode 100644 index 0000000000..2b70008fee --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmiDis= patch.c @@ -0,0 +1,2452 @@ +/** @file + This function handle the register/unregister of PCH specific SMI events. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmHelpers.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + The internal function used to create and insert a database record + for SMI record of Pch Smi types. + + @param[in] SrcDesc The pointer to the SMI source desc= ription + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[in] PchSmiType Specific SMI type of PCH SMI + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. +**/ +EFI_STATUS +PchSmiRecordInsert ( + IN CONST PCH_SMM_SOURCE_DESC *SrcDesc, + IN PCH_SMI_CALLBACK_FUNCTIONS DispatchFunction, + IN PCH_SMI_TYPES PchSmiType, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD Record; + + if (SrcDesc =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + ZeroMem (&Record, sizeof (DATABASE_RECORD)); + // + // Gather information about the registration request + // + Record.Signature =3D DATABASE_RECORD_SIGNATURE; + Record.PchSmiCallback =3D DispatchFunction; + Record.ProtocolType =3D PchSmiDispatchType; + Record.PchSmiType =3D PchSmiType; + + CopyMem (&Record.SrcDesc, SrcDesc, sizeof (PCH_SMM_SOURCE_DESC)); + Status =3D SmmCoreInsertRecord ( + &Record, + DispatchHandle + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + + +// +// TCO_STS bit that needs to be cleared +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mDescSrcTcoSts =3D= { + PCH_SMM_NO_FLAGS, + { + NULL_BIT_DESC_INITIALIZER, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } + }, + NULL_BIT_DESC_INITIALIZER +}; + +/** + Clear the TCO SMI status bit and block after the SMI handling is done + + @param[in] SrcDesc Pointer to the PCH SMI source desc= ription table + +**/ +VOID +EFIAPI +PchTcoSmiClearSourceAndBlock ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + PchSmmClearSourceAndBlock (SrcDesc); + // + // Any TCO-based status bits require special handling. + // SMI_STS.TCO_STS must be cleared in addition to the status bit in the = TCO registers + // + PchSmmClearSource (&mDescSrcTcoSts); +} + +/** + Clear the TCO SMI status bit after the SMI handling is done + + @param[in] SrcDesc Pointer to the PCH SMI source desc= ription table + +**/ +VOID +EFIAPI +PchTcoSmiClearSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + PchSmmClearSource (SrcDesc); + // + // Any TCO-based status bits require special handling. + // SMI_STS.TCO_STS must be cleared in addition to the status bit in the = TCO registers + // + PchSmmClearSource (&mDescSrcTcoSts); +} + +/** + Initialize Source descriptor structure + + @param[in] SrcDesc Pointer to the PCH SMI source des= cription table + +**/ +VOID +EFIAPI +NullInitSourceDesc ( + PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + ZeroMem (SrcDesc, sizeof (PCH_SMM_SOURCE_DESC)); + SrcDesc->En[0].Reg.Type =3D PCH_SMM_ADDR_TYPE_NULL; + SrcDesc->En[1].Reg.Type =3D PCH_SMM_ADDR_TYPE_NULL; + SrcDesc->Sts[0].Reg.Type =3D PCH_SMM_ADDR_TYPE_NULL; + SrcDesc->PmcSmiSts.Reg.Type =3D PCH_SMM_ADDR_TYPE_NULL; +} + +// +// Mch srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescMch =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_TCO + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + TCO_ADDR_TYPE, + {R_TCO_IO_TCO1_STS} + }, + S_TCO_IO_TCO1_STS, + N_TCO_IO_TCO1_STS_DMISMI + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + The register function used to register SMI handler of MCH event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiMchRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescMch, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchTcoSmiMchType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + Record->ClearSource =3D PchTcoSmiClearSource; + PchSmmClearSource (&Record->SrcDesc); + PchSmmEnableSource (&Record->SrcDesc); + SmiHandlerProfileRegisterHandler (&gPchTcoSmiDispatchProtocolGuid, (EF= I_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NUL= L, 0); + } + return Status; +} + +// +// TcoTimeout srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescTcoTimeout= =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_TCO + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + TCO_ADDR_TYPE, + {R_TCO_IO_TCO1_STS} + }, + S_TCO_IO_TCO1_STS, + N_TCO_IO_TCO1_STS_TIMEOUT + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + The register function used to register SMI handler of TcoTimeout event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiTcoTimeoutRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescTcoTimeout, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchTcoSmiTcoTimeoutType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + Record->ClearSource =3D PchTcoSmiClearSource; + PchSmmClearSource (&Record->SrcDesc); + PchSmmEnableSource (&Record->SrcDesc); + SmiHandlerProfileRegisterHandler (&gPchTcoSmiDispatchProtocolGuid, (EF= I_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NUL= L, 0); + } + return Status; +} + +// +// OsTco srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescOsTco =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_TCO + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + TCO_ADDR_TYPE, + {R_TCO_IO_TCO1_STS} + }, + S_TCO_IO_TCO1_STS, + N_TCO_IO_TCO1_STS_SW_TCO_SMI + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + The register function used to register SMI handler of OS TCO event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiOsTcoRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescOsTco, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchTcoSmiOsTcoType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + Record->ClearSource =3D PchTcoSmiClearSource; + PchSmmClearSource (&Record->SrcDesc); + PchSmmEnableSource (&Record->SrcDesc); + SmiHandlerProfileRegisterHandler (&gPchTcoSmiDispatchProtocolGuid, (EF= I_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NUL= L, 0); + } + return Status; +} + +// +// Nmi +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescNmi =3D { + PCH_SMM_NO_FLAGS, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ITSS, R_ITSS_PCR_NMI)} + }, + 4, + N_ITSS_PCR_NMI_NMI2SMI_EN + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ITSS, R_ITSS_PCR_NMI)} + }, + 4, + N_ITSS_PCR_NMI_NMI2SMI_STS + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + Enable the Nmi2Smi source +**/ +VOID +PchNmi2SmiEnableSource ( + VOID + ) +{ + // + // The PCR[ITSS].NMI register can only be accessed with BOOT_SAI and SMM= _SAI. + // Since in CFL there is no SMM_SAI it needs PMC assistance to access th= is register. + // + UINT32 ItssNmi; + ItssNmi =3D PmcGetNmiControl (); + PmcSetNmiControl (ItssNmi | B_ITSS_PCR_NMI_NMI2SMI_EN); +} + +/** + Clear the NMI status bit after the SMI handling is done + + @param[in] SrcDesc Pointer to the PCH SMI source desc= ription table +**/ +VOID +EFIAPI +PchNmi2SmiClearSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + // No need to clear NMI2SMI_STS since it's cleared when NMI source is cl= eared. + // Clear TCO status only. + PchSmmClearSource (&mDescSrcTcoSts); +} + +/** + The register function used to register SMI handler of NMI event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiNmiRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescNmi, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchTcoSmiNmiType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + // + // Since the NMI2SMI status and enable bit are at the same register, + // it needs separate function to handle the source enable and clear. + // + Record->ClearSource =3D PchNmi2SmiClearSource; + PchNmi2SmiEnableSource (); + SmiHandlerProfileRegisterHandler (&gPchTcoSmiDispatchProtocolGuid, (EF= I_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NUL= L, 0); + } + return Status; +} + +// +// IntruderDetect srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescIntruderDe= t =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_TCO + }, + { + { + TCO_ADDR_TYPE, + {R_TCO_IO_TCO2_CNT} + }, + S_TCO_IO_TCO2_CNT, + N_TCO_IO_TCO2_CNT_INTRD_SEL + } + }, + { + { + { + TCO_ADDR_TYPE, + {R_TCO_IO_TCO2_STS} + }, + S_TCO_IO_TCO2_STS, + N_TCO_IO_TCO2_STS_INTRD_DET + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + The register function used to register SMI handler of Intruder Detect ev= ent. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiIntruderDetRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescIntruderDet, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchTcoSmiIntruderDetectType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + Record->ClearSource =3D PchTcoSmiClearSourceAndBlock; + PchSmmClearSource (&Record->SrcDesc); + PchSmmEnableSource (&Record->SrcDesc); + SmiHandlerProfileRegisterHandler (&gPchTcoSmiDispatchProtocolGuid, (EF= I_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NUL= L, 0); + } + return Status; +} + +// +// SpiBiosWp srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescSpiBiosWp = =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_TCO + }, + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_SPI << 19) | + (PCI_FUNCTION_NUMBER_PCH_SPI << 16) | + R_SPI_CFG_BC + ) } + }, + S_SPI_CFG_BC, + N_SPI_CFG_BC_BLE + }, + }, + { + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_SPI << 19) | + (PCI_FUNCTION_NUMBER_PCH_SPI << 16) | + R_SPI_CFG_BC + ) } + }, + S_SPI_CFG_BC, + N_SPI_CFG_BC_SYNC_SS + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + Special handling for SPI Write Protect + + @param[in] SrcDesc Not used +**/ +VOID +EFIAPI +PchTcoSpiWpClearSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + UINT64 SpiRegBase; + UINT32 BiosControl; + UINT32 Timeout; + + SpiRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + PciSegmentAndThenOr32 ( + SpiRegBase + R_SPI_CFG_BC, + (UINT32) ~B_SPI_CFG_BC_ASYNC_SS, + B_SPI_CFG_BC_SYNC_SS + ); + // + // Ensure the SYNC is cleared + // + Timeout =3D 1000; + do { + BiosControl =3D PciSegmentRead32 (SpiRegBase + R_SPI_CFG_BC); + Timeout--; + } while ((BiosControl & B_SPI_CFG_BC_SYNC_SS) && (Timeout > 0)); + // + // Any TCO-based status bits require special handling. + // SMI_STS.TCO_STS must be cleared in addition to the status bit in the = TCO registers + // + PchSmmClearSource (&mDescSrcTcoSts); +} + +/** + The register function used to register SMI handler of BIOS write protect= event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiSpiBiosWpRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescSpiBiosWp, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchTcoSmiSpiBiosWpType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + Record->ClearSource =3D PchTcoSpiWpClearSource; + PchTcoSpiWpClearSource (NULL); + // + // It doesn't enable the BIOSLOCK here. Enable it by policy in DXE. + // + SmiHandlerProfileRegisterHandler (&gPchTcoSmiDispatchProtocolGuid, (EF= I_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NUL= L, 0); + } + return Status; +} + +// +// LpcBiosWp srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescLpcBiosWp = =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_TCO + }, + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_LPC << 19) | + (PCI_FUNCTION_NUMBER_PCH_LPC << 16) | + R_LPC_CFG_BC + ) } + }, + S_LPC_CFG_BC, + N_LPC_CFG_BC_LE + } + }, + { + { + { + TCO_ADDR_TYPE, + {R_TCO_IO_TCO1_STS} + }, + S_TCO_IO_TCO1_STS, + N_TCO_IO_TCO1_STS_BIOSWR + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + The register function used to register SMI handler of LPC BIOS write pro= tect event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiLpcBiosWpRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + if (IsEspiEnabled ()) { + // + // Status is D31F0's PCBC.BWPDS + // + ASSERT (FALSE); + return EFI_UNSUPPORTED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescLpcBiosWp, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchTcoSmiLpcBiosWpType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + Record->ClearSource =3D PchTcoSmiClearSource; + PchSmmClearSource (&Record->SrcDesc); + // + // It doesn't enable the BIOSLOCK here. Enable it by policy in DXE. + // + SmiHandlerProfileRegisterHandler (&gPchTcoSmiDispatchProtocolGuid, (EF= I_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NUL= L, 0); + } + return Status; +} + +// +// NEWCENTURY_STS bit that needs to be cleared +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescNewCentury= =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_TCO + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + TCO_ADDR_TYPE, + {R_TCO_IO_TCO1_STS} + }, + S_TCO_IO_TCO1_STS, + N_TCO_IO_TCO1_STS_NEWCENTURY + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + The register function used to register SMI handler of NEW CENTURY event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiNewCenturyRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescNewCentury, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchTcoSmiNewCenturyType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + Record->ClearSource =3D PchTcoSmiClearSourceAndBlock; + PchSmmClearSource (&Record->SrcDesc); + PchSmmEnableSource (&Record->SrcDesc); + SmiHandlerProfileRegisterHandler (&gPchTcoSmiDispatchProtocolGuid, (EF= I_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NUL= L, 0); + } + return Status; +} + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchTcoSmiUnRegister ( + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *Record; + EFI_STATUS Status; + + Record =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + if ((Record->SrcDesc.En[1].Reg.Type =3D=3D ACPI_ADDR_TYPE) && + (Record->SrcDesc.En[1].Reg.Data.pcie.Fields.Dev =3D=3D PCI_DEVICE_NU= MBER_PCH_SPI) && + (Record->SrcDesc.En[1].Reg.Data.pcie.Fields.Fnc =3D=3D PCI_FUNCTION_= NUMBER_PCH_SPI) && + (Record->SrcDesc.En[1].Reg.Data.pcie.Fields.Reg =3D=3D R_SPI_CFG_BC)= && + (Record->SrcDesc.En[1].Bit =3D=3D N_SPI_CFG_BC_BLE)) { + // + // SPI Write Protect cannot be disabled + // + return EFI_ACCESS_DENIED; + } else if ((Record->SrcDesc.En[1].Reg.Type =3D=3D ACPI_ADDR_TYPE) && + (Record->SrcDesc.En[1].Reg.Data.pcie.Fields.Dev =3D=3D PCI_DE= VICE_NUMBER_PCH_LPC) && + (Record->SrcDesc.En[1].Reg.Data.pcie.Fields.Fnc =3D=3D PCI_FU= NCTION_NUMBER_PCH_LPC) && + (Record->SrcDesc.En[1].Reg.Data.pcie.Fields.Reg =3D=3D R_LPC_= CFG_BC) && + (Record->SrcDesc.En[1].Bit =3D=3D N_LPC_CFG_BC_LE)) { + // + // eSPI/LPC Write Protect cannot be disabled + // + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmmCoreUnRegister (NULL, DispatchHandle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileUnregisterHandler (&gPchTcoSmiDispatchProtocolGuid, R= ecord->Callback, NULL, 0); + } + return Status; +} + + +// +// PcieRpHotPlug srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_SMM_SOURCE_DESC PchPcieSmiRpHotPlugTempl= ate =3D { + PCH_SMM_NO_FLAGS, + { + { + { + PCIE_ADDR_TYPE, + {R_PCH_PCIE_CFG_MPC} + }, + S_PCH_PCIE_CFG_MPC, + N_PCH_PCIE_CFG_MPC_HPME + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCIE_ADDR_TYPE, + {R_PCH_PCIE_CFG_SMSCS} + }, + S_PCH_PCIE_CFG_SMSCS, + N_PCH_PCIE_CFG_SMSCS_HPPDM + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_PCI_EXP + } +}; + +/** + The register function used to register SMI handler of PCIE RP hotplug ev= ent. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[in] RpIndex Indicate the RP index (0-based) + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchPcieSmiHotPlugRegister ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, + IN UINTN RpIndex, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + UINTN RpDev; + UINTN RpFun; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + GetPchPcieRpDevFun (RpIndex, &RpDev, &RpFun); + // + // Patch the RP device number and function number of srcdesc. + // + PchPcieSmiRpHotPlugTemplate.En[0].Reg.Data.pcie.Fields.Dev =3D (UINT8) R= pDev; + PchPcieSmiRpHotPlugTemplate.En[0].Reg.Data.pcie.Fields.Fnc =3D (UINT8) R= pFun; + PchPcieSmiRpHotPlugTemplate.Sts[0].Reg.Data.pcie.Fields.Dev =3D (UINT8) = RpDev; + PchPcieSmiRpHotPlugTemplate.Sts[0].Reg.Data.pcie.Fields.Fnc =3D (UINT8) = RpFun; + + Status =3D PchSmiRecordInsert ( + &PchPcieSmiRpHotPlugTemplate, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchPcieSmiRpHotplugType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchPcieSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + PchSmmClearSource (&PchPcieSmiRpHotPlugTemplate); + PchSmmEnableSource (&PchPcieSmiRpHotPlugTemplate); + + return Status; +} + +// +// PcieRpLinkActive srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_SMM_SOURCE_DESC PchPcieSmiRpLinkActiveTe= mplate =3D { + PCH_SMM_NO_FLAGS, + { + { + { + PCIE_ADDR_TYPE, + {R_PCH_PCIE_CFG_MPC} + }, + S_PCH_PCIE_CFG_MPC, + N_PCH_PCIE_CFG_MPC_HPME + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCIE_ADDR_TYPE, + {R_PCH_PCIE_CFG_SMSCS} + }, + S_PCH_PCIE_CFG_SMSCS, + N_PCH_PCIE_CFG_SMSCS_HPLAS + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_PCI_EXP + } +}; + +/** + The register function used to register SMI handler of PCIE RP link activ= e event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[in] RpIndex Indicate the RP index (0-based) + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchPcieSmiLinkActiveRegister ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, + IN UINTN RpIndex, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + UINTN RpDev; + UINTN RpFun; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + GetPchPcieRpDevFun (RpIndex, &RpDev, &RpFun); + // + // Patch the RP device number and function number of srcdesc. + // + PchPcieSmiRpLinkActiveTemplate.En[0].Reg.Data.pcie.Fields.Dev =3D (UINT8= ) RpDev; + PchPcieSmiRpLinkActiveTemplate.En[0].Reg.Data.pcie.Fields.Fnc =3D (UINT8= ) RpFun; + PchPcieSmiRpLinkActiveTemplate.Sts[0].Reg.Data.pcie.Fields.Dev =3D (UINT= 8) RpDev; + PchPcieSmiRpLinkActiveTemplate.Sts[0].Reg.Data.pcie.Fields.Fnc =3D (UINT= 8) RpFun; + + Status =3D PchSmiRecordInsert ( + &PchPcieSmiRpLinkActiveTemplate, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchPcieSmiRpLinkActiveType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchPcieSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + PchSmmClearSource (&PchPcieSmiRpLinkActiveTemplate); + PchSmmEnableSource (&PchPcieSmiRpLinkActiveTemplate); + + return Status; +} + +// +// PcieRpLinkEq srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED PCH_SMM_SOURCE_DESC PchPcieSmiRpLinkEqTempla= te =3D { + PCH_SMM_NO_FLAGS, + { + { + { + PCIE_ADDR_TYPE, + {R_PCH_PCIE_CFG_EQCFG1} + }, + S_PCH_PCIE_CFG_EQCFG1, + N_PCH_PCIE_CFG_EQCFG1_LERSMIE + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCIE_ADDR_TYPE, + {R_PCH_PCIE_CFG_SMSCS} + }, + S_PCH_PCIE_CFG_SMSCS, + N_PCH_PCIE_CFG_SMSCS_LERSMIS + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_PCI_EXP + } +}; + +/** + The register function used to register SMI handler of PCIE RP Link Equal= ization Request event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[in] RpIndex Indicate the RP index (0-based) + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchPcieSmiLinkEqRegister ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction, + IN UINTN RpIndex, + OUT EFI_HANDLE *DispatchHandle + ) +{ + UINTN RpDev; + UINTN RpFun; + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + GetPchPcieRpDevFun (RpIndex, &RpDev, &RpFun); + // + // Patch the RP device number and function number of srcdesc. + // + PchPcieSmiRpLinkEqTemplate.En[0].Reg.Data.pcie.Fields.Dev =3D (UINT8) Rp= Dev; + PchPcieSmiRpLinkEqTemplate.En[0].Reg.Data.pcie.Fields.Fnc =3D (UINT8) Rp= Fun; + PchPcieSmiRpLinkEqTemplate.Sts[0].Reg.Data.pcie.Fields.Dev =3D (UINT8) R= pDev; + PchPcieSmiRpLinkEqTemplate.Sts[0].Reg.Data.pcie.Fields.Fnc =3D (UINT8) R= pFun; + + Status =3D PchSmiRecordInsert ( + &PchPcieSmiRpLinkEqTemplate, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchPcieSmiRpLinkEqType, + DispatchHandle + ); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchPcieSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2) DispatchFunction, (UINTN)RETURN_ADDRESS (0), N= ULL, 0); + } + return Status; +} + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchPcieSmiUnRegister ( + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *RecordToDelete; + EFI_STATUS Status; + + RecordToDelete =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + Status =3D PchSmmCoreUnRegister (NULL, DispatchHandle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileUnregisterHandler (&gPchPcieSmiDispatchProtocolGuid= , RecordToDelete->Callback, NULL, 0); + } + return Status; +} + +// +// Pme srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescPme =3D { + PCH_SMM_SCI_EN_DEPENDENT, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_GPE0_EN_127_96} + }, + S_ACPI_IO_GPE0_EN_127_96, + N_ACPI_IO_GPE0_EN_127_96_PME + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_GPE0_STS_127_96} + }, + S_ACPI_IO_GPE0_STS_127_96, + N_ACPI_IO_GPE0_STS_127_96_PME + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_GPE0 + } +}; + +/** + The register function used to register SMI handler of PME event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchAcpiSmiPmeRegister ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescPme, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchAcpiSmiPmeType, + DispatchHandle + ); + PchSmmClearSource (&mSrcDescPme); + PchSmmEnableSource (&mSrcDescPme); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchAcpiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +// +// PmeB0 srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescPmeB0 =3D { + PCH_SMM_SCI_EN_DEPENDENT, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_GPE0_EN_127_96} + }, + S_ACPI_IO_GPE0_EN_127_96, + N_ACPI_IO_GPE0_EN_127_96_PME_B0 + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_GPE0_STS_127_96} + }, + S_ACPI_IO_GPE0_STS_127_96, + N_ACPI_IO_GPE0_STS_127_96_PME_B0 + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_GPE0 + } +}; +/** + The register function used to register SMI handler of PME B0 event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchAcpiSmiPmeB0Register ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescPmeB0, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchAcpiSmiPmeB0Type, + DispatchHandle + ); + PchSmmClearSource (&mSrcDescPmeB0); + PchSmmEnableSource (&mSrcDescPmeB0); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchAcpiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +// +// RtcAlarm srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescRtcAlarm = =3D { + PCH_SMM_SCI_EN_DEPENDENT, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_PM1_EN} + }, + S_ACPI_IO_PM1_EN, + N_ACPI_IO_PM1_EN_RTC + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_PM1_STS} + }, + S_ACPI_IO_PM1_STS, + N_ACPI_IO_PM1_STS_RTC + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_PM1_STS_REG + } +}; + +/** + The register function used to register SMI handler of RTC alarm event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchAcpiSmiRtcAlarmRegister ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescRtcAlarm, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchAcpiSmiRtcAlarmType, + DispatchHandle + ); + + PchSmmClearSource (&mSrcDescRtcAlarm); + PchSmmEnableSource (&mSrcDescRtcAlarm); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchAcpiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +// +// TmrOverflow srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescTmrOverflo= w =3D { + PCH_SMM_SCI_EN_DEPENDENT, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_PM1_EN} + }, + S_ACPI_IO_PM1_EN, + N_ACPI_IO_PM1_EN_TMROF + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_PM1_STS} + }, + S_ACPI_IO_PM1_STS, + N_ACPI_IO_PM1_STS_TMROF + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_PM1_STS_REG + } +}; + +/** + The register function used to register SMI handler of Timer Overflow eve= nt. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchAcpiSmiTmrOverflowRegister ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescTmrOverflow, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchAcpiSmiTmrOverflowType, + DispatchHandle + ); + PchSmmClearSource (&mSrcDescTmrOverflow); + PchSmmEnableSource (&mSrcDescTmrOverflow); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchAcpiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + + return Status; +} + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchAcpiSmiUnRegister ( + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *RecordToDelete; + EFI_STATUS Status; + + RecordToDelete =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + Status =3D PchSmmCoreUnRegister (NULL, DispatchHandle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileUnregisterHandler (&gPchAcpiSmiDispatchProtocolGuid, = RecordToDelete->Callback, NULL, 0); + } + return Status; +} + +// +// SerialIrq srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescSerialIrq = =3D { + PCH_SMM_NO_FLAGS, + { + NULL_BIT_DESC_INITIALIZER, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_SERIRQ + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_SERIRQ + } +}; + +/** + The register function used to register SMI handler of Serial IRQ event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchSmiSerialIrqRegister ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescSerialIrq, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchSmiSerialIrqType, + DispatchHandle + ); + PchSmmClearSource (&mSrcDescSerialIrq); + PchSmmEnableSource (&mSrcDescSerialIrq); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchSmiDispatchProtocolGuid, (EFI_= SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NULL,= 0); + } + return Status; +} + +// +// McSmi srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescMcSmi =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_MCSMI + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_MCSMI + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_MCSMI + } +}; + +/** + The register function used to register SMI handler of MCSMI event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchSmiMcSmiRegister ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescMcSmi, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchSmiMcSmiType, + DispatchHandle + ); + PchSmmClearSource (&mSrcDescMcSmi); + PchSmmEnableSource (&mSrcDescMcSmi); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchSmiDispatchProtocolGuid, (EFI_S= MM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NULL, = 0); + } + return Status; +} + +// +// SmBus srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescSmbus =3D { + PCH_SMM_NO_FLAGS, + { + NULL_BIT_DESC_INITIALIZER, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_SMBUS + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_SMBUS + } +}; + +/** + The register function used to register SMI handler of SMBUS event. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchSmiSmbusRegister ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescSmbus, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchSmiSmBusType, + DispatchHandle + ); + PchSmmClearSource (&mSrcDescSmbus); + PchSmmEnableSource (&mSrcDescSmbus); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchSmiDispatchProtocolGuid, (EFI_S= MM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NULL, = 0); + } + return Status; +} + +// +// SpiAsyncSmi srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescSpiAsyncSm= i =3D { + PCH_SMM_NO_FLAGS, + { + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_SPI << 19) | + (PCI_FUNCTION_NUMBER_PCH_SPI << 16) | + R_SPI_CFG_BC + ) } + }, + S_SPI_CFG_BC, + N_SPI_CFG_BC_ASE_BWP + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_SPI << 19) | + (PCI_FUNCTION_NUMBER_PCH_SPI << 16) | + R_SPI_CFG_BC + ) } + }, + S_SPI_CFG_BC, + N_SPI_CFG_BC_ASYNC_SS + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_SPI + } +}; + +/** + Special handling for SPI Asynchronous SMI. + If SPI ASYNC SMI is enabled, De-assert SMI is sent when Flash Cycle Done + transitions from 1 to 0 or when the SMI enable becomes false. + + @param[in] SrcDesc Not used +**/ +VOID +EFIAPI +PchSmiSpiAsyncClearSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + UINT64 SpiRegBase; + UINT32 SpiBar0; + + SpiRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + SpiBar0 =3D PciSegmentRead32 (SpiRegBase + R_SPI_CFG_BAR0) & ~(B_SPI_CFG= _BAR0_MASK); + if (SpiBar0 !=3D PCH_SPI_BASE_ADDRESS) { + // + // Temporary disable MSE, and override with SPI reserved MMIO address,= then enable MSE. + // + SpiBar0 =3D PCH_SPI_BASE_ADDRESS; + PciSegmentAnd8 (SpiRegBase + PCI_COMMAND_OFFSET, (UINT8) ~EFI_PCI_COMM= AND_MEMORY_SPACE); + PciSegmentWrite32 (SpiRegBase + R_SPI_CFG_BAR0, SpiBar0); + PciSegmentOr8 (SpiRegBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY= _SPACE); + } + + MmioOr32 (SpiBar0 + R_SPI_MEM_HSFSC, B_SPI_MEM_HSFSC_FDONE); +} + +/** + Special handling to enable SPI Asynchronous SMI +**/ +VOID +PchSmiSpiAsyncEnableSource ( + VOID + ) +{ + UINT64 SpiRegBase; + SpiRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + PciSegmentAndThenOr32 ( + SpiRegBase + R_SPI_CFG_BC, + (UINT32) ~B_SPI_CFG_BC_SYNC_SS, + B_SPI_CFG_BC_ASE_BWP + ); + + // + // Clear the source + // + PchSmiSpiAsyncClearSource (NULL); +} + +/** + The register function used to register SMI handler of SPI Asynchronous e= vent. + + @param[in] This The pointer to the protocol itself + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchSmiSpiAsyncRegister ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D PchSmiRecordInsert ( + &mSrcDescSpiAsyncSmi, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchSmiSpiAsyncType, + DispatchHandle + ); + + if (!EFI_ERROR (Status)) { + Record =3D DATABASE_RECORD_FROM_LINK (*DispatchHandle); + Record->ClearSource =3D PchSmiSpiAsyncClearSource; + PchSmiSpiAsyncClearSource (NULL); + PchSmiSpiAsyncEnableSource (); + SmiHandlerProfileRegisterHandler (&gPchSmiDispatchProtocolGuid, (EFI_S= MM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NULL, = 0); + } + return Status; +} + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered + @retval EFI_ACCESS_DENIED Return access denied since SPI ayn= c SMI handler is not able to disabled. +**/ +EFI_STATUS +EFIAPI +PchSmiUnRegister ( + IN PCH_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *Record; + UINT64 SpiRegBase; + EFI_STATUS Status; + + Record =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + if ((Record->SrcDesc.En[0].Reg.Type =3D=3D PCIE_ADDR_TYPE) && + (Record->SrcDesc.En[0].Reg.Data.pcie.Fields.Dev =3D=3D PCI_DEVICE_NU= MBER_PCH_SPI) && + (Record->SrcDesc.En[0].Reg.Data.pcie.Fields.Fnc =3D=3D PCI_FUNCTION_= NUMBER_PCH_SPI) && + (Record->SrcDesc.En[0].Reg.Data.pcie.Fields.Reg =3D=3D R_SPI_CFG_BC)= && + (Record->SrcDesc.En[0].Bit =3D=3D N_SPI_CFG_BC_ASE_BWP)) { + SpiRegBase =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + 0 + ); + if (PciSegmentRead8 (SpiRegBase + R_SPI_CFG_BC) & B_SPI_CFG_BC_BILD) { + // + // SPI Asynchronous SMI cannot be disabled + // + return EFI_ACCESS_DENIED; + } + } + Status =3D PchSmmCoreUnRegister (NULL, DispatchHandle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileUnregisterHandler (&gPchSmiDispatchProtocolGuid, Reco= rd->Callback, NULL, 0); + } + return Status; +} + + +/** + Declaration of PCH TCO SMI DISPATCH PROTOCOL instance +**/ +PCH_TCO_SMI_DISPATCH_PROTOCOL mPchTcoSmiDispatchProtocol =3D { + PCH_TCO_SMI_DISPATCH_REVISION, // Revision + PchTcoSmiUnRegister, // Unregister + PchTcoSmiMchRegister, // Mch + PchTcoSmiTcoTimeoutRegister, // TcoTimeout + PchTcoSmiOsTcoRegister, // OsTco + PchTcoSmiNmiRegister, // Nmi + PchTcoSmiIntruderDetRegister, // IntruderDectect + PchTcoSmiSpiBiosWpRegister, // SpiBiosWp + PchTcoSmiLpcBiosWpRegister, // LpcBiosWp + PchTcoSmiNewCenturyRegister // NewCentury +}; + +/** + Declaration of PCH PCIE SMI DISPATCH PROTOCOL instance +**/ +PCH_PCIE_SMI_DISPATCH_PROTOCOL mPchPcieSmiDispatchProtocol =3D { + PCH_PCIE_SMI_DISPATCH_REVISION, // Revision + PchPcieSmiUnRegister, // Unregister + PchPcieSmiHotPlugRegister, // PcieRpXHotPlug + PchPcieSmiLinkActiveRegister, // PcieRpXLinkActive + PchPcieSmiLinkEqRegister // PcieRpXLinkEq +}; + +/** + Declaration of PCH ACPI SMI DISPATCH PROTOCOL instance +**/ +PCH_ACPI_SMI_DISPATCH_PROTOCOL mPchAcpiSmiDispatchProtocol =3D { + PCH_ACPI_SMI_DISPATCH_REVISION, // Revision + PchAcpiSmiUnRegister, // Unregister + PchAcpiSmiPmeRegister, // Pme + PchAcpiSmiPmeB0Register, // PmeB0 + PchAcpiSmiRtcAlarmRegister, // RtcAlarm + PchAcpiSmiTmrOverflowRegister // TmrOverflow +}; + +/** + Declaration of MISC PCH SMI DISPATCH PROTOCOL instance +**/ +PCH_SMI_DISPATCH_PROTOCOL mPchSmiDispatchProtocol =3D { + PCH_SMI_DISPATCH_REVISION, // Revision + PchSmiUnRegister, // Unregister + PchSmiSerialIrqRegister, // SerialIrq + PchSmiMcSmiRegister, // McSmi + PchSmiSmbusRegister, // SmBus + PchSmiSpiAsyncRegister // SpiAsync +}; + +/** + Install protocols of PCH specifics SMI types, including + PCH TCO SMI types, PCH PCIE SMI types, PCH ACPI SMI types, PCH MISC SMI = types. + + @retval the result of protocol installation +**/ +EFI_STATUS +InstallPchSmiDispatchProtocols ( + VOID + ) +{ + EFI_HANDLE Handle; + EFI_STATUS Status; + + Handle =3D NULL; + Status =3D gSmst->SmmInstallProtocolInterface ( + &Handle, + &gPchTcoSmiDispatchProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPchTcoSmiDispatchProtocol + ); + Status =3D gSmst->SmmInstallProtocolInterface ( + &Handle, + &gPchPcieSmiDispatchProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPchPcieSmiDispatchProtocol + ); + Status =3D gSmst->SmmInstallProtocolInterface ( + &Handle, + &gPchAcpiSmiDispatchProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPchAcpiSmiDispatchProtocol + ); + Status =3D gSmst->SmmInstallProtocolInterface ( + &Handle, + &gPchSmiDispatchProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPchSmiDispatchProtocol + ); + + return Status; +} + +/** + The function to dispatch all callback function of PCH SMI types. + + @retval EFI_SUCCESS Function successfully completed + @retval EFI_UNSUPPORTED no +**/ +EFI_STATUS +PchSmiTypeCallbackDispatcher ( + IN DATABASE_RECORD *Record + ) +{ + EFI_STATUS Status; + PCH_SMI_TYPES PchSmiType; + UINTN RpIndex; + PCH_PCIE_SMI_RP_CONTEXT RpContext; + + PchSmiType =3D Record->PchSmiType; + Status =3D EFI_SUCCESS; + + switch (PchSmiType) { + case PchTcoSmiMchType: + case PchTcoSmiTcoTimeoutType: + case PchTcoSmiOsTcoType: + case PchTcoSmiNmiType: + case PchTcoSmiIntruderDetectType: + case PchTcoSmiSpiBiosWpType: + case PchTcoSmiLpcBiosWpType: + case PchTcoSmiNewCenturyType: + ((PCH_TCO_SMI_DISPATCH_CALLBACK) (Record->PchSmiCallback)) ((EFI_HAN= DLE)&Record->Link); + break; + case PchPcieSmiRpHotplugType: + case PchPcieSmiRpLinkActiveType: + case PchPcieSmiRpLinkEqType: + RpContext.BusNum =3D DEFAULT_PCI_BUS_NUMBER_PCH; + RpContext.DevNum =3D (UINT8) Record->SrcDesc.En[0].Reg.Data.pcie.Fi= elds.Dev; + RpContext.FuncNum =3D (UINT8) Record->SrcDesc.En[0].Reg.Data.pcie.Fi= elds.Fnc; + GetPchPcieRpNumber (RpContext.DevNum, RpContext.FuncNum, &RpIndex); + RpContext.RpIndex =3D (UINT8) RpIndex; + ((PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) (Record->PchSmiCallback)) ((EFI= _HANDLE)&Record->Link, &RpContext); + break; + case PchAcpiSmiPmeType: + case PchAcpiSmiPmeB0Type: + case PchAcpiSmiRtcAlarmType: + case PchAcpiSmiTmrOverflowType: + ((PCH_ACPI_SMI_DISPATCH_CALLBACK) (Record->PchSmiCallback)) ((EFI_HA= NDLE)&Record->Link); + break; + case PchEspiSmiEspiSlaveType: + ((PCH_ESPI_SMI_DISPATCH_CALLBACK) (Record->PchSmiCallback)) ((EFI_HA= NDLE)&Record->Link); + break; + case PchSmiSerialIrqType: + case PchSmiMcSmiType: + case PchSmiSmBusType: + case PchSmiSpiAsyncType: + case PchIoTrapSmiType: ///< internal type for IoTrap + ((PCH_SMI_DISPATCH_CALLBACK) (Record->PchSmiCallback)) ((EFI_HANDLE)= &Record->Link); + break; + default: + Status =3D EFI_UNSUPPORTED; + break; + } + + return Status; +} + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescIoTrap[4] = =3D { + // + // PCH I/O Trap register 0 monitor + // + { + PCH_SMM_NO_FLAGS, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_PSTH, R_PSTH_PCR_TRPREG0) } + }, + 4, + 0 + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_PSTH, R_PSTH_PCR_TRPST) } + }, + 1, + 0 + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_MONITOR + } + }, + // + // PCH I/O Trap register 1 monitor + // + { + PCH_SMM_NO_FLAGS, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_PSTH, R_PSTH_PCR_TRPREG1) } + }, + 4, + 0 + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_PSTH, R_PSTH_PCR_TRPST) } + }, + 1, + 1 + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_MONITOR + } + }, + // + // PCH I/O Trap register 2 monitor + // + { + PCH_SMM_NO_FLAGS, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_PSTH, R_PSTH_PCR_TRPREG2) } + }, + 4, + 0 + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_PSTH, R_PSTH_PCR_TRPST) } + }, + 1, + 2 + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_MONITOR + } + }, + // + // PCH I/O Trap register 3 monitor, + // + { + PCH_SMM_NO_FLAGS, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_PSTH, R_PSTH_PCR_TRPREG3) } + }, + 4, + 0 + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_PSTH, R_PSTH_PCR_TRPST) } + }, + 1, + 3 + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_MONITOR + } + } +}; + +/** + The register function used to register SMI handler of IoTrap event. + This is internal function and only used by Iotrap module. + + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for this SMI source + @param[in] IoTrapIndex Index number of IOTRAP register + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. +**/ +EFI_STATUS +PchInternalIoTrapSmiRegister ( + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction, + IN UINTN IoTrapIndex, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + Status =3D PchSmiRecordInsert ( + &mSrcDescIoTrap[IoTrapIndex], + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchIoTrapSmiType, + DispatchHandle + ); + PchSmmClearSource (&mSrcDescIoTrap[IoTrapIndex]); + PchSmmEnableSource (&mSrcDescIoTrap[IoTrapIndex]); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gEfiSmmIoTrapDispatch2ProtocolGuid,= (EFI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0),= NULL, 0); + } + return Status; +} + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. +**/ +EFI_STATUS +PchInternalIoTrapSmiUnRegister ( + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *RecordToDelete; + EFI_STATUS Status; + + RecordToDelete =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + Status =3D PchSmmCoreUnRegister (NULL, DispatchHandle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileUnregisterHandler (&gEfiSmmIoTrapDispatch2ProtocolGui= d, RecordToDelete->Callback, NULL, 0); + } + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmCore.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmCore.c new file mode 100644 index 0000000000..9c36103396 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmCor= e.c @@ -0,0 +1,911 @@ +/** @file + This driver is responsible for the registration of child drivers + and the abstraction of the PCH SMI sources. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmm.h" +#include "PchSmmHelpers.h" +#include "PchSmmEspi.h" +#include +#include +#include +#include + +// +// MODULE / GLOBAL DATA +// +// Module variables used by the both the main dispatcher and the source di= spatchers +// Declared in PchSmm.h +// +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mAcpiBaseAddr; +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mTcoBaseAddr; +GLOBAL_REMOVE_IF_UNREFERENCED BOOLEAN mReadyToLock; + +GLOBAL_REMOVE_IF_UNREFERENCED PRIVATE_DATA mPrivateData =3D { + { + NULL, + NULL + }, // CallbackDataBase linked list he= ad + NULL, // EFI handle returned when callin= g InstallMultipleProtocolInterfaces + NULL, // + { // protocol arrays + // + // elements within the array + // + { + PROTOCOL_SIGNATURE, + UsbType, + &gEfiSmmUsbDispatch2ProtocolGuid, + {{ + (PCH_SMM_GENERIC_REGISTER) PchPiSmmCoreRegister, + (PCH_SMM_GENERIC_UNREGISTER) PchPiSmmCoreUnRegister + }} + }, + { + PROTOCOL_SIGNATURE, + SxType, + &gEfiSmmSxDispatch2ProtocolGuid, + {{ + (PCH_SMM_GENERIC_REGISTER) PchPiSmmCoreRegister, + (PCH_SMM_GENERIC_UNREGISTER) PchPiSmmCoreUnRegister + }} + }, + { + PROTOCOL_SIGNATURE, + SwType, + &gEfiSmmSwDispatch2ProtocolGuid, + {{ + (PCH_SMM_GENERIC_REGISTER) PchSwSmiRegister, + (PCH_SMM_GENERIC_UNREGISTER) PchSwSmiUnRegister, + (UINTN) MAXIMUM_SWI_VALUE + }} + }, + { + PROTOCOL_SIGNATURE, + GpiType, + &gEfiSmmGpiDispatch2ProtocolGuid, + {{ + (PCH_SMM_GENERIC_REGISTER) PchGpiSmiRegister, + (PCH_SMM_GENERIC_UNREGISTER) PchGpiSmiUnRegister, + (UINTN) PCH_GPIO_NUM_SUPPORTED_GPIS + }} + }, + { + PROTOCOL_SIGNATURE, + PowerButtonType, + &gEfiSmmPowerButtonDispatch2ProtocolGuid, + {{ + (PCH_SMM_GENERIC_REGISTER) PchPiSmmCoreRegister, + (PCH_SMM_GENERIC_UNREGISTER) PchPiSmmCoreUnRegister + }} + }, + { + PROTOCOL_SIGNATURE, + PeriodicTimerType, + &gEfiSmmPeriodicTimerDispatch2ProtocolGuid, + {{ + (PCH_SMM_GENERIC_REGISTER) PchPiSmmCoreRegister, + (PCH_SMM_GENERIC_UNREGISTER) PchPiSmmCoreUnRegister, + (UINTN) PchSmmPeriodicTimerDispatchGetNextShorterInterval + }} + }, + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED CONTEXT_FUNCTIONS mContextFunctions[PCH_= SMM_PROTOCOL_TYPE_MAX] =3D { + { + NULL, + NULL, + NULL + }, + { + SxGetContext, + SxCmpContext, + NULL + }, + { + NULL, + NULL, + NULL + }, + { + NULL, + NULL, + NULL + }, + { + PowerButtonGetContext, + PowerButtonCmpContext, + NULL + }, + { + PeriodicTimerGetContext, + PeriodicTimerCmpContext, + PeriodicTimerGetCommBuffer + }, +}; + +// +// PROTOTYPES +// +// Functions use only in this file +// +EFI_STATUS +EFIAPI +PchSmmCoreDispatcher ( + IN EFI_HANDLE SmmImageHandle, + IN CONST VOID *PchSmmCore, OPTIONAL + IN OUT VOID *CommunicationBuffer, + IN OUT UINTN *SourceSize + ); + +// +// FUNCTIONS +// +/** + SMM ready to lock notification event handler. + + @param Protocol Points to the protocol's unique identifier + @param Interface Points to the interface instance + @param Handle The handle on which the interface was installed + + @retval EFI_SUCCESS SmmReadyToLockCallback runs successfully + +**/ +EFI_STATUS +EFIAPI +SmmReadyToLockCallback ( + IN CONST EFI_GUID *Protocol, + IN VOID *Interface, + IN EFI_HANDLE Handle + ) +{ + mReadyToLock =3D TRUE; + + return EFI_SUCCESS; +} + +/** + PchSmiDispatcher SMM Module Entry Point\n + - Introduction\n + The PchSmiDispatcher module is an SMM driver which provides SMI handl= er registration + services for PCH generated SMIs. + + - Details\n + This module provides SMI handler registration servicies for PCH SMIs. + NOTE: All the register/unregister functions will be locked after SMM r= eady to boot signal event. + Please make sure no handler is installed after that. + + - @pre + - EFI_SMM_BASE2_PROTOCOL + - Documented in the System Management Mode Core Interface Specificat= ion + - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + - Documented in the UEFI 2.0 Specification and above + - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + - This is to ensure that PCI MMIO and IO resource has been prepared = and available for this driver to allocate. + - EFI_SMM_CPU_PROTOCOL + + - @result + The PchSmiDispatcher driver produces: + - EFI_SMM_USB_DISPATCH2_PROTOCOL + - EFI_SMM_SX_DISPATCH2_PROTOCOL + - EFI_SMM_SW_DISPATCH2_PROTOCOL + - EFI_SMM_GPI_DISPATCH2_PROTOCOL + - EFI_SMM_IO_TRAP_DISPATCH2_PROTOCOL + - EFI_SMM_POWER_BUTTON_DISPATCH2_PROTOCOL + - EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL + - @link _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_PROT= OCOL @endlink + - @link _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PROTOCOL= @endlink + - @link _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PROTOCOL @= endlink + - @link _PCH_ACPI_SMI_DISPATCH_PROTOCOL PCH_ACPI_SMI_DISPATCH_PROTOCOL= @endlink + - @link _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCOL @endlink + - @link _PCH_ESPI_SMI_DISPATCH_PROTOCOL PCH_ESPI_SMI_DISPATCH_PROTOCOL= @endlink + + @param[in] ImageHandle Pointer to the loaded image protocol for= this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS PchSmmDispatcher Initialization complete= d. +**/ +EFI_STATUS +EFIAPI +InitializePchSmmDispatcher ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + VOID *SmmReadyToLockRegistration; + + // + // Access ACPI Base Addresses Register + // + + mAcpiBaseAddr =3D PmcGetAcpiBase (); + ASSERT (mAcpiBaseAddr !=3D 0); + + // + // Access TCO Base Addresses Register + // + PchTcoBaseGet (&mTcoBaseAddr); + ASSERT (mTcoBaseAddr !=3D 0); + + + // + // Register a callback function to handle subsequent SMIs. This callback + // will be called by SmmCoreDispatcher. + // + Status =3D gSmst->SmiHandlerRegister (PchSmmCoreDispatcher, NULL, &mPriv= ateData.SmiHandle); + ASSERT_EFI_ERROR (Status); + // + // Initialize Callback DataBase + // + InitializeListHead (&mPrivateData.CallbackDataBase); + + // + // Enable SMIs on the PCH now that we have a callback + // + PchSmmInitHardware (); + + // + // Install and initialize all the needed protocols + // + PchSwDispatchInit (); + PchSmmPublishDispatchProtocols (); + InstallPchSmiDispatchProtocols (); + InstallIoTrap (ImageHandle); + InstallEspiSmi (ImageHandle); + InstallPchSmmPeriodicTimerControlProtocol (mPrivateData.InstallMultProtH= andle); + + // + // Register EFI_SMM_READY_TO_LOCK_PROTOCOL_GUID notify function. + // + Status =3D gSmst->SmmRegisterProtocolNotify ( + &gEfiSmmReadyToLockProtocolGuid, + SmmReadyToLockCallback, + &SmmReadyToLockRegistration + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + The internal function used to create and insert a database record + + @param[in] InsertRecord Record to insert to database. + @param[out] DispatchHandle Handle of dispatch function to reg= ister. + + @retval EFI_INVALID_PARAMETER Error with NULL SMI source descrip= tion + @retval EFI_OUT_OF_RESOURCES Fail to allocate pool for database= record + @retval EFI_SUCCESS The database record is created suc= cessfully. +**/ +EFI_STATUS +SmmCoreInsertRecord ( + IN DATABASE_RECORD *NewRecord, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + if ((NewRecord =3D=3D NULL) || + (NewRecord->Signature !=3D DATABASE_RECORD_SIGNATURE)) + { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Status =3D gSmst->SmmAllocatePool (EfiRuntimeServicesData, sizeof (DATAB= ASE_RECORD), (VOID **) &Record); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + CopyMem (Record, NewRecord, sizeof (DATABASE_RECORD)); + + // + // After ensuring the source of event is not null, we will insert the re= cord into the database + // + InsertTailList (&mPrivateData.CallbackDataBase, &Record->Link); + + // + // Child's handle will be the address linked list link in the record + // + *DispatchHandle =3D (EFI_HANDLE) (&Record->Link); + + return EFI_SUCCESS; +} + +/** + Unregister a child SMI source dispatch function with a parent SMM driver + + @param[in] This Protocol instance pointer. + @param[in] DispatchHandle Handle of dispatch function to der= egister. + + @retval EFI_SUCCESS The dispatch function has been suc= cessfully + unregistered and the SMI source ha= s been disabled + if there are no other registered c= hild dispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered +**/ +EFI_STATUS +EFIAPI +PchPiSmmCoreUnRegister ( + IN PCH_SMM_GENERIC_PROTOCOL *This, + IN EFI_HANDLE *DispatchHandle + ) +{ + DATABASE_RECORD *RecordToDelete; + EFI_STATUS Status; + PCH_SMM_QUALIFIED_PROTOCOL *Qualified; + + Qualified =3D QUALIFIED_PROTOCOL_FROM_GENERIC (This); + RecordToDelete =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + Status =3D PchSmmCoreUnRegister (NULL, DispatchHandle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileUnregisterHandler (Qualified->Guid, RecordToDelete->C= allback, NULL, 0); + } + return Status; +} + +/** + Register a child SMI dispatch function with a parent SMM driver. + + @param[in] This Pointer to the PCH_SMM_GENERIC_PROTOCOL = instance. + @param[in] DispatchFunction Pointer to dispatch function to be invok= ed for this SMI source. + @param[in] DispatchContext Pointer to the dispatch function's conte= xt. + @param[out] DispatchHandle Handle of dispatch function, for when in= terfacing + with the parent SMM driver, will be the = address of linked + list link in the call back record. + + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databas= e record + @retval EFI_INVALID_PARAMETER The input parameter is invalid + @retval EFI_SUCCESS The dispatch function has been successfu= lly + registered and the SMI source has been e= nabled. +**/ +EFI_STATUS +EFIAPI +PchPiSmmCoreRegister ( + IN PCH_SMM_GENERIC_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN PCH_SMM_CONTEXT *DispatchContext, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD Record; + PCH_SMM_QUALIFIED_PROTOCOL *Qualified; + PCH_SMM_SOURCE_DESC NullSourceDesc; + + // + // Initialize NullSourceDesc + // + NullInitSourceDesc (&NullSourceDesc); + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the EndOfDxe event ha= s been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + ZeroMem (&Record, sizeof (DATABASE_RECORD)); + + // + // Gather information about the registration request + // + Record.Callback =3D DispatchFunction; + + Qualified =3D QUALIFIED_PROTOCOL_FROM_GENERIC (This); + + Record.ProtocolType =3D Qualified->Type; + + Record.ContextFunctions =3D mContextFunctions[Qualified->Type]; + // + // Perform linked list housekeeping + // + Record.Signature =3D DATABASE_RECORD_SIGNATURE; + + switch (Qualified->Type) { + // + // By the end of this switch statement, we'll know the + // source description the child is registering for + // + case UsbType: + Record.ContextSize =3D sizeof (EFI_SMM_USB_REGISTER_CONTEXT); + CopyMem (&Record.ChildContext, DispatchContext, Record.ContextSize); + // + // Check the validity of Context Type + // + if ((Record.ChildContext.Usb.Type < UsbLegacy) || (Record.ChildConte= xt.Usb.Type > UsbWake)) { + return EFI_INVALID_PARAMETER; + } + + MapUsbToSrcDesc (DispatchContext, &Record.SrcDesc); + Record.ClearSource =3D NULL; + // + // use default clear source function + // + break; + + case SxType: + Record.ContextSize =3D sizeof (EFI_SMM_SX_REGISTER_CONTEXT); + CopyMem (&Record.ChildContext, DispatchContext, Record.ContextSize); + // + // Check the validity of Context Type and Phase + // + if ((Record.ChildContext.Sx.Type < SxS0) || + (Record.ChildContext.Sx.Type >=3D EfiMaximumSleepType) || + (Record.ChildContext.Sx.Phase < SxEntry) || + (Record.ChildContext.Sx.Phase >=3D EfiMaximumPhase) + ) { + return EFI_INVALID_PARAMETER; + } + + CopyMem (&Record.SrcDesc, &mSxSourceDesc, sizeof (PCH_SMM_SOURCE_DES= C)); + Record.ClearSource =3D NULL; + // + // use default clear source function + // + break; + + case PowerButtonType: + Record.ContextSize =3D sizeof (EFI_SMM_POWER_BUTTON_REGISTER_CONTEXT= ); + CopyMem (&Record.ChildContext, DispatchContext, Record.ContextSize); + // + // Check the validity of Context Phase + // + if ((Record.ChildContext.PowerButton.Phase < EfiPowerButtonEntry) || + (Record.ChildContext.PowerButton.Phase > EfiPowerButtonExit)) + { + return EFI_INVALID_PARAMETER; + } + + CopyMem (&Record.SrcDesc, &mPowerButtonSourceDesc, sizeof (PCH_SMM_S= OURCE_DESC)); + Record.ClearSource =3D NULL; + // + // use default clear source function + // + break; + + case PeriodicTimerType: + Record.ContextSize =3D sizeof (EFI_SMM_PERIODIC_TIMER_REGISTER_CONTE= XT); + CopyMem (&Record.ChildContext, DispatchContext, Record.ContextSize); + // + // Check the validity of timer value + // + if (DispatchContext->PeriodicTimer.SmiTickInterval <=3D 0) { + return EFI_INVALID_PARAMETER; + } + + MapPeriodicTimerToSrcDesc (DispatchContext, &Record.SrcDesc); + Record.ClearSource =3D PchSmmPeriodicTimerClearSource; + break; + + default: + return EFI_INVALID_PARAMETER; + break; + } + + if (CompareSources (&Record.SrcDesc, &NullSourceDesc)) { + return EFI_INVALID_PARAMETER; + } + + // + // After ensuring the source of event is not null, we will insert the re= cord into the database + // Child's handle will be the address linked list link in the record + // + Status =3D SmmCoreInsertRecord ( + &Record, + DispatchHandle + ); + ASSERT_EFI_ERROR (Status); + + if (Record.ClearSource =3D=3D NULL) { + // + // Clear the SMI associated w/ the source using the default function + // + PchSmmClearSource (&Record.SrcDesc); + } else { + // + // This source requires special handling to clear + // + Record.ClearSource (&Record.SrcDesc); + } + + PchSmmEnableSource (&Record.SrcDesc); + SmiHandlerProfileRegisterHandler (Qualified->Guid, DispatchFunction, (UI= NTN)RETURN_ADDRESS (0), DispatchContext, Record.ContextSize); + + return EFI_SUCCESS; +} + +/** + Unregister a child SMI source dispatch function with a parent SMM driver. + + @param[in] This Pointer to the PCH_SMM_GENERIC_PROTOCOL = instance. + @param[in] DispatchHandle Handle of dispatch function to deregiste= r. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + unregistered and the SMI source has been= disabled + if there are no other registered child d= ispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. +**/ +EFI_STATUS +EFIAPI +PchSmmCoreUnRegister ( + IN PCH_SMM_GENERIC_PROTOCOL *This, + IN EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + BOOLEAN NeedClearEnable; + UINTN DescIndex; + DATABASE_RECORD *RecordToDelete; + DATABASE_RECORD *RecordInDb; + LIST_ENTRY *LinkInDb; + + if (DispatchHandle =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "UnRegister is not allowed if the SmmReadyToLock = event has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + RecordToDelete =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + + // + // Take the entry out of the linked list + // + if (RecordToDelete->Link.ForwardLink =3D=3D (LIST_ENTRY *) EFI_BAD_POINT= ER) { + return EFI_INVALID_PARAMETER; + } + + RemoveEntryList (&RecordToDelete->Link); + + // + // Loop through all the souces in record linked list to see if any sourc= e enable is equal. + // If any source enable is equal, we do not want to disable it. + // + for (DescIndex =3D 0; DescIndex < NUM_EN_BITS; ++DescIndex) { + if (IS_BIT_DESC_NULL (RecordToDelete->SrcDesc.En[DescIndex])) { + continue; + } + NeedClearEnable =3D TRUE; + LinkInDb =3D GetFirstNode (&mPrivateData.CallbackDataBase); + while (!IsNull (&mPrivateData.CallbackDataBase, LinkInDb)) { + RecordInDb =3D DATABASE_RECORD_FROM_LINK (LinkInDb); + if (IsBitEqualToAnySourceEn (&RecordToDelete->SrcDesc.En[DescIndex],= &RecordInDb->SrcDesc)) { + NeedClearEnable =3D FALSE; + break; + } + LinkInDb =3D GetNextNode (&mPrivateData.CallbackDataBase, &RecordInD= b->Link); + } + if (NeedClearEnable =3D=3D FALSE) { + continue; + } + WriteBitDesc (&RecordToDelete->SrcDesc.En[DescIndex], 0, FALSE); + } + Status =3D gSmst->SmmFreePool (RecordToDelete); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + return EFI_SUCCESS; +} + +/** + This function clears the pending SMI status before set EOS. + NOTE: This only clears the pending SMI with known reason. + Please do not clear unknown pending SMI status since that will hid= e potential issues. + + @param[in] SmiStsValue SMI status + @param[in] SciEn Sci Enable status +**/ +STATIC +VOID +ClearPendingSmiStatus ( + UINT32 SmiStsValue, + BOOLEAN SciEn + ) +{ + // + // Clear NewCentury status if it's not handled. + // + if (SmiStsValue & B_ACPI_IO_SMI_STS_TCO) { + if (IoRead16 (mTcoBaseAddr + R_TCO_IO_TCO1_STS) & B_TCO_IO_TCO1_STS_NE= WCENTURY) { + PchTcoSmiClearSourceAndBlock (&mSrcDescNewCentury); + } + } + // Clear PWRBTNOR_STS if it's not handled. + // + if (IoRead16 (mAcpiBaseAddr + R_ACPI_IO_PM1_STS) & B_ACPI_IO_PM1_STS_PRB= TNOR) { + IoWrite16 (mAcpiBaseAddr + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PRBTNO= R); + } + // + // Clear WADT_STS if this is triggered by WADT timer. + // + if (!SciEn) { + if ((IoRead32 (mAcpiBaseAddr + R_ACPI_IO_GPE0_EN_127_96) & B_ACPI_IO_G= PE0_EN_127_96_WADT) && + (IoRead32 (mAcpiBaseAddr + R_ACPI_IO_GPE0_STS_127_96) & B_ACPI_IO_= GPE0_STS_127_96_WADT)) { + IoWrite32 (mAcpiBaseAddr + R_ACPI_IO_GPE0_STS_127_96, B_ACPI_IO_GPE0= _STS_127_96_WADT); + } + } + // + // Clear GPIO_UNLOCK_SMI_STS in case it is set as GPIO Unlock SMI is not= supported + // + if (SmiStsValue & B_ACPI_IO_SMI_STS_GPIO_UNLOCK) { + IoWrite32 (mAcpiBaseAddr + R_ACPI_IO_SMI_STS, B_ACPI_IO_SMI_STS_GPIO_U= NLOCK); + } +} + +/** + The callback function to handle subsequent SMIs. This callback will be = called by SmmCoreDispatcher. + + @param[in] SmmImageHandle Not used + @param[in] PchSmmCore Not used + @param[in, out] CommunicationBuffer Not used + @param[in, out] SourceSize Not used + + @retval EFI_SUCCESS Function successfully completed +**/ +EFI_STATUS +EFIAPI +PchSmmCoreDispatcher ( + IN EFI_HANDLE SmmImageHandle, + IN CONST VOID *PchSmmCore, + IN OUT VOID *CommunicationBuffer, + IN OUT UINTN *SourceSize + ) +{ + // + // Used to prevent infinite loops + // + UINTN EscapeCount; + + BOOLEAN ContextsMatch; + BOOLEAN EosSet; + BOOLEAN SxChildWasDispatched; + + DATABASE_RECORD *RecordInDb; + LIST_ENTRY *LinkInDb; + DATABASE_RECORD *RecordToExhaust; + LIST_ENTRY *LinkToExhaust; + + PCH_SMM_CONTEXT Context; + VOID *CommBuffer; + UINTN CommBufferSize; + + EFI_STATUS Status; + BOOLEAN SciEn; + UINT32 SmiEnValue; + UINT32 SmiStsValue; + UINT8 Port74Save; + UINT8 Port76Save; + + PCH_SMM_SOURCE_DESC ActiveSource; + + // + // Initialize ActiveSource + // + NullInitSourceDesc (&ActiveSource); + + EscapeCount =3D 3; + ContextsMatch =3D FALSE; + EosSet =3D FALSE; + SxChildWasDispatched =3D FALSE; + Status =3D EFI_SUCCESS; + + // + // Save IO index registers + // @note: Save/Restore port 70h directly might break NMI_EN# setting, + // then save/restore 74h/76h instead. + // @note: CF8 is not saved. Prefer method is to use MMIO instead of CF8 + // + Port76Save =3D IoRead8 (R_RTC_IO_EXT_INDEX_ALT); + Port74Save =3D IoRead8 (R_RTC_IO_INDEX_ALT); + + if (!IsListEmpty (&mPrivateData.CallbackDataBase)) { + // + // We have children registered w/ us -- continue + // + while ((!EosSet) && (EscapeCount > 0)) { + EscapeCount--; + + LinkInDb =3D GetFirstNode (&mPrivateData.CallbackDataBase); + + // + // Cache SciEn, SmiEnValue and SmiStsValue to determine if source is= active + // + SciEn =3D PchSmmGetSciEn (); + SmiEnValue =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_EN)= ); + SmiStsValue =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_STS= )); + + while (!IsNull (&mPrivateData.CallbackDataBase, LinkInDb)) { + RecordInDb =3D DATABASE_RECORD_FROM_LINK (LinkInDb); + + // + // look for the first active source + // + if (!SourceIsActive (&RecordInDb->SrcDesc, SciEn, SmiEnValue, SmiS= tsValue)) { + // + // Didn't find the source yet, keep looking + // + LinkInDb =3D GetNextNode (&mPrivateData.CallbackDataBase, &Recor= dInDb->Link); + + // + // if it's the last one, try to clear EOS + // + if (IsNull (&mPrivateData.CallbackDataBase, LinkInDb)) { + // + // Clear pending SMI status before EOS + // + ClearPendingSmiStatus (SmiStsValue, SciEn); + EosSet =3D PchSmmSetAndCheckEos (); + } + } else { + // + // We found a source. If this is a sleep type, we have to go to + // appropriate sleep state anyway.No matter there is sleep child= or not + // + if (RecordInDb->ProtocolType =3D=3D SxType) { + SxChildWasDispatched =3D TRUE; + } + // + // "cache" the source description and don't query I/O anymore + // + CopyMem ((VOID *) &ActiveSource, (VOID *) &(RecordInDb->SrcDesc)= , sizeof (PCH_SMM_SOURCE_DESC)); + LinkToExhaust =3D LinkInDb; + + // + // exhaust the rest of the queue looking for the same source + // + while (!IsNull (&mPrivateData.CallbackDataBase, LinkToExhaust)) { + RecordToExhaust =3D DATABASE_RECORD_FROM_LINK (LinkToExhaust); + // + // RecordToExhaust->Link might be removed (unregistered) by Ca= llback function, and then the + // system will hang in ASSERT() while calling GetNextNode(). + // To prevent the issue, we need to get next record in DB here= (before Callback function). + // + LinkToExhaust =3D GetNextNode (&mPrivateData.CallbackDataBase,= &RecordToExhaust->Link); + + if (CompareSources (&RecordToExhaust->SrcDesc, &ActiveSource))= { + // + // These source descriptions are equal, so this callback sho= uld be + // dispatched. + // + if (RecordToExhaust->ContextFunctions.GetContext !=3D NULL) { + // + // This child requires that we get a calling context from + // hardware and compare that context to the one supplied + // by the child. + // + ASSERT (RecordToExhaust->ContextFunctions.CmpContext !=3D = NULL); + + // + // Make sure contexts match before dispatching event to ch= ild + // + RecordToExhaust->ContextFunctions.GetContext (RecordToExha= ust, &Context); + ContextsMatch =3D RecordToExhaust->ContextFunctions.CmpCon= text (&Context, &RecordToExhaust->ChildContext); + + } else { + // + // This child doesn't require any more calling context bey= ond what + // it supplied in registration. Simply pass back what it = gave us. + // + Context =3D RecordToExhaust->ChildContext; + ContextsMatch =3D TRUE; + } + + if (ContextsMatch) { + if (RecordToExhaust->ProtocolType =3D=3D PchSmiDispatchTyp= e) { + // + // For PCH SMI dispatch protocols + // + PchSmiTypeCallbackDispatcher (RecordToExhaust); + } else { + // + // For EFI standard SMI dispatch protocols + // + if (RecordToExhaust->Callback !=3D NULL) { + if (RecordToExhaust->ContextFunctions.GetCommBuffer != =3D NULL) { + // + // This callback function needs CommBuffer and CommB= ufferSize. + // Get those from child and then pass to callback fu= nction. + // + RecordToExhaust->ContextFunctions.GetCommBuffer (Rec= ordToExhaust, &CommBuffer, &CommBufferSize); + } else { + // + // Child doesn't support the CommBuffer and CommBuff= erSize. + // Just pass NULL value to callback function. + // + CommBuffer =3D NULL; + CommBufferSize =3D 0; + } + + PERF_START_EX (NULL, "SmmFunction", NULL, AsmReadTsc (= ), RecordToExhaust->ProtocolType); + RecordToExhaust->Callback ((EFI_HANDLE) & RecordToExha= ust->Link, &Context, CommBuffer, &CommBufferSize); + PERF_END_EX (NULL, "SmmFunction", NULL, AsmReadTsc (),= RecordToExhaust->ProtocolType); + if (RecordToExhaust->ProtocolType =3D=3D SxType) { + SxChildWasDispatched =3D TRUE; + } + } else { + ASSERT (FALSE); + } + } + } + } + } + + if (RecordInDb->ClearSource =3D=3D NULL) { + // + // Clear the SMI associated w/ the source using the default fu= nction + // + PchSmmClearSource (&ActiveSource); + } else { + // + // This source requires special handling to clear + // + RecordInDb->ClearSource (&ActiveSource); + } + // + // Clear pending SMI status before EOS + // + ClearPendingSmiStatus (SmiStsValue, SciEn); + // + // Also, try to clear EOS + // + EosSet =3D PchSmmSetAndCheckEos (); + // + // Queue is empty, reset the search + // + break; + } + } + } + } + // + // If you arrive here, there are two possible reasons: + // (1) you've got problems with clearing the SMI status bits in the + // ACPI table. If you don't properly clear the SMI bits, then you won't= be able to set the + // EOS bit. If this happens too many times, the loop exits. + // (2) there was a SMM communicate for callback messages that was receiv= ed prior + // to this driver. + // If there is an asynchronous SMI that occurs while processing the Call= back, let + // all of the drivers (including this one) have an opportunity to scan f= or the SMI + // and handle it. + // If not, we don't want to exit and have the foreground app. clear EOS = without letting + // these other sources get serviced. + // + // This assert is not valid with CSM legacy solution because it generate= s software SMI + // to test for legacy USB support presence. + // This may not be illegal, so we cannot assert at this time. + // + // ASSERT (EscapeCount > 0); + // + if (SxChildWasDispatched) { + // + // A child of the SmmSxDispatch protocol was dispatched during this ca= ll; + // put the system to sleep. + // + PchSmmSxGoToSleep (); + } + // + // Restore IO index registers + // @note: Save/Restore port 70h directly might break NMI_EN# setting, + // then save/restore 74h/76h instead. + // + IoWrite8 (R_RTC_IO_EXT_INDEX_ALT, Port76Save); + IoWrite8 (R_RTC_IO_INDEX_ALT, Port74Save); + + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmEspi.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmEspi.c new file mode 100644 index 0000000000..9eb61947a3 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmEsp= i.c @@ -0,0 +1,1595 @@ +/** @file + eSPI SMI implementation + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmEspi.h" +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED ESPI_SMI_INSTANCE mEspiSmiInstance =3D { + // + // Signature + // + ESPI_SMI_INSTANCE_SIGNATURE, + // + // Handle + // + NULL, + // + // PchEspiSmiDispatchProtocol + // + { + PCH_ESPI_SMI_DISPATCH_REVISION, + EspiSmiUnRegister, + BiosWrProtectRegister, + BiosWrReportRegister, + PcNonFatalErrRegister, + PcFatalErrRegister, + VwNonFatalErrRegister, + VwFatalErrRegister, + FlashNonFatalErrRegister, + FlashFatalErrRegister, + LnkType1ErrRegister, + EspiSlaveSmiRegister + }, + // + // PchSmiEspiHandle[EspiTopLevelTypeMax] + // + { + NULL, NULL, NULL + }, + // + // CallbackDataBase[EspiSmiTypeMax] + // + { + {NULL, NULL}, {NULL, NULL}, {NULL, NULL}, {NULL, NULL}, {NULL, NULL}, + {NULL, NULL}, {NULL, NULL}, {NULL, NULL}, {NULL, NULL}, {NULL, NULL} + }, + // + // EspiSmiEventCounter[EspiSmiTypeMax] + // + { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 + }, + // + // Barrier[EspiTopLevelTypeMax] + // + { + { + BiosWrProtect, + BiosWrProtect + }, + { + BiosWrReport, + LnkType1Err + }, + { + EspiSlaveSmi, + EspiSlaveSmi + } + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST ESPI_DESCRIPTOR mEspiDescriptor[EspiSm= iTypeMax] =3D { + // + // BiosWrProtect + // + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_LPC << 19) | + (PCI_FUNCTION_NUMBER_PCH_LPC << 16) | + R_ESPI_CFG_PCBC + ) } + }, + // + // SourceIsActiveAndMask and SourceIsActiveValue + // + B_ESPI_CFG_PCBC_BWPDS | B_ESPI_CFG_PCBC_LE, + B_ESPI_CFG_PCBC_BWPDS | B_ESPI_CFG_PCBC_LE, + // + // ClearStatusAndMask and ClearStatusOrMask + // + (UINT32) ~B_ESPI_CFG_PCBC_BWRS, + B_ESPI_CFG_PCBC_BWPDS + }, + // + // BiosWrReport + // + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_LPC << 19) | + (PCI_FUNCTION_NUMBER_PCH_LPC << 16) | + R_ESPI_CFG_PCBC + ) } + }, + B_ESPI_CFG_PCBC_BWRS | B_ESPI_CFG_PCBC_BWRE, + B_ESPI_CFG_PCBC_BWRS | B_ESPI_CFG_PCBC_BWRE, + (UINT32) ~B_ESPI_CFG_PCBC_BWPDS, + B_ESPI_CFG_PCBC_BWRS + }, + // + // PcNonFatalErr + // + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ESPISPI, R_ESPI_PCR_PCERR_SLV0) } + }, + (B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XNFEE), + (B_ESPI_PCR_XERR_XNFES | (V_ESPI_PCR_XERR_XNFEE_SMI << N_ESPI_PCR_XERR= _XNFEE)), + (UINT32) ~(B_ESPI_PCR_PCERR_SLV0_PCURD | B_ESPI_PCR_XERR_XFES), + B_ESPI_PCR_XERR_XNFES + }, + // + // PcFatalErr + // + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ESPISPI, R_ESPI_PCR_PCERR_SLV0) } + }, + (B_ESPI_PCR_XERR_XFES | B_ESPI_PCR_XERR_XFEE), + (B_ESPI_PCR_XERR_XFES | (V_ESPI_PCR_XERR_XFEE_SMI << N_ESPI_PCR_XERR_X= FEE)), + (UINT32) ~(B_ESPI_PCR_PCERR_SLV0_PCURD | B_ESPI_PCR_XERR_XNFES), + B_ESPI_PCR_XERR_XFES + }, + // + // VwNonFatalErr + // + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ESPISPI, R_ESPI_PCR_VWERR_SLV0) } + }, + (B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XNFEE), + (B_ESPI_PCR_XERR_XNFES | (V_ESPI_PCR_XERR_XNFEE_SMI << N_ESPI_PCR_XERR= _XNFEE)), + (UINT32) ~B_ESPI_PCR_XERR_XFES, + B_ESPI_PCR_XERR_XNFES + }, + // + // VwFatalErr + // + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ESPISPI, R_ESPI_PCR_VWERR_SLV0) } + }, + (B_ESPI_PCR_XERR_XFES | B_ESPI_PCR_XERR_XFEE), + (B_ESPI_PCR_XERR_XFES | (V_ESPI_PCR_XERR_XFEE_SMI << N_ESPI_PCR_XERR_X= FEE)), + (UINT32) ~B_ESPI_PCR_XERR_XNFES, + B_ESPI_PCR_XERR_XFES + }, + // + // FlashNonFatalErr + // + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ESPISPI, R_ESPI_PCR_FCERR_SLV0) } + }, + (B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XNFEE), + (B_ESPI_PCR_XERR_XNFES | (V_ESPI_PCR_XERR_XNFEE_SMI << N_ESPI_PCR_XERR= _XNFEE)), + (UINT32) ~B_ESPI_PCR_XERR_XFES, + B_ESPI_PCR_XERR_XNFES + }, + // + // FlashFatalErr + // + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ESPISPI, R_ESPI_PCR_FCERR_SLV0) } + }, + (B_ESPI_PCR_XERR_XFES | B_ESPI_PCR_XERR_XFEE), + (B_ESPI_PCR_XERR_XFES | (V_ESPI_PCR_XERR_XFEE_SMI << N_ESPI_PCR_XERR_X= FEE)), + (UINT32) ~B_ESPI_PCR_XERR_XNFES, + B_ESPI_PCR_XERR_XFES + }, + // + // LnkType1Err + // + { + { + PCR_ADDR_TYPE, + {PCH_PCR_ADDRESS (PID_ESPISPI, R_ESPI_PCR_LNKERR_SLV0) } + }, + B_ESPI_PCR_LNKERR_SLV0_LFET1S | B_ESPI_PCR_LNKERR_SLV0_LFET1E, + B_ESPI_PCR_LNKERR_SLV0_LFET1S | (V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI << = N_ESPI_PCR_LNKERR_SLV0_LFET1E), + (UINT32) ~B_ESPI_PCR_LNKERR_SLV0_SLCRR, + B_ESPI_PCR_LNKERR_SLV0_LFET1S + }, +}; + +/** + Enable eSPI SMI source + + @param[in] EspiSmiType Type based on ESPI_SMI_TYPE +**/ +STATIC +VOID +EspiSmiEnableSource ( + IN CONST ESPI_SMI_TYPE EspiSmiType + ) +{ + UINT64 PciBaseAddress; + + switch (EspiSmiType) { + case BiosWrProtect: + // + // It doesn't enable the BIOSLOCK here. Enable it by policy in DXE. + // + break; + case BiosWrReport: + PciBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + PciSegmentAndThenOr32 ( + PciBaseAddress + R_ESPI_CFG_PCBC, + (UINT32) ~(B_ESPI_CFG_PCBC_BWRS | B_ESPI_CFG_PCBC_BWPDS), + B_ESPI_CFG_PCBC_BWRE + ); + break; + case PcNonFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_PCERR_SLV0, + (UINT32) ~(B_ESPI_PCR_PCERR_SLV0_PCURD | B_ESPI_PCR_XERR_XNFES | B= _ESPI_PCR_XERR_XFES), + B_ESPI_PCR_XERR_XNFEE + ); + break; + + case PcFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_PCERR_SLV0, + (UINT32) ~(B_ESPI_PCR_PCERR_SLV0_PCURD | B_ESPI_PCR_XERR_XNFES | B= _ESPI_PCR_XERR_XFES), + B_ESPI_PCR_XERR_XFEE + ); + break; + + case VwNonFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_VWERR_SLV0, + (UINT32) ~(B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES), + B_ESPI_PCR_XERR_XNFEE + ); + break; + + case VwFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_VWERR_SLV0, + (UINT32) ~(B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES), + B_ESPI_PCR_XERR_XFEE + ); + break; + + case FlashNonFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_FCERR_SLV0, + (UINT32) ~(B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES), + B_ESPI_PCR_XERR_XNFEE + ); + break; + + case FlashFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_FCERR_SLV0, + (UINT32) ~(B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES), + B_ESPI_PCR_XERR_XFEE + ); + break; + + case LnkType1Err: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_LNKERR_SLV0, + (UINT32) ~(B_ESPI_PCR_LNKERR_SLV0_SLCRR | B_ESPI_PCR_LNKERR_SLV0_L= FET1S), + (UINT32) (V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI << N_ESPI_PCR_LNKERR_S= LV0_LFET1E) + ); + + if (IsEspiSecondSlaveSupported ()) { + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_LNKERR_SLV1, + (UINT32) ~(B_ESPI_PCR_LNKERR_SLV0_SLCRR | B_ESPI_PCR_LNKERR_SLV0= _LFET1S), + (UINT32) (V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI << N_ESPI_PCR_LNKERR= _SLV0_LFET1E) + ); + } + break; + + default: + DEBUG ((DEBUG_ERROR, "Unsupported EspiSmiType \n")); + ASSERT (FALSE); + break; + } +} + + +/** + Disable eSPI SMI source + + @param[in] EspiSmiType Type based on ESPI_SMI_TYPE +**/ +STATIC +VOID +EspiSmiDisableSource ( + IN CONST ESPI_SMI_TYPE EspiSmiType + ) +{ + + switch (EspiSmiType) { + case BiosWrProtect: + case BiosWrReport: + DEBUG ((DEBUG_ERROR, "Bit is write lock, thus BWRE/BWPDS source cann= ot be disabled \n")); + ASSERT (FALSE); + break; + case PcNonFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_PCERR_SLV0, + (UINT32) ~(B_ESPI_PCR_PCERR_SLV0_PCURD | B_ESPI_PCR_XERR_XNFES | B= _ESPI_PCR_XERR_XFES | B_ESPI_PCR_XERR_XNFEE), + 0 + ); + break; + + case PcFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_PCERR_SLV0, + (UINT32) ~(B_ESPI_PCR_PCERR_SLV0_PCURD | B_ESPI_PCR_XERR_XNFES | B= _ESPI_PCR_XERR_XFES | B_ESPI_PCR_XERR_XFEE), + 0 + ); + break; + + case VwNonFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_VWERR_SLV0, + (UINT32) ~(B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES | B_ESPI_P= CR_XERR_XNFEE), + 0 + ); + break; + + case VwFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_VWERR_SLV0, + (UINT32) ~(B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES | B_ESPI_P= CR_XERR_XFEE), + 0 + ); + break; + + case FlashNonFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_FCERR_SLV0, + (UINT32) ~(B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES | B_ESPI_P= CR_XERR_XNFEE), + 0 + ); + break; + + case FlashFatalErr: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_FCERR_SLV0, + (UINT32) ~(B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES | B_ESPI_PC= R_XERR_XFEE), + 0 + ); + break; + + case LnkType1Err: + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_LNKERR_SLV0, + (UINT32) ~(B_ESPI_PCR_LNKERR_SLV0_SLCRR | B_ESPI_PCR_LNKERR_SLV0_L= FET1S), + 0 + ); + + if (IsEspiSecondSlaveSupported ()) { + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) R_ESPI_PCR_LNKERR_SLV1, + (UINT32) ~(B_ESPI_PCR_LNKERR_SLV0_SLCRR | B_ESPI_PCR_LNKERR_SLV0= _LFET1S), + 0 + ); + } + break; + + default: + DEBUG ((DEBUG_ERROR, "Unsupported EspiSmiType \n")); + ASSERT (FALSE); + break; + } +} + +/** + Clear a status for the SMI event + + @param[in] EspiSmiType Type based on ESPI_SMI_TYPE +**/ +STATIC +VOID +EspiSmiClearStatus ( + IN CONST ESPI_SMI_TYPE EspiSmiType + ) +{ + UINT32 PciBus; + UINT32 PciDev; + UINT32 PciFun; + UINT32 PciReg; + UINT64 PciBaseAddress; + CONST ESPI_DESCRIPTOR *Desc; + + Desc =3D &mEspiDescriptor[EspiSmiType]; + + switch (Desc->Address.Type) { + case PCIE_ADDR_TYPE: + PciBus =3D Desc->Address.Data.pcie.Fields.Bus; + PciDev =3D Desc->Address.Data.pcie.Fields.Dev; + PciFun =3D Desc->Address.Data.pcie.Fields.Fnc; + PciReg =3D Desc->Address.Data.pcie.Fields.Reg; + PciBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMB= ER_PCH, PciBus, PciDev, PciFun, 0); + PciSegmentAndThenOr32 (PciBaseAddress + PciReg, Desc->ClearStatusAnd= Mask, Desc->ClearStatusOrMask); + break; + case PCR_ADDR_TYPE: + PchPcrAndThenOr32 ( + Desc->Address.Data.Pcr.Fields.Pid, + Desc->Address.Data.Pcr.Fields.Offset, + Desc->ClearStatusAndMask, + Desc->ClearStatusOrMask + ); + break; + default: + DEBUG ((DEBUG_ERROR, "Address type for eSPI SMI is invalid \n")); + ASSERT (FALSE); + break; + } +} + +/** + Checks if a source is active by looking at the enable and status bits + + @param[in] EspiSmiType Type based on ESPI_SMI_TYPE +**/ +STATIC +BOOLEAN +EspiSmiSourceIsActive ( + IN CONST ESPI_SMI_TYPE EspiSmiType + ) +{ + BOOLEAN Active; + UINT32 PciBus; + UINT32 PciDev; + UINT32 PciFun; + UINT32 PciReg; + UINT64 PciBaseAddress; + UINT32 Data32; + CONST ESPI_DESCRIPTOR *Desc; + + Desc =3D &mEspiDescriptor[EspiSmiType]; + + Active =3D FALSE; + switch (Desc->Address.Type) { + case PCIE_ADDR_TYPE: + PciBus =3D Desc->Address.Data.pcie.Fields.Bus; + PciDev =3D Desc->Address.Data.pcie.Fields.Dev; + PciFun =3D Desc->Address.Data.pcie.Fields.Fnc; + PciReg =3D Desc->Address.Data.pcie.Fields.Reg; + PciBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMB= ER_PCH, PciBus, PciDev, PciFun, 0); + Data32 =3D PciSegmentRead32 (PciBaseAddress + PciReg); + break; + + case PCR_ADDR_TYPE: + Data32 =3D PchPcrRead32 ( + Desc->Address.Data.Pcr.Fields.Pid, + Desc->Address.Data.Pcr.Fields.Offset + ); + break; + + default: + Data32 =3D 0; + DEBUG ((DEBUG_ERROR, "Address type for eSPI SMI is invalid \n")); + ASSERT (FALSE); + break; + } + + if ((Data32 & Desc->SourceIsActiveAndMask) =3D=3D Desc->SourceIsActiveVa= lue) { + Active =3D TRUE; + } + + return Active; +} + +/** + Insert a handler into the corresponding linked list based on EspiSmiType + + @param[in] DispatchFunction The callback to execute + @param[in] EspiSmiType Type based on ESPI_SMI_TYPE to determi= ne which linked list to use + @param[out] DispatchHandle The link to the record in the database + + @retval EFI_SUCCESS Record was successfully inserted into = master database + @retval EFI_OUT_OF_RESOURCES Cannot allocate pool to insert record +**/ +STATIC +EFI_STATUS +InsertEspiRecord ( + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + IN ESPI_SMI_TYPE EspiSmiType, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + ESPI_SMI_RECORD *Record; + + Status =3D gSmst->SmmAllocatePool (EfiRuntimeServicesData, sizeof (ESPI_= SMI_RECORD), (VOID **) &Record); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + SetMem (Record, sizeof (ESPI_SMI_RECORD), 0); + + Record->Callback =3D DispatchFunction; + Record->Signature =3D ESPI_SMI_RECORD_SIGNATURE; + + InsertTailList (&mEspiSmiInstance.CallbackDataBase[EspiSmiType], &Record= ->Link); + EspiSmiClearStatus (EspiSmiType); + EspiSmiEnableSource (EspiSmiType); + + ++mEspiSmiInstance.EspiSmiEventCounter[EspiSmiType]; + + *DispatchHandle =3D (EFI_HANDLE) (&Record->Link); + + return EFI_SUCCESS; +} + +/** + This callback is registered to PchSmiDispatch + + @param[in] DispatchHandle Used to determine which source have been tri= ggered +**/ +VOID +EspiSmiCallback ( + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *PchSmiRecord; + ESPI_TOP_LEVEL_TYPE EspiTopLevelType; + ESPI_SMI_TYPE EspiSmiType; + ESPI_SMI_RECORD *RecordInDb; + LIST_ENTRY *LinkInDb; + + PchSmiRecord =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + + if (PchSmiRecord->PchSmiType =3D=3D PchTcoSmiLpcBiosWpType) { + EspiTopLevelType =3D EspiBiosWrProtect; + } else if (PchSmiRecord->PchSmiType =3D=3D PchSmiSerialIrqType) { + EspiTopLevelType =3D EspiSerialIrq; + } else { + DEBUG ((DEBUG_ERROR, "EspiSmiCallback was dispatched with a wrong Disp= atchHandle")); + ASSERT (FALSE); + return; + } + + for (EspiSmiType =3D mEspiSmiInstance.Barrier[EspiTopLevelType].Start; E= spiSmiType <=3D mEspiSmiInstance.Barrier[EspiTopLevelType].End; ++EspiSmiTy= pe) { + if (!EspiSmiSourceIsActive (EspiSmiType)) { + continue; + } + // + // The source is active, so walk the callback database and dispatch + // + if (!IsListEmpty (&mEspiSmiInstance.CallbackDataBase[EspiSmiType])) { + // + // We have children registered w/ us -- continue + // + LinkInDb =3D GetFirstNode (&mEspiSmiInstance.CallbackDataBase[EspiSm= iType]); + + while (!IsNull (&mEspiSmiInstance.CallbackDataBase[EspiSmiType], Lin= kInDb)) { + RecordInDb =3D ESPI_RECORD_FROM_LINK (LinkInDb); + + // + // RecordInDb->Link might be removed (unregistered) by Callback fu= nction, and then the + // system will hang in ASSERT() while calling GetNextNode(). + // To prevent the issue, we need to get next record in DB here (be= fore Callback function). + // + LinkInDb =3D GetNextNode (&mEspiSmiInstance.CallbackDataBase[EspiS= miType], &RecordInDb->Link); + + // + // Callback + // + if (RecordInDb->Callback !=3D NULL) { + RecordInDb->Callback ((EFI_HANDLE) &RecordInDb->Link); + } else { + ASSERT (FALSE); + } + } + } else if (EspiSmiType =3D=3D LnkType1Err) { + // + // If no proper handler registered for Link Type 1 Error + // Call default SMI handler recover otherwise + // + EspiDefaultFatalErrorHandler (); + } + + // + // Finish walking the linked list for the EspiSmiType, so clear status + // + EspiSmiClearStatus (EspiSmiType); + } +} + +// +// EspiBiosWp srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescEspiBiosWp= =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_TCO + }, + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_LPC << 19) | + (PCI_FUNCTION_NUMBER_PCH_LPC << 16) | + R_ESPI_CFG_PCBC + ) } + }, + S_ESPI_CFG_PCBC, + N_ESPI_CFG_PCBC_LE + } + }, + { + { + { + PCIE_ADDR_TYPE, + { ( + (DEFAULT_PCI_BUS_NUMBER_PCH << 24) | + (PCI_DEVICE_NUMBER_PCH_LPC << 19) | + (PCI_FUNCTION_NUMBER_PCH_LPC << 16) | + R_ESPI_CFG_PCBC + ) } + }, + S_ESPI_CFG_PCBC, + N_ESPI_CFG_PCBC_BWPDS + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_TCO + } +}; + +/** + This function will register EspiSmiCallback with mSrcDescEspiBiosWp sour= ce decriptor + This function make sure there is only one BIOS WP SMI handler is registe= red. + While any ESPI sub BIOS WP SMI type is registered, all the BIOS WP SMI + will go to callback function EspiSmiCallback first, and then dispatchs t= he callbacks + recorded in mEspiSmiInstance. + + @retval EFI_SUCCESS Registration succeed + @retval others Registration failed +**/ +STATIC +EFI_STATUS +RegisterBiosWrProtectIfNull ( + VOID + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *Record; + + if (mEspiSmiInstance.PchSmiEspiHandle[EspiBiosWrProtect] =3D=3D NULL) { + Status =3D PchSmiRecordInsert ( + &mSrcDescEspiBiosWp, + (PCH_SMI_CALLBACK_FUNCTIONS) EspiSmiCallback, + PchTcoSmiLpcBiosWpType, + &mEspiSmiInstance.PchSmiEspiHandle[EspiBiosWrProtect] + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to register BIOS WP SMI handler \n")); + return Status; + } + Record =3D DATABASE_RECORD_FROM_LINK (mEspiSmiInstance.PchSmiEspiHandl= e[EspiBiosWrProtect]); + Record->ClearSource =3D PchTcoSmiClearSource; + } + + return EFI_SUCCESS; +} + +/** + This function will register EspiSmiCallback with mSrcDescSerialIrq sourc= e decriptor + This function make sure there is only one Serial IRQ SMI handler is regi= stered. + While any ESPI sub Serial IRQ SMI type is registered, all the Serial IRQ= SMI + will go to callback function EspiSmiCallback first, and then dispatchs t= he callbacks + recorded in mEspiSmiInstance. + + @retval EFI_SUCCESS Registration succeed + @retval others Registration failed +**/ +STATIC +EFI_STATUS +RegisterSerialIrqIfNull ( + VOID + ) +{ + EFI_STATUS Status; + + if (mEspiSmiInstance.PchSmiEspiHandle[EspiSerialIrq] =3D=3D NULL) { + Status =3D PchSmiRecordInsert ( + &mSrcDescSerialIrq, + (PCH_SMI_CALLBACK_FUNCTIONS) EspiSmiCallback, + PchSmiSerialIrqType, + &mEspiSmiInstance.PchSmiEspiHandle[EspiSerialIrq] + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Fail to register Serial IRQ SMI handler \n")); + return Status; + } + } + + return EFI_SUCCESS; +} + +/** + Installs and initialize this protocol + + @param[in] ImageHandle Not used + + @retval EFI_SUCCESS Installation succeed + @retval others Installation failed +**/ +EFI_STATUS +EFIAPI +InstallEspiSmi ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + ESPI_SMI_TYPE EspiSmiType; + + DEBUG ((DEBUG_INFO, "[InstallEspiSmi] Enter\n")); + + // + // InitializeListHead for mEspiSmiInstance.CallBackDataBase[EspiTopLevel= TypeMax] + // + for (EspiSmiType =3D 0; EspiSmiType < EspiSmiTypeMax; ++EspiSmiType) { + InitializeListHead (&mEspiSmiInstance.CallbackDataBase[EspiSmiType]); + } + + // + // Install EfiEspiSmiDispatchProtocol + // + Status =3D gSmst->SmmInstallProtocolInterface ( + &mEspiSmiInstance.Handle, + &gPchEspiSmiDispatchProtocolGuid, + EFI_NATIVE_INTERFACE, + &mEspiSmiInstance.PchEspiSmiDispatchProtocol + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to install eSPI SMI Dispatch Protocol\n")= ); + ASSERT (FALSE); + return Status; + } + + // Register eSPI SMM callback to enable Fatal Error handling by default = handler + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + + // Enable LnkType1Err SMI generation for default handler + EspiSmiClearStatus (LnkType1Err); + EspiSmiEnableSource (LnkType1Err); + + return EFI_SUCCESS; +} + +/** + eSPI SMI Dispatch Protocol instance to register a BIOS Write Protect eve= nt + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +BiosWrProtectRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterBiosWrProtectIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, BiosWrProtect, DispatchHa= ndle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to register a BIOS Write Report event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +BiosWrReportRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, BiosWrReport, DispatchHan= dle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to register a Peripheral Channel Non= Fatal Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +PcNonFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, PcNonFatalErr, DispatchHa= ndle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to register a Peripheral Channel Fat= al Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +PcFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, PcFatalErr, DispatchHandl= e); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to register a Virtual Wire Non Fatal= Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +VwNonFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, VwNonFatalErr, DispatchHa= ndle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to register a Virtual Wire Fatal Err= or event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +VwFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, VwFatalErr, DispatchHandl= e); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to register a Flash Channel Non Fata= l Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +FlashNonFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, FlashNonFatalErr, Dispatc= hHandle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to register a Flash Channel Fatal Er= ror event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +FlashFatalErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, FlashFatalErr, DispatchHa= ndle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to register a Link Error event + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback registration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock= event has been triggered + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +LnkType1ErrRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D RegisterSerialIrqIfNull (); + if (EFI_ERROR (Status)) { + return Status; + } + // + // Insert a record + // + Status =3D InsertEspiRecord (DispatchFunction, LnkType1Err, DispatchHand= le); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + return Status; +} + +// +// EspiSlave srcdesc +// +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSrcDescEspiSlave = =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_ESPI + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_ESPI + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_ESPI + } +}; + +/** + eSPI SMI Dispatch Protocol instance to register a eSPI slave SMI + This routine will also lock down ESPI_SMI_LOCK bit after registration an= d prevent + this handler from unregistration. + On platform that supports more than 1 device through another chip select= (SPT-H), + the SMI handler itself needs to inspect both the eSPI devices' interrupt= status registers + (implementation specific for each Slave) in order to identify and servic= e the cause. + After servicing it, it has to clear the Slaves' internal SMI# status reg= isters + + @param[in] This Not used + @param[in] DispatchFunction The callback to execute + @param[out] DispatchHandle The handle for this callback regis= tration + + @retval EFI_SUCCESS Registration succeed + @retval EFI_ACCESS_DENIED Return access denied if the SmmRea= dyToLock event has been triggered + @retval EFI_ACCESS_DENIED The ESPI_SMI_LOCK is set and regis= ter is blocked. + @retval others Registration failed +**/ +EFI_STATUS +EFIAPI +EspiSlaveSmiRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + // + // If ESPI_SMI_LOCK is set, the register is blocked. + // + if (PmcIsEspiSmiLockSet ()) { + return EFI_ACCESS_DENIED; + } + + // + // @note: This service doesn't utilize the data base of mEspiSmiInstance. + // While SMI is triggered it directly goes to the registing Dispa= tchFunction + // instead of EspiSmiCallback. + // + Status =3D PchSmiRecordInsert ( + &mSrcDescEspiSlave, + (PCH_SMI_CALLBACK_FUNCTIONS) DispatchFunction, + PchEspiSmiEspiSlaveType, + DispatchHandle + ); + PchSmmClearSource (&mSrcDescEspiSlave); + PchSmmEnableSource (&mSrcDescEspiSlave); + + // + // Lock down the ESPI_SMI_LOCK after ESPI SMI is enabled. + // + PmcLockEspiSmi (); + // + // Keep the DispatchHandle which will be used for unregister function. + // + mEspiSmiInstance.PchSmiEspiHandle[EspiPmc] =3D *DispatchHandle; + + if (!EFI_ERROR (Status)) { + SmiHandlerProfileRegisterHandler (&gPchEspiSmiDispatchProtocolGuid, (E= FI_SMM_HANDLER_ENTRY_POINT2)DispatchFunction, (UINTN)RETURN_ADDRESS (0), NU= LL, 0); + } + + return Status; +} + +/** + eSPI SMI Dispatch Protocol instance to unregister a callback based on ha= ndle + + @param[in] This Not used + @param[in] DispatchHandle Handle acquired during registration + + @retval EFI_SUCCESS Unregister successful + @retval EFI_INVALID_PARAMETER DispatchHandle is null + @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has ba= d pointer + @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in dat= abase + @retval EFI_ACCESS_DENIED Unregistration is done after end of = DXE + @retval EFI_ACCESS_DENIED DispatchHandle is not allowed to unr= egistered +**/ +EFI_STATUS +EFIAPI +EspiSmiUnRegister ( + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + EFI_STATUS Status; + ESPI_TOP_LEVEL_TYPE EspiTopLevelType; + ESPI_SMI_TYPE EspiSmiType; + BOOLEAN SafeToDisable; + LIST_ENTRY *LinkInDb; + ESPI_SMI_RECORD *RecordPointer; + DATABASE_RECORD *RecordToDelete; + + if (DispatchHandle =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "UnRegister is not allowed if the SmmReadyToLock = event has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + if (((LIST_ENTRY *) DispatchHandle)->ForwardLink =3D=3D (LIST_ENTRY *) E= FI_BAD_POINTER) { + return EFI_INVALID_PARAMETER; + } + + // + // For DispatchHandle belongs to Espi Slave SMI, refuses the request of = unregistration. + // + if (mEspiSmiInstance.PchSmiEspiHandle[EspiPmc] =3D=3D DispatchHandle) { + DEBUG ((DEBUG_ERROR, "UnRegister is not allowed for ESPI Slave SMI han= dle! \n")); + return EFI_ACCESS_DENIED; + } + + // + // Iterate through all the database to find the record + // + for (EspiSmiType =3D 0; EspiSmiType < EspiSmiTypeMax; ++EspiSmiType) { + LinkInDb =3D GetFirstNode (&mEspiSmiInstance.CallbackDataBase[EspiSmiT= ype]); + + while (!IsNull (&mEspiSmiInstance.CallbackDataBase[EspiSmiType], LinkI= nDb)) { + if (LinkInDb !=3D (LIST_ENTRY *) DispatchHandle) { + LinkInDb =3D GetNextNode (&mEspiSmiInstance.CallbackDataBase[EspiS= miType], LinkInDb); + + } else { + // + // Found the source to be from this list + // + RemoveEntryList (LinkInDb); + RecordPointer =3D (ESPI_RECORD_FROM_LINK (LinkInDb)); + + if (mEspiSmiInstance.EspiSmiEventCounter[EspiSmiType] !=3D 0) { + if (--mEspiSmiInstance.EspiSmiEventCounter[EspiSmiType] =3D=3D 0= ) { + EspiSmiDisableSource (EspiSmiType); + } + } + + Status =3D gSmst->SmmFreePool (RecordPointer); + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + } + + goto EspiSmiUnRegisterEnd; + } + } + } + // + // If the code reach here, the handle passed in cannot be found + // + DEBUG ((DEBUG_ERROR, "eSPI SMI handle is not in record database \n")); + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + +EspiSmiUnRegisterEnd: + + // + // Unregister and clear the handle from PchSmiDispatch + // + for (EspiTopLevelType =3D 0; EspiTopLevelType < EspiTopLevelTypeMax; ++E= spiTopLevelType) { + SafeToDisable =3D TRUE; + // + // Checks all the child events that belongs to a top level status in P= MC + // + for (EspiSmiType =3D mEspiSmiInstance.Barrier[EspiTopLevelType].Start;= EspiSmiType <=3D mEspiSmiInstance.Barrier[EspiTopLevelType].End; ++EspiSmi= Type) { + if (mEspiSmiInstance.EspiSmiEventCounter[EspiSmiType] !=3D 0) { + SafeToDisable =3D FALSE; + } + } + // + // Finally, disable the top level event in PMC + // + if (SafeToDisable) { + if (mEspiSmiInstance.PchSmiEspiHandle[EspiTopLevelType] !=3D NULL) { + Status =3D PchSmmCoreUnRegister (NULL, mEspiSmiInstance.PchSmiEspi= Handle[EspiTopLevelType]); + ASSERT_EFI_ERROR (Status); + mEspiSmiInstance.PchSmiEspiHandle[EspiTopLevelType] =3D NULL; + } + } + } + RecordToDelete =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + if (!EFI_ERROR (Status)) { + SmiHandlerProfileUnregisterHandler (&gPchEspiSmiDispatchProtocolGuid, = RecordToDelete->Callback, NULL, 0); + } + return EFI_SUCCESS; +} + +/** + Returns AND maks for clearing eSPI channel registers errors statuses + In addition to common status bit we add channel specific erro bits to av= oid clearing them + + @param[in] ChannelNumber Channel number (0 for PC, 1 for VW, = 2 for OOB, 3 for FA) + + @retval UINT32 AND mask with all the status bit mas= ked to not clear them by mistake +**/ +UINT32 +GetEspiChannelStatusClearMask ( + UINT8 ChannelNumber + ) +{ + UINT32 Data32; + + // Common error status bits for all channel registers + Data32 =3D B_ESPI_PCR_XERR_XNFES | B_ESPI_PCR_XERR_XFES; + + // Check channels for channel specific status bits + switch(ChannelNumber) { + case 0: // Peripheral Channel specific status bits + Data32 |=3D B_ESPI_PCR_PCERR_PCURD; + break; + case 3: // Flash Access Channel specific status bits + Data32 |=3D B_ESPI_PCR_FCERR_SAFBLK; + break; + default: + break; + } + + // Return the expected AND mask + return (UINT32)~(Data32); +} + +/** + Checks if channel error register data has Fatal Error bit set + If yes then reset the channel on slave + + @param[in] ChannelBaseAddress Base address + @param[in] ChannelNumber Channel number (0 for PC, 1 for VW, = 2 for OOB, 3 for FA) + @param[in] SlaveId Slave ID of which channel is to be r= eset +**/ +VOID +CheckSlaveChannelErrorAndReset ( + UINT16 ChannelBaseAddress, + UINT8 ChannelNumber, + UINT8 SlaveId + ) +{ + UINT32 Data32; + UINT16 ChannelAddress; + EFI_STATUS Status; + + if (ChannelNumber =3D=3D 2) { + DEBUG ((DEBUG_INFO, "Channel %d is not supported by this function due = to lack of error register\n", ChannelNumber)); + return; + } + + if (!IsEspiSlaveChannelSupported (SlaveId, ChannelNumber)) { + DEBUG ((DEBUG_WARN, "Channel %d is not supported by slave device\n", C= hannelNumber)); + return; + } + + // Calculate channel address based on slave id + ChannelAddress =3D (UINT16) (ChannelBaseAddress + (SlaveId * S_ESPI_PCR_= XERR)); + + // Reading channel error register data + Data32 =3D PchPcrRead32 (PID_ESPISPI, ChannelAddress); + + DEBUG ((DEBUG_INFO, "eSPI channel error register (0x%4X) has value 0x%8X= \n", ChannelAddress, Data32)); + + // Check Fatal Error status bit in channel error register data + if ((Data32 & B_ESPI_PCR_XERR_XFES) !=3D 0) { + Status =3D PchEspiSlaveChannelReset (SlaveId, ChannelNumber); + + if (EFI_ERROR (Status)) { + switch (Status) { + case EFI_UNSUPPORTED: + DEBUG ((DEBUG_ERROR, "Slave doesn't support channel %d\n", Chann= elNumber)); + break; + case EFI_TIMEOUT: + DEBUG ((DEBUG_ERROR, "Timeout occured during channel %d reset on= slave %d\n", ChannelNumber, SlaveId)); + break; + default: + DEBUG ((DEBUG_ERROR, "Error occured during channel %d reset\n", = ChannelNumber)); + break; + } + } else { + DEBUG ((DEBUG_INFO, "eSPI Slave %d channel %d reset ended successful= ly\n", SlaveId, ChannelNumber)); + // If channel reset was successfull clear the fatal error flag by wr= iting one + // we should be aware not to clear other status bits by mistake and = mask them + PchPcrAndThenOr32 ( + PID_ESPISPI, + ChannelAddress, + GetEspiChannelStatusClearMask (ChannelNumber), + B_ESPI_PCR_XERR_XFES + ); + } + } +} + +/** + eSPI SMI handler for Fatal Error recovery flow +**/ +VOID +EspiDefaultFatalErrorHandler ( + VOID + ) +{ + UINT32 Data32; + UINT8 SlaveId; + UINT8 MaxSlavesCount; + + DEBUG ((DEBUG_INFO, "[EspiRecoverFromFatalError] Enter\n")); + + MaxSlavesCount =3D IsEspiSecondSlaveSupported () ? 2 : 1; + + DEBUG ((DEBUG_INFO, "[EspiRecoverFromFatalError] MaxSlavesCount %d\n", M= axSlavesCount)); + + for (SlaveId =3D 0; SlaveId < MaxSlavesCount; ++SlaveId) { + // + // Check if slave has SLCRR bit set. If it does it means it needs reco= very. + // + Data32 =3D PchPcrRead32 (PID_ESPISPI, (UINT16) (R_ESPI_PCR_LNKERR_SLV0= + (SlaveId * S_ESPI_PCR_XERR))); + + DEBUG ((DEBUG_INFO, "[EspiRecoverFromFatalError] Slave %d LNKERR reg 0= x%8X\n", SlaveId, Data32)); + // + // If SLCRR[31] bit is set we need to recover that slave + // + if ((Data32 & B_ESPI_PCR_LNKERR_SLV0_SLCRR) !=3D 0) { + // 1. Perform in-band reset + PchEspiSlaveInBandReset (SlaveId); + + // 2. Channels reset + CheckSlaveChannelErrorAndReset (R_ESPI_PCR_PCERR_SLV0, 0, SlaveId); = // Peripheral channel reset + CheckSlaveChannelErrorAndReset (R_ESPI_PCR_VWERR_SLV0, 1, SlaveId); = // Virtual Wire channel reset + + // Flash Access channel is not supported for CS1# + if (SlaveId =3D=3D 0) { + CheckSlaveChannelErrorAndReset (R_ESPI_PCR_PCERR_SLV0, 3, SlaveId)= ; // Flash Access channel reset + } + + // Clear SLCRR bit of slave after all channels recovery was done + PchPcrAndThenOr32 ( + PID_ESPISPI, + (UINT16) (R_ESPI_PCR_LNKERR_SLV0 + (SlaveId * S_ESPI_PCR_XERR)), + (UINT32)~(B_ESPI_PCR_LNKERR_SLV0_LFET1S), + (UINT32) (B_ESPI_PCR_LNKERR_SLV0_SLCRR) + ); + } + } + + DEBUG ((DEBUG_INFO, "[EspiRecoverFromFatalError] Exit\n")); +} + + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmGpi.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pch= SmmGpi.c new file mode 100644 index 0000000000..43277f0938 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmGpi= .c @@ -0,0 +1,254 @@ +/** @file + File to contain all the hardware specific stuff for the Smm Gpi dispatch= protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmm.h" +#include "PchSmmHelpers.h" +#include +#include +#include + +// +// Structure for GPI SMI is a template which needs to have +// GPI Smi bit offset and Smi Status & Enable registers updated (according= ly +// to choosen group and pad number) after adding it to SMM Callback databa= se +// + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mPchGpiSourceDescT= emplate =3D { + PCH_SMM_NO_FLAGS, + { + NULL_BIT_DESC_INITIALIZER, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + GPIO_ADDR_TYPE, {0x0} + }, + S_GPIO_PCR_GP_SMI_STS, 0x0, + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_GPIO_SMI + } +}; + +/** + The register function used to register SMI handler of GPI SMI event. + + @param[in] This Pointer to the EFI_SMM_GPI_DISPATCH2_PROT= OCOL instance. + @param[in] DispatchFunction Function to register for handler when the= specified GPI causes an SMI. + @param[in] RegisterContext Pointer to the dispatch function's contex= t. + The caller fills this context in before c= alling + the register function to indicate to the = register + function the GPI(s) for which the dispatc= h function + should be invoked. + @param[out] DispatchHandle Handle generated by the dispatcher to tra= ck the + function instance. + + @retval EFI_SUCCESS The dispatch function has been successful= ly + registered and the SMI source has been en= abled. + @retval EFI_ACCESS_DENIED Register is not allowed + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The GPI input= value + is not within valid range. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or SMM= ) to manage this child. +**/ +EFI_STATUS +EFIAPI +PchGpiSmiRegister ( + IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN CONST EFI_SMM_GPI_REGISTER_CONTEXT *RegisterContext, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD Record; + GPIO_PAD GpioPad; + UINT8 GpiSmiBitOffset; + UINT32 GpiHostSwOwnRegAddress; + UINT32 GpiSmiStsRegAddress; + UINT32 Data32Or; + UINT32 Data32And; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the EndOfDxe event ha= s been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + Status =3D GpioGetPadAndSmiRegs ( + (UINT32) RegisterContext->GpiNum, + &GpioPad, + &GpiSmiBitOffset, + &GpiHostSwOwnRegAddress, + &GpiSmiStsRegAddress + ); + + if (EFI_ERROR (Status)) { + return Status; + } + + ZeroMem (&Record, sizeof (DATABASE_RECORD)); + + // + // Gather information about the registration request + // + Record.Callback =3D DispatchFunction; + Record.ChildContext.Gpi =3D *RegisterContext; + Record.ProtocolType =3D GpiType; + Record.Signature =3D DATABASE_RECORD_SIGNATURE; + + CopyMem (&Record.SrcDesc, &mPchGpiSourceDescTemplate, sizeof (PCH_SMM_SO= URCE_DESC) ); + + Record.SrcDesc.Sts[0].Reg.Data.raw =3D GpiSmiStsRegAddress; // GPI SMI = Status register + Record.SrcDesc.Sts[0].Bit =3D GpiSmiBitOffset; // Bit posi= tion for selected pad + + // + // Insert GpiSmi handler to PchSmmCore database + // + *DispatchHandle =3D NULL; + + Status =3D SmmCoreInsertRecord ( + &Record, + DispatchHandle + ); + ASSERT_EFI_ERROR (Status); + + SmiHandlerProfileRegisterHandler (&gEfiSmmGpiDispatch2ProtocolGuid, (EFI= _SMM_HANDLER_ENTRY_POINT2) DispatchFunction, (UINTN)RETURN_ADDRESS (0), (vo= id *)RegisterContext, sizeof(*RegisterContext)); + + // + // Enable GPI SMI + // HOSTSW_OWN with respect to generating GPI SMI has negative logic: + // - 0 (ACPI mode) - GPIO pad will be capable of generating SMI/NMI/SCI + // - 1 (GPIO mode) - GPIO pad will not generate SMI/NMI/SCI + // + Data32And =3D (UINT32)~(1u << GpiSmiBitOffset); + MmioAnd32 (GpiHostSwOwnRegAddress, Data32And); + + // + // Add HOSTSW_OWN programming into S3 boot script + // + Data32Or =3D 0; + S3BootScriptSaveMemReadWrite (S3BootScriptWidthUint32, GpiHostSwOwnRegAd= dress, &Data32Or, &Data32And); + + return EFI_SUCCESS; +} + +/** + Unregister a GPI SMI source dispatch function with a parent SMM driver + + @param[in] This Pointer to the EFI_SMM_GPI_DISPATCH2_PRO= TOCOL instance. + @param[in] DispatchHandle Handle of dispatch function to deregiste= r. + + @retval EFI_SUCCESS The dispatch function has been successfu= lly + unregistered and the SMI source has been= disabled + if there are no other registered child d= ispatch + functions for this SMI source. + @retval EFI_INVALID_PARAMETER Handle is invalid. +**/ +EFI_STATUS +EFIAPI +PchGpiSmiUnRegister ( + IN CONST EFI_SMM_GPI_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + EFI_STATUS Status; + DATABASE_RECORD *RecordToDelete; + DATABASE_RECORD *RecordInDb; + LIST_ENTRY *LinkInDb; + GPIO_PAD GpioPad; + UINT8 GpiSmiBitOffset; + UINT32 GpiHostSwOwnRegAddress; + UINT32 GpiSmiStsRegAddress; + UINT32 Data32Or; + UINT32 Data32And; + BOOLEAN DisableGpiSmiSource; + + + if (DispatchHandle =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + RecordToDelete =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + if ((RecordToDelete->Signature !=3D DATABASE_RECORD_SIGNATURE) || + (RecordToDelete->ProtocolType !=3D GpiType)) { + return EFI_INVALID_PARAMETER; + } + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "UnRegister is not allowed if the SmmReadyToLock = event has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + DisableGpiSmiSource =3D TRUE; + // + // Loop through all sources in record linked list to see if any other GP= I SMI + // is installed on the same pin. If no then disable GPI SMI capability o= n this pad + // + LinkInDb =3D GetFirstNode (&mPrivateData.CallbackDataBase); + while (!IsNull (&mPrivateData.CallbackDataBase, LinkInDb)) { + RecordInDb =3D DATABASE_RECORD_FROM_LINK (LinkInDb); + LinkInDb =3D GetNextNode (&mPrivateData.CallbackDataBase, &RecordInDb-= >Link); + // + // If this is the record to delete skip it + // + if (RecordInDb =3D=3D RecordToDelete) { + continue; + } + // + // Check if record is GPI SMI type + // + if (RecordInDb->ProtocolType =3D=3D GpiType) { + // + // Check if same GPIO pad is the source of this SMI + // + if (RecordInDb->ChildContext.Gpi.GpiNum =3D=3D RecordToDelete->Child= Context.Gpi.GpiNum) { + DisableGpiSmiSource =3D FALSE; + break; + } + } + } + + if (DisableGpiSmiSource) { + GpioGetPadAndSmiRegs ( + (UINT32) RecordToDelete->ChildContext.Gpi.GpiNum, + &GpioPad, + &GpiSmiBitOffset, + &GpiHostSwOwnRegAddress, + &GpiSmiStsRegAddress + ); + + Data32Or =3D 1u << GpiSmiBitOffset; + Data32And =3D 0xFFFFFFFF; + MmioOr32 (GpiHostSwOwnRegAddress, Data32Or); + S3BootScriptSaveMemReadWrite (S3BootScriptWidthUint32, GpiHostSwOwnReg= Address, &Data32Or, &Data32And); + } + + + RemoveEntryList (&RecordToDelete->Link); + ZeroMem (RecordToDelete, sizeof (DATABASE_RECORD)); + Status =3D gSmst->SmmFreePool (RecordToDelete); + + if (EFI_ERROR (Status)) { + ASSERT (FALSE); + return Status; + } + SmiHandlerProfileUnregisterHandler (&gEfiSmmGpiDispatch2ProtocolGuid, Re= cordToDelete->Callback, NULL, 0); + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmHelpers.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm= /PchSmmHelpers.c new file mode 100644 index 0000000000..f6413921eb --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmHel= pers.c @@ -0,0 +1,358 @@ +/** @file + Helper functions for PCH SMM dispatcher. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmHelpers.h" +#include +#include +#include +#include + +/// +/// #define BIT_ZERO 0x00000001 +/// +GLOBAL_REMOVE_IF_UNREFERENCED CONST UINT32 BIT_ZERO =3D 0x00000001; + +/// +/// SUPPORT / HELPER FUNCTIONS (PCH version-independent) +/// + +/** + Compare 2 SMM source descriptors' enable settings. + + @param[in] Src1 Pointer to the PCH SMI source descriptio= n table 1 + @param[in] Src2 Pointer to the PCH SMI source descriptio= n table 2 + + @retval TRUE The enable settings of the 2 SMM source = descriptors are identical. + @retval FALSE The enable settings of the 2 SMM source = descriptors are not identical. +**/ +BOOLEAN +CompareEnables ( + CONST IN PCH_SMM_SOURCE_DESC *Src1, + CONST IN PCH_SMM_SOURCE_DESC *Src2 + ) +{ + BOOLEAN IsEqual; + UINTN DescIndex; + + IsEqual =3D TRUE; + for (DescIndex =3D 0; DescIndex < NUM_EN_BITS; DescIndex++) { + /// + /// It's okay to compare a NULL bit description to a non-NULL bit desc= ription. + /// They are unequal and these tests will generate the correct result. + /// + if (Src1->En[DescIndex].Bit !=3D Src2->En[DescIndex].Bit || + Src1->En[DescIndex].Reg.Type !=3D Src2->En[DescIndex].Reg.Type || + Src1->En[DescIndex].Reg.Data.raw !=3D Src2->En[DescIndex].Reg.Data= .raw + ) { + IsEqual =3D FALSE; + break; + /// + /// out of for loop + /// + } + } + + return IsEqual; +} + +/** + Compare a bit descriptor to the enables of source descriptor. Includes n= ull address type. + + @param[in] BitDesc Pointer to the PCH SMI bit descriptor + @param[in] Src Pointer to the PCH SMI source descriptio= n table 2 + + @retval TRUE The bit desc is equal to any of the enab= les in source descriptor + @retval FALSE The bid desc is not equal to all of the = enables in source descriptor +**/ +BOOLEAN +IsBitEqualToAnySourceEn ( + CONST IN PCH_SMM_BIT_DESC *BitDesc, + CONST IN PCH_SMM_SOURCE_DESC *Src + ) +{ + BOOLEAN IsEqual; + UINTN DescIndex; + + IsEqual =3D FALSE; + + for (DescIndex =3D 0; DescIndex < NUM_EN_BITS; ++DescIndex) { + if ((BitDesc->Reg.Type =3D=3D Src->En[DescIndex].Reg.Type) && + (BitDesc->Reg.Data.raw =3D=3D Src->En[DescIndex].Reg.Data.raw) && + (BitDesc->Bit =3D=3D Src->En[DescIndex].Bit)) { + IsEqual =3D TRUE; + break; + } + } + return IsEqual; +} + +/** + Compare 2 SMM source descriptors' statuses. + + @param[in] Src1 Pointer to the PCH SMI source descriptio= n table 1 + @param[in] Src2 Pointer to the PCH SMI source descriptio= n table 2 + + @retval TRUE The statuses of the 2 SMM source descrip= tors are identical. + @retval FALSE The statuses of the 2 SMM source descrip= tors are not identical. +**/ +BOOLEAN +CompareStatuses ( + CONST IN PCH_SMM_SOURCE_DESC *Src1, + CONST IN PCH_SMM_SOURCE_DESC *Src2 + ) +{ + BOOLEAN IsEqual; + UINTN DescIndex; + + IsEqual =3D TRUE; + + for (DescIndex =3D 0; DescIndex < NUM_STS_BITS; DescIndex++) { + /// + /// It's okay to compare a NULL bit description to a non-NULL bit desc= ription. + /// They are unequal and these tests will generate the correct result. + /// + if (Src1->Sts[DescIndex].Bit !=3D Src2->Sts[DescIndex].Bit || + Src1->Sts[DescIndex].Reg.Type !=3D Src2->Sts[DescIndex].Reg.Type || + Src1->Sts[DescIndex].Reg.Data.raw !=3D Src2->Sts[DescIndex].Reg.Da= ta.raw + ) { + IsEqual =3D FALSE; + break; + /// + /// out of for loop + /// + } + } + + return IsEqual; +} + +/** + Compare 2 SMM source descriptors, based on Enable settings and Status se= ttings of them. + + @param[in] Src1 Pointer to the PCH SMI source descriptio= n table 1 + @param[in] Src2 Pointer to the PCH SMI source descriptio= n table 2 + + @retval TRUE The 2 SMM source descriptors are identic= al. + @retval FALSE The 2 SMM source descriptors are not ide= ntical. +**/ +BOOLEAN +CompareSources ( + CONST IN PCH_SMM_SOURCE_DESC *Src1, + CONST IN PCH_SMM_SOURCE_DESC *Src2 + ) +{ + return (BOOLEAN) (CompareEnables (Src1, Src2) && CompareStatuses (Src1, = Src2)); +} + +/** + Check if an SMM source is active. + + @param[in] Src Pointer to the PCH SMI source descriptio= n table + @param[in] SciEn Indicate if SCI is enabled or not + @param[in] SmiEnValue Value from R_ACPI_IO_SMI_EN + @param[in] SmiStsValue Value from R_ACPI_IO_SMI_STS + + @retval TRUE It is active. + @retval FALSE It is inactive. +**/ +BOOLEAN +SourceIsActive ( + CONST IN PCH_SMM_SOURCE_DESC *Src, + CONST IN BOOLEAN SciEn, + CONST IN UINT32 SmiEnValue, + CONST IN UINT32 SmiStsValue + ) +{ + UINTN DescIndex; + + /// + /// This source is dependent on SciEn, and SciEn =3D=3D 1. An ACPI OS i= s present, + /// so we shouldn't do anything w/ this source until SciEn =3D=3D 0. + /// + if ((Src->Flags =3D=3D PCH_SMM_SCI_EN_DEPENDENT) && (SciEn)) { + return FALSE; + } + + /// + /// Checking top level SMI status. If the status is not active, return f= alse immediately + /// + if (!IS_BIT_DESC_NULL (Src->PmcSmiSts)) { + if ((Src->PmcSmiSts.Reg.Type =3D=3D ACPI_ADDR_TYPE) && + (Src->PmcSmiSts.Reg.Data.acpi =3D=3D R_ACPI_IO_SMI_STS) && + ((SmiStsValue & (1u << Src->PmcSmiSts.Bit)) =3D=3D 0)) { + return FALSE; + } + } + + // + // Special handling for NMI bit since it requires PMC IPC command. + // Do w/a here instead of in ReadBitDesc to reduce the PMC IPC command u= sage. + // + // The PCR[ITSS].NMI register can only be accessed with BOOT_SAI and SMM= _SAI. + // Since in CFL there is no SMM_SAI it needs PMC assistance to access th= is register. + // + if ((Src->En[0].Reg.Data.Pcr.Fields.Pid =3D=3D PID_ITSS) && + (Src->En[0].Reg.Data.Pcr.Fields.Offset =3D=3D R_ITSS_PCR_NMI)) + { + UINT32 ItssNmi; + ItssNmi =3D PmcGetNmiControl (); + if ((ItssNmi & (BIT0 << Src->En[0].Bit)) && + (ItssNmi & (BIT0 << Src->Sts[0].Bit))) + { + return TRUE; + } else { + return FALSE; + } + } + + /// + /// Read each bit desc from hardware and make sure it's a one + /// + for (DescIndex =3D 0; DescIndex < NUM_EN_BITS; DescIndex++) { + if (!IS_BIT_DESC_NULL (Src->En[DescIndex])) { + if ((Src->En[DescIndex].Reg.Type =3D=3D ACPI_ADDR_TYPE) && + (Src->En[DescIndex].Reg.Data.acpi =3D=3D R_ACPI_IO_SMI_EN) && + ((SmiEnValue & (1u << Src->En[DescIndex].Bit)) =3D=3D 0)) { + return FALSE; + } else if (ReadBitDesc (&Src->En[DescIndex]) =3D=3D 0) { + return FALSE; + } + } + } + + /// + /// Read each bit desc from hardware and make sure it's a one + /// + for (DescIndex =3D 0; DescIndex < NUM_STS_BITS; DescIndex++) { + if (!IS_BIT_DESC_NULL (Src->Sts[DescIndex])) { + if ((Src->Sts[DescIndex].Reg.Type =3D=3D ACPI_ADDR_TYPE) && + (Src->Sts[DescIndex].Reg.Data.acpi =3D=3D R_ACPI_IO_SMI_STS) && + ((SmiStsValue & (1u << Src->Sts[DescIndex].Bit)) =3D=3D 0)) { + return FALSE; + } else if (ReadBitDesc (&Src->Sts[DescIndex]) =3D=3D 0) { + return FALSE; + } + } + } + + return TRUE; +} + +/** + Enable the SMI source event by set the SMI enable bit, this function wou= ld also clear SMI + status bit to make initial state is correct + + @param[in] SrcDesc Pointer to the PCH SMI source descriptio= n table + +**/ +VOID +PchSmmEnableSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + UINTN DescIndex; + + /// + /// Set enables to 1 by writing a 1 + /// + for (DescIndex =3D 0; DescIndex < NUM_EN_BITS; DescIndex++) { + if (!IS_BIT_DESC_NULL (SrcDesc->En[DescIndex])) { + WriteBitDesc (&SrcDesc->En[DescIndex], 1, FALSE); + } + } + /// + /// Clear statuses to 0 by writing a 1 + /// + for (DescIndex =3D 0; DescIndex < NUM_STS_BITS; DescIndex++) { + if (!IS_BIT_DESC_NULL (SrcDesc->Sts[DescIndex])) { + WriteBitDesc (&SrcDesc->Sts[DescIndex], 1, TRUE); + } + } +} + +/** + Disable the SMI source event by clear the SMI enable bit + + @param[in] SrcDesc Pointer to the PCH SMI source descriptio= n table + +**/ +VOID +PchSmmDisableSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + UINTN DescIndex; + + for (DescIndex =3D 0; DescIndex < NUM_EN_BITS; DescIndex++) { + if (!IS_BIT_DESC_NULL (SrcDesc->En[DescIndex])) { + WriteBitDesc (&SrcDesc->En[DescIndex], 0, FALSE); + } + } +} + +/** + Clear the SMI status bit by set the source bit of SMI status register + + @param[in] SrcDesc Pointer to the PCH SMI source descriptio= n table + +**/ +VOID +PchSmmClearSource ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + UINTN DescIndex; + + for (DescIndex =3D 0; DescIndex < NUM_STS_BITS; DescIndex++) { + if (!IS_BIT_DESC_NULL (SrcDesc->Sts[DescIndex])) { + WriteBitDesc (&SrcDesc->Sts[DescIndex], 1, TRUE); + } + } +} + +/** + Sets the source to a 1 and then waits for it to clear. + Be very careful when calling this function -- it will not + ASSERT. An acceptable case to call the function is when + waiting for the NEWCENTURY_STS bit to clear (which takes + 3 RTCCLKs). + + @param[in] SrcDesc Pointer to the PCH SMI source descriptio= n table + +**/ +VOID +PchSmmClearSourceAndBlock ( + CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + UINTN DescIndex; + BOOLEAN IsSet; + + for (DescIndex =3D 0; DescIndex < NUM_STS_BITS; DescIndex++) { + + if (!IS_BIT_DESC_NULL (SrcDesc->Sts[DescIndex])) { + /// + /// Write the bit + /// + WriteBitDesc (&SrcDesc->Sts[DescIndex], 1, TRUE); + + /// + /// Don't return until the bit actually clears. + /// + IsSet =3D TRUE; + while (IsSet) { + IsSet =3D ReadBitDesc (&SrcDesc->Sts[DescIndex]); + /// + /// IsSet will eventually clear -- or else we'll have + /// an infinite loop. + /// + } + } + } +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmPeriodicTimer.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatch= er/Smm/PchSmmPeriodicTimer.c new file mode 100644 index 0000000000..9a5ae464e0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmPer= iodicTimer.c @@ -0,0 +1,675 @@ +/** @file + File to contain all the hardware specific stuff for the Periodical Timer= dispatch protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmHelpers.h" +#include +#include + +// +// There is only one instance for PeriodicTimerCommBuffer. +// It's safe in SMM since there is no re-entry for the function. +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_PERIODIC_TIMER_CONTEXT mPch= PeriodicTimerCommBuffer; + +typedef enum { + PERIODIC_TIMER=3D 0, + SWSMI_TIMER, + NUM_TIMERS +} SUPPORTED_TIMER; + +typedef struct _TIMER_INTERVAL { + UINT64 Interval; + UINT8 AssociatedTimer; +} TIMER_INTERVAL; + +#define NUM_INTERVALS 8 + +// +// Time constants, in 100 nano-second units +// +#define TIME_64s 640000000 ///< 64 s +#define TIME_32s 320000000 ///< 32 s +#define TIME_16s 160000000 ///< 16 s +#define TIME_8s 80000000 ///< 8 s +#define TIME_64ms 640000 ///< 64 ms +#define TIME_32ms 320000 ///< 32 ms +#define TIME_16ms 160000 ///< 16 ms +#define TIME_1_5ms 15000 ///< 1.5 ms + +typedef enum { + INDEX_TIME_64s =3D 0, + INDEX_TIME_32s, + INDEX_TIME_16s, + INDEX_TIME_8s, + INDEX_TIME_64ms, + INDEX_TIME_32ms, + INDEX_TIME_16ms, + INDEX_TIME_1_5ms, + INDEX_TIME_MAX +} TIMER_INTERVAL_INDEX; + +static TIMER_INTERVAL mSmmPeriodicTimerIntervals[NUM_INTERVALS] =3D { + { + TIME_64s, + PERIODIC_TIMER + }, + { + TIME_32s, + PERIODIC_TIMER + }, + { + TIME_16s, + PERIODIC_TIMER + }, + { + TIME_8s, + PERIODIC_TIMER + }, + { + TIME_64ms, + SWSMI_TIMER + }, + { + TIME_32ms, + SWSMI_TIMER + }, + { + TIME_16ms, + SWSMI_TIMER + }, + { + TIME_1_5ms, + SWSMI_TIMER + }, +}; + +typedef struct _TIMER_INFO { + UINTN NumChildren; ///< number of children using this timer + UINT64 MinReqInterval; ///< minimum interval required by children + UINTN CurrentSetting; ///< interval this timer is set at right now= (index into interval table) +} TIMER_INFO; + +GLOBAL_REMOVE_IF_UNREFERENCED TIMER_INFO mTimers[NUM_TIMERS]; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mTimerSourceDesc[N= UM_TIMERS] =3D { + { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_PERIODIC + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_PERIODIC + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_PERIODIC + } + }, + { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_SWSMI_TMR + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_SWSMI_TMR + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_SWSMI_TMR + } + } +}; + +/** + Program Smm Periodic Timer + + @param[in] SrcDesc Pointer to the PCH_SMM_SOURCE_DESC insta= nce. +**/ +VOID +PchSmmPeriodicTimerProgramTimers ( + IN CONST PCH_SMM_SOURCE_DESC *SrcDesc + ); + +/** + Convert the dispatch context to the timer interval, this function will a= ssert if then either: + (1) The context contains an invalid interval + (2) The timer interval table is corrupt + + @param[in] DispatchContext The pointer to the Dispatch Context + + @retval TIMER_INTERVAL The timer interval of input dispatch con= text +**/ +TIMER_INTERVAL * +ContextToTimerInterval ( + IN PCH_SMM_CONTEXT *DispatchContext + ) +{ + UINTN loopvar; + + /// + /// Determine which timer this child is using + /// + for (loopvar =3D 0; loopvar < NUM_INTERVALS; loopvar++) { + if (((DispatchContext->PeriodicTimer.SmiTickInterval =3D=3D 0) && + (DispatchContext->PeriodicTimer.Period >=3D mSmmPeriodicTimerInte= rvals[loopvar].Interval)) || + (DispatchContext->PeriodicTimer.SmiTickInterval =3D=3D mSmmPeriodi= cTimerIntervals[loopvar].Interval)) { + return &mSmmPeriodicTimerIntervals[loopvar]; + } + } + /// + /// If this assertion fires, then either: + /// (1) the context contains an invalid interval + /// (2) the timer interval table is corrupt + /// + ASSERT (FALSE); + + return NULL; +} + +/** + Figure out which timer the child is requesting and + send back the source description + + @param[in] DispatchContext The pointer to the Dispatch Context inst= ances + @param[out] SrcDesc The pointer to the source description + +**/ +VOID +MapPeriodicTimerToSrcDesc ( + IN PCH_SMM_CONTEXT *DispatchContext, + OUT PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + TIMER_INTERVAL *TimerInterval; + + /// + /// Figure out which timer the child is requesting and + /// send back the source description + /// + TimerInterval =3D ContextToTimerInterval (DispatchContext); + if (TimerInterval =3D=3D NULL) { + return; + } + + CopyMem ( + (VOID *) SrcDesc, + (VOID *) (&mTimerSourceDesc[TimerInterval->AssociatedTimer]), + sizeof (PCH_SMM_SOURCE_DESC) + ); + + /// + /// Program the value of the interval into hardware + /// + PchSmmPeriodicTimerProgramTimers (SrcDesc); +} + +/** + Update the elapsed time from the Interval data of DATABASE_RECORD + + @param[in] Record The pointer to the DATABASE_RECORD. + @param[out] HwContext The Context to be updated. + +**/ +VOID +EFIAPI +PeriodicTimerGetContext ( + IN DATABASE_RECORD *Record, + OUT PCH_SMM_CONTEXT *HwContext + ) +{ + TIMER_INTERVAL *TimerInterval; + + ASSERT (Record->ProtocolType =3D=3D PeriodicTimerType); + + TimerInterval =3D ContextToTimerInterval (&Record->ChildContext); + if (TimerInterval =3D=3D NULL) { + return; + } + /// + /// Ignore the hardware context. It's not required for this protocol. + /// Instead, just increment the child's context. + /// Update the elapsed time w/ the data from our tables + /// + Record->MiscData.ElapsedTime +=3D mTimers[TimerInterval->AssociatedTimer= ].MinReqInterval; + *HwContext =3D Record->ChildContext; +} + +/** + Check whether Periodic Timer of two contexts match + + @param[in] Context1 Context 1 that includes Periodic Timer 1 + @param[in] Context2 Context 2 that includes Periodic Timer 2 + + @retval FALSE Periodic Timer match + @retval TRUE Periodic Timer don't match +**/ +BOOLEAN +EFIAPI +PeriodicTimerCmpContext ( + IN PCH_SMM_CONTEXT *HwContext, + IN PCH_SMM_CONTEXT *ChildContext + ) +{ + DATABASE_RECORD *Record; + Record =3D DATABASE_RECORD_FROM_CHILDCONTEXT (ChildContext); + + if (Record->MiscData.ElapsedTime >=3D ChildContext->PeriodicTimer.Period= ) { + /// + /// For EDKII, the ElapsedTime is reset when PeriodicTimerGetCommBuffer + /// + return TRUE; + } else { + return FALSE; + } +} + +/** + Gather the CommBuffer information of SmmPeriodicTimerDispatch2. + + @param[in] Record No use + @param[out] CommBuffer Point to the CommBuffer structure + @param[out] CommBufferSize Point to the Size of CommBuffer structure + +**/ +VOID +EFIAPI +PeriodicTimerGetCommBuffer ( + IN DATABASE_RECORD *Record, + OUT VOID **CommBuffer, + OUT UINTN *CommBufferSize + ) +{ + ASSERT (Record->ProtocolType =3D=3D PeriodicTimerType); + + mPchPeriodicTimerCommBuffer.ElapsedTime =3D Record->MiscData.ElapsedTime; + + /// + /// For EDKII, the ElapsedTime is reset here + /// + Record->MiscData.ElapsedTime =3D 0; + + /// + /// Return the CommBuffer + /// + *CommBuffer =3D (VOID *) &mPchPeriodicTimerCommBuffer; + *CommBufferSize =3D sizeof (EFI_SMM_PERIODIC_TIMER_CONTEXT); +} + +/** + Program Smm Periodic Timer + + @param[in] SrcDesc Pointer to the PCH_SMM_SOURCE_DESC insta= nce. +**/ +VOID +PchSmmPeriodicTimerProgramTimers ( + IN CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + SUPPORTED_TIMER Timer; + DATABASE_RECORD *RecordInDb; + LIST_ENTRY *LinkInDb; + TIMER_INTERVAL *TimerInterval; + + /// + /// Find the minimum required interval for each timer + /// + for (Timer =3D 0; Timer < NUM_TIMERS; Timer++) { + mTimers[Timer].MinReqInterval =3D ~ (UINT64) 0x0; + mTimers[Timer].NumChildren =3D 0; + } + + LinkInDb =3D GetFirstNode (&mPrivateData.CallbackDataBase); + while (!IsNull (&mPrivateData.CallbackDataBase, LinkInDb)) { + RecordInDb =3D DATABASE_RECORD_FROM_LINK (LinkInDb); + if (RecordInDb->ProtocolType =3D=3D PeriodicTimerType) { + /// + /// This child is registerd with the PeriodicTimer protocol + /// + TimerInterval =3D ContextToTimerInterval (&RecordInDb->ChildContext); + if (TimerInterval =3D=3D NULL) { + return; + } + + Timer =3D TimerInterval->AssociatedTimer; + if (Timer < 0 || Timer >=3D NUM_TIMERS) { + ASSERT (FALSE); + CpuDeadLoop (); + return; + } + + if (mTimers[Timer].MinReqInterval > RecordInDb->ChildContext.Periodi= cTimer.SmiTickInterval) { + mTimers[Timer].MinReqInterval =3D RecordInDb->ChildContext.Periodi= cTimer.SmiTickInterval; + } + + mTimers[Timer].NumChildren++; + } + + LinkInDb =3D GetNextNode (&mPrivateData.CallbackDataBase, &RecordInDb-= >Link); + } + /// + /// Program the hardware + /// + if (mTimers[PERIODIC_TIMER].NumChildren > 0) { + switch (mTimers[PERIODIC_TIMER].MinReqInterval) { + case TIME_64s: + PmcSetPeriodicSmiRate (PmcPeriodicSmiRate64s); + mTimers[PERIODIC_TIMER].CurrentSetting =3D INDEX_TIME_64s; + break; + + case TIME_32s: + PmcSetPeriodicSmiRate (PmcPeriodicSmiRate32s); + mTimers[PERIODIC_TIMER].CurrentSetting =3D INDEX_TIME_32s; + break; + + case TIME_16s: + PmcSetPeriodicSmiRate (PmcPeriodicSmiRate16s); + mTimers[PERIODIC_TIMER].CurrentSetting =3D INDEX_TIME_16s; + break; + + case TIME_8s: + PmcSetPeriodicSmiRate (PmcPeriodicSmiRate8s); + mTimers[PERIODIC_TIMER].CurrentSetting =3D INDEX_TIME_8s; + break; + + default: + ASSERT (FALSE); + break; + } + + /// + /// Restart the timer here, just need to clear the SMI + /// + if (SrcDesc->Sts[0].Bit =3D=3D N_ACPI_IO_SMI_STS_PERIODIC) { + PchSmmClearSource (&mTimerSourceDesc[PERIODIC_TIMER]); + } + } else { + PchSmmDisableSource (&mTimerSourceDesc[PERIODIC_TIMER]); + } + + if (mTimers[SWSMI_TIMER].NumChildren > 0) { + switch (mTimers[SWSMI_TIMER].MinReqInterval) { + case TIME_64ms: + PmcSetSwSmiRate (PmcSwSmiRate64ms); + mTimers[SWSMI_TIMER].CurrentSetting =3D INDEX_TIME_64ms; + break; + + case TIME_32ms: + PmcSetSwSmiRate (PmcSwSmiRate32ms); + mTimers[SWSMI_TIMER].CurrentSetting =3D INDEX_TIME_32ms; + break; + + case TIME_16ms: + PmcSetSwSmiRate (PmcSwSmiRate16ms); + mTimers[SWSMI_TIMER].CurrentSetting =3D INDEX_TIME_16ms; + break; + + case TIME_1_5ms: + PmcSetSwSmiRate (PmcSwSmiRate1p5ms); + mTimers[SWSMI_TIMER].CurrentSetting =3D INDEX_TIME_1_5ms; + break; + + default: + ASSERT (FALSE); + break; + } + + /// + /// Restart the timer here, need to disable, clear, then enable to res= tart this timer + /// + if (SrcDesc->Sts[0].Bit =3D=3D N_ACPI_IO_SMI_STS_SWSMI_TMR) { + PchSmmDisableSource (&mTimerSourceDesc[SWSMI_TIMER]); + PchSmmClearSource (&mTimerSourceDesc[SWSMI_TIMER]); + PchSmmEnableSource (&mTimerSourceDesc[SWSMI_TIMER]); + } + } else { + PchSmmDisableSource (&mTimerSourceDesc[SWSMI_TIMER]); + } +} + +/** + This services returns the next SMI tick period that is supported by the = chipset. + The order returned is from longest to shortest interval period. + + @param[in] This Pointer to the EFI_SMM_PERIODIC_TIMER_DI= SPATCH2_PROTOCOL instance. + @param[in, out] SmiTickInterval Pointer to pointer of the next shorter S= MI interval period that is supported by the child. + + @retval EFI_SUCCESS The service returned successfully. + @retval EFI_INVALID_PARAMETER The parameter SmiTickInterval is invalid. +**/ +EFI_STATUS +PchSmmPeriodicTimerDispatchGetNextShorterInterval ( + IN CONST EFI_SMM_PERIODIC_TIMER_DISPATCH2_PROTOCOL *This, + IN OUT UINT64 **SmiTickInterval + ) +{ + TIMER_INTERVAL *IntervalPointer; + + if (SmiTickInterval =3D=3D NULL) { + ASSERT(FALSE); + return EFI_INVALID_PARAMETER; + } + + IntervalPointer =3D (TIMER_INTERVAL *) *SmiTickInterval; + + if (IntervalPointer =3D=3D NULL) { + /// + /// The first time child requesting an interval + /// + IntervalPointer =3D &mSmmPeriodicTimerIntervals[0]; + } else if (IntervalPointer =3D=3D &mSmmPeriodicTimerIntervals[NUM_INTERV= ALS - 1]) { + /// + /// At end of the list + /// + IntervalPointer =3D NULL; + } else { + if ((IntervalPointer >=3D &mSmmPeriodicTimerIntervals[0]) && + (IntervalPointer < &mSmmPeriodicTimerIntervals[NUM_INTERVALS - 1]) + ) { + /// + /// Get the next interval in the list + /// + IntervalPointer++; + } else { + /// + /// Input is out of range + /// + return EFI_INVALID_PARAMETER; + } + } + + if (IntervalPointer !=3D NULL) { + *SmiTickInterval =3D &IntervalPointer->Interval; + } else { + *SmiTickInterval =3D NULL; + } + + return EFI_SUCCESS; +} + +/** + This function is responsible for calculating and enabling any timers tha= t are required + to dispatch messages to children. The SrcDesc argument isn't acutally us= ed. + + @param[in] SrcDesc Pointer to the PCH_SMM_SOURCE_DESC insta= nce. + +**/ +VOID +EFIAPI +PchSmmPeriodicTimerClearSource ( + IN CONST PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + PchSmmPeriodicTimerProgramTimers (SrcDesc); +} + + +/** + Check if the handle is in type of PeriodicTimer + + @retval TRUE The handle is in type of PeriodicT= imer. + @retval FALSE The handle is not in type of Perio= dicTimer. +**/ +BOOLEAN +IsSmmPeriodicTimerHandle ( + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *RecordInDb; + LIST_ENTRY *LinkInDb; + + LinkInDb =3D GetFirstNode (&mPrivateData.CallbackDataBase); + while (!IsNull (&mPrivateData.CallbackDataBase, LinkInDb)) { + if (DispatchHandle =3D=3D (EFI_HANDLE) LinkInDb) { + RecordInDb =3D DATABASE_RECORD_FROM_LINK (LinkInDb); + if (RecordInDb->ProtocolType =3D=3D PeriodicTimerType) { + return TRUE; + } + } + LinkInDb =3D GetNextNode (&mPrivateData.CallbackDataBase, LinkInDb); + } + return FALSE; +} + +/** + Pause SMM periodic timer callback function. + + This function disable the SMI enable of SMI timer according to the Dispa= tchHandle, + which is returned by SMM periodic timer callback registration. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. +**/ +EFI_STATUS +EFIAPI +PchSmmPeriodicTimerControlPause ( + IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *RecordInDb; + TIMER_INTERVAL *TimerInterval; + + if (IsSmmPeriodicTimerHandle (DispatchHandle) =3D=3D FALSE) { + return EFI_INVALID_PARAMETER; + } + + RecordInDb =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + TimerInterval =3D NULL; + TimerInterval =3D ContextToTimerInterval (&RecordInDb->ChildContext); + if (TimerInterval =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + PchSmmDisableSource (&mTimerSourceDesc[TimerInterval->AssociatedTimer]); + return EFI_SUCCESS; +} + +/** + Resume SMM periodic timer callback function. + + This function enable the SMI enable of SMI timer according to the Dispat= chHandle, + which is returned by SMM periodic timer callback registration. + + @retval EFI_SUCCESS This operation is complete. + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid. +**/ +EFI_STATUS +EFIAPI +PchSmmPeriodicTimerControlResume ( + IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + DATABASE_RECORD *RecordInDb; + TIMER_INTERVAL *TimerInterval; + + if (IsSmmPeriodicTimerHandle (DispatchHandle) =3D=3D FALSE) { + return EFI_INVALID_PARAMETER; + } + + RecordInDb =3D DATABASE_RECORD_FROM_LINK (DispatchHandle); + TimerInterval =3D NULL; + TimerInterval =3D ContextToTimerInterval (&RecordInDb->ChildContext); + if (TimerInterval =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + PchSmmEnableSource (&mTimerSourceDesc[TimerInterval->AssociatedTimer]); + return EFI_SUCCESS; +} + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL mPch= SmmPeriodicTimerControlProtocol =3D { + PchSmmPeriodicTimerControlPause, + PchSmmPeriodicTimerControlResume +}; + +/** + Install PCH SMM periodic timer control protocol + + @param[in] Handle handle for this driver + + @retval EFI_SUCCESS Driver initialization completed su= ccessfully +**/ +EFI_STATUS +EFIAPI +InstallPchSmmPeriodicTimerControlProtocol ( + IN EFI_HANDLE Handle + ) +{ + EFI_STATUS Status; + + // + // Install protocol interface + // + Status =3D gSmst->SmmInstallProtocolInterface ( + &Handle, + &gPchSmmPeriodicTimerControlGuid, + EFI_NATIVE_INTERFACE, + &mPchSmmPeriodicTimerControlProtocol + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmPowerButton.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher= /Smm/PchSmmPowerButton.c new file mode 100644 index 0000000000..17898b899b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmPow= erButton.c @@ -0,0 +1,83 @@ +/** @file + File to contain all the hardware specific stuff for the Smm Power Button= dispatch protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mPowerButtonSource= Desc =3D { + PCH_SMM_SCI_EN_DEPENDENT, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_PM1_EN} + }, + S_ACPI_IO_PM1_EN, + N_ACPI_IO_PM1_EN_PWRBTN + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_PM1_STS} + }, + S_ACPI_IO_PM1_STS, + N_ACPI_IO_PM1_STS_PWRBTN + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_PM1_STS_REG + } +}; + +/** + Get the power button status. + + @param[in] Record The pointer to the DATABASE_RECORD. + @param[out] Context Calling context from the hardware, will = be updated with the current power button status. + +**/ +VOID +EFIAPI +PowerButtonGetContext ( + IN DATABASE_RECORD *Record, + OUT PCH_SMM_CONTEXT *Context + ) +{ + if (PmcGetPwrBtnLevel ()) { + Context->PowerButton.Phase =3D EfiPowerButtonExit; + } else { + Context->PowerButton.Phase =3D EfiPowerButtonEntry; + } +} + +/** + Check whether Power Button status of two contexts match + + @param[in] Context1 Context 1 that includes Power Button sta= tus 1 + @param[in] Context2 Context 2 that includes Power Button sta= tus 2 + + @retval FALSE Power Button status match + @retval TRUE Power Button status don't match +**/ +BOOLEAN +EFIAPI +PowerButtonCmpContext ( + IN PCH_SMM_CONTEXT *Context1, + IN PCH_SMM_CONTEXT *Context2 + ) +{ + return (BOOLEAN) (Context1->PowerButton.Phase =3D=3D Context2->PowerButt= on.Phase); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmSw.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchS= mmSw.c new file mode 100644 index 0000000000..35ecfe5238 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmSw.c @@ -0,0 +1,385 @@ +/** @file + File to contain all the hardware specific stuff for the Smm Sw dispatch = protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmHelpers.h" +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SMM_CPU_PROTOCOL *mSmmCpuProtoc= ol; + +STATIC LIST_ENTRY mSwSmiCallbackDataBase; + +// +// "SWSMI" RECORD +// Linked list data structures +// +#define SW_SMI_RECORD_SIGNATURE SIGNATURE_32 ('S', 'W', 'S', 'M') + +#define SW_SMI_RECORD_FROM_LINK(_record) CR (_record, SW_SMI_RECORD, Link= , SW_SMI_RECORD_SIGNATURE) + +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_SMM_SW_REGISTER_CONTEXT Context; + EFI_SMM_HANDLER_ENTRY_POINT2 Callback; +} SW_SMI_RECORD; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSwSourceDesc =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_APMC + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_APM + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_APM + } +}; + +/** + Check the SwSmiInputValue to see if there is a duplicated one in the dat= abase + + @param[in] SwSmiInputValue SwSmiInputValue + + @retval EFI_SUCCESS There is no duplicated SwSmiInputValue + @retval EFI_INVALID_PARAMETER There is a duplicated SwSmiInputValue +**/ +EFI_STATUS +SmiInputValueDuplicateCheck ( + IN UINTN SwSmiInputValue + ) +{ + SW_SMI_RECORD *SwSmiRecord; + LIST_ENTRY *LinkInDb; + + LinkInDb =3D GetFirstNode (&mSwSmiCallbackDataBase); + while (!IsNull (&mSwSmiCallbackDataBase, LinkInDb)) { + SwSmiRecord =3D SW_SMI_RECORD_FROM_LINK (LinkInDb); + if (SwSmiRecord->Context.SwSmiInputValue =3D=3D SwSmiInputValue) { + return EFI_INVALID_PARAMETER; + } + LinkInDb =3D GetNextNode (&mSwSmiCallbackDataBase, &SwSmiRecord->Link); + } + + return EFI_SUCCESS; +} + +/** + Register a child SMI source dispatch function for the specified software= SMI. + + This service registers a function (DispatchFunction) which will be calle= d when the software + SMI source specified by RegisterContext->SwSmiCpuIndex is detected. On r= eturn, + DispatchHandle contains a unique handle which may be used later to unreg= ister the function + using UnRegister(). + + @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PRO= TOCOL instance. + @param[in] DispatchFunction Function to register for handler when t= he specified software + SMI is generated. + @param[in, out] RegisterContext Pointer to the dispatch function's cont= ext. + The caller fills this context in before= calling + the register function to indicate to th= e register + function which Software SMI input value= the + dispatch function should be invoked for. + @param[out] DispatchHandle Handle generated by the dispatcher to t= rack the + function instance. + + @retval EFI_SUCCESS The dispatch function has been successful= ly + registered and the SMI source has been en= abled. + @retval EFI_DEVICE_ERROR The SW driver was unable to enable the SM= I source. + @retval EFI_INVALID_PARAMETER RegisterContext is invalid. The SW SMI in= put value + is not within a valid range or is already= in use. + @retval EFI_OUT_OF_RESOURCES There is not enough memory (system or SMM= ) to manage this + child. + @retval EFI_OUT_OF_RESOURCES A unique software SMI value could not be = assigned + for this dispatch. +**/ +EFI_STATUS +EFIAPI +PchSwSmiRegister ( + IN EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_SMM_HANDLER_ENTRY_POINT2 DispatchFunction, + IN EFI_SMM_SW_REGISTER_CONTEXT *DispatchContext, + OUT EFI_HANDLE *DispatchHandle + ) +{ + EFI_STATUS Status; + SW_SMI_RECORD *SwSmiRecord; + UINTN Index; + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "Register is not allowed if the SmmReadyToLock ev= ent has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + // + // Find available SW SMI value if the input is -1 + // + if (DispatchContext->SwSmiInputValue =3D=3D (UINTN) -1) { + for (Index =3D 1; Index < MAXIMUM_SWI_VALUE; Index++) { + Status =3D SmiInputValueDuplicateCheck (Index); + if (!EFI_ERROR (Status)) { + DispatchContext->SwSmiInputValue =3D Index; + break; + } + } + if (DispatchContext->SwSmiInputValue =3D=3D (UINTN) -1) { + return EFI_OUT_OF_RESOURCES; + } + } + // + // Check if it's a valid SW SMI value. + // The value must not bigger than 0xFF. + // And the value must not be 0xFF sincie it's used for SmmControll proto= col. + // + if (DispatchContext->SwSmiInputValue >=3D MAXIMUM_SWI_VALUE) { + return EFI_INVALID_PARAMETER; + } + + Status =3D SmiInputValueDuplicateCheck (DispatchContext->SwSmiInputValue= ); + if (EFI_ERROR (Status)) { + return EFI_INVALID_PARAMETER; + } + + // + // Create database record and add to database + // + Status =3D gSmst->SmmAllocatePool ( + EfiRuntimeServicesData, + sizeof (SW_SMI_RECORD), + (VOID **) &SwSmiRecord + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to allocate memory for SwSmiRecord! \n")); + return EFI_OUT_OF_RESOURCES; + } + // + // Gather information about the registration request + // + SwSmiRecord->Signature =3D SW_SMI_RECORD_SIGNATURE; + SwSmiRecord->Context.SwSmiInputValue =3D DispatchContext->SwSmiInputValu= e; + SwSmiRecord->Callback =3D DispatchFunction; + // + // Publish the S/W SMI numbers in Serial logs used for Debug build. + // + DEBUG ((DEBUG_INFO, "SW SMI NUM %x Sw Record at Address 0x%X\n", SwSmiR= ecord->Context.SwSmiInputValue, SwSmiRecord)); + + InsertTailList (&mSwSmiCallbackDataBase, &SwSmiRecord->Link); + + // + // Child's handle will be the address linked list link in the record + // + *DispatchHandle =3D (EFI_HANDLE) (&SwSmiRecord->Link); + + return EFI_SUCCESS; +} + +/** + Unregister a child SMI source dispatch function for the specified softwa= re SMI. + + This service removes the handler associated with DispatchHandle so that = it will no longer be + called in response to a software SMI. + + @param[in] This Pointer to the EFI_SMM_SW_DISPATCH2_PROTO= COL instance. + @param[in] DispatchHandle Handle of dispatch function to deregister. + + @retval EFI_SUCCESS The dispatch function has been successful= ly unregistered. + @retval EFI_INVALID_PARAMETER The DispatchHandle was not valid. +**/ +EFI_STATUS +EFIAPI +PchSwSmiUnRegister ( + IN CONST EFI_SMM_SW_DISPATCH2_PROTOCOL *This, + IN EFI_HANDLE DispatchHandle + ) +{ + EFI_STATUS Status; + SW_SMI_RECORD *RecordToDelete; + + if (DispatchHandle =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + // + // Return access denied if the SmmReadyToLock event has been triggered + // + if (mReadyToLock =3D=3D TRUE) { + DEBUG ((DEBUG_ERROR, "UnRegister is not allowed if the SmmReadyToLock = event has been triggered! \n")); + return EFI_ACCESS_DENIED; + } + + RecordToDelete =3D SW_SMI_RECORD_FROM_LINK (DispatchHandle); + // + // Take the entry out of the linked list + // + if (RecordToDelete->Signature !=3D SW_SMI_RECORD_SIGNATURE) { + return EFI_INVALID_PARAMETER; + } + + RemoveEntryList (&RecordToDelete->Link); + ZeroMem (RecordToDelete, sizeof (SW_SMI_RECORD)); + Status =3D gSmst->SmmFreePool (RecordToDelete); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + Main entry point for an SMM handler dispatch or communicate-based callba= ck. + + @param[in] DispatchHandle The unique handle assigned to this handle= r by SmiHandlerRegister(). + @param[in] Context Points to an optional handler context whi= ch was specified when the + handler was registered. + @param[in,out] CommBuffer A pointer to a collection of data in memo= ry that will + be conveyed from a non-SMM environment in= to an SMM environment. + @param[in,out] CommBufferSize The size of the CommBuffer. + + @retval EFI_SUCCESS The interrupt was handled an= d quiesced. No other handlers + should still be called. + @retval EFI_WARN_INTERRUPT_SOURCE_QUIESCED The interrupt has been quies= ced but other handlers should + still be called. + @retval EFI_WARN_INTERRUPT_SOURCE_PENDING The interrupt is still pendi= ng and other handlers should still + be called. + @retval EFI_INTERRUPT_PENDING The interrupt could not be q= uiesced. +**/ +EFI_STATUS +EFIAPI +PchSwSmiDispatcher ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *Context, + IN OUT VOID *CommBuffer, + IN OUT UINTN *CommBufferSize + ) +{ + EFI_STATUS Status; + EFI_SMM_SAVE_STATE_IO_INFO SmiIoInfo; + UINTN CpuIndex; + SW_SMI_RECORD *SwSmiRecord; + LIST_ENTRY *LinkInDb; + EFI_SMM_SW_CONTEXT SwSmiCommBuffer; + UINTN SwSmiCommBufferSize; + + SwSmiCommBufferSize =3D sizeof (EFI_SMM_SW_CONTEXT); + // + // The value in DataPort might not be accurate in multiple thread enviro= nment. + // There might be racing condition for R_PCH_IO_APM_STS port. + // Therefor, this is just for reference. + // + SwSmiCommBuffer.DataPort =3D IoRead8 (R_PCH_IO_APM_STS); + + for (CpuIndex =3D 0; CpuIndex < gSmst->NumberOfCpus; CpuIndex++) { + Status =3D mSmmCpuProtocol->ReadSaveState ( + mSmmCpuProtocol, + sizeof (EFI_SMM_SAVE_STATE_IO_INFO), + EFI_SMM_SAVE_STATE_REGISTER_IO, + CpuIndex, + &SmiIoInfo + ); + // + // If this is not the SMI source, skip it. + // + if (EFI_ERROR (Status)) { + continue; + } + // + // If the IO address is not "BYTE" "WRITE" to "R_PCH_IO_APM_CNT (0xB2)= ", skip it. + // + if ((SmiIoInfo.IoPort !=3D R_PCH_IO_APM_CNT) || + (SmiIoInfo.IoType !=3D EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT) || + (SmiIoInfo.IoWidth !=3D EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8)) + { + continue; + } + // + // If the IO data is used for SmmControl protocol, skip it. + // + if (SmiIoInfo.IoData =3D=3D 0xFF) { + continue; + } + + SwSmiCommBuffer.SwSmiCpuIndex =3D CpuIndex; + SwSmiCommBuffer.CommandPort =3D (UINT8) SmiIoInfo.IoData; + + LinkInDb =3D GetFirstNode (&mSwSmiCallbackDataBase); + while (!IsNull (&mSwSmiCallbackDataBase, LinkInDb)) { + SwSmiRecord =3D SW_SMI_RECORD_FROM_LINK (LinkInDb); + if (SwSmiRecord->Context.SwSmiInputValue =3D=3D SmiIoInfo.IoData) { + SwSmiRecord->Callback ((EFI_HANDLE) &SwSmiRecord->Link, &SwSmiReco= rd->Context, &SwSmiCommBuffer, &SwSmiCommBufferSize); + } + LinkInDb =3D GetNextNode (&mSwSmiCallbackDataBase, &SwSmiRecord->Lin= k); + } + } + + return EFI_SUCCESS; +} + +/** + Init required protocol for Pch Sw Dispatch protocol. +**/ +VOID +PchSwDispatchInit ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HANDLE DispatchHandle; + DATABASE_RECORD Record; + + // + // Locate PI SMM CPU protocol + // + Status =3D gSmst->SmmLocateProtocol (&gEfiSmmCpuProtocolGuid, NULL, (VOI= D **)&mSmmCpuProtocol); + ASSERT_EFI_ERROR (Status); + + // + // Initialize SW SMI Callback DataBase + // + InitializeListHead (&mSwSmiCallbackDataBase); + + // + // Insert SwSmi handler to PchSmmCore database + // There will always be one SwType record in PchSmmCore database + // + ZeroMem (&Record, sizeof (DATABASE_RECORD)); + Record.Signature =3D DATABASE_RECORD_SIGNATURE; + Record.Callback =3D PchSwSmiDispatcher; + Record.ProtocolType =3D SwType; + + CopyMem (&Record.SrcDesc, &mSwSourceDesc, sizeof (PCH_SMM_SOURCE_DESC)); + + DispatchHandle =3D NULL; + Status =3D SmmCoreInsertRecord ( + &Record, + &DispatchHandle + ); + ASSERT_EFI_ERROR (Status); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmSx.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchS= mmSx.c new file mode 100644 index 0000000000..52bb906315 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmSx.c @@ -0,0 +1,229 @@ +/** @file + File to contain all the hardware specific stuff for the Smm Sx dispatch = protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmHelpers.h" +#include +#include + +#define PROGRESS_CODE_S3_SUSPEND_END PcdGet32 (PcdProgressCodeS3SuspendEn= d) + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mSxSourceDesc =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_ON_SLP_EN + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_ON_SLP_EN + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_ON_SLP_EN + } +}; + +/** + Get the Sleep type + + @param[in] Record No use + @param[out] Context The context that includes SLP_TYP bits t= o be filled + +**/ +VOID +EFIAPI +SxGetContext ( + IN DATABASE_RECORD *Record, + OUT PCH_SMM_CONTEXT *Context + ) +{ + UINT32 Pm1Cnt; + + Pm1Cnt =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_CNT)); + + /// + /// By design, the context phase will always be ENTRY + /// + Context->Sx.Phase =3D SxEntry; + + /// + /// Map the PM1_CNT register's SLP_TYP bits to the context type + /// + switch (Pm1Cnt & B_ACPI_IO_PM1_CNT_SLP_TYP) { + case V_ACPI_IO_PM1_CNT_S0: + Context->Sx.Type =3D SxS0; + break; + + case V_ACPI_IO_PM1_CNT_S1: + Context->Sx.Type =3D SxS1; + break; + + case V_ACPI_IO_PM1_CNT_S3: + Context->Sx.Type =3D SxS3; + break; + + case V_ACPI_IO_PM1_CNT_S4: + Context->Sx.Type =3D SxS4; + break; + + case V_ACPI_IO_PM1_CNT_S5: + Context->Sx.Type =3D SxS5; + break; + + default: + ASSERT (FALSE); + break; + } +} + +/** + Check whether sleep type of two contexts match + + @param[in] Context1 Context 1 that includes sleep type 1 + @param[in] Context2 Context 2 that includes sleep type 2 + + @retval FALSE Sleep types match + @retval TRUE Sleep types don't match +**/ +BOOLEAN +EFIAPI +SxCmpContext ( + IN PCH_SMM_CONTEXT *Context1, + IN PCH_SMM_CONTEXT *Context2 + ) +{ + return (BOOLEAN) (Context1->Sx.Type =3D=3D Context2->Sx.Type); +} + +/** + For each PCIE RP clear PME SCI status and disable SCI, then PCIEXP_WAKE_= STS from PMC. + This prevents platform from waking more than one time due to a single PC= IE wake event. + Normally it's up to OS to clear SCI statuses. But in a scenario where pl= atform wakes + and goes to S5 instead of booting to OS, the SCI status would remain set= and would trigger another wake. +**/ +VOID +ClearPcieSci ( + VOID + ) +{ + UINT32 MaxPorts; + UINT32 RpIndex; + UINT64 RpBase; + + MaxPorts =3D GetPchMaxPciePortNum (); + for (RpIndex =3D 0; RpIndex < MaxPorts; RpIndex++) { + RpBase =3D PchPcieBase (RpIndex); + if (PciSegmentRead16 (RpBase + PCI_VENDOR_ID_OFFSET) !=3D 0xFFFF) { + PciSegmentAnd8 ((RpBase + R_PCH_PCIE_CFG_MPC + 3), (UINT8)~((UINT8)(= B_PCH_PCIE_CFG_MPC_PMCE >> 24))); + PciSegmentWrite32 (RpBase + R_PCH_PCIE_CFG_SMSCS, B_PCH_PCIE_CFG_SMS= CS_PMCS); + } + } + IoWrite16 (mAcpiBaseAddr + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PCIEXP_W= AKE_STS); +} + + +/** + When we get an SMI that indicates that we are transitioning to a sleep s= tate, + we need to actually transition to that state. We do this by disabling t= he + "SMI on sleep enable" feature, which generates an SMI when the operating= system + tries to put the system to sleep, and then physically putting the system= to sleep. + + +**/ +VOID +PchSmmSxGoToSleep ( + VOID + ) +{ + UINT32 Pm1Cnt; + + ClearPcieSci (); + + /// + /// Flush cache into memory before we go to sleep. It is necessary for S= 3 sleep + /// because we may update memory in SMM Sx sleep handlers -- the updates= are in cache now + /// + AsmWbinvd (); + + /// + /// Disable SMIs + /// + PchSmmClearSource (&mSxSourceDesc); + PchSmmDisableSource (&mSxSourceDesc); + + /// + /// Get Power Management 1 Control Register Value + /// + Pm1Cnt =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_CNT)); + + /// + /// Record S3 suspend performance data + /// + if ((Pm1Cnt & B_ACPI_IO_PM1_CNT_SLP_TYP) =3D=3D V_ACPI_IO_PM1_CNT_S3) { + /// + /// Report status code before goto S3 sleep + /// + REPORT_STATUS_CODE (EFI_PROGRESS_CODE, PROGRESS_CODE_S3_SUSPEND_END); + + /// + /// Flush cache into memory before we go to sleep. + /// + AsmWbinvd (); + } + + /// + /// Now that SMIs are disabled, write to the SLP_EN bit again to trigger= the sleep + /// + Pm1Cnt |=3D B_ACPI_IO_PM1_CNT_SLP_EN; + + IoWrite32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_CNT), Pm1Cnt); + + /// + /// Should only proceed if wake event is generated. + /// + if ((Pm1Cnt & B_ACPI_IO_PM1_CNT_SLP_TYP) =3D=3D V_ACPI_IO_PM1_CNT_S1) { + while (((IoRead16 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_STS))) & B_A= CPI_IO_PM1_STS_WAK) =3D=3D 0x0); + } else { + CpuDeadLoop (); + } + /// + /// The system just went to sleep. If the sleep state was S1, then code = execution will resume + /// here when the system wakes up. + /// + Pm1Cnt =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_CNT)); + + if ((Pm1Cnt & B_ACPI_IO_PM1_CNT_SCI_EN) =3D=3D 0) { + /// + /// An ACPI OS isn't present, clear the sleep information + /// + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SLP_TYP; + Pm1Cnt |=3D V_ACPI_IO_PM1_CNT_S0; + + IoWrite32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_CNT), Pm1Cnt); + } + + PchSmmClearSource (&mSxSourceDesc); + PchSmmEnableSource (&mSxSourceDesc); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hSmmUsb.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pch= SmmUsb.c new file mode 100644 index 0000000000..061dbe4300 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchSmmUsb= .c @@ -0,0 +1,231 @@ +/** @file + File to contain all the hardware specific stuff for the Smm USB dispatch= protocol. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmHelpers.h" +#include +#include +#include + + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mUsb1Legacy =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_LEGACY_USB + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_LEGACY_USB + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_LEGACY_USB + } +}; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST PCH_SMM_SOURCE_DESC mUsb3Legacy =3D { + PCH_SMM_NO_FLAGS, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_EN} + }, + S_ACPI_IO_SMI_EN, + N_ACPI_IO_SMI_EN_LEGACY_USB3 + }, + NULL_BIT_DESC_INITIALIZER + }, + { + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_LEGACY_USB3 + } + }, + { + { + ACPI_ADDR_TYPE, + {R_ACPI_IO_SMI_STS} + }, + S_ACPI_IO_SMI_STS, + N_ACPI_IO_SMI_STS_LEGACY_USB3 + } +}; + +typedef enum { + PchUsbControllerLpc0 =3D 0, + PchUsbControllerXhci, + PchUsbControllerTypeMax +} PCH_USB_CONTROLLER_TYPE; + +typedef struct { + UINT8 Function; + UINT8 Device; + PCH_USB_CONTROLLER_TYPE UsbConType; +} USB_CONTROLLER; + +GLOBAL_REMOVE_IF_UNREFERENCED USB_CONTROLLER mUsbControllersMap[] =3D { + { + PCI_FUNCTION_NUMBER_PCH_LPC, + PCI_DEVICE_NUMBER_PCH_LPC, + PchUsbControllerLpc0 + }, + { + PCI_FUNCTION_NUMBER_PCH_XHCI, + PCI_DEVICE_NUMBER_PCH_XHCI, + PchUsbControllerXhci + } +}; + +/** + Find the handle that best matches the input Device Path and return the U= SB controller type + + @param[in] DevicePath Pointer to the device Path table + @param[out] Controller Returned with the USB controller type of= the input device path + + @retval EFI_SUCCESS Find the handle that best matches the in= put Device Path + @exception EFI_UNSUPPORTED Invalid device Path table or can't find = any match USB device path + PCH_USB_CONTROLLER_TYPE The USB controll= er type of the input + device path +**/ +EFI_STATUS +DevicePathToSupportedController ( + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, + OUT PCH_USB_CONTROLLER_TYPE *Controller + ) +{ + EFI_STATUS Status; + EFI_HANDLE DeviceHandle; + ACPI_HID_DEVICE_PATH *AcpiNode; + PCI_DEVICE_PATH *PciNode; + EFI_DEVICE_PATH_PROTOCOL *RemaingDevicePath; + UINT8 UsbIndex; + /// + /// Find the handle that best matches the Device Path. If it is only a + /// partial match the remaining part of the device path is returned in + /// RemainingDevicePath. + /// + RemaingDevicePath =3D DevicePath; + Status =3D gBS->LocateDevicePath ( + &gEfiPciRootBridgeIoProtocolGuid, + &DevicePath, + &DeviceHandle + ); + if (EFI_ERROR (Status)) { + return EFI_UNSUPPORTED; + } + + DevicePath =3D RemaingDevicePath; + + /// + /// Get first node: Acpi Node + /// + AcpiNode =3D (ACPI_HID_DEVICE_PATH *) RemaingDevicePath; + + if (AcpiNode->Header.Type !=3D ACPI_DEVICE_PATH || + AcpiNode->Header.SubType !=3D ACPI_DP || + DevicePathNodeLength (&AcpiNode->Header) !=3D sizeof (ACPI_HID_DEVIC= E_PATH) || + AcpiNode->HID !=3D EISA_PNP_ID (0x0A03) || + AcpiNode->UID !=3D 0 + ) { + return EFI_UNSUPPORTED; + } else { + /// + /// Get the next node: Pci Node + /// + RemaingDevicePath =3D NextDevicePathNode (RemaingDevicePath); + PciNode =3D (PCI_DEVICE_PATH *) RemaingDevicePath; + if (PciNode->Header.Type !=3D HARDWARE_DEVICE_PATH || + PciNode->Header.SubType !=3D HW_PCI_DP || + DevicePathNodeLength (&PciNode->Header) !=3D sizeof (PCI_DEVICE_PA= TH) + ) { + return EFI_UNSUPPORTED; + } + + for (UsbIndex =3D 0; UsbIndex < sizeof (mUsbControllersMap) / sizeof (= USB_CONTROLLER); UsbIndex++) { + if ((PciNode->Device =3D=3D mUsbControllersMap[UsbIndex].Device) && + (PciNode->Function =3D=3D mUsbControllersMap[UsbIndex].Function)= ) { + *Controller =3D mUsbControllersMap[UsbIndex].UsbConType; + return EFI_SUCCESS; + } + } + + return EFI_UNSUPPORTED; + } +} + +/** + Maps a USB context to a source description. + + @param[in] Context The context we need to map. Type must b= e USB. + @param[in] SrcDesc The source description that corresponds = to the given context. + +**/ +VOID +MapUsbToSrcDesc ( + IN PCH_SMM_CONTEXT *Context, + OUT PCH_SMM_SOURCE_DESC *SrcDesc + ) +{ + PCH_USB_CONTROLLER_TYPE Controller; + EFI_STATUS Status; + + Status =3D DevicePathToSupportedController (Context->Usb.Device, &Contro= ller); + /// + /// Either the device path passed in by the child is incorrect or + /// the ones stored here internally are incorrect. + /// + ASSERT_EFI_ERROR (Status); + + switch (Context->Usb.Type) { + case UsbLegacy: + switch (Controller) { + case PchUsbControllerLpc0: + CopyMem ((VOID *) SrcDesc, (VOID *) (&mUsb1Legacy), sizeof (PCH_= SMM_SOURCE_DESC)); + break; + + case PchUsbControllerXhci: + CopyMem ((VOID *) SrcDesc, (VOID *) (&mUsb3Legacy), sizeof (PCH_= SMM_SOURCE_DESC)); + break; + + default: + ASSERT (FALSE); + break; + } + break; + + case UsbWake: + ASSERT (FALSE); + break; + + default: + ASSERT (FALSE); + break; + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/Pc= hxSmmHelpers.c b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Sm= m/PchxSmmHelpers.c new file mode 100644 index 0000000000..4ac00b831f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/PchSmiDispatcher/Smm/PchxSmmHe= lpers.c @@ -0,0 +1,764 @@ +/** @file + This driver is responsible for the registration of child drivers + and the abstraction of the PCH SMI sources. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchSmmHelpers.h" +#include +#include + +// +// Help handle porting bit shifts to IA-64. +// +#define BIT_ZERO 0x00000001 + +/** + Publish SMI Dispatch protocols. + + +**/ +VOID +PchSmmPublishDispatchProtocols ( + VOID + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UINTN Index; + // + // Install protocol interfaces. + // + for (Index =3D 0; Index < PCH_SMM_PROTOCOL_TYPE_MAX; Index++) { + Status =3D gSmst->SmmInstallProtocolInterface ( + &mPrivateData.InstallMultProtHandle, + mPrivateData.Protocols[Index].Guid, + EFI_NATIVE_INTERFACE, + &mPrivateData.Protocols[Index].Protocols.Generic + ); + } + ASSERT_EFI_ERROR (Status); +} + +/** + Initialize bits that aren't necessarily related to an SMI source. + + + @retval EFI_SUCCESS SMI source initialization completed. + @retval Asserts Global Smi Bit is not enabled successful= ly. +**/ +EFI_STATUS +PchSmmInitHardware ( + VOID + ) +{ + EFI_STATUS Status; + + // + // Clear all SMIs + // + PchSmmClearSmi (); + + Status =3D PchSmmEnableGlobalSmiBit (); + ASSERT_EFI_ERROR (Status); + + // + // Be *really* sure to clear all SMIs + // + PchSmmClearSmi (); + + return EFI_SUCCESS; +} + +/** + Enables the PCH to generate SMIs. Note that no SMIs will be generated + if no SMI sources are enabled. Conversely, no enabled SMI source will + generate SMIs if SMIs are not globally enabled. This is the main + switchbox for SMI generation. + + + @retval EFI_SUCCESS Enable Global Smi Bit completed +**/ +EFI_STATUS +PchSmmEnableGlobalSmiBit ( + VOID + ) +{ + UINT32 SmiEn; + + SmiEn =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_EN)); + + // + // Set the "global smi enable" bit + // + SmiEn |=3D B_ACPI_IO_SMI_EN_GBL_SMI; + + IoWrite32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_EN), SmiEn); + + return EFI_SUCCESS; +} + +/** + Clears the SMI after all SMI source have been processed. + Note that this function will not work correctly (as it is + written) unless all SMI sources have been processed. + A revision of this function could manually clear all SMI + status bits to guarantee success. +**/ +VOID +PchSmmClearSmi ( + VOID + ) +{ + BOOLEAN EosSet; + BOOLEAN SciEn; + UINT32 Pm1Cnt; + UINT16 Pm1Sts; + UINT32 Gpe0Sts; + UINT32 SmiSts; + UINT16 DevActSts; + UINT16 Tco1Sts; + + Gpe0Sts =3D 0; + // + // Determine whether an ACPI OS is present (via the SCI_EN bit) + // + Pm1Cnt =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_CNT)); + SciEn =3D (BOOLEAN) ((Pm1Cnt & B_ACPI_IO_PM1_CNT_SCI_EN) =3D=3D B_ACPI_= IO_PM1_CNT_SCI_EN); + if (!SciEn) { + // + // Clear any SMIs that double as SCIs (when SCI_EN=3D=3D0) + // + Pm1Sts =3D IoRead16 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_STS)); + Gpe0Sts =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_GPE0_STS_127= _96)); + + Pm1Sts |=3D + ( + B_ACPI_IO_PM1_STS_WAK | + B_ACPI_IO_PM1_STS_PRBTNOR | + B_ACPI_IO_PM1_STS_RTC | + B_ACPI_IO_PM1_STS_PWRBTN | + B_ACPI_IO_PM1_STS_GBL | + B_ACPI_IO_PM1_STS_TMROF + ); + + Gpe0Sts &=3D (UINT32)~(B_ACPI_IO_GPE0_STS_127_96_WADT); + + IoWrite16 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_STS), (UINT16) Pm1St= s); + IoWrite32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_GPE0_STS_127_96), (UINT3= 2) Gpe0Sts); + } + // + // Clear all SMIs that are unaffected by SCI_EN + // + SmiSts =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_STS)); + DevActSts =3D IoRead16 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_DEVACT_ST= S)); + Tco1Sts =3D IoRead16 ((UINTN) (mTcoBaseAddr + R_TCO_IO_TCO1_STS)); + + SmiSts |=3D + ( + B_ACPI_IO_SMI_STS_SMBUS | + B_ACPI_IO_SMI_STS_PERIODIC | + B_ACPI_IO_SMI_STS_TCO | + B_ACPI_IO_SMI_STS_MCSMI | + B_ACPI_IO_SMI_STS_SWSMI_TMR | + B_ACPI_IO_SMI_STS_APM | + B_ACPI_IO_SMI_STS_ON_SLP_EN | + B_ACPI_IO_SMI_STS_BIOS + ); + DevActSts |=3D + ( + B_ACPI_IO_DEVACT_STS_KBC | + B_ACPI_IO_DEVACT_STS_PIRQDH | + B_ACPI_IO_DEVACT_STS_PIRQCG | + B_ACPI_IO_DEVACT_STS_PIRQBF | + B_ACPI_IO_DEVACT_STS_PIRQAE + ); + Tco1Sts |=3D + ( + B_TCO_IO_TCO1_STS_DMISERR | + B_TCO_IO_TCO1_STS_DMISMI | + B_TCO_IO_TCO1_STS_DMISCI | + B_TCO_IO_TCO1_STS_BIOSWR | + B_TCO_IO_TCO1_STS_NEWCENTURY | + B_TCO_IO_TCO1_STS_TIMEOUT | + B_TCO_IO_TCO1_STS_TCO_INT | + B_TCO_IO_TCO1_STS_SW_TCO_SMI + ); + + GpioClearAllGpiSmiSts (); + + IoWrite16 ((UINTN) (mTcoBaseAddr + R_TCO_IO_TCO1_STS), Tco1Sts); + + // + // We do not want to write 1 to clear INTRD_DET bit. + // + IoWrite16 ((UINTN) (mTcoBaseAddr + R_TCO_IO_TCO2_STS), (UINT16) ~B_TCO_I= O_TCO2_STS_INTRD_DET); + + IoWrite32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_STS), SmiSts); + + IoWrite16 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_DEVACT_STS), DevActSts); + + // + // Try to clear the EOS bit. ASSERT on an error + // + EosSet =3D PchSmmSetAndCheckEos (); + ASSERT (EosSet); +} + +/** + Set the SMI EOS bit after all SMI source have been processed. + + + @retval FALSE EOS was not set to a 1; this is an error + @retval TRUE EOS was correctly set to a 1 +**/ +BOOLEAN +PchSmmSetAndCheckEos ( + VOID + ) +{ + UINT32 SmiEn; + + SmiEn =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_EN)); + + // + // Reset the PCH to generate subsequent SMIs + // + SmiEn |=3D B_ACPI_IO_SMI_EN_EOS; + + IoWrite32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_EN), SmiEn); + + // + // Double check that the assert worked + // + SmiEn =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_SMI_EN)); + + // + // Return TRUE if EOS is set correctly + // + if ((SmiEn & B_ACPI_IO_SMI_EN_EOS) =3D=3D 0) { + // + // EOS was not set to a 1; this is an error + // + return FALSE; + } else { + // + // EOS was correctly set to a 1 + // + return TRUE; + } +} + +/** + Determine whether an ACPI OS is present (via the SCI_EN bit) + + + @retval TRUE ACPI OS is present + @retval FALSE ACPI OS is not present +**/ +BOOLEAN +PchSmmGetSciEn ( + VOID + ) +{ + BOOLEAN SciEn; + UINT32 Pm1Cnt; + + // + // Determine whether an ACPI OS is present (via the SCI_EN bit) + // + Pm1Cnt =3D IoRead32 ((UINTN) (mAcpiBaseAddr + R_ACPI_IO_PM1_CNT)); + SciEn =3D (BOOLEAN) ((Pm1Cnt & B_ACPI_IO_PM1_CNT_SCI_EN) =3D=3D B_ACPI= _IO_PM1_CNT_SCI_EN); + + return SciEn; +} + +/** + Read a specifying bit with the register + These may or may not need to change w/ the PCH version; they're highly I= A-32 dependent, though. + + @param[in] BitDesc The struct that includes register addres= s, size in byte and bit number + + @retval TRUE The bit is enabled + @retval FALSE The bit is disabled +**/ +BOOLEAN +ReadBitDesc ( + CONST PCH_SMM_BIT_DESC *BitDesc + ) +{ + EFI_STATUS Status; + UINT64 Register; + UINT32 PciBus; + UINT32 PciDev; + UINT32 PciFun; + UINT32 PciReg; + UINTN RegSize; + BOOLEAN BitWasOne; + UINTN ShiftCount; + UINTN RegisterOffset; + UINT32 BaseAddr; + UINT64 PciBaseAddress; + + ASSERT (BitDesc !=3D NULL); + ASSERT (!IS_BIT_DESC_NULL (*BitDesc)); + + RegSize =3D 0; + Register =3D 0; + ShiftCount =3D 0; + BitWasOne =3D FALSE; + + switch (BitDesc->Reg.Type) { + + case ACPI_ADDR_TYPE: + case TCO_ADDR_TYPE: + if (BitDesc->Reg.Type =3D=3D ACPI_ADDR_TYPE) { + RegisterOffset =3D BitDesc->Reg.Data.acpi; + BaseAddr =3D mAcpiBaseAddr; + } else { + RegisterOffset =3D BitDesc->Reg.Data.tco; + BaseAddr =3D mTcoBaseAddr; + } + switch (BitDesc->SizeInBytes) { + + case 0: + // + // Chances are that this field didn't get initialized. + // Check your assignments to bit descriptions. + // + ASSERT (FALSE); + break; + + case 1: + RegSize =3D SMM_IO_UINT8; + break; + + case 2: + RegSize =3D SMM_IO_UINT16; + break; + + case 4: + RegSize =3D SMM_IO_UINT32; + break; + + case 8: + RegSize =3D SMM_IO_UINT64; + break; + + default: + // + // Unsupported or invalid register size + // + ASSERT (FALSE); + break; + } + // + // Double check that we correctly read in the acpi base address + // + ASSERT ((BaseAddr !=3D 0x0) && ((BaseAddr & 0x1) !=3D 0x1)); + + ShiftCount =3D BitDesc->Bit; + // + // As current CPU Smm Io can only support at most + // 32-bit read/write,if Operation is 64 bit, + // we do a 32 bit operation according to BitDesc->Bit + // + if (RegSize =3D=3D SMM_IO_UINT64) { + RegSize =3D SMM_IO_UINT32; + // + // If the operation is for high 32 bits + // + if (BitDesc->Bit >=3D 32) { + RegisterOffset +=3D 4; + ShiftCount -=3D 32; + } + } + + Status =3D gSmst->SmmIo.Io.Read ( + &gSmst->SmmIo, + RegSize, + BaseAddr + RegisterOffset, + 1, + &Register + ); + ASSERT_EFI_ERROR (Status); + + if ((Register & (LShiftU64 (BIT_ZERO, ShiftCount))) !=3D 0) { + BitWasOne =3D TRUE; + } else { + BitWasOne =3D FALSE; + } + break; + + case GPIO_ADDR_TYPE: + case MEMORY_MAPPED_IO_ADDRESS_TYPE: + // + // Read the register, and it with the bit to read + // + switch (BitDesc->SizeInBytes) { + case 1: + Register =3D (UINT64) MmioRead8 ((UINTN) BitDesc->Reg.Data.Mmio); + break; + + case 2: + Register =3D (UINT64) MmioRead16 ((UINTN) BitDesc->Reg.Data.Mmio= ); + break; + + case 4: + Register =3D (UINT64) MmioRead32 ((UINTN) BitDesc->Reg.Data.Mmio= ); + break; + + case 8: + Register =3D (UINT64) MmioRead32 ((UINTN) B= itDesc->Reg.Data.Mmio); + *((UINT32 *) (&Register) + 1) =3D MmioRead32 ((UINTN) BitDesc->R= eg.Data.Mmio + 4); + break; + + default: + // + // Unsupported or invalid register size + // + ASSERT (FALSE); + break; + } + + Register =3D Register & (LShiftU64 (BIT0, BitDesc->Bit)); + if (Register) { + BitWasOne =3D TRUE; + } else { + BitWasOne =3D FALSE; + } + break; + + case PCIE_ADDR_TYPE: + PciBus =3D BitDesc->Reg.Data.pcie.Fields.Bus; + PciDev =3D BitDesc->Reg.Data.pcie.Fields.Dev; + PciFun =3D BitDesc->Reg.Data.pcie.Fields.Fnc; + PciReg =3D BitDesc->Reg.Data.pcie.Fields.Reg; + PciBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMB= ER_PCH, PciBus, PciDev, PciFun, 0); + switch (BitDesc->SizeInBytes) { + + case 0: + // + // Chances are that this field didn't get initialized. + // Check your assignments to bit descriptions. + // + ASSERT (FALSE); + break; + + case 1: + Register =3D (UINT64) PciSegmentRead8 (PciBaseAddress + PciReg); + break; + + case 2: + Register =3D (UINT64) PciSegmentRead16 (PciBaseAddress + PciReg); + break; + + case 4: + Register =3D (UINT64) PciSegmentRead32 (PciBaseAddress + PciReg); + break; + + default: + // + // Unsupported or invalid register size + // + ASSERT (FALSE); + break; + } + + if ((Register & (LShiftU64 (BIT_ZERO, BitDesc->Bit))) !=3D 0) { + BitWasOne =3D TRUE; + } else { + BitWasOne =3D FALSE; + } + break; + + case PCR_ADDR_TYPE: + // + // Read the register, and it with the bit to read + // + switch (BitDesc->SizeInBytes) { + case 1: + Register =3D PchPcrRead8 (BitDesc->Reg.Data.Pcr.Fields.Pid, Bit= Desc->Reg.Data.Pcr.Fields.Offset); + break; + + case 2: + Register =3D PchPcrRead16 (BitDesc->Reg.Data.Pcr.Fields.Pid, Bit= Desc->Reg.Data.Pcr.Fields.Offset); + break; + + case 4: + Register =3D PchPcrRead32 (BitDesc->Reg.Data.Pcr.Fields.Pid, Bit= Desc->Reg.Data.Pcr.Fields.Offset); + break; + + default: + // + // Unsupported or invalid register size + // + ASSERT (FALSE); + break; + } + + Register =3D Register & (LShiftU64 (BIT0, BitDesc->Bit)); + if (Register) { + BitWasOne =3D TRUE; + } else { + BitWasOne =3D FALSE; + } + break; + + default: + // + // This address type is not yet implemented + // + ASSERT (FALSE); + break; + } + + return BitWasOne; +} + +/** + Write a specifying bit with the register + + @param[in] BitDesc The struct that includes register addres= s, size in byte and bit number + @param[in] ValueToWrite The value to be wrote + @param[in] WriteClear If the rest bits of the register is writ= e clear + +**/ +VOID +WriteBitDesc ( + CONST PCH_SMM_BIT_DESC *BitDesc, + CONST BOOLEAN ValueToWrite, + CONST BOOLEAN WriteClear + ) +{ + EFI_STATUS Status; + UINT64 Register; + UINT64 AndVal; + UINT64 OrVal; + UINT32 RegSize; + UINT32 PciBus; + UINT32 PciDev; + UINT32 PciFun; + UINT32 PciReg; + UINTN RegisterOffset; + UINT32 BaseAddr; + UINT64 PciBaseAddress; + + ASSERT (BitDesc !=3D NULL); + ASSERT (!IS_BIT_DESC_NULL (*BitDesc)); + + RegSize =3D 0; + Register =3D 0; + + if (WriteClear) { + AndVal =3D LShiftU64 (BIT_ZERO, BitDesc->Bit); + } else { + AndVal =3D ~(LShiftU64 (BIT_ZERO, BitDesc->Bit)); + } + + OrVal =3D (LShiftU64 ((UINT32) ValueToWrite, BitDesc->Bit)); + + switch (BitDesc->Reg.Type) { + + case ACPI_ADDR_TYPE: + case TCO_ADDR_TYPE: + if (BitDesc->Reg.Type =3D=3D ACPI_ADDR_TYPE) { + RegisterOffset =3D BitDesc->Reg.Data.acpi; + BaseAddr =3D mAcpiBaseAddr; + } else { + RegisterOffset =3D BitDesc->Reg.Data.tco; + BaseAddr =3D mTcoBaseAddr; + } + + switch (BitDesc->SizeInBytes) { + + case 0: + // + // Chances are that this field didn't get initialized. + // Check your assignments to bit descriptions. + // + ASSERT (FALSE); + break; + + case 1: + RegSize =3D SMM_IO_UINT8; + break; + + case 2: + RegSize =3D SMM_IO_UINT16; + break; + + case 4: + RegSize =3D SMM_IO_UINT32; + break; + + case 8: + RegSize =3D SMM_IO_UINT64; + break; + + default: + // + // Unsupported or invalid register size + // + ASSERT (FALSE); + break; + } + // + // Double check that we correctly read in the acpi base address + // + ASSERT ((BaseAddr !=3D 0x0) && ((BaseAddr & 0x1) !=3D 0x1)); + + // + // As current CPU Smm Io can only support at most + // 32-bit read/write,if Operation is 64 bit, + // we do a 32 bit operation according to BitDesc->Bit + // + if (RegSize =3D=3D SMM_IO_UINT64) { + RegSize =3D SMM_IO_UINT32; + // + // If the operation is for high 32 bits + // + if (BitDesc->Bit >=3D 32) { + RegisterOffset +=3D 4; + + if (WriteClear) { + AndVal =3D LShiftU64 (BIT_ZERO, BitDesc->Bit - 32); + } else { + AndVal =3D ~(LShiftU64 (BIT_ZERO, BitDesc->Bit - 32)); + } + + OrVal =3D LShiftU64 ((UINT32) ValueToWrite, BitDesc->Bit - 32); + } + } + + Status =3D gSmst->SmmIo.Io.Read ( + &gSmst->SmmIo, + RegSize, + BaseAddr + RegisterOffset, + 1, + &Register + ); + ASSERT_EFI_ERROR (Status); + + Register &=3D AndVal; + Register |=3D OrVal; + + Status =3D gSmst->SmmIo.Io.Write ( + &gSmst->SmmIo, + RegSize, + BaseAddr + RegisterOffset, + 1, + &Register + ); + ASSERT_EFI_ERROR (Status); + break; + + case GPIO_ADDR_TYPE: + case MEMORY_MAPPED_IO_ADDRESS_TYPE: + // + // Read the register, or it with the bit to set, then write it back. + // + switch (BitDesc->SizeInBytes) { + case 1: + MmioAndThenOr8 ((UINTN) BitDesc->Reg.Data.Mmio, (UINT8) AndVal= , (UINT8) OrVal); + break; + + case 2: + MmioAndThenOr16 ((UINTN) BitDesc->Reg.Data.Mmio, (UINT16) AndVal= , (UINT16) OrVal); + break; + + case 4: + MmioAndThenOr32 ((UINTN) BitDesc->Reg.Data.Mmio, (UINT32) AndVal= , (UINT32) OrVal); + break; + + case 8: + Register =3D (UINT64) MmioRead32 ((UINTN) B= itDesc->Reg.Data.Mmio); + *((UINT32 *) (&Register) + 1) =3D MmioRead32 ((UINTN) BitDesc->R= eg.Data.Mmio + 4); + Register &=3D AndVal; + Register |=3D OrVal; + MmioWrite32 ((UINTN) BitDesc->Reg.Data.Mmio, (UINT32) Register); + MmioWrite32 ((UINTN) BitDesc->Reg.Data.Mmio + 4, *((UINT32 *) (&= Register) + 1)); + break; + + default: + // + // Unsupported or invalid register size + // + ASSERT (FALSE); + break; + } + break; + + case PCIE_ADDR_TYPE: + PciBus =3D BitDesc->Reg.Data.pcie.Fields.Bus; + PciDev =3D BitDesc->Reg.Data.pcie.Fields.Dev; + PciFun =3D BitDesc->Reg.Data.pcie.Fields.Fnc; + PciReg =3D BitDesc->Reg.Data.pcie.Fields.Reg; + PciBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUMB= ER_PCH, PciBus, PciDev, PciFun, 0); + switch (BitDesc->SizeInBytes) { + + case 0: + // + // Chances are that this field didn't get initialized -- check y= our assignments + // to bit descriptions. + // + ASSERT (FALSE); + break; + + case 1: + PciSegmentAndThenOr8 (PciBaseAddress + PciReg, (UINT8) AndVal, (= UINT8) OrVal); + break; + + case 2: + PciSegmentAndThenOr16 (PciBaseAddress + PciReg, (UINT16) AndVal,= (UINT16) OrVal); + break; + + case 4: + PciSegmentAndThenOr32 (PciBaseAddress + PciReg, (UINT32) AndVal,= (UINT32) OrVal); + break; + + default: + // + // Unsupported or invalid register size + // + ASSERT (FALSE); + break; + } + break; + + case PCR_ADDR_TYPE: + // + // Read the register, or it with the bit to set, then write it back. + // + switch (BitDesc->SizeInBytes) { + case 1: + PchPcrAndThenOr8 ((PCH_SBI_PID) BitDesc->Reg.Data.Pcr.Fields.Pi= d, (UINT16) BitDesc->Reg.Data.Pcr.Fields.Offset, (UINT8) AndVal, (UINT8) = OrVal); + break; + + case 2: + PchPcrAndThenOr16 ((PCH_SBI_PID) BitDesc->Reg.Data.Pcr.Fields.Pi= d, (UINT16) BitDesc->Reg.Data.Pcr.Fields.Offset, (UINT16) AndVal, (UINT16) = OrVal); + break; + + case 4: + PchPcrAndThenOr32 ((PCH_SBI_PID) BitDesc->Reg.Data.Pcr.Fields.Pi= d, (UINT16) BitDesc->Reg.Data.Pcr.Fields.Offset, (UINT32) AndVal, (UINT32) = OrVal); + break; + + default: + // + // Unsupported or invalid register size + // + ASSERT (FALSE); + break; + } + break; + + default: + // + // This address type is not yet implemented + // + ASSERT (FALSE); + break; + } +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45903): https://edk2.groups.io/g/devel/message/45903 Mute This Topic: https://groups.io/mt/32918196/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45906+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45906+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001020; cv=none; d=zoho.com; s=zohoarc; b=fsPMZBUxh9Oe0GcUUI5dFq0YNMReVw7rrRqt6wNoTkQ4ivr7/d+eNFua4/vSgMrK1wGK63aqQZY/cZ7qAunBXHqCnMm/1zKzumQ0/azjs0/Qy5Cwwkb3PIK1dXlGVAtzmTrw52+KFoSL4SxQCegLWYc7MEcC92LcALMP1mVYmRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001020; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=PwVpBOofqptocG/L30jQrc2VKaU2be13ULXRMtZdyFQ=; b=I3Ad92WreHY5UsITcr2suGKZbJ7Ln7abz0Fk7Rxefb4YYUYTwztZwEHGM314+7ROdLGewJikgP2bQGxOkqrtIfqXJWQKatm1jkYYgsXvi/KB/pG/N1wTw8dMju5MUpnT+rYtB4q/TcwhxS6DK4iOPgtXC9BcwEAGKy5ZzOY1PIs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45906+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001020165463.39334690037924; Fri, 16 Aug 2019 17:17:00 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:58 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319329" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:56 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 28/37] CoffeelakeSiliconPkg/SystemAgent: Add modules Date: Fri, 16 Aug 2019 17:15:54 -0700 Message-Id: <20190817001603.30632-29-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001019; bh=B13R2hoabEuMl1gEEhF6QI8WGSU65Tk7VVvibnsCBZ0=; h=Cc:Date:From:Reply-To:Subject:To; b=QJDQvf/DasO+EXUjXF7Dtfv2CVuGbbN/V/HrYcx4xb/KMkMkFC/U0nzzlX+feU8UNkY DFSWb6yqCZdWfYwUr9CJC3Kc5oDiBzwCTaoZ5U14MW5+oBlDYriDWWlvXALNdSCNGW94K 2hDfSFVUMOIuu7j/Te0ylbHUo5SAbr7sa3M= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 * SaAcpiTables - SA (DMAR) ACPI tables. * SaSsdt - SA SSDT ACPI tables. * SaInitDxe - Generic DXE SA initialization. * SmmAccess - Produces an instance of EFI_SMM_ACCESS2_PROTOCOL. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaAcpiTables.inf= | 50 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.in= f | 49 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf = | 116 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccess.inf= | 48 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.h = | 25 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeela= ke/MrcCommonTypes.h | 230 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeela= ke/MrcInterface.h | 1567 ++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeela= ke/MrcRmtData.h | 203 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeela= ke/MrcSpdData.h | 1167 ++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Coffeela= ke/MrcTypes.h | 237 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/MrcInter= face.h | 15 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsInit.h = | 50 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegionInit.= h | 193 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PciExpressInit.h= | 91 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PcieComplex.h = | 23 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h = | 71 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h = | 139 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SwitchableGraphi= csInit.h | 17 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.h = | 53 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccessDriv= er.h | 162 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsInit.c = | 157 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegionInit.= c | 570 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PciExpressInit.c= | 171 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PcieComplex.c = | 171 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c = | 496 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c = | 179 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c = | 122 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.c = | 717 +++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAccessDriv= er.c | 356 +++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.aslc = | 250 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/HostBus.asl = | 794 ++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx.asl = | 1666 ++++++++++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxCommo= n.asl | 472 ++++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxDsm.a= sl | 369 +++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpGbd= a.asl | 129 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpRn.= asl | 296 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/IgfxOpSbc= b.asl | 262 +++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Ipu.asl = | 87 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl = | 31 + Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaNvs.asl= | 147 ++ Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.as= l | 22 + 41 files changed, 11970 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaAc= piTables.inf b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Sa= AcpiTables.inf new file mode 100644 index 0000000000..56ddc2957f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaAcpiTable= s.inf @@ -0,0 +1,50 @@ +## @file +# Component description file for the ACPI tables +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010005 +BASE_NAME =3D SaAcpiTables +FILE_GUID =3D 3c0ed5e2-91ea-4b94-820d-9daf9a3bb4a2 +MODULE_TYPE =3D USER_DEFINED +VERSION_STRING =3D 1.0 + +[Sources] + Dmar/Dmar.aslc + Dmar/Dmar.h + + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + +##########################################################################= ###### +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +##########################################################################= ###### +[Pcd] + +[Protocols] + +[PPIs] + +[Guids] + +[Depex] + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/SaSsdt.inf b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/S= aSsdt/SaSsdt.inf new file mode 100644 index 0000000000..3588565aac --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSs= dt.inf @@ -0,0 +1,49 @@ +## @file +# Component description file for the ACPI tables +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010005 +BASE_NAME =3D SaSsdt +FILE_GUID =3D ca89914d-2317-452e-b245-36c6fb77a9c6 +MODULE_TYPE =3D USER_DEFINED +VERSION_STRING =3D 1.0 + +[Sources] + SaSsdt.asl + + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +##########################################################################= ###### +# +# Library Class Section - list of Library Classes that are required for +# this module. +# +##########################################################################= ###### + +[LibraryClasses] + +##########################################################################= ###### +# +# Protocol C Name Section - list of Protocol and Protocol Notify C Names +# that this module uses or produces. +# +##########################################################################= ###### +[Pcd] + +[Protocols] + +[PPIs] + +[Guids] + +[Depex] + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIn= itDxe.inf b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIni= tDxe.inf new file mode 100644 index 0000000000..9937fc60e5 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.i= nf @@ -0,0 +1,116 @@ +## @file +# Component description file for SystemAgent Initialization driver +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D SaInitDxe +FILE_GUID =3D DE23ACEE-CF55-4fb6-AA77-984AB53DE811 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_DRIVER +ENTRY_POINT =3D SaInitEntryPointDxe +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[LibraryClasses] +UefiDriverEntryPoint +UefiLib +UefiBootServicesTableLib +DxeServicesTableLib +DebugLib +TimerLib +PciCf8Lib +PciSegmentLib +BaseMemoryLib +MemoryAllocationLib +CpuPlatformLib +IoLib +S3BootScriptLib +PmcLib +PchCycleDecodingLib +PchInfoLib +GpioLib +ConfigBlockLib +SaPlatformLib +PchPcieRpLib + +[Packages] +MdePkg/MdePkg.dec +UefiCpuPkg/UefiCpuPkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec +CoffeelakeSiliconPkg/SiPkg.dec +PcAtChipsetPkg/PcAtChipsetPkg.dec + +[Pcd] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision +gSiPkgTokenSpaceGuid.PcdMchBaseAddress +gPcAtChipsetPkgTokenSpaceGuid.PcdIoApicBaseAddress + +[Sources] +SaInitDxe.h +SaInitDxe.c +SaInit.h +SaInit.c +VTd.c +VTd.h +IgdOpRegionInit.h +IgdOpRegionInit.c +GraphicsInit.h +GraphicsInit.c +PciExpressInit.h +PciExpressInit.c +PcieComplex.c +PcieComplex.h +SaAcpi.c + +[Protocols] +gEfiAcpiTableProtocolGuid ## CONSUMES +gSaNvsAreaProtocolGuid ## PRODUCES +gSaPolicyProtocolGuid ## CONSUMES +gEfiCpuArchProtocolGuid ## CONSUMES +gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES +gEfiPciRootBridgeIoProtocolGuid ## CONSUMES +gEfiPciIoProtocolGuid ## CONSUMES +gIgdOpRegionProtocolGuid ## PRODUCES +gEfiFirmwareVolume2ProtocolGuid ## CONSUMES +gEfiLegacyBiosProtocolGuid ## CONSUMES +gGopComponentName2ProtocolGuid ## CONSUMES +gSaIotrapSmiProtocolGuid ## CONSUMES + +[Guids] +gSaConfigHobGuid +gSgAcpiTablePchStorageGuid +gSaAcpiTableStorageGuid +gSgAcpiTableStorageGuid +gSaSsdtAcpiTableStorageGuid +gPegSsdtAcpiTableStorageGuid +gEfiEndOfDxeEventGroupGuid +gSiConfigHobGuid ## CONSUMES +gMiscDxeConfigGuid +gGraphicsDxeConfigGuid +gMemoryDxeConfigGuid +gPcieDxeConfigGuid +gVbiosDxeConfigGuid +gPchInfoHobGuid + +[Depex] +gEfiAcpiTableProtocolGuid AND +gEfiFirmwareVolume2ProtocolGuid AND +gSaPolicyProtocolGuid AND +gEfiPciRootBridgeIoProtocolGuid AND +gEfiPciHostBridgeResourceAllocationProtocolGuid AND # This is to ensure th= at PCI MMIO resource has been prepared and available for this driver to all= ocate. +gEfiHiiDatabaseProtocolGuid + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/S= mmAccess.inf b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe= /SmmAccess.inf new file mode 100644 index 0000000000..9356781c9e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAcces= s.inf @@ -0,0 +1,48 @@ +## @file +# Component description file for the SmmAccess module +# +# {1323C7F8-DAD5-4126-A54B-7A05FBF41515} +# +# Copyright (c) 2017 - 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D SmmAccess +FILE_GUID =3D 1323C7F8-DAD5-4126-A54B-7A05FBF41515 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D DXE_DRIVER +ENTRY_POINT =3D SmmAccessDriverEntryPoint + + +[LibraryClasses] +UefiDriverEntryPoint +BaseLib +BaseMemoryLib +DebugLib +HobLib +PciLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec + + +[Sources] +SmmAccessDriver.h +SmmAccessDriver.c + + +[Protocols] +gEfiSmmAccess2ProtocolGuid ## PRODUCES + + +[Guids] +gEfiSmmPeiSmramMemoryReserveGuid + + +[Depex] +TRUE diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Dmar= /Dmar.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dm= ar.h new file mode 100644 index 0000000000..4339256bba --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.h @@ -0,0 +1,25 @@ +/** @file + This file describes the contents of the ACPI DMA address Remapping + Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_DMAR_H_ +#define _SA_DMAR_H_ + +/// +/// Include standard ACPI table definitions +/// +#include +#include + +#pragma pack(1) + +#define EFI_ACPI_DMAR_OEM_TABLE_ID 0x20202020324B4445 ///< "EDK2 " +#define EFI_ACPI_DMAR_OEM_CREATOR_ID 0x4C544E49 ///< "INTL" +#pragma pack() + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Incl= ude/Coffeelake/MrcCommonTypes.h b/Silicon/Intel/CoffeelakeSiliconPkg/System= Agent/MemoryInit/Include/Coffeelake/MrcCommonTypes.h new file mode 100644 index 0000000000..54cb69066d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Cof= feelake/MrcCommonTypes.h @@ -0,0 +1,230 @@ +/** @file + This file contains the definitions common to the MRC API and other APIs. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MrcCommonTypes_h_ +#define _MrcCommonTypes_h_ + +#define INT32_MIN (0x80000000) +#ifndef INT32_MAX //INT32_MAX->Already defined +#define INT32_MAX (0x7FFFFFFF) +#endif +#define INT16_MIN (0x8000) +#define INT16_MAX (0x7FFF) + +/// +/// System boot mode. +/// +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration m= aximum value. + MrcBootModeDelim =3D INT32_MAX ///< This value ensures the en= um size is consistent on both sides of the PPI. +} MrcBootMode; + +/// +/// DIMM memory package +/// This enum matches SPD Module Type - SPD byte 3, bits [3:0] +/// Note that DDR4 have different encoding for some module types +/// +typedef enum { + RDimmMemoryPackage =3D 1, + UDimmMemoryPackage =3D 2, + SoDimmMemoryPackage =3D 3, + MicroDimmMemoryPackageDdr3 =3D 4, + LrDimmMemoryPackageDdr4 =3D 4, + MiniRDimmMemoryPackage =3D 5, + MiniUDimmMemoryPackage =3D 6, + MiniCDimmMemoryPackage =3D 7, + LpDimmMemoryPackage =3D 7, + SoUDimmEccMemoryPackageDdr3 =3D 8, + SoRDimmEccMemoryPackageDdr4 =3D 8, + SoRDimmEccMemoryPackageDdr3 =3D 9, + SoUDimmEccMemoryPackageDdr4 =3D 9, + SoCDimmEccMemoryPackage =3D 10, + LrDimmMemoryPackage =3D 11, + SoDimm16bMemoryPackage =3D 12, + SoDimm32bMemoryPackage =3D 13, + NonDimmMemoryPackage =3D 14, + MemoryPackageMax, ///< MEMORY_PACKAGE enumeration = maximum value. + MemoryPackageDelim =3D INT32_MAX ///< This value ensures the en= um size is consistent on both sides of the PPI. +} MEMORY_PACKAGE; + +/// +/// Memory training I/O levels. +/// +typedef enum { + DdrLevel =3D 0, ///< Refers to frontside of DI= MM + LrbufLevel =3D 1, ///< Refers to data level at b= ackside of LRDIMM or AEP buffer + RegALevel =3D 2, ///< Refers to cmd level at ba= ckside of register - side A + RegBLevel =3D 3, ///< Refers to cmd level at ba= ckside of register - side B + GsmLtMax, ///< GSM_LT enumeration maximum = value. + GsmLtDelim =3D INT32_MAX ///< This value ensures the en= um size is consistent on both sides of the PPI. +} GSM_LT; + +/// +/// Memory training margin group selectors. +/// +typedef enum { + RecEnDelay =3D 0, ///< Linear delay (PI ticks), = where the positive increment moves the RCVEN sampling window later in time = relative to the RX DQS strobes. + RxDqsDelay =3D 1, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQS strobe later in time relative= to the RX DQ signal (i.e. toward the hold side of the eye). + RxDqDelay =3D 2, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQ byte/nibble/bitlane later in t= ime relative to the RX DQS signal (i.e.closing the gap between DQ and DQS i= n the setup side of the eye). + RxDqsPDelay =3D 3, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQS strobe for "even" chunks late= r in time relative to the RX DQ signal. Even chunks are 0, 2, 4, 6 within t= he 0 to 7 chunks of an 8 burst length cacheline, for example. + RxDqsNDelay =3D 4, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQS strobe for "odd" chunks later= in time relative to the RX DQ signal. Odd chunks are 1, 3, 5, 7 within the= 0 to 7 chunks of an 8 burst length cacheline, for example. + RxVref =3D 5, ///< Linear increment (Vref ti= cks), where the positive increment moves the byte/nibble/bitlane RX Vref to= a higher voltage. + RxEq =3D 6, ///< RX CTLE setting indicatin= g a set of possible resistances, capacitance, current steering, etc. values= , which may be a different set of values per product. The setting combinati= ons are indexed by integer values. + RxDqBitDelay =3D 7, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQ bitlane later in time relative= to the RX DQS signal (i.e.closing the gap between DQ and DQS in the setup = side of the eye). + RxVoc =3D 8, ///< Monotonic increment (Sens= e Amp setting), where the positive increment moves the byte/nibble/bitlane'= s effective switching point to a lower Vref value. + RxOdt =3D 9, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + RxOdtUp =3D 10, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + RxOdtDn =3D 11, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + DramDrvStr =3D 12, ///< Drive strength setting re= sistance setting within a set of possible resistances (or currents), which = may be a different set of values per product. Indexed by integer values. + McOdtDelay =3D 13, ///< + McOdtDuration =3D 14, ///< + SenseAmpDelay =3D 15, ///< This may be used to indic= ate CmdToDiffAmpEn for SoC's. + SenseAmpDuration =3D 16, ///< + RoundTripDelay =3D 17, ///< This may be used to indic= ate CmdToRdDataValid for SoC's. + RxDqsBitDelay =3D 18, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQS within the bitlane later in t= ime relative to the RX DQ signal (i.e.closing the gap between DQ and DQS in= the hold side of the eye). + RxDqDqsDelay =3D 19, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQS per strobe later in time rela= tive to the RX DQ signal (i.e. closing the gap between DQS and DQ in the ho= ld side of the eye. The difference between this parameter and RxDqsDelay is= that both the DQ and DQS timings may be moved in order to increase the tot= al range of DQDQS timings. + WrLvlDelay =3D 20, ///< Linear delay (PI ticks), = where the positive increment moves both the TX DQS and TX DQ signals later = in time relative to all other bus signals. + TxDqsDelay =3D 21, ///< Linear delay (PI ticks), = where the positive increment moves the TX DQS strobe later in time relative= to all other bus signals. + TxDqDelay =3D 22, ///< Linear delay (PI ticks), = where the positive increment moves the TX DQ byte/nibble/bitlane later in t= ime relative to all other bus signals. + TxVref =3D 23, ///< Linear increment (Vref ti= cks), where the positive increment moves the byte/nibble/bitlane TX Vref to= a higher voltage. (Assuming this will abstract away from the range specifi= cs for DDR4, for example.) + TxEq =3D 24, ///< TX EQ setting indicating = a set of possible equalization levels, which may be a different set of valu= es per product. The setting combinations are indexed by integer values. + TxDqBitDelay =3D 25, ///< Linear delay (PI ticks), = where the positive increment moves the TX DQ bitlane later in time relative= to all other bus signals. + TxRon =3D 26, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + TxRonUp =3D 27, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + TxRonDn =3D 28, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + TxSlewRate =3D 29, ///< Monotonic increment, wher= e the positive increment moves the byte/nibble/bitlane's effective slew rat= e to a higher slope. + TxImode =3D 30, ///< TX I-Mode Boost setting i= ndicating a set of possible current boost levels, which may be a different = set of values per product. The setting combinations are indexed by integer = values. + WrOdt =3D 31, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + NomOdt =3D 32, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + ParkOdt =3D 33, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + TxTco =3D 34, ///< + RxCtleR =3D 36, ///< + RxCtleC =3D 37, ///< + RxDqsPBitDelay =3D 38, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQS bitlane timing for "even" chu= nks later in time relative to the RX DQ bitlane signal. Even chunks are 0, = 2, 4, 6 within the 0 to 7 chunks of an 8 burst length cacheline, for exampl= e. + RxDqsNBitDelay =3D 39, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQS bitlane timing for "odd" chun= ks later in time relative to the RX DQ bitlane signal. Odd chunks are 1, 3,= 5, 7 within the 0 to 7 chunks of an 8 burst length cacheline, for example. + CmdAll =3D 40, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CMD_ALL cate= gory later in time relative to all other signals on the bus. + CmdGrp0 =3D 41, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CMD_GRP0 cat= egory later in time relative to all other signals on the bus. + CmdGrp1 =3D 42, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CMD_GRP1 cat= egory later in time relative to all other signals on the bus. + CmdGrp2 =3D 43, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CMD_GRP2 cat= egory later in time relative to all other signals on the bus. + CtlAll =3D 44, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CTL_ALL cate= gory later in time relative to all other signals on the bus. + CtlGrp0 =3D 45, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CTL_GRP0 cat= egory later in time relative to all other signals on the bus. + CtlGrp1 =3D 46, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CTL_GRP1 cat= egory later in time relative to all other signals on the bus. + CtlGrp2 =3D 47, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CTL_GRP2 cat= egory later in time relative to all other signals on the bus. + CtlGrp3 =3D 48, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CTL_GRP3 cat= egory later in time relative to all other signals on the bus. + CtlGrp4 =3D 49, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CTL_GRP4 cat= egory later in time relative to all other signals on the bus. + CtlGrp5 =3D 50, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CTL_GRP5 cat= egory later in time relative to all other signals on the bus. + CmdCtlAll =3D 51, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CMD_CTL_ALL = category later in time relative to all other signals on the bus. + CkAll =3D 52, ///< Linear delay (PI ticks), = where the positive increment moves all signals assigned to the CK_ALL categ= ory later in time relative to all other signals on the bus. + CmdVref =3D 53, ///< Linear increment (Vref ti= cks), where the positive increment moves the CMD Vref to a higher voltage. + AlertVref =3D 54, ///< Linear increment (Vref ti= cks), where the positive increment moves the ALERT Vref to a higher voltage. + CmdRon =3D 55, ///< Resistance setting within= a set of possible resistances, which may be a different set of values per = product. Indexed by integer values. + + EridDelay =3D 60, ///< Linear delay (PI ticks), = where the positive increment moves the ERID signals later in time relative = to the internal sampling clock (i.e.closing the gap between ERID and intern= al sampling clock in the setup side of the eye). This group is applicable f= or DDRT DIMMs. + EridVref =3D 61, ///< Linear increment (Vref ti= cks), where the positive increment moves the ERID Vref to a higher voltage.= This group is applicable for DDRT DIMMs. + ErrorVref =3D 62, ///< Linear increment (Vref ti= cks), where the positive increment moves the ERROR Vref to a higher voltage= . This group is applicable for DDRT DIMMs. + ReqVref =3D 63, ///< Linear increment (Vref ti= cks), where the positive increment moves the REQ Vref to a higher voltage. = This group is applicable for DDRT DIMMs. + RecEnOffset =3D 64, ///< Linear delay (PI ticks), = where the positive increment moves the RCVEN sampling window later in time = relative to the RX DQS strobes. + RxDqsOffset =3D 65, ///< Linear delay (PI ticks), = where the positive increment moves the RX DQS strobe later in time relative= to the RX DQ signal (i.e. toward the hold side of the eye). + RxVrefOffset =3D 66, ///< Linear increment (Vref ti= cks), where the positive increment moves the byte/nibble/bitlane RX Vref to= a higher voltage. + TxDqsOffset =3D 67, ///< Linear delay (PI ticks), = where the positive increment moves the TX DQS strobe later in time relative= to all other bus signals. + TxDqOffset =3D 68, ///< Linear delay (PI ticks), = where the positive increment moves the TX DQ byte/nibble/bitlane later in t= ime relative to all other bus signals. + GsmGtMax, ///< SSA_GSM_GT enumeration maxi= mum value. + GsmGtDelim =3D INT32_MAX ///< This value ensures the en= um size is consistent on both sides of the PPI. +} GSM_GT; + +typedef enum { + SigRasN =3D 0, + SigCasN =3D 1, + SigWeN =3D 2, + SigBa0 =3D 3, + SigBa1 =3D 4, + SigBa2 =3D 5, + SigA0 =3D 6, + SigA1 =3D 7, + SigA2 =3D 8, + SigA3 =3D 9, + SigA4 =3D 10, + SigA5 =3D 11, + SigA6 =3D 12, + SigA7 =3D 13, + SigA8 =3D 14, + SigA9 =3D 15, + SigA10 =3D 16, + SigA11 =3D 17, + SigA12 =3D 18, + SigA13 =3D 19, + SigA14 =3D 20, + SigA15 =3D 21, + SigA16 =3D 22, + SigA17 =3D 23, + SigCs0N =3D 24, + SigCs1N =3D 25, + SigCs2N =3D 26, + SigCs3N =3D 27, + SigCs4N =3D 28, + SigCs5N =3D 29, + SigCs6N =3D 30, + SigCs7N =3D 31, + SigCs8N =3D 32, + SigCs9N =3D 33, + SigCke0 =3D 34, + SigCke1 =3D 35, + SigCke2 =3D 36, + SigCke3 =3D 37, + SigCke4 =3D 38, + SigCke5 =3D 39, + SigOdt0 =3D 40, //could also be used for CA-ODT for LP4 + SigOdt1 =3D 41, //could also be used for CA-ODT for LP4 + SigOdt2 =3D 42, + SigOdt3 =3D 43, + SigOdt4 =3D 44, + SigOdt5 =3D 45, + SigPar =3D 46, + SigAlertN =3D 47, + SigBg0 =3D 48, + SigBg1 =3D 49, + SigActN =3D 50, + SigCid0 =3D 51, + SigCid1 =3D 52, + SigCid2 =3D 53, + SigCk0 =3D 54, + SigCk1 =3D 55, + SigCk2 =3D 56, + SigCk3 =3D 57, + SigCk4 =3D 58, + SigCk5 =3D 59, + SigGnt0 =3D 60, + SigGnt1 =3D 61, + SigErid00 =3D 62, + SigErid01 =3D 63, + SigErid10 =3D 64, + SigErid11 =3D 65, + SigErr0 =3D 66, + SigErr1 =3D 67, + SigCa00 =3D 68, // First instantiation of the CA bus for a given ch= annel + SigCa01 =3D 69, + SigCa02 =3D 70, + SigCa03 =3D 71, + SigCa04 =3D 72, + SigCa05 =3D 73, + SigCa10 =3D 74, // Second instantiation of the CA bus for a given c= hannel + SigCa11 =3D 75, + SigCa12 =3D 76, + SigCa13 =3D 77, + SigCa14 =3D 78, + SigCa15 =3D 79, + GsmCsnMax, + GsmCsnDelim =3D INT32_MAX +} GSM_CSN; + + +#endif // _MrcCommonTypes_h_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Incl= ude/Coffeelake/MrcInterface.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAg= ent/MemoryInit/Include/Coffeelake/MrcInterface.h new file mode 100644 index 0000000000..635906cc2b --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Cof= feelake/MrcInterface.h @@ -0,0 +1,1567 @@ +/** @file + This file includes all the data structures that the MRC considers "globa= l data". + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MrcInterface_h_ +#define _MrcInterface_h_ + +#define MAX_CPU_SOCKETS (1) ///< The maximum number of CPUs= per system. +#define MAX_CONTROLLERS (1) ///< The maximum number of memo= ry controllers per CPU socket. +#define MAX_CHANNEL (2) ///< The maximum number of chan= nels per memory controller. +#define MAX_DIMMS_IN_CHANNEL (2) ///< The maximum number of DIMM= s per channel. +#define MAX_RANK_IN_DIMM (2) ///< The maximum number of rank= s per DIMM. +#define MAX_RANK_IN_CHANNEL (MAX_DIMMS_IN_CHANNEL * MAX_RANK_IN_DIMM)= ///< The maximum number of ranks per channel. +#define MAX_SDRAM_IN_DIMM (9) ///< The maximum number of SDRA= Ms per DIMM when ECC is enabled. +#define MAX_MR_IN_DIMM (7) ///< Maximum number of mode reg= isters in a DIMM. +#define MAX_DEVICES_IN_DDR4 (8) ///< The maximum number of SDRA= Ms per DDR4 DIMM. +#define MAX_BITS (8) ///< BITS per byte. +#define MAX_STROBE (18) ///< Number of strobe groups. +#define MAX_DQ (72) ///< Number of Dq bits used by = the rank. +#define CHAR_BITS (8) ///< Number of bits in a char. +#define PSMI_SIZE_MB (64) ///< Define the max size of PSM= I needed in MB +#define BCLK_DEFAULT (100 * 1000 * 1000) ///< BCLK default val= ue, in Hertz. +#define MAX_COMMAND_GROUPS (2) +#define MAX_EDGES (2) ///< Maximum number of edges. +#define SUPPORT_DDR3 SUPPORT ///< SUPPORT means that DDR3 is= supported by the MRC. +#define ULT_SUPPORT_LPDDR3 SUPPORT ///< SUPPORT means that LPDDR3 = is supported by the MRC. +#define TRAD_SUPPORT_LPDDR3 /*UN*/SUPPORT ///< SUPPORT means that LPD= DR3 is supported by the MRC. +#define BDW_SUPPORT_LPDDR3 SUPPORT ///< SUPPORT means that LPDDR3 = is supported by the MRC. +#define JEDEC_SUPPORT_LPDDR SUPPORT ///< SUPPORT means that JEDEC S= PD Spec for LPDDR3 is supported by the MRC. +#define SUPPORT_DDR4 SUPPORT ///< SUPPORT means that DDR4 is= supported by the MRC. +#define SUPPORT_LPDDR3 (ULT_SUPPORT_LPDDR3 || TRAD_SUPPORT_LPDDR= 3 || BDW_SUPPORT_LPDDR3 || JEDEC_SUPPORT_LPDDR) +#define MRC_ALL_DDR_SUPPORTED ((SUPPORT_DDR4 =3D=3D SUPPORT) && ((SUPPO= RT_DDR3 =3D=3D SUPPORT) && (SUPPORT_LPDDR3 =3D=3D SUPPORT))) +#define MRC_DDR3_LPDDR_SUPPORTED ((SUPPORT_DDR3 =3D=3D SUPPORT) || (SUPPOR= T_LPDDR3 =3D=3D SUPPORT)) +#define SPD3_MANUF_START 117 ///< The starting point for the= SPD manufacturing data. +#define SPD3_MANUF_END 127 ///< The ending point for the S= PD manufacturing data. +#if (SUPPORT_DDR4 =3D=3D SUPPORT) +#define SPD4_MANUF_START 320 ///< The starting point for the= SPD manufacturing data. +#define SPD4_MANUF_END 328 ///< The ending point for the S= PD manufacturing data. +#endif +#if (JEDEC_SUPPORT_LPDDR =3D=3D SUPPORT) +#define SPDLP_MANUF_START 320 ///< The starting point for the= SPD manufacturing data. +#define SPDLP_MANUF_END 328 ///< The ending point for the S= PD manufacturing data. +#endif +#include "MrcSpdData.h" +#include "MrcRmtData.h" +#include "MrcCommonTypes.h" +#pragma pack (push, 1) + + +/// +//////////////////////////////////////////////////////////////////////////= //////////// +/// OEM platform routines and types = // +//////////////////////////////////////////////////////////////////////////= //////////// +/// +/// define the oem check points the OEM can define more point and locate t= hem in the code. +/// +typedef enum { + OemFastBootPermitted, ///< before fast boot. + OemRestoreNonTraining, + OemPrintInputParameters, ///< before printing input parameters + OemSpdProcessingRun, ///< before spd processing code + OemSetOverridePreSpd, ///< before set overrides pre spd + OemSetOverride, ///< before set overrides + OemMcCapability, ///< before MC capability + OemMcInitRun, ///< before mc init code + OemMcMemoryMap, ///< before memory map + OemMcResetRun, ///< before jedec reset + OemPreTraining, ///< before the training. + OemMcTrainingRun, ///< before training code + OemEarlyCommandTraining, ///< before Early Command training + OemJedecInitLpddr3, ///< before Jedec Init Lpddr3 + OemSenseAmpTraining, ///< before Sense Amp Training + OemReadMprTraining, ///< before Read MPR Training + OemReceiveEnable, ///< before Read Leveling + OemJedecWriteLeveling, ///< before Jedec Write Leveling + OemLpddrLatencySetB, ///< before LPDDR Latency Set B + OemWriteDqDqs, ///< before Write Timing Centering + OemWriteVoltage, ///< before Write Voltage Centering + OemEarlyWriteDqDqs2D, ///< before Early Write Timing Centering 2D + OemEarlyWrDsEq, ///< before Early Write Drive Strength / Equa= lization + OemEarlyReadDqDqs2D, ///< before Early Read Timing Centering 2D + OemEarlyReadMprDqDqs2D, ///< before Early MPR Read Timing Centering 2D + OemReadDqDqs, ///< before Read Timing Centering + OemDdr4Map, ///< before DDR4 PDA Mapping + OemDimmRonTraining, ///< before DIMM Ron Training + OemDimmODTTraining, ///< before DIMM ODT Training + OemWriteDriveStrengthEq, ///< before Write Drive Strength/Equalization= 2D Training + OemWriteDriveUpDn, ///< before Write Drive Strength Up/Dn 2D Tra= ining + OemWriteSlewRate, ///< before Write Slew Rate Training + OemReadODTTraining, ///< before Read ODT algorithm. + OemReadEQTraining, ///< before Read Equalization Training + OemReadAmplifierPower, ///< before Read Amplifier Power + OemOptimizeComp, ///< before Comp Optimization Training + OemPowerSavingMeter, ///< before PowerSavingMeter step + OemWriteDqDqs2D, ///< before Write Timing Centering 2D + OemReadDqDqs2D, ///< before Read Timing Centering 2D + OemCmdVoltCenterPreLct, ///< before Command Voltage Centering that ru= ns pre-LCT + OemCmdSlewRate, ///< before CMD Slew Rate + OemCmdVoltCentering, ///< before Command Voltage Centering + OemCmdDriveStrengthEq, ///< before Command Drive Strength Equalizati= on + OemWriteVoltCentering2D, ///< before Write Voltage Centering 2D + OemReadVoltCentering2D, ///< before Read Voltage Centering 2D + OemLateCommandTraining, ///< before Late Command training + OemCmdNormalization, ///< before CMD Normalization + OemRoundTripLatency, ///< before Round Trip Latency Traiing + OemTurnAroundTimes, ///< before Turn Aorund Times. + OemRcvEnCentering1D, ///< before Receive Enable Centring + OemSaveMCValues, ///< before saving memory controller values + OemRmt, ///< before RMT crosser tool. + OemMemTest, ///< before Memory testing + OemRestoreTraining, ///< before Restoring Training Values + OemJedecResetDdr4Fast, ///< before JEDEC reset for DDR4 in Fast flow + OemSelfRefreshExit, ///< before Self Refresh Exit + OemNormalMode, ///< before Normal Mode on non-cold boots. + OemThermalConfig, ///< set Thermal config values. + OemTxtAliasCheck, ///< before TxT Alias Check Call. + OemAliasCheck, ///< before alias checking on cold boots. + OemHwMemInit, + + OemPostTraining, ///< after the training. + OemForceOltm, ///< before MrcForceOltm + OemMrcActivate, ///< before MrcActivate call. + OemMrcRhPrevention, ///< before MrcRhPrevention + OemSaGvSwitch, ///< before SA GV switch + OemEngPerfGain, ///< before Energy Performance Gain. + OemMrcDone, ///< call to MrcOemCheckPoint when MRC was do= ne. + OemFrequencySet, ///< do operation before frequency set. + OemFrequencySetDone, ///< do operation after frequency set. + OemStartMemoryConfiguration, + OemBeforeNormalMode, ///< call to MrcOemCheckPoint before normal m= ode is enalbed + OemAfterNormalMode, ///< call to MrcOemCheckPoint after normal mo= de is enalbed + OemMrcFillBdat, + OemRetrainMarginCheck, + OemRmtPerBit, ///< before Rank Margin Tool Per-Bit. + OemUpdateSaveMCValues, ///< before Updating memory controller values. + /// + ///*********************************************************************= ************ + /// + OemNumOfCommands ///< Should always be last in the list! +} MrcOemStatusCommand; + +typedef UINT8 MrcIteration; ///< Mrc invocation sequence number, start wit= h 0 and increment by one each time MRC library is called. +#define MRC_ITERATION_MAX ((1 << ((sizeof (MrcIteration) * 8) - 1)) + ((1 = << ((sizeof (MrcIteration) * 8) - 1)) - 1)) + +#define MAX_RCOMP (3) +#define MAX_RCOMP_TARGETS (5) + +/// +/// Thermal Options +/// +typedef struct { + UINT8 RaplLim2WindX; ///< Offset 110= - Power Limit 2 Time Window X value: 0=3DMinimal, 3=3DMaximum, 1=3DDef= ault + UINT8 RaplLim2WindY; ///< Offset 111= - Power Limit 2 Time Window Y value: 0=3DMinimal, 3=3DMaximum, 1=3DDef= ault + UINT8 RaplLim1WindX; ///< Offset 112= - Power Limit 1 Time Window X value: 0=3DMinimal, 3=3DMaximum + UINT8 RaplLim1WindY; ///< Offset 113= - Power Limit 1 Time Window Y value: 0=3DMinimal, 31=3DMaximum + UINT16 RaplLim2Pwr; ///< Offset 114= - Power Limit 2: 0=3DMinimal, 16383=3DMaximum, 222=3DDefault + UINT16 RaplLim1Pwr; ///< Offset 116= - Power Limit 1: 0=3DMinimal, 16383=3DMaximum + UINT8 WarmThreshold[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; ///< Offset 118= - Warm Threshold (Channel 0, Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotThreshold[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; ///< Offset 122= - Hot Threshold (Channel 0, Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 WarmBudget[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; ///< Offset 126= - Warm Budget (Channel 0, Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 HotBudget[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; ///< Offset 130= - Hot Budget (Channel 0, Dimm 0): 0=3DMinimal, 255=3DMaximum + UINT8 IdleEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + UINT8 PdEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + UINT8 ActEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + UINT8 RdEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; + UINT8 WrEnergy[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; +} ThermalMngmtEn; + + +typedef struct { + UINT8 GdxcEnable; ///< GDXC MOT enable + UINT8 GdxcIotSize; ///< IOT size in multiples of 8MEG + UINT8 GdxcMotSize; ///< MOT size in multiples of 8MEG +} MrcGdxc; + +typedef struct { + UINT32 ECT : 1; ///< BIT0 - Early Command Training + UINT32 SOT : 1; ///< BIT1 - Sense Amp Offset Training + UINT32 ERDMPRTC2D : 1; ///< BIT2 - Early ReadMPR Timing Centering 2D + UINT32 RDMPRT : 1; ///< BIT3 - Read MPR Training + UINT32 RCVET : 1; ///< BIT4 - Read Leveling Training (RcvEn) + UINT32 JWRL : 1; ///< BIT5 - Jedec Write Leveling + UINT32 EWRTC2D : 1; ///< BIT6 - Early Write Time Centering 2D + UINT32 ERDTC2D : 1; ///< BIT7 - Early Read Time Centering 2D + UINT32 WRTC1D : 1; ///< BIT8 - Write Timing Centering 1D + UINT32 WRVC1D : 1; ///< BIT9 - Write Voltage Centering 1D + UINT32 RDTC1D : 1; ///< BIT10 - Read Timing Centering 1D + UINT32 DIMMODTT : 1; ///< BIT11 - Dimm ODT Training + UINT32 DIMMRONT : 1; ///< BIT12 - Dimm Ron Training + UINT32 WRDSEQT : 1; ///< BIT13 - Write Drive Strength / Equalization = Training 2D + UINT32 WRSRT : 1; ///< BIT14 - Write Slew Rate Training + UINT32 RDODTT : 1; ///< BIT15 - Read ODT Training + UINT32 RDEQT : 1; ///< BIT16 - Read Equalization Training + UINT32 RDAPT : 1; ///< BIT17 - Read Amplifier Power Training + UINT32 WRTC2D : 1; ///< BIT18 - Write Timing Centering 2D + UINT32 RDTC2D : 1; ///< BIT19 - Read Timing Centering 2D + UINT32 WRVC2D : 1; ///< BIT20 - Write Voltage Centering 2D + UINT32 RDVC2D : 1; ///< BIT21 - Read Voltage Centering 2D + UINT32 CMDVC : 1; ///< BIT22 - Command Voltage Centering + UINT32 LCT : 1; ///< BIT23 - Late Command Training + UINT32 RTL : 1; ///< BIT24 - Round Trip latency + UINT32 TAT : 1; ///< BIT25 - Turn Around Timing + UINT32 RMT : 1; ///< BIT26 - RMT Tool + UINT32 MEMTST : 1; ///< BIT27 - Memory Test + UINT32 ALIASCHK: 1; ///< BIT28 - SPD Alias Check + UINT32 RCVENC1D: 1; ///< BIT29 - Receive Enable Centering 1D + UINT32 RMC : 1; ///< BIT30 - Retrain Margin Check + UINT32 WRDSUDT : 1; ///< BIT31 - Write Drive Strength Up/Dn independe= ntly +} TrainingStepsEn; + +typedef struct { + UINT32 CMDSR : 1; ///< BIT0 - CMD Slew Rate Training + UINT32 CMDDSEQ : 1; ///< BIT1 - CMD Drive Strength and Tx Equalizati= on + UINT32 CMDNORM : 1; ///< BIT2 - CMD Normalization + UINT32 EWRDSEQ : 1; ///< BIT3 - Early DQ Write Drive Strength and Eq= ualization Training + UINT32 TeRsv4 : 1; ///< BIT4 - Reserved + UINT32 TeRsv5 : 1; ///< BIT5 - Reserved + UINT32 TeRsv6 : 1; ///< BIT6 - Reserved + UINT32 RsvdBits :25; +} TrainingStepsEn2; + +/// +/// Defines whether the MRC is executing in full or mini BIOS mode. +/// +typedef enum { + MrcModeFull, ///< Select full BIOS MRC execution. + MrcModeMini, ///< Select mini BIOS MRC execution. + MrcModeMaximum ///< Delimiter. +} MrcMode; + +typedef enum { + MrcTmPower, + MrcTmMargin, + MrcTmMax +} TrainingModeType; + +typedef enum { + LastRxV, + LastRxT, + LastTxV, + LastTxT, + LastRcvEna, + LastWrLevel, + LastCmdT, + LastCmdV, + MAX_RESULT_TYPE +} MrcMarginResult; + +typedef enum { + MSG_LEVEL_NEVER, + MSG_LEVEL_ERROR, + MSG_LEVEL_WARNING, + MSG_LEVEL_NOTE, + MSG_LEVEL_EVENT, + MSG_LEVEL_ALGO, + MSG_LEVEL_MMIO, + MSG_LEVEL_CSV, + MSG_LEVEL_TIME, + MSG_LEVEL_ALL =3D MRC_INT32_MAX +} MrcDebugMsgLevel; + +/// +/// Define the frequencies that may be possible in the memory controller. +/// Note that not all these values may be supported. +/// +#define fNoInit (0) +#define f800 (800) +#define f1000 (1000) +#define f1100 (1100) +#define f1067 (1067) +#define f1200 (1200) +#define f1300 (1300) +#define f1333 (1333) +#define f1400 (1400) +#define f1467 (1467) +#define f1500 (1500) +#define f1600 (1600) +#define f1700 (1700) +#define f1733 (1733) +#define f1800 (1800) +#define f1867 (1867) +#define f1900 (1900) +#define f2000 (2000) +#define f2100 (2100) +#define f2133 (2133) +#define f2200 (2200) +#define f2267 (2267) +#define f2300 (2300) +#define f2400 (2400) +#define f2500 (2500) +#define f2533 (2533) +#define f2600 (2600) +#define f2667 (2667) +#define f2700 (2700) +#define f2800 (2800) +#define f2900 (2900) +#define f2933 (2933) +#define f3000 (3000) +#define f3067 (3067) +#define f3100 (3100) +#define f3200 (3200) +#define f3333 (3333) +#define f3467 (3467) +#define f3600 (3600) +#define f3733 (3733) +#define f3867 (3867) +#define f4000 (4000) +#define f4133 (4133) +#define fInvalid (0x7FFFFFFF) +typedef UINT32 MrcFrequency; + +// +// Max supported frequency in OC mode +// RefClk133: 15*266 + 100 =3D 4133 (using Odd ratio mode) +// RefClk100: 15*200 + 100 =3D 3100 (using Odd ratio mode) +// +#define MAX_FREQ_OC_133 f4133 +#define MAX_FREQ_OC_100 f3100 + +// +// tCK value in femtoseconds for various frequencies +// If Freq is in MHz, then tCK[fs] =3D 10^9 * 1/(Freq/2) +// +#define MRC_DDR_800_TCK_MIN 2500000 +#define MRC_DDR_1000_TCK_MIN 2000000 +#define MRC_DDR_1067_TCK_MIN 1875000 +#define MRC_DDR_1100_TCK_MIN 1818182 +#define MRC_DDR_1200_TCK_MIN 1666667 +#define MRC_DDR_1300_TCK_MIN 1538462 +#define MRC_DDR_1333_TCK_MIN 1500000 +#define MRC_DDR_1400_TCK_MIN 1428571 +#define MRC_DDR_1467_TCK_MIN 1363636 +#define MRC_DDR_1500_TCK_MIN 1333333 +#define MRC_DDR_1600_TCK_MIN 1250000 +#define MRC_DDR_1700_TCK_MIN 1176471 +#define MRC_DDR_1733_TCK_MIN 1153846 +#define MRC_DDR_1800_TCK_MIN 1111111 +#define MRC_DDR_1867_TCK_MIN 1071429 +#define MRC_DDR_1900_TCK_MIN 1052632 +#define MRC_DDR_2000_TCK_MIN 1000000 +#define MRC_DDR_2100_TCK_MIN 952381 +#define MRC_DDR_2133_TCK_MIN 938000 +#define MRC_DDR_2200_TCK_MIN 909091 +#define MRC_DDR_2267_TCK_MIN 882353 +#define MRC_DDR_2300_TCK_MIN 869565 +#define MRC_DDR_2400_TCK_MIN 833333 +#define MRC_DDR_2500_TCK_MIN 800000 +#define MRC_DDR_2533_TCK_MIN 789474 +#define MRC_DDR_2600_TCK_MIN 769231 +#define MRC_DDR_2667_TCK_MIN 750000 +#define MRC_DDR_2700_TCK_MIN 740741 +#define MRC_DDR_2800_TCK_MIN 714286 +#define MRC_DDR_2900_TCK_MIN 689655 +#define MRC_DDR_2933_TCK_MIN 681818 +#define MRC_DDR_3000_TCK_MIN 666667 +#define MRC_DDR_3067_TCK_MIN 652174 +#define MRC_DDR_3100_TCK_MIN 645161 +#define MRC_DDR_3200_TCK_MIN 625000 +#define MRC_DDR_3333_TCK_MIN 600000 +#define MRC_DDR_3467_TCK_MIN 576923 +#define MRC_DDR_3600_TCK_MIN 555556 +#define MRC_DDR_3733_TCK_MIN 535714 +#define MRC_DDR_3867_TCK_MIN 517241 +#define MRC_DDR_4000_TCK_MIN 500000 +#define MRC_DDR_4133_TCK_MIN 483871 + +/// +/// Define the memory nominal voltage (VDD). +/// Note that not all these values may be supported. +/// +typedef enum { + VDD_INVALID, + VDD_1_00 =3D 1000, + VDD_1_05 =3D 1050, + VDD_1_10 =3D 1100, + VDD_1_15 =3D 1150, + VDD_1_20 =3D 1200, + VDD_1_25 =3D 1250, + VDD_1_30 =3D 1300, + VDD_1_35 =3D 1350, + VDD_1_40 =3D 1400, + VDD_1_45 =3D 1450, + VDD_1_50 =3D 1500, + VDD_1_55 =3D 1550, + VDD_1_60 =3D 1600, + VDD_1_65 =3D 1650, + VDD_1_70 =3D 1700, + VDD_1_75 =3D 1750, + VDD_1_80 =3D 1800, + VDD_1_85 =3D 1850, + VDD_1_90 =3D 1900, + VDD_1_95 =3D 1950, + VDD_2_00 =3D 2000, + VDD_2_05 =3D 2050, + VDD_2_10 =3D 2100, + VDD_2_15 =3D 2150, + VDD_2_20 =3D 2200, + VDD_2_25 =3D 2250, + VDD_2_30 =3D 2300, + VDD_2_35 =3D 2350, + VDD_2_40 =3D 2400, + VDD_2_45 =3D 2450, + VDD_2_50 =3D 2500, + VDD_2_55 =3D 2550, + VDD_2_60 =3D 2600, + VDD_2_65 =3D 2650, + VDD_2_70 =3D 2700, + VDD_2_75 =3D 2750, + VDD_2_80 =3D 2800, + VDD_2_85 =3D 2850, + VDD_2_90 =3D 2900, + VDD_2_95 =3D 2950, + VDD_MAXIMUM =3D 0x7FFFFFFF +} MrcVddSelect; + +/// +/// SA GV points +/// +typedef enum { + MrcSaGvPointLow, + MrcSaGvPointHigh, +} MrcSaGvPoint; + +/// +/// SA GV modes +/// Disabled: SA GV Disabled, run all MRC tasks +/// FixedLow: SA GV Disabled, run only MRC tasks marked with MRC_PF_GV_L= OW +/// FixedHigh: SA GV Disabled, run only MRC tasks marked with MRC_PF_GV_H= IGH +/// Enabled: SA GV Enabled +/// +typedef enum { + MrcSaGvDisabled, + MrcSaGvFixedLow, + MrcSaGvFixedHigh, + MrcSaGvEnabled, +} MrcSaGv; + +/// +/// DIMM SPD Security Status +/// +typedef enum { + MrcSpdStatusGood, ///< Memory is in a secure state. + MrcSpdStatusAliased, ///< Memory is aliased. + MrcSpdStatusLast ///< Must be last in the list +} MrcSpdStatus; + +/// +/// Define the virtual channel. +/// +typedef enum { + vcL, ///< Virtual channel L + vcS, ///< Virtual channel S +} MrcVirtualChannel; + +/// +/// Define the board types. +/// +typedef enum { + btCRBMB, ///< 0 - CRB Mobile + btCRBDT, ///< 1 - CRB Desktop + btUser1, ///< 2 - SV Karkom + btUser2, ///< 3 - SV desktop + btUser3, ///< 4 - SV miniDVP + btUser4, ///< 5 - Ult + btCRBEMB, ///< 6 - CRB Embedded + btUpServer, ///< 7 - Up Server + btUnknown, ///< 8 - Unknown + btMaximum ///< Delimiter +} MrcBoardType; + +/// +/// Define the CPU family/model. +/// +typedef enum { + cmCFL_ULX_ULT =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_ULT_ULX, ///< Co= ffeelake ULT/ULX + cmCFL_DT_HALO =3D CPUID_FULL_FAMILY_MODEL_COFFEELAKE_DT_HALO ///< Co= ffeelake DT/Halo +} MrcCpuModel; + +/// +/// Define the CPU Tick/Tock. +/// +typedef enum { + cfCfl =3D 0, ///< Coffeelake + cfMax +} MrcCpuFamily; + +/// +/// Define the CPU stepping number. +/// +typedef enum { + /// + /// Coffeelake ULX/ULT + /// + csKblH0 =3D EnumKblH0, + csCflD0 =3D EnumCflD0, + csCflW0 =3D EnumCflW0, + csCflV0 =3D EnumCflV0, + csCflUlxUltLast =3D csCflV0, + + /// + /// Coffeelake DT/Halo + /// + csCflU0 =3D EnumCflU0, + csCflB0 =3D EnumCflB0, + csCflP0 =3D EnumCflP0, + csCflR0 =3D EnumCflR0, + csCflDtHaloLast =3D csCflR0, +} MrcCpuStepping; + +typedef enum { + CONTROLLER_NOT_PRESENT, ///< There is no controller present in the syste= m. + CONTROLLER_DISABLED, ///< There is a controller present but it is dis= abled. + CONTROLLER_PRESENT, ///< There is a controller present and it is ena= bled. + MAX_CONTROLLER_STATUS ///< Delimiter +} MrcControllerSts; + +typedef enum { + CHANNEL_NOT_PRESENT, ///< There is no channel present on the controll= er. + CHANNEL_DISABLED, ///< There is a channel present but it is disabl= ed. + CHANNEL_PRESENT, ///< There is a channel present and it is enable= d. + MAX_CHANNEL_STATUS ///< Delimiter +} MrcChannelSts; + +typedef enum { + DIMM_ENABLED, ///< DIMM/rank Pair is enabled, presence will be= detected. + DIMM_DISABLED, ///< DIMM/rank Pair is disabled, regardless of p= resence. + DIMM_PRESENT, ///< There is a DIMM present in the slot/rank pa= ir and it will be used. + DIMM_NOT_PRESENT, ///< There is no DIMM present in the slot/rank p= air. + MAX_DIMM_STATUS ///< Delimiter +} MrcDimmSts; + +typedef enum { + STD_PROFILE, ///< Standard DIMM profile select. + USER_PROFILE, ///< User specifies various override values. + XMP_PROFILE1, ///< XMP enthusiast settings select (XMP profile= #1). + XMP_PROFILE2, ///< XMP extreme settings select (XMP profile #2= ). + MAX_PROFILE ///< Delimiter +} MrcProfile; + +#define XMP_PROFILES_ENABLE (0x3) +#define XMP1_PROFILE_ENABLE (0x1) +#define XMP2_PROFILE_ENABLE (0x2) + +typedef enum { + MRC_REF_CLOCK_133, ///< 133MHz reference clock + MRC_REF_CLOCK_100, ///< 100MHz reference clock + MRC_REF_CLOCK_MAXIMUM ///< Delimiter +} MrcRefClkSelect; ///< This value times the MrcClockRatio determin= es the MrcFrequency. + +typedef enum { + MRC_FREQ_INVALID =3D 0, + MRC_FREQ_133 =3D (MRC_BIT0 << MRC_REF_CLOCK_133), // Bit 0 + MRC_FREQ_100 =3D (MRC_BIT0 << MRC_REF_CLOCK_100), // Bit 1 + MRC_FREQ_133_ODD_RATIO =3D (MRC_BIT2 << MRC_REF_CLOCK_133), // Bit 2 + MRC_FREQ_100_ODD_RATIO =3D (MRC_BIT2 << MRC_REF_CLOCK_100), // Bit 3 + MRC_FREQ_MAX // Delimiter +} MrcFreqFlag; + +typedef UINT32 MrcBClkRef; ///< Base clock, in Hertz, Default is 100MHz = or leave at zero for default. + +// +// This encoding matches CFL SC_GS_CFG.DRAM_technology and MAD_INTER_CHANN= EL.DDR_TYPE registers +// +typedef enum { + MRC_DDR_TYPE_DDR4 =3D 0, + MRC_DDR_TYPE_DDR3 =3D 1, + MRC_DDR_TYPE_LPDDR3 =3D 2, + MRC_DDR_TYPE_UNKNOWN =3D 3, + MAX_MRC_DDR_TYPE ///< Delimiter +} MrcDdrType; + +typedef enum { + MrcIterationClock, + MrcIterationCmdN, + MrcIterationCmdS, + MrcIterationCke, + MrcIterationCtl, + MrcIterationCmdV, + MrcIterationMax +} MrcIterationType; + +typedef enum { + UpmLimit, + PowerLimit, + RetrainLimit, + MarginLimitMax +} MRC_MARGIN_LIMIT_TYPE; + + +typedef enum { + HardwareRhp, + Refresh2x +} MrcRhpType; + +typedef enum { + OneIn2To1 =3D 1, + OneIn2To2, + OneIn2To3, + OneIn2To4, + OneIn2To5, + OneIn2To6, + OneIn2To7, + OneIn2To8, + OneIn2To9, + OneIn2To10, + OneIn2To11, + OneIn2To12, + OneIn2To13, + OneIn2To14, + OneIn2To15 +} MrcRhProbType; + +typedef enum { + MRC_POST_CODE, + MRC_POST_CODE_WRITE, + MRC_POST_CODE_READ, + MRC_POST_CODE_MAX +} MrcDebugPostCode; + +typedef struct { + UINT32 MrcData; + UINT32 Stream; + UINT32 Start; + UINT32 End; + UINT32 Current; + int Level; + UINT16 PostCode[MRC_POST_CODE_MAX]; + UINT32 TopStackAddr; ///< Initial stack address. + UINT32 LowestStackAddr; ///< Track the lowest stack address used throug= h MrcPrintfVaList() +} MrcDebug; + +typedef UINT16 MrcPostCode; +typedef UINT8 MrcClockRatio; ///< This value times the MrcRefClkSelect d= etermines the MrcFrequency. +typedef UINT32 MrcGfxDataSize; ///< The size of the stolen graphics data m= emory, in MBytes. +typedef UINT32 MrcGfxGttSize; ///< The size of the graphics translation t= able, in MBytes. + + +/// +/// This data structure contains all the "DDR power saving data" values th= at are considered output by the MRC. +/// The following are memory controller level definitions. All channels on= a controller are set to these values. +/// +typedef struct { + BOOLEAN BaseFlag; ///< Indicates if the base line of power was a= lready calculated. + UINT16 BaseSavingRd; ///< Indicates the base line of power consume = by the ddr on read. + UINT16 BaseSavingWr; ///< Indicates the base line of power consume = by the ddr on write. + UINT16 BaseSavingCmd; ///< Indicates the base line of power consume = by the ddr on command. + UINT16 MrcSavingRd; ///< Indicates the power consume by the ddr on= read at the end of MRC. + UINT16 MrcSavingWr; ///< Indicates the power consume by the ddr on= write at the end of MRC. + UINT16 MrcSavingCmd; ///< Indicates the power consume by the ddr on= command at the end of MRC. +} MrcOdtPowerSaving; + +/// +/// The memory controller capabilities. +/// +typedef union { + UINT32 Data; + UINT16 Data16[2]; + UINT8 Data8[4]; +} MrcCapabilityIdA; + +typedef union { + UINT32 Data; + UINT16 Data16[2]; + UINT8 Data8[4]; +} MrcCapabilityIdB; + +typedef union { + UINT64 Data; + struct { + MrcCapabilityIdA A; + MrcCapabilityIdB B; + } Data32; +} MrcCapabilityId; + +/// +/// MRC version description. +/// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} MrcVersion; + +/// +/// Memory map configuration information. +/// +typedef struct { + UINT32 TomMinusMe; + UINT32 ToludBase; + UINT32 BdsmBase; + UINT32 GttBase; + UINT32 GraphicsControlRegister; + UINT32 TsegBase; + BOOLEAN ReclaimEnable; + UINT32 RemapBase; + UINT32 RemapLimit; + UINT32 TouudBase; + UINT32 TotalPhysicalMemorySize; + UINT32 MeStolenBase; + UINT32 MeStolenSize; + UINT32 GdxcMotBase; + UINT32 GdxcMotSize; + UINT32 GdxcIotBase; + UINT32 GdxcIotSize; + UINT32 DprSize; + UINT32 PttStolenBase; + UINT32 PrmrrBase; + UINT32 LowestBase; +} MrcMemoryMap; + +/// +/// Real time clock information. +/// +typedef struct { + UINT8 Seconds; ///< Seconds, 0-59 + UINT8 Minutes; ///< Minutes, 0-59 + UINT8 Hours; ///< Hours, 0-23 + UINT8 DayOfMonth; ///< Day of the month, 1-31 + UINT8 Month; ///< Month of the year, 1-12 + UINT16 Year; ///< Year, 0-65535 +} MrcBaseTime; + +/// +/// DIMM timings +/// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command= rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS lat= ency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum= CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum= four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum= active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum= RAS# to CAS# delay time and Row Precharge delay time. + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum= Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum= refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum= per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum= refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum= refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum= row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum= row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum= row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum= row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum= internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum= write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum= internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum= internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum= internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum= CAS-to-CAS delay for same bank group. +} MrcTiming; + +typedef struct { + UINT8 SG; ///< Number of tCK cycles between transactions in the sa= me bank group. + UINT8 DG; ///< Number of tCK cycles between transactions when swit= ching bank groups. + UINT8 DR; ///< Number of tCK cycles between transactions when swit= ching between Ranks (in the same DIMM). + UINT8 DD; ///< Number of tCK cycles between transactions when swit= ching between DIMMs +} MrcTurnaroundTimes; + +typedef struct { + INT32 Mtb; ///< Medium time base. + INT32 Ftb; ///< Fine time base. +} MrcTimeBase; + +typedef struct { + UINT8 Left; ///< The left side of the timing eye. + UINT8 Center; ///< The center of the timing eye. + UINT8 Right; ///< The right side of the timing eye. +} MrcDqTimeMargin; + +typedef struct { + UINT8 High; ///< The high side of the Vref eye. + UINT8 Center; ///< The center of the Vref eye. + UINT8 Low; ///< The low side of the Vref eye. +} MrcDqVrefMargin; + +typedef struct { + UINT8 Left; ///< The left side of the command eye. + UINT8 Right; ///< The right side of the command eye. + UINT8 High; ///< The high side of the command eye. + UINT8 Low; ///< The low side of the command eye. +} MrcCommandMargin; + +typedef struct { + UINT8 Left; ///< The left side of the receive enable eye. + UINT8 Right; ///< The right side of the receive enableeye. +} MrcRecvEnMargin; + +typedef struct { + UINT8 Left; ///< The left side of the write leveling eye. + UINT8 Right; ///< The right side of the write leveling eye. +} MrcWrLevelMargin; + +typedef struct { + UINT8 SpdValid[sizeof (MrcSpd) / (CHAR_BITS * sizeof (UINT8))]; ///<= Each valid bit maps to SPD byte. + UINT8 MrcSpdString[3]; ///< The SPD data start marker. This must be = located at the start of the SPD data structure. It includes this string plu= s the following flag. + union { + struct { + UINT8 DimmNumber : 4; ///< SPD zero based DIMM number. + UINT8 ChannelNumber : 3; ///< SPD zero based channel number. + UINT8 MdSocket : 1; ///< 0 =3D memory down, 1 =3D socketed. + } Bit; + UINT8 Data; + } Flag; + MrcSpd Data; ///< The SPD data for each DIMM. SPDGeneral fiel= d =3D 0 when absent. +} MrcSpdData; + +typedef UINT8 (*MRC_IO_READ_8) (UINT32 IoAddress); +typedef UINT16 (*MRC_IO_READ_16) (UINT32 IoAddress); +typedef UINT32 (*MRC_IO_READ_32) (UINT32 IoAddress); +typedef void (*MRC_IO_WRITE_8) (UINT32 IoAddress, UIN= T8 Value); +typedef void (*MRC_IO_WRITE_16) (UINT32 IoAddress, UIN= T16 Value); +typedef void (*MRC_IO_WRITE_32) (UINT32 IoAddress, UIN= T32 Value); +typedef UINT8 (*MRC_MMIO_READ_8) (UINT32 Address); +typedef UINT16 (*MRC_MMIO_READ_16) (UINT32 Address); +typedef UINT32 (*MRC_MMIO_READ_32) (UINT32 Address); +typedef UINT64 (*MRC_MMIO_READ_64) (UINT32 Address); +typedef UINT8 (*MRC_MMIO_WRITE_8) (UINT32 Address, UINT8= Value); +typedef UINT16 (*MRC_MMIO_WRITE_16) (UINT32 Address, UINT1= 6 Value); +typedef UINT32 (*MRC_MMIO_WRITE_32) (UINT32 Address, UINT3= 2 Value); +typedef UINT64 (*MRC_MMIO_WRITE_64) (UINT32 Address, UINT6= 4 Value); +typedef UINT8 (*MRC_SMBUS_READ_8) (UINT32 Address, UINT3= 2 *Status); +typedef UINT16 (*MRC_SMBUS_READ_16) (UINT32 Address, UINT3= 2 *Status); +typedef UINT8 (*MRC_SMBUS_WRITE_8) (UINT32 Address, UINT8= Value, UINT32 *Status); +typedef UINT16 (*MRC_SMBUS_WRITE_16) (UINT32 Address, UINT1= 6 Value, UINT32 *Status); +typedef UINT32 (*MRC_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Devi= ce, UINT8 Function, UINT8 Offset); +typedef UINT32 (*MRC_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8 Devi= ce, UINT8 Function, UINT8 Offset); +typedef void (*MRC_GET_RTC_TIME) (UINT8 *Second, UINT8 = *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); +typedef UINT64 (*MRC_GET_CPU_TIME) (void *MrcData); +typedef void * (*MRC_MEMORY_COPY) (UINT8 *Destination, U= INT8 *Source, UINT32 NumBytes); +typedef void * (*MRC_MEMORY_SET_BYTE) (UINT8 *Destination, U= INT32 NumBytes, UINT8 Value); +typedef void * (*MRC_MEMORY_SET_WORD) (UINT16 *Destination, = UINT32 NumWords, UINT16 Value); +typedef void * (*MRC_MEMORY_SET_DWORD) (UINT32 *Destination, = UINT32 NumDwords, UINT32 Value); +typedef UINT64 (*MRC_LEFT_SHIFT_64) (UINT64 Data, UINT32 N= umBits); +typedef UINT64 (*MRC_RIGHT_SHIFT_64) (UINT64 Data, UINT32 N= umBits); +typedef UINT64 (*MRC_MULT_U64_U32) (UINT64 Multiplicand, = UINT32 Multiplier); +typedef UINT64 (*MRC_DIV_U64_U64) (UINT64 Dividend, UINT= 64 Divisor, UINT64 *Remainder); +typedef BOOLEAN (*MRC_GET_SPD_DATA) (UINT8 BootMode, UINT8= SpdAddress, UINT8 *SpdData, UINT8 *Ddr3Table, UINT32 Ddr3TableSize, UINT8 = *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 LpddrTableSize); +typedef BOOLEAN (*MRC_GET_RANDOM_NUMBER) (UINT32 *Rand); +typedef UINT32 (*MRC_CPU_MAILBOX_READ) (UINT32 Type, UINT32 C= ommand, UINT32 *Value, UINT32 *Status); +typedef UINT32 (*MRC_CPU_MAILBOX_WRITE) (UINT32 Type, UINT32 C= ommand, UINT32 Value, UINT32 *Status); +typedef UINT32 (*MRC_GET_MEMORY_VDD) (void *MrcData, UINT32= DefaultVdd); +typedef UINT32 (*MRC_SET_MEMORY_VDD) (void *MrcData, UINT32= DefaultVdd, UINT32 Value); +typedef UINT32 (*MRC_CHECKPOINT) (void *MrcData, UINT32= CheckPoint, void *Scratch); +typedef void (*MRC_DEBUG_HOOK) (void *GlobalData, UIN= T16 DisplayDebugNumber); +typedef void (*MRC_PRINT_STRING) (void *String); +typedef UINT8 (*MRC_GET_RTC_CMOS) (UINT8 Location); +typedef UINT64 (*MRC_MSR_READ_64) (UINT32 Location); +typedef UINT64 (*MRC_MSR_WRITE_64) (UINT32 Location, UINT= 64 Data); +typedef void (*MRC_RETURN_FROM_SMC) (void *GlobalData, UIN= T32 MrcStatus); +typedef void (*MRC_DRAM_RESET) (UINT32 PciEBaseAddres= s, UINT32 ResetValue); +typedef void (*MRC_SET_LOCK_PRMRR) (UINT32 PrmrrBase, UIN= T32 PrmrrSize); +typedef void (*MRC_TXT_ACHECK) (void); + +/// +/// Function calls that are called external to the MRC. +/// This structure needs to be aligned with SA_FUNCTION_CALLS. All func= tions that are +/// not apart of SA_FUNCTION_CALLS need to be at the end of the structur= e. +/// +typedef struct { + MRC_IO_READ_8 MrcIoRead8; + MRC_IO_READ_16 MrcIoRead16; + MRC_IO_READ_32 MrcIoRead32; + MRC_IO_WRITE_8 MrcIoWrite8; + MRC_IO_WRITE_16 MrcIoWrite16; + MRC_IO_WRITE_32 MrcIoWrite32; + MRC_MMIO_READ_8 MrcMmioRead8; + MRC_MMIO_READ_16 MrcMmioRead16; + MRC_MMIO_READ_32 MrcMmioRead32; + MRC_MMIO_READ_64 MrcMmioRead64; + MRC_MMIO_WRITE_8 MrcMmioWrite8; + MRC_MMIO_WRITE_16 MrcMmioWrite16; + MRC_MMIO_WRITE_32 MrcMmioWrite32; + MRC_MMIO_WRITE_64 MrcMmioWrite64; + MRC_SMBUS_READ_8 MrcSmbusRead8; + MRC_SMBUS_READ_16 MrcSmbusRead16; + MRC_SMBUS_WRITE_8 MrcSmbusWrite8; + MRC_SMBUS_WRITE_16 MrcSmbusWrite16; + MRC_GET_PCI_DEVICE_ADDRESS MrcGetPciDeviceAddress; + MRC_GET_PCIE_DEVICE_ADDRESS MrcGetPcieDeviceAddress; + MRC_GET_RTC_TIME MrcGetRtcTime; + MRC_GET_CPU_TIME MrcGetCpuTime; + MRC_MEMORY_COPY MrcCopyMem; + MRC_MEMORY_SET_BYTE MrcSetMem; + MRC_MEMORY_SET_WORD MrcSetMemWord; + MRC_MEMORY_SET_DWORD MrcSetMemDword; + MRC_LEFT_SHIFT_64 MrcLeftShift64; + MRC_RIGHT_SHIFT_64 MrcRightShift64; + MRC_MULT_U64_U32 MrcMultU64x32; + MRC_DIV_U64_U64 MrcDivU64x64; + MRC_GET_SPD_DATA MrcGetSpdData; + MRC_GET_RANDOM_NUMBER MrcGetRandomNumber; + MRC_CPU_MAILBOX_READ MrcCpuMailboxRead; + MRC_CPU_MAILBOX_WRITE MrcCpuMailboxWrite; + MRC_GET_MEMORY_VDD MrcGetMemoryVdd; + MRC_SET_MEMORY_VDD MrcSetMemoryVdd; + MRC_CHECKPOINT MrcCheckpoint; + MRC_DEBUG_HOOK MrcDebugHook; + MRC_PRINT_STRING MrcPrintString; + MRC_GET_RTC_CMOS MrcRtcCmos; + MRC_MSR_READ_64 MrcReadMsr64; + MRC_MSR_WRITE_64 MrcWriteMsr64; + MRC_RETURN_FROM_SMC MrcReturnFromSmc; + MRC_DRAM_RESET MrcDramReset; + MRC_SET_LOCK_PRMRR MrcSetLockPrmrr; + MRC_TXT_ACHECK MrcTxtAcheck; +} MRC_FUNCTION; + +/// +///***************************************** +/// Output related "global data" structures. +///***************************************** +/// +/// This data structure contains all the "global data" values that are con= sidered output by the MRC. +/// The following are SDRAM level definitions. All ranks on a rank are set= to these values. +/// +/* Commented out until needed, in order to save space. +typedef struct { +} MrcSdramOut; +*/ + +/// +/// This data structure contains all the "global data" values that are con= sidered output by the MRC. +/// The following are rank level definitions. All ranks on a DIMM are set = to these values. +/// +typedef struct { +//MrcSdramOut Sdram[MAX_SDRAM_IN_DIMM]; ///< The following are= SDRAM level definitions. + UINT16 MR[MAX_MR_IN_DIMM]; ///< DRAM mode registe= r value. + UINT16 MR11; ///< LPDDR3 ODT MR + UINT8 Ddr4PdaMr6[MAX_SDRAM_IN_DIMM]; ///< DDR4 MR6[6:0] for= per-DRAM VrefDQ (PDA) +#if (SUPPORT_DDR4 =3D=3D SUPPORT) + UINT8 Device[MAX_SDRAM_IN_DIMM]; ///< Which Bytes are t= ied to which Device where BIT0 set means Byte 0 +#endif //SUPPORT_DDR4 +} MrcRankOut; + +/// +/// This data structure contains all the "global data" values that are con= sidered output by the MRC. +/// The following are DIMM level definitions. All ranks on a DIMM are set = to these values. +/// +typedef struct { + MrcDimmSts Status; ///< See MrcDimmSts for the de= finition of this field. + MrcTiming Timing[MAX_PROFILE]; ///< The DIMMs timing values. + MrcVddSelect VddVoltage[MAX_PROFILE]; ///< The voltage (VDD) setting= for this DIMM, per profile. + BOOLEAN EccSupport; ///< TRUE if ECC is enabled an= d supported on this DIMM. + BOOLEAN IgnoreNonEccDimm; ///< TRUE if a DIMM without EC= C capability should be ignored. + BOOLEAN AddressMirrored; ///< TRUE if the DIMM is addre= ss mirrored. + BOOLEAN SelfRefreshTemp; ///< TRUE if the DIMM supports= self refresh extended operating temperature range (SRT). + BOOLEAN AutoSelfRefresh; ///< TRUE if the DIMM supports= automatic self refresh (ASR). + BOOLEAN PartialSelfRefresh; ///< TRUE if the DIMM supports= Partial Array Self Refresh (PASR). + BOOLEAN OnDieThermalSensor; ///< TRUE if the DIMM supports= On-die Thermal Sensor (ODTS) Readout. + BOOLEAN ExtendedTemperRange; ///< TRUE if the DIMM supports= Extended Temperature Range (ETR). + BOOLEAN ExtendedTemperRefresh; ///< TRUE if the DIMM supports= 1x Extended Temperature Refresh rate, FALSE =3D 2x. + MrcDdrType DdrType; ///< DDR type: DDR3 or LPDDR3 + MEMORY_PACKAGE ModuleType; ///< Module type: UDIMM, SO-DI= MM, etc. + UINT32 SdramCount; ///< The number of SDRAM compo= nents on a DIMM. + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT32 RowSize; ///< The DIMMs row address siz= e. + UINT16 ColumnSize; ///< The DIMMs column address = size. + UINT16 Crc; ///< Calculated CRC16 of the D= IMM's provided SPD. Can be used to detect DIMM change. + UINT8 RankInDimm; ///< The number of ranks in th= is DIMM. + UINT8 Banks; ///< Number of banks the DIMM = contains. + UINT8 BankGroups; ///< Number of bank groups the= DIMM contains. + UINT8 PrimaryBusWidth; ///< DIMM primary bus width. + UINT8 SdramWidth; ///< DIMM SDRAM width. + UINT8 SdramWidthIndex; ///< DIMM SDRAM width index (0= =3D x4, 1 =3D x8, 2 =3D x16, 3 =3D x32). + UINT8 DensityIndex; ///< Total SDRAM capacity inde= x (0 =3D 256Mb, 1 =3D 512Mb, 2 =3D 1Gb, etc). + UINT8 tMAC; ///< Maximum Activate Count fo= r pTRR. + UINT8 ReferenceRawCard; ///< Indicates which JEDEC ref= erence design raw card was used as the basis for the module assembly. + UINT8 ReferenceRawCardRevision; ///< Indicates which JEDEC ref= erence design raw card revision. + UINT8 XmpSupport; ///< Indicates if XMP profiles= are supported. 0 =3D None, 1 =3D XMP1 only, 2 =3D XMP2 only, 3 =3D All. + UINT8 XmpRevision; ///< Indicates the XMP revisio= n of this DIMM. 0 =3D None, 12h =3D 1.2, 13h =3D 1.3. + MrcFrequency Speed; ///< Max DIMM speed in the cur= rent profile - needed for SMBIOS. + MrcRankOut Rank[MAX_RANK_IN_DIMM]; ///< The following are rank le= vel definitions. +} MrcDimmOut; + +/// +/// This data structure contains all the "global data" values that are con= sidered output by the MRC. +/// The following are channel level definitions. All DIMMs on a memory cha= nnel are set to these values. +/// +typedef struct { + MrcChannelSts Status; = ///< Indicates whether this channel should be used. + MrcVirtualChannel VirtualChannel; = ///< define the virtual channel type A or B. + MrcTiming Timing[MAX_PROFILE]; = ///< The channel timing values. + MrcTimeBase TimeBase[MAX_DIMMS_IN_CHANNEL][MAX_PROFILE]; = ///< Medium and fine timebases for each DIMM in the channel and e= ach memory profile. + UINT32 Capacity; = ///< Amount of memory in this channel, in MBytes. + UINT32 DimmCount; = ///< Number of valid DIMMs that exist in the channel. + UINT32 DataOffsetTrain[MAX_SDRAM_IN_DIMM]; = ///< DataOffsetTrain CR + UINT32 DataCompOffset[MAX_SDRAM_IN_DIMM]; = ///< DataCompOffset CR + UINT32 CkeCmdPiCode[MAX_COMMAND_GROUPS]; = ///< CKE CmdPiCode CR, per group + UINT32 CmdsCmdPiCode[MAX_COMMAND_GROUPS]; = ///< CmdS CmdPiCode CR, per group + UINT32 CmdnCmdPiCode[MAX_COMMAND_GROUPS]; = ///< CmdN CmdPiCode CR, per group + UINT16 TxDqs[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; = ///< TxDQS PI Code + UINT16 TxDq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; = ///< TxDQ Pi Code + UINT16 RcvEn[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; = ///< RcvEn PI Code + UINT16 WlDelay[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; = ///< WlDelay PI Code + UINT8 ClkPiCode[MAX_RANK_IN_CHANNEL]; = ///< Clk Pi Code + UINT8 CtlPiCode[MAX_RANK_IN_CHANNEL]; = ///< Ctl Pi Code + UINT8 CkePiCode[MAX_RANK_IN_CHANNEL]; = ///< Ctl Pi Code + UINT8 TxEq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; = ///< TxEq setting + MrcCommandMargin Command[MAX_RANK_IN_CHANNEL]; = ///< Cmd setting + MrcDqTimeMargin RxDqPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_B= ITS]; ///< Rx PerBit Pi Code + MrcDqTimeMargin TxDqPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_B= ITS]; ///< Tx PerBit Pi Code + MrcDqVrefMargin RxDqVrefPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][M= AX_BITS]; ///< Rx PerBit Vref + MrcDqVrefMargin TxDqVrefPb[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM][M= AX_BITS]; ///< Rx PerBit Vref + MrcRecvEnMargin ReceiveEnable[MAX_RANK_IN_CHANNEL]; = ///< Receive enable per rank + MrcWrLevelMargin WriteLevel[MAX_RANK_IN_CHANNEL]; = ///< Write leveling per rank + UINT8 IoLatency[MAX_RANK_IN_CHANNEL]; = ///< IOLatency + UINT8 RTLatency[MAX_RANK_IN_CHANNEL]; = ///< RoundTripLatency + UINT32 RTIoComp; = ///< RoundTrip IO Compensation of the Channel + UINT8 RxVref[MAX_SDRAM_IN_DIMM]; = ///< RX Vref in steps of 7.9 mv + UINT8 RxEq[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; = ///< RxEQ Setting + UINT8 RxDqsP[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; = ///< RxDQSP PI Code + UINT8 RxDqsN[MAX_RANK_IN_CHANNEL][MAX_SDRAM_IN_DIMM]; = ///< RxDQSN PI Code + UINT8 ValidRankBitMask; = ///< Bit map of the populated ranks per channel + UINT8 ValidCkeBitMask; = ///< Bit map of the used CKE pins per channel + MrcDimmOut Dimm[MAX_DIMMS_IN_CHANNEL]; = ///< DIMM specific output variables. + MrcTurnaroundTimes tRd2Rd; = ///< The system's minimal delay timings for Read command followe= d by Read command. + MrcTurnaroundTimes tRd2Wr; = ///< The system's minimal delay timings for Read command followe= d by Write command. + MrcTurnaroundTimes tWr2Rd; = ///< The system's minimal delay timings for Write command followe= d by Read command. + MrcTurnaroundTimes tWr2Wr; = ///< The system's minimal delay timings for Write command followe= d by Write command. +} MrcChannelOut; + +/// +/// This data structure contains all the "global data" values that are con= sidered output by the MRC. +/// The following are memory controller level definitions. All channels on= a controller are set to these values. +/// +typedef struct { + MrcControllerSts Status; ///< Indicates whether this contr= oller should be used. + UINT16 DeviceId; ///< The PCI device id of this me= mory controller. + UINT8 RevisionId; ///< The PCI revision id of this = memory controller. + UINT8 ChannelCount; ///< Number of valid channels tha= t exist on the controller. + MrcChannelOut Channel[MAX_CHANNEL]; ///< The following are channel le= vel definitions. +} MrcControllerOut; + +/// +///******************************************** +/// Saved data related "global data" structures. +///******************************************** +/// + +/// +/// This data structure contains all the "global data" values that are con= sidered to be needed +/// by the MRC between power state transitions (S0->S3->S0) and also fast = and warm boot modes. +/// The following are DIMM level definitions. +/// +typedef struct { + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information = needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information need= ed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth inform= ation needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information n= eeded for SMBIOS structure creation. +} MrcDimmSave; + +/// +/// This data structure contains all the "global data" values that are con= sidered to be needed +/// by the MRC between power state transitions (S0->S3->S0) and also fast = and warm boot modes. +/// The following are channel level definitions. +/// +typedef struct { + MrcChannelSts Status; ///< Indicates wheth= er this channel should be used. + UINT32 DimmCount; ///< Number of valid= DIMMs that exist in the channel. + UINT8 ValidRankBitMask; ///< Bit map of the = populated ranks per channel + MrcTiming Timing[MAX_PROFILE]; ///< The channel tim= ing values. + MrcDimmOut Dimm[MAX_DIMMS_IN_CHANNEL]; ///< Save the DIMM o= utput characteristics. + MrcDimmSave DimmSave[MAX_DIMMS_IN_CHANNEL]; ///< Save SPD inform= ation needed for SMBIOS structure creation. +} MrcChannelSave; + +/// +/// This data structure contains all the "global data" values that are con= sidered to be needed +/// by the MRC between power state transitions (S0->S3->S0) and also fast = and warm boot modes. +/// The following are controller level definitions. +/// +typedef struct { + MrcControllerSts Status; ///< Indicates whether this cont= roller should be used. + UINT8 ChannelCount; ///< Number of valid channels th= at exist on the controller. + MrcChannelSave Channel[MAX_CHANNEL]; ///< The following are channel l= evel definitions. +} MrcContSave; + +/// +/// This data structure contains all the "global data" values that are con= sidered to be needed +/// by the MRC between power state transitions (S0->S3->S0) and also fast = and warm boot modes. +/// The following are system level definitions. +/// +typedef struct { + UINT32 Crc; ///< The CRC-32 of the data in this structu= re. +} MrcSaveHeader; + +// +// ------- IMPORTANT NOTE -------- +// MRC_MC_REGISTER_COUNT in MrcInterface.h should match the table in MrcSa= veRestore.c. +// Update this define whenever you add/remove registers from this table. +// +#define MRC_REGISTER_COUNT_COMMON (1376 / sizeof (UINT32)) ///< The number= of MC registers that need to be saved (common) +#define MRC_REGISTER_COUNT_SAGV (1528 / sizeof (UINT32)) ///< The number= of MC registers that need to be saved (per SA GV point) + +typedef struct { + MrcCapabilityId McCapId; ///< The memo= ry controller's capabilities. + UINT32 RegSaveCommon[MRC_REGISTER_COUNT_COMMON]; ///< The MC r= egisters that are common to both SA GV points + UINT32 RegSaveLow[MRC_REGISTER_COUNT_SAGV]; ///< The MC r= egisters for the Low SA GV point + UINT32 RegSaveHigh[MRC_REGISTER_COUNT_SAGV]; ///< The MC r= egisters for the High SA GV point, or for SA GV Disabled case + UINT32 MeStolenSize; ///< The mana= gebility engine memory size, in Mbyte units. + MrcCpuStepping CpuStepping; ///< The last= cold boot happended with this CPU stepping. + MrcCpuModel CpuModel; ///< The last= cold boot happended with this CPU model. + MrcCpuFamily CpuFamily; ///< CPU is C= offeelake + MrcVersion Version; ///< The last= cold boot happended with this MRC version. + UINT32 SaMemCfgCrc; ///< The CRC3= 2 of the system agent memory configuration structure. + MrcContSave Controller[MAX_CONTROLLERS]; ///< The foll= owing are controller level definitions. + MrcFrequency FreqMax; ///< The syst= em's requested maximum frequency. + MrcFrequency Frequency; ///< The syst= em's common memory controller frequency. + UINT32 MemoryClock; ///< The syst= em's common memory controller clock, in femtoseconds. + BOOLEAN OddRatioModeLow; ///< If Odd R= atio Mode is enabled, QCLK frequency has an addition of 133/100 MHz. This i= s for SAGV Low point. + BOOLEAN OddRatioModeHigh; ///< If Odd R= atio Mode is enabled, QCLK frequency has an addition of 133/100 MHz. This i= s for SAGV High point, or SAGV disabled / fixed high / fixed low + MrcRefClkSelect RefClk; ///< The memo= ry controller is going to use this reference clock. + MrcClockRatio Ratio; ///< Request = for this memory controller to use this clock ratio. + MrcVddSelect VddVoltage[MAX_PROFILE]; ///< The volt= age (VDD) setting for all DIMMs in the system, per profile. + BOOLEAN EccSupport; ///< TRUE if = ECC is enabled and supported on this controller. + MrcDdrType DdrType; ///< DDR type= : DDR3, DDR4, or LPDDR3 + UINT32 DefaultXmptCK[MAX_PROFILE - XMP_PROFILE1]; ///< The Defa= ult XMP tCK values read from SPD. + UINT8 XmpProfileEnable; ///< If XMP c= apable DIMMs are detected, this will indicate which XMP Profiles are common= among all DIMMs. + BOOLEAN BinnedLpddrDevices; ///< Binned L= PDDR3 devices (6Gb/12Gb/etc) + BOOLEAN TCRSensitiveHynixDDR4; ///< TCR sens= itive Hynix DDR4 in the system + BOOLEAN TCRSensitiveMicronDDR4; ///< TCR sens= itive Micron DDR4 in the system + BOOLEAN LpddrEctDone; ///< Set to TRUE onc= e Early Command Training on LPDDR is done, and we can run JEDEC Init + UINT8 BerEnable; ///< BER Enable (and= # of Addresses) + UINT64 BerAddress[4]; ///< BER Addresses + BOOLEAN DmfcLimitedBoard; ///< Indicates if th= e system has 2DPC Memory Configuration which should be DMFC limited. + BOOLEAN DmfcLimited; ///< Indicates if th= e system has DMFC limited. Should only be set if DmfcLImitedBoard is TRUE. + BOOLEAN MixedUDimmConfig2Dpc; ///< Indicates if th= e system has 2DPC Memory Configuration with Mixed U-DIMM Part Numbers + BOOLEAN ExtendedDdrOverclock; ///< Indicates if MC= is capable of extended Overclock Memory frequencies. +} MrcSaveData; + +typedef struct { + UINT32 Size; ///< The size of this s= tructure, in bytes. Must be the first entry in this structure. + MrcDebug Debug; ///< MRC debug related = variables used for serial output and debugging purposes. + MrcVersion Version; ///< The memory referen= ce code version. + MrcFrequency FreqMax; ///< The requested maxi= mum valid frequency. + MrcFrequency Frequency; ///< The system's commo= n memory controller frequency. + UINT32 MemoryClockMax; ///< The system's commo= n memory controller maximum clock, in femtoseconds. + UINT32 MemoryClock; ///< The system's commo= n memory controller clock, in femtoseconds. + MrcRefClkSelect RefClk; ///< The memory control= ler is going to use this reference clock. + MrcClockRatio Ratio; ///< Request for this m= emory controller to use this clock ratio. + MrcMemoryMap MemoryMapData; ///< The system's memor= y map data. + MrcGfxDataSize GraphicsStolenSize; ///< Graphics Data Stol= en Memory size in MB + MrcGfxGttSize GraphicsGttSize; ///< GTT graphics stole= n memory size in MB + MrcVddSelect VddVoltage[MAX_PROFILE]; ///< The currently runn= ing voltage (VDD) setting for all DIMMs in the system, per profile. + MrcGdxc Gdxc; ///< GDXC enable and si= ze. + BOOLEAN VddVoltageDone; ///< To determine if Vd= dVoltageDone update has been done already + BOOLEAN EccSupport; ///< TRUE if ECC is ena= bled and supported on this controller. + BOOLEAN EnDumRd; ///< Enable/Disable Log= ic Analyzer + BOOLEAN RestoreMRs; ///< Enable/Disable res= toring + BOOLEAN LpddrEctDone; ///< Set to TRUE once E= arly Command Training on LPDDR is done, and we can run JEDEC Init + BOOLEAN LpddrWLUpdated; ///< Set to TRUE once L= PDDR WL Memory Set has been updated + BOOLEAN JedecInitDone; ///< Set to TRUE once J= EDEC Init on LPDDR/DDR4 is done + UINT32 DefaultXmptCK[MAX_PROFILE - XMP_PROFILE1]; = ///< The Default XMP tCK values read from SPD. + UINT8 XmpProfileEnable; ///< If XMP capable DIM= Ms are detected, this will indicate which XMP Profiles are common among all= DIMMs. + BOOLEAN Capable100; ///< The MC is capable = of 100 reference clock (0 =3D no, 1 =3D yes). + BOOLEAN AutoSelfRefresh; ///< Indicates ASR is s= upported for all the DIMMS for 2xRefresh + MrcDdrType DdrType; ///< Current memory typ= e: DDR3, DDR4, or LPDDR3 + MrcSpdStatus SpdSecurityStatus; ///< Status variable to= inform BIOS that memory contains an alias. + UINT32 MrcTotalChannelLimit; ///< The maximum allowe= d memory size per channel, in MBytes. + UINT8 SdramCount; ///< The number of SDRA= M components on a DIMM. + UINT16 Qclkps; ///< Qclk period in pS + UINT8 DQPat; ///< Global Variables s= toring the current DQPat REUT Test + INT8 DQPatLC; ///< Global Variables s= toring the current DQPat Loopcount + UINT16 NumCL; ///< Global Variables s= toring the current number of Cachelines + UINT8 ValidRankMask; ///< Rank bit map - inc= ludes both channels + UINT8 ValidChBitMask; ///< Channel bit map of= the populated channels + BOOLEAN UpmPwrRetrainFlag; ///< A flag that indica= tes if training with higher UPM/PWR limits. + UINT32 MarginResult[MAX_RESULT_TYPE][MAX_RANK_IN_CHANNEL][M= AX_CHANNEL][MAX_SDRAM_IN_DIMM][MAX_EDGES]; ///< Stores last margin measurem= ent. + BOOLEAN MarginSignReversed[MAX_RANK_IN_CHANNEL][MAX_CHANNEL]= [MAX_SDRAM_IN_DIMM][MAX_EDGES]; ///< Indicates if the Margin Sign is Revers= ed + MrcOdtPowerSaving OdtPowerSavingData; ///< ODT power savings = data. + BOOLEAN TxDIMMVref[MAX_CHANNEL]; ///< Whether Write DIMM= Vref is enabled based on Channel + UINT32 MchBarWriteCount; ///< The number of MMIO= writes performed during MRC execution. + UINT32 MchBarReadCount; ///< The number of MMIO= reads performed during MRC execution. + UINT8 BerEnable; ///< BER Enable (and # = of Addresses) + UINT64 BerAddress[4]; ///< BER Addresses + UINT8 CmdVLoop; ///< Keeps track of the= # of CmdV training step runned + UINT8 CmdVLoopStatus; ///< Keeps the last sta= tus of the CmdV training step + UINT8 tMAC; ///< Maximum Activate C= ount for pTRR. + UINT8 LpddrMemWriteLatencySet; ///< 0 =3D Set A (WL), = 1 =3D Set B (WL) if supported + BOOLEAN Ddr4PdaEnable; ///< Current status of = PDA - if true all the Mr6 operations need to use PDA mode. + BOOLEAN BinnedLpddrDevices; ///< Binned LPDDR3 devi= ces (6Gb/12Gb/etc) + MrcControllerOut Controller[MAX_CONTROLLERS]; ///< The following are = controller level definitions. + BOOLEAN TCRSensitiveHynixDDR4; ///< TCR sensitive Hyni= x DDR4 in the system + BOOLEAN TCRSensitiveMicronDDR4; ///< TCR sensitive Micr= on DDR4 in the system + BOOLEAN OddRatioMode; ///< If Odd Ratio Mode = is enabled, QCLK frequency has an addition of 133/100 MHz + BOOLEAN LpddrDramOdt; ///< Indicates if LPDDR= DRAM ODT is used - Only used for 2133+ + BOOLEAN ExtendedDdrOverclock; ///< Indicates if MC is= capable of extended Overclock Memory frequencies. + BOOLEAN DmfcLimitedBoard; ///< Indicates if the s= ystem has 2DPC Memory Configuration which should be DMFC limited. + BOOLEAN DmfcLimited; ///< Indicates if the s= ystem has DMFC has been limited. Should only be set if DmfcLImitedBoard is = TRUE. + BOOLEAN MixedUDimmConfig2Dpc; ///< Indicates if the s= ystem has 2DPC Memory Configuration with Mixed U-DIMM Part Numbers +#ifdef BDAT_SUPPORT + union { + MRC_BDAT_SCHEMA_LIST_HOB *Pointer; ///< Pointer to the BDA= T schema list. + UINT64 Data; + } BdatSchemasHob; + union { + BDAT_MEMORY_DATA_HOB *Pointer; ///< Pointer to the BDA= T memory data HOB. + UINT64 Data; + } BdatMemoryHob[MAX_SCHEMA_LIST_LENGTH]; + UINT8 Margin2DResult[MAX_2D_EYE_TYPE][MAX_RANK_IN_CHANNEL]= [MAX_CHANNEL][MAX_2D_EYE_OFFSETS][MAX_EDGES]; ///< Stores the 2D Eye Margin +#endif + +#ifdef UP_SERVER_FLAG + UINT8 ThermOffset[MAX_CHANNEL][MAX_DIMMS_IN_CHANNEL]; = ///< TSOD Thermal Offset +#endif +} MrcOutput; + +/// +///**************************************** +/// Input related "global data" structures. +///**************************************** +/// +/// This data structure contains all the "global data" values that are con= sidered input by the MRC. +/// The following are SDRAM level definitions. All ranks on a rank are set= to these values. +/// +/* Commented out until needed, in order to save space. +typedef struct { + UINT8 Placeholder; ///< TODO: Is there anything that needs to go in he= re? +} MrcSdramIn; +*/ + +/// +/// This data structure contains all the "global data" values that are con= sidered input by the MRC. +/// The following are rank level definitions. All ranks on a DIMM are set = to these values. +/// +/* Commented out until needed, in order to save space. +typedef struct { + MrcSdramIn Sdram[MAX_SDRAM_IN_DIMM]; ///< The following are SDRAM level= definitions. +} MrcRankIn; +*/ + +/// +/// This data structure contains all the "global data" values that are con= sidered input by the MRC. +/// The following are DIMM level definitions. All ranks on a DIMM are set = to these values. +/// +typedef struct { + MrcDimmSts Status; ///< Indicates whether this DIMM sho= uld be used. + MrcSpdData Spd; ///< The SPD data for each DIMM. SPD= General field =3D 0 when absent. + MrcTiming Timing; ///< The DIMMs requested timing over= rides. + UINT8 SpdAddress; ///< The SMBus address for the DIMM'= s SPD data. +//MrcRankIn Rank[MAX_RANK_IN_DIMM]; ///< The following are rank level de= finitions. +} MrcDimmIn; + +/// +/// This data structure contains all the "global data" values that are con= sidered input by the MRC. +/// The following are channel level definitions. All DIMMs on a memory cha= nnel are set to these values. +/// +typedef struct { + MrcChannelSts Status; ///< Indicates whether this= channel should be used. + UINT32 DimmCount; ///< The maximum number of = DIMMs on this channel. + MrcDimmIn Dimm[MAX_DIMMS_IN_CHANNEL]; ///< The following are DIMM= level definitions. + UINT8 DqsMapCpu2Dram[8]; ///< Mapping from CPU DQS p= ins to SDRAM DQS pins + UINT8 DqMapCpu2Dram[8][MAX_BITS]; ///< Mapping from CPU DQ pi= ns to SDRAM DQ pins + UINT8 DQByteMap[MrcIterationMax][2]; ///< Maps which PI clocks a= re used by what LPDDR DQ Bytes (from CPU side), per group + ///< DQByteMap[0] - ClkDQBy= teMap: + ///< If clock is per rank= , program to [0xFF, 0xFF] + ///< If clock is shared b= y 2 ranks, program to [0xFF, 0] or [0, 0xFF] + ///< If clock is shared b= y 2 ranks but does not go to all bytes, + ///< Entry[i] def= ines which DQ bytes Group i services + ///< DQByteMap[1] - CmdNDQB= yteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN/CAB + ///< DQByteMap[2] - CmdSDQB= yteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS/CAB + ///< DQByteMap[3] - CkeDQBy= teMap : Entry[0] is CKE /CAA and Entry[1] is CKE /CAB + ///< For DDR= , DQByteMap[3:1] =3D [0xFF, 0] + ///< DQByteMap[4] - CtlDQBy= teMap : Always program to [0xFF, 0] since we have 1 CTL / rank + ///< = Variable only exists to make the code easier to use + ///< DQByteMap[5] - CmdVDQB= yteMap: Always program to [0xFF, 0] since we have 1 CA Vref + ///< = Variable only exists to make the code easier to use +} MrcChannelIn; + +/// +/// This data structure contains all the "global data" values that are con= sidered input by the MRC. +/// The following are memory controller level definitions. All channels on= a controller are set to these values. +/// +typedef struct { + MrcControllerSts Status; ///< Indicates whether this cont= roller should be used. + UINT8 ChannelCount; ///< Number of valid channels th= at are requested on the controller. + MrcChannelIn Channel[MAX_CHANNEL]; ///< The following are channel l= evel definitions. +} MrcControllerIn; + +/// This data structure contains all the "global data" values that are con= sidered input by the MRC. +/// The following are system level definitions. All memory controllers in = the system are set to these values. +typedef struct { + // Start of synchronization to the SA MEMORY_CONFIGURATION structure. + // Alignment of this block must be maintained and field offsets must mat= ch. + UINT8 Header[28]; ///< Offset 0-27 Config Block Header + UINT16 Size; ///< Offset 28 The size of this structur= e, in bytes. Must be the first entry in this structure. + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer + UINT8 MemoryProfile; ///< Offset 31 SPD XMP profile selection= - for XMP supported DIMM: 0=3DDefault DIMM profile, 1=3DCustomized = profile, 2=3DXMP profile 1, 3=3DXMP profile 2. + // The following parameters are used only when MemoryProfile is UserDefi= ned (CUSTOM PROFILE) + UINT16 tCL; ///< Offset 32 User defined Memory Timin= g tCL value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 31=3DMaximum. + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timin= g tRCD value (same as tRP), valid when MemoryProfile is CUSTOM_PROFILE: = 0=3DAUTO, 63=3DMaximum. + UINT16 tRAS; ///< Offset 36 User defined Memory Timin= g tRAS value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 64=3DMaximum. + UINT16 tWR; ///< Offset 38 User defined Memory Timin= g tWR value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24. + UINT16 tRFC; ///< Offset 40 User defined Memory Timin= g tRFC value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 1023=3DMaximum. + UINT16 tRRD; ///< Offset 42 User defined Memory Timin= g tRRD value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 15=3DMaximum. + UINT16 tWTR; ///< Offset 44 User defined Memory Timin= g tWTR value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 28=3DMaximum. + UINT16 tRTP; ///< Offset 46 User defined Memory Timin= g tRTP value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 15=3DMaximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12 + UINT16 tFAW; ///< Offset 48 User defined Memory Timin= g tFAW value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 63=3DMaximum. + UINT16 tCWL; ///< Offset 50 User defined Memory Timin= g tCWL value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 20=3DMaximum. + UINT16 tREFI; ///< Offset 52 User defined Memory Timin= g tREFI value, valid when MemoryProfile is CUSTOM_PROFILE: 0=3DAUTO,= 65535=3DMaximum. + UINT16 PciIndex; ///< Offset 54 Pci index register addres= s: 0xCF8=3DDefault + UINT16 PciData; ///< Offset 56 Pci data register address= : 0xCFC=3DDefault + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in mil= livolts: 0=3DPlatform Default (no override), 1200=3D1.2V, 1350=3D1.3= 5V etc. + UINT16 Idd3n; ///< Offset 60 EPG Active standby curren= t (Idd3N) in milliamps from DIMM datasheet. + UINT16 Idd3p; ///< Offset 62 EPG Active power-down cur= rent (Idd3P) in milliamps from DIMM datasheet. + + UINT32 EccSupport:1; ///< Offset 64 DIMM Ecc Support = option - for Desktop only: 0=3DDisable, 1=3DEnable + UINT32 MrcSafeConfig:1; ///< - MRC Safe Mode: 0=3DDi= sable, 1=3DEnable + UINT32 RemapEnable:1; ///< - This option is used to c= ontrol whether to enable/disable memory remap above 4GB: 0=3DDisable, 1= =3DEnable. + UINT32 ScramblerEnable:1; ///< - Memory scrambler support= : 0=3DDisable, 1=3DEnable + UINT32 Vc1ReadMeter:1; ///< - VC1 Read Metering Enable= : 0=3DDisable, 1=3DEnable + UINT32 DdrThermalSensor:1; ///< - Ddr Thermal Sensor: 0=3D= Disable, 1=3DEnable + UINT32 LpddrMemWriteLatencySet:1; ///< - LPDDR3 Write Latency Set= option: 0=3DSet A, 1=3DSet B + UINT32 Off64Bits7to8Rsvd:2; ///< - Bits 7-8 Reserved + UINT32 SimicsFlag:1; ///< - Option to Enable SIMICS:= 0=3DDisable, 1=3DEnable + UINT32 Ddr4DdpSharedClock:1; ///< - New Select if CLK0 is sh= ared between Rank0 and Rank1 in DDR4 DDP package. 0=3DNot shared, 1= =3DShared + UINT32 Ddr4DdpSharedZq:1; ///< - Select if ZQ pin is shar= ed between Rank0 and Rank1 in DDR4 DDP package. 0=3DNot shared, 1=3D= Shared + // Thermal Management + UINT32 ThermalManagement:1; ///< - Memory Thermal Managemen= t Support: 0=3DDisable, 1=3DEnable. + UINT32 PeciInjectedTemp:1; ///< - Enable/Disable memory te= mperatures to be injected to the processor via PECI: 0=3DDisable, 1= =3DEnable. + UINT32 ExttsViaTsOnBoard:1; ///< - Enable/Disable routing T= S-on-Board's ALERT# and THERM# to EXTTS# pins on the PCH: 0=3DDisable, 1=3DEnable. + UINT32 ExttsViaTsOnDimm:1; ///< - Enable/Disable routing T= S-on-DIMM's ALERT# to EXTTS# pin on the PCH: 0=3DDisable, 1=3DEnable. + UINT32 VirtualTempSensor:1; ///< - Enable/Disable Virtual T= emperature Sensor (VTS): 0=3DDisable, 1=3DEnable. + UINT32 Lp4DqsOscEn:1; ///< - DqDqsReTraining support:= 0=3DDisable, 1=3DEnable + UINT32 DualDimmPerChannelBoardType:1; ///< - DualDimmPerChannelBoardT= ype: Option to indicate if the Memory Design for the board includes two DIM= Ms per channel: 0=3DSingle DIMM Design, 1=3DDual DIMM Design + UINT32 ReservedBits1:13; + /** + Disables a DIMM slot in the channel even if a DIMM is present\n + Array index represents the channel number (0 =3D channel 0, 1 =3D chann= el 1)\n + 0x0 =3D DIMM 0 and DIMM 1 enabled\n + 0x1 =3D DIMM 0 disabled, DIMM 1 enabled\n + 0x2 =3D DIMM 0 enabled, DIMM 1 disabled\n + 0x3 =3D DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n + **/ + UINT8 DisableDimmChannel[MAX_CHANNEL]; ///< Offset 68 + /** + Selects the ratio to multiply the reference clock by for the DDR freque= ncy\n + When RefClk is 133MHz\n + 0x00 =3D Auto, 0x03 through 0x0C are valid values, all others ar= e invalid\n + When RefClk is 100MHz\n + 0x00 =3D Auto, 0x06 through 0x10 are valid values, all others ar= e invalid\n + **/ + UINT8 Ratio; ///< Offset 70 + UINT8 ProbelessTrace; ///< Offset 71 Probeless Trace: 0=3DD= isabled, 1=3DEnabled + UINT32 BClkFrequency; ///< Offset 72 Base reference clock valu= e, in Hertz: 100000000 =3D 100Hz, 125000000=3D125Hz, 167000000=3D167= Hz, 250000000=3D250Hz + /** + - Channel Hash Enable.\n + NOTE: BIT7 will interleave the channels at a 2 cacheline granularity, = BIT8 at 4 and BIT9 at 8\n + 0=3DBIT6, 1=3DBIT7, 2=3DBIT8, 3=3DBIT9 + **/ + UINT8 ChHashInterleaveBit; ///< Offset 76 + UINT8 EnergyScaleFact; ///< Offset 77 - Energy Scale Factor. 0= =3DMinimal, 7=3DMaximum, 4=3DDefault + UINT8 Reserved0; ///< Offset 78 - Reserved for future use. + UINT8 McLock; ///< Offset 79 - Enable/Disable memory c= onfiguration register locking: 0=3DDisable, 1=3DEnable. + // Training Algorithms + TrainingStepsEn TrainingEnables; ///< Offset 80 - Options to Enable i= ndividual training steps + TrainingStepsEn2 TrainingEnables2; ///< Offset 84 - Options to Enable i= ndividual training steps + + UINT32 OddRatioMode:1; ///< Offset 88 - If Odd Ratio Mode i= s enabled, QCLK frequency has an addition of 133/100 MHz: 0=3DDisable, 1=3DEnable + UINT32 MrcTimeMeasure:1; ///< - Enables serial debug level to= display the MRC execution times only: 0=3DDisable, 1=3DEnable + UINT32 MrcFastBoot:1; ///< - Enables the MRC fast boot pat= h for faster cold boot execution: 0=3DDisable, 1=3DEnable + UINT32 DqPinsInterleaved:1; ///< - Interleaving mode of DQ/DQS p= ins for HSW_ULT which depends on board routing: 0=3DDisable, 1=3DEna= ble + UINT32 RankInterleave:1; ///< - Rank Interleave Mode: 0=3DDis= able, 1=3DEnable + UINT32 EnhancedInterleave:1; ///< - Enhanced Interleave Mode: 0= =3DDisable, 1=3DEnable + UINT32 WeaklockEn:1; ///< - Weak Lock Enable: 0=3DDisable= , 1=3DEnable + UINT32 CmdTriStateDis:1; ///< - CMD Tri-State Support: 0= =3DEnable, 1=3DDisable. Note: This should be set to 1 (Disable) if Comm= and RTT is not present on the platform. + UINT32 MemoryTrace:1; ///< - Memory Trace to second DDR ch= annel using Stacked Mode: 0=3DDisable, 1=3DEnable + UINT32 ChHashEnable:1; ///< - Channel Hash Enable: 0=3DDisa= ble, 1=3DEnable + UINT32 EnableExtts:1; ///< - Enable Extts: 0=3DDisable<= /b>, 1=3DEnable + UINT32 EnableCltm:1; ///< - Enable Closed Loop Thermal Ma= nagement: 0=3DDisable, 1=3DEnable + UINT32 EnableOltm:1; ///< - Enable Open Loop Thermal Mana= gement: 0=3DDisable, 1=3DEnable + UINT32 EnablePwrDn:1; ///< - Enable Power Down control for= DDR: 0=3DPCODE control, 1=3DBIOS control + UINT32 EnablePwrDnLpddr:1; ///< - Enable Power Down for LPDDR: = 0=3DPCODE control, 1=3DBIOS control + UINT32 LockPTMregs:1; ///< - Lock PCU Thermal Management r= egisters: 0=3DDisable, 1=3DEnable + UINT32 UserPowerWeightsEn:1; ///< - Allows user to explicitly set= power weight, scale factor, and channel power floor values: 0=3DDisable= , 1=3DEnable + UINT32 RaplLim2Lock:1; ///< - Lock DDR_RAPL_LIMIT register:= 0=3DDisable, 1=3DEnable + UINT32 RaplLim2Ena:1; ///< - Enable Power Limit 2: 0=3D= Disable, 1=3DEnable + UINT32 RaplLim1Ena:1; ///< - Enable Power Limit 1: 0=3D= Disable, 1=3DEnable + UINT32 SrefCfgEna:1; ///< - Enable Self Refresh: 0=3DDisa= ble, 1=3DEnable + UINT32 ThrtCkeMinDefeatLpddr:1; ///< - Throttler CKE min defeature f= or LPDDR: 0=3DDisable, 1=3DEnable + UINT32 ThrtCkeMinDefeat:1; ///< - Throttler CKE min defeature: = 0=3DDisable, 1=3DEnable + UINT32 AutoSelfRefreshSupport:1; ///< - FALSE =3D No auto self refres= h support, TRUE =3D auto self refresh support + UINT32 ExtTemperatureSupport:1; ///< - FALSE =3D No extended tempera= ture support, TRUE =3D extended temperature support + UINT32 MobilePlatform:1; ///< - Memory controller device id i= ndicates: TRUE if mobile, FALSE if not. Note: This will be auto-dete= cted and updated. + UINT32 Force1Dpc:1; ///< - TRUE means force one DIMM per= channel, FALSE means no limit + UINT32 ForceSingleRank:1; ///< - TRUE means use Rank0 only (in= each DIMM): 0=3DDisable, 1=3DEnable + UINT32 RhPrevention:1; ///< - RH Prevention Enable/Disable:= 0=3DDisable, 1=3DEnable + UINT32 VttTermination:1; ///< - Vtt Termination for Data ODT:= 0=3DDisable, 1=3DEnable + UINT32 VttCompForVsshi:1; ///< - Enable/Disable Vtt Comparator= For Vsshi: 0=3DDisable, 1=3DEnable + UINT32 ExitOnFailure:1; ///< - MRC option for exit on failur= e or continue on failure: 0=3DDisable, 1=3DEnable + + UINT32 VddSettleWaitTime; ///< Offset 92 - Amount of time in micro= seconds to wait for Vdd to settle on top of 200us required by JEDEC spec: <= b>Default=3D0 + UINT16 FreqSaGvLow; ///< Offset 96 - SA GV: 0 is Auto/defaul= t, otherwise holds the frequency value: 0=3DDefault, 1067, 1200, 133= 3, 1400, 1600, 1800, 1867. + UINT16 SrefCfgIdleTmr; ///< Offset 98 - Self Refresh idle timer= : 512=3DMinimal, 65535=3DMaximum + UINT8 RhActProbability; ///< Offset 100 - Activation probability= for Hardware RHP + UINT8 SmramMask; ///< Offset 101 - Reserved memory ranges= for SMRAM + UINT16 Vc1ReadMeterThreshold; ///< Offset 102 - VC1 Read Meter Thresho= ld (within Time Window): 0=3DMinimal, 0xFFFF=3DMaximum, 0x118=3DDefault<= /b> + UINT32 Vc1ReadMeterTimeWindow; ///< Offset 104 - VC1 Read Meter Time Wi= ndow: 0=3DMinimal, 0x1FFFF=3DMaximum, 0x320=3DDefault + UINT64 BerAddress[4]; ///< Offset 108 - 139 BER Address(es): <= b>0=3DMinimal, 0xFFFFFFFFFFFFFFFF=3DMaximum (step is 0x40) + + UINT16 ChHashMask; ///< Offset 140 - Channel Hash Mask: 0x0= 001=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT[= 19:18, 13:12 ,9:7] set + UINT16 DdrFreqLimit; ///< Offset 142 - Memory Frequency Limit= : 0=3DAuto (limited by SPD/CPU capability), for valid values see Mrc= Frequency in MrcInterface.h + ThermalMngmtEn ThermalEnables; ///< Offset 144 - 187 + + UINT8 MaxRttWr; ///< Offset 188 - Maximum DIMM RTT_WR to= use in power training: 0=3DODT Off, 1 =3D 120 ohms + UINT8 ThrtCkeMinTmr; ///< Offset 189 - Throttler CKE min time= r: 0=3DMinimal, 0xFF=3DMaximum, 0x30=3DDefault + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 190 - Throttler CKE min time= r for LPDDR: 0=3DMinimal, 0xFF=3DMaximum, 0x40=3DDefault + UINT8 BerEnable; ///< Offset 191 - BER Enable and # of Ad= dresses passed in: 0=3DMinimal, 8=3DMaximum + UINT8 CkeRankMapping; ///< Offset 192 - Bits [7:4] - Channel 1= , bits [3:0] - Channel 0. 0xAA=3DDefault Bit [i] specifies which ran= k CKE[i] goes to. + UINT8 StrongWkLeaker; ///< Offset 193 - Strong Weak Leaker: 1= =3DMinimal, 7=3DMaximum + UINT8 CaVrefConfig; ///< Offset 194 - 0=3DVREF_CA goes to bo= th CH_A and CH_B, 1=3DVREF_CA to CH_A, VREF_DQ_A to CH_B, 2=3DVREF_CA to= CH_A, VREF_DQ_B to CH_B + UINT8 SaGv; ///< Offset 195 - SA GV: 0=3DDisabled= , 1=3DFixedLow, 2=3DFixedHigh, 3=3DEnabled + UINT8 RaplPwrFlCh1; ///< Offset 196 - Power Channel 1 Floor = value: 0=3DMinimal, 255=3DMaximum + UINT8 RaplPwrFlCh0; ///< Offset 197 - Power Channel 0 Floor = value: 0=3DMinimal, 255=3DMaximum + UINT8 NModeSupport; ///< Offset 198 - Memory N Mode Support = - Enable user to select Auto, 1N or 2N: 0=3DAUTO, 1=3D1N, 2=3D2N. + UINT8 RefClk; ///< Offset 199 - Selects the DDR base r= eference clock. 0x01 =3D 100MHz, 0x00 =3D 133MHz + UINT8 EnCmdRate; ///< Offset 200 - CMD Rate Enable: 0=3DD= isable, 1=3D1 CMD, 2=3D2 CMDs, 3=3D3 CMDs, 4=3D4 CMDs, 5=3D5 CMDs, 6= =3D6 CMDs, 7=3D7 CMDs + UINT8 Refresh2X; ///< Offset 201 - Refresh 2x: 0=3DDis= able, 1=3DEnable for WARM or HOT, 2=3DEnable for HOT only + UINT8 EpgEnable; ///< Offset 202 - Enable Energy Performa= nce Gain. + UINT8 RhSolution; ///< Offset 203 - Type of solution to be= used for RHP - 0/1 =3D HardwareRhp/Refresh2x + UINT8 UserThresholdEnable; ///< Offset 204 - Flag to manually selec= t the DIMM CLTM Thermal Threshold, 0=3DDisable, 1=3DEnable, 0=3DDefault= + UINT8 UserBudgetEnable; ///< Offset 205 - Flag to manually selec= t the Budget Registers for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 TsodTcritMax; ///< Offset 206 - TSOD Tcrit Maximum Val= ue to be Configure , 0=3DMinimal, 128=3DMaximum, , 105=3DDefault + + UINT8 TsodEventMode; ///< Offset 207 - Flag to Enable Event M= ode Interruption in TSOD Configuration Register, 0=3DDisable, 1=3DEnable, = 1=3DDefault + UINT8 TsodEventPolarity; ///< Offset 208 - Event Signal Polarity = in TSOD Configuration Register, 0=3DLow, 1=3DHigh, 0=3DDefault + UINT8 TsodCriticalEventOnly; ///< Offset 209 - Critical Trigger Only = in TSOD Configuration Register,0=3DDisable, 1=3DEnable, 1=3DDefault + UINT8 TsodEventOutputControl; ///< Offset 210 - Event Output Control i= n TSOD Configuration Register,0=3DDisable, 1=3DEnable, 1=3DDefault + UINT8 TsodAlarmwindowLockBit; ///< Offset 211 - Alarm Windows Lock Bit= in TSOD Configuration Register,0=3DUnlock, 1=3DLock, 0=3DDefault + UINT8 TsodCriticaltripLockBit;///< Offset 212 - Critical Trip Lock Bit= in TSOD Configuration Register,0=3DUnlock, 1=3DLock, 0=3DDefault + UINT8 TsodShutdownMode; ///< Offset 213 - Shutdown Mode TSOD Con= figuration Register,0=3DEnable, 1=3DDisable, 0=3DDefault + UINT8 TsodThigMax; ///< Offset 214 - Thigh Max Value In the= for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 TsodManualEnable; ///< Offset 215 - Flag to manually selec= t the TSOD Register Values , 0=3DDisable, 1=3DEnable, 0=3DDefault + UINT8 DllBwEn0; ///< Offset 216 - DllBwEn value for 1067 + UINT8 DllBwEn1; ///< Offset 217 - DllBwEn value for 1333 + UINT8 DllBwEn2; ///< Offset 218 - DllBwEn value for 1600 + UINT8 DllBwEn3; ///< Offset 219 - DllBwEn value for 1867= and up + UINT8 RetrainOnFastFail; ///< Offset 220 - Restart MRC in Cold mo= de if SW MemTest fails during Fast flow. 0 =3D Disabled, 1 =3D Enabled + UINT8 ForceOltmOrRefresh2x; ///< Offset 221 - Force OLTM or 2X Refre= sh when needed. 0 =3D Force OLTM, 1 =3D Force 2x Refresh + UINT8 PowerDownMode; ///< Offset 222 - CKE Power Down Mode: <= b>0xFF=3DAUTO, 0=3DNo Power Down, 1=3D APD mode, 6=3DPPD-DLL Off mode + UINT8 PwdwnIdleCounter; ///< Offset 223 - CKE Power Down Mode Id= le Counter: 0=3DMinimal, 255=3DMaximum, 0x80=3D0x80 DCLK + UINT8 IsvtIoPort; ///< Offset 224 ISVT IO Port Address: 0= =3DMinimal, 0xFF=3DMaximum, 0x99=3DDefault + UINT8 Reserved3; ///< Offset 225 - ConfigBlock size must= be a multiple of DWORDs + MrcGdxc Gdxc; ///< Offset 226 - 228 - GDXC enable and = size. + UINT8 RMTLoopCount; ///< Offset 229 - Indicates the Loop Cou= nt to be used for Rank Margin Tool Testing: 1=3DMinimal, 32=3DMaximum, 0=3D= AUTO, 0=3DDefault + UINT8 Reserved4[2]; ///< Offset 230 - 231 Reserved for DWORD= alignment. + UINT32 RmtPerTask:1; ///< Offset 232 Bit 0: Rank Margin= Tool Per Task. 0 =3D Disabled, 1 =3D Enabled + UINT32 Off232Bit1Rsvd:2; ///< Offset 232 Bit 1-2: Reserved + UINT32 EnBER:1; ///< Offset 232 Bit 3: Define if E= nBER is enabled for Rank Margin Tool + UINT32 Ddr4MixedUDimm2DpcLimit:1; ///< Offset 232 Bit 4: Enable/Disa= ble 2667 Frequency Limitation for DDR4 U-DIMM Mixed Dimm 2DPC population. 0= =3D Disabled, 1 =3D Enabled + UINT32 FastBootRmt:1; ///< Offset 232 Bit 5: Enable/Disa= ble RMT on FastBoot. 0 =3D Disabled, 1 =3D Enabled + UINT32 MrcTrainOnWarm:1; ///< Offset 232 Bit 6: Enalbes MRC= trainin on warm boot : 0=3DDisable, 1 =3D Enabled + UINT32 LongFlyByModeEnabled:1; ///< Offset 232 Bit 7: Long FlyBy = Mode Enabled : 0 =3D Disabled, 1 =3D Enabled + UINT32 Off232RsvdBits:24; ///< Offset 232 Bit 8-31: Reserved + + // + // TurnAround Timing + // + MrcTurnaroundTimes tRd2Rd; ///< Offset 236 - User-defined overrides= for Read-to-Read Turn Around Timings. 0 =3D AUTO + MrcTurnaroundTimes tRd2Wr; ///< Offset 240 - User-defined overrides= for Read-to-Write Turn Around Timings. 0 =3D AUTO + MrcTurnaroundTimes tWr2Rd; ///< Offset 244 - User-defined overrides= for Write-to-Read Turn Around Timings. 0 =3D AUTO + MrcTurnaroundTimes tWr2Wr; ///< Offset 248 - User-defined overrides= for Write-to-Write Turn Around Timings. 0 =3D AUTO + UINT16 tRRD_L; ///< Offset 252 - User defined DDR4 Memo= ry Timing tRRD_L value, valid when MemoryProfile is CUSTOM_PROFILE: 0= =3DAUTO, 15=3DMaximum. + UINT16 tRRD_S; ///< Offset 254 - User defined DDR4 Memo= ry Timing tRRD_S value, valid when MemoryProfile is CUSTOM_PROFILE: 0= =3DAUTO, 15=3DMaximum. + UINT16 tWTR_L; ///< Offset 266 - User defined DDR4 Memo= ry Timing tWTR_L value, valid when MemoryProfile is CUSTOM_PROFILE: 0= =3DAUTO, 28=3DMaximum. + UINT16 tWTR_S; ///< Offset 268 - User defined DDR4 Memo= ry Timing tWTR_S value, valid when MemoryProfile is CUSTOM_PROFILE: 0= =3DAUTO, 28=3DMaximum. + + // + // End of synchronization to the SA MEMORY_CONFIGURATION structure. + // + MrcFrequency FreqMax; ///< The requested maximum= valid frequency. + MrcBoardType BoardType; ///< Define the board type= (CRBMB,CRBDT,User1,User2). the OEM can add more boards. + MrcCpuStepping CpuStepping; ///< Define the CPU steppi= ng. + MrcCpuModel CpuModel; ///< Define the CPU model. + MrcCpuFamily CpuFamily; ///< CPU is Coffeelake + MrcGfxDataSize GraphicsStolenSize; ///< Graphics Data Stolen = Memory size in MB + MrcGfxGttSize GraphicsGttSize; ///< GTT graphics stolen m= emory size in MB + MrcBaseTime BaseTime; ///< RTC base time. + MrcIteration Iteration; ///< Number of iterations = thru the MRC core call table. + MrcMode MrcMode; ///< The control for full = or MiniBIOS MRC. + MrcBootMode BootMode; ///< The requested memory = controller boot mode. + BOOLEAN TxtFlag; ///< Trusted eXecution Tec= hnology flag. + BOOLEAN SetRxDqs32; ///< Set DQS Delay to 32 c= ontrol. + BOOLEAN GfxIsVersatileAcceleration; ///< iGFX engines are in V= ersatile Acceleration + BOOLEAN DDR4MAP; ///< DDR4 PDA Mapping trai= ning control. + POINTER_STRUCT SaMemCfgAddress; ///< Starting address of t= he input parameters to CRC. + UINT32 SaMemCfgSize; ///< The size of the input= parameters to CRC. + UINT32 PciEBaseAddress; ///< define the PciE base = address. + UINT32 MchBarBaseAddress; ///< define the MCH bar ba= se address. + UINT32 SmbusBaseAddress; ///< This field defines th= e smbus base address. + UINT32 GdxcBaseAddress; ///< This field defines th= e GDXC base address. + UINT32 HpetBaseAddress; ///< This field defines th= e hpet base address. + UINT32 MeStolenSize; ///< define the size that = the ME need in MB. + UINT32 MmioSize; ///< define the MMIO size = in MB. + UINT32 TsegSize; ///< TSEG size that requir= e by the system in MB. + UINT32 IedSize; ///< IED size that require= by the system in MB. + UINT32 DprSize; ///< DPR size required by = system in MB. + UINT32 PrmrrSize; ///< Prmrr size required b= y the system in MB. + POINTER_STRUCT SerialBuffer; ///< Pointer to the start = of the serial buffer. + UINT32 SerialBufferSize; ///< The size of the seria= l buffer, in bytes. + UINT32 DebugStream; ///< The debug port pointe= r. + INT32 DebugLevel; ///< Indicates the level o= f debug messaging. + UINT16 VccIomV; ///< VccIO logic voltage i= n mV. + MrcControllerIn Controller[MAX_CONTROLLERS]; ///< The following are con= troller level definitions. + UINT32 HeapBase; ///< Starting address of t= he heap space. + UINT32 HeapSize; ///< Size of the heap spac= e, in bytes. + UINT32 MrcStackTop; ///< Top of the stack at t= he beginning of MRC, for stack usage calculations. + BOOLEAN BdatEnable; ///< Option to enable outp= ut of training results into BDAT. + UINT8 BdatTestType; ///< When BdatEnable is se= t to TRUE, this option selects the type of training results data which will= be populated into BDAT: 0=3DRMT, 1=3DRMT Per Bit, 2=3DMargin 2D. + BOOLEAN LpddrDramOdt; ///< TRUE if LPDDR DRAM OD= T is used - depends on board design + BOOLEAN Ddr3DramOdt; ///< TRUE if DDR3 DRAM OD= T is used - depends on board design + BOOLEAN Ddr4DramOdt; ///< TRUE if DDR4 DRAM OD= T is used - depends on board design + BOOLEAN EnableVrefPwrDn; ///< Setting this limits V= refGen to be off only during CKEPowerDown + BOOLEAN TxEqDis; ///< Disable TX Equalizati= on + BOOLEAN EnVttOdt; ///< Enable VTT Terminatio= n for Data ODT + UINT32 CpuidModel; ///< Unique CPU identifier. + UINT8 CpuidStepping; ///< Revision of the CPU. + UINT8 CpuidSku; ///< SKU of the CPU. + UINT32 SiPreMemPolicyPpi; + TrainingModeType PowerTrainingMode; ///< 0 - Power Training. 1= - Margin Training. + union { + MRC_FUNCTION *Func; ///< External to MRC funct= ion pointers + UINT64 Data; + } Call; + UINT16 RcompResistor[MAX_RCOMP]; ///< Reference RCOMP resis= tors on motherboard + UINT16 RcompTarget[MAX_RCOMP_TARGETS]; ///< RCOMP target values= for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv + UINT32 CleanMemory:1; ///< TRUE to request a mem= ory clean + UINT32 OcSupport:1; ///< TRUE if Overclocking = is enabled in BIOS + UINT32 RsvdBits5:30; + /** + Sets the serial debug message level\n + 0x00 =3D Disabled\n + 0x01 =3D Errors only\n + 0x02 =3D Errors and Warnings\n + 0x03 =3D Errors, Warnings, and Info\n + 0x04 =3D Errors, Warnings, Info, and Events\n + 0x05 =3D Displays Memory Init Execution Time Summary only\n + **/ + UINT8 SerialDebugLevel; +} MrcInput; + +typedef struct { + UINT32 Size; ///< The size of this structure, in bytes. Must be= the first entry in this structure. + MrcSaveHeader Header; ///< The header portion of the MRC saved data. + MrcSaveData Data; ///< The data portion of the MRC saved data. +} MrcSave; + +typedef struct { + // Global variables that will be copied to the HOB follow. + UINT8 MrcDataString[4]; ///< Beginning of global data marker, sta= rts with "MRC". Must be the first entry in this structure. + UINT32 MrcDataSize; ///< The size of the MRC global data area= , in bytes. Must be the second entry in this structure. + MrcSave Save; ///< System specific save variables. + MrcInput Inputs; ///< System specific input variables. + MrcOutput Outputs; ///< System specific output variables. + + // Global variables that will remain internal to the MRC library follow. + union { + void *Internal; ///< System specific output variables that remain in= ternal to the library. + UINT64 Data; + } IntOutputs; +} MrcParameters; + +#pragma pack (pop) +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Incl= ude/Coffeelake/MrcRmtData.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgen= t/MemoryInit/Include/Coffeelake/MrcRmtData.h new file mode 100644 index 0000000000..9dd9b096ba --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Cof= feelake/MrcRmtData.h @@ -0,0 +1,203 @@ +/** @file + Copies the memory related timing and configuration information into the + Compatible BIOS data (BDAT) table. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MrcRmtData_h_ +#define _MrcRmtData_h_ + +#include "MrcTypes.h" + +#define VDD_1_350 1350 ///< VDD in milliv= olts +#define VDD_1_500 1500 ///< VDD in milliv= olts +#define PI_STEP_BASE 2048 ///< Magic number = from spec +#define PI_STEP_INTERVAL 128 ///< tCK is split = into this amount of intervals +#define PI_STEP ((PI_STEP_BASE) / (PI_STEP_INTERVAL)) +#define VREF_STEP_BASE 100 ///< Magic number = from spec +#define TX_VREF_STEP 7800 ///< TX Vref step = in microvolts +#define TX_VREF(VDD) (((TX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)= ) ///< VDD passed in is in millivolts +#define RX_VREF_STEP 8000 ///< TX Vref step = in microvolts +#define RX_VREF(VDD) (((RX_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)= ) ///< VDD passed in is in millivolts +#define CA_VREF_STEP 8000 ///< TX Vref step = in microvolts +#define CA_VREF(VDD) (((CA_VREF_STEP) * (VREF_STEP_BASE)) / (VDD)= ) ///< VDD passed in is in millivolts + +#define MAX_SPD_RMT 512 ///< The maximum a= mount of data, in bytes, in an SPD structure. +#define RMT_PRIMARY_VERSION 4 ///< The BDAT stru= cture that is currently supported. +#define RMT_SECONDARY_VERSION 0 ///< The BDAT stru= cture that is currently supported. +#define MAX_MODE_REGISTER 7 ///< Number of mod= e registers +#define MAX_DRAM_DEVICE 9 ///< Maximum numbe= r of memory devices +#define MAX_2D_EYE_TYPE 2 ///< Maximum numbe= r of supported Margin 2D Eye Types +#define MAX_2D_EYE_OFFSETS 7 ///< Number of 2D = Eye Offsets + +// +// Warning: Bdat4.h has its own copy of this #define +// make sure to change it in both places +// +#define MAX_SCHEMA_LIST_LENGTH (10) + + +#ifdef BDAT_SUPPORT +/* + BSSA result Memory Schema GUID + {8F4E928-0F5F-46D4-8410-479FDA279DB6} +*/ +extern EFI_GUID gSsaBiosResultsGuid; +/* + RMT Results Metadata GUID + {02CB1552-D659-4232-B51F-CAB1E11FCA87} +*/ +extern EFI_GUID gRmtResultMetadataGuid; +/* + RMT Results Columns GUID + {0E60A1EB-331F-42A1-9DE7-453E84761154} +*/ +extern EFI_GUID gRmtResultColumnsGuid; + +/* +Margin2D Results Metadata GUID +{48265582-8E49-4AC7-AA06-E1B9A74C9716} +*/ +extern EFI_GUID gMargin2DResultMetadataGuid; +/* +Margin2D Results Columns GUID +{91A449EC-8A4A-4736-AD71-A3F6F6D752D9} +*/ +extern EFI_GUID gMargin2DResultColumnsGuid; + +#endif +/* + GUID for Schema List HOB + This is private GUID used by MemoryInit internally. + {3047C2AC-5E8E-4C55-A1CB-EAAD0A88861B} +*/ +extern EFI_GUID gMrcSchemaListHobGuid; + +#pragma pack(push, 1) + + +/// +/// SSA results buffer header. +/// +typedef struct { + UINT32 Revision; + BOOLEAN TransferMode; + struct { + UINT32 Reserved; + UINT32 MetadataSize; + EFI_GUID MetadataType; + } MdBlock; + struct { + UINT32 Reserved; + EFI_GUID ResultType; + UINT32 ResultElementSize; + INT32 ResultCapacity; + INT32 ResultElementCount; + } RsBlock; +} RESULTS_DATA_HDR; + +// start auto-generated by the BSSA CCK sourced from the result xml files. +typedef enum { + DisableScrambler =3D 0, + EnableScrambler =3D 1, + DontTouchScrambler =3D 2, + SCRAMBLER_OVERRIDE_MODE_DELIM =3D MRC_INT32_MAX +} SCRAMBLER_OVERRIDE_MODE; + +typedef struct _RMT_RESULT_METADATA { + BOOLEAN EnableCtlAllMargin; + UINT16 SinglesBurstLength; + UINT32 SinglesLoopCount; + UINT16 TurnaroundsBurstLength; + UINT32 TurnaroundsLoopCount; + SCRAMBLER_OVERRIDE_MODE ScramblerOverrideMode; + UINT8 PiStepUnit[2]; + UINT16 RxVrefStepUnit[2]; + UINT16 TxVrefStepUnit[2][2]; + UINT16 CmdVrefStepUnit[2][2]; + UINT8 MajorVer; + UINT8 MinorVer; + UINT8 RevVer; + UINT32 BuildVer; + UINT16 ResultEleCount; +} RMT_RESULT_METADATA; + + +typedef struct _RMT_RESULT_ROW_HEADER { + UINT32 ResultType : 5; + UINT32 Socket : 3; + UINT32 Controller : 2; + UINT32 Channel : 3; + UINT32 DimmA : 1; + UINT32 RankA : 3; + UINT32 DimmB : 1; + UINT32 RankB : 3; + UINT32 Lane : 8; + UINT32 IoLevel : 1; + UINT32 Reserved : 2; +} RMT_RESULT_ROW_HEADER; + +typedef struct _RMT_RESULT_COLUMNS { + RMT_RESULT_ROW_HEADER Header; + UINT8 Margin[4][2]; +} RMT_RESULT_COLUMNS; + +// end of auto-generated by the BSSA CCK sourced from the result xml files. + +typedef struct _BASE_RMT_RESULT { + RESULTS_DATA_HDR ResultsHeader; + RMT_RESULT_METADATA Metadata; + RMT_RESULT_COLUMNS Rows[1]; +} BASE_RMT_RESULT; + + +typedef struct { + UINT32 Data1; + UINT16 Data2; + UINT16 Data3; + UINT8 Data4[8]; +} BDAT_EFI_GUID; + +typedef struct { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} BDAT_HOB_GENERIC_HEADER; + +typedef struct { + BDAT_HOB_GENERIC_HEADER Header; + BDAT_EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} BDAT_HOB_GUID_TYPE; + +typedef struct { + BDAT_EFI_GUID SchemaId; ///< The G= UID uniquely identifies the format of the data contained within the structu= re. + UINT32 DataSize; ///< The t= otal size of the memory block, including both the header as well as the sch= ema specific data. + UINT16 Crc16; ///< Crc16= is computed in the same manner as the field in the BDAT_HEADER_STRUCTURE. +} MRC_BDAT_SCHEMA_HEADER_STRUCTURE; + +typedef struct { + MRC_BDAT_SCHEMA_HEADER_STRUCTURE SchemaHeader; ///< The s= chema header. + BASE_RMT_RESULT RMT_RESULTS_WITH_META_COLUMNS; +} BDAT_MEMORY_DATA_STRUCTURE; + +typedef struct { + BDAT_HOB_GUID_TYPE HobGuidType; + BDAT_MEMORY_DATA_STRUCTURE MemorySchema; +} BDAT_MEMORY_DATA_HOB; + +#pragma pack (pop) + +typedef struct { + BDAT_HOB_GUID_TYPE HobGuidType; + UINT16 SchemaHobCount; + UINT16 Reserved; + BDAT_EFI_GUID SchemaHobGuids[MAX_SCHEMA_LIST_LENGTH]; +} MRC_BDAT_SCHEMA_LIST_HOB; + +#endif //_MrcRmtData_h_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Incl= ude/Coffeelake/MrcSpdData.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgen= t/MemoryInit/Include/Coffeelake/MrcSpdData.h new file mode 100644 index 0000000000..45de5084c0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Cof= feelake/MrcSpdData.h @@ -0,0 +1,1167 @@ +/** @file + SPD data format header file. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MrcSpdData_h_ +#define _MrcSpdData_h_ +#pragma pack (push, 1) + +#include "MrcTypes.h" + +#define MAX_XMP_PROFILES (2) +#define SPD3_MANUF_SIZE (SPD3_MANUF_END - SPD3_MANUF_START + 1) ///< T= he size of the SPD manufacturing data. +#define SPD4_MANUF_SIZE (SPD4_MANUF_END - SPD4_MANUF_START + 1) ///< T= he size of the SPD manufacturing data. +#define SPDLP_MANUF_SIZE (SPDLP_MANUF_END - SPDLP_MANUF_START + 1) ///< T= he size of the SPD manufacturing data + +typedef union { + struct { + UINT8 BytesUsed : 4; ///< Bits 3:0 + UINT8 BytesTotal : 3; ///< Bits 6:4 + UINT8 CrcCoverage : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_DEVICE_DESCRIPTION_STRUCT; + +typedef union { + struct { + UINT8 Minor : 4; ///< Bits 3:0 + UINT8 Major : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_REVISION_STRUCT; + +typedef union { + struct { + UINT8 Type : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_DRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 ModuleType : 4; ///< Bits 3:0 + UINT8 : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_MODULE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 3; ///< Bits 6:4 + UINT8 : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 ColumnAddress : 3; ///< Bits 2:0 + UINT8 RowAddress : 3; ///< Bits 5:3 + UINT8 : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_SDRAM_ADDRESSING_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_50 : 1; ///< Bits 0:0 + UINT8 OperationAt1_35 : 1; ///< Bits 1:1 + UINT8 OperationAt1_25 : 1; ///< Bits 2:2 + UINT8 : 5; ///< Bits 7:3 + } Bits; + UINT8 Data; +} SPD_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 SdramDeviceWidth : 3; ///< Bits 2:0 + UINT8 RankCount : 3; ///< Bits 5:3 + UINT8 : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_MODULE_ORGANIZATION_STRUCT; + +typedef union { + struct { + UINT8 PrimaryBusWidth : 3; ///< Bits 2:0 + UINT8 BusWidthExtension : 2; ///< Bits 4:3 + UINT8 : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT; + +typedef union { + struct { + UINT8 Divisor : 4; ///< Bits 3:0 + UINT8 Dividend : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_FINE_TIMEBASE_STRUCT; + +typedef union { + struct { + UINT8 Dividend : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT; + +typedef union { + struct { + UINT8 Divisor : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT; + +typedef struct { + SPD_MEDIUM_TIMEBASE_DIVIDEND_STRUCT Dividend; ///< Medium Timebase (MTB)= Dividend + SPD_MEDIUM_TIMEBASE_DIVISOR_STRUCT Divisor; ///< Medium Timebase (MTB)= Divisor +} SPD_MEDIUM_TIMEBASE; + +typedef union { + struct { + UINT8 tCKmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TCK_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT16 CL4 : 1; ///< Bits 0:0 + UINT16 CL5 : 1; ///< Bits 1:1 + UINT16 CL6 : 1; ///< Bits 2:2 + UINT16 CL7 : 1; ///< Bits 3:3 + UINT16 CL8 : 1; ///< Bits 4:4 + UINT16 CL9 : 1; ///< Bits 5:5 + UINT16 CL10 : 1; ///< Bits 6:6 + UINT16 CL11 : 1; ///< Bits 7:7 + UINT16 CL12 : 1; ///< Bits 8:8 + UINT16 CL13 : 1; ///< Bits 9:9 + UINT16 CL14 : 1; ///< Bits 10:10 + UINT16 CL15 : 1; ///< Bits 11:11 + UINT16 CL16 : 1; ///< Bits 12:12 + UINT16 CL17 : 1; ///< Bits 13:13 + UINT16 CL18 : 1; ///< Bits 14:14 + UINT16 : 1; ///< Bits 15:15 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + UINT8 tAAmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TAA_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWRmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TWR_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRCDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRCD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRRDmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRRD_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRPmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRP_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRPab : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRP_AB_MTB_STRUCT; + +typedef union { + struct { + INT8 tRPabFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRP_AB_FTB_STRUCT; + +typedef union { + struct { + UINT8 tRPpb : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRP_PB_MTB_STRUCT; + +typedef union { + struct { + INT8 tRPpbFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRP_PB_FTB_STRUCT; + +typedef union { + struct { + UINT16 tRFCab : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_TRFC_AB_MTB_STRUCT; + +typedef union { +struct { + UINT16 tRFCpb : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_TRFC_PB_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRASminUpper : 4; ///< Bits 3:0 + UINT8 tRCminUpper : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_TRAS_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRASmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRAS_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRCmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT16 tRFCmin : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_TRFC_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tWTRmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TWTR_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tRTPmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TRTP_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tFAWminUpper : 4; ///< Bits 3:0 + UINT8 : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_TFAW_MIN_MTB_UPPER_STRUCT; + +typedef union { + struct { + UINT8 tFAWmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TFAW_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 tCWLmin : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_TCWL_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 NMode : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_SYSTEM_COMMAND_RATE_STRUCT; + +typedef union { + struct { + UINT16 tREFImin : 16; ///< Bits 15:0 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_TREFI_MIN_MTB_STRUCT; + +typedef union { + struct { + UINT8 RZQ6 : 1; ///< Bits 0:0 + UINT8 RZQ7 : 1; ///< Bits 1:1 + UINT8 : 5; ///< Bits 6:2 + UINT8 DllOff : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_SDRAM_OPTIONAL_FEATURES_STRUCT; + +typedef union { + struct { + UINT8 ExtendedTemperatureRange : 1; ///< Bits 0:0 + UINT8 ExtendedTemperatureRefreshRate : 1; ///< Bits 1:1 + UINT8 AutoSelfRefresh : 1; ///< Bits 2:2 + UINT8 OnDieThermalSensor : 1; ///< Bits 3:3 + UINT8 : 3; ///< Bits 6:4 + UINT8 PartialArraySelfRefresh : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 ThermalSensorAccuracy : 7; ///< Bits 6:0 + UINT8 ThermalSensorPresence : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_MODULE_THERMAL_SENSOR_STRUCT; + +typedef union { + struct { + UINT8 NonStandardDeviceDescription : 7; ///< Bits 6:0 + UINT8 SdramDeviceType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_SDRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_AUTO_SELF_REFRESH_PERF_STRUCT; + +typedef union { + struct { + INT8 tCKminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TCK_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tAAminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TAA_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRCD_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRPminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRP_MIN_FTB_STRUCT; + +typedef union { + struct { + INT8 tRCminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRC_MIN_FTB_STRUCT; + +typedef union { + struct { + UINT8 tMACencoding : 4; ///< Bits 3:0 + UINT8 tMAWencoding : 2; ///< Bits 5:4 + UINT8 Reserved : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_PTRR_SUPPORT_STRUCT; + +typedef union { + struct { + INT8 tRRDminFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_TRRD_MIN_FTB_STRUCT; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_UNBUF_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_UNBUF_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_UNBUF_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 MappingRank1 : 1; ///< Bits 0:0 + UINT8 : 7; ///< Bits 7:1 + } Bits; + UINT8 Data; +} SPD_UNBUF_ADDRESS_MAPPING; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_RDIMM_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_RDIMM_MODULE_NOMINAL_THICKNESS; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_RDIMM_REFERENCE_RAW_CARD; + +typedef union { + struct { + UINT8 RegisterCount : 2; ///< Bits 1:0 + UINT8 DramRowCount : 2; ///< Bits 3:2 + UINT8 : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_RDIMM_MODULE_ATTRIBUTES; + +typedef union { + struct { + UINT16 ContinuationCount : 7; ///< Bits 6:0 + UINT16 ContinuationParity : 1; ///< Bits 7:7 + UINT16 LastNonZeroByte : 8; ///< Bits 15:8 + } Bits; + UINT16 Data; + UINT8 Data8[2]; +} SPD_MANUFACTURER_ID_CODE; + +typedef struct { + UINT8 Year; ///< Year represented in BC= D (00h =3D 2000) + UINT8 Week; ///< Year represented in BC= D (47h =3D week 47) +} SPD_MANUFACTURING_DATE; + +typedef union { + UINT32 Data; + UINT16 SerialNumber16[2]; + UINT8 SerialNumber8[4]; +} SPD_MANUFACTURER_SERIAL_NUMBER; + +typedef struct { + UINT8 Location; ///< Module Manufacturing L= ocation +} SPD_MANUFACTURING_LOCATION; + +typedef struct { + SPD_MANUFACTURER_ID_CODE IdCode; ///< Modul= e Manufacturer ID Code + SPD_MANUFACTURING_LOCATION Location; ///< Modul= e Manufacturing Location + SPD_MANUFACTURING_DATE Date; ///< Modul= e Manufacturing Year, in BCD (range: 2000-2255) + SPD_MANUFACTURER_SERIAL_NUMBER SerialNumber; ///< Modul= e Serial Number +} SPD_UNIQUE_MODULE_ID; + +typedef union { + UINT16 Crc[1]; + UINT8 Data8[2]; +} SPD_CYCLIC_REDUNDANCY_CODE; + +typedef union { + struct { + UINT8 ProfileEnable1 : 1; ///< Bi= ts 0:0 + UINT8 ProfileEnable2 : 1; ///< Bi= ts 1:1 + UINT8 ProfileConfig1 : 2; ///< Bi= ts 3:2 + UINT8 ProfileConfig2 : 2; ///< Bi= ts 5:4 + UINT8 : 2; ///< Bi= ts 7:6 + } Bits; + UINT8 Data; +} SPD_XMP_ORG_CONFIG; + +typedef struct { + UINT16 XmpId; ///< 176-1= 77 XMP Identification String + SPD_XMP_ORG_CONFIG XmpOrgConf; ///< 178 X= MP Organization & Configuration + SPD_REVISION_STRUCT XmpRevision; ///< 179 X= MP Revision + SPD_MEDIUM_TIMEBASE MediumTimeBase[MAX_XMP_PROFILES]; //= /< 180-183 Medium Timebase (MTB) + SPD_FINE_TIMEBASE_STRUCT FineTimeBase; ///< 184 F= ine Timebase (FTB) Dividend / Divisor +} SPD_EXTREME_MEMORY_PROFILE_HEADER; + +typedef union { + struct { + UINT8 Decimal : 5; + UINT8 Integer : 2; + UINT8 : 1; + } Bits; + UINT8 Data; +} SPD_VDD_VOLTAGE_LEVEL_STRUCT; + +typedef union { + struct { + UINT8 Decimal : 7; + UINT8 Integer : 1; + } Bits; + UINT8 Data; +} SPD_VDD_VOLTAGE_LEVEL_STRUCT_2_0; + +typedef union { + struct { + UINT8 Fine : 2; ///< Bits 1:0 + UINT8 Medium : 2; ///< Bits 3:2 + UINT8 : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD4_TIMEBASE_STRUCT; + +typedef union { + struct { + UINT32 CL7 : 1; ///< Bits 0:0 + UINT32 CL8 : 1; ///< Bits 1:1 + UINT32 CL9 : 1; ///< Bits 2:2 + UINT32 CL10 : 1; ///< Bits 3:3 + UINT32 CL11 : 1; ///< Bits 4:4 + UINT32 CL12 : 1; ///< Bits 5:5 + UINT32 CL13 : 1; ///< Bits 6:6 + UINT32 CL14 : 1; ///< Bits 7:7 + UINT32 CL15 : 1; ///< Bits 8:8 + UINT32 CL16 : 1; ///< Bits 9:9 + UINT32 CL17 : 1; ///< Bits 10:10 + UINT32 CL18 : 1; ///< Bits 11:11 + UINT32 CL19 : 1; ///< Bits 12:12 + UINT32 CL20 : 1; ///< Bits 13:13 + UINT32 CL21 : 1; ///< Bits 14:14 + UINT32 CL22 : 1; ///< Bits 15:15 + UINT32 CL23 : 1; ///< Bits 16:16 + UINT32 CL24 : 1; ///< Bits 17:17 + UINT32 : 14; ///< Bits 31:18 + } Bits; + UINT32 Data; + UINT16 Data16[2]; + UINT8 Data8[4]; +} SPD4_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef struct { + SPD_VDD_VOLTAGE_LEVEL_STRUCT Vdd; ///< 185, = 220 XMP Module VDD Voltage Level + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 186, = 221 XMP SDRAM Minimum Cycle Time (tCKmin) + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 187, = 222 XMP Minimum CAS Latency Time (tAAmin) + SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 188-1= 89, 223-224 XMP CAS Latencies Supported, Least Significant Byte + SPD_TCWL_MIN_MTB_STRUCT tCWLmin; ///< 190, = 225 XMP Minimum CAS Write Latency Time (tCWLmin) + SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 191, = 226 XMP Minimum Row Precharge Delay Time (tRPmin) + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 192, = 227 XMP Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 193, = 228 XMP Minimum Write Recovery Time (tWRmin) + SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 194, = 229 XMP Upper Nibbles for tRAS and tRC + SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 195, = 230 XMP Minimum Active to Precharge Delay Time (tRASmin), Least Significant= Byte + SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 196, = 231 XMP Minimum Active to Active/Refresh Delay Time (tRCmin), Least Signifi= cant Byte + SPD_TREFI_MIN_MTB_STRUCT tREFImin; ///< 197-1= 98, 232-233 XMP Maximum tREFI Time (Average Periodic Refresh Interval), Lea= st Significant Byte + SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 199-2= 00, 234-235 XMP Minimum Refresh Recovery Delay Time (tRFCmin), Least Signif= icant Byte + SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 201, = 236 XMP Minimum Internal Read to Precharge Command Delay Time (tRTPmin) + SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 202, = 237 XMP Minimum Row Active to Row Active Delay Time (tRRDmin) + SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 203, = 238 XMP Upper Nibble for tFAW + SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 204, = 239 XMP Minimum Four Activate Window Delay Time (tFAWmin) + SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 205, = 240 XMP Minimum Internal Write to Read Command Delay Time (tWTRmin) + UINT8 Reserved1[207 - 206 + 1]; ///< 206-2= 07, 241-242 XMP Reserved + SPD_SYSTEM_COMMAND_RATE_STRUCT SystemCmdRate; ///< 208, = 243 XMP System ADD/CMD Rate (1N or 2N mode) + SPD_AUTO_SELF_REFRESH_PERF_STRUCT AsrPerf; ///< 209, = 244 XMP SDRAM Auto Self Refresh Performance (Sub 1x Refresh and IDD6 impact) + UINT8 VoltageLevel; ///< 210, = 245 XMP Memory Controller Voltage Level + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 211, = 246 XMP Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 212, = 247 XMP Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 213, = 248 XMP Minimum Row Precharge Delay Time (tRPmin) + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 214, = 249 XMP Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 215, = 250 XMP Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + UINT8 Reserved2[218 - 216 + 1]; ///< 216-2= 18, 251-253 XMP Reserved + UINT8 VendorPersonality; ///< 219, = 254 XMP Vendor Personality +} SPD_EXTREME_MEMORY_PROFILE_DATA; + +typedef struct { + SPD_EXTREME_MEMORY_PROFILE_HEADER Header; ///< 176-1= 84 XMP header + SPD_EXTREME_MEMORY_PROFILE_DATA Data[MAX_XMP_PROFILES]; ///< 185-2= 54 XMP profiles +} SPD_EXTREME_MEMORY_PROFILE; + +typedef struct { + UINT16 XmpId; ///< 3= 84-385 XMP Identification String + SPD_XMP_ORG_CONFIG XmpOrgConf; ///< 3= 86 XMP Organization & Configuration + SPD_REVISION_STRUCT XmpRevision; ///< 3= 87 XMP Revision + SPD4_TIMEBASE_STRUCT TimeBase[MAX_XMP_PROFILES]; ///< 3= 88-389 Medium and Fine Timebase + UINT8 Reserved[392 - 390 + 1]; ///< 39= 0-392 Reserved +} SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0; + +typedef struct { + SPD_VDD_VOLTAGE_LEVEL_STRUCT_2_0 Vdd; ///< 393, = 440 XMP Module VDD Voltage Level + UINT8 Reserved1[395 - 394 + 1]; ///< 394-3= 95, 441-442 XMP Reserved + SPD_TCK_MIN_MTB_STRUCT tCKAVGmin; ///< 396, = 443 XMP SDRAM Minimum Cycle Time (tCKAVGmin) + SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 397-4= 00, 444-447 XMP CAS Latencies Supported + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 401, = 448 XMP Minimum CAS Latency Time (tAAmin) + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 402, = 449 XMP Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 403, = 450 XMP Minimum Row Precharge Delay Time (tRPmin) + SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 404, = 451 XMP Upper Nibbles for tRAS and tRC + SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 405, = 452 XMP Minimum Active to Precharge Delay Time (tRASmin), Least Significant= Byte + SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 406, = 453 XMP Minimum Active to Active/Refresh Delay Time (tRCmin), Least Signifi= cant Byte + SPD_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 407-4= 08, 454-455 XMP Minimum Refresh Recovery Delay Time (tRFC1min) + SPD_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 409-4= 10, 456-457 XMP Minimum Refresh Recovery Delay Time (tRFC2min) + SPD_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 411-4= 12, 458-459 XMP Minimum Refresh Recovery Delay Time (tRFC4min) + SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 413, = 460 Upper Nibble for tFAW + SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 414, = 461 Minimum Four Activate Window Delay Time (tFAWmin) + SPD_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 415, = 462 Minimum Activate to Activate Delay Time (tRRD_Smin), different bank gro= up + SPD_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 416, = 463 Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group + UINT8 Reserved2[424 - 417 + 1]; ///< 417-4= 24, 464-471 XMP Reserved + SPD_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 425, = 472 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), di= fferent bank group + SPD_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 426, = 473 Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), sa= me bank group + SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 427, = 474 Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 428, = 475 Minimum Row Precharge Delay Time (tRPmin) + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 429, = 476 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 430, = 477 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_TCK_MIN_FTB_STRUCT tCKAVGminFine; ///< 431, = 478 Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmin) + UINT8 Reserved3[439 - 432 + 1]; ///< 432-4= 39, 479-486 XMP Reserved +} SPD_EXTREME_MEMORY_PROFILE_DATA_2_0; + +typedef struct { + SPD_EXTREME_MEMORY_PROFILE_HEADER_2_0 Header; ///= < 384-392 XMP header + SPD_EXTREME_MEMORY_PROFILE_DATA_2_0 Data[MAX_XMP_PROFILES]; ///= < 393-486 XMP profiles +} SPD_EXTREME_MEMORY_PROFILE_2_0; + +typedef struct { + SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 N= umber of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD_REVISION_STRUCT Revision; ///< 1 S= PD Revision + SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 D= RAM Device Type + SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 M= odule Type + SPD_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 S= DRAM Density and Banks + SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 S= DRAM Addressing + SPD_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 6 M= odule Nominal Voltage, VDD + SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 7 M= odule Organization + SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 8 M= odule Memory Bus Width + SPD_FINE_TIMEBASE_STRUCT FineTimebase; ///< 9 F= ine Timebase (FTB) Dividend / Divisor + SPD_MEDIUM_TIMEBASE MediumTimebase; ///< 10-11= Medium Timebase (MTB) Dividend + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 12 S= DRAM Minimum Cycle Time (tCKmin) + UINT8 Reserved1; ///< 13 R= eserved + SPD_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 14-15= CAS Latencies Supported + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 16 M= inimum CAS Latency Time (tAAmin) + SPD_TWR_MIN_MTB_STRUCT tWRmin; ///< 17 M= inimum Write Recovery Time (tWRmin) + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 18 M= inimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRRD_MIN_MTB_STRUCT tRRDmin; ///< 19 M= inimum Row Active to Row Active Delay Time (tRRDmin) + SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 20 M= inimum Row Precharge Delay Time (tRPmin) + SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 21 U= pper Nibbles for tRAS and tRC + SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 22 M= inimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 23 M= inimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte + SPD_TRFC_MIN_MTB_STRUCT tRFCmin; ///< 24-25= Minimum Refresh Recovery Delay Time (tRFCmin) + SPD_TWTR_MIN_MTB_STRUCT tWTRmin; ///< 26 M= inimum Internal Write to Read Command Delay Time (tWTRmin) + SPD_TRTP_MIN_MTB_STRUCT tRTPmin; ///< 27 M= inimum Internal Read to Precharge Command Delay Time (tRTPmin) + SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 28 U= pper Nibble for tFAW + SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 29 M= inimum Four Activate Window Delay Time (tFAWmin) + SPD_SDRAM_OPTIONAL_FEATURES_STRUCT SdramOptionalFeatures; ///< 30 S= DRAM Optional Features + SPD_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 31 S= DRAMThermalAndRefreshOptions + SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 32 M= odule Thermal Sensor + SPD_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 33 S= DRAM Device Type + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 34 F= ine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 35 F= ine Offset for Minimum CAS Latency Time (tAAmin) + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 36 F= ine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 37 M= inimum Row Precharge Delay Time (tRPmin) + SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 38 F= ine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + SPD_TRP_AB_MTB_STRUCT tRPab; ///< 39 M= inimum Row Precharge Delay Time for all banks (tRPab) + SPD_TRP_AB_FTB_STRUCT tRPabFine; ///< 40 F= ine Offset for Minimum Row Precharge Delay Time for all banks (tRPab) + SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///< 41 - = pTRR support with TMAC value + UINT8 Reserved3[59 - 42 + 1]; ///< 42 - = 59 Reserved +} SPD_GENERAL_SECTION; + +typedef struct { + SPD_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Mo= dule Nominal Height + SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Mo= dule Maximum Thickness + SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Re= ference Raw Card Used + SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 63 Ad= dress Mapping from Edge Connector to DRAM + UINT8 Reserved[116 - 64 + 1]; ///< 64-11= 6 Reserved +} SPD_MODULE_UNBUFFERED; + +typedef struct { + SPD_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 60 Mo= dule Nominal Height + SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 61 Mo= dule Maximum Thickness + SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 62 Re= ference Raw Card Used + SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 63 DI= MM Module Attributes + UINT8 Reserved[116 - 64 + 1]; ///< 64-11= 6 Reserved +} SPD_MODULE_REGISTERED; + +typedef union { + SPD_MODULE_UNBUFFERED Unbuffered; + SPD_MODULE_REGISTERED Registered; +} SPD_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[145 - 128 + 1]; /= //< 128-145 Module Part Number +} SPD_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ModuleRevisionCode[147 - 146 + 1]; /= //< 146-147 Module Revision Code +} SPD_MODULE_REVISION_CODE; + +typedef struct { + UINT8 ManufactureSpecificData[175 - 150 + 1]; /= //< 150-175 Manufacturer's Specific Data +} SPD_MANUFACTURE_SPECIFIC; + +/// +/// DDR3 Serial Presence Detect structure +/// +typedef struct { + SPD_GENERAL_SECTION General; ///<= 0-59 General Section + SPD_MODULE_SPECIFIC Module; ///<= 60-116 Module-Specific Section + SPD_UNIQUE_MODULE_ID ModuleId; ///<= 117-125 Unique Module ID + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///<= 126-127 Cyclical Redundancy Code (CRC) + SPD_MODULE_PART_NUMBER ModulePartNumber; ///<= 128-145 Module Part Number + SPD_MODULE_REVISION_CODE ModuleRevisionCode; ///<= 146-147 Module Revision Code + SPD_MANUFACTURER_ID_CODE DramIdCode; ///<= 148-149 Dram Manufacturer ID Code + SPD_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///<= 150-175 Manufacturer's Specific Data + SPD_EXTREME_MEMORY_PROFILE Xmp; ///<= 176-254 Intel(r) Extreme Memory Profile support + UINT8 Reserved; ///<= 255 Reserved +} MrcSpdDdr3; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 2; ///< Bits 5:4 + UINT8 BankGroup : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD4_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramDeviceType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD4_SDRAM_DEVICE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_20 : 1; ///< Bits 0:0 + UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 + UINT8 : 6; ///< Bits 7:2 + } Bits; + UINT8 Data; +} SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 tCKmax : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_TCK_MAX_MTB_STRUCT; + +typedef union { + struct { + INT8 tCKmaxFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD4_TCK_MAX_FTB_STRUCT; + +typedef union { + struct { + UINT8 : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD4_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD4_UNBUF_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD4_RDIMM_MODULE_NOMINAL_HEIGHT; + +typedef struct { + SPD_DEVICE_DESCRIPTION_STRUCT Description; ///< 0 = Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 1, 2 + SPD_REVISION_STRUCT Revision; ///< 1 = SPD Revision + SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///< 2 = DRAM Device Type + SPD_MODULE_TYPE_STRUCT ModuleType; ///< 3 = Module Type + SPD4_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///< 4 = SDRAM Density and Banks + SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///< 5 = SDRAM Addressing + SPD4_SDRAM_DEVICE_TYPE_STRUCT SdramDeviceType; ///< 6 = SDRAM Device Type + SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///< 7 = pTRR support with TMAC value + SPD4_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///< 8 = SDRAM Thermal and Refresh Options + UINT8 Reserved0[10 - 9 + 1]; ///< 9-10 = Reserved + SPD4_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///< 11 = Module Nominal Voltage, VDD + SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///< 12 = Module Organization + SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///< 13 = Module Memory Bus Width + SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///< 14 = Module Thermal Sensor + UINT8 Reserved1[16 - 15 + 1]; ///< 15-16= Reserved + SPD4_TIMEBASE_STRUCT Timebase; ///< 17 = Timebases + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///< 18 = SDRAM Minimum Cycle Time (tCKmin) + SPD4_TCK_MAX_MTB_STRUCT tCKmax; ///< 19 = SDRAM Maximum Cycle Time (tCKmax) + SPD4_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///< 20-23= CAS Latencies Supported + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///< 24 = Minimum CAS Latency Time (tAAmin) + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///< 25 = Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRP_MIN_MTB_STRUCT tRPmin; ///< 26 = Minimum Row Precharge Delay Time (tRPmin) + SPD_TRAS_TRC_MIN_MTB_STRUCT tRASMintRCMinUpper; ///< 27 = Upper Nibbles for tRAS and tRC + SPD_TRAS_MIN_MTB_STRUCT tRASmin; ///< 28 = Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte + SPD_TRC_MIN_MTB_STRUCT tRCmin; ///< 29 = Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant = Byte + SPD_TRFC_MIN_MTB_STRUCT tRFC1min; ///< 30-31= Minimum Refresh Recovery Delay Time (tRFC1min) + SPD_TRFC_MIN_MTB_STRUCT tRFC2min; ///< 32-33= Minimum Refresh Recovery Delay Time (tRFC2min) + SPD_TRFC_MIN_MTB_STRUCT tRFC4min; ///< 34-35= Minimum Refresh Recovery Delay Time (tRFC4min) + SPD_TFAW_MIN_MTB_UPPER_STRUCT tFAWMinUpper; ///< 36 = Upper Nibble for tFAW + SPD_TFAW_MIN_MTB_STRUCT tFAWmin; ///< 37 = Minimum Four Activate Window Delay Time (tFAWmin) + SPD_TRRD_MIN_MTB_STRUCT tRRD_Smin; ///< 38 = Minimum Activate to Activate Delay Time (tRRD_Smin), different bank group + SPD_TRRD_MIN_MTB_STRUCT tRRD_Lmin; ///< 39 = Minimum Activate to Activate Delay Time (tRRD_Lmin), same bank group + UINT8 Reserved2[117 - 40 + 1]; ///< 40-11= 7 Reserved + SPD_TRRD_MIN_FTB_STRUCT tRRD_LminFine; ///< 118 = Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Lmin), dif= ferent bank group + SPD_TRRD_MIN_FTB_STRUCT tRRD_SminFine; ///< 119 = Fine Offset for Minimum Activate to Activate Delay Time (tRRD_Smin), sam= e bank group + SPD_TRC_MIN_FTB_STRUCT tRCminFine; ///< 120 = Fine Offset for Minimum Active to Active/Refresh Delay Time (tRCmin) + SPD_TRP_MIN_FTB_STRUCT tRPminFine; ///< 121 = Minimum Row Precharge Delay Time (tRPmin) + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///< 122 = Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///< 123 = Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD4_TCK_MAX_FTB_STRUCT tCKmaxFine; ///< 124 = Fine Offset for SDRAM Minimum Cycle Time (tCKmax) + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///< 125 = Fine Offset for SDRAM Maximum Cycle Time (tCKmin) + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 126-1= 27 Cyclical Redundancy Code (CRC) +} SPD4_BASE_SECTION; + +typedef struct { + SPD4_UNBUF_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 = Module Nominal Height + SPD_UNBUF_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 = Module Maximum Thickness + SPD_UNBUF_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 = Reference Raw Card Used + SPD_UNBUF_ADDRESS_MAPPING AddressMappingEdgeConn; ///< 131 = Address Mapping from Edge Connector to DRAM + UINT8 Reserved[253 - 132 + 1]; ///< 132-2= 53 Reserved + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-2= 55 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_UNBUFFERED; + +typedef struct { + SPD4_RDIMM_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 128 = Module Nominal Height + SPD_RDIMM_MODULE_NOMINAL_THICKNESS ModuleMaximumThickness; ///< 129 = Module Maximum Thickness + SPD_RDIMM_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 130 = Reference Raw Card Used + SPD_RDIMM_MODULE_ATTRIBUTES DimmModuleAttributes; ///< 131 = DIMM Module Attributes + UINT8 Reserved[253 - 132 + 1]; ///< 253-1= 32 Reserved + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 254-2= 55 Cyclical Redundancy Code (CRC) +} SPD4_MODULE_REGISTERED; + +typedef union { + SPD4_MODULE_UNBUFFERED Unbuffered; ///< 128-2= 55 Unbuffered Memory Module Types + SPD4_MODULE_REGISTERED Registered; ///< 128-2= 55 Registered Memory Module Types +} SPD4_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[348 - 329 + 1]; ///= < 329-348 Module Part Number +} SPD4_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ManufactureSpecificData[381 - 353 + = 1]; ///< 353-381 Manufacturer's Specific Data +} SPD4_MANUFACTURE_SPECIFIC; + +typedef UINT8 SPD4_MODULE_REVISION_CODE;///< 349 = Module Revision Code +typedef UINT8 SPD4_DRAM_STEPPING; ///< 352 = Dram Stepping + +typedef struct { + SPD_UNIQUE_MODULE_ID ModuleId; ///< 320-3= 28 Unique Module ID + SPD4_MODULE_PART_NUMBER ModulePartNumber; ///< 329-3= 48 Module Part Number + SPD4_MODULE_REVISION_CODE ModuleRevisionCode; ///< 349 = Module Revision Code + SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 350-3= 51 Dram Manufacturer ID Code + SPD4_DRAM_STEPPING DramStepping; ///< 352 = Dram Stepping + SPD4_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 353-3= 81 Manufacturer's Specific Data + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 382-3= 83 Cyclical Redundancy Code (CRC) +} SPD4_MANUFACTURING_DATA; + +typedef union { + SPD_EXTREME_MEMORY_PROFILE_2_0 Xmp; ///< 384-4= 63 Intel(r) Extreme Memory Profile support + UINT8 Reserved0[511 - 384 + 1]; ///< 384-5= 11 Unbuffered Memory Module Types +} SPD4_END_USER_SECTION; + +/// +/// DDR4 Serial Presence Detect structure +/// +typedef struct { + SPD4_BASE_SECTION Base; ///< 0-127= Base Configuration and DRAM Parameters + SPD4_MODULE_SPECIFIC Module; ///< 128-2= 55 Module-Specific Section + UINT8 Reserved0[319 - 256 + 1]; ///< 256-3= 19 Reserved + SPD4_MANUFACTURING_DATA ManufactureInfo; ///< 320-3= 83 Manufacturing Information + SPD4_END_USER_SECTION EndUser; ///< 384-5= 11 End User Programmable +} MrcSpdDdr4; + +typedef union { + struct { + UINT8 Fine : 2; ///< Bits 1:0 + UINT8 Medium : 2; ///< Bits 3:2 + UINT8 : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_TIMEBASE_STRUCT; + +typedef union { + struct { + UINT32 CL3 : 1; ///< Bits 0:0 + UINT32 CL6 : 1; ///< Bits 1:1 + UINT32 CL8 : 1; ///< Bits 2:2 + UINT32 CL9 : 1; ///< Bits 3:3 + UINT32 CL10 : 1; ///< Bits 4:4 + UINT32 CL11 : 1; ///< Bits 5:5 + UINT32 CL12 : 1; ///< Bits 6:6 + UINT32 CL14 : 1; ///< Bits 7:7 + UINT32 CL16 : 1; ///< Bits 8:8 + UINT32 : 1; ///< Bits 9:9 + UINT32 CL20 : 1; ///< Bits 10:10 + UINT32 CL22 : 1; ///< Bits 11:11 + UINT32 CL24 : 1; ///< Bits 12:12 + UINT32 : 1; ///< Bits 13:13 + UINT32 CL28 : 1; ///< Bits 14:14 + UINT32 : 1; ///< Bits 15:15 + UINT32 CL32 : 1; ///< Bits 16:16 + UINT32 : 1; ///< Bits 17:17 + UINT32 CL36 : 1; ///< Bits 18:18 + UINT32 : 1; ///< Bits 19:19 + UINT32 CL40 : 1; ///< Bits 20:20 + UINT32 : 11; ///< Bits 31:21 + } Bits; + UINT32 Data; + UINT16 Data16[2]; + UINT8 Data8[4]; +} SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT; + +typedef union { + struct { + UINT8 Density : 4; ///< Bits 3:0 + UINT8 BankAddress : 2; ///< Bits 5:4 + UINT8 BankGroup : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT; + +typedef union { + struct { + UINT8 SignalLoading : 2; ///< Bits 1:0 + UINT8 ChannelsPerDie : 2; ///< Bits 3:2 + UINT8 DieCount : 3; ///< Bits 6:4 + UINT8 SdramPackageType : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT; + +typedef union { + struct { + UINT8 OperationAt1_20 : 1; ///< Bits 0:0 + UINT8 EndurantAt1_20 : 1; ///< Bits 1:1 + UINT8 OperationAt1_10 : 1; ///< Bits 2:2 + UINT8 EndurantAt1_10 : 1; ///< Bits 3:3 + UINT8 OperationAtTBD2V : 1; ///< Bits 4:4 + UINT8 EndurantAtTBD2V : 1; ///< Bits 5:5 + UINT8 : 2; ///< Bits 7:6 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT; + +typedef union { + struct { + UINT8 tCKmax : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_TCK_MAX_MTB_STRUCT; + +typedef union { + struct { + UINT8 ReadLatencyMode : 2; ///< Bits 1:0 + UINT8 WriteLatencySet : 2; ///< Bits 3:2 + UINT8 : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_RW_LATENCY_OPTION_STRUCT; + +typedef union { + struct { + INT8 tCKmaxFine : 8; ///< Bits 7:0 + } Bits; + INT8 Data; +} SPD_LPDDR_TCK_MAX_FTB_STRUCT; + +typedef union { + struct { + UINT8 : 8; ///< Bits 7:0 + } Bits; + UINT8 Data; +} SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_LPDDR_UNBUF_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_LPDDR_RDIMM_MODULE_NOMINAL_HEIGHT; + +typedef struct { + SPD_DEVICE_DESCRIPTION_STRUCT Description; ///<= 0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage= 1, 2 + SPD_REVISION_STRUCT Revision; ///<= 1 SPD Revision + SPD_DRAM_DEVICE_TYPE_STRUCT DramDeviceType; ///<= 2 DRAM Device Type + SPD_MODULE_TYPE_STRUCT ModuleType; ///<= 3 Module Type + SPD_LPDDR_SDRAM_DENSITY_BANKS_STRUCT SdramDensityAndBanks; ///<= 4 SDRAM Density and Banks + SPD_SDRAM_ADDRESSING_STRUCT SdramAddressing; ///<= 5 SDRAM Addressing + SPD_LPDDR_SDRAM_PACKAGE_TYPE_STRUCT SdramPackageType; ///<= 6 SDRAM Package Type + SPD_PTRR_SUPPORT_STRUCT pTRRsupport; ///<= 7 pTRR support with TMAC value - SDRAM Optional Features + SPD_LPDDR_SDRAM_THERMAL_REFRESH_STRUCT ThermalAndRefreshOptions; ///<= 8 SDRAM Thermal and Refresh Options + UINT8 Reserved0[10 - 9 + 1]; ///<= 9-10 Reserved + SPD_LPDDR_MODULE_NOMINAL_VOLTAGE_STRUCT ModuleNominalVoltage; ///<= 11 Module Nominal Voltage, VDD + SPD_MODULE_ORGANIZATION_STRUCT ModuleOrganization; ///<= 12 Module Organization + SPD_MODULE_MEMORY_BUS_WIDTH_STRUCT ModuleMemoryBusWidth; ///<= 13 Module Memory Bus Width + SPD_MODULE_THERMAL_SENSOR_STRUCT ModuleThermalSensor; ///<= 14 Module Thermal Sensor + UINT8 Reserved1[16 - 15 + 1]; ///<= 15-16 Reserved + SPD_LPDDR_TIMEBASE_STRUCT Timebase; ///<= 17 Timebases + SPD_TCK_MIN_MTB_STRUCT tCKmin; ///<= 18 SDRAM Minimum Cycle Time (tCKmin) + SPD_LPDDR_TCK_MAX_MTB_STRUCT tCKmax; ///<= 19 SDRAM Maximum Cycle Time (tCKmax) + SPD_LPDDR_CAS_LATENCIES_SUPPORTED_STRUCT CasLatencies; ///<= 20-23 CAS Latencies Supported + SPD_TAA_MIN_MTB_STRUCT tAAmin; ///<= 24 Minimum CAS Latency Time (tAAmin) + SPD_LPDDR_RW_LATENCY_OPTION_STRUCT LatencySetOptions; ///<= 25 Read and Write Latency Set Options + SPD_TRCD_MIN_MTB_STRUCT tRCDmin; ///<= 26 Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TRP_AB_MTB_STRUCT tRPab; ///<= 27 Minimum Row Precharge Delay Time (tRPab), all banks + SPD_TRP_PB_MTB_STRUCT tRPpb; ///<= 28 Minimum Row Precharge Delay Time (tRPpb), per bank + SPD_TRFC_AB_MTB_STRUCT tRFCab; ///<= 29-30 Minimum Refresh Recovery Delay Time (tRFCab), all banks + SPD_TRFC_PB_MTB_STRUCT tRFCpb; ///<= 31-32 Minimum Refresh Recovery Delay Time (tRFCpb), per bank + UINT8 Reserved2[119 - 33 + 1]; ///<= 33-119 Reserved + SPD_TRP_PB_FTB_STRUCT tRPpbFine; ///<= 120 Fine Offset for Minimum Row Precharge Delay Time (tRPpbFine), per = bank + SPD_TRP_AB_FTB_STRUCT tRPabFine; ///<= 121 Fine Offset for Minimum Row Precharge Delay Time (tRPabFine), all = ranks + SPD_TRCD_MIN_FTB_STRUCT tRCDminFine; ///<= 122 Fine Offset for Minimum RAS# to CAS# Delay Time (tRCDmin) + SPD_TAA_MIN_FTB_STRUCT tAAminFine; ///<= 123 Fine Offset for Minimum CAS Latency Time (tAAmin) + SPD_LPDDR_TCK_MAX_FTB_STRUCT tCKmaxFine; ///<= 124 Fine Offset for SDRAM Maximum Cycle Time (tCKmax) + SPD_TCK_MIN_FTB_STRUCT tCKminFine; ///<= 125 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///<= 126-127 Cyclical Redundancy Code (CRC) +} SPD_LPDDR_BASE_SECTION; + +typedef union { + struct { + UINT8 FrontThickness : 4; ///< Bits 3:0 + UINT8 BackThickness : 4; ///< Bits 7:4 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_MAXIMUM_THICKNESS; + +typedef union { + struct { + UINT8 Height : 5; ///< Bits 4:0 + UINT8 RawCardExtension : 3; ///< Bits 7:5 + } Bits; + UINT8 Data; +} SPD_LPDDR_MODULE_NOMINAL_HEIGHT; + +typedef union { + struct { + UINT8 Card : 5; ///< Bits 4:0 + UINT8 Revision : 2; ///< Bits 6:5 + UINT8 Extension : 1; ///< Bits 7:7 + } Bits; + UINT8 Data; +} SPD_LPDDR_REFERENCE_RAW_CARD; + +typedef struct { + SPD_LPDDR_MODULE_NOMINAL_HEIGHT ModuleNominalHeight; ///< 1= 28 Module Nominal Height + SPD_LPDDR_MODULE_MAXIMUM_THICKNESS ModuleMaximumThickness; ///< 1= 29 Module Maximum Thickness + SPD_LPDDR_REFERENCE_RAW_CARD ReferenceRawCardUsed; ///< 1= 30 Reference Raw Card Used + UINT8 Reserved[253 - 131 + 1]; ///< 1= 31-253 Reserved + SPD_CYCLIC_REDUNDANCY_CODE Crc; ///< 2= 54-255 Cyclical Redundancy Code (CRC) +} SPD_LPDDR_MODULE_LPDIMM; + +typedef union { + SPD_LPDDR_MODULE_LPDIMM LpDimm; ///< 1= 28-255 Unbuffered Memory Module Types +} SPD_LPDDR_MODULE_SPECIFIC; + +typedef struct { + UINT8 ModulePartNumber[348 - 329 + 1];= ///< 329-348 Module Part Number +} SPD_LPDDR_MODULE_PART_NUMBER; + +typedef struct { + UINT8 ManufactureSpecificData[381 - 35= 3 + 1]; ///< 353-381 Manufacturer's Specific Data +} SPD_LPDDR_MANUFACTURE_SPECIFIC; + +typedef UINT8 SPD_LPDDR_MODULE_REVISION_CODE;/= //< 349 Module Revision Code +typedef UINT8 SPD_LPDDR_DRAM_STEPPING; /= //< 352 Dram Stepping + +typedef struct { + SPD_UNIQUE_MODULE_ID ModuleId; ///< 3= 20-328 Unique Module ID + SPD_LPDDR_MODULE_PART_NUMBER ModulePartNumber; ///< 3= 29-348 Module Part Number + SPD_LPDDR_MODULE_REVISION_CODE ModuleRevisionCode; ///< 3= 49 Module Revision Code + SPD_MANUFACTURER_ID_CODE DramIdCode; ///< 3= 50-351 Dram Manufacturer ID Code + SPD_LPDDR_DRAM_STEPPING DramStepping; ///< 3= 52 Dram Stepping + SPD_LPDDR_MANUFACTURE_SPECIFIC ManufactureSpecificData; ///< 3= 53-381 Manufacturer's Specific Data + UINT8 Reserved[383 - 382 + 1]; ///< 3= 82-383 Reserved +} SPD_LPDDR_MANUFACTURING_DATA; + +typedef union { + UINT8 Reserved0[511 - 384 + 1]; ///< 3= 84-511 End User Programmable +} SPD_LPDDR_END_USER_SECTION; + +typedef struct { + SPD_LPDDR_BASE_SECTION Base; ///< 0= -127 Base Configuration and DRAM Parameters + SPD_LPDDR_MODULE_SPECIFIC Module; ///< 1= 28-255 Module-Specific Section + UINT8 Reserved0[319 - 256 + 1]; ///< 2= 56-319 Reserved + SPD_LPDDR_MANUFACTURING_DATA ManufactureInfo; ///< 3= 20-383 Manufacturing Information + SPD_LPDDR_END_USER_SECTION EndUser; ///< 3= 84-511 End User Programmable +} MrcSpdLpDdr; + +typedef union { + MrcSpdDdr3 Ddr3; + MrcSpdDdr4 Ddr4; + MrcSpdLpDdr Lpddr; +} MrcSpd; + +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE (sizeof (SPD_MANUFACTURER_ID_CODE) + \ + sizeof (SPD_MANUFACTURING_LOCATION) + \ + sizeof (SPD_MANUFACTURING_DATE) + \ + sizeof (SPD_MANUFACTURER_SERIAL_NUMBER) + \ + sizeof (SPD4_MODULE_PART_NUMBER)) +#endif + +#pragma pack (pop) +#endif // _MrcSpdData_h_ diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Incl= ude/Coffeelake/MrcTypes.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/= MemoryInit/Include/Coffeelake/MrcTypes.h new file mode 100644 index 0000000000..b267315f36 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Cof= feelake/MrcTypes.h @@ -0,0 +1,237 @@ +/** @file + Include the the general MRC types + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _MRC_TYPES_H +#define _MRC_TYPES_H + +#ifdef MRC_MINIBIOS_BUILD +#include "MrcMiniBiosEfiDefs.h" +#else +#include +#endif // MRC_MINIBIOS_BUILD + +// +// Data Types +// +typedef union { + struct { + UINT32 Low; + UINT32 High; + } Data32; + UINT64 Data; +} UINT64_STRUCT; + +typedef union { + struct { + INT32 Low; + INT32 High; + } Data32; + INT64 Data; +} INT64_STRUCT; + +typedef union { + VOID *Ptr; + UINTN DataN; + UINT64 Data64; +} POINTER_STRUCT; + +#define UNSUPPORT 0 +#define SUPPORT 1 + +typedef enum { + mrcSuccess, + mrcFail, + mrcWrongInputParameter, + mrcCasError, + mrcTimingError, + mrcSenseAmpErr, + mrcReadMPRErr, + mrcReadLevelingError, + mrcWriteLevelingError, + mrcDataTimeCentering1DErr, + mrcWriteVoltage2DError, + mrcReadVoltage2DError, + mrcMiscTrainingError, + mrcWrError, + mrcDimmNotSupport, + mrcChannelNotSupport, + mrcPiSettingError, + mrcDqsPiSettingError, + mrcDeviceBusy, + mrcFrequencyChange, + mrcReutSequenceError, + mrcCrcError, + mrcFrequencyError, + mrcDimmNotExist, + mrcColdBootRequired, + mrcRoundTripLatencyError, + mrcMixedDimmSystem, + mrcAliasDetected, + mrcRetrain, + mrcRtpError, + mrcUnsupportedTechnology, + mrcMappingError, + mrcSocketNotSupported, + mrcControllerNotSupported, + mrcRankNotSupported, + mrcTurnAroundTripError +} MrcStatus; + +// +// general macros +// +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef ABS +#define ABS(x) (((x) < 0) ? (-(x)) : (x)) +#endif + +// +// Make sure x is inside the range of [a..b] +// +#ifndef RANGE +#define RANGE(x, a, b) (MIN ((b), MAX ((x), (a)))) +#endif + +#ifndef DIVIDECEIL +#define DIVIDECEIL(a, b) (((a) + (b) - 1) / (b)) +#endif + +#ifndef DIVIDEROUND +#define DIVIDEROUND(a, b) (((a) * (b) > 0) ? ((a) + (b) / 2) / (b) : ((a)= - (b) / 2) / (b)) +#endif + +#ifndef DIVIDEFLOOR +#define DIVIDEFLOOR(a, b) ((a) / (b)) +#endif + +// +// Number of elements in a 1D array +// +#ifndef ARRAY_COUNT +#define ARRAY_COUNT(a) (sizeof (a) / sizeof (a[0])) +#endif + +// +// use for ignore parames +// +// #define MRC_IGNORE_PARAM(x) ((x) =3D (x)) +// +#if _MSC_EXTENSIONS +// +// Disable warning that make it impossible to compile at /W4 +// This only works for Microsoft* tools +// +// +// Disabling bitfield type checking warnings. +// +#pragma warning (disable : 4214) +// +// Unreferenced formal parameter - We are object oriented, so we pass para= meters even +// if we don't need them. +// +#pragma warning (disable : 4100) +// +// ASSERT(FALSE) or while (TRUE) are legal constructs so supress this warn= ing +// +#pragma warning(disable : 4127) +// +// The given function was selected for inline expansion, but the compiler = did not perform the inlining. +// +#pragma warning(disable : 4710) + +#endif // _MSC_EXTENSIONS +#define MRC_BIT0 0x00000001 +#define MRC_BIT1 0x00000002 +#define MRC_BIT2 0x00000004 +#define MRC_BIT3 0x00000008 +#define MRC_BIT4 0x00000010 +#define MRC_BIT5 0x00000020 +#define MRC_BIT6 0x00000040 +#define MRC_BIT7 0x00000080 +#define MRC_BIT8 0x00000100 +#define MRC_BIT9 0x00000200 +#define MRC_BIT10 0x00000400 +#define MRC_BIT11 0x00000800 +#define MRC_BIT12 0x00001000 +#define MRC_BIT13 0x00002000 +#define MRC_BIT14 0x00004000 +#define MRC_BIT15 0x00008000 +#define MRC_BIT16 0x00010000 +#define MRC_BIT17 0x00020000 +#define MRC_BIT18 0x00040000 +#define MRC_BIT19 0x00080000 +#define MRC_BIT20 0x00100000 +#define MRC_BIT21 0x00200000 +#define MRC_BIT22 0x00400000 +#define MRC_BIT23 0x00800000 +#define MRC_BIT24 0x01000000 +#define MRC_BIT25 0x02000000 +#define MRC_BIT26 0x04000000 +#define MRC_BIT27 0x08000000 +#define MRC_BIT28 0x10000000 +#define MRC_BIT29 0x20000000 +#define MRC_BIT30 0x40000000 +#define MRC_BIT31 0x80000000 +#define MRC_BIT32 0x100000000ULL +#define MRC_BIT33 0x200000000ULL +#define MRC_BIT34 0x400000000ULL +#define MRC_BIT35 0x800000000ULL +#define MRC_BIT36 0x1000000000ULL +#define MRC_BIT37 0x2000000000ULL +#define MRC_BIT38 0x4000000000ULL +#define MRC_BIT39 0x8000000000ULL +#define MRC_BIT40 0x10000000000ULL +#define MRC_BIT41 0x20000000000ULL +#define MRC_BIT42 0x40000000000ULL +#define MRC_BIT43 0x80000000000ULL +#define MRC_BIT44 0x100000000000ULL +#define MRC_BIT45 0x200000000000ULL +#define MRC_BIT46 0x400000000000ULL +#define MRC_BIT47 0x800000000000ULL +#define MRC_BIT48 0x1000000000000ULL +#define MRC_BIT49 0x2000000000000ULL +#define MRC_BIT50 0x4000000000000ULL +#define MRC_BIT51 0x8000000000000ULL +#define MRC_BIT52 0x10000000000000ULL +#define MRC_BIT53 0x20000000000000ULL +#define MRC_BIT54 0x40000000000000ULL +#define MRC_BIT55 0x80000000000000ULL +#define MRC_BIT56 0x100000000000000ULL +#define MRC_BIT57 0x200000000000000ULL +#define MRC_BIT58 0x400000000000000ULL +#define MRC_BIT59 0x800000000000000ULL +#define MRC_BIT60 0x1000000000000000ULL +#define MRC_BIT61 0x2000000000000000ULL +#define MRC_BIT62 0x4000000000000000ULL +#define MRC_BIT63 0x8000000000000000ULL + +#define MRC_DEADLOOP() { volatile int __iii; __iii =3D 1; while (__iii); } + +#ifndef ASM +#define ASM __asm +#endif + +/// +/// Type Max/Min Values +/// +#define MRC_INT32_MAX (0x7FFFFFFF) +#define MRC_INT32_MIN (0x80000000) +#define MRC_INT64_MAX (0x7FFFFFFFFFFFFFFFLL) +#define MRC_INT64_MIN (0x8000000000000000LL) +#define MRC_UINT32_MAX (0xFFFFFFFF) +#define MRC_UINT64_MAX (0xFFFFFFFFFFFFFFFFULL) +#define MRC_UINT_MIN (0x0) + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Incl= ude/MrcInterface.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryI= nit/Include/MrcInterface.h new file mode 100644 index 0000000000..d444e937d6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/MemoryInit/Include/Mrc= Interface.h @@ -0,0 +1,15 @@ +/** @file + This file includes all the data structures that the MRC considers "globa= l data". + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _UNIFIED_MrcInterface_h_ +#define _UNIFIED_MrcInterface_h_ + +#include "Coffeelake/MrcInterface.h" + +#endif + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Grap= hicsInit.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Grap= hicsInit.h new file mode 100644 index 0000000000..82d798b783 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsIni= t.h @@ -0,0 +1,50 @@ +/** @file + Header file for initialization of GT PowerManagement + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GRAPHICS_INIT_H_ +#define _GRAPHICS_INIT_H_ + +#include +#include +#include +#include +#include +#include +#include "SaInitDxe.h" +#include "SaInit.h" +#include +#include +#include + + +/** + Initialize GT ACPI tables + + @param[in] ImageHandle - Handle for the image of this driver + @param[in] SaPolicy - SA DXE Policy protocol + + @retval EFI_SUCCESS - GT ACPI initialization complete + @retval EFI_NOT_FOUND - Dxe System Table not found. + @retval EFI_OUT_OF_RESOURCES - Mmio not allocated successfully. +**/ +EFI_STATUS +GraphicsInit ( + IN EFI_HANDLE ImageHandle, + IN SA_POLICY_PROTOCOL *SaPolicy + ); + +/** + Do Post GT PM Init Steps after VBIOS Initialization. + + @retval EFI_SUCCESS Succeed. +**/ +EFI_STATUS +PostPmInitEndOfDxe ( + VOID + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdO= pRegionInit.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/I= gdOpRegionInit.h new file mode 100644 index 0000000000..0e95db3d02 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegion= Init.h @@ -0,0 +1,193 @@ +/** @file + This is part of the implementation of an Intel Graphics drivers OpRegion= / + Software SCI interface between system BIOS, ASL code, and Graphics drive= rs. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IGD_OPREGION_INIT_H_ +#define _IGD_OPREGION_INIT_H_ + +/// +/// Statements that include other header files. +/// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/// +/// Driver Consumed Protocol Prototypes +/// +#include +#include +#include +#include + + +#include + +/// +/// Driver Produced Protocol Prototypes +/// +#include + +/// +/// +/// OpRegion (Miscellaneous) defines. +/// +/// OpRegion Header defines. +/// +typedef UINT16 STRING_REF; +#define HEADER_SIGNATURE "IntelGraphicsMem" +#define HEADER_SIZE 0x2000 +#define HEADER_OPREGION_VER 0x0200 +#define HEADER_OPREGION_REV 0x00 +#define HEADER_MBOX_SUPPORT (HD_MBOX5 + HD_MBOX4 + HD_MBOX3 + HD_M= BOX2 + HD_MBOX1) +#define HD_MBOX1 BIT0 +#define HD_MBOX2 BIT1 +#define HD_MBOX3 BIT2 +#define HD_MBOX4 BIT3 +#define HD_MBOX5 BIT4 +#define SVER_SIZE 32 + +/// +/// OpRegion Mailbox 1 EQUates. +/// +/// OpRegion Mailbox 3 EQUates. +/// +#define ALS_ENABLE BIT0 +#define BLC_ENABLE BIT1 +#define BACKLIGHT_BRIGHTNESS 0xFF +#define FIELD_VALID_BIT BIT31 +#define PFIT_ENABLE BIT2 +#define PFIT_OPRN_AUTO 0x00000000 +#define PFIT_OPRN_SCALING 0x00000007 +#define PFIT_OPRN_OFF 0x00000000 +#define PFIT_SETUP_AUTO 0 +#define PFIT_SETUP_SCALING 1 +#define PFIT_SETUP_OFF 2 +#define INIT_BRIGHT_LEVEL 0x64 +#define PFIT_STRETCH 6 + +/// +/// Video BIOS / VBT defines +/// +#define OPTION_ROM_SIGNATURE 0xAA55 +#define VBIOS_LOCATION_PRIMARY 0xC0000 + +#define VBT_SIGNATURE SIGNATURE_32 ('$', 'V', 'B', 'T') +/// +/// Typedef stuctures +/// +#pragma pack(1) +typedef struct { + UINT16 Signature; /// 0xAA55 + UINT8 Size512; + UINT8 Reserved[21]; + UINT16 PcirOffset; + UINT16 VbtOffset; +} INTEL_VBIOS_OPTION_ROM_HEADER; +#pragma pack() + +#pragma pack(1) +typedef struct { + UINT32 Signature; /// "PCIR" + UINT16 VendorId; /// 0x8086 + UINT16 DeviceId; + UINT16 Reserved0; + UINT16 Length; + UINT8 Revision; + UINT8 ClassCode[3]; + UINT16 ImageLength; + UINT16 CodeRevision; + UINT8 CodeType; + UINT8 Indicator; + UINT16 Reserved1; +} INTEL_VBIOS_PCIR_STRUCTURE; +#pragma pack() + +#pragma pack(1) +typedef struct { + UINT8 HeaderSignature[20]; + UINT16 HeaderVersion; + UINT16 HeaderSize; + UINT16 HeaderVbtSize; + UINT8 HeaderVbtCheckSum; + UINT8 HeaderReserved; + UINT32 HeaderOffsetVbtDataBlock; + UINT32 HeaderOffsetAim1; + UINT32 HeaderOffsetAim2; + UINT32 HeaderOffsetAim3; + UINT32 HeaderOffsetAim4; + UINT8 DataHeaderSignature[16]; + UINT16 DataHeaderVersion; + UINT16 DataHeaderSize; + UINT16 DataHeaderDataBlockSize; + UINT8 CoreBlockId; + UINT16 CoreBlockSize; + UINT16 CoreBlockBiosSize; + UINT8 CoreBlockBiosType; + UINT8 CoreBlockReleaseStatus; + UINT8 CoreBlockHWSupported; + UINT8 CoreBlockIntegratedHW; + UINT8 CoreBlockBiosBuild[4]; + UINT8 CoreBlockBiosSignOn[155]; +} VBIOS_VBT_STRUCTURE; +#pragma pack() +/// +/// Driver Private Function definitions +/// + +/** + Graphics OpRegion / Software SCI driver installation function. + + @retval EFI_SUCCESS - The driver installed without error. + @retval EFI_ABORTED - The driver encountered an error and could not = complete + installation of the ACPI tables. +**/ +EFI_STATUS +IgdOpRegionInit ( + VOID + ); + +/** + Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size). + The VBT (Video BIOS Table) is a block of customizable data that is built + within the video BIOS and edited by customers. + + @retval EFI_SUCCESS - Video BIOS VBT information returned. + @exception EFI_UNSUPPORTED - Could not find VBT information (*VBiosV= btPtr =3D NULL). +**/ +EFI_STATUS +GetVBiosVbtEndOfDxe ( + VOID + ); + +/** + Update Graphics OpRegion after PCI enumeration. + + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +UpdateIgdOpRegionEndOfDxe ( + VOID + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PciE= xpressInit.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Pc= iExpressInit.h new file mode 100644 index 0000000000..34a2809f80 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PciExpressI= nit.h @@ -0,0 +1,91 @@ +/** @file + Header file for PciExpress Initialization Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCIEXPRESS_INITIALIZATION_DRIVER_H_ +#define _PCIEXPRESS_INITIALIZATION_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define GEN1 1 +#define GEN2 2 + +/// +/// Function prototypes +/// +/** + PCI Express Dxe Initialization. + Run before PCI Bus Init, where assignment of Bus, Memory, + and I/O Resources are assigned. + + @param[in] SaPolicy - SA DXE Policy protocol + + @retval EFI_SUCCESS - Pci Express successfully started and ready = to be used + @exception EFI_UNSUPPORTED - Pci Express can't be initialized +**/ +EFI_STATUS +PciExpressInit ( + IN SA_POLICY_PROTOCOL *SaPolicy + ); + +/** + Find the Offset to a given Capabilities ID + + @param[in] Segment - Pci Segment Number + @param[in] Bus - Pci Bus Number + @param[in] Device - Pci Device Number + @param[in] Function - Pci Function Number + @param[in] CapId - CAPID to search fo + + @retval 0 - CAPID not found + @retval Other - CAPID found, Offset of desired CAPID +**/ +UINT32 +PcieFindCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 CapId + ); + +/** + Search and return the offset of desired Pci Express Capability ID + + @param[in] Segment - Pci Segment Number + @param[in] Bus - Pci Bus Number + @param[in] Device - Pci Device Number + @param[in] Function - Pci Function Number + @param[in] CapId - Extended CAPID to search for + + @retval 0 - CAPID not found + @retval Other - CAPID found, Offset of desired CAPID +**/ +UINT32 +PcieFindExtendedCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT16 CapId + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Pcie= Complex.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PcieC= omplex.h new file mode 100644 index 0000000000..73af27e9d7 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PcieComplex= .h @@ -0,0 +1,23 @@ +/** @file + This is header file for SA PCIE Root Complex initialization. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +EFI_STATUS +PegInitBeforeEndOfDxe ( + VOID + ); + +/** + This function performs SA registers Saving/Restoring in EndOfDxe callback + + @retval EFI_SUCCESS - Save/restore has done + @retval EFI_UNSUPPORTED - Save/restore not done successfully +**/ +EFI_STATUS +SaSaveRestore ( + VOID + ); diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIn= it.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h new file mode 100644 index 0000000000..d7e2423ffd --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.h @@ -0,0 +1,71 @@ +/** @file + Header file for SA Common Initialization Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_INITIALIZATION_DRIVER_H_ +#define _SA_INITIALIZATION_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +extern SA_POLICY_PROTOCOL *mSaPolicy; +extern SA_CONFIG_HOB *SaConfigHob; + +typedef struct { + UINT64 BaseAddr; + UINT32 Offset; + UINT32 AndMask; + UINT32 OrMask; +} BOOT_SCRIPT_REGISTER_SETTING; + +/** + SystemAgent Initialization Common Function. + + @retval EFI_SUCCESS - Always. +**/ +VOID +SaInitEntryPoint ( + VOID + ); + +/** + Common function locks the PAM register as part of the SA Security requir= ements. + + @retval EFI_SUCCESS - Always. +**/ +VOID +SaPamLock ( + VOID + ); +/** + This function performs SA Security locking in EndOfDxe callback + + @retval EFI_SUCCESS - Security lock has done + @retval EFI_UNSUPPORTED - Security lock not done successfully +**/ +EFI_STATUS +SaSecurityInit ( + VOID + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIn= itDxe.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitD= xe.h new file mode 100644 index 0000000000..1991fd82c4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.h @@ -0,0 +1,139 @@ +/** @file + Header file for SA Initialization Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_INITIALIZATION_DXE_DRIVER_H_ +#define _SA_INITIALIZATION_DXE_DRIVER_H_ + +#include +#include +#include "VTd.h" +#include "PcieComplex.h" +#include "IgdOpRegionInit.h" +#include +#include "GraphicsInit.h" +#include "PciExpressInit.h" +#include "SwitchableGraphicsInit.h" +#include + +/// +/// Driver Consumed Protocol Prototypes +/// +#include + +extern EFI_GUID gSaAcpiTableStorageGuid; +extern EFI_GUID gSaSsdtAcpiTableStorageGuid; +extern EFI_GUID gPegSsdtAcpiTableStorageGuid; + +typedef struct { + UINT64 Address; + EFI_BOOT_SCRIPT_WIDTH Width; + UINT32 Value; +} BOOT_SCRIPT_PCI_REGISTER_SAVE; + +/// +/// Function Prototype +/// +/** + This function gets registered as a callback to perform SA initialization= before ExitPmAuth + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. + + @retval EFI_SUCCESS - Always. + +**/ +VOID +EFIAPI +SaPciEnumCompleteCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + System Agent Initialization DXE Driver Entry Point + - Introduction \n + Based on the information/data in SA_POLICY_PROTOCOL, this module perfo= rms further SA initialization in DXE phase, + e.g. internal devices enable/disable, SSVID/SID programming, graphic p= ower-management, VT-d, IGD OpRegion initialization. + From the perspective of a PCI Express hierarchy, the Broadwell System = Agent and PCH together appear as a Root Complex with root ports the number = of which depends on how the 8 PCH ports and 4 System Agent PCIe ports are c= onfigured [4x1, 2x8, 1x16]. + There is an internal link (DMI or OPI) that connects the System Agent = to the PCH component. This driver includes initialization of SA DMI, PCI Ex= press, SA & PCH Root Complex Topology. + For iGFX, this module implements the initialization of the Graphics Te= chnology Power Management from the Broadwell System Agent BIOS Specificatio= n and the initialization of the IGD OpRegion/Software SCI - BIOS Specificat= ion. + The ASL files that go along with the driver define the IGD OpRegion ma= ilboxes in ACPI space and implement the software SCI interrupt mechanism. + The IGD OpRegion/Software SCI code serves as a communication interface= between system BIOS, ASL, and Intel graphics driver including making a blo= ck of customizable data (VBT) from the Intel video BIOS available. + Reference Code for the SCI service functions "Get BIOS Data" and "Syst= em BIOS Callback" can be found in the ASL files, those functions can be pla= tform specific, the sample provided in the reference code are implemented f= or Intel CRB. + This module implements the VT-d functionality described in the Broadwe= ll System Agent BIOS Specification. + This module publishes the LegacyRegion protocol to control the read an= d write accesses to the Legacy BIOS ranges. + E000 and F000 segments are the legacy BIOS ranges and contain pointers= to the ACPI regions, SMBIOS tables and so on. This is a private protocol u= sed by Intel Framework. + This module registers CallBack function that performs SA security regi= sters lockdown at end of post as required from Broadwell Bios Spec. + In addition, this module publishes the SaInfo Protocol with informatio= n such as current System Agent reference code version#. + + - @pre + - EFI_FIRMWARE_VOLUME_PROTOCOL: Documented in Firmware Volume Specific= ation, available at the URL: http://www.intel.com/technology/framework/spec= .htm + - SA_POLICY_PROTOCOL: A protocol published by a platform DXE module ex= ecuted earlier; this is documented in this document as well. + - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL: Documented in the Unified Extensibl= e Firmware Interface Specification, version 2.0, available at the URL: http= ://www.uefi.org/specs/ + - EFI_BOOT_SCRIPT_SAVE_PROTOCOL: A protocol published by a platform DX= E module executed earlier; refer to the Sample Code section of the Framewor= k PCH Reference Code. + - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL: Documented in the = Unified Extensible Firmware Interface Specification, version 2.0, available= at the URL: http://www.uefi.org/specs/ + - EFI_ACPI_TABLE_PROTOCOL : Documented in PI Specification 1.2 + - EFI_CPU_IO_PROTOCOL: Documented in CPU I/O Protocol Specification, a= vailable at the URL: http://www.intel.com/technology/framework/spec.htm + - EFI_DATA_HUB_PROTOCOL: Documented in EFI Data Hub Infrastructure Spe= cification, available at the URL: http://www.intel.com/technology/framework= /spec.htm + - EFI_HII_PROTOCOL (or EFI_HII_DATABASE_PROTOCOL for UEFI 2.1): Docume= nted in Human Interface Infrastructure Specification, available at the URL:= http://www.intel.com/technology/framework/spec.htm + (For EFI_HII_DATABASE_PROTOCOL, refer to UEFI Specification Version 2.= 1 available at the URL: http://www.uefi.org/) + + - @result + IGD power-management functionality is initialized; VT-d is initialize= d (meanwhile, the DMAR table is updated); IGD OpRegion is initialized - IGD= _OPREGION_PROTOCOL installed, IGD OpRegion allocated and mailboxes initiali= zed, chipset initialized and ready to generate Software SCI for Internal gr= aphics events. Publishes the SA_INFO_PROTOCOL with current SA reference cod= e version #. Publishes the EFI_LEGACY_REGION_PROTOCOL documented in the Com= patibility Support Module Specification, version 0.9, available at the URL:= http://www.intel.com/technology/framework/spec.htm + + - References \n + IGD OpRegion/Software SCI for Broadwell + Advanced Configuration and Power Interface Specification Revision 4.0a. + + - Porting Recommendations \n + No modification of the DXE driver should be typically necessary. + This driver should be executed after all related devices (audio, video= , ME, etc.) are initialized to ensure correct data in DMAR table and DMA-re= mapping registers. + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate +**/ +EFI_STATUS +EFIAPI +SaInitEntryPointDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + SystemAgent Acpi Initialization. + + @param[in] ImageHandle Handle for the image of this driver + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate +**/ +EFI_STATUS +EFIAPI +SaAcpiInit ( + IN EFI_HANDLE ImageHandle + ); + +/** + This function locks the PAM register as part of the SA Security requirem= ents. + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. + + @retval EFI_SUCCESS - Always. +**/ +VOID +EFIAPI +SaPamLockDxe ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Swit= chableGraphicsInit.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaIni= t/Dxe/SwitchableGraphicsInit.h new file mode 100644 index 0000000000..2b1b4c5880 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SwitchableG= raphicsInit.h @@ -0,0 +1,17 @@ +/** @file + Header file for the SwitchableGraphics Dxe driver. + This driver loads SwitchableGraphics ACPI tables. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SWITCHABLE_GRAPHICS_DXE_H_ +#define _SWITCHABLE_GRAPHICS_DXE_H_ + + +#include + + +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.= h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.h new file mode 100644 index 0000000000..c4bc47f7fe --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.h @@ -0,0 +1,53 @@ +/** @file + This code provides a initialization of intel VT-d (Virtualization Techno= logy for Directed I/O). + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _VT_D_H_ +#define _VT_D_H_ + +/// +/// Include files +/// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +#define VTD_ECAP_REG 0x10 +#define IR BIT3 + +/** + Locate the VT-d ACPI tables data file and read ACPI SSDT tables. + Publish the appropriate SSDT based on current configuration and capabili= ties. + + @param[in] SaPolicy SA DXE Policy protocol + + @retval EFI_SUCCESS - Vtd initialization complete + @retval Other - No Vtd function initiated +**/ +EFI_STATUS +VtdInit ( + IN SA_POLICY_PROTOCOL *SaPolicy + ); + +/** + PciEnumerationComplete routine for update DMAR +**/ +VOID +UpdateDmarPciEnumCompleteCallback ( + VOID + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/S= mmAccessDriver.h b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess= /Dxe/SmmAccessDriver.h new file mode 100644 index 0000000000..02c74c0672 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAcces= sDriver.h @@ -0,0 +1,162 @@ +/** @file + Header file for SMM Access Driver. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SMM_ACCESS_DRIVER_H_ +#define _SMM_ACCESS_DRIVER_H_ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a') + +/// +/// Private data +/// +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_SMM_ACCESS2_PROTOCOL SmmAccess; + + /// + /// Local Data for SMM Access interface goes here + /// + UINTN NumberRegions; + EFI_SMRAM_DESCRIPTOR *SmramDesc; +} SMM_ACCESS_PRIVATE_DATA; + +#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \ + CR (a, \ + SMM_ACCESS_PRIVATE_DATA, \ + SmmAccess, \ + SMM_ACCESS_PRIVATE_DATA_SIGNATURE \ + ) + +// +// Prototypes +// Driver model protocol interface +// +/** + SMM Access Driver Entry Point + This driver installs an SMM Access Protocol + - Introduction \n + This module publishes the SMM access protocol. The protocol is used b= y the SMM Base driver to access the SMRAM region when the processor is not = in SMM. + The SMM Base driver uses the services provided by the SMM access proto= col to open SMRAM during post and copy the SMM handler. + SMM access protocol is also used to close the SMRAM region once the co= pying is done. + Finally, the SMM access protocol provides services to "Lock" the SMRAM= region. + Please refer the SMM Protocols section in the attached SMM CIS Specifi= cation version 0.9 for further details. + This driver is required if SMM is supported. Proper configuration of S= MM registers is recommended even if SMM is not supported. + + - @result + Publishes the _EFI_SMM_ACCESS_PROTOCOL: Documented in the System Manag= ement Mode Core Interface Specification, available at the URL: http://www.i= ntel.com/technology/framework/spec.htm + + - Porting Recommendations \n + No modification of this module is recommended. Any modification shoul= d be done in compliance with the _EFI_SMM_ACCESS_PROTOCOL protocol definiti= on. + + @param[in] ImageHandle - Handle for the image of this driver + @param[in] SystemTable - Pointer to the EFI System Table + + @retval EFI_SUCCESS - Protocol was installed successfully + @exception EFI_UNSUPPORTED - Protocol was not installed +**/ +EFI_STATUS +EFIAPI +SmmAccessDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +/** + This routine accepts a request to "open" a region of SMRAM. The + region could be legacy ABSEG, HSEG, or TSEG near top of physical memory. + The use of "open" means that the memory is visible from all boot-service + and SMM agents. + + @param[in] This - Pointer to the SMM Access Interface. + + @retval EFI_SUCCESS - The region was successfully opened. + @retval EFI_DEVICE_ERROR - The region could not be opened because l= ocked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Open ( + IN EFI_SMM_ACCESS2_PROTOCOL *This + ); + +/** + This routine accepts a request to "close" a region of SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "close" means that the memory is only visible from SMM agents, + not from BS or RT code. + + @param[in] This - Pointer to the SMM Access Interface. + + @retval EFI_SUCCESS - The region was successfully closed. + @retval EFI_DEVICE_ERROR - The region could not be closed because l= ocked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Close ( + IN EFI_SMM_ACCESS2_PROTOCOL *This + ); + +/** + This routine accepts a request to "lock" SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "lock" means that the memory can no longer be opened + to BS state.. + + @param[in] This - Pointer to the SMM Access Interface. + + @retval EFI_SUCCESS - The region was successfully locked. + @retval EFI_DEVICE_ERROR - The region could not be locked because a= t least + one range is still open. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Lock ( + IN EFI_SMM_ACCESS2_PROTOCOL *This + ); + +/** + This routine services a user request to discover the SMRAM + capabilities of this platform. This will report the possible + ranges that are possible for SMRAM access, based upon the + memory controller capabilities. + + @param[in] This - Pointer to the SMRAM Access Interface. + @param[in] SmramMapSize - Pointer to the variable containing si= ze of the + buffer to contain the description information. + @param[in] SmramMap - Buffer containing the data describing= the Smram + region descriptors. + + @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient bu= ffer. + @retval EFI_SUCCESS - The user provided a sufficiently-sized b= uffer. +**/ +EFI_STATUS +EFIAPI +GetCapabilities ( + IN CONST EFI_SMM_ACCESS2_PROTOCOL *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap + ); +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Grap= hicsInit.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Grap= hicsInit.c new file mode 100644 index 0000000000..5daa2367e6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/GraphicsIni= t.c @@ -0,0 +1,157 @@ +/** @file + DXE driver for Initializing SystemAgent Graphics ACPI table initializati= on. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "GraphicsInit.h" +#include "SaInit.h" +#include +#include +#include + +typedef union { + struct { + UINT32 Low; + UINT32 High; + } Data32; + UINT64 Data; +} UINT64_STRUCT; + +extern SYSTEM_AGENT_NVS_AREA_PROTOCOL mSaNvsAreaProtocol; + +GLOBAL_REMOVE_IF_UNREFERENCED UINT64 mGttMmAdr; +GLOBAL_REMOVE_IF_UNREFERENCED UINT64_STRUCT mMchBarBase; +GLOBAL_REMOVE_IF_UNREFERENCED GOP_COMPONENT_NAME2_PROTOCOL *GopComponentN= ame2Protocol =3D NULL; + +/** + Do Post GT PM Init Steps after VBIOS Initialization. + + @retval EFI_SUCCESS Succeed. +**/ +EFI_STATUS +PostPmInitEndOfDxe ( + VOID + ) +{ + CHAR16 *DriverVersion; + UINTN Index; + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios; + EFI_STATUS Status; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + EFI_PEI_HOB_POINTERS HobPtr; + SI_CONFIG_HOB_DATA *SiConfigHobData; + + /// + /// Get the platform setup policy. + /// + DriverVersion =3D NULL; + LegacyBios =3D NULL; + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) = &mSaPolicy); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) mSaPolicy, &gGraphicsDxeConfigGuid, = (VOID *)&GraphicsDxeConfig); + ASSERT_EFI_ERROR (Status); + + // + // Get Silicon Config data HOB + // + HobPtr.Guid =3D GetFirstGuidHob (&gSiConfigHobGuid); + SiConfigHobData =3D (SI_CONFIG_HOB_DATA *)GET_GUID_HOB_DATA (HobPtr.Guid= ); + + if (SiConfigHobData->CsmFlag =3D=3D 1) { + Status =3D gBS->LocateProtocol ( + &gEfiLegacyBiosProtocolGuid, + NULL, + (VOID **) &LegacyBios + ); + } + + if (LegacyBios =3D=3D NULL) { + Status =3D gBS->LocateProtocol (&gGopComponentName2ProtocolGuid, NULL,= (VOID **)&GopComponentName2Protocol); + if (!EFI_ERROR (Status)) { + Status =3D GopComponentName2Protocol->GetDriverVersion ( + GopComponentName2Protocol, + "en-US", + &DriverVersion + ); + if (!EFI_ERROR (Status)) { + for (Index =3D 0; (DriverVersion[Index] !=3D '\0'); Index++) { + } + Index =3D (Index+1)*2; + CopyMem (GraphicsDxeConfig->GopVersion, DriverVersion, Index); + } + } + } + + /// + /// Return final status + /// + return EFI_SUCCESS; +} + + +/** +Initialize GT ACPI tables + + @param[in] ImageHandle - Handle for the image of this driver + @param[in] SaPolicy - SA DXE Policy protocol + + @retval EFI_SUCCESS - GT ACPI initialization complete + @retval EFI_NOT_FOUND - Dxe System Table not found. + @retval EFI_OUT_OF_RESOURCES - Mmio not allocated successfully. +**/ +EFI_STATUS +GraphicsInit ( + IN EFI_HANDLE ImageHandle, + IN SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + + mGttMmAdr =3D 0; + Status =3D EFI_SUCCESS; + mMchBarBase.Data32.High =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (S= A_SEG_NUM, SA_MC_BUS, 0, 0, R_SA_MCHBAR + 4)); + mMchBarBase.Data32.Low =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (S= A_SEG_NUM, SA_MC_BUS, 0, 0, R_SA_MCHBAR)); + mMchBarBase.Data &=3D (UINT64) ~BIT0; + + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig); + ASSERT_EFI_ERROR (Status); + + /// + /// Update IGD SA Global NVS + /// + DEBUG ((DEBUG_INFO, " Update Igd SA Global NVS Area.\n")); + + mSaNvsAreaProtocol.Area->AlsEnable =3D GraphicsDxeCon= fig->AlsEnable; + /// + /// Initialize IGD state by checking if IGD Device 2 Function 0 is enabl= ed in the chipset + /// + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0,= 0, R_SA_DEVEN)) & B_SA_DEVEN_D2EN_MASK) { + mSaNvsAreaProtocol.Area->IgdState =3D 1; + } else { + mSaNvsAreaProtocol.Area->IgdState =3D 0; + } + + mSaNvsAreaProtocol.Area->BrightnessPercentage =3D 100; + mSaNvsAreaProtocol.Area->IgdBootType =3D GraphicsDxeCon= fig->IgdBootType; + mSaNvsAreaProtocol.Area->IgdPanelType =3D GraphicsDxeCon= fig->IgdPanelType; + mSaNvsAreaProtocol.Area->IgdPanelScaling =3D GraphicsDxeCon= fig->IgdPanelScaling; + /// + /// Get SFF power mode platform data for the IGD driver. Flip the bit (= bitwise xor) + /// since Setup value is opposite of NVS and IGD OpRegion value. + /// + mSaNvsAreaProtocol.Area->IgdDvmtMemSize =3D GraphicsDxeCon= fig->IgdDvmtMemSize; + mSaNvsAreaProtocol.Area->IgdFunc1Enable =3D 0; + mSaNvsAreaProtocol.Area->IgdHpllVco =3D MmioRead8 (mMc= hBarBase.Data + 0xC0F) & 0x07; + mSaNvsAreaProtocol.Area->IgdSciSmiMode =3D 0; + mSaNvsAreaProtocol.Area->GfxTurboIMON =3D GraphicsDxeCon= fig->GfxTurboIMON; + + mSaNvsAreaProtocol.Area->EdpValid =3D 0; + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdO= pRegionInit.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/I= gdOpRegionInit.c new file mode 100644 index 0000000000..6ec0691074 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/IgdOpRegion= Init.c @@ -0,0 +1,570 @@ +/** @file + This is part of the implementation of an Intel Graphics drivers OpRegion= / + Software SCI interface between system BIOS, ASL code, and Graphics drive= rs. + The code in this file will load the driver and initialize the interface + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "IgdOpRegionInit.h" + +GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion; + +/** + Get VBT data using SaPlaformPolicy + + @param[out] VbtFileBuffer Pointer to VBT data buffer. + + @retval EFI_SUCCESS VBT data was returned. + @retval EFI_NOT_FOUND VBT data not found. + @exception EFI_UNSUPPORTED Invalid signature in VBT data. +**/ +EFI_STATUS +GetIntegratedIntelVbtPtr ( + OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS VbtAddress; + UINT32 Size; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + + /// + /// Get the SA policy. + /// + Status =3D gBS->LocateProtocol ( + &gSaPolicyProtocolGuid, + NULL, + (VOID **) &mSaPolicy + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D GetConfigBlock ((VOID *) mSaPolicy, &gGraphicsDxeConfigGuid, = (VOID *)&GraphicsDxeConfig); + ASSERT_EFI_ERROR (Status); + + VbtAddress =3D GraphicsDxeConfig->VbtAddress; + Size =3D GraphicsDxeConfig->Size; + + if (VbtAddress =3D=3D 0x00000000) { + return EFI_NOT_FOUND; + } else { + /// + /// Check VBT signature + /// + *VbtFileBuffer =3D NULL; + *VbtFileBuffer =3D (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress; + if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) !=3D VBT_SIGNA= TURE) { + FreePool (*VbtFileBuffer); + *VbtFileBuffer =3D NULL; + return EFI_UNSUPPORTED; + } + } + if (Size =3D=3D 0) { + return EFI_NOT_FOUND; + } else { + /// + /// Check VBT size + /// + if ((*VbtFileBuffer)->HeaderVbtSize > Size) { + (*VbtFileBuffer)->HeaderVbtSize =3D (UINT16) Size; + } + } + return EFI_SUCCESS; +} + +/** + Get a pointer to an uncompressed image of the Intel video BIOS. + + @Note: This function would only be called if the video BIOS at 0xC000 is + missing or not an Intel video BIOS. It may not be an Intel video= BIOS + if the Intel graphic contoller is considered a secondary adapter. + + @param[out] VBiosImage - Pointer to an uncompressed Intel video BIOS= . This pointer must + be set to NULL if an uncompressed image of = the Intel Video BIOS + is not obtainable. + + @retval EFI_SUCCESS - VBiosPtr is updated. + @exception EFI_UNSUPPORTED - No Intel video BIOS found. +**/ +EFI_STATUS +GetIntegratedIntelVBiosPtr ( + OUT INTEL_VBIOS_OPTION_ROM_HEADER **VBiosImage + ) +{ + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + UINTN Index; + INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr; + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + INTEL_VBIOS_OPTION_ROM_HEADER *VBiosRomImage; + + /// + /// Set as if an umcompressed Intel video BIOS image was not obtainable. + /// + VBiosRomImage =3D NULL; + + /// + /// Get all PCI IO protocols + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Find the video BIOS by checking each PCI IO handle for an Intel video + /// BIOS OPROM. + /// + for (Index =3D 0; Index < HandleCount; Index++) { + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + ASSERT_EFI_ERROR (Status); + + VBiosRomImage =3D PciIo->RomImage; + + /// + /// If this PCI device doesn't have a ROM image, skip to the next devi= ce. + /// + if (!VBiosRomImage) { + continue; + } + /// + /// Get pointer to PCIR structure + /// + PcirBlockPtr =3D (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBiosRomIma= ge + VBiosRomImage->PcirOffset); + + /// + /// Check if we have an Intel video BIOS OPROM. + /// + if ((VBiosRomImage->Signature =3D=3D OPTION_ROM_SIGNATURE) && + (PcirBlockPtr->VendorId =3D=3D V_SA_MC_VID) && + (PcirBlockPtr->ClassCode[0] =3D=3D 0x00) && + (PcirBlockPtr->ClassCode[1] =3D=3D 0x00) && + (PcirBlockPtr->ClassCode[2] =3D=3D 0x03) + ) { + /// + /// Found Intel video BIOS. + /// + *VBiosImage =3D VBiosRomImage; + return EFI_SUCCESS; + } + } + /// + /// No Intel video BIOS found. + /// + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + return EFI_UNSUPPORTED; +} + +/** + Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size). + The VBT (Video BIOS Table) is a block of customizable data that is built + within the video BIOS and edited by customers. + + @retval EFI_SUCCESS - Video BIOS VBT information returned. + @exception EFI_UNSUPPORTED - Could not find VBT information (*VBiosV= btPtr =3D NULL). +**/ +EFI_STATUS +GetVBiosVbtEndOfDxe ( + VOID + ) +{ + INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr; + UINT32 PcirBlockAddress; + UINT16 PciVenderId; + INTEL_VBIOS_OPTION_ROM_HEADER *VBiosPtr; + VBIOS_VBT_STRUCTURE *VBiosVbtPtr; + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios; + EFI_STATUS Status; + VBIOS_VBT_STRUCTURE *VbtFileBuffer; + UINTN Index; + UINT8 LegacyVbtFound; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + EFI_PEI_HOB_POINTERS HobPtr; + SI_CONFIG_HOB_DATA *SiConfigHobData; + + VbtFileBuffer =3D NULL; + LegacyVbtFound =3D 1; + + /// + /// Get the SA policy. + /// + Status =3D gBS->LocateProtocol ( + &gSaPolicyProtocolGuid, + NULL, + (VOID **) &mSaPolicy + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D GetConfigBlock ((VOID *) mSaPolicy, &gGraphicsDxeConfigGuid, = (VOID *)&GraphicsDxeConfig); + ASSERT_EFI_ERROR (Status); + + LegacyBios =3D NULL; + VBiosPtr =3D NULL; + // + // Get Silicon Config data HOB + // + HobPtr.Guid =3D GetFirstGuidHob (&gSiConfigHobGuid); + SiConfigHobData =3D (SI_CONFIG_HOB_DATA *)GET_GUID_HOB_DATA (HobPtr.Guid= ); + if (SiConfigHobData->CsmFlag =3D=3D 1) { + Status =3D gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, NULL, (VO= ID **) &LegacyBios); + + if (LegacyBios) { + VBiosPtr =3D (INTEL_VBIOS_OPTION_ROM_HEADER *) (UINTN) (VBIOS_L= OCATION_PRIMARY); + PcirBlockAddress =3D VBIOS_LOCATION_PRIMARY + VBiosPtr->PcirOffset; + PcirBlockPtr =3D (INTEL_VBIOS_PCIR_STRUCTURE *) (UINTN) (PcirBlockA= ddress); + PciVenderId =3D PcirBlockPtr->VendorId; + /// + /// If the video BIOS is not at 0xC0000 or it is not an Intel video = BIOS get + /// the integrated Intel video BIOS (must be uncompressed). + /// + if ((VBiosPtr->Signature !=3D OPTION_ROM_SIGNATURE) || (PciVenderId = !=3D V_SA_MC_VID)) { + GetIntegratedIntelVBiosPtr (&VBiosPtr); + if (VBiosPtr !=3D NULL) { + /// + /// Video BIOS found. + /// + PcirBlockPtr =3D (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBio= sPtr + VBiosPtr->PcirOffset); + PciVenderId =3D PcirBlockPtr->VendorId; + + if ((VBiosPtr->Signature !=3D OPTION_ROM_SIGNATURE) || (PciVende= rId !=3D V_SA_MC_VID)) { + /// + /// Intel video BIOS not found. + /// + VBiosVbtPtr =3D NULL; + LegacyVbtFound =3D 0; + } + } + } + } + } + if ((LegacyBios =3D=3D NULL) || (LegacyVbtFound =3D=3D 0)) { + /// + /// No Video BIOS found, try to get VBT from FV. + /// + GetIntegratedIntelVbtPtr (&VbtFileBuffer); + if (VbtFileBuffer !=3D NULL) { + /// + /// Video BIOS not found, use VBT from SaPolicy + /// + DEBUG ((DEBUG_INFO, "VBT data found\n")); + for (Index =3D 0; (GraphicsDxeConfig->GopVersion[Index] !=3D '\0'); = Index++) { + } + Index =3D (Index+1)*2; + CopyMem (mIgdOpRegion.OpRegion->Header.DVER, GraphicsDxeConfig->GopV= ersion, Index); + CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VbtFileBuffer, VbtFileBu= ffer->HeaderVbtSize); + return EFI_SUCCESS; + } + } + + if (VBiosPtr =3D=3D NULL) { + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "VBIOS found at 0x%X\n", VBiosPtr)); + VBiosVbtPtr =3D (VBIOS_VBT_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->= VbtOffset); + + if ((*((UINT32 *) (VBiosVbtPtr->HeaderSignature))) !=3D VBT_SIGNATURE) { + return EFI_UNSUPPORTED; + } + + /// + /// Initialize Video BIOS version with its build number. + /// + mIgdOpRegion.OpRegion->Header.VVER[0] =3D VBiosVbtPtr->CoreBlockBiosBuil= d[0]; + mIgdOpRegion.OpRegion->Header.VVER[1] =3D VBiosVbtPtr->CoreBlockBiosBuil= d[1]; + mIgdOpRegion.OpRegion->Header.VVER[2] =3D VBiosVbtPtr->CoreBlockBiosBuil= d[2]; + mIgdOpRegion.OpRegion->Header.VVER[3] =3D VBiosVbtPtr->CoreBlockBiosBuil= d[3]; + CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VBiosVbtPtr, VBiosVbtPtr->He= aderVbtSize); + + /// + /// Return final status + /// + return EFI_SUCCESS; +} + +/** + Graphics OpRegion / Software SCI driver installation function. + + @param[in] void - None + @retval EFI_SUCCESS - The driver installed without error. + @retval EFI_ABORTED - The driver encountered an error and could not = complete + installation of the ACPI tables. +**/ +EFI_STATUS +IgdOpRegionInit ( + VOID + ) +{ + EFI_HANDLE Handle; + EFI_STATUS Status; + UINT32 DwordData; + UINT64 IgdBaseAddress; + SA_POLICY_PROTOCOL *SaPolicy; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + UINT8 Index; + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol; + + /// + /// Get the SA policy. + /// + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **)&= SaPolicy); + + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig); + ASSERT_EFI_ERROR (Status); + /// + /// Locate the SA Global NVS Protocol. + /// + Status =3D gBS->LocateProtocol ( + &gSaNvsAreaProtocolGuid, + NULL, + (VOID **) &SaNvsAreaProtocol + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Allocate an ACPI NVS memory buffer as the IGD OpRegion, zero initial= ize + /// the first 1K, and set the IGD OpRegion pointer in the Global NVS + /// area structure. + /// + Status =3D (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (IGD_OPREGION_S= TRUCTURE), (VOID **) &mIgdOpRegion.OpRegion); + ASSERT_EFI_ERROR (Status); + + SetMem (mIgdOpRegion.OpRegion, sizeof (IGD_OPREGION_STRUCTURE), 0); + SaNvsAreaProtocol->Area->IgdOpRegionAddress =3D (UINT32) (UINTN) (mIgdOp= Region.OpRegion); + + /// + /// If IGD is disabled return + /// + IgdBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_IGD_BUS, SA_I= GD_DEV, SA_IGD_FUN_0, 0); + if (PciSegmentRead32 (IgdBaseAddress + 0) =3D=3D 0xFFFFFFFF) { + return EFI_SUCCESS; + } + /// + /// Initialize OpRegion Header + /// + CopyMem (mIgdOpRegion.OpRegion->Header.SIGN, HEADER_SIGNATURE, sizeof (H= EADER_SIGNATURE)); + /// + /// Set OpRegion Size in KBs + /// + mIgdOpRegion.OpRegion->Header.SIZE =3D HEADER_SIZE / 1024; + mIgdOpRegion.OpRegion->Header.OVER =3D (UINT32) (LShiftU64 (HEADER_OPREG= ION_VER, 16) + LShiftU64 (HEADER_OPREGION_REV, 8)); + + /// + /// All Mailboxes are supported. + /// + mIgdOpRegion.OpRegion->Header.MBOX =3D HEADER_MBOX_SUPPORT; + + /// + /// Initialize OpRegion Mailbox 1 (Public ACPI Methods). + /// + /// Note - The initial setting of mailbox 1 fields is implementation spe= cific. + /// Adjust them as needed many even coming from user setting in setup. + /// + /// + /// Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservation= ). + /// + /// Note - The initial setting of mailbox 3 fields is implementation spe= cific. + /// Adjust them as needed many even coming from user setting in setup. + /// + /// + /// Do not initialize TCHE. This field is written by the graphics driver= only. + /// + /// + /// The ALSI field is generally initialized by ASL code by reading the e= mbedded controller. + /// + mIgdOpRegion.OpRegion->Header.PCON =3D GraphicsDxeConfig->PlatformConfig; + mIgdOpRegion.OpRegion->Header.PCON =3D mIgdOpRegion.OpRegion->Header.PCO= N | 0x2; + + mIgdOpRegion.OpRegion->MBox3.BCLP =3D BACKLIGHT_BRIGHTNESS; + + mIgdOpRegion.OpRegion->MBox3.PFIT =3D (FIELD_VALID_BIT | PFIT_STRETCH); + + /// + /// Reporting to driver for VR IMON Calibration. Bits [5-1] values suppo= rted 14A to 31A. + /// + mIgdOpRegion.OpRegion->MBox3.PCFT =3D (SaNvsAreaProtocol->Area->GfxTurbo= IMON << 1) & 0x003E; + + /// + /// Set Initial current Brightness + /// + mIgdOpRegion.OpRegion->MBox3.CBLV =3D (INIT_BRIGHT_LEVEL | FIELD_VALID_B= IT); + + /// + /// Static Backlight Brightness Level Duty cycle Mapping Table + /// + for (Index =3D 0; Index < MAX_BCLM_ENTRIES; Index++) { + mIgdOpRegion.OpRegion->MBox3.BCLM[Index] =3D GraphicsDxeConfig->BCLM[I= ndex]; + } + + mIgdOpRegion.OpRegion->MBox3.IUER =3D 0x00; + + if (!EFI_ERROR (Status)) { + mIgdOpRegion.OpRegion->MBox3.IUER =3D GraphicsDxeConfig->IuerStatusVa= l; + } + + /// + /// Initialize hardware state: + /// Set ASLS Register to the OpRegion physical memory address. + /// Set SWSCI register bit 15 to a "1" to activate SCI interrupts. + /// + PciSegmentWrite32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET, (UINT32) (UINT= N) (mIgdOpRegion.OpRegion)); + PciSegmentAndThenOr16 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET, (UINT16) = ~(BIT0), BIT15); + + DwordData =3D PciSegmentRead32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (IgdBaseAddress + R_SA_I= GD_ASLS_OFFSET), + 1, + &DwordData + ); + DwordData =3D PciSegmentRead32 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET); + S3BootScriptSaveMemWrite ( + S3BootScriptWidthUint32, + (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (IgdBaseAddress + R_SA_I= GD_SWSCI_OFFSET), + 1, + &DwordData + ); + + /// + /// Install OpRegion / Software SCI protocol + /// + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gIgdOpRegionProtocolGuid, + &mIgdOpRegion, + NULL + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Return final status + /// + return EFI_SUCCESS; +} + +/** + Update Graphics OpRegion after PCI enumeration. + + @param[in] void - None + @retval EFI_SUCCESS - The function completed successfully. +**/ +EFI_STATUS +UpdateIgdOpRegionEndOfDxe ( + VOID + ) +{ + EFI_STATUS Status; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + UINTN Index; + EFI_PCI_IO_PROTOCOL *PciIo; + PCI_TYPE00 Pci; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + + Bus =3D 0; + Device =3D 0; + Function =3D 0; + + DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n")); + + mIgdOpRegion.OpRegion->Header.PCON |=3D BIT8; //Set External Gfx Adapter= field is valid + mIgdOpRegion.OpRegion->Header.PCON &=3D (UINT32) (~BIT7); //Assume No Ex= ternal Gfx Adapter + + /// + /// Get all PCI IO protocols handles + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + + if (!EFI_ERROR (Status)) { + for (Index =3D 0; Index < HandleCount; Index++) { + /// + /// Get the PCI IO Protocol Interface corresponding to each handle + /// + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiPciIoProtocolGuid, + (VOID **) &PciIo + ); + + if (!EFI_ERROR (Status)) { + /// + /// Read the PCI configuration space + /// + Status =3D PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint32, + 0, + sizeof (Pci) / sizeof (UINT32), + &Pci + ); + + /// + /// Find the display controllers devices + /// + if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) { + Status =3D PciIo->GetLocation ( + PciIo, + &Segment, + &Bus, + &Device, + &Function + ); + + // + // Assumption: Onboard devices will be sits on Bus no 0, while e= xternal devices will be sits on Bus no > 0 + // + if (!EFI_ERROR (Status) && (Bus > 0)) { + //External Gfx Adapter Detected and Available + DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and = Available\n")); + mIgdOpRegion.OpRegion->Header.PCON |=3D BIT7; + break; + } + } + } + } + } + + /// + /// Free any allocated buffers + /// + if (HandleBuffer !=3D NULL) { + FreePool (HandleBuffer); + } + + /// + /// Return final status + /// + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PciE= xpressInit.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Pc= iExpressInit.c new file mode 100644 index 0000000000..bbdf0d0fab --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PciExpressI= nit.c @@ -0,0 +1,171 @@ +/** @file + This driver does SA PCI Express ACPI table initialization. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PciExpressInit.h" + +extern SYSTEM_AGENT_NVS_AREA_PROTOCOL mSaNvsAreaProtocol; +extern SA_CONFIG_HOB *mSaConfigHob; + +/** + PCI Express Dxe Initialization. + Run before PCI Bus Init, where assignment of Bus, Memory, + and I/O Resources are assigned. + + @param[in] SaPolicy - SA DXE Policy protocol + + @retval EFI_SUCCESS - Pci Express successfully started and ready to = be used +**/ +EFI_STATUS +PciExpressInit ( + IN SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + PCIE_DXE_CONFIG *PcieDxeConfig; + MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr; + + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gPcieDxeConfigGuid, (VOID= *)&PcieDxeConfig); + ASSERT_EFI_ERROR (Status); + + + Msr.Uint64 =3D AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL); + mSaNvsAreaProtocol.Area->PackageCstateLimit =3D (UINT8) Msr.Bits.Limit; + + mSaNvsAreaProtocol.Area->PwrDnBundlesGlobalEnable =3D 0; + + if (mSaConfigHob !=3D NULL) { + mSaNvsAreaProtocol.Area->Peg0PowerDownUnusedBundles =3D mSaConfigHob-= >PowerDownUnusedBundles[0]; + mSaNvsAreaProtocol.Area->Peg1PowerDownUnusedBundles =3D mSaConfigHob-= >PowerDownUnusedBundles[1]; + mSaNvsAreaProtocol.Area->Peg2PowerDownUnusedBundles =3D mSaConfigHob-= >PowerDownUnusedBundles[2]; + if (SA_PEG_MAX_FUN > 3) { + mSaNvsAreaProtocol.Area->Peg3PowerDownUnusedBundles =3D mSaConfigHo= b->PowerDownUnusedBundles[3]; + } + } + /// + /// LTR/OBFF + /// + mSaNvsAreaProtocol.Area->Peg0LtrEnable =3D PcieDxeConfig-= >PegPwrOpt[0].LtrEnable; + mSaNvsAreaProtocol.Area->Peg0ObffEnable =3D PcieDxeConfig-= >PegPwrOpt[0].ObffEnable; + mSaNvsAreaProtocol.Area->Peg1LtrEnable =3D PcieDxeConfig-= >PegPwrOpt[1].LtrEnable; + mSaNvsAreaProtocol.Area->Peg1ObffEnable =3D PcieDxeConfig-= >PegPwrOpt[1].ObffEnable; + mSaNvsAreaProtocol.Area->Peg2LtrEnable =3D PcieDxeConfig-= >PegPwrOpt[2].LtrEnable; + mSaNvsAreaProtocol.Area->Peg2ObffEnable =3D PcieDxeConfig-= >PegPwrOpt[2].ObffEnable; + mSaNvsAreaProtocol.Area->PegLtrMaxSnoopLatency =3D LTR_MAX_SNOOP_= LATENCY_VALUE; + mSaNvsAreaProtocol.Area->PegLtrMaxNoSnoopLatency =3D LTR_MAX_NON_SN= OOP_LATENCY_VALUE; + + return EFI_SUCCESS; +} + +/** + Find the Offset to a given Capabilities ID + CAPID list: + 0x01 =3D PCI Power Management Interface + 0x04 =3D Slot Identification + 0x05 =3D MSI Capability + 0x10 =3D PCI Express Capability + + @param[in] Segment - Pci Segment Number + @param[in] Bus - Pci Bus Number + @param[in] Device - Pci Device Number + @param[in] Function - Pci Function Number + @param[in] CapId - CAPID to search for + + @retval 0 - CAPID not found + @retval Other - CAPID found, Offset of desired CAPID +**/ +UINT32 +PcieFindCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 CapId + ) +{ + UINT64 DeviceBaseAddress; + UINT8 CapHeader; + + /// + /// Always start at Offset 0x34 + /// + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Fun= ction, 0); + CapHeader =3D PciSegmentRead8 (DeviceBaseAddress + PCI_CAPBILITY= _POINTER_OFFSET); + if (CapHeader =3D=3D 0xFF) { + return 0; + } + + while (CapHeader !=3D 0) { + /// + /// Bottom 2 bits of the pointers are reserved per PCI Local Bus Spec = 2.2 + /// + CapHeader &=3D ~(BIT1 + BIT0); + /// + /// Search for desired CapID + /// + if (PciSegmentRead8 (DeviceBaseAddress + CapHeader) =3D=3D CapId) { + return CapHeader; + } + + CapHeader =3D PciSegmentRead8 (DeviceBaseAddress + CapHeader + 1); + } + + return 0; +} + +/** + Search and return the offset of desired Pci Express Capability ID + CAPID list: + 0x0001 =3D Advanced Error Rreporting Capability + 0x0002 =3D Virtual Channel Capability + 0x0003 =3D Device Serial Number Capability + 0x0004 =3D Power Budgeting Capability + + @param[in] Segment - Pci Segment Number + @param[in] Bus - Pci Bus Number + @param[in] Device - Pci Device Number + @param[in] Function - Pci Function Number + @param[in] CapId - Extended CAPID to search for + + @retval 0 - CAPID not found + @retval Other - CAPID found, Offset of desired CAPID +**/ +UINT32 +PcieFindExtendedCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT16 CapId + ) +{ + UINT64 DeviceBaseAddress; + UINT16 CapHeaderOffset; + UINT16 CapHeaderId; + + /// + /// Start to search at Offset 0x100 + /// Get Capability Header + /// + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Fun= ction, 0); + CapHeaderId =3D 0; + CapHeaderOffset =3D 0x100; + + while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D 0xFFFF) { + /// + /// Search for desired CapID + /// + CapHeaderId =3D PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset); + if (CapHeaderId =3D=3D CapId) { + return CapHeaderOffset; + } + + CapHeaderOffset =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOf= fset + 2) >> 4); + } + + return 0; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/Pcie= Complex.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PcieC= omplex.c new file mode 100644 index 0000000000..1dc37334ae --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/PcieComplex= .c @@ -0,0 +1,171 @@ +/** @file + This file will perform SA PCIE Root Complex initialization. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PciExpressInit.h" +#include +#include "PcieComplex.h" +#include +#include "SaInit.h" + +/// +/// Global variables +/// +UINT16 mSaIotrapSmiAddress; +extern SA_CONFIG_HOB *mSaConfigHob; + +/// +/// Functions +/// +/** + This function gets registered as a callback to perform all SA late ini= tialization + + @param[in] Event - A pointer to the Event that triggered the callb= ack. + @param[in] Context - A pointer to private data registered with the c= allback function. +**/ +VOID +EFIAPI +SaLateInitSmiCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + SA_IOTRAP_SMI_PROTOCOL *SaIotrapSmiProtocol; + + if (mSaIotrapSmiAddress =3D=3D 0) { + // + // Use global variable instead of protocol data since it maybe tampere= d in unsecure environment + // Get IOTrap address when first time this routine calling (gEfiPciEnu= merationCompleteProtocolGuid callback) + // + SaIotrapSmiProtocol =3D NULL; + Status =3D gBS->LocateProtocol (&gSaIotrapSmiProtocolGuid, NULL, (VOID= **) &SaIotrapSmiProtocol); + ASSERT_EFI_ERROR (Status); + if (SaIotrapSmiProtocol !=3D NULL) { + mSaIotrapSmiAddress =3D SaIotrapSmiProtocol->SaIotrapSmiAddress; + } + } + + ASSERT (mSaIotrapSmiAddress !=3D 0); + if (mSaIotrapSmiAddress !=3D 0) { + // + // Generate IOTRAP SMI immediately + // + DEBUG ((DEBUG_INFO, "[SA] Issue IOTRAP SMI %X\n", mSaIotrapSmiAddress)= ); + IoWrite8 (mSaIotrapSmiAddress, 0); + } + if (Event !=3D NULL) { + gBS->CloseEvent (Event); + } + return; +} + +/** + This function performs Peg initialization before EndOfDxe. + @note This function will be executed as gEfiPciEnumerationCompleteProtoc= olGuid protocol callback and assumed SA DXE/SMM drivers have been dispatche= d. + + @retval EFI_SUCCESS - Always. +**/ +EFI_STATUS +PegInitBeforeEndOfDxe ( + VOID + ) +{ + EFI_EVENT ReadyToBoot; + EFI_STATUS Status; + BOOLEAN AspmHasBeenHandled; + + DEBUG ((DEBUG_INFO, "[SA] Pcie before EndOfDxe callback.\n")); + AspmHasBeenHandled =3D FALSE; + /// + /// SMM mode ASPM handling + /// Check if supported and enabled + /// + if ((mSaConfigHob !=3D NULL) && (mSaConfigHob->InitPcieAspmAfterOprom = =3D=3D TRUE)) { + /// + /// Do the Phase 1 SMI callback + /// This will enumerate PCIe downstream devices + /// + SaLateInitSmiCallback (NULL, NULL); + + if (mSaIotrapSmiAddress !=3D 0) { + /// + /// Create an ReadyToBoot call back event to do the Phase 3 SMI call= back + /// This will handle PEG ASPM programming after OROM execution + /// Note: Phase 2 SMI callback will be triggered in EndOfDxe callback + /// to initialize rest of PCIe settings prior to OPROM + /// + Status =3D EfiCreateEventReadyToBootEx ( + TPL_NOTIFY, + (EFI_EVENT_NOTIFY) SaLateInitSmiCallback, + NULL, + &ReadyToBoot + ); + ASSERT_EFI_ERROR (Status); + AspmHasBeenHandled =3D TRUE; + } + } + + /// + /// DXE mode ASPM handling + /// Check if SMM mode already taken care all things + /// TRUE to skip DXE mode task. Otherwise do DXE mode ASPM initialization + /// + if (AspmHasBeenHandled =3D=3D FALSE) { + + } + + return EFI_SUCCESS; +} + +/** + This function performs SA registers Saving/Restoring in EndOfDxe callback + + @retval EFI_SUCCESS - Save/restore has done + @retval EFI_UNSUPPORTED - Save/restore not done successfully +**/ +EFI_STATUS +SaSaveRestore ( + VOID + ) +{ + BOOLEAN SaveRestoreHasBeenHandled; + UINT8 SmiData; + + SaveRestoreHasBeenHandled =3D FALSE; + + if ((mSaConfigHob !=3D NULL) && (mSaConfigHob->InitPcieAspmAfterOprom = =3D=3D TRUE)) { + /// + /// Generate the Phase 2 of SA SMI to do SA chipset save/restore and s= ecurity lock + /// + SaLateInitSmiCallback (NULL, NULL); + + if (mSaIotrapSmiAddress !=3D 0) { + /// + /// Store IOTRAP SMI address into Boot Script save table + /// This is required to trigger this IOTRAP during S3 resume to rest= ore all settings + /// + SmiData =3D 0; + S3BootScriptSaveIoWrite ( + S3BootScriptWidthUint8, + (UINTN) mSaIotrapSmiAddress, + 1, + &SmiData + ); + SaveRestoreHasBeenHandled =3D TRUE; + } + } + + /// + /// Check if SMM mode already taken care this task + /// + if (SaveRestoreHasBeenHandled =3D=3D TRUE) { + return EFI_SUCCESS; + } else { + return EFI_UNSUPPORTED; + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAc= pi.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c new file mode 100644 index 0000000000..d5a63785b4 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaAcpi.c @@ -0,0 +1,496 @@ +/** @file + This is the driver that initializes the Intel System Agent. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SaInitDxe.h" +#include "SaInit.h" +#include +#include +#include + +/// +/// Global Variables +/// +GLOBAL_REMOVE_IF_UNREFERENCED SYSTEM_AGENT_NVS_AREA_PROTOCOL mSaNvsAreaPr= otocol; +GLOBAL_REMOVE_IF_UNREFERENCED SA_POLICY_PROTOCOL *mSaPolicy; +extern SA_CONFIG_HOB *mSaConfigHo= b; + +/** + Initialize System Agent SSDT ACPI tables + + @retval EFI_SUCCESS ACPI tables are initialized successfully + @retval EFI_NOT_FOUND ACPI tables not found +**/ +EFI_STATUS +InitializeSaSsdtAcpiTables ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN i; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + INTN Instance; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN AcpiTableKey; + UINT8 *CurrPtr; + UINT8 *EndPtr; + UINT32 *Signature; + EFI_ACPI_DESCRIPTION_HEADER *SaAcpiTable; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + + FwVol =3D NULL; + SaAcpiTable =3D NULL; + + /// + /// Locate ACPI Table protocol + /// + DEBUG ((DEBUG_INFO, "Init SA SSDT table\n")); + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID = **) &AcpiTable); + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_WARN, "Fail to locate EfiAcpiTableProtocol.\n")); + return EFI_NOT_FOUND; + } + + /// + /// Locate protocol. + /// There is little chance we can't find an FV protocol + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + /// + /// Looking for FV with ACPI storage file + /// + for (i =3D 0; i < NumberOfHandles; i++) { + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status =3D gBS->HandleProtocol ( + HandleBuffer[i], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &FwVol + ); + ASSERT_EFI_ERROR (Status); + + /// + /// See if it has the ACPI storage file + /// + Size =3D 0; + FvStatus =3D 0; + Status =3D FwVol->ReadFile ( + FwVol, + &gSaSsdtAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (Status =3D=3D EFI_SUCCESS) { + break; + } + } + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + /// + /// Sanity check that we found our data file + /// + ASSERT (FwVol !=3D NULL); + if (FwVol =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "SA Global NVS table not found\n")); + return EFI_NOT_FOUND; + } + /// + /// Our exit status is determined by the success of the previous operati= ons + /// If the protocol was found, Instance already points to it. + /// Read tables from the storage file. + /// + Instance =3D 0; + CurrentTable =3D NULL; + while (Status =3D=3D EFI_SUCCESS) { + Status =3D FwVol->ReadSection ( + FwVol, + &gSaSsdtAcpiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + (VOID **) &CurrentTable, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + /// + /// Check the table ID to modify the table + /// + if (((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->OemTableId =3D= =3D SIGNATURE_64 ('S', 'a', 'S', 's', 'd', 't', ' ', 0)) { + SaAcpiTable =3D (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable; + /// + /// Locate the SSDT package + /// + CurrPtr =3D (UINT8 *) SaAcpiTable; + EndPtr =3D CurrPtr + SaAcpiTable->Length; + + for (; CurrPtr <=3D EndPtr; CurrPtr++) { + Signature =3D (UINT32 *) (CurrPtr + 3); + if (*Signature =3D=3D SIGNATURE_32 ('S', 'A', 'N', 'V')) { + ASSERT (*(UINT32 *) (CurrPtr + 3 + sizeof (*Signature) + 2) = =3D=3D 0xFFFF0000); + ASSERT (*(UINT16 *) (CurrPtr + 3 + sizeof (*Signature) + 2 + s= izeof (UINT32) + 1) =3D=3D 0xAA55); + /// + /// SA Global NVS Area address + /// + *(UINT32 *) (CurrPtr + 3 + sizeof (*Signature) + 2) =3D (UINT3= 2) (UINTN) mSaNvsAreaProtocol.Area; + /// + /// SA Global NVS Area size + /// + *(UINT16 *) (CurrPtr + 3 + sizeof (*Signature) + 2 + sizeof (U= INT32) + 1) =3D + sizeof (SYSTEM_AGENT_NVS_AREA); + + AcpiTableKey =3D 0; + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + SaAcpiTable, + SaAcpiTable->Length, + &AcpiTableKey + ); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; + } + } + } + /// + /// Increment the instance + /// + Instance++; + CurrentTable =3D NULL; + } + } + + return Status; + +} + +/** + Install SSDT Table + + @retval EFI_SUCCESS - SSDT Table load successful. +**/ +EFI_STATUS +InstallSsdtAcpiTable ( + IN GUID SsdtTableGuid, + IN UINT64 Signature + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + BOOLEAN LoadTable; + UINTN NumberOfHandles; + UINTN Index; + INTN Instance; + UINTN Size; + UINT32 FvStatus; + UINTN TableHandle; + EFI_FV_FILETYPE FileType; + EFI_FV_FILE_ATTRIBUTES Attributes; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_ACPI_DESCRIPTION_HEADER *TableHeader; + EFI_ACPI_COMMON_HEADER *Table; + + FwVol =3D NULL; + Table =3D NULL; + + DEBUG ((DEBUG_INFO, "Loading SSDT Table GUID: %g\n", SsdtTableGuid)); + + /// + /// Locate FV protocol. + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Look for FV with ACPI storage file + /// + for (Index =3D 0; Index < NumberOfHandles; Index++) { + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &FwVol + ); + ASSERT_EFI_ERROR (Status); + if (FwVol =3D=3D NULL) { + return EFI_NOT_FOUND; + } + /// + /// See if it has the ACPI storage file + /// + Size =3D 0; + FvStatus =3D 0; + Status =3D FwVol->ReadFile ( + FwVol, + &SsdtTableGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (!EFI_ERROR (Status)) { + break; + } + } + /// + /// Our exit status is determined by the success of the previous operati= ons + /// If the protocol was found, Instance already points to it. + /// + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + /// + /// Sanity check that we found our data file + /// + ASSERT (FwVol); + + /// + /// Locate ACPI tables + /// + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID = **) &AcpiTable); + + /// + /// Read tables from the storage file. + /// + if (FwVol =3D=3D NULL) { + ASSERT_EFI_ERROR (EFI_NOT_FOUND); + return EFI_NOT_FOUND; + } + Instance =3D 0; + + while (Status =3D=3D EFI_SUCCESS) { + /// + /// Read the ACPI tables + /// + Status =3D FwVol->ReadSection ( + FwVol, + &SsdtTableGuid, + EFI_SECTION_RAW, + Instance, + (VOID **) &Table, + &Size, + &FvStatus + ); + if (!EFI_ERROR (Status)) { + /// + /// check and load SwitchableGraphics SSDT table + /// + LoadTable =3D FALSE; + TableHeader =3D (EFI_ACPI_DESCRIPTION_HEADER *) Table; + + if (((EFI_ACPI_DESCRIPTION_HEADER *) TableHeader)->OemTableId =3D=3D= Signature) { + /// + /// This is the SSDT table that match the Signature + /// + DEBUG ((DEBUG_INFO, "Found out SSDT Table GUID: %g\n", SsdtTableGu= id)); + LoadTable =3D TRUE; + } + + /// + /// Add the table + /// + if (LoadTable) { + TableHandle =3D 0; + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + TableHeader, + TableHeader->Length, + &TableHandle + ); + } + /// + /// Increment the instance + /// + Instance++; + Table =3D NULL; + } + } + + return EFI_SUCCESS; +} + +/** + This function gets registered as a callback to perform Dmar Igd + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +SaAcpiEndOfDxeCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 2,= 0, R_SA_IGD_VID)) !=3D 0xFFFF) { + Status =3D PostPmInitEndOfDxe (); + if (EFI_SUCCESS !=3D Status) { + DEBUG ((DEBUG_WARN, "[SA] EndOfDxe GraphicsInit Error, Status =3D %r= \n", Status)); + ASSERT_EFI_ERROR (Status); + } + } + + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 2,= 0, R_SA_IGD_VID)) !=3D 0xFFFF) { + Status =3D GetVBiosVbtEndOfDxe (); + if (EFI_SUCCESS !=3D Status) { + DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Op Region Error, Status =3D %r \n= ", Status)); + } + + Status =3D UpdateIgdOpRegionEndOfDxe (); + if (EFI_SUCCESS !=3D Status) { + DEBUG ((DEBUG_WARN, "[SA] EndOfDxe Update Op Region Error, Status = =3D %r \n", Status)); + } + } + + return; +} + +/** + SystemAgent Acpi Initialization. + + @param[in] ImageHandle Handle for the image of this driver + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate +**/ +EFI_STATUS +EFIAPI +SaAcpiInit ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + EFI_CPUID_REGISTER CpuidRegs; + CPU_FAMILY CpuFamilyId; + EFI_EVENT EndOfDxeEvent; + + CpuFamilyId =3D GetCpuFamily(); + AsmCpuid (1, &CpuidRegs.RegEax, 0, 0, 0); + /// + /// Get the platform setup policy. + /// + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) = &mSaPolicy); + ASSERT_EFI_ERROR (Status); + + /// + /// Install System Agent Global NVS protocol + /// + DEBUG ((DEBUG_INFO, "Install SA GNVS protocol\n")); + Status =3D (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (SYSTEM_AGENT_N= VS_AREA), (VOID **) &mSaNvsAreaProtocol.Area); + ASSERT_EFI_ERROR (Status); + ZeroMem ((VOID *) mSaNvsAreaProtocol.Area, sizeof (SYSTEM_AGENT_NVS_AREA= )); + mSaNvsAreaProtocol.Area->XPcieCfgBaseAddress =3D (UINT32) (PcdGet64 (Pc= dPciExpressBaseAddress)); + mSaNvsAreaProtocol.Area->CpuIdInfo =3D CpuidRegs.RegEax; + if (mSaConfigHob !=3D NULL) { + mSaNvsAreaProtocol.Area->IpuAcpiMode =3D mSaConfigHob->IpuAcpiMode; + } + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gSaNvsAreaProtocolGuid, + &mSaNvsAreaProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + + /// + /// PciExpress Dxe Initialization + /// + DEBUG ((DEBUG_INFO, "Initializing PciExpress (Dxe)\n")); + PciExpressInit (mSaPolicy); + + /// + /// GtPostInit Initialization + /// + DEBUG ((DEBUG_INFO, "Initializing GT ACPI tables\n")); + + GraphicsInit (ImageHandle, mSaPolicy); + + /// Vtd Initialization + /// + DEBUG ((DEBUG_INFO, "Initializing VT-d ACPI tables\n")); + VtdInit (mSaPolicy); + + /// + /// IgdOpRegion Install Initialization + /// + DEBUG ((DEBUG_INFO, "Initializing IGD OpRegion\n")); + IgdOpRegionInit (); + + /// + /// Register an end of DXE event for SA ACPI to do tasks before invoking= any UEFI drivers, + /// applications, or connecting consoles,... + /// + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SaAcpiEndOfDxeCallback, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + + /// + /// Install System Agent Global NVS ACPI table + /// + Status =3D InitializeSaSsdtAcpiTables (); + + /// + /// Install PEG SSDT table only if PEG port is present + /// + if (IsPchLinkDmi (CpuFamilyId)) { + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_PEG_BUS_= NUM, SA_PEG_DEV_NUM, SA_PEG0_FUN_NUM, R_SA_PEG_DID_OFFSET)) !=3D V_SA_DEVIC= E_ID_INVALID) { + Status =3D InstallSsdtAcpiTable (gPegSsdtAcpiTableStorageGuid, SIGNA= TURE_64 ('P','e','g','S','s','d','t',0)); + ASSERT_EFI_ERROR (Status); + } + } + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIn= it.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c new file mode 100644 index 0000000000..40bb107ad0 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit.c @@ -0,0 +1,179 @@ +/** @file + This is the Common driver that initializes the Intel System Agent. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SaInit.h" +#include +#include +#include + +// +// Declare I/O Ports used to perform PCI Confguration Cycles +// +#define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8 +#define PCI_CONFIGURATION_DATA_PORT 0xCFC + +/** + Convert a PCI Library address to PCI CF8 formatted address. + + Declare macro to convert PCI Library address to PCI CF8 formatted addres= s. + Bit fields of PCI Library and CF8 formatted address is as follows: + PCI Library formatted address CF8 Formatted Address + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D + Bits 00..11 Register Bits 00..07 Register + Bits 12..14 Function Bits 08..10 Function + Bits 15..19 Device Bits 11..15 Device + Bits 20..27 Bus Bits 16..23 Bus + Bits 28..31 Reserved(MBZ) Bits 24..30 Reserved(MBZ) + Bits 31..31 Must be 1 + + @param A The address to convert. + + @retval The coverted address. + +**/ +#define PCI_TO_CF8_ADDRESS(A) \ + ((UINT32) ((((A) >> 4) & 0x00ffff00) | ((A) & 0xfc) | 0x80000000)) + +/// +/// Global Variables +/// +GLOBAL_REMOVE_IF_UNREFERENCED SA_CONFIG_HOB *mSaC= onfigHob; +BOOLEAN mSkip= PamLock =3D FALSE; + +/* + Intel(R) Core Processor Skylake BWG version 0.4.0 + + 18.6 System Agent Configuration Locking + For reliable operation and security, System BIOS must set the following= bits: + 1. For all modern Intel processors, Intel strongly recommends that BIOS= should set + the D_LCK bit. Set B0:D0:F0.R088h [4] =3D 1b to lock down SMRAM spa= ce. + BaseAddr values for mSaSecurityRegisters that uses PciExpressBaseAddress= will be initialized at + Runtime inside function SaPcieInitPolicy(). +*/ +GLOBAL_REMOVE_IF_UNREFERENCED BOOT_SCRIPT_REGISTER_SETTING mSaSecurityRegi= sters[] =3D { + {0, R_SA_SMRAMC, 0xFFFFFFFF, BIT4} +}; + +/** + SystemAgent Initialization Common Function. + + @retval EFI_SUCCESS - Always. +**/ + +VOID +SaInitEntryPoint ( + VOID + ) +{ + /// + /// Get SaConfigHob HOB + /// + mSaConfigHob =3D NULL; + mSaConfigHob =3D (SA_CONFIG_HOB *) GetFirstGuidHob (&gSaCon= figHobGuid); + if (mSaConfigHob !=3D NULL) { + mSkipPamLock =3D mSaConfigHob->SkipPamLock; + } + + return; +} + + + +/** + Common function locks the PAM register as part of the SA Security requir= ements. + + @retval EFI_SUCCESS - Always. +**/ + +VOID +SaPamLock ( + VOID + ) +{ + UINT64 BaseAddress; + UINT32 Data32Or; + + if (mSkipPamLock =3D=3D FALSE) { + // + // Lock PAM by PAM Lock Bit + // + BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, 0, 0, 0, 0); + Data32Or =3D BIT0; + DEBUG ((DEBUG_INFO, "PAM_LOCK!!\n")); + PciSegmentOr32 (BaseAddress + R_SA_PAM0, Data32Or); + } +} + +/** + This function does SA security lock +**/ +VOID +SaSecurityLock ( + VOID + ) +{ + UINT8 Index; + UINT32 RegOffset; + UINT32 Data32Or; + UINT32 Data32; + UINT8 Data8; + + /// + /// 17.2 System Agent Security Lock configuration + /// + DEBUG ((DEBUG_INFO, "DXE SaSecurityLock\n")); + for (Index =3D 0; Index < (sizeof (mSaSecurityRegisters) / sizeof (BOOT_= SCRIPT_REGISTER_SETTING)); Index++) { + RegOffset =3D mSaSecurityRegisters[Index].Offset; + Data32Or =3D mSaSecurityRegisters[Index].OrMask; + + if (RegOffset =3D=3D R_SA_SMRAMC) { + /// + /// SMRAMC LOCK must use CF8/CFC access + /// + PciCf8Or8 (PCI_CF8_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_S= A_SMRAMC), (UINT8) Data32Or); + Data8 =3D PciCf8Read8 (PCI_CF8_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA= _MC_FUN, R_SA_SMRAMC)); + Data32 =3D PCI_TO_CF8_ADDRESS (PCI_CF8_LIB_ADDRESS (SA_MC_BUS, SA_MC= _DEV, SA_MC_FUN, R_SA_SMRAMC)); + S3BootScriptSaveIoWrite ( + S3BootScriptWidthUint32, + (UINTN) (PCI_CONFIGURATION_ADDRESS_PORT), + 1, + &Data32 + ); + S3BootScriptSaveIoWrite ( + S3BootScriptWidthUint8, + (UINTN) (PCI_CONFIGURATION_DATA_PORT), + 1, + &Data8 + ); + } + } +} + +/** + This function performs SA Security locking in EndOfDxe callback + + @retval EFI_SUCCESS - Security lock has done + @retval EFI_UNSUPPORTED - Security lock not done successfully +**/ +EFI_STATUS +SaSecurityInit ( + VOID + ) +{ + + UINT8 Index; + + for (Index =3D 0; Index < (sizeof (mSaSecurityRegisters) / sizeof (BOOT_= SCRIPT_REGISTER_SETTING)); Index++) { + if (mSaSecurityRegisters[Index].BaseAddr !=3D PcdGet64 (PcdMchBaseAddr= ess)) { + mSaSecurityRegisters[Index].BaseAddr =3D PcdGet64 (PcdPciExpressBase= Address); + } + } + SaSecurityLock (); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaIn= itDxe.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitD= xe.c new file mode 100644 index 0000000000..d646e60618 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c @@ -0,0 +1,122 @@ +/** @file + This is the driver that initializes the Intel System Agent. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SaInitDxe.h" +#include "SaInit.h" +#include +#include +#include + +/// +/// Global Variables +/// +extern SA_CONFIG_HOB *mSaConfigHob; + +/** + SystemAgent Dxe Initialization. + + @param[in] ImageHandle Handle for the image of this driver + @param[in] SystemTable Pointer to the EFI System Table + + @retval EFI_SUCCESS The function completed successfully + @retval EFI_OUT_OF_RESOURCES No enough buffer to allocate +**/ +EFI_STATUS +EFIAPI +SaInitEntryPointDxe ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + VOID *Registration; + + DEBUG ((DEBUG_INFO, "SaInitDxe Start\n")); + + SaInitEntryPoint (); + + Status =3D SaAcpiInit (ImageHandle); + + /// + /// Create PCI Enumeration Completed callback for SA + /// + EfiCreateProtocolNotifyEvent ( + &gEfiPciEnumerationCompleteProtocolGuid, + TPL_CALLBACK, + SaPciEnumCompleteCallback, + NULL, + &Registration + ); + + DEBUG ((DEBUG_INFO, "SaInitDxe End\n")); + + return EFI_SUCCESS; +} + +/** + This function gets registered as a callback to perform SA initialization= before EndOfDxe + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +SaPciEnumCompleteCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + VOID *ProtocolPointer; + + DEBUG ((DEBUG_INFO, "SaPciEnumCompleteCallback Start\n")); + /// + /// Check if this is first time called by EfiCreateProtocolNotifyEvent()= or not, + /// if it is, we will skip it until real event is triggered + /// + Status =3D gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid,= NULL, (VOID **) &ProtocolPointer); + if (EFI_SUCCESS !=3D Status) { + return; + } + + gBS->CloseEvent (Event); + + Status =3D PegInitBeforeEndOfDxe (); + if (EFI_SUCCESS !=3D Status) { + DEBUG ((DEBUG_WARN, "[SA] Pcie initialization before EndOfDxe Error, S= tatus =3D %r \n", Status)); + ASSERT_EFI_ERROR (Status); + } + + SaSaveRestore (); + SaSecurityInit (); + UpdateDmarPciEnumCompleteCallback (); + + DEBUG ((DEBUG_INFO, "SaPciEnumCompleteCallback End\n")); + return; +} + +/** + This function locks the PAM register as part of the SA Security requirem= ents. + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. + +**/ +VOID +EFIAPI +SaPamLockDxe ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + DEBUG ((DEBUG_INFO, "SaPamLockDxe Start\n")); + + SaPamLock (); + + DEBUG ((DEBUG_INFO, "SaPamLockDxe End\n")); +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.= c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.c new file mode 100644 index 0000000000..acbf6b7aab --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/VTd.c @@ -0,0 +1,717 @@ +/** @file + This code provides a initialization of intel VT-d (Virtualization Techno= logy for Directed I/O). + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SaInitDxe.h" +#include "SaInit.h" +#include "VTd.h" +#include +#include +#include +#include +#include +#include +#include + + +extern SA_CONFIG_HOB *mSaConfigHo= b; + +/** + For device that specified by Device Num and Function Num, + mDevEnMap is used to check device presence. + 0x80 means use Device ID to detemine presence + 0x8F means force to update + + The structure is used to check if device scope is valid when update DMAR= table +**/ +UINT16 mDevEnMap[][2] =3D {{0x0200, 0x80}, {0x1400, 0x80}, {0x1401, 0x80}= , {0x1607, 0x8F}}; + +BOOLEAN mInterruptRemappingSupport; + +/** + Get the corresponding device Enable/Disable bit according DevNum and Fun= Num + + @param[in] DevNum - Device Number + @param[in] FunNum - Function Number + + @retval If the device is found, return disable/Enable bit in FD/Deven re= igster + @retval If not found return 0xFF +**/ +UINT16 +GetFunDisableBit ( + UINT8 DevNum, + UINT8 FunNum + ) +{ + UINTN Index; + + for (Index =3D 0; Index < sizeof (mDevEnMap) / 4; Index++) { + if (mDevEnMap[Index][0] =3D=3D ((DevNum << 0x08) | FunNum)) { + return mDevEnMap[Index][1]; + } + } + + return 0xFF; +} + +/** + Update the DRHD structure + + @param[in, out] DrhdEnginePtr - A pointer to DRHD structure +**/ +VOID +UpdateDrhd ( + IN OUT VOID *DrhdEnginePtr + ) +{ + UINT16 Length; + UINT16 DisableBit; + BOOLEAN NeedRemove; + EFI_ACPI_DRHD_ENGINE1_STRUCT *DrhdEngine; + + // + // Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE1_STRUCT Pointer + // + DrhdEngine =3D (EFI_ACPI_DRHD_ENGINE1_STRUCT *) DrhdEnginePtr; + Length =3D DrhdEngine->DrhdHeader.Header.Length; + DisableBit =3D GetFunDisableBit ( + DrhdEngine->DeviceScope[0].PciPath.Device, + DrhdEngine->DeviceScope[0].PciPath.Function + ); + NeedRemove =3D FALSE; + + if ((DisableBit =3D=3D 0xFF) || + (DrhdEngine->DrhdHeader.RegisterBaseAddress =3D=3D 0) || + ((DisableBit =3D=3D 0x80) && + (PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, 0, DrhdEngi= ne->DeviceScope[0].PciPath.Device, DrhdEngine->DeviceScope[0].PciPath.Funct= ion, 0x00)) =3D=3D 0xFFFFFFFF)) + ) { + NeedRemove =3D TRUE; + } + if (NeedRemove) { + Length -=3D sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + } + /// + /// If no devicescope is left, we set the structure length as 0x00 + /// + if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine->DrhdHe= ader.Flags =3D=3D 0x01)) { + DrhdEngine->DrhdHeader.Header.Length =3D Length; + } else { + DrhdEngine->DrhdHeader.Header.Length =3D 0; + } +} + +/** + Get IOAPIC ID from LPC + + @retval APIC ID +**/ +UINT8 +GetIoApicId ( + VOID + ) +{ + UINT32 IoApicAddress; + UINT32 IoApicId; + + IoApicAddress =3D PcdGet32 (PcdIoApicBaseAddress); + /// + /// Get current IO APIC ID + /// + MmioWrite8 ((UINTN) (IoApicAddress + R_IO_APIC_INDEX_OFFSET), 0); + IoApicId =3D MmioRead32 ((UINTN) (IoApicAddress + R_IO_APIC_DATA_OFFSET)= ) >> 24; + + return (UINT8) IoApicId; +} + +/** + Update the second DRHD structure + + @param[in, out] DrhdEnginePtr - A pointer to DRHD structure +**/ +VOID +UpdateDrhd2 ( + IN OUT VOID *DrhdEnginePtr + ) +{ + UINT16 Length; + UINTN DeviceScopeNum; + UINTN ValidDeviceScopeNum; + UINT16 Index; + UINT8 Bus; + UINT8 Path[2]; + BOOLEAN NeedRemove; + EFI_ACPI_DRHD_ENGINE3_STRUCT *DrhdEngine; + VOID *HobPtr; + PCH_INFO_HOB *PchInfoHob; + + /// + /// Convert DrhdEnginePtr to EFI_ACPI_DRHD_ENGINE3_STRUCT Pointer + /// + DrhdEngine =3D (EFI_ACPI_DRHD_ENGINE3_STRUCT *) DrhdEnginePtr; + + Length =3D DrhdEngine->DrhdHeader.Header.Length; + DeviceScopeNum =3D (DrhdEngine->DrhdHeader.Header.Length - EFI_ACPI_DRH= D_ENGINE_HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + Bus =3D 0; + ValidDeviceScopeNum =3D 0; + Path[0] =3D 0; + Path[1] =3D 0; + + HobPtr =3D GetFirstGuidHob (&gPchInfoHobGuid); + ASSERT (HobPtr !=3D NULL); + if (HobPtr =3D=3D NULL) { + return; + } + PchInfoHob =3D (PCH_INFO_HOB *) GET_GUID_HOB_DATA (HobPtr); + ASSERT (PchInfoHob !=3D NULL); + if (PchInfoHob =3D=3D NULL) { + return; + } + + for (Index =3D 0; Index < DeviceScopeNum; Index++) { + NeedRemove =3D FALSE; + /** + For HPET and APIC, update device scope if Interrupt remapping is sup= ported. remove device scope + if interrupt remapping is not supported. + - Index =3D 0 - IOAPIC + - Index =3D 1 - HPET + **/ + if (mInterruptRemappingSupport) { + if (Index =3D=3D 0) { + /// + /// Update source id for IoApic's device scope entry + /// + Bus =3D (UINT8) PchInfoHob->IoApicBusNum; + Path[0] =3D (UINT8) PchInfoHob->IoApicDevNum; + Path[1] =3D (UINT8) PchInfoHob->IoApicFuncNum; + DrhdEngine->DeviceScope[Index].DeviceScopeStructureHeader.StartBus= Number =3D Bus; + DrhdEngine->DeviceScope[Index].PciPath.Device =3D Path[0]; + DrhdEngine->DeviceScope[Index].PciPath.Function =3D Path[1]; + // + // Update APIC ID + // + DrhdEngine->DeviceScope[Index].DeviceScopeStructureHeader.Enumerat= ionId =3D GetIoApicId (); + } + if (Index =3D=3D 1) { + /// + /// Update source id for HPET's device scope entry + /// + Bus =3D (UINT8) PchInfoHob->HpetBusNum; + Path[0] =3D (UINT8) PchInfoHob->HpetDevNum; + Path[1] =3D (UINT8) PchInfoHob->HpetFuncNum; + DrhdEngine->DeviceScope[Index].DeviceScopeStructureHeader.StartBus= Number =3D Bus; + DrhdEngine->DeviceScope[Index].PciPath.Device =3D Path[0]; + DrhdEngine->DeviceScope[Index].PciPath.Function =3D Path[1]; + } + } else { + if ((Index =3D=3D 0) || (Index =3D=3D 1)) { + NeedRemove =3D TRUE; + } + } + + CopyMem ( + &DrhdEngine->DeviceScope[ValidDeviceScopeNum], + &DrhdEngine->DeviceScope[Index], + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE) + ); + if (NeedRemove) { + Length -=3D sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + } else { + ValidDeviceScopeNum++; + } + } + /// + /// If no devicescope is left, we set the structure length as 0x00 + /// + if ((Length > EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH) || (DrhdEngine->DrhdHe= ader.Flags =3D=3D 0x01)) { + DrhdEngine->DrhdHeader.Header.Length =3D Length; + } else { + DrhdEngine->DrhdHeader.Header.Length =3D 0; + } +} + +/** + Update the RMRR structure + + @param[in, out] RmrrPtr - A pointer to RMRR structure +**/ +VOID +UpdateRmrr ( + IN OUT VOID *RmrrPtr + ) +{ + UINT16 Length; + UINT16 DisableBit; + UINTN DeviceScopeNum; + UINTN ValidDeviceScopeNum; + UINTN Index; + BOOLEAN NeedRemove; + EFI_ACPI_RMRR_USB_STRUC *Rmrr; + + /// + /// To make sure all devicescope can be checked, + /// we convert the RmrrPtr to EFI_ACPI_RMRR_USB_STRUC pointer + /// + Rmrr =3D (EFI_ACPI_RMRR_USB_STRUC *) RmrrPtr; + + Length =3D Rmrr->RmrrHeader.Header.Length; + ValidDeviceScopeNum =3D 0; + DeviceScopeNum =3D (Rmrr->RmrrHeader.Header.Length - EFI_ACPI_RMRR_= HEADER_LENGTH) / sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + for (Index =3D 0; Index < DeviceScopeNum; Index++) { + DisableBit =3D GetFunDisableBit ( + Rmrr->DeviceScope[Index].PciPath.Device, + Rmrr->DeviceScope[Index].PciPath.Function + ); + NeedRemove =3D FALSE; + if ((DisableBit =3D=3D 0xFF) || + ((DisableBit =3D=3D 0x80) && + (PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, 0, Rmrr->= DeviceScope[Index].PciPath.Device, Rmrr->DeviceScope[Index].PciPath.Functio= n, 0x00)) =3D=3D 0xFFFFFFFF)) + ) { + NeedRemove =3D TRUE; + } else if (DisableBit =3D=3D 0x8F) { + NeedRemove =3D FALSE; + } + CopyMem ( + &Rmrr->DeviceScope[ValidDeviceScopeNum], + &Rmrr->DeviceScope[Index], + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE) + ); + + if (Rmrr->RmrrHeader.ReservedMemoryRegionLimitAddress =3D=3D 0x0) { + NeedRemove =3D TRUE; + } + + if (NeedRemove) { + Length -=3D sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE); + } else { + ValidDeviceScopeNum++; + } + } + /// + /// If No deviceScope is left, set length as 0x00 + /// + if (Length > EFI_ACPI_RMRR_HEADER_LENGTH) { + Rmrr->RmrrHeader.Header.Length =3D Length; + } else { + Rmrr->RmrrHeader.Header.Length =3D 0; + } +} + +/** + Update the DMAR table + + @param[in, out] TableHeader - The table to be set + @param[in, out] Version - Version to publish +**/ +VOID +DmarTableUpdate ( + IN OUT EFI_ACPI_DESCRIPTION_HEADER *TableHeader, + IN OUT EFI_ACPI_TABLE_VERSION *Version + ) +{ + EFI_ACPI_DMAR_TABLE *DmarTable; + EFI_ACPI_DMAR_TABLE TempDmarTable; + UINTN Offset; + UINTN StructureLen; + UINT64 McD0BaseAddress; + UINTN MchBar; + UINT16 IgdMode; + UINT16 GttMode; + UINT32 IgdMemSize; + UINT32 GttMemSize; + EFI_STATUS Status; + MISC_DXE_CONFIG *MiscDxeConfig; + + IgdMemSize =3D 0; + GttMemSize =3D 0; + DmarTable =3D (EFI_ACPI_DMAR_TABLE *) TableHeader; + + Status =3D GetConfigBlock ((VOID *) mSaPolicy, &gMiscDxeConfigGuid, (VOI= D *)&MiscDxeConfig); + ASSERT_EFI_ERROR (Status); + + /// + /// Set INTR_REMAP bit (BIT 0) if interrupt remapping is supported + /// + if (mInterruptRemappingSupport) { + DmarTable->DmarHeader.Flags |=3D BIT0; + } + + if (mSaConfigHob->VtdData.X2ApicOptOut =3D=3D 1) { + DmarTable->DmarHeader.Flags |=3D BIT1; + } else { + DmarTable->DmarHeader.Flags &=3D 0xFD; + } + + /// + /// Get OemId + /// + CopyMem (DmarTable->DmarHeader.Header.OemId, PcdGetPtr (PcdAcpiDefaultOe= mId), sizeof (DmarTable->DmarHeader.Header.OemId)); + DmarTable->DmarHeader.Header.OemTableId =3D PcdGet64 (PcdAcpiDefaul= tOemTableId); + DmarTable->DmarHeader.Header.OemRevision =3D PcdGet32 (PcdAcpiDefaul= tOemRevision); + DmarTable->DmarHeader.Header.CreatorId =3D PcdGet32 (PcdAcpiDefaul= tCreatorId); + DmarTable->DmarHeader.Header.CreatorRevision =3D PcdGet32 (PcdAcpiDefaul= tCreatorRevision); + + /// + /// Calculate IGD memsize + /// + McD0BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0= , 0); + MchBar =3D PciSegmentRead32 (McD0BaseAddress + R_SA_MCHBAR) & ~= BIT0; + IgdMode =3D ((PciSegmentRead16 (McD0BaseAddress + R_SA_GGC) & B_SA_GGC_G= MS_MASK) >> N_SA_GGC_GMS_OFFSET) & 0xFF; + if (IgdMode < 0xF0) { + IgdMemSize =3D IgdMode * 32 * (1024) * (1024); + } else { + IgdMemSize =3D 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024); + } + /// + /// Calculate GTT mem size + /// + GttMemSize =3D 0; + GttMode =3D (PciSegmentRead16 (McD0BaseAddress + R_SA_GGC) & B_SA_GGC_GG= MS_MASK) >> N_SA_GGC_GGMS_OFFSET; + if (GttMode <=3D V_SA_GGC_GGMS_8MB) { + GttMemSize =3D (1 << GttMode) * (1024) * (1024); + } + + DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress =3D (Pci= SegmentRead32 (McD0BaseAddress + R_SA_TOLUD) & ~(0x01)) - IgdMemSize - GttM= emSize; + DmarTable->RmrrIgd.RmrrHeader.ReservedMemoryRegionLimitAddress =3D Dmar= Table->RmrrIgd.RmrrHeader.ReservedMemoryRegionBaseAddress + IgdMemSize + Gt= tMemSize - 1; + DEBUG ((DEBUG_INFO, "RMRR Base address IGD %016lX\n", DmarTable->RmrrIg= d.RmrrHeader.ReservedMemoryRegionBaseAddress)); + DEBUG ((DEBUG_INFO, "RMRR Limit address IGD %016lX\n", DmarTable->RmrrIg= d.RmrrHeader.ReservedMemoryRegionLimitAddress)); + + DmarTable->RmrrUsb.RmrrHeader.ReservedMemoryRegionBaseAddress =3D Misc= DxeConfig->RmrrUsbBaseAddress[0]; + DmarTable->RmrrUsb.RmrrHeader.ReservedMemoryRegionLimitAddress =3D Misc= DxeConfig->RmrrUsbBaseAddress[1]; + + /// + /// Convert to 4KB alignment. + /// + if (DmarTable->RmrrUsb.RmrrHeader.ReservedMemoryRegionLimitAddress !=3D = 0x0) { + DmarTable->RmrrUsb.RmrrHeader.ReservedMemoryRegionBaseAddress &=3D (E= FI_PHYSICAL_ADDRESS) ~0xFFF; + DmarTable->RmrrUsb.RmrrHeader.ReservedMemoryRegionLimitAddress &=3D (E= FI_PHYSICAL_ADDRESS) ~0xFFF; + DmarTable->RmrrUsb.RmrrHeader.ReservedMemoryRegionLimitAddress +=3D 0x= 1000-1; + } + + DEBUG ((DEBUG_INFO, "RMRR Base address USB %016lX\n", DmarTable->RmrrUs= b.RmrrHeader.ReservedMemoryRegionBaseAddress)); + DEBUG ((DEBUG_INFO, "RMRR Limit address USB %016lX\n", DmarTable->RmrrUs= b.RmrrHeader.ReservedMemoryRegionLimitAddress)); + + if (DmarTable->RmrrUsb.RmrrHeader.ReservedMemoryRegionBaseAddress =3D=3D= 0) { + DEBUG ((DEBUG_WARN, "WARNING: RmrrUsb.RmrrHeader.ReservedMemoryRegion= BaseAddress is 0.\n")); + } + + DmarTable->RmrrCsme.RmrrHeader.ReservedMemoryRegionBaseAddress =3D Mis= cDxeConfig->RmrrCsmeBaseAddress[0]; + DmarTable->RmrrCsme.RmrrHeader.ReservedMemoryRegionLimitAddress =3D Mis= cDxeConfig->RmrrCsmeBaseAddress[1]; + DEBUG ((DEBUG_INFO, "RMRR Base address CSME %016lX\n", DmarTable->RmrrC= sme.RmrrHeader.ReservedMemoryRegionBaseAddress)); + DEBUG ((DEBUG_INFO, "RMRR Limit address CSME %016lX\n", DmarTable->RmrrC= sme.RmrrHeader.ReservedMemoryRegionLimitAddress)); + /// + /// Update DRHD structures of DmarTable + /// + DmarTable->DrhdEngine1.DrhdHeader.RegisterBaseAddress =3D (MmioRead32 (M= chBar + R_SA_MCHBAR_VTD1_OFFSET) &~1); + DmarTable->DrhdEngine3.DrhdHeader.RegisterBaseAddress =3D (MmioRead32 (M= chBar + R_SA_MCHBAR_VTD3_OFFSET) &~1); + + DEBUG ((DEBUG_INFO, "VTD base address1 %x\n", DmarTable->DrhdEngine1.Drh= dHeader.RegisterBaseAddress)); + DEBUG ((DEBUG_INFO, "VTD base address3 %x\n", DmarTable->DrhdEngine3.Drh= dHeader.RegisterBaseAddress)); + /// + /// copy DmarTable to TempDmarTable to be processed + /// + CopyMem (&TempDmarTable, DmarTable, sizeof (EFI_ACPI_DMAR_TABLE)); + + /// + /// Update DRHD structures of temp DMAR table + /// + UpdateDrhd (&TempDmarTable.DrhdEngine1); + UpdateDrhd2 (&TempDmarTable.DrhdEngine3); + + /// + /// Update RMRR structures of temp DMAR table + /// + UpdateRmrr ((VOID *) &TempDmarTable.RmrrUsb); + UpdateRmrr ((VOID *) &TempDmarTable.RmrrIgd); + UpdateRmrr ((VOID *) &TempDmarTable.RmrrCsme); + + /// + /// Remove unused device scope or entire DRHD structures + /// + Offset =3D (UINTN) (&TempDmarTable.DrhdEngine1); + if (TempDmarTable.DrhdEngine1.DrhdHeader.Header.Length !=3D 0) { + Offset +=3D TempDmarTable.DrhdEngine1.DrhdHeader.Header.Length; + } + if (TempDmarTable.DrhdEngine3.DrhdHeader.Header.Length !=3D 0) { + StructureLen =3D TempDmarTable.DrhdEngine3.DrhdHeader.Header.Length; + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.DrhdEngine3, TempDma= rTable.DrhdEngine3.DrhdHeader.Header.Length); + Offset +=3D StructureLen; + } + /// + /// Remove unused device scope or entire RMRR structures + /// + if (TempDmarTable.RmrrUsb.RmrrHeader.Header.Length !=3D 0) { + StructureLen =3D TempDmarTable.RmrrUsb.RmrrHeader.Header.Length; + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrUsb, TempDmarTab= le.RmrrUsb.RmrrHeader.Header.Length); + Offset +=3D StructureLen; + } + if (TempDmarTable.RmrrIgd.RmrrHeader.Header.Length !=3D 0) { + StructureLen =3D TempDmarTable.RmrrIgd.RmrrHeader.Header.Length; + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrIgd, TempDmarTab= le.RmrrIgd.RmrrHeader.Header.Length); + Offset +=3D StructureLen; + } + if (TempDmarTable.RmrrCsme.RmrrHeader.Header.Length !=3D 0) { + StructureLen =3D TempDmarTable.RmrrCsme.RmrrHeader.Header.Length; + CopyMem ((VOID *) Offset, (VOID *) &TempDmarTable.RmrrCsme, TempDmarTa= ble.RmrrCsme.RmrrHeader.Header.Length); + Offset +=3D StructureLen; + } + + Offset =3D Offset - (UINTN) &TempDmarTable; + /// + /// Re-calculate DMAR table check sum + /// + TempDmarTable.DmarHeader.Header.Checksum =3D (UINT8) (TempDmarTable.Dmar= Header.Header.Checksum + TempDmarTable.DmarHeader.Header.Length - Offset); + /// + /// Set DMAR table length + /// + TempDmarTable.DmarHeader.Header.Length =3D (UINT32) Offset; + /// + /// Replace DMAR table with rebuilt table TempDmarTable + /// + CopyMem ((VOID *) DmarTable, (VOID *) &TempDmarTable, TempDmarTable.Dmar= Header.Header.Length); +} + +/** + PciEnumerationComplete routine for update DMAR +**/ +VOID +UpdateDmarPciEnumCompleteCallback ( + VOID + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN i; + INTN Instance; + EFI_ACPI_TABLE_VERSION Version; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINTN AcpiTableHandle; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + EFI_ACPI_DESCRIPTION_HEADER *VtdAcpiTable; + STATIC BOOLEAN Triggered =3D FALSE; + + + if (Triggered) { + return; + } + + Triggered =3D TRUE; + + FwVol =3D NULL; + AcpiTable =3D NULL; + VtdAcpiTable =3D NULL; + + DEBUG ((DEBUG_INFO, "UpdateDmarPciEnumCompleteCallback \n")); + + + /// + /// Fix DMAR Table always created, skip install when disabled + /// + if ((mSaConfigHob->VtdData.VtdDisable =3D=3D TRUE) || (PciSegmentRead32 = (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, 0, R_SA_MC_CAPID0_A_OFF= SET)) & BIT23)) { + DEBUG ((DEBUG_INFO, "Vtd Disabled, skip DMAR Table install\n")); + return; + } + + + /// + /// Locate ACPI support protocol + /// + Status =3D gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID = **) &AcpiTable); + + /// + /// Locate protocol. + /// There is little chance we can't find an FV protocol + /// + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Looking for FV with ACPI storage file + /// + for (i =3D 0; i < NumberOfHandles; i++) { + /// + /// Get the protocol on this handle + /// This should not fail because of LocateHandleBuffer + /// + Status =3D gBS->HandleProtocol ( + HandleBuffer[i], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &FwVol + ); + ASSERT_EFI_ERROR (Status); + + /// + /// See if it has the ACPI storage file + /// + Size =3D 0; + FvStatus =3D 0; + Status =3D FwVol->ReadFile ( + FwVol, + &gSaAcpiTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + + /// + /// If we found it, then we are done + /// + if (Status =3D=3D EFI_SUCCESS) { + break; + } + } + /// + /// Our exit status is determined by the success of the previous operati= ons + /// If the protocol was found, Instance already points to it. + /// + /// + /// Free any allocated buffers + /// + FreePool (HandleBuffer); + + /// + /// Sanity check that we found our data file + /// + ASSERT (FwVol); + if (FwVol =3D=3D NULL) { + return; + } + /// + /// By default, a table belongs in all ACPI table versions published. + /// + Version =3D EFI_ACPI_TABLE_VERSION_1_0B | EFI_ACPI_TABLE_VERSION_2_0 | E= FI_ACPI_TABLE_VERSION_3_0; + + /// + /// Read tables from the storage file. + /// + Instance =3D 0; + CurrentTable =3D NULL; + + while (Status =3D=3D EFI_SUCCESS) { + Status =3D FwVol->ReadSection ( + FwVol, + &gSaAcpiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + (VOID **) &CurrentTable, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + /// + /// Check the Signature ID to modify the table + /// + switch (((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Signature) { + + case EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE: + VtdAcpiTable =3D (EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable; + DmarTableUpdate (VtdAcpiTable, &Version); + break; + + default: + break; + } + /// + /// Increment the instance + /// + Instance++; + CurrentTable =3D NULL; + } + } + /// + /// Update the VTD table in the ACPI tables. + /// + AcpiTableHandle =3D 0; + if (VtdAcpiTable !=3D NULL) { + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + VtdAcpiTable, + VtdAcpiTable->Length, + &AcpiTableHandle + ); + FreePool (VtdAcpiTable); + } +} + +/** + Locate the VT-d ACPI tables data file and read ACPI SSDT tables. + Publish the appropriate SSDT based on current configuration and capabili= ties. + + @param[in] SaPolicy - SA DXE Policy protocol + + @retval EFI_SUCCESS - Vtd initialization complete + @exception EFI_UNSUPPORTED - Vtd is not enabled by policy +**/ +EFI_STATUS +VtdInit ( + IN SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + UINT64 McD0BaseAddress; + UINT64 McD2BaseAddress; + UINTN MchBar; + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol; + + mInterruptRemappingSupport =3D FALSE; + mSaConfigHob =3D NULL; + mSaConfigHob =3D GetFirstGuidHob (&gSaConfigHobGuid); + if (mSaConfigHob !=3D NULL) { + mInterruptRemappingSupport =3D mSaConfigHob->VtdData.InterruptRemappi= ngSupport; + } + + /// + /// Locate the SA Global NVS Protocol. + /// + Status =3D gBS->LocateProtocol ( + &gSaNvsAreaProtocolGuid, + NULL, + (VOID **) &SaNvsAreaProtocol + ); + if (EFI_ERROR (Status)) { + return Status; + } + + McD0BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0, = 0, 0); + McD2BaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_IGD_BUS, SA= _IGD_DEV, SA_IGD_FUN_0, 0); + mSaPolicy =3D SaPolicy; + MchBar =3D PciSegmentRead32(McD0BaseAddress + R_SA_MCHBAR) & ~= BIT0; + + if (mSaConfigHob !=3D NULL) { + SaNvsAreaProtocol->Area->VtdDisable =3D mSaConfigHob->VtdData.VtdDisab= le; + } + SaNvsAreaProtocol->Area->VtdBaseAddress1 =3D (MmioRead32(MchBar + R_SA_M= CHBAR_VTD1_OFFSET) &~1); + SaNvsAreaProtocol->Area->VtdBaseAddress3 =3D (MmioRead32(MchBar + R_SA_M= CHBAR_VTD3_OFFSET) &~1); + SaNvsAreaProtocol->Area->VtdEngine1Vid =3D PciSegmentRead16(McD2BaseAddr= ess + PCI_VENDOR_ID_OFFSET); + + if (mSaConfigHob !=3D NULL) { + if ((mSaConfigHob->VtdData.VtdDisable) || (PciSegmentRead32 (McD0BaseA= ddress + R_SA_MC_CAPID0_A_OFFSET) & BIT23)) { + DEBUG ((DEBUG_WARN, "VTd disabled or no capability!\n")); + return EFI_UNSUPPORTED; + } + } + /// + /// Check SA supports VTD and VTD is enabled in setup menu + /// + DEBUG ((DEBUG_INFO, "VTd enabled\n")); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/S= mmAccessDriver.c b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess= /Dxe/SmmAccessDriver.c new file mode 100644 index 0000000000..08fd9266c6 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SmmAccess/Dxe/SmmAcces= sDriver.c @@ -0,0 +1,356 @@ +/** @file + This is the driver that publishes the SMM Access Protocol + instance for System Agent. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SmmAccessDriver.h" + +static SMM_ACCESS_PRIVATE_DATA mSmmAccess; + + +/** + This is the standard EFI driver point that + installs an SMM Access Protocol + + @param[in] ImageHandle - Handle for the image of this driver + @param[in] SystemTable - Pointer to the EFI System Table + + @retval EFI_SUCCESS - Protocol was installed successfully + @exception EFI_UNSUPPORTED - Protocol was not installed + @retval EFI_NOT_FOUND - Protocol can't be found. + @retval EFI_OUT_OF_RESOURCES - Protocol does not have enough resources = to initialize the driver. +**/ +EFI_STATUS +EFIAPI +SmmAccessDriverEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINTN Index; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock; + EFI_PEI_HOB_POINTERS *Hob; + + /// + /// --cr-- INITIALIZE_SCRIPT (ImageHandle, SystemTable); + /// + /// Initialize Global variables + /// + ZeroMem (&mSmmAccess, sizeof (mSmmAccess)); + + mSmmAccess.Signature =3D SMM_ACCESS_PRIVATE_DATA_SIGNATURE; + mSmmAccess.Handle =3D NULL; + + /// + /// Get Hob list + /// + Hob =3D GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid); + if (Hob =3D=3D NULL) { + DEBUG ((DEBUG_WARN, "SmramMemoryReserve HOB not found\n")); + return EFI_NOT_FOUND; + } + + DescriptorBlock =3D (VOID *) ((UINT8 *) Hob + sizeof (EFI_HOB_GUID_TYPE)= ); + + /// + /// Alloc space for mSmmAccess.SmramDesc + /// + mSmmAccess.SmramDesc =3D AllocateZeroPool ((DescriptorBlock->NumberOfSmm= ReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR)); + if (mSmmAccess.SmramDesc =3D=3D NULL) { + DEBUG ((DEBUG_WARN, "Alloc mSmmAccess.SmramDesc fail.\n")); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "Alloc mSmmAccess.SmramDesc success.\n")); + + /// + /// Use the HOB to publish SMRAM capabilities + /// + for (Index =3D 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; I= ndex++) { + mSmmAccess.SmramDesc[Index].PhysicalStart =3D DescriptorBlock->Descrip= tor[Index].PhysicalStart; + mSmmAccess.SmramDesc[Index].CpuStart =3D DescriptorBlock->Descrip= tor[Index].CpuStart; + mSmmAccess.SmramDesc[Index].PhysicalSize =3D DescriptorBlock->Descrip= tor[Index].PhysicalSize; + mSmmAccess.SmramDesc[Index].RegionState =3D DescriptorBlock->Descrip= tor[Index].RegionState; + } + + mSmmAccess.NumberRegions =3D Index; + mSmmAccess.SmmAccess.Open =3D Open; + mSmmAccess.SmmAccess.Close =3D Close; + mSmmAccess.SmmAccess.Lock =3D Lock; + mSmmAccess.SmmAccess.GetCapabilities =3D GetCapabilities; + mSmmAccess.SmmAccess.LockState =3D FALSE; + mSmmAccess.SmmAccess.OpenState =3D FALSE; + + /// + /// Install our protocol interfaces on the device's handle + /// + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &mSmmAccess.Handle, + &gEfiSmmAccess2ProtocolGuid, + &mSmmAccess.SmmAccess, + NULL + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "InstallMultipleProtocolInterfaces returned %r\n",= Status)); + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + This routine accepts a request to "open" a region of SMRAM. The + region could be legacy ABSEG, HSEG, or TSEG near top of physical memory. + The use of "open" means that the memory is visible from all boot-service + and SMM agents. + + @param[in] This - Pointer to the SMM Access Interface. + + @retval EFI_SUCCESS - The region was successfully opened. + @retval EFI_DEVICE_ERROR - The region could not be opened because l= ocked by + chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Open ( + IN EFI_SMM_ACCESS2_PROTOCOL *This + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + UINT64 Address; + UINT8 SmramControl; + UINTN DescriptorIndex; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + for (DescriptorIndex =3D 0; DescriptorIndex < SmmAccess->NumberRegions; = DescriptorIndex++) { + if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCK= ED) { + DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n")); + return EFI_DEVICE_ERROR; + } + } + + /// + /// BEGIN CHIPSET SPECIFIC CODE + /// + /// + /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit) + /// + Address =3D PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAM= C); + + SmramControl =3D PciRead8 (Address); + /// + /// Is SMRAM locked? + /// + for (DescriptorIndex =3D 0; DescriptorIndex < SmmAccess->NumberRegions; = DescriptorIndex++) { + if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) !=3D 0) { + /// + /// Cannot Open a locked region + /// + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D EFI_SMRAM_LOC= KED; + DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n")); + return EFI_DEVICE_ERROR; + } + } + /// + /// Open SMRAM region + /// + SmramControl |=3D B_SA_SMRAMC_D_OPEN_MASK; + SmramControl &=3D ~(B_SA_SMRAMC_D_CLS_MASK); + + PciWrite8 (Address, SmramControl); + /// + /// END CHIPSET SPECIFIC CODE + /// + for (DescriptorIndex =3D 0; DescriptorIndex < SmmAccess->NumberRegions; = DescriptorIndex++) { + SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D (UINT64) ~(EFI_= SMRAM_CLOSED | EFI_ALLOCATED); + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (UINT64) EFI_SM= RAM_OPEN; + } + SmmAccess->SmmAccess.OpenState =3D TRUE; + return EFI_SUCCESS; +} + +/** + This routine accepts a request to "close" a region of SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "close" means that the memory is only visible from SMM agents, + not from BS or RT code. + + @param[in] This - Pointer to the SMM Access Interface. + + @retval EFI_SUCCESS - The region was successfully closed. + @retval EFI_DEVICE_ERROR - The region could not be closed because l= ocked by chipset. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Close ( + IN EFI_SMM_ACCESS2_PROTOCOL *This + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + UINT64 Address; + UINT8 SmramControl; + BOOLEAN OpenState; + UINT8 Index; + UINTN DescriptorIndex; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + + for (DescriptorIndex =3D 0; DescriptorIndex < SmmAccess->NumberRegions; = DescriptorIndex++) { + if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_LOCK= ED) { + DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n")); + continue; + } + + /// + /// BEGIN CHIPSET SPECIFIC CODE + /// + /// + /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit) + /// + Address =3D PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMR= AMC); + + SmramControl =3D PciRead8 (Address); + /// + /// Is SMRAM locked? + /// + if ((SmramControl & B_SA_SMRAMC_D_LCK_MASK) !=3D 0) { + /// + /// Cannot Close a locked region + /// + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D EFI_SMRAM_LOC= KED; + DEBUG ((DEBUG_WARN, "Cannot close a locked SMRAM region\n")); + return EFI_DEVICE_ERROR; + } + /// + /// Close SMRAM region + /// + SmramControl &=3D ~(B_SA_SMRAMC_D_OPEN_MASK); + + PciWrite8 (Address, SmramControl); + /// + /// END CHIPSET SPECIFIC CODE + /// + SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D (UINT64) ~EFI_S= MRAM_OPEN; + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (UINT64) (EFI_S= MRAM_CLOSED | EFI_ALLOCATED); + } + + /// + /// Find out if any regions are still open + /// + OpenState =3D FALSE; + for (Index =3D 0; Index < mSmmAccess.NumberRegions; Index++) { + if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) =3D=3D = EFI_SMRAM_OPEN) { + OpenState =3D TRUE; + } + } + + SmmAccess->SmmAccess.OpenState =3D OpenState; + return EFI_SUCCESS; +} + +/** + This routine accepts a request to "lock" SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "lock" means that the memory can no longer be opened + to BS state.. + + @param[in] This - Pointer to the SMM Access Interface. + + @retval EFI_SUCCESS - The region was successfully locked. + @retval EFI_DEVICE_ERROR - The region could not be locked because a= t least + one range is still open. + @retval EFI_INVALID_PARAMETER - The descriptor index was out of bounds. +**/ +EFI_STATUS +EFIAPI +Lock ( + IN EFI_SMM_ACCESS2_PROTOCOL *This + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + UINT64 Address; + UINT8 SmramControl; + UINTN DescriptorIndex; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + + if (SmmAccess->SmmAccess.OpenState) { + DEBUG ((DEBUG_WARN, "Cannot lock SMRAM when SMRAM regions are still op= en\n")); + return EFI_DEVICE_ERROR; + } + for (DescriptorIndex =3D 0; DescriptorIndex < SmmAccess->NumberRegions; = DescriptorIndex++) { + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D EFI_SMRAM_LOCKE= D; + } + SmmAccess->SmmAccess.LockState =3D TRUE; + + /// + /// BEGIN CHIPSET SPECIFIC CODE + /// + /// + /// SMRAM register is PCI 0:0:0:88, SMRAMC (8 bit) + /// + Address =3D PCI_LIB_ADDRESS (SA_MC_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_SMRAM= C); + + SmramControl =3D PciRead8 (Address); + /// + /// Lock the SMRAM + /// + SmramControl |=3D B_SA_SMRAMC_D_LCK_MASK; + + PciWrite8 (Address, SmramControl); + /// + /// END CHIPSET SPECIFIC CODE + /// + return EFI_SUCCESS; +} + +/** + This routine services a user request to discover the SMRAM + capabilities of this platform. This will report the possible + ranges that are possible for SMRAM access, based upon the + memory controller capabilities. + + @param[in] This - Pointer to the SMRAM Access Interface. + @param[in] SmramMapSize - Pointer to the variable containing si= ze of the + buffer to contain the description inf= ormation. + @param[in] SmramMap - Buffer containing the data describing= the Smram + region descriptors. + + @retval EFI_BUFFER_TOO_SMALL - The user did not provide a sufficient bu= ffer. + @retval EFI_SUCCESS - The user provided a sufficiently-sized b= uffer. +**/ +EFI_STATUS +EFIAPI +GetCapabilities ( + IN CONST EFI_SMM_ACCESS2_PROTOCOL *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap + ) +{ + EFI_STATUS Status; + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + UINTN NecessaryBufferSize; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + + NecessaryBufferSize =3D SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DES= CRIPTOR); + + if (*SmramMapSize < NecessaryBufferSize) { + DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too small\n")); + Status =3D EFI_BUFFER_TOO_SMALL; + } else { + CopyMem (SmramMap, SmmAccess->SmramDesc, NecessaryBufferSize); + Status =3D EFI_SUCCESS; + } + + *SmramMapSize =3D NecessaryBufferSize; + + return Status; +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Dmar= /Dmar.aslc b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Dmar= /Dmar.aslc new file mode 100644 index 0000000000..c864a0ca8f --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Dmar/Dmar.a= slc @@ -0,0 +1,250 @@ +/** @file + This file describes the contents of the ACPI DMA address Remapping + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "Dmar.h" +#include + +EFI_ACPI_DMAR_TABLE DmarTable =3D { + // + // EFI_ACPI_DMAR_HEADER + // + { + // + // EFI_ACPI_DESCRIPTION_HEADER + // + { + EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE, + sizeof (EFI_ACPI_DMAR_TABLE), + EFI_ACPI_DMAR_TABLE_REVISION, + + // + // Checksum will be updated at runtime + // + 0x00, + + // + // It is expected that these values will be programmed at runtime + // + { 'I', 'N', 'T', 'E', 'L', ' ' }, + EFI_ACPI_DMAR_OEM_TABLE_ID, + 0x1, + EFI_ACPI_DMAR_OEM_CREATOR_ID, + 1 + }, + + // + // DMAR table specific entries below: + // + + // + // 39-bit addressing Host Address Width + // + 38, + + // + // Flags + // + 0, + + // + // Reserved fields + // + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } + }, + + // + // First DRHD structure, VT-d Engine #1 + // + { + // + // EFI_ACPI_DMAR_DRHD_HEADER + // + { + {0, // Type =3D 0 (DRHD) + sizeof (EFI_ACPI_DRHD_ENGINE1_STRUCT)}, // Length of structure + 0, // Flag - Do not include= all + 0, // Reserved fields + 0, // Segment + 0 // Base address of DMA-r= emapping hardware - Updated at boot time + }, + // + // Device Scopes + // + { + { + {1, // Type + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Segment number + 0, // Reserved + 0}, // Start bus number + {2, 0} // PCI path + } + } + }, + + // + //Third DRHD structure VT-d Engine# 3 + // + { + // + // EFI_ACPI_DMAR_DRHD_HEADER + // + { + {0, // Type =3D 0 (DRHD) + sizeof (EFI_ACPI_DRHD_ENGINE3_STRUCT)}, // Length of strucure. + 1, // Flag - Include all + 0, // Reserved + 0, // Segment Number + 0 // Base address of DMA-re= mapping hardware. + }, + { + // + // Device Scopes + // + { + {3, // Type=3DIO APIC + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 2, // Enumeration ID + V_P2SB_CFG_IBDF_BUS}, // Start bus number + {V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC} // PCI path + }, + // + // Device Scopes + // + { + {4, // Type=3DHPET + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enumeration ID + V_P2SB_CFG_HBDF_BUS}, // Start bus number + {V_P2SB_CFG_HBDF_DEV, V_P2SB_CFG_HBDF_FUNC} // PCI path + } + } + }, + //RMRR structure for USB devices. + { + // + // EFI_ACPI_DMAR_RMRR_HEADER + // + { + { + 0x1, // Type 1 - RMRR structure + sizeof(EFI_ACPI_RMRR_USB_STRUC) // Length + }, + { 0x00, 0x00 }, // Reserved + 0x0000, // Segment Num + 0x00000000000E0000, // RMRR Base address - Up= dated in runtime. + 0x00000000000EFFFF // RMRR Limit address - U= pdated in runtime. + }, + // + // Device Scopes + // + { + { + {1, // Type + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0}, // Start bus number + {20, 0} // PCI path + }, + { + {1, // Type + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0}, // Start bus number + {20, 1} // PCI path + } + } + }, + + //RMRR structure for IGD device. + { + // + // EFI_ACPI_DMAR_RMRR_HEADER + // + { + {1, // Type 1 - RMRR structure + sizeof (EFI_ACPI_RMRR_IGD_STRUC)}, // Length + {0x0000}, // Reserved + 0x0000, // Segment Num + 0x0000000000000000, // RMRR Base address - Upd= ated in runtime. + 0x0000000000000000 // RMRR Limit address - Up= dated in runtime. + }, + // + // Device Scopes + // + { + { + {1, // Type + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0}, // Start bus number + {2, 0} // PCI path + } + } + }, + + // RMRR structure for WiAMT DMA access. + // Keep this device in end of RMRR queue. + { + // + // EFI_ACPI_DMAR_RMRR_HEADER + // + { + {1, // Type 1 - RMRR structure + sizeof (EFI_ACPI_RMRR_CSME_STRUC)}, // Length + {0x0000}, // Reserved + 0x0000, // Segment Num + 0x0000000000000000, // RMRR Base address - Upd= ated in runtime. + 0x0000000000000000 // RMRR Limit address - Up= dated in runtime. + }, + // + // Device Scopes + // + { + { + {1, // Type + sizeof (EFI_ACPI_DEV_SCOPE_STRUCTURE), // Length + 0, // Reserved + 0, // Enum ID + 0}, // Start bus number + {22, 7} // PCI path + } + } + } +}; + +// +// Dummy function required for build tools +// +#if defined (__GNUC__) +VOID* +ReferenceAcpiTable ( + VOID + ) + +{ + // + // Reference the table being generated to prevent the optimizer from rem= oving the + // data structure from the exeutable + // + return (VOID*)&DmarTable; +} +#else +int +main ( + VOID + ) +{ + return 0; +} +#endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Host= Bus.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/HostBus= .asl new file mode 100644 index 0000000000..b431a77f05 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/HostBus.asl @@ -0,0 +1,794 @@ +/** @file + This file contains the SystemAgent PCI Configuration space + definition. + It defines various System Agent PCI Configuration Space registers + which will be used to dynamically produce all resources in the Host Bus. + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +External(M64B) +External(M64L) +External(M32B) +External(M32L) + +// +// Define various System Agent (SA) PCI Configuration Space +// registers which will be used to dynamically produce all +// resources in the Host Bus _CRS. +// +OperationRegion (HBUS, PCI_Config, 0x00, 0x100) +Field (HBUS, DWordAcc, NoLock, Preserve) +{ + Offset(0x40), // EPBAR (0:0:0:40) + EPEN, 1, // Enable + , 11, + EPBR, 20, // EPBAR [31:12] + + Offset(0x48), // MCHBAR (0:0:0:48) + MHEN, 1, // Enable + , 14, + MHBR, 17, // MCHBAR [31:15] + + Offset(0x50), // GGC (0:0:0:50) + GCLK, 1, // GGCLCK + + Offset(0x54), // DEVEN (0:0:0:54) + D0EN, 1, // DEV0 Enable + D1F2, 1, // DEV1 FUN2 Enable + D1F1, 1, // DEV1 FUN1 Enable + D1F0, 1, // DEV1 FUN0 Enable + + Offset(0x60), // PCIEXBAR (0:0:0:60) + PXEN, 1, // Enable + PXSZ, 2, // PCI Express Size + , 23, + PXBR, 6, // PCI Express BAR [31:26] + + Offset(0x68), // DMIBAR (0:0:0:68) + DIEN, 1, // Enable + , 11, + DIBR, 20, // DMIBAR [31:12] + + Offset(0x70), // MESEG_BASE (0:0:0:70) + , 20, + MEBR, 12, // MESEG_BASE [31:20] + + Offset(0x80), // PAM0 Register (0:0:0:80) + PMLK, 1, // PAM Lock bit. + , 3, + PM0H, 2, // PAM 0, High Nibble + , 2, + + Offset(0x81), // PAM1 Register (0:0:0:81) + PM1L, 2, // PAM1, Low Nibble + , 2, + PM1H, 2, // PAM1, High Nibble + , 2, + + Offset(0x82), // PAM2 Register (0:0:0:82) + PM2L, 2, // PAM2, Low Nibble + , 2, + PM2H, 2, // PAM2, High Nibble + , 2, + + Offset(0x83), // PAM3 Register (0:0:0:83) + PM3L, 2, // PAM3, Low Nibble + , 2, + PM3H, 2, // PAM3, High Nibble + , 2, + + Offset(0x84), // PAM4 Register (0:0:0:84) + PM4L, 2, // PAM4, Low Nibble + , 2, + PM4H, 2, // PAM4, High Nibble + , 2, + + Offset(0x85), // PAM5 Register (0:0:0:85) + PM5L, 2, // PAM5, Low Nibble + , 2, + PM5H, 2, // PAM5, High Nibble + , 2, + + Offset(0x86), // PAM6 Register (0:0:0:86) + PM6L, 2, // PAM6, Low Nibble + , 2, + PM6H, 2, // PAM6, High Nibble + , 2, + + Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8) + , 20, + TUUD, 19, // TOUUD [38:20] + + Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC) + , 20, + TLUD, 12, // TOLUD [31:20] + + Offset(0xC8), // ERRSTS register (0:0:0:C8) + , 7, + HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR +} +// +// Define a buffer that will store all the bus, memory, and IO information +// relating to the Host Bus. This buffer will be dynamically altered in +// the _CRS and passed back to the OS. +// +Name(BUF0,ResourceTemplate() +{ + // + // Bus Number Allocation: Bus 0 to 0xFF + // + WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00, + 0x0000,0x00FF,0x00,0x0100,,,PB00) + + // + // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 ) + // + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00) + + // + // PCI Configuration Registers ( 0x0CF8 - 0x0CFF ) + // + Io(Decode16,0x0CF8,0x0CF8,1,0x08) + + // + // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF ) + // + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01) + + // + // Video Buffer Area ( 0xA0000 - 0xBFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000) + + // + // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000) + + // + // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400) + + // + // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800) + + // + // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00) + + // + // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000) + + // + // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400) + + // + // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800) + + // + // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00) + + // + // BIOS Extension Area ( 0xE0000 - 0xE3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000) + + // + // BIOS Extension Area ( 0xE4000 - 0xE7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400) + + // + // BIOS Extension Area ( 0xE8000 - 0xEBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800) + + // + // BIOS Extension Area ( 0xEC000 - 0xEFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00) + + // + // BIOS Area ( 0xF0000 - 0xFFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000) + +// // +// // Memory Hole Region ( 0xF00000 - 0xFFFFFF ) +// // +// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, +// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE) + + // + // PCI Memory Region ( TOLUD - 0xDFFFFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, + ReadWrite,0x00,0x00000000,0xDFFFFFFF,0x00,0xE0000000,,,PM01) + + // + // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) ) + // (This is dummy range for OS compatibility, will patch it in _CRS) + // + QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, + ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02) + + // + // PCH reserved resources ( 0xFC800000 - 0xFE7FFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, + ReadWrite,0x00,0xFC800000,0xFE7FFFFF,0x00,0x2000000,,,PM03) +}) + + // + // SA reserved resources + // + Device(SRRE) { + Name(_HID,EISAID("PNP0C02")) // motherboard resource + Name(_UID,"SARESV") + Method(_STA,0,Serialized) // device present and decodes its resources,= but not to be displayed in OSPM + { + If(LGreaterEqual(TLUD, 0x404)) { + Return (3) + } Else { + Return (0) + } + } + + Method(_CRS,0,Serialized) + { + Name(BUF0,ResourceTemplate(){ + // + // Reserve the 0x40000000 ~ 0x403FFFFF to prevent other driver use= this memory range + // + Memory32Fixed(ReadOnly,0x40000000,0x400000) + }) + If(LGreaterEqual(TLUD, 0x404)) { + Return (BUF0) + } Else { + Return (Buffer(){}) + } + } + } + +Name(EP_B, 0) // to store EP BAR +Name(MH_B, 0) // to store MCH BAR +Name(PC_B, 0) // to store PCIe BAR +Name(PC_L, 0) // to store PCIe BAR Length +Name(DM_B, 0) // to store DMI BAR + +// +// Get EP BAR +// +Method(GEPB,0,Serialized) +{ + if(LEqual(EP_B,0)) + { + ShiftLeft(\_SB.PCI0.EPBR,12,EP_B) + } + Return(EP_B) +} + +// +// Get MCH BAR +// +Method(GMHB,0,Serialized) +{ + if(LEqual(MH_B,0)) + { + ShiftLeft(\_SB.PCI0.MHBR,15,MH_B) + } + Return(MH_B) +} + +// +// Get PCIe BAR +// +Method(GPCB,0,Serialized) +{ + if(LEqual(PC_B,0)) + { + ShiftLeft(\_SB.PCI0.PXBR,26,PC_B) + } + Return(PC_B) +} + +// +// Get PCIe Length +// +Method(GPCL,0,Serialized) +{ + if(LEqual(PC_L,0)) { + ShiftRight(0x10000000, \_SB.PCI0.PXSZ,PC_L) + } + Return(PC_L) +} + +// +// Get DMI BAR +// +Method(GDMB,0,Serialized) +{ + if(LEqual(DM_B,0)) + { + ShiftLeft(\_SB.PCI0.DIBR,12,DM_B) + } + Return(DM_B) +} + + +Method(_CRS,0,Serialized) +{ + // + // Fix up Max Bus Number and Length + // + Store(\_SB.PCI0.GPCL(),Local0) + CreateWordField(BUF0, ^PB00._MAX, PBMX) + Store(Subtract(ShiftRight(Local0,20),2), PBMX) + CreateWordField(BUF0, ^PB00._LEN, PBLN) + Store(Subtract(ShiftRight(Local0,20),1), PBLN) + // + // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF. + // + If(PM1L) // \_SB.PCI0 + { + // PAMx !=3D 0. Set length =3D 0. + + CreateDwordField(BUF0, ^C000._LEN,C0LN) + Store(Zero,C0LN) + } + + If(LEqual(PM1L,1)) + { + CreateBitField(BUF0, ^C000._RW,C0RW) + Store(Zero,C0RW) + } + + If(PM1H) + { + CreateDwordField(BUF0, ^C400._LEN,C4LN) + Store(Zero,C4LN) + } + + If(LEqual(PM1H,1)) + { + CreateBitField(BUF0, ^C400._RW,C4RW) + Store(Zero,C4RW) + } + + If(PM2L) + { + CreateDwordField(BUF0, ^C800._LEN,C8LN) + Store(Zero,C8LN) + } + + If(LEqual(PM2L,1)) + { + CreateBitField(BUF0, ^C800._RW,C8RW) + Store(Zero,C8RW) + } + + If(PM2H) + { + CreateDwordField(BUF0, ^CC00._LEN,CCLN) + Store(Zero,CCLN) + } + + If(LEqual(PM2H,1)) + { + CreateBitField(BUF0, ^CC00._RW,CCRW) + Store(Zero,CCRW) + } + + If(PM3L) + { + CreateDwordField(BUF0, ^D000._LEN,D0LN) + Store(Zero,D0LN) + } + + If(LEqual(PM3L,1)) + { + CreateBitField(BUF0, ^D000._RW,D0RW) + Store(Zero,D0RW) + } + + If(PM3H) + { + CreateDwordField(BUF0, ^D400._LEN,D4LN) + Store(Zero,D4LN) + } + + If(LEqual(PM3H,1)) + { + CreateBitField(BUF0, ^D400._RW,D4RW) + Store(Zero,D4RW) + } + + If(PM4L) + { + CreateDwordField(BUF0, ^D800._LEN,D8LN) + Store(Zero,D8LN) + } + + If(LEqual(PM4L,1)) + { + CreateBitField(BUF0, ^D800._RW,D8RW) + Store(Zero,D8RW) + } + + If(PM4H) + { + CreateDwordField(BUF0, ^DC00._LEN,DCLN) + Store(Zero,DCLN) + } + + If(LEqual(PM4H,1)) + { + CreateBitField(BUF0, ^DC00._RW,DCRW) + Store(Zero,DCRW) + } + + If(PM5L) + { + CreateDwordField(BUF0, ^E000._LEN,E0LN) + Store(Zero,E0LN) + } + + If(LEqual(PM5L,1)) + { + CreateBitField(BUF0, ^E000._RW,E0RW) + Store(Zero,E0RW) + } + + If(PM5H) + { + CreateDwordField(BUF0, ^E400._LEN,E4LN) + Store(Zero,E4LN) + } + + If(LEqual(PM5H,1)) + { + CreateBitField(BUF0, ^E400._RW,E4RW) + Store(Zero,E4RW) + } + + If(PM6L) + { + CreateDwordField(BUF0, ^E800._LEN,E8LN) + Store(Zero,E8LN) + } + + If(LEqual(PM6L,1)) + { + CreateBitField(BUF0, ^E800._RW,E8RW) + Store(Zero,E8RW) + } + + If(PM6H) + { + CreateDwordField(BUF0, ^EC00._LEN,ECLN) + Store(Zero,ECLN) + } + + If(LEqual(PM6H,1)) + { + CreateBitField(BUF0, ^EC00._RW,ECRW) + Store(Zero,ECRW) + } + + If(PM0H) + { + CreateDwordField(BUF0, ^F000._LEN,F0LN) + Store(Zero,F0LN) + } + + If(LEqual(PM0H,1)) + { + CreateBitField(BUF0, ^F000._RW,F0RW) + Store(Zero,F0RW) + } + + // Enable the 1MB region between 15-16MB if HENA =3D 1. + // + // If( MCHC.HENA) + // { + // CreateDwordField(BUF0, HOLE._LEN,H0LN) + // Store(0x100000,H0LN) + // } + + // + // Create pointers to Memory Sizing values. + // + CreateDwordField(BUF0, ^PM01._MIN,M1MN) + CreateDwordField(BUF0, ^PM01._MAX,M1MX) + CreateDwordField(BUF0, ^PM01._LEN,M1LN) + + // + // Set Memory Size Values. TLUD represents bits 31:20 of phyical + // TOM, so shift these bits into the correct position and fix up + // the Memory Region available to PCI. + // + Store (M32L, M1LN) + Store (M32B, M1MN) + Subtract (Add (M1MN, M1LN), 1, M1MX) + + // + // Create pointers to Memory Sizing values. + // Patch PM02 range basing on memory size and OS type + // + If (LEqual(M64L, 0)) { + CreateQwordField(BUF0, ^PM02._LEN,MSLN) + // + // Set resource length to 0 + // + Store (0, MSLN) + } + Else { + CreateQwordField(BUF0, ^PM02._LEN,M2LN) + CreateQwordField(BUF0, ^PM02._MIN,M2MN) + CreateQwordField(BUF0, ^PM02._MAX,M2MX) + // + // Set 64bit MMIO resource Base and Length + // + Store (M64L, M2LN) + Store (M64B, M2MN) + Subtract (Add (M2MN, M2LN), 1, M2MX) + } + Return(BUF0) +} + +// +//Name(GUID,UUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) +// +Name(GUID,Buffer(){0x5b, 0x4d, 0xdb, 0x33, + 0xf7, 0x1f, + 0x1c, 0x40, + 0x96, 0x57, + 0x74, 0x41, 0xc0, 0x3d, 0xd7, 0x66}) + + +Name(SUPP,0) // PCI _OSC Support Field value +Name(CTRL,0) // PCI _OSC Control Field value +Name(XCNT, 0) // Variable used in _OSC for counting + +Method(_OSC,4,Serialized) +{ + // + // Check for proper UUID + // Save the capabilities buffer + // + Store(Arg3,Local0) + + // + // Create DWord-adressable fields from the Capabilties Buffer + // + CreateDWordField(Local0,0,CDW1) + CreateDWordField(Local0,4,CDW2) + CreateDWordField(Local0,8,CDW3) + + + // + // Check for proper UUID + // + If(LEqual(Arg0,GUID)) + { + // Save Capabilities DWord2 & 3 + Store(CDW2,SUPP) + Store(CDW3,CTRL) + + // + // You can clear bits in CTRL here if you don't want OS to take + // control + // + If(LNot(NEXP)) + { + And(CTRL, 0xFFFFFFF8, CTRL) // disable Native hot plug, PME + } + + If(LEqual(TBTS, 1)) { + // \_OSC disallow only Advanced Error Reporting control + And(CTRL, 0xFFFFFFF7, CTRL) + } + + If(Not(And(CDW1,1))) // Query flag clear? + { // Disable GPEs for features granted native control. + If(And(CTRL,0x01)) + { + NHPG() + } + If(And(CTRL,0x04)) // PME control granted? + { + NPME() + } + } + + If(LNotEqual(Arg1,One)) + { + // + // Unknown revision + // + Or(CDW1,0x08,CDW1) + } + + If(LNotEqual(CDW3,CTRL)) + { + // + // Capabilities bits were masked + // + Or(CDW1,0x10,CDW1) + } + // + // Update DWORD3 in the buffer + // + Store(CTRL,CDW3) + Store(CTRL,OSCC) + Return(Local0) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Local0) + } +} // End _OSC + +// +// Added code for Dual IRQ support. Two set of ACPI IRQ tables were genera= ted. +// Code has been added to select the appropriate IRQ table by checking the= CPUID. +// +Scope(\_SB.PCI0) +{ + Method(AR00) { + Return(\_SB.AR00) + } + + Method(PD00) { + Return(\_SB.PD00) + } + + Method(AR02) { + Return(\_SB.AR02) + } + + Method(PD02) { + Return(\_SB.PD02) + } + + Method(AR04) { + Return(\_SB.AR04) + } + + Method(PD04) { + Return(\_SB.PD04) + } + + Method(AR05) { + Return(\_SB.AR05) + } + + Method(PD05) { + Return(\_SB.PD05) + } + + Method(AR06) { + Return(\_SB.AR06) + } + + Method(PD06) { + Return(\_SB.PD06) + } + + Method(AR07) { + Return(\_SB.AR07) + } + + Method(PD07) { + Return(\_SB.PD07) + } + + Method(AR08) { + Return(\_SB.AR08) + } + + Method(PD08) { + Return(\_SB.PD08) + } + + Method(AR09) { + Return(\_SB.AR09) + } + + Method(PD09) { + Return(\_SB.PD09) + } + + Method(AR0A) { + Return(\_SB.AR0A) + } + + Method(PD0A) { + Return(\_SB.PD0A) + } + + Method(AR0B) { + Return(\_SB.AR0B) + } + + Method(PD0B) { + Return(\_SB.PD0B) + } + + // + // Add device scope definition for System Agent + // P.E.G. Root Port D1F0 + // + Device(PEG0) { + Name(_ADR, 0x00010000) + Device(PEGP) { // P.E.G. Port Slot x16 + Name(_ADR, 0x00000000) + } + } + // + // P.E.G. Root Port D1F1 + // + Device(PEG1) { + Name(_ADR, 0x00010001) + Device(PEGP) { // P.E.G. Port Slot x8 + Name(_ADR, 0x00000000) + } + } + // + // P.E.G. Root Port D1F2 + // + Device(PEG2) { + Name(_ADR, 0x00010002) + Device(PEGP) { // P.E.G. Port Slot x4 + Name(_ADR, 0x00000000) + } + } + // + // I.G.D + // + Device(GFX0) { + Name(_ADR, 0x00020000) + } + // + // SA Thermal Device + // + Device(B0D4) { + Method(_DSM,4,serialized){if(PCIC(Arg0)) { return(PCID(Arg0,Arg1,Arg2,= Arg3)) }; Return(Buffer() {0})} + Name(_ADR, 0x00040000) + } + // + // Device IPU0 is the IPU PCI device + // + Device(IPU0) { + Name(_ADR, 0x00050000) + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/Igfx.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaS= sdt/Igfx.asl new file mode 100644 index 0000000000..e7a797c973 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx= .asl @@ -0,0 +1,1666 @@ +/** @file + This file contains the IGD OpRegion/Software ACPI Reference + Code. + It defines the methods to enable/disable output switching, + store display switching and LCD brightness BIOS control + and return valid addresses for all display device encoders + present in the system, etc. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +External(\ECST, MethodObj) +External(\PBCL, MethodObj) +External(HDOS, MethodObj) +External(\ECON, IntObj) +External(\PNHM, IntObj) +External(OSYS, IntObj) +External(CPSC) +External(\GUAM, MethodObj) +External(DSEN) +External(S0ID) + +Name(TMP1,Package() {0xFFFFFFFF}) +Name(TMP2,Package() {0xFFFFFFFF, 0xFFFFFFFF}) +Name(TMP3,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) +Name(TMP4,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) +Name(TMP5,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF}) +Name(TMP6,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF}) +Name(TMP7,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) +Name(TMP8,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF}) +Name(TMP9,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF}) +Name(TMPA,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF }) +Name(TMPB,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) +Name(TMPC,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF}) +Name(TMPD,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF}) +Name(TMPE,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF}) +Name(TMPF,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF}) +Name(TMPG,Package() {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFF= FFFFF, 0xFFFFFFFF, 0xFFFFFFFF, + 0xFFFFFFFF, 0xFFFFFFFF}) + +// Enable/Disable Output Switching. In WIN2K/WINXP, _DOS =3D 0 will +// get called during initialization to prepare for an ACPI Display +// Switch Event. During an ACPI Display Switch, the OS will call +// _DOS =3D 2 immediately after a Notify=3D0x80 to temporarily disable +// all Display Switching. After ACPI Display Switching is complete, +// the OS will call _DOS =3D 0 to re-enable ACPI Display Switching. +Method(_DOS,1) +{ + // + // Store Display Switching and LCD brightness BIOS control bit + // + Store(And(Arg0,7),DSEN) + + If(LEqual(And(Arg0, 0x3), 0)) // If _DOS[1:0]=3D0 + { + If(CondRefOf(HDOS)) + { + HDOS() + } + } +} + +// +// Enumerate the Display Environment. This method will return +// valid addresses for all display device encoders present in the +// system. The Miniport Driver will reject the addresses for every +// encoder that does not have an attached display device. After +// enumeration is complete, the OS will call the _DGS methods +// during a display switch only for the addresses accepted by the +// Miniport Driver. For hot-insertion and removal of display +// devices, a re-enumeration notification will be required so the +// address of the newly present display device will be accepted by +// the Miniport Driver. +// +Method(_DOD,0) +{ + If (LEqual(IPTP,1)) { + // + // Increment number of devices if IPU is enabled + // + Store(1, NDID) + } Else { + Store(0, NDID) + } + + If(LNotEqual(DIDL, Zero)) + { + Store(SDDL(DIDL),DID1) + } + If(LNotEqual(DDL2, Zero)) + { + Store(SDDL(DDL2),DID2) + } + If(LNotEqual(DDL3, Zero)) + { + Store(SDDL(DDL3),DID3) + } + If(LNotEqual(DDL4, Zero)) + { + Store(SDDL(DDL4),DID4) + } + If(LNotEqual(DDL5, Zero)) + { + Store(SDDL(DDL5),DID5) + } + If(LNotEqual(DDL6, Zero)) + { + Store(SDDL(DDL6),DID6) + } + If(LNotEqual(DDL7, Zero)) + { + Store(SDDL(DDL7),DID7) + } + If(LNotEqual(DDL8, Zero)) + { + Store(SDDL(DDL8),DID8) + } + If(LNotEqual(DDL9, Zero)) + { + Store(SDDL(DDL9),DID9) + } + If(LNotEqual(DD10, Zero)) + { + Store(SDDL(DD10),DIDA) + } + If(LNotEqual(DD11, Zero)) + { + Store(SDDL(DD11),DIDB) + } + If(LNotEqual(DD12, Zero)) + { + Store(SDDL(DD12),DIDC) + } + If(LNotEqual(DD13, Zero)) + { + Store(SDDL(DD13),DIDD) + } + If(LNotEqual(DD14, Zero)) + { + Store(SDDL(DD14),DIDE) + } + If(LNotEqual(DD15, Zero)) + { + Store(SDDL(DD15),DIDF) + } + + // + // Enumerate the encoders. Note that for + // current silicon, the maximum number of encoders + // possible is 15. + // + If(LEqual(NDID,1)) + { + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP1,0)) + } Else { + Store(Or(0x10000,DID1),Index(TMP1,0)) + } + Return(TMP1) + } + + If(LEqual(NDID,2)) + { + Store(Or(0x10000,DID1),Index(TMP2,0)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP2,1)) + } Else { + Store(Or(0x10000,DID2),Index(TMP2,1)) + } + Return(TMP2) + } + + If(LEqual(NDID,3)) + { + Store(Or(0x10000,DID1),Index(TMP3,0)) + Store(Or(0x10000,DID2),Index(TMP3,1)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP3,2)) + } Else { + Store(Or(0x10000,DID3),Index(TMP3,2)) + } + Return(TMP3) + } + + If(LEqual(NDID,4)) + { + Store(Or(0x10000,DID1),Index(TMP4,0)) + Store(Or(0x10000,DID2),Index(TMP4,1)) + Store(Or(0x10000,DID3),Index(TMP4,2)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP4,3)) + } Else { + Store(Or(0x10000,DID4),Index(TMP4,3)) + } + Return(TMP4) + } + + If(LEqual(NDID,5)) + { + Store(Or(0x10000,DID1),Index(TMP5,0)) + Store(Or(0x10000,DID2),Index(TMP5,1)) + Store(Or(0x10000,DID3),Index(TMP5,2)) + Store(Or(0x10000,DID4),Index(TMP5,3)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP5,4)) + } Else { + Store(Or(0x10000,DID5),Index(TMP5,4)) + } + Return(TMP5) + } + + If(LEqual(NDID,6)) + { + Store(Or(0x10000,DID1),Index(TMP6,0)) + Store(Or(0x10000,DID2),Index(TMP6,1)) + Store(Or(0x10000,DID3),Index(TMP6,2)) + Store(Or(0x10000,DID4),Index(TMP6,3)) + Store(Or(0x10000,DID5),Index(TMP6,4)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP6,5)) + } Else { + Store(Or(0x10000,DID6),Index(TMP6,5)) + } + Return(TMP6) + } + + If(LEqual(NDID,7)) + { + Store(Or(0x10000,DID1),Index(TMP7,0)) + Store(Or(0x10000,DID2),Index(TMP7,1)) + Store(Or(0x10000,DID3),Index(TMP7,2)) + Store(Or(0x10000,DID4),Index(TMP7,3)) + Store(Or(0x10000,DID5),Index(TMP7,4)) + Store(Or(0x10000,DID6),Index(TMP7,5)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP7,6)) + } Else { + Store(Or(0x10000,DID7),Index(TMP7,6)) + } + Return(TMP7) + } + + If(LEqual(NDID,8)) + { + Store(Or(0x10000,DID1),Index(TMP8,0)) + Store(Or(0x10000,DID2),Index(TMP8,1)) + Store(Or(0x10000,DID3),Index(TMP8,2)) + Store(Or(0x10000,DID4),Index(TMP8,3)) + Store(Or(0x10000,DID5),Index(TMP8,4)) + Store(Or(0x10000,DID6),Index(TMP8,5)) + Store(Or(0x10000,DID7),Index(TMP8,6)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP8,7)) + } Else { + Store(Or(0x10000,DID8),Index(TMP8,7)) + } + Return(TMP8) + } + + If(LEqual(NDID,9)) + { + Store(Or(0x10000,DID1),Index(TMP9,0)) + Store(Or(0x10000,DID2),Index(TMP9,1)) + Store(Or(0x10000,DID3),Index(TMP9,2)) + Store(Or(0x10000,DID4),Index(TMP9,3)) + Store(Or(0x10000,DID5),Index(TMP9,4)) + Store(Or(0x10000,DID6),Index(TMP9,5)) + Store(Or(0x10000,DID7),Index(TMP9,6)) + Store(Or(0x10000,DID8),Index(TMP9,7)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMP9,8)) + } Else { + Store(Or(0x10000,DID9),Index(TMP9,8)) + } + Return(TMP9) + } + + If(LEqual(NDID,0x0A)) + { + Store(Or(0x10000,DID1),Index(TMPA,0)) + Store(Or(0x10000,DID2),Index(TMPA,1)) + Store(Or(0x10000,DID3),Index(TMPA,2)) + Store(Or(0x10000,DID4),Index(TMPA,3)) + Store(Or(0x10000,DID5),Index(TMPA,4)) + Store(Or(0x10000,DID6),Index(TMPA,5)) + Store(Or(0x10000,DID7),Index(TMPA,6)) + Store(Or(0x10000,DID8),Index(TMPA,7)) + Store(Or(0x10000,DID9),Index(TMPA,8)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMPA,9)) + } Else { + Store(Or(0x10000,DIDA),Index(TMPA,9)) + } + Return(TMPA) + } + + If(LEqual(NDID,0x0B)) + { + Store(Or(0x10000,DID1),Index(TMPB,0)) + Store(Or(0x10000,DID2),Index(TMPB,1)) + Store(Or(0x10000,DID3),Index(TMPB,2)) + Store(Or(0x10000,DID4),Index(TMPB,3)) + Store(Or(0x10000,DID5),Index(TMPB,4)) + Store(Or(0x10000,DID6),Index(TMPB,5)) + Store(Or(0x10000,DID7),Index(TMPB,6)) + Store(Or(0x10000,DID8),Index(TMPB,7)) + Store(Or(0x10000,DID9),Index(TMPB,8)) + Store(Or(0x10000,DIDA),Index(TMPB,9)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMPB,10)) + } Else { + Store(Or(0x10000,DIDB),Index(TMPB,10)) + } + Return(TMPB) + } + + If(LEqual(NDID,0x0C)) + { + Store(Or(0x10000,DID1),Index(TMPC,0)) + Store(Or(0x10000,DID2),Index(TMPC,1)) + Store(Or(0x10000,DID3),Index(TMPC,2)) + Store(Or(0x10000,DID4),Index(TMPC,3)) + Store(Or(0x10000,DID5),Index(TMPC,4)) + Store(Or(0x10000,DID6),Index(TMPC,5)) + Store(Or(0x10000,DID7),Index(TMPC,6)) + Store(Or(0x10000,DID8),Index(TMPC,7)) + Store(Or(0x10000,DID9),Index(TMPC,8)) + Store(Or(0x10000,DIDA),Index(TMPC,9)) + Store(Or(0x10000,DIDB),Index(TMPC,10)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMPC,11)) + } Else { + Store(Or(0x10000,DIDC),Index(TMPC,11)) + } + Return(TMPC) + } + + If(LEqual(NDID,0x0D)) + { + Store(Or(0x10000,DID1),Index(TMPD,0)) + Store(Or(0x10000,DID2),Index(TMPD,1)) + Store(Or(0x10000,DID3),Index(TMPD,2)) + Store(Or(0x10000,DID4),Index(TMPD,3)) + Store(Or(0x10000,DID5),Index(TMPD,4)) + Store(Or(0x10000,DID6),Index(TMPD,5)) + Store(Or(0x10000,DID7),Index(TMPD,6)) + Store(Or(0x10000,DID8),Index(TMPD,7)) + Store(Or(0x10000,DID9),Index(TMPD,8)) + Store(Or(0x10000,DIDA),Index(TMPD,9)) + Store(Or(0x10000,DIDB),Index(TMPD,10)) + Store(Or(0x10000,DIDC),Index(TMPD,11)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMPD,12)) + } Else { + Store(Or(0x10000,DIDD),Index(TMPD,12)) + } + Return(TMPD) + } + + If(LEqual(NDID,0x0E)) + { + Store(Or(0x10000,DID1),Index(TMPE,0)) + Store(Or(0x10000,DID2),Index(TMPE,1)) + Store(Or(0x10000,DID3),Index(TMPE,2)) + Store(Or(0x10000,DID4),Index(TMPE,3)) + Store(Or(0x10000,DID5),Index(TMPE,4)) + Store(Or(0x10000,DID6),Index(TMPE,5)) + Store(Or(0x10000,DID7),Index(TMPE,6)) + Store(Or(0x10000,DID8),Index(TMPE,7)) + Store(Or(0x10000,DID9),Index(TMPE,8)) + Store(Or(0x10000,DIDA),Index(TMPE,9)) + Store(Or(0x10000,DIDB),Index(TMPE,10)) + Store(Or(0x10000,DIDC),Index(TMPE,11)) + Store(Or(0x10000,DIDD),Index(TMPE,12)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMPE,13)) + } Else { + Store(Or(0x10000,DIDE),Index(TMPE,13)) + } + Return(TMPE) + } + + If(LEqual(NDID,0x0F)) + { + Store(Or(0x10000,DID1),Index(TMPF,0)) + Store(Or(0x10000,DID2),Index(TMPF,1)) + Store(Or(0x10000,DID3),Index(TMPF,2)) + Store(Or(0x10000,DID4),Index(TMPF,3)) + Store(Or(0x10000,DID5),Index(TMPF,4)) + Store(Or(0x10000,DID6),Index(TMPF,5)) + Store(Or(0x10000,DID7),Index(TMPF,6)) + Store(Or(0x10000,DID8),Index(TMPF,7)) + Store(Or(0x10000,DID9),Index(TMPF,8)) + Store(Or(0x10000,DIDA),Index(TMPF,9)) + Store(Or(0x10000,DIDB),Index(TMPF,10)) + Store(Or(0x10000,DIDC),Index(TMPF,11)) + Store(Or(0x10000,DIDD),Index(TMPF,12)) + Store(Or(0x10000,DIDE),Index(TMPF,13)) + If (LEqual(IPTP,1)) { + // + // IGFX need report IPUA as GFX0 child + // + Store(0x00023480,Index(TMPF,14)) + } Else { + Store(Or(0x10000,DIDF),Index(TMPF,14)) + } + Return(TMPF) + } + + If(LEqual(NDID,0x10)) + { + Store(Or(0x10000,DID1),Index(TMPG,0)) + Store(Or(0x10000,DID2),Index(TMPG,1)) + Store(Or(0x10000,DID3),Index(TMPG,2)) + Store(Or(0x10000,DID4),Index(TMPG,3)) + Store(Or(0x10000,DID5),Index(TMPG,4)) + Store(Or(0x10000,DID6),Index(TMPG,5)) + Store(Or(0x10000,DID7),Index(TMPG,6)) + Store(Or(0x10000,DID8),Index(TMPG,7)) + Store(Or(0x10000,DID9),Index(TMPG,8)) + Store(Or(0x10000,DIDA),Index(TMPG,9)) + Store(Or(0x10000,DIDB),Index(TMPG,10)) + Store(Or(0x10000,DIDC),Index(TMPG,11)) + Store(Or(0x10000,DIDD),Index(TMPG,12)) + Store(Or(0x10000,DIDE),Index(TMPG,13)) + Store(Or(0x10000,DIDF),Index(TMPG,14)) + // + // IGFX need report IPUA as GFX0 child + // NDID can only be 0x10 if IPU is enabled + // + Store(0x00023480,Index(TMPG,15)) + Return(TMPG) + } + + // + // If nothing else, return Unknown LFP. + // (Prevents compiler warning.) + // + Return(Package() {0x00000400}) +} + +Device(DD01) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID1),0x400)) + { + Store(0x1, EDPV) + Store(NXD1, NXDX) + Store(DID1, DIDX) + Return(1) + } + If(LEqual(DID1,0)) + { + Return(1) + } + Else + { + Return(And(0xFFFF,DID1)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + Return(CDDS(DID1)) + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD1) + } + Return(NDDS(DID1)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD02) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID2),0x400)) + { + Store(0x2, EDPV) + Store(NXD2, NXDX) + Store(DID2, DIDX) + Return(2) + } + If(LEqual(DID2,0)) + { + Return(2) + } + Else + { + Return(And(0xFFFF,DID2)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(LIDS,0)) + { + Return(0x0) + } + Return(CDDS(DID2)) + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + // + // Return the Next State. + // + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD2) + } + Return(NDDS(DID2)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD03) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID3),0x400)) + { + Store(0x3, EDPV) + Store(NXD3, NXDX) + Store(DID3, DIDX) + Return(3) + } + If(LEqual(DID3,0)) + { + Return(3) + } + Else + { + Return(And(0xFFFF,DID3)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DID3,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID3)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD3) + } + Return(NDDS(DID3)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD04) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID4),0x400)) + { + Store(0x4, EDPV) + Store(NXD4, NXDX) + Store(DID4, DIDX) + Return(4) + } + If(LEqual(DID4,0)) + { + Return(4) + } + Else + { + Return(And(0xFFFF,DID4)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DID4,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID4)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD4) + } + Return(NDDS(DID4)) + } + + // + // Device Set State. (See table above.) + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD05) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID5),0x400)) + { + Store(0x5, EDPV) + Store(NXD5, NXDX) + Store(DID5, DIDX) + Return(5) + } + If(LEqual(DID5,0)) + { + Return(5) + } + Else + { + Return(And(0xFFFF,DID5)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DID5,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID5)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD5) + } + Return(NDDS(DID5)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD06) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID6),0x400)) + { + Store(0x6, EDPV) + Store(NXD6, NXDX) + Store(DID6, DIDX) + Return(6) + } + If(LEqual(DID6,0)) + { + Return(6) + } + Else + { + Return(And(0xFFFF,DID6)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DID6,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID6)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD6) + } + Return(NDDS(DID6)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD07) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID7),0x400)) + { + Store(0x7, EDPV) + Store(NXD7, NXDX) + Store(DID7, DIDX) + Return(7) + } + If(LEqual(DID7,0)) + { + Return(7) + } + Else + { + Return(And(0xFFFF,DID7)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DID7,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID7)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD7) + } + Return(NDDS(DID7)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD08) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID8),0x400)) + { + Store(0x8, EDPV) + Store(NXD8, NXDX) + Store(DID8, DIDX) + Return(8) + } + If(LEqual(DID8,0)) + { + Return(8) + } + Else + { + Return(And(0xFFFF,DID8)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DID8,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID8)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DID8)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD09) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DID9),0x400)) + { + Store(0x9, EDPV) + Store(NXD8, NXDX) + Store(DID9, DIDX) + Return(9) + } + If(LEqual(DID9,0)) + { + Return(9) + } + Else + { + Return(And(0xFFFF,DID9)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DID9,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DID9)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DID9)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD0A) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDA),0x400)) + { + Store(0xA, EDPV) + Store(NXD8, NXDX) + Store(DIDA, DIDX) + Return(0x0A) + } + If(LEqual(DIDA,0)) + { + Return(0x0A) + } + Else + { + Return(And(0xFFFF,DIDA)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DIDA,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DIDA)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDA)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD0B) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDB),0x400)) + { + Store(0xB, EDPV) + Store(NXD8, NXDX) + Store(DIDB, DIDX) + Return(0X0B) + } + If(LEqual(DIDB,0)) + { + Return(0x0B) + } + Else + { + Return(And(0xFFFF,DIDB)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DIDB,0)) + { + Return(0x0B) + } + Else + { + Return(CDDS(DIDB)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDB)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD0C) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDC),0x400)) + { + Store(0xC, EDPV) + Store(NXD8, NXDX) + Store(DIDC, DIDX) + Return(0X0C) + } + If(LEqual(DIDC,0)) + { + Return(0x0C) + } + Else + { + Return(And(0xFFFF,DIDC)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DIDC,0)) + { + Return(0x0C) + } + Else + { + Return(CDDS(DIDC)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDC)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD0D) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDD),0x400)) + { + Store(0xD, EDPV) + Store(NXD8, NXDX) + Store(DIDD, DIDX) + Return(0X0D) + } + If(LEqual(DIDD,0)) + { + Return(0x0D) + } + Else + { + Return(And(0xFFFF,DIDD)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DIDD,0)) + { + Return(0x0D) + } + Else + { + Return(CDDS(DIDD)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDD)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD0E) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDE),0x400)) + { + Store(0xE, EDPV) + Store(NXD8, NXDX) + Store(DIDE, DIDX) + Return(0X0E) + } + If(LEqual(DIDE,0)) + { + Return(0x0E) + } + Else + { + Return(And(0xFFFF,DIDE)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DIDE,0)) + { + Return(0x0E) + } + Else + { + Return(CDDS(DIDE)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDE)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +Device(DD0F) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(And(0x0F00,DIDF),0x400)) + { + Store(0xF, EDPV) + Store(NXD8, NXDX) + Store(DIDF, DIDX) + Return(0X0F) + } + If(LEqual(DIDF,0)) + { + Return(0x0F) + } + Else + { + Return(And(0xFFFF,DIDF)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(DIDC,0)) + { + Return(0x0F) + } + Else + { + Return(CDDS(DIDF)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXD8) + } + Return(NDDS(DIDF)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } +} + +// +//Device for eDP +// +Device(DD1F) +{ + // + // Return Unique ID. + // + Method(_ADR,0,Serialized) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x1F) + } + Else + { + Return(And(0xFFFF,DIDX)) + } + } + + // + // Return the Current Status. + // + Method(_DCS,0) + { + If(LEqual(EDPV, 0x0)) + { + Return(0x00) + } + Else + { + Return(CDDS(DIDX)) + } + } + + // + // Query Graphics State (active or inactive). + // + Method(_DGS,0) + { + If(LAnd(LEqual(And(SGMD,0x7F),0x01),CondRefOf(SNXD))) + { + Return (NXDX) + } + Return(NDDS(DIDX)) + } + + // + // Device Set State. + // + Method(_DSS,1) + { + DSST(Arg0) + } + + // + // Query List of Brightness Control Levels Supported. + // + Method(_BCL,0) + { + // + // List of supported brightness levels in the following sequence. + // Level when machine has full power. + // Level when machine is on batteries. + // Other supported levels. + // + If(CondRefOf(\PBCL)) { + Return (PBCL()) + } Else { + Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1= 3, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, = 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,= 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69= , 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 8= 8, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100}) + } + } + + // + // Set the Brightness Level. + // + Method (_BCM,1) + { + // + // Set the requested level if it is between 0 and 100%. + // + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100))) + { + \_SB.PCI0.GFX0.AINT(1, Arg0) + Store(Arg0,BRTL) // Store Brightness Level. + } + } + + // + // Brightness Query Current level. + // + Method (_BQC,0) + { + Return(BRTL) + } +} + +Method(SDDL,1) +{ + Increment(NDID) + Store(And(Arg0,0xF0F),Local0) + Or(0x80000000,Local0, Local1) + If(LEqual(DIDL,Local0)) + { + Return(Local1) + } + If(LEqual(DDL2,Local0)) + { + Return(Local1) + } + If(LEqual(DDL3,Local0)) + { + Return(Local1) + } + If(LEqual(DDL4,Local0)) + { + Return(Local1) + } + If(LEqual(DDL5,Local0)) + { + Return(Local1) + } + If(LEqual(DDL6,Local0)) + { + Return(Local1) + } + If(LEqual(DDL7,Local0)) + { + Return(Local1) + } + If(LEqual(DDL8,Local0)) + { + Return(Local1) + } + If(LEqual(DDL9,Local0)) + { + Return(Local1) + } + If(LEqual(DD10,Local0)) + { + Return(Local1) + } + If(LEqual(DD11,Local0)) + { + Return(Local1) + } + If(LEqual(DD12,Local0)) + { + Return(Local1) + } + If(LEqual(DD13,Local0)) + { + Return(Local1) + } + If(LEqual(DD14,Local0)) + { + Return(Local1) + } + If(LEqual(DD15,Local0)) + { + Return(Local1) + } + Return(0) +} + +Method(CDDS,1) +{ + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0x1D) + } + If(LEqual(CADL, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL2, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL3, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL4, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL5, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL6, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL7, Local0)) + { + Return(0x1F) + } + If(LEqual(CAL8, Local0)) + { + Return(0x1F) + } + Return(0x1D) +} + +Method(NDDS,1) +{ + Store(And(Arg0,0xF0F),Local0) + + If(LEqual(0, Local0)) + { + Return(0) + } + If(LEqual(NADL, Local0)) + { + Return(1) + } + If(LEqual(NDL2, Local0)) + { + Return(1) + } + If(LEqual(NDL3, Local0)) + { + Return(1) + } + If(LEqual(NDL4, Local0)) + { + Return(1) + } + If(LEqual(NDL5, Local0)) + { + Return(1) + } + If(LEqual(NDL6, Local0)) + { + Return(1) + } + If(LEqual(NDL7, Local0)) + { + Return(1) + } + If(LEqual(NDL8, Local0)) + { + Return(1) + } + Return(0) +} + +// +// Device Set State Table +// BIT31 BIT30 Execution +// 0 0 Don't implement. +// 0 1 Cache change. Nothing to Implement. +// 1 0 Don't Implement. +// 1 1 Display Switch Complete. Implement. +// +Method(DSST,1) +{ + If(LEqual(And(Arg0,0xC0000000),0xC0000000)) + { + // + // State change was performed by the + // Video Drivers. Simply update the + // New State. + // + Store(NSTE,CSTE) + } +} + +// +// Include IGD OpRegion/Software SCI interrupt handler/DSM which is used by +// the graphics drivers to request data from system BIOS. +// +include ("IgfxOpRn.asl") +include ("IgfxDsm.asl") diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/IgfxCommon.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTabl= es/SaSsdt/IgfxCommon.asl new file mode 100644 index 0000000000..7edbe45e2e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx= Common.asl @@ -0,0 +1,472 @@ +/** @file + IGD OpRegion/Software SCI Reference Code. + This file contains ASL code with the purpose of handling events + i.e. hotkeys and other system interrupts. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +/************************************************************************; +;* ACPI Notification Methods +;************************************************************************/ + + +/************************************************************************; +;* +;* Name: PDRD +;* +;* Description: Check if the graphics driver is ready to process +;* notifications and video extensions. +;* +;* Usage: This method is to be called prior to performing any +;* notifications or handling video extensions. +;* Ex: If (PDRD()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: DRDY (Driver ready status), ASLP (Driver recommended +;* sleep timeout value). +;* +;************************************************************************/ + +External(HNOT, MethodObj) + +Method(PDRD) +{ + // + // If DRDY is clear, the driver is not ready. If the return value is + // !=3D0, do not perform any notifications or video extension handling. + // + Return(LNot(DRDY)) +} + +/************************************************************************; +;* +;* Name: PSTS +;* +;* Description: Check if the graphics driver has completed the previous +;* "notify" command. +;* +;* Usage: This method is called before every "notify" command. A +;* "notify" should only be set if the driver has completed the +;* previous command. Else, ignore the event and exit the par= ent +;* method. +;* Ex: If (PSTS()) {Return (FAIL)} +;* +;* Input: None +;* +;* Output: None +;* +;* References: CSTS (Notification status), ASLP (Driver recommended sleep +;* timeout value). +;* +;************************************************************************/ + +Method(PSTS) +{ + If(LGreater(CSTS, 2)) + { + // + // Sleep for ASLP milliseconds if the status is not "success, + // failure, or pending" + // + Sleep(ASLP) + } + + Return(LEqual(CSTS, 3)) // Return True if still Dispatched +} + +/************************************************************************; +;* +;* Name: GNOT +;* +;* Description: Call the appropriate methods to query the graphics driver +;* status. If all methods return success, do a notification = of +;* the graphics device. +;* +;* Usage: This method is to be called when a graphics device +;* notification is required (display switch hotkey, etc). +;* +;* Input: Arg0 =3D Current event type: +;* 1 =3D display switch +;* 2 =3D lid +;* 3 =3D dock +;* Arg1 =3D Notification type: +;* 0 =3D Re-enumeration +;* 0x80 =3D Display switch +;* +;* Output: Returns 0 =3D success, 1 =3D failure +;* +;* References: PDRD and PSTS methods. OSYS (OS version) +;* +;************************************************************************/ + +Method(GNOT, 2) +{ + // + // Check for 1. Driver loaded, 2. Driver ready. + // If any of these cases is not met, skip this event and return failure. + // + If(PDRD()) + { + Return(0x1) // Return failure if driver not loaded. + } + + Store(Arg0, CEVT) // Set up the current event value + Store(3, CSTS) // CSTS=3DBIOS dispatched an event + + If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver s= upports hotplug + { + // + // Re-enumerate the Graphics Device for non-XP operating systems. + // + Notify(\_SB.PCI0.GFX0, Arg1) + } + + If(CondRefOf(HNOT)) + { + HNOT(Arg0) //Notification handler for Switchable graphics + } + Else + { + Notify(\_SB.PCI0.GFX0,0x80) + } + + Return(0x0) // Return success +} + +/************************************************************************; +;* +;* Name: GHDS +;* +;* Description: Handle a hotkey display switching event (performs a +;* Notify(GFX0, 0). +;* +;* Usage: This method must be called when a hotkey event occurs and = the +;* purpose of that hotkey is to do a display switch. +;* +;* Input: Arg0 =3D Toggle table number. +;* +;* Output: Returns 0 =3D success, 1 =3D failure. +;* CEVT and TIDX are indirect outputs. +;* +;* References: TIDX, GNOT +;* +;************************************************************************/ + +Method(GHDS, 1) +{ + Store(Arg0, TIDX) // Store the table number + // + // Call GNOT for CEVT =3D 1 =3D hotkey, notify value =3D 0 + // + Return(GNOT(1, 0)) // Return stats from GNOT +} + +/************************************************************************; +;* +;* Name: GLID +;* +;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not = the +;* lid notify). +;* +;* Usage: This method must be called when a lid event occurs. A +;* Notify(LID0, 0x80) must follow the call to this method. +;* +;* Input: Arg0 =3D Lid state: +;* 0 =3D All closed +;* 1 =3D internal LFP lid open +;* 2 =3D external lid open +;* 3 =3D both external and internal open +;* +;* Output: Returns 0=3Dsuccess, 1=3Dfailure. +;* CLID and CEVT are indirect outputs. +;* +;* References: CLID, GNOT +;* +;************************************************************************/ + +Method(GLID, 1) +{ + + If (LEqual(Arg0,1)) + { + Store(3,CLID) + } + Else + { + Store(Arg0, CLID) + } + // + //Store(Arg0, CLID) // Store the current lid state + // Call GNOT for CEVT=3D2=3DLid, notify value =3D 0 + // + if (GNOT(2, 0)) { + Or (CLID, 0x80000000, CLID) + Return (1) // Return Fail + } + + Return (0) // Return Pass +} + +/************************************************************************; +;* +;* Name: GDCK +;* +;* Description: Handle a docking event by updating the current docking sta= tus +;* and doing a notification. +;* +;* Usage: This method must be called when a docking event occurs. +;* +;* Input: Arg0 =3D Docking state: +;* 0 =3D Undocked +;* 1 =3D Docked +;* +;* Output: Returns 0=3Dsuccess, 1=3Dfailure. +;* CDCK and CEVT are indirect outputs. +;* +;* References: CDCK, GNOT +;* +;************************************************************************/ + +Method(GDCK, 1) +{ + Store(Arg0, CDCK) // Store the current dock state + // + // Call GNOT for CEVT=3D4=3DDock, notify value =3D 0 + // + Return(GNOT(4, 0)) // Return stats from GNOT +} + +/************************************************************************; +;* ASLE Interrupt Methods +;************************************************************************/ + +/************************************************************************; +;* +;* Name: PARD +;* +;* Description: Check if the driver is ready to handle ASLE interrupts +;* generate by the system BIOS. +;* +;* Usage: This method must be called before generating each ASLE +;* interrupt. +;* +;* Input: None +;* +;* Output: Returns 0 =3D success, 1 =3D failure. +;* +;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep +;* timeout value) +;* +;************************************************************************/ + +Method(PARD) +{ + If(LNot(ARDY)) + { + // + // Sleep for ASLP milliseconds if the driver is not ready. + // + Sleep(ASLP) + } + // + // If ARDY is clear, the driver is not ready. If the return value is + // !=3D0, do not generate the ASLE interrupt. + // + Return(LNot(ARDY)) +} + +// +// Intel Ultrabook Event Handler. Arg0 represents the Ultrabook Event Bit= # to pass +// to the Intel Graphics Driver. Note that this is a serialized method, m= eaning +// sumultaneous events are not allowed. +// +Method(IUEH,1,Serialized) +{ + And(IUER,0xC0,IUER) // Clear all button events on entry. + XOr(IUER,Shiftleft(1,Arg0),IUER) // Toggle status. + + If(LLessEqual(Arg0,4)) // Button Event? + { + Return(AINT(5,0)) // Generate event and return status. + + } + Else // Indicator Event. + { + Return(AINT(Arg0,0)) // Generate event and return status. + } +} + +/************************************************************************; +;* +;* Name: AINT +;* +;* Description: Call the appropriate methods to generate an ASLE interrupt. +;* This process includes ensuring the graphics driver is ready +;* to process the interrupt, ensuring the driver supports the +;* interrupt of interest, and passing information about the e= vent +;* to the graphics driver. +;* +;* Usage: This method must called to generate an ASLE interrupt. +;* +;* Input: Arg0 =3D ASLE command function code: +;* 0 =3D Set ALS illuminance +;* 1 =3D Set backlight brightness +;* 2 =3D Do Panel Fitting +;* 4 =3D Reserved +;* 5 =3D Button Indicator Event +;* 6 =3D Convertible Indicator Event +;* 7 =3D Docking Indicator Event +;* Arg1 =3D If Arg0 =3D 0, current ALS reading: +;* 0 =3D Reading below sensor range +;* 1-0xFFFE =3D Current sensor reading +;* 0xFFFF =3D Reading above sensor range +;* Arg1 =3D If Arg0 =3D 1, requested backlight percentage +;* +;* Output: Returns 0 =3D success, 1 =3D failure +;* +;* References: PARD method. +;* +;************************************************************************/ + +Method(AINT, 2) +{ + // + // Return failure if the requested feature is not supported by the + // driver. + // + If(LNot(And(TCHE, ShiftLeft(1, Arg0)))) + { + Return(0x1) + } + // + // Return failure if the driver is not ready to handle an ASLE + // interrupt. + // + If(PARD()) + { + Return(0x1) + } + // + // Handle Intel Ultrabook Events. + // + If(LAnd(LGreaterEqual(Arg0,5),LLessEqual(Arg0,7))) + { + Store(ShiftLeft(1,Arg0), ASLC) // Set Ultrbook Event [6:4]. + Store(0x01, ASLE) // Generate ASLE interrupt + + Store(0,Local2) // Use Local2 as a timeout counter. Intialize to zero. + + While(LAnd(LLess(Local2,250),LNotEqual(ASLC,0))) // Wait 1 second or u= ntil Driver ACKs a success. + { + Sleep(4) // Delay 4 ms. + Increment(Local2) // Increment Timeout. + } + + Return(0) // Return success + } + // + // Evaluate the first argument (Panel fitting, backlight brightness, or = ALS). + // + If(LEqual(Arg0, 2)) // Arg0 =3D 2, so request a panel fitting mo= de change. + { + If(CPFM) // If current mode field is non-zero use it. + { + And(CPFM, 0x0F, Local0) // Create variables without reserved + And(EPFM, 0x0F, Local1) // or valid bits. + + If(LEqual(Local0, 1)) // If current mode is centered, + { + If(And(Local1, 6)) // and if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Otherwise, + { + If(And(Local1, 8)) // if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Only centered mode is enabled + { + Store(1, PFIT) // so request centered. (No change.) + } + } + } + If(LEqual(Local0, 6)) // If current mode is stretched, + { + If(And(Local1, 8)) // and if aspect ratio is enabled, + { + Store(8, PFIT) // request aspect ratio. + } + Else // Otherwise, + { + If(And(Local1, 1)) // if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Only stretched mode is enabled + { + Store(6, PFIT) // so request stretched. (No change.) + } + } + } + If(LEqual(Local0, 8)) // If current mode is aspect ratio, + { + If(And(Local1, 1)) // and if centered is enabled, + { + Store(1, PFIT) // request centered. + } + Else // Otherwise, + { + If(And(Local1, 6)) // if stretched is enabled, + { + Store(6, PFIT) // request stretched. + } + Else // Only aspect ratio mode is enabled + { + Store(8, PFIT) // so request aspect ratio. (No change.) + } + } + } + } + // + // The following code for panel fitting (within the Else condition) is= retained for backward compatiblity. + // + Else // If CFPM field is zero use PFIT and toggle= the + { + Xor(PFIT,7,PFIT) // mode setting between stretched and center= ed only. + } + Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases. + Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 1)) // Arg0=3D1, so set the backlight brightness. + { + Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percen= t to 0-255. + Or(BCLP, 0x80000000, BCLP) // Set the valid bit. + Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1] + } + Else + { + If(LEqual(Arg0, 0)) // Arg0=3D0, so set the ALS illuminace + { + Store(Arg1, ALSI) + Store(1, ASLC) // Store "ALS event" to ASLC[31:1] + } + Else + { + Return(0x1) // Unsupported function + } + } + } + + Store(0x01, ASLE) // Generate ASLE interrupt + Return(0x0) // Return success +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/IgfxDsm.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/= SaSsdt/IgfxDsm.asl new file mode 100644 index 0000000000..e7b3c92cda --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx= Dsm.asl @@ -0,0 +1,369 @@ +/** @file + IGD OpRegion/_DSM Reference Code. + This file contains Get BIOS Data and Callback functions for + the Integrated Graphics Device (IGD) OpRegion/DSM mechanism + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// _DSM Device Specific Method +// +// Arg0: UUID Unique function identifier +// Arg1: Integer Revision Level +// Arg2: Integer Function Index (1 =3D Return Supported Functions) +// Arg3: Additional Inputs/Package Parameters Bits [31:0] input as {Byte0,= Byte1, Byte2, Byte3} to BIOS which is passed as 32 bit DWORD by Driver +// +Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgO= bj}) { + + If (LEqual(Arg0, ToUUID ("3E5B41C6-EB1D-4260-9D15-C71FBADAE414"))) { + // + // _DSM Definition for Igd functions + // Arguments: + // Arg0: UUID: 3E5B41C6-EB1D-4260-9D15-C71FBADAE414 + // Arg1: Revision ID: 1 + // Arg2: Function Index: 16 + // Arg3: Additional Inputs Bits[31:0] Arg3 {Byte0, Byte1, Byte2, Byte3} + // + // Return: + // Success for simple notification, Opregion update for some routines = and a Package for AKSV + // + // + // Switch by function index + // + Switch(ToInteger(Arg2)) { + // + // Function Index: 0 + // Standard query - A bitmask of functions supported + // + // Return: A bitmask of functions supported + // + Case (0) + { + If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 + Store("iGfx Supported Functions Bitmap ", Debug) + Return (0x1E7FF) // bit 11 and 12 is not supported + } + } + + // + // Function Index: 1 + // Adapter Power State Notification + // Arg3 Bits [7:0]: Adapter Power State bits [7:0] from Driver 00h = =3D D0; 01h =3D D1; 02h =3D D2; 04h =3D D3 (Cold/Hot); 08h =3D D4 (Hibernat= e Notification) + // Return: Success + // + Case(1) { + If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 + Store(" Adapter Power State Notification ", Debug) + + // + // Handle Low Power S0 Idle Capability if enabled + // + If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) { + // + // Call GUAM to trigger CS Entry + // If Adapter Power State Notification =3D D1 (Arg3[0]=3D0x0= 1) + // + If (LEqual (And(DerefOf (Index (Arg3,0)), 0xFF), 0x01)) { + // GUAM - Global User Absent Mode Notification Method + \GUAM(One) // 0x01 - Power State Standby (CS Entry) + } + Store(And(DerefOf (Index (Arg3,1)), 0xFF), Local0) + // + // Call GUAM + // If Display Turn ON Notification (Arg3 [1] =3D=3D 0) for CS = Exit + // + If (LEqual (Local0, 0)) { + // GUAM - Global User Absent Mode Notification Method + \GUAM(0) + } + } + + // Upon notification from driver that the Adapter Power State = =3D D0, + // check if previous lid event failed. If it did, retry the lid + // event here. + If(LEqual(DerefOf (Index (Arg3,0)), 0)) { + Store(CLID, Local0) + If(And(0x80000000,Local0)) { + And(CLID, 0x0000000F, CLID) + GLID(CLID) + } + } + Return(0x01) + } + } + // + // Function Index: 2 + // Display Power State Notification + // Arg3: Display Power State Bits [15:8] + // 00h =3D On + // 01h =3D Standby + // 02h =3D Suspend + // 04h =3D Off + // 08h =3D Reduced On + // Return: Success + // + Case(2) { + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 + + Store("Display Power State Notification ", Debug) + Return(0x01) + } + } + + // + // Function Index: 3 + // BIOS POST Completion Notification + // Return: Success + // + Case(3) { + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 + Store("BIOS POST Completion Notification ", Debug) + Return(0x01) // Not supported, but no failure + } + } + + // + // Function Index: 4 + // Pre-Hires Set Mode + // Return: Success + // + Case(4) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + Store("Pre-Hires Set Mode ", Debug) + Return(0x01) // Not supported, but no failure + } + } + + // + // Function Index: 5 + // Post-Hires Set Mode + // Return: Success + // + Case(5) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + Store("Post-Hires Set Mode ", Debug) + Return(0x01) // Not supported, but no failure + } + } + + // + // Function Index: 6 + // SetDisplayDeviceNotification (Display Switch) + // Return: Success + // + Case(6) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + Store("SetDisplayDeviceNotification", Debug) + Return(0x01) // Not supported, but no failure + } + } + + // + // Function Index: 7 + // SetBootDevicePreference + // Return: Success + // + Case(7) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + // An OEM may elect to implement this method. In that cas= e, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is I= ntel + // validated implementation. + + Store("SetBootDevicePreference ", Debug) + And(DerefOf (Index (Arg3,0)), 0xFF, IBTT) // Save the boot displ= ay to NVS + Return(0x01) + } + } + + // + // Function Index: 8 + // SetPanelPreference + // Return: Success + // + Case(8) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is I= ntel + // validated implementation. + + Store("SetPanelPreference ", Debug) + + // Set the panel-related NVRAM variables based the input from th= e driver. + And(DerefOf (Index (Arg3,0)), 0xFF, IPSC) + + // Change panel type if a change is requested by the driver (Cha= nge if + // panel type input is non-zero). Zero=3DNo change requested. + If(And(DerefOf (Index (Arg3,1)), 0xFF)) { + And(DerefOf (Index (Arg3,1)), 0xFF, IPAT) + Decrement(IPAT) // 0 =3D no change, so fit to CMOS map + } + And(ShiftRight(DerefOf (Index (Arg3,2)), 4), 0x7, IBIA) + Return(0x01) // Success + } + } + + // + // Function Index: 9 + // FullScreenDOS + // Return: Success + // + Case(9) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + Store("FullScreenDOS ", Debug) + Return(0x01) // Not supported, but no failure + } + } + + // + // Function Index: 10 + // APM Complete + // Return: Adjusted Lid State + // + Case(10) { + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 + + Store("APM Complete ", Debug) + Store(ShiftLeft(LIDS, 8), Local0) // Report the lid state + Add(Local0, 0x100, Local0) // Adjust the lid state, 0 =3D= Unknown + Return(Local0) + } + } + + // + // + // Function Index: 13 + // GetBootDisplayPreference + // Arg3 Bits [30:16] : Boot Device Ports + // Arg3 Bits [7:0] : Boot Device Type + // Return: Boot device port and Boot device type from saved configur= ation + // + Case(13) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + + Store("GetBootDisplayPreference ", Debug) + Or(ShiftLeft(DerefOf (Index (Arg3,3)), 24), ShiftLeft(DerefOf (I= ndex (Arg3,2)), 16), Local0) // Combine Arg3 Bits [31:16] + And(Local0, 0xEFFF0000, Local0) + And(Local0, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), Local0) + Or(IBTT, Local0, Local0) // Arg3 Bits [7:0] =3D Boot device type + Return(Local0) + } + } + + // + // Function Index: 14 + // GetPanelDetails + // Return: Different Panel Settings + // + Case(14) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + Store("GetPanelDetails ", Debug) + + // Report the scaling setting + // Bits [7:0] - Panel Scaling + // Bits contain the panel scaling user setting from CMOS + // 00h =3D On: Auto + // 01h =3D On: Force Scaling + // 02h =3D Off + // 03h =3D Maintain Aspect Ratio + + Store(IPSC, Local0) + Or(Local0, ShiftLeft(IPAT, 8), Local0) + + // Adjust panel type, 0 =3D VBT default + // Bits [15:8] - Panel Type + // Bits contain the panel type user setting from CMOS + // 00h =3D Not Valid, use default Panel Type & Timings from VBT + // 01h - 0Fh =3D Panel Number + + Add(Local0, 0x100, Local0) + + // Report the lid state and Adjust it + // Bits [16] - Lid State + // Bits contain the current panel lid state + // 0 =3D Lid Open + // 1 =3D Lid Closed + + Or(Local0, ShiftLeft(LIDS, 16), Local0) + Add(Local0, 0x10000, Local0) + + // Report the BIA setting + // Bits [22:20] - Backlight Image Adaptation (BIA) Control + // Bits contain the backlight image adaptation control user setti= ng from CMOS + // 000 =3D VBT Default + // 001 =3D BIA Disabled (BLC may still be enabled) + // 010 - 110 =3D BIA Enabled at Aggressiveness Level [1 - 5] + + Or(Local0, ShiftLeft(IBIA, 20), Local0) + Return(Local0) + } + } + + // + // Function Index: 15 + // GetInternalGraphics + // Return: Different Internal Grahics Settings + // + + Case(15) { + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1 + Store("GetInternalGraphics ", Debug) + + Store(GIVD, Local0) // Local0[0] - VGA m= ode(1=3DVGA) + Xor(Local0, 1, Local0) // Invert the VGA mode po= larity + + Or(Local0, ShiftLeft(GMFN, 1), Local0) // Local0[1] - # IGD= PCI functions-1 + // Local0[3:2] - Reser= ved + // Local0[4] - IGD D= 3 support(0=3Dcold) + // Local0[10:5] - Reser= ved + Or(Local0, ShiftLeft(3, 11), Local0) // Local0[12:11] - DVMT = version (11b =3D 5.0) + + // + // Report DVMT 5.0 Total Graphics memory size. + // + Or(Local0, ShiftLeft(IDMS, 17), Local0) // Bits 20:17 are for Gf= x total memory size + + // If the "Set Internal Graphics" call is supported, the modified + // settings flag must be programmed per the specification. This= means + // that the flag must be set to indicate that system BIOS reques= ts + // these settings. Once "Set Internal Graphics" is called, the + // modified settings flag must be cleared on all subsequent cal= ls to + // this function. + + // Report the graphics frequency based on B0:D2:F0:RF0h[12]. Mu= st + // take into account the current VCO. + + Or(ShiftLeft(DeRefOf(Index(DeRefOf(Index(CDCT, HVCO)), CDVL)), 2= 1),Local0, Local0) + Return(Local0) + } + } + + // + // Function Index: 16 + // GetAKSV + // Retrun: 5 bytes of AKSV + // + Case(16) { + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1 + + Store("GetAKSV ", Debug) + Name (KSVP, Package() + { + 0x80000000, + 0x8000 + }) + Store(KSV0, Index(KSVP,0)) // First four bytes of AKSV + Store(KSV1, Index(KSVP,1)) // Fifth byte of AKSV + Return(KSVP) // Success + } + } + } // End of switch(Arg2) + + } // End of if (ToUUID("3E5B41C6-EB1D-4260-9D15-C71FBADAE414D")) + + Return (Buffer () {0x00}) +} // End of _DSM diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/IgfxOpGbda.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTabl= es/SaSsdt/IgfxOpGbda.asl new file mode 100644 index 0000000000..26e560a358 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx= OpGbda.asl @@ -0,0 +1,129 @@ +/** @file + IGD OpRegion/Software SCI Reference Code. + This file contains Get BIOS Data Area funciton support for + the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +Method (GBDA, 0, Serialized) +{ + // + // Supported calls: Sub-function 0 + // + If (LEqual(GESF, 0)) + { + // + // Reference code is set to Intel's validated implementation. + // + Store(0x0000659, PARM) + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + // + // Requested callbacks: Sub-function 1 + // + If (LEqual(GESF, 1)) + { + // + // Call back functions are where the driver calls the + // system BIOS at function indicated event. + // + Store(0x300482, PARM) + If(LEqual(S0ID, One)){ + Or(PARM, 0x100, PARM) //Request Fn 8 callback in CS systems + } + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + // + // Get Boot display Preferences: Sub-function 4 + // + If (LEqual(GESF, 4)) + { + // + // Get Boot Display Preferences function. + // + And(PARM, 0xEFFF0000, PARM) // PARM[30:16] =3D Boot device ports + And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM) + Or(IBTT, PARM, PARM) // PARM[7:0] =3D Boot device type + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Success + } + // + // Panel details: Sub-function 5 + // + If (LEqual(GESF, 5)) + { + // + // Get Panel Details function. + // + Store(IPSC, PARM) // Report the scaling setting + Or(PARM, ShiftLeft(IPAT, 8), PARM) + Add(PARM, 0x100, PARM) // Adjust panel type, 0 =3D VBT default + Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state + Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 =3D Unknown + Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting + Store(Zero, GESF) + Return(SUCC) + } + // + // Internal graphics: Sub-function 7 + // + If (LEqual(GESF, 7)) + { + Store(GIVD, PARM) // PARM[0] - VGA mode(1=3DVGA) + Xor(PARM, 1, PARM) // Invert the VGA mode polarity + Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI functions-1 + // PARM[3:2] - Reserved + // PARM[4] - IGD D3 support(0= =3Dcold) + // PARM[10:5] - Reserved + Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b =3D 5.= 0) + + // + // Report DVMT 5.0 Total Graphics memory size. + // + Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total me= mory size + // + // If the "Set Internal Graphics" call is supported, the modified + // settings flag must be programmed per the specification. This means + // that the flag must be set to indicate that system BIOS requests + // these settings. Once "Set Internal Graphics" is called, the + // modified settings flag must be cleared on all subsequent calls to + // this function. + // Report the graphics frequency based on B0:D2:F0:RF0h[12]. Must + // take into account the current VCO. + // + Or(ShiftLeft(Derefof(Index(Derefof(Index(CDCT, HVCO)), CDVL)), 21),PAR= M, PARM) + Store(1, GESF) // Set the modified settings flag + Return(SUCC) + } + // + // Spread spectrum clocks: Sub-function 10 + // + If (LEqual(GESF, 10)) + { + Store(0, PARM) // Assume SSC is disabled + If(ISSC) + { + Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled + } + Store(0, GESF) // Set the modified settings flag + Return(SUCC) // Success + } + + If (LEqual(GESF, 11)) + { + Store(KSV0, PARM) // First four bytes of AKSV + Store(KSV1, GESF) // Fifth byte of AKSV + + Return(SUCC) // Success + } + // + // A call to a reserved "Get BIOS data" function was received. + // + Store(Zero, GESF) // Clear the exit parameter + Return(CRIT) // Reserved, "Critical failure" +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/IgfxOpRn.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables= /SaSsdt/IgfxOpRn.asl new file mode 100644 index 0000000000..a26cbdb00c --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx= OpRn.asl @@ -0,0 +1,296 @@ +/** @file + IGD OpRegion/Software SCI Reference Code. + This file contains the interrupt handler code for the Integrated + Graphics Device (IGD) OpRegion/Software SCI mechanism. + It defines OperationRegions to cover the IGD PCI configuration space + as described in the IGD OpRegion specification. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// Define an OperationRegion to cover the GMCH PCI configuration space as +// described in the IGD OpRegion specificiation. +// +Scope(\_SB.PCI0) +{ + OperationRegion(MCHP, PCI_Config, 0x40, 0xC0) + Field(MCHP, AnyAcc, NoLock, Preserve) + { + Offset(0x14), + AUDE, 8, + + Offset(0x60), // Top of Memory register + TASM, 10, // Total system memory (64MB gran) + , 6, + } +} + +// +// Define an OperationRegion to cover the IGD PCI configuration space as +// described in the IGD OpRegion specificiation. +// +OperationRegion(IGDP, PCI_Config, 0x40, 0xC0) +Field(IGDP, AnyAcc, NoLock, Preserve) +{ + Offset(0x10), // Mirror of gfx control reg + , 1, + GIVD, 1, // IGD VGA disable bit + , 2, + GUMA, 3, // Stolen memory size + , 9, + Offset(0x14), + , 4, + GMFN, 1, // Gfx function 1 enable + , 27, + Offset(0xA4), + ASLE, 8, // Reg 0xE4, ASLE interrupt register + , 24, // Only use first byte of ASLE reg + Offset(0xA8), // Reg 0xE8, SWSCI control register + GSSE, 1, // Graphics SCI event (1=3Devent pending) + GSSB, 14, // Graphics SCI scratchpad bits + GSES, 1, // Graphics event select (1=3DSCI) + Offset(0xB0), // Gfx Clk Frequency and Gating Control + , 12, + CDVL, 1, // Core display clock value + , 3, // Graphics Core Display Clock Select + Offset(0xB5), + LBPC, 8, // Legacy brightness control + Offset(0xBC), + ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion +} + +// +// Define an OperationRegion to cover the IGD OpRegion layout. +// +OperationRegion(IGDM, SystemMemory, ASLB, 0x2000) +Field(IGDM, AnyAcc, NoLock, Preserve) +{ + // + // OpRegion Header + // + SIGN, 128, // Signature-"IntelGraphicsMem" + SIZE, 32, // OpRegion Size + OVER, 32, // OpRegion Version + SVER, 256, // System BIOS Version + VVER, 128, // VBIOS Version + GVER, 128, // Driver version + MBOX, 32, // Mailboxes supported + DMOD, 32, // Driver Model + PCON, 32, // Platform Configuration + DVER, 64, // GOP Version + // + // OpRegion Mailbox 1 (Public ACPI Methods) + // Note: Mailbox 1 is normally reserved for desktop platforms. + // + Offset(0x100), + DRDY, 32, // Driver readiness (ACPI notification) + CSTS, 32, // Notification status + CEVT, 32, // Current event + Offset(0x120), + DIDL, 32, // Supported display device ID list + DDL2, 32, // Allows for 8 devices + DDL3, 32, + DDL4, 32, + DDL5, 32, + DDL6, 32, + DDL7, 32, + DDL8, 32, + CPDL, 32, // Currently present display list + CPL2, 32, // Allows for 8 devices + CPL3, 32, + CPL4, 32, + CPL5, 32, + CPL6, 32, + CPL7, 32, + CPL8, 32, + CADL, 32, // Currently active display list + CAL2, 32, // Allows for 8 devices + CAL3, 32, + CAL4, 32, + CAL5, 32, + CAL6, 32, + CAL7, 32, + CAL8, 32, + NADL, 32, // Next active display list + NDL2, 32, // Allows for 8 devices + NDL3, 32, + NDL4, 32, + NDL5, 32, + NDL6, 32, + NDL7, 32, + NDL8, 32, + ASLP, 32, // ASL sleep timeout + TIDX, 32, // Toggle table index + CHPD, 32, // Current hot plug enable indicator + CLID, 32, // Current lid state indicator + CDCK, 32, // Current docking state indicator + SXSW, 32, // Display switch notify on resume + EVTS, 32, // Events supported by ASL (diag only) + CNOT, 32, // Current OS notifications (diag only) + NRDY, 32, + // + //Extended DIDL list + // + DDL9, 32, + DD10, 32, + DD11, 32, + DD12, 32, + DD13, 32, + DD14, 32, + DD15, 32, + // + //Extended Currently attached Display Device List CPD2 + // + CPL9, 32, + CP10, 32, + CP11, 32, + CP12, 32, + CP13, 32, + CP14, 32, + CP15, 32, + // + // OpRegion Mailbox 2 (Software SCI Interface) + // + Offset(0x200), // SCIC + SCIE, 1, // SCI entry bit (1=3Dcall unserviced) + GEFC, 4, // Entry function code + GXFC, 3, // Exit result + GESF, 8, // Entry/exit sub-function/parameter + , 16, // SCIC[31:16] reserved + Offset(0x204), // PARM + PARM, 32, // PARM register (extra parameters) + DSLP, 32, // Driver sleep time out + // + // OpRegion Mailbox 3 (BIOS to Driver Notification) + // Note: Mailbox 3 is normally reserved for desktop platforms. + // + Offset(0x300), + ARDY, 32, // Driver readiness (power conservation) + ASLC, 32, // ASLE interrupt command/status + TCHE, 32, // Technology enabled indicator + ALSI, 32, // Current ALS illuminance reading + BCLP, 32, // Backlight brightness + PFIT, 32, // Panel fitting state or request + CBLV, 32, // Current brightness level + BCLM, 320, // Backlight brightness level duty cycle mapping table + CPFM, 32, // Current panel fitting mode + EPFM, 32, // Enabled panel fitting modes + PLUT, 592, // Optional. 74-byte Panel LUT Table + PFMB, 32, // Optional. PWM Frequency and Minimum Brightness + CCDV, 32, // Optional. Gamma, Brightness, Contrast values. + PCFT, 32, // Optional. Power Conservation Features + SROT, 32, // Supported rotation angle. + IUER, 32, // Optional. Intel Ultrabook Event Register. + FDSS, 64, // Optional. FFS Display Physical address + FDSP, 32, // Optional. FFS Display Size + STAT, 32, // State Indicator + // + // OpRegion Mailbox 4 (VBT) + // + Offset(0x400), + RVBT, 0xC000, // 6K bytes maximum VBT image + // + // OpRegion Mailbox 5 (BIOS to Driver Notification Extension) + // + Offset(0x1C00), + PHED, 32, // Panel Header + BDDC, 2048, // Panel EDID (Max 256 bytes) + +} + +// +// Convert boot display type into a port mask. +// +Name (DBTB, Package() +{ + 0x0000, // Automatic + 0x0007, // Port-0 : Integrated CRT + 0x0038, // Port-1 : DVO-A, or Integrated LVDS + 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C + 0x0E00, // Port-3 : SDVO-C + 0x003F, // [CRT + DVO-A / Integrated LVDS] + 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C] + 0x0E07, // [CRT + SDVO-C] + 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B] + 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C] + 0x0FC0, // [SDVO-B + SDVO-C] + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x0000, // Reserved + 0x7000, // Port-4: Integrated TV + 0x7007, // [Integrated TV + CRT] + 0x7038, // [Integrated TV + LVDS] + 0x71C0, // [Integrated TV + DVOB] + 0x7E00 // [Integrated TV + DVOC] +}) + +// +// Core display clock value table. +// +Name (CDCT, Package() +{ + Package() {228, 320}, + Package() {222, 333}, + Package() {222, 333}, + Package() { 0, 0}, + Package() {222, 333}, +}) + +// +// Defined exit result values: +// +Name (SUCC, 1) // Exit result: Success +Name (NVLD, 2) // Exit result: Invalid parameter +Name (CRIT, 4) // Exit result: Critical failure +Name (NCRT, 6) // Exit result: Non-critical failure + +/************************************************************************; +;* +;* Name: GSCI +;* +;* Description: Handles an SCI generated by the graphics driver. The +;* PARM and SCIC input fields are parsed to determine the +;* functionality requested by the driver. GBDA or SBCB +;* is called based on the input data in SCIC. +;* +;* Usage: The method must be called in response to a GPE 06 event +;* which will be generated by the graphics driver. +;* Ex: Method(\_GPE._L06) {Return(\_SB.PCI0.GFX0.GSCI())} +;* +;* Input: PARM and SCIC are indirect inputs +;* +;* Output: PARM and SIC are indirect outputs +;* +;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback +;* method) +;* +;************************************************************************/ + +Method (GSCI, 0, Serialized) +{ + Include("IgfxOpGbda.asl") // "Get BIOS Data" Functions + Include("IgfxOpSbcb.asl") // "System BIOS CallBacks" + + If (LEqual(GEFC, 4)) + { + Store(GBDA(), GXFC) // Process Get BIOS Data functions + } + + If (LEqual(GEFC, 6)) + { + Store(SBCB(), GXFC) // Process BIOS Callback functions + } + + Store(0, GEFC) // Wipe out the entry function code + Store(1, CPSC) // Clear CPUSCI_STS to clear the PCH TCO SCI st= atus + Store(0, GSSE) // Clear the SCI generation bit in PCI space. + Store(0, SCIE) // Clr SCI serviced bit to signal completion + + Return(Zero) +} + +Include("IgfxCommon.asl") // IGD SCI mobile features diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/IgfxOpSbcb.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTabl= es/SaSsdt/IgfxOpSbcb.asl new file mode 100644 index 0000000000..0167d922ff --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Igfx= OpSbcb.asl @@ -0,0 +1,262 @@ +/** @file + This file contains the system BIOS call back functionality for the + OpRegion/Software SCI mechanism. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +Method (SBCB, 0, Serialized) +{ + // + // Supported Callbacks: Sub-function 0 + // + If (LEqual(GESF, 0x0)) + { + // + // An OEM may support the driver->SBIOS status callbacks, but + // the supported callbacks value must be modified. The code that is + // executed upon reception of the callbacks must be also be updated + // to perform the desired functionality. + // + Store(0x00000000, PARM) // No callbacks supported + //Store(0x000787FD, PARM) // Used for Intel test implementaion + Store(0x000F87DD, PARM) + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // "Success" + } + // + // BIOS POST Completion: Sub-function 1 + // + If (LEqual(GESF, 1)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + // + // Pre-Hires Set Mode: Sub-function 3 + // + If (LEqual(GESF, 3)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + // + // Post-Hires Set Mode: Sub-function 4 + // + If (LEqual(GESF, 4)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + // + // Display Switch: Sub-function 5 + // + If (LEqual(GESF, 5)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + // + // Adapter Power State: Sub-function 7 + // + If (LEqual(GESF, 7)) + { + // + // Handle Low Power S0 Idle Capability if enabled + // + If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) { + // + // Call GUAM to trigger CS Entry + // If Adapter Power State Notification =3D D1 (PARM[7:0]=3D0x01) + // + If (LEqual (And(PARM,0xFF), 0x01)) { + // GUAM - Global User Absent Mode Notification Method + \GUAM(One) // 0x01 - Power State Standby (CS Entry) + } + If (LEqual (And(PARM,0xFF), 0x00)) { + // GUAM - Global User Absent Mode Notification Method + \GUAM(0) + } + } + // + // Upon notification from driver that the Adapter Power State =3D D0, + // check if previous lid event failed. If it did, retry the lid + // event here. + // + If(LEqual(PARM, 0)) + { + Store(CLID, Local0) + If(And(0x80000000,Local0)) + { + And(CLID, 0x0000000F, CLID) + GLID(CLID) + } + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + // + // Display Power State: Sub-function 8 + // + If (LEqual(GESF, 8)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + // + // Set Boot Display: Sub-function 9 + // + If (LEqual(GESF, 9)) + { + // + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + // + And(PARM, 0xFF, IBTT) // Save the boot display to NVS + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Reserved, "Critical failure" + } + // + // Set Panel Details: Sub-function 10 (0Ah) + // + If (LEqual(GESF, 10)) + { + // + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + // Set the panel-related NVRAM variables based the input from the driv= er. + // + And(PARM, 0xFF, IPSC) + // + // Change panel type if a change is requested by the driver (Change if + // panel type input is non-zero). Zero=3DNo change requested. + // + If(And(ShiftRight(PARM, 8), 0xFF)) + { + And(ShiftRight(PARM, 8), 0xFF, IPAT) + Decrement(IPAT) // 0 =3D no change, so fit to CMOS map + } + And(ShiftRight(PARM, 20), 0x7, IBIA) + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + // + // Set Internal Graphics: Sub-function 11 (0Bh) + // + If (LEqual(GESF, 11)) + { + // + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + // + And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 option + If(And(PARM, ShiftLeft(0xF, 13))) // Use fixed memory if fixed si= ze !=3D 0 + { + // + // Fixed memory + // + And(ShiftRight(PARM, 13), 0xF, IDMS) // Program fixed memory size + } + Else + { + // + // DVMT memory + // + And(ShiftRight(PARM, 17), 0xF, IDMS) // Program fixed memory size + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + // + // Post-Hires to DOS FS: Sub-function 16 (10h) + // + If (LEqual(GESF, 16)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + // + // APM Complete: Sub-function 17 (11h) + // + If (LEqual(GESF, 17)) + { + Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state + Add(PARM, 0x100, PARM) // Adjust the lid state, 0 =3D Unknown + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Not supported, but no failure + } + // + // Set Spread Spectrum Clocks: Sub-function 18 (12h) + // + If (LEqual(GESF, 18)) + { + // + // An OEM may elect to implement this method. In that case, + // the input values must be saved into non-volatile storage for + // parsing during the next boot. The following Sample code is Intel + // validated implementation. + // + If(And(PARM, 1)) + { + If(LEqual(ShiftRight(PARM, 1), 1)) + { + Store(1, ISSC) // Enable HW SSC, only for clock 1 + } + Else + { + Store(Zero, GESF) + Return(CRIT) // Failure, as the SSC clock must be 1 + } + } + Else + { + Store(0, ISSC) // Disable SSC + } + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + // + // Post VBE/PM Callback: Sub-function 19 (13h) + // + If (LEqual(GESF, 19)) + { + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Not supported, but no failure + } + // + // Set PAVP Data: Sub-function 20 (14h) + // + If (LEqual(GESF, 20)) + { + And(PARM, 0xF, PAVP) // Store PAVP info + Store(Zero, GESF) // Clear the exit parameter + Store(Zero, PARM) + Return(SUCC) // Success + } + + // + // A call to a reserved "System BIOS callbacks" function was received + // + Store(Zero, GESF) // Clear the exit parameter + Return(SUCC) // Reserved, "Critical failure" +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/Ipu.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/Ipu.asl new file mode 100644 index 0000000000..e4e47ddf1e --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Ipu.= asl @@ -0,0 +1,87 @@ +/** @file + This file contains the device definition of the System Agent + ACPI reference code. + Currently defines the device objects for the + System Agent IPU device + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// Device IPUA is the IPU AVStream virtual device and it appears under GFX0 +// +Scope (\_SB.PCI0.GFX0) +{ + Device(IPUA) // IPU AVStream virtual device name + { + /* + The identifier for this device (Same as in + _DOD above). This is required so GFX driver can + associate a matching device ID for the AVStream + driver and provide it to PnP (this device ID + should appear in the INF file of the AVStream + driver). + */ + Name(_ADR, 0x00003480) + /* + The following is a technique that may be used (per OEM needs) to pre= vent + the load of the camera device in one of the following cases: + - Camera device is fused out + - If the platform setup requires that in a secured boot the camera d= evice + should not be enabled + */ + Method (_STA, 0, NotSerialized) { + If(LEqual(IPTP,1)){ // IGFX need report IPU AVStream virtual device = as GFX0 child + Return (0xF) + } Else { // IGFX should NOT report IPU AVStream virtual device as GF= X0 child + Return (0x0) + } + } + } // End SKC0 +} // end I.G.D + +Scope(\_SB.PCI0.IPU0) +{ +//------------------------------------------------------------------------= ---------------- +// Intel Proprietary Passing LTR information from BIOS to IPU Driver. DSM= Method +// +// Method(_DSM, 0x4, Serialized, 0, {IntObj, BuffObj}, {BuffObj, IntObj, = IntObj, PkgObj}) +// Arguments: +// Arg0: GUID: "9A9E6AB4-E3FC-475D-AD1C-C4789E4CFE90" +// Arg1: Integer Revision Level (Current revision is 0) +// Arg2: Integer Function Index +// 0x1 - return UINT 32bit LTR values +// 0x2 - return UINT 32bit Fill Time +// +//------------------------------------------------------------------------= ----------------- +Method (_DSM, 4, NotSerialized) { // _DSM: Device-Specific Method + If (LEqual(Arg0, ToUUID("9A9E6AB4-E3FC-475D-AD1C-C4789E4CFE90"))) + { + // Function 0 : Query Function + If (LEqual(Arg2, 0)) + { + // Revision 0 + If (LEqual(Arg1, 0)) // The current revision is 0 + { + Return(Buffer() { 0x07 }) // There are 2 function defined other = than Query. + } Else { + Return(0) // Revision mismatch + } + } + // Function 1 : Return UINT 32bit LTR values + If(LEqual(Arg2, 1)) + { + Return(0x64503C19) + } + // Function 2 : Return UINT 32bit Fill Time + If(LEqual(Arg2, 2)) + { + Return(0xFFF0783C) + } + } + + Return(0) // Function number or GUID mismatch but normal return. + } +} diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/Sa.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsd= t/Sa.asl new file mode 100644 index 0000000000..4817968240 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.a= sl @@ -0,0 +1,31 @@ +/** @file + This file contains the device definition of the System Agent + ACPI reference code. + Currently defines the device objects for the + System Agent PCI Express* ports (PEG), iGfx and other devices. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +External(\_SB.PCI0, DeviceObj) +External(\_SB.PCI0.GFX0, DeviceObj) +External(\_SB.PCI0.IPU0, DeviceObj) +External(\_SB.PCI0.B0D3, DeviceObj) +External(\_SB.PCI0.PCIC, MethodObj) +External(\_SB.PCI0.PCID, MethodObj) + + +/// +/// I.G.D +/// +Scope (\_SB.PCI0.GFX0) +{ + include("Igfx.asl") +} // end I.G.D + +/// +/// IPU Device +/// +include("Ipu.asl") diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/SaNvs.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/Sa= Ssdt/SaNvs.asl new file mode 100644 index 0000000000..09d36ade53 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaNv= s.asl @@ -0,0 +1,147 @@ +/** @file + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // + // Define SA NVS Area operatino region. + // + + + + OperationRegion(SANV,SystemMemory, 0xFFFF0000,0xAA55) + Field(SANV,AnyAcc,Lock,Preserve) + { Offset(0), ASLB, 32, // Offset(0), IGD OpRegion base address + Offset(4), IMON, 8, // Offset(4), IMON Current Value + Offset(5), IGDS, 8, // Offset(5), IGD State (Primary Display = =3D 1) + Offset(6), IBTT, 8, // Offset(6), IGD Boot Display Device + Offset(7), IPAT, 8, // Offset(7), IGD Panel Type CMOS option + Offset(8), IPSC, 8, // Offset(8), IGD Panel Scaling + Offset(9), IBIA, 8, // Offset(9), IGD BIA Configuration + Offset(10), ISSC, 8, // Offset(10), IGD SSC Configuration + Offset(11), IDMS, 8, // Offset(11), IGD DVMT Memory Size + Offset(12), IF1E, 8, // Offset(12), IGD Function 1 Enable + Offset(13), HVCO, 8, // Offset(13), HPLL VCO + Offset(14), GSMI, 8, // Offset(14), GMCH SMI/SCI mode (0=3DSCI) + Offset(15), PAVP, 8, // Offset(15), IGD PAVP data + Offset(16), CADL, 8, // Offset(16), Current Attached Device List + Offset(17), CSTE, 16, // Offset(17), Current Display State + Offset(19), NSTE, 16, // Offset(19), Next Display State + Offset(21), NDID, 8, // Offset(21), Number of Valid Device IDs + Offset(22), DID1, 32, // Offset(22), Device ID 1 + Offset(26), DID2, 32, // Offset(26), Device ID 2 + Offset(30), DID3, 32, // Offset(30), Device ID 3 + Offset(34), DID4, 32, // Offset(34), Device ID 4 + Offset(38), DID5, 32, // Offset(38), Device ID 5 + Offset(42), DID6, 32, // Offset(42), Device ID 6 + Offset(46), DID7, 32, // Offset(46), Device ID 7 + Offset(50), DID8, 32, // Offset(50), Device ID 8 + Offset(54), DID9, 32, // Offset(54), Device ID 9 + Offset(58), DIDA, 32, // Offset(58), Device ID 10 + Offset(62), DIDB, 32, // Offset(62), Device ID 11 + Offset(66), DIDC, 32, // Offset(66), Device ID 12 + Offset(70), DIDD, 32, // Offset(70), Device ID 13 + Offset(74), DIDE, 32, // Offset(74), Device ID 14 + Offset(78), DIDF, 32, // Offset(78), Device ID 15 + Offset(82), DIDX, 32, // Offset(82), Device ID for eDP device + Offset(86), NXD1, 32, // Offset(86), Next state DID1 for _DGS + Offset(90), NXD2, 32, // Offset(90), Next state DID2 for _DGS + Offset(94), NXD3, 32, // Offset(94), Next state DID3 for _DGS + Offset(98), NXD4, 32, // Offset(98), Next state DID4 for _DGS + Offset(102), NXD5, 32, // Offset(102), Next state DID5 for _DGS + Offset(106), NXD6, 32, // Offset(106), Next state DID6 for _DGS + Offset(110), NXD7, 32, // Offset(110), Next state DID7 for _DGS + Offset(114), NXD8, 32, // Offset(114), Next state DID8 for _DGS + Offset(118), NXDX, 32, // Offset(118), Next state DID for eDP + Offset(122), LIDS, 8, // Offset(122), Lid State (Lid Open =3D 1) + Offset(123), KSV0, 32, // Offset(123), First four bytes of AKSV (ma= nufacturing mode) + Offset(127), KSV1, 8, // Offset(127), Fifth byte of AKSV (manufact= uring mode) + Offset(128), BRTL, 8, // Offset(128), Brightness Level Percentage + Offset(129), ALSE, 8, // Offset(129), Ambient Light Sensor Enable + Offset(130), ALAF, 8, // Offset(130), Ambient Light Adjusment Fact= or + Offset(131), LLOW, 8, // Offset(131), LUX Low Value + Offset(132), LHIH, 8, // Offset(132), LUX High Value + Offset(133), ALFP, 8, // Offset(133), Active LFP + Offset(134), IPTP, 8, // Offset(134), IPU ACPI device type (0=3DDi= sabled, 1=3DAVStream virtual device as child of GFX) + Offset(135), EDPV, 8, // Offset(135), Check for eDP display device + Offset(136), SGMD, 8, // Offset(136), SG Mode (0=3DDisabled, 1=3DS= G Muxed, 2=3DSG Muxless, 3=3DDGPU Only) + Offset(137), SGFL, 8, // Offset(137), SG Feature List + Offset(138), SGGP, 8, // Offset(138), PCIe0 GPIO Support (0=3DDisa= bled, 1=3DPCH Based, 2=3DI2C Based) + Offset(139), HRE0, 8, // Offset(139), PCIe0 HLD RST IO Expander Nu= mber + Offset(140), HRG0, 32, // Offset(140), PCIe0 HLD RST GPIO Number + Offset(144), HRA0, 8, // Offset(144), PCIe0 HLD RST GPIO Active In= formation + Offset(145), PWE0, 8, // Offset(145), PCIe0 PWR Enable IO Expander= Number + Offset(146), PWG0, 32, // Offset(146), PCIe0 PWR Enable GPIO Number + Offset(150), PWA0, 8, // Offset(150), PCIe0 PWR Enable GPIO Active= Information + Offset(151), P1GP, 8, // Offset(151), PCIe1 GPIO Support (0=3DDisa= bled, 1=3DPCH Based, 2=3DI2C Based) + Offset(152), HRE1, 8, // Offset(152), PCIe1 HLD RST IO Expander Nu= mber + Offset(153), HRG1, 32, // Offset(153), PCIe1 HLD RST GPIO Number + Offset(157), HRA1, 8, // Offset(157), PCIe1 HLD RST GPIO Active In= formation + Offset(158), PWE1, 8, // Offset(158), PCIe1 PWR Enable IO Expander= Number + Offset(159), PWG1, 32, // Offset(159), PCIe1 PWR Enable GPIO Number + Offset(163), PWA1, 8, // Offset(163), PCIe1 PWR Enable GPIO Active= Information + Offset(164), P2GP, 8, // Offset(164), PCIe2 GPIO Support (0=3DDisa= bled, 1=3DPCH Based, 2=3DI2C Based) + Offset(165), HRE2, 8, // Offset(165), PCIe2 HLD RST IO Expander Nu= mber + Offset(166), HRG2, 32, // Offset(166), PCIe2 HLD RST GPIO Number + Offset(170), HRA2, 8, // Offset(170), PCIe2 HLD RST GPIO Active In= formation + Offset(171), PWE2, 8, // Offset(171), PCIe2 PWR Enable IO Expander= Number + Offset(172), PWG2, 32, // Offset(172), PCIe2 PWR Enable GPIO Number + Offset(176), PWA2, 8, // Offset(176), PCIe2 PWR Enable GPIO Active= Information + Offset(177), DLPW, 16, // Offset(177), Delay after power enable for= PCIe + Offset(179), DLHR, 16, // Offset(179), Delay after Hold Reset for P= CIe + Offset(181), EECP, 8, // Offset(181), PCIe0 Endpoint Capability St= ructure Offset + Offset(182), XBAS, 32, // Offset(182), Any Device's PCIe Config Spa= ce Base Address + Offset(186), GBAS, 16, // Offset(186), GPIO Base Address + Offset(188), NVGA, 32, // Offset(188), NVIG opregion address + Offset(192), NVHA, 32, // Offset(192), NVHM opregion address + Offset(196), AMDA, 32, // Offset(196), AMDA opregion address + Offset(200), LTRX, 8, // Offset(200), Latency Tolerance Reporting = Enable + Offset(201), OBFX, 8, // Offset(201), Optimized Buffer Flush and F= ill + Offset(202), LTRY, 8, // Offset(202), Latency Tolerance Reporting = Enable + Offset(203), OBFY, 8, // Offset(203), Optimized Buffer Flush and F= ill + Offset(204), LTRZ, 8, // Offset(204), Latency Tolerance Reporting = Enable + Offset(205), OBFZ, 8, // Offset(205), Optimized Buffer Flush and F= ill + Offset(206), LTRW, 8, // Offset(206), Latency Tolerance Reporting = Enable + Offset(207), OBFA, 8, // Offset(207), Optimized Buffer Flush and F= ill + Offset(208), SMSL, 16, // Offset(208), SA Peg Latency Tolerance Rep= orting Max Snoop Latency + Offset(210), SNSL, 16, // Offset(210), SA Peg Latency Tolerance Rep= orting Max No Snoop Latency + Offset(212), P0UB, 8, // Offset(212), Peg0 Unused Bundle Control + Offset(213), P1UB, 8, // Offset(213), Peg1 Unused Bundle Control + Offset(214), P2UB, 8, // Offset(214), Peg2 Unused Bundle Control + Offset(215), P3UB, 8, // Offset(215), Peg3 Unused Bundle Control + Offset(216), PCSL, 8, // Offset(216), The lowest C-state for the p= ackage + Offset(217), PBGE, 8, // Offset(217), Pegx Unused Bundle Control G= lobal Enable (0=3DDisabled, 1=3DEnabled) + Offset(218), M64B, 64, // Offset(218), Base of above 4GB MMIO resou= rce + Offset(226), M64L, 64, // Offset(226), Length of above 4GB MMIO res= ource + Offset(234), CPEX, 32, // Offset(234), CPU ID info to get Family Id= or Stepping + Offset(238), EEC1, 8, // Offset(238), PCIe1 Endpoint Capability St= ructure Offset + Offset(239), EEC2, 8, // Offset(239), PCIe2 Endpoint Capability St= ructure Offset + Offset(240), SBN0, 8, // Offset(240), PCIe0 Secondary Bus Number (= PCIe0 Endpoint Bus Number) + Offset(241), SBN1, 8, // Offset(241), PCIe1 Secondary Bus Number (= PCIe0 Endpoint Bus Number) + Offset(242), SBN2, 8, // Offset(242), PCIe2 Secondary Bus Number (= PCIe0 Endpoint Bus Number) + Offset(243), M32B, 32, // Offset(243), Base of below 4GB MMIO resou= rce + Offset(247), M32L, 32, // Offset(247), Length of below 4GB MMIO res= ource + Offset(251), P0WK, 32, // Offset(251), PCIe0 RTD3 Device Wake GPIO = Number + Offset(255), P1WK, 32, // Offset(255), PCIe1 RTD3 Device Wake GPIO = Number + Offset(259), P2WK, 32, // Offset(259), PCIe2 RTD3 Device Wake GPIO = Number + Offset(263), VTDS, 8, // Offset(263), VT-d Enable/Disable + Offset(264), VTB1, 32, // Offset(264), VT-d Base Address 1 + Offset(268), VTB2, 32, // Offset(268), VT-d Base Address 2 + Offset(272), VTB3, 32, // Offset(272), VT-d Base Address 3 + Offset(276), VE1V, 16, // Offset(276), VT-d Engine#1 Vendor ID + Offset(278), VE2V, 16, // Offset(278), VT-d Engine#2 Vendor ID + Offset(280), SBN3, 8, // Offset(280), PCIe3 Secondary Bus Number (= PCIe3 Endpoint Bus Number) + Offset(281), P3GP, 8, // Offset(281), PCIe3 GPIO Support (0=3DDisa= bled, 1=3DPCH Based, 2=3DI2C Based) + Offset(282), HRE3, 8, // Offset(282), PCIe3 HLD RST IO Expander Nu= mber + Offset(283), HRG3, 32, // Offset(283), PCIe3 HLD RST GPIO Number + Offset(287), HRA3, 8, // Offset(287), PCIe3 HLD RST GPIO Active In= formation + Offset(288), PWE3, 8, // Offset(288), PCIe3 PWR Enable IO Expander= Number + Offset(289), PWG3, 32, // Offset(289), PCIe3 PWR Enable GPIO Number + Offset(293), PWA3, 8, // Offset(293), PCIe3 PWR Enable GPIO Active= Information + Offset(294), P3WK, 32, // Offset(294), PCIe3 RTD3 Device Wake GPIO = Number + Offset(298), EEC3, 8, // Offset(298), PCIe3 Endpoint Capability St= ructure Offset + Offset(299), RPIN, 8, // Offset(299), RootPort Number + Offset(300), RPBA, 32, // Offset(300), RootPortAddress + Offset (500), // Offset(304) : Offset(499), Reserved bytes + } diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSs= dt/SaSsdt.asl b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/S= aSsdt/SaSsdt.asl new file mode 100644 index 0000000000..0db354901d --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSs= dt.asl @@ -0,0 +1,22 @@ +/** @file + This file contains the SystemAgent SSDT Table ASL code. + It defines a Global NVS table which exchanges datas between OS + and BIOS. + + Copyright (c) 2019 Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +DefinitionBlock ( + "SaSsdt.aml", + "SSDT", + 0x02, + "SaSsdt", + "SaSsdt ", + 0x3000 + ) +{ + include ("SaNvs.asl") + include ("Sa.asl") +} --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45906): https://edk2.groups.io/g/devel/message/45906 Mute This Topic: https://groups.io/mt/32918199/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45905+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45905+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001019; cv=none; d=zoho.com; s=zohoarc; b=Ec+XjKgTxB70fdyir9JaLGyx1BM+ZeSVe1AurEJlgHl52hR09w2a1NNOjLbpl+ypS9DwTK2OJvXZpxAGCDbFxEAvo1qaxgWWiOPju5A+xCq49Y1HMEq4ijRuJa1EcUTN5FEqm4fUSDlD2PH1J2rOAoI7hZqKlHUJzulURIIFszc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001019; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZPQooGbGHBeoBZsuk67HJCUENmHiR59fFcGifp2AigM=; b=QYFQ+q4wl3gDEtWsdbI9XOe3T1f6UahVAM2NyVBT4NhPbPCWJyn+p8a3llV209Zp7UCENcccSlt0hbnmq7NwSmSrkhpAVDAVcvtghTv4lAd+hNW7maHsBUxBbpA0mtFNl8I62bcIQb6+jiynwXb+DXJBRQatO8SyfGbFJKOPnqk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45905+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156600101956615.237835320601448; Fri, 16 Aug 2019 17:16:59 -0700 (PDT) Return-Path: X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:58 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319331" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:57 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 29/37] CoffeelakeSiliconPkg: Add package DSC files Date: Fri, 16 Aug 2019 17:15:55 -0700 Message-Id: <20190817001603.30632-30-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001019; bh=Ytp9yrpdNVlR6lNZPecvXen26E+kGhsoOrIqMBYvdqI=; h=Cc:Date:From:Reply-To:Subject:To; b=fAmKM3umK17tWHTOSrYjMQPrNMZR8/CTLVC9T0SIMmSskqTvGOd25VnqpELlmStn8HH FPWkn9SGPy0kpvYI73fEg73pUO/0zpA4njgkeCmhLCJo5fW8lngJibrpcwwyC+bwektHs sbezJpg9SX4sHXj1MFRPuwO845NcpBYKv40= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc | 215 ++++++++= ++++++++++++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc | 130 ++++++++= ++++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc | 69 +++++++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc | 33 +++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc | 37 ++++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc | 21 ++ Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc | 44 ++++ 7 files changed, 549 insertions(+) diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc b/= Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc new file mode 100644 index 0000000000..37c77d8f63 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/CoffeelakeSiliconPkg.dsc @@ -0,0 +1,215 @@ +## @file +# Component description file for the Coffee Lake silicon package DSC file. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[PcdsFeatureFlag] +gSiPkgTokenSpaceGuid.PcdTraceHubEnable |FALSE +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE +gSiPkgTokenSpaceGuid.PcdSiCsmEnable |FALSE +gSiPkgTokenSpaceGuid.PcdUseHpetTimer |TRUE +gSiPkgTokenSpaceGuid.PcdSgEnable |TRUE +gSiPkgTokenSpaceGuid.PcdAcpiEnable |FALSE +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE +gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE +gSiPkgTokenSpaceGuid.PcdIpuEnable |TRUE +gSiPkgTokenSpaceGuid.PcdGnaEnable |TRUE +gSiPkgTokenSpaceGuid.PcdSaOcEnable |TRUE +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE +gSiPkgTokenSpaceGuid.PcdCflCpuEnable |FALSE +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |TRUE +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE + +[PcdsFixedAtBuild.common] +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000 + + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |10 + gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |18 + +[PcdsDynamicDefault.common] +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000 + +## Specifies the AP wait loop state during POST phase. +# The value is defined as below. +# 1: Place AP in the Hlt-Loop state. +# 2: Place AP in the Mwait-Loop state. +# 3: Place AP in the Run-Loop state. +# @Prompt The AP wait loop state. +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 +## Specifies the AP target C-state for Mwait during POST phase. +# The default value 0 means C1 state. +# The value is defined as below.

+# @Prompt The specified AP target C-state for Mwait. +gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 + +[Defines] + PLATFORM_NAME =3D CoffeelakeSiliconPkg + PLATFORM_GUID =3D A45CA44C-AB04-4932-A77C-5A7179F66A22 + PLATFORM_VERSION =3D 0.4 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/CoffeelakeSiliconPkg + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + + DEFINE PLATFORM_SI_PACKAGE =3D CoffeelakeSiliconPkg + + # + # Definition for Build Flag + # + !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc + +[LibraryClasses.common] + # + # Entry point + # + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf + + # + # Basic + # + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf + # + # UEFI & PI + # + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf + + S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL= ibNull.inf + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf + + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf + + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + SmiHandlerProfileLib|Edk2/MdePkg/Library/SmiHandlerProfileLibNull/SmiHan= dlerProfileLibNull.inf + + # + # Misc + # + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf + PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + MtrrLib|ClientSiliconPkg/Override/UefiCpuPkg/Library/MtrrLib/MtrrLib.inf= # CSPO-0012: RoyalParkOverrideContent + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf + +##########################################################################= ########################### + +# +# Silicon Init Common Library +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc +ConfigBlockLib|ClientSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlock= Lib.inf +PchTraceHubInitLib|ClientSiliconPkg/Library/BasePchTraceHubInitLib/BasePch= TraceHubInitLib.inf + +[LibraryClasses.IA32] +# +# PEI phase common +# + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf + +##########################################################################= ########################################################### + +# +# Silicon Init Pei Library +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc + +[LibraryClasses.IA32.SEC] + +[LibraryClasses.X64] + # + # DXE phase common + # + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf + +# +# Hsti +# + HstiLib|MdePkg/Library/DxeHstiLib/DxeHstiLib.inf + +##########################################################################= ######################### +# +# Silicon Init Dxe Library +# +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + +[LibraryClasses.X64.PEIM] + +[LibraryClasses.X64.DXE_CORE] + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.X64.DXE_SMM_DRIVER] + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableL= ib.inf + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAlloc= ationLib.inf + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf + +[LibraryClasses.X64.SMM_CORE] + +[LibraryClasses.X64.UEFI_DRIVER] + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + +[LibraryClasses.X64.UEFI_APPLICATION] + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf + +[Components.IA32] +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + +[Components.X64] +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc b/Sili= con/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc new file mode 100644 index 0000000000..b6d2058669 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgBuildOption.dsc @@ -0,0 +1,130 @@ +## @file +# Silicon build option configuration file. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[BuildOptions] +# Define Build Options both for EDK and EDKII drivers. + +# SA +!if gSiPkgTokenSpaceGuid.PcdPttEnable =3D=3D TRUE + DEFINE PTT_BUILD_OPTION =3D -DPTT_FLAG=3D1 +!else + DEFINE PTT_BUILD_OPTION =3D +!endif + +# +# System Agent +# +!if gSiPkgTokenSpaceGuid.PcdSgEnable =3D=3D TRUE + DEFINE DSC_SG_BUILD_OPTIONS =3D -DSG_SUPPORT=3D1 +!else + DEFINE DSC_SG_BUILD_OPTIONS =3D +!endif + +!if gSiPkgTokenSpaceGuid.PcdBdatEnable =3D=3D TRUE + DEFINE BDAT_BUILD_OPTION =3D -DBDAT_SUPPORT=3D1 +!else + DEFINE BDAT_BUILD_OPTION =3D +!endif + + DEFINE SLE_BUILD_OPTIONS =3D +!if $(TARGET) =3D=3D RELEASE +!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable =3D=3D TRUE + DEFINE DEBUG_BUILD_OPTIONS =3D +!else + # MDEPKG_NDEBUG is introduced for the intention + # of size reduction when compiler optimization is disabled. If MDEPKG_ND= EBUG is + # defined, then debug and assert related macros wrapped by it are the NU= LL implementations. + DEFINE DEBUG_BUILD_OPTIONS =3D -DMDEPKG_NDEBUG +!endif +!else + DEFINE DEBUG_BUILD_OPTIONS =3D +!endif + +!if ($(TARGET) =3D=3D RELEASE) AND (gSiPkgTokenSpaceGuid.PcdSiCatalogDebug= Enable =3D=3D TRUE) + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =3D -DRELEASE_CATALOG +!else + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =3D +!endif + +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL- +!else + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D +!endif + + DEFINE HSLE_BUILD_OPTIONS =3D + +!if gSiPkgTokenSpaceGuid.PcdCflCpuEnable =3D=3D TRUE + DEFINE CPU_FLAGS =3D -DCPU_CFL +!else + DEFINE CPU_FLAGS =3D +!endif + + +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =3D $(BDAT_BUILD_OPTION) $(PTT_BUIL= D_OPTION) $(DEBUG_BUILD_OPTIONS) +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIO= NS) $(DSC_SG_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(CPU_FLAGS) $(HSLE_BUI= LD_OPTIONS) $(RELEASE_CATALOG_BUILD_OPTIONS) $(DSC_TXT_BUILD_OPTIONS) + +!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable =3D=3D TRUE + *_*_X64_GENFW_FLAGS =3D --keepexceptiontable +!endif + +[BuildOptions.Common.EDKII] + +# +# For IA32 Global Build Flag +# + *_*_IA32_PP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI= _SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI + *_*_IA32_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For IA32 Specific Build Flag +# +MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI +MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) + +# +# For X64 Global Build Flag +# + *_*_X64_PP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI= _SPECIFICATION_VERSION=3D0x00010015 + *_*_X64_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For X64 Specific Build Flag +# +MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 +MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) + +# +# For Xcode Specific Build Flag +# +# Override assembly code build order +*_XCODE5_*_*_BUILDRULEORDER =3D nasm S s +# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of VA_ST= ART in undefined way +*_XCODE5_*_CC_FLAGS =3D -Wno-varargs + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection of runtime modules +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096 + GCC: *_GCC*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc b/Silico= n/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc new file mode 100644 index 0000000000..2df08c6d01 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgCommonLib.dsc @@ -0,0 +1,69 @@ +## @file +# Component description file for the Coffee Lake silicon package both PEI= and DXE libraries DSC file. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Set PCH generation according PCD. +# The DEFINE will be used to select PCH library INF file corresponding to = PCH generation +# +DEFINE PCH =3D Cnl + +# +# Cpu +# + CpuPlatformLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiDxeSmmCpuPlatformLib= /PeiDxeSmmCpuPlatformLib.inf + CpuMailboxLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/BaseCpuMailboxLibNull/Ba= seCpuMailboxLibNull.inf + +# +# Me +# + +# +# Pch +# + PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCycleD= ecodingLib/PeiDxeSmmPchCycleDecodingLib.inf + PchGbeLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchGbeLib/PeiDxeSmm= PchGbeLib.inf + PchInfoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeS= mmPchInfoLib$(PCH).inf + SataLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmSataLib/PeiDxeSmmSata= Lib$(PCH).inf + PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcieRpLib/Pei= DxeSmmPchPcieRpLib.inf + PchPcrLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPcrLib/PeiDxeSmm= PchPcrLib.inf + PmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib= .inf + + PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSbiAccessL= ib/PeiDxeSmmPchSbiAccessLib.inf + GpioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpio= Lib.inf +!if gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable =3D=3D TRUE + PchSerialIoUartLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSerialI= oUartLib/PeiDxeSmmPchSerialIoUartLib.inf +!else + PchSerialIoUartLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchSerialIoUart= LibNull/BasePchSerialIoUartLibNull.inf +!endif + PchSerialIoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchSerialIoLib= /PeiDxeSmmPchSerialIoLibCnl.inf + PchEspiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchEspiLib/PeiDxeS= mmPchEspiLib.inf + PchWdtCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchWdtCommonL= ib/PeiDxeSmmPchWdtCommonLib.inf + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/Base= ResetSystemLib.inf + SmbusLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseSmbusLib/BaseSmbusLib.inf + BiosLockLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmBiosLockLib/PeiDx= eSmmBiosLockLib.inf + #private + PchPciExpressHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxe= SmmPchPciExpressHelpersLib/PeiDxeSmmPchPciExpressHelpersLib.inf + PchInitCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchI= nitCommonLib/PeiDxeSmmPchInitCommonLib.inf + PchSpiCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BasePchSpiComm= onLib/BasePchSpiCommonLib.inf + GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmGpioPr= ivateLib/PeiDxeSmmGpioPrivateLibCnl.inf + PchPsfPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchP= sfPrivateLib/PeiDxeSmmPchPsfPrivateLib$(PCH).inf + PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPmcPriv= ateLib/PeiDxeSmmPmcPrivateLibCnl.inf + PmcPrivateLibWithS3|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmP= mcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf + PchDmiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchDmiLib/P= eiDxeSmmPchDmiLib.inf + PchDmiWithS3Lib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiDxeSmmPchDm= iLib/PeiDxeSmmPchDmiWithS3Lib.inf + SiScheduleResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BaseSiSched= uleResetLib/BaseSiScheduleResetLib.inf + +# +# SA +# + SaPlatformLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiDxeSmmSaPlatf= ormLib/PeiDxeSmmSaPlatformLib.inf + +# +# Memory +# diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc b/Silicon/Inte= l/CoffeelakeSiliconPkg/SiPkgDxe.dsc new file mode 100644 index 0000000000..07677ece1a --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxe.dsc @@ -0,0 +1,33 @@ +## @file +# Component description file for the Coffee Lake silicon package DXE driv= ers. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Common +# + +# +# Pch +# + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf + $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf + + $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf + + $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf + +# +# SystemAgent +# + $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf + +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf +!endif diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc b/Silicon/I= ntel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc new file mode 100644 index 0000000000..214de06d58 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgDxeLib.dsc @@ -0,0 +1,37 @@ +## @file +# Component description file for the Coffee Lake silicon package DXE libr= aries. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Silicon Init Dxe Library +# + +# +# Common +# +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE + AslUpdateLib|$(PLATFORM_SI_PACKAGE)/Library/DxeAslUpdateLib/DxeAslUpdateL= ib.inf +!else + AslUpdateLib|$(PLATFORM_SI_PACKAGE)/Library/DxeAslUpdateLibNull/DxeAslUpd= ateLibNull.inf +!endif + SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/Base= SiConfigBlockLib.inf + +# +# Pch +# + PchHdaLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/DxePchHdaLib/DxePchH= daLib.inf + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeResetSystemLib/DxeRe= setSystemLib.inf + DxePchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxePchPolicyLib/DxePch= PolicyLib.inf + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/BaseGpioHelpers= LibNull/BaseGpioHelpersLibNull.inf + GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/DxeGpioNameB= ufferLib/DxeGpioNameBufferLib.inf + SmmPchPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/SmmPchPrivate= Lib/SmmPchPrivateLib.inf + +# +# SystemAgent +# + DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaPolicyLib/= DxeSaPolicyLib.inf diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc b/Silicon/Inte= l/CoffeelakeSiliconPkg/SiPkgPei.dsc new file mode 100644 index 0000000000..f30c7e0ae1 --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPei.dsc @@ -0,0 +1,21 @@ +## @file +# Component description file for theCoffee Lake silicon package PEI drive= rs. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Common +# + +# +# SystemAgent +# + +# +# Cpu +# + diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc b/Silicon/I= ntel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc new file mode 100644 index 0000000000..6e244a6ded --- /dev/null +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SiPkgPeiLib.dsc @@ -0,0 +1,44 @@ +## @file +# Component description file for the Coffee Lake silicon package PEI libr= aries. +# +# Copyright (c) 2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +# +# Silicon Init Pei Library +# + SiPolicyLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiPolicyLib/PeiSiPolicyLib.= inf + SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/Base= SiConfigBlockLib.inf + StallPpiLib|$(PLATFORM_SI_PACKAGE)/Library/PeiInstallStallPpiLib/PeiStall= PpiLib.inf + +# +# Pch +# + PchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchPolicyLib/PeiPchPol= icyLibCnl.inf +!if gSiPkgTokenSpaceGuid.PcdOcWdtEnable =3D=3D TRUE + OcWdtLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiOcWdtLib/PeiOcWdtLib.inf +!else + OcWdtLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiOcWdtLibNull/PeiOcWdtLibNu= ll.inf +!endif + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiResetSystemLib/PeiRe= setSystemLib.inf + PchResetLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiPchResetLib/PeiPchReset= Lib.inf + SpiLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiSpiLib/PeiSpiLib.inf + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiGpioHelpersL= ib/PeiGpioHelpersLib.inf + GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/Private/PeiGpioNameB= ufferLib/PeiGpioNameBufferLib.inf + +# +# Me +# + PeiMePolicyLib|$(PLATFORM_SI_PACKAGE)/Me/Library/PeiMePolicyLib/PeiMePoli= cyLib.inf + +# +# SA +# + PeiSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiSaPolicyLib= /PeiSaPolicyLib.inf +# +# Cpu +# + CpuPolicyLib|$(PLATFORM_SI_PACKAGE)/Cpu/Library/PeiCpuPolicyLib/PeiCpuPol= icyLib.inf --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45905): https://edk2.groups.io/g/devel/message/45905 Mute This Topic: https://groups.io/mt/32918198/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45904+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45904+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001019; cv=none; d=zoho.com; s=zohoarc; b=aTmtnbkCiKAFJzU7RXnlSvprygtntmGi6PBHj8gxcYUKDRyb5EbqjDEHt2sfd54SoWbKYq323jT1er6e1tKI/zZJxvaOc2HhejfCZ+14BPhbfWCE8ZjQ86wy5wtZMlsVGu4ey3ZEkW+W4hRZTOF02BWxujPNpqW+MfnYSY6VjgU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001019; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=cFQQNjqssVAMzPTFTwSfkJ9IORlICJgZ9t8mnXQrTXY=; b=ilrcGfIM/xp5gqezItWnyymkABMRxPAcwGJd2NrZ88Xk+Qmprqp0z4KBK1D+85i6OpwTcMgr9m+pJ/O3nYfWCLmKWYG0BYa++e1Z+JJLswGvaHKqpBPGN+yqymh2um+nCEJIojoTMDPOTaU03IyUIpQb93VEDmwQ9vVR5MhgYrE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45904+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001019262592.569506131642; Fri, 16 Aug 2019 17:16:59 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:16:58 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319337" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:57 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Liming Gao , Michael D Kinney Subject: [edk2-devel] [edk2-platforms][PATCH V1 30/37] Maintainers.txt: Add CoffeelakeSiliconPkg maintainers Date: Fri, 16 Aug 2019 17:15:56 -0700 Message-Id: <20190817001603.30632-31-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001018; bh=gE7wYYdDRwD3Qy9g3ej+8dqYfr34j6LIf1+VRSdehig=; h=Cc:Date:From:Reply-To:Subject:To; b=aNgzz7caICbcZaEDk8ALPPUEiuGyJAhkUNMR4bkWmYiPlX3wYXNw0X4f6D+GeVr3hbP k85oN6e5QBIjH4p5UwNb/2EXcsqv4Hi5H6L5JW3EjUzrhmhtzgEW7Jw8c67jl4dVbVl24 jMVstYhW8UM9WxNzkMXhyPzMmTmzSel/FNo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2082 Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Liming Gao Cc: Michael D Kinney Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Maintainers.txt | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Maintainers.txt b/Maintainers.txt index 876ae5612a..bc8cbd6458 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -125,9 +125,14 @@ Silicon/Intel/Vlv2DeviceRefCodePkg M: Zailiang Sun M: Yi Qian =20 +Silicon/Intel/CoffeelakeSiliconPkg +M: Chasel Chiu +M: Michael Kubacki +M: Sai Chaganty + Silicon/Intel/KabylakeSiliconPkg M: Chasel Chiu -M: Michael A Kubacki +M: Michael Kubacki M: Sai Chaganty =20 Silicon/Intel/LewisburgPkg --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45904): https://edk2.groups.io/g/devel/message/45904 Mute This Topic: https://groups.io/mt/32918197/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45908+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45908+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001031; cv=none; d=zoho.com; s=zohoarc; b=CK/AjPqh1PTmGrC8fIeqmIwGboG7lJ4XV/dRz1VZuNK9IhcShhecqrQtY5I3R5vDkMQGviArPL+uCyiZ6I6++XEvPNmmMZ27xqPczI7YOWEHdK31iGQsmDC9gM9spzLvtDJvRjmorpdvFmXbbHvC6r27YoF2EYDgOSU6Y2YY1HA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001031; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=1dS2z/sjVw2+qrNp+87PWk9v9OW9D0FjOR58fRgu+4s=; b=aHE3VO/VUftefibJPd/zkJ1JaUc3YCgm6J7AEqCpg4m4+KtyWuOI/EXySPiKDF9aOMxDdBg+WUIbTEzyHNHK8wt2H74IL9aQYgOxXhYKKUc+dZat1CHkow2kJ0PROeUtBCW7j4mp2Fum4cktWz7JF6uZYITFb3JQ5jXn16/Nm1I= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45908+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001031120772.3721887295317; Fri, 16 Aug 2019 17:17:11 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:10 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319352" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:58 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 31/37] WhiskeylakeOpenBoardPkg: Add package and headers Date: Fri, 16 Aug 2019 17:15:57 -0700 Message-Id: <20190817001603.30632-32-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001030; bh=47jzmYjNm5cmCBiTlB5ppRebgVHfV7Y38P7+vXshGEw=; h=Cc:Date:From:Reply-To:Subject:To; b=HOvoOnaEQod+jBpgmL8wrQ7n5r9uo9nHPQsoZ8FdCIKOOuLaC6vWA4MldXzhfg/Ag8x b2cnSN5s9rkJmPnQ8sQhiDE+tri/TGRKetzBc650U7fzcYrlhRc1aBnrE8AgEfv2TlaYM qeiWnS+t/hNsFM3zecx/phK9AkTFsxBjJgQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 Create the WhiskeylakeOpenBoardPkg to provide board support code. The package may support Coffee Lake (CFL) and Whiskey Lake (WHL) boards. The package serves as a board support package in the EDK II Minimum Platform design. Silicon support for this package is provided in CoffeeLakeFspBinPkg in the FSP repository and CoffeelakeSiliconPkg in the edk2-platforms repository. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec = | 565 +++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/DxeChe= ckIommuSupportLib.h | 43 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbt= PolicyLib.h | 49 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/DxeTbt= SecurityLib.h | 131 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/PeiChe= ckIommuSupportLib.h | 21 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbt= PolicyLib.h | 43 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/PeiTbt= TaskDispatchLib.h | 61 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/TbtCom= monLib.h | 261 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTbtPoli= cy.h | 31 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Private/Librar= y/PeiDTbtInitLib.h | 130 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Private/Librar= y/PeiTbtCommonInitLib.h | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/Disab= leBmeProtocol.h | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/DxeTb= tPolicy.h | 137 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/TbtNv= sArea.h | 50 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtBoardInfo.h= | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtNvsAreaDef.= h | 68 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtPolicyCommo= nDefinition.h | 84 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h = | 118 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/AttemptUsbFirst.h = | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/CpuSmm.h = | 57 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/FirwmareConfigurations.h = | 20 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/GopConfigLib.h = | 1766 ++++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h = | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/IoExpander.h = | 68 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeCpuPolicyUpdateL= ib.h | 75 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeMePolicyUpdateLi= b.h | 27 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePchPolicyUpdateL= ib.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePolicyBoardConfi= gLib.h | 30 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeSaPolicyUpdateLi= b.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/FspPolicyInitLib.h = | 29 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioCheckConflictLi= b.h | 46 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioExpanderLib.h = | 123 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/HdaVerbTableLib.h = | 48 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/I2cAccessLib.h = | 34 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPlatformLib.h = | 40 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPolicyBoardConfi= gLib.h | 141 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPolicyInitLib.h = | 38 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PlatformInitLib.h = | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PchHsioPtssTables.h = | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h = | 106 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Platform.h = | 33 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PlatformBoardId.h = | 29 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Protocol/GlobalNvsArea.h = | 47 + Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Setup.h = | 144 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/SioRegs.h = | 157 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl = | 112 ++ 46 files changed, 5288 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec b/Plat= form/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec new file mode 100644 index 0000000000..9d56f0e841 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec @@ -0,0 +1,565 @@ +## @file +# Module describe the entire platform configuration. +# +# The DEC files are used by the utilities that parse DSC and +# INF files to generate AutoGen.c and AutoGen.h files +# for the build infrastructure. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + + +[Defines] +DEC_SPECIFICATION =3D 0x00010017 +PACKAGE_NAME =3D OpenBoardPkg +PACKAGE_VERSION =3D 0.1 +PACKAGE_GUID =3D 0A8BA6E8-C8AC-4AC1-87AC-52772FA6AE5E + +[Includes] +Include +WhiskeylakeURvp\Include +Features\Tbt\Include + +[Guids] + +gBoardModuleTokenSpaceGuid =3D {0x72d1fff7, 0xa42a, 0x4219, {0= xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}} + +gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0= x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} + +gTbtInfoHobGuid =3D {0x74a81eaa, 0x033c, 0x4783, {0= xbe, 0x2b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}} + +gPlatformModuleTokenSpaceGuid =3D {0x69d13bf0, 0xaf91, 0x4d96, {0= xaa, 0x9f, 0x21, 0x84, 0xc5, 0xce, 0x3b, 0xc0}} + +gMeInfoSetupGuid =3D {0x78259433, 0x7b6d, 0x4db3, {0= x9a, 0xe8, 0x36, 0xc4, 0xc2, 0xc3, 0xa1, 0x7d}} +gRealModeFileGuid =3D {0xdf84ed23, 0x5d53, 0x423f, {0= xaa, 0x81, 0x0f, 0x0e, 0x6f, 0x55, 0xc6, 0x9b}} +gVirtualKeyboardDriverImageGuid =3D {0xe4735aac, 0x9c27, 0x493f, {0= x86, 0xea, 0x9e, 0xff, 0x43, 0xd7, 0xad, 0xcd}} +gPegConfigVariableGuid =3D {0xb414caf8, 0x8225, 0x4d6f, {0= xb9, 0x18, 0xcd, 0xe5, 0xcb, 0x84, 0xcf, 0x0b}} +gSaSetupVariableGuid =3D {0x72c5e28c, 0x7783, 0x43a1, {0= x87, 0x67, 0xfa, 0xd7, 0x3f, 0xcc, 0xaf, 0xa4}} +gMeSetupVariableGuid =3D {0x5432122d, 0xd034, 0x49d2, {0= xa6, 0xde, 0x65, 0xa8, 0x29, 0xeb, 0x4c, 0x74}} +gCpuSetupVariableGuid =3D {0xb08f97ff, 0xe6e8, 0x4193, {0= xa9, 0x97, 0x5e, 0x9e, 0x9b, 0xa, 0xdb, 0x32}} +gCpuSmmGuid =3D {0x90d93e09, 0x4e91, 0x4b3d, {0= x8c, 0x77, 0xc8, 0x2f, 0xf1, 0xe, 0x3c, 0x81}} +gPchSetupVariableGuid =3D {0x4570b7f1, 0xade8, 0x4943, {0= x8d, 0xc3, 0x40, 0x64, 0x72, 0x84, 0x23, 0x84}} +gSiSetupVariableGuid =3D {0xAAF8E719, 0x48F8, 0x4099, {0= xA6, 0xF7, 0x64, 0x5F, 0xBD, 0x69, 0x4C, 0x3D}} +gDebugConfigVariableGuid =3D {0xDE0A5E74, 0x4E3E, 0x3D96, {0= xA4, 0x40, 0x2C, 0x96, 0xEC, 0xBD, 0x3C, 0x97}} +gDebugConfigHobGuid =3D {0x2f6a6bb7, 0x9dc7, 0x4bf6, {0= x94, 0x04, 0x22, 0x70, 0xc0, 0xe3, 0xbe, 0x2f}} +gChassisIntrudeDetHobGuid =3D {0xdea43de2, 0x756b, 0x4b3b, {0= x75, 0x1c, 0xad, 0xeb, 0x8d, 0xff, 0x56, 0xa3}} + +gGpioCheckConflictHobGuid =3D {0x5603f872, 0xefac, 0x40ae, {0= xb9, 0x7e, 0x13, 0xb2, 0xf8, 0x07, 0x80, 0x21}} + +gAttemptUsbFirstHotkeyInfoHobGuid =3D {0x38b8e214, 0x1468, 0x4bb7, {0= x95, 0xb1, 0x74, 0x59, 0x1e, 0x4c, 0x6e, 0x1d}} +gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, {0= x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}} +## +## ChipsetInitBinary +## +gCnlPchLpChipsetInitTableDxGuid =3D {0xc9505bc0, 0xaa3d, 0x4056,= {0x99, 0x95, 0x87, 0x0c, 0x8d, 0xe8, 0x59, 0x4e}} + + +[Protocols] +gTbtNvsAreaProtocolGuid =3D {0x4d6a54d1, 0xcd56, 0x47f3, {0= x93, 0x6e, 0x7e, 0x51, 0xd9, 0x31, 0x15, 0x4f}} +gDxeTbtPolicyProtocolGuid =3D {0x196bf9e3, 0x20d7, 0x4b7b, {0= x89, 0xf9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}} + +[Ppis] +gPeiTbtPolicyPpiGuid =3D {0xd7e7e1e6, 0xcbec, 0x4f5f, {0= xae, 0xd3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}} +gPeiTbtPolicyBoardInitDonePpiGuid =3D {0x970f9c60, 0x8547, 0x49d7, { = 0xa4, 0xb, 0x1e, 0xc4, 0xbc, 0x4e, 0xe8, 0x9b}} + +[LibraryClasses] + +[PcdsFixedAtBuild, PcdsPatchableInModule] + +[PcdsFixedAtBuild] + +gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004 +gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x10001005 + +gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT64|0x900000= 03 +gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x90000004 +gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress|0xFED19000|UINT64|0x90000005 +gPlatformModuleTokenSpaceGuid.PcdEpMmioSize|0x1000|UINT32|0x90000006 +gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress|0xFED84000|UINT64|0x90000= 007 +gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize|0x1000|UINT32|0x90000008 +gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress|0xFED80000|UINT64|0x9000= 0009 +gPlatformModuleTokenSpaceGuid.PcdEdramMmioSize|0x4000|UINT32|0x9000000A +gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress|0xFEE00000|UINT64|0x9000= 000B +gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize|0x1000|UINT32|0x9000000C +gPlatformModuleTokenSpaceGuid.PcdApicIoAddress|0xFEC00000|UINT64|0x9000000D +gPlatformModuleTokenSpaceGuid.PcdApicIoMmioSize|0x1000|UINT32|0x9000000E +gPlatformModuleTokenSpaceGuid.PcdGttMmAddress|0xCF000000|UINT64|0x9000000F +gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress|0xD0000000|UINT64|0x90000010 +gPlatformModuleTokenSpaceGuid.PcdAcpiEnableSwSmi|0xF0|UINT8|0x90000012 +gPlatformModuleTokenSpaceGuid.PcdAcpiDisableSwSmi|0xF1|UINT8|0x90000013 +gPlatformModuleTokenSpaceGuid.PcdPcieDockBridgeResourcePatchSmi|0x4D|UINT8= |0x90000014 +gPlatformModuleTokenSpaceGuid.PcdCmosFastBootDefaultValue|0x01|UINT8|0x900= 00016 +gPlatformModuleTokenSpaceGuid.PcdCmosDebugPrintErrorLevelDefaultValue|0x80= 000046|UINT32|0x90000017 +gPlatformModuleTokenSpaceGuid.PcdOverClockingInterfaceSwSmi|0x72|UINT8|0x9= 0000019 +gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort|0x2F|UINT16|= 0x9000001A +gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort|0x2E|UINT16= |0x9000001B +gPlatformModuleTokenSpaceGuid.PcdApicIoIdPch|0x02|UINT8|0x9000001E +gPlatformModuleTokenSpaceGuid.PcdRuntimeUpdateFvHeaderLength|0x48|UINT8|0x= 90000020 +gPlatformModuleTokenSpaceGuid.PcdEcExtraIoBase|0x6A0|UINT16|0x20000505 +gPlatformModuleTokenSpaceGuid.PcdFspTemporaryRamSize|0x1000|UINT32|0x10001= 003 + +gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition|0x01|UINT8|0x90000015 +gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018 +gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x9000= 001C +gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D +gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F +gBoardModuleTokenSpaceGuid.PcdLpcSioIndexDefaultPort|0x164E|UINT16|0x90000= 021 +gBoardModuleTokenSpaceGuid.PcdLpcSioDataDefaultPort|0x164F|UINT16|0x900000= 22 + +[PcdsDynamic] +# Board GPIO Table +gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2|0|UINT32|0x00000042 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size|0|UINT16|0x00000043 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x000000113 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000114 + +# Board Expander GPIO Table +gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable|0|UINT32|0x00000044 +gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize|0|UINT16|0x00000045 +gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2|0|UINT32|0x00000046 +gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size|0|UINT16|0x00000047 + +# TouchPanel & SDHC CD GPIO Table +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel|0|UINT32|0x00000048 + +# PCH-LP HSIO PTSS Table +gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1|0|UINT32|0x0000004A +gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2|0|UINT32|0x0000004B +gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size|0|UINT16|0x000000= 4C +gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size|0|UINT16|0x000000= 4D +gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1|0|UINT32|0x0000004E +gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2|0|UINT32|0x0000004F +gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size|0|UINT16|0x0000= 0050 +gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size|0|UINT16|0x0000= 0051 + +# PCH-H HSIO PTSS Table +gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1|0|UINT32|0x00000052 +gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2|0|UINT32|0x00000053 +gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size|0|UINT16|0x00000054 +gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size|0|UINT16|0x00000055 +gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1|0|UINT32|0x00000056 +gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2|0|UINT32|0x00000057 +gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size|0|UINT16|0x00000= 058 +gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size|0|UINT16|0x00000= 059 + +# HDA Verb Table +gBoardModuleTokenSpaceGuid.PcdHdaVerbTable|0|UINT32|0x0000005A +gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2|0|UINT32|0x0000005B +gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable|0|UINT32|0x0000005C +gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1|0|UINT32|0x0000005D +gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2|0|UINT32|0x0000005E +gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3|0|UINT32|0x0000005F +gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable|0|UINT32|0x00000060 + +# SA Misc Configuration +gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066 +gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x00000067 +gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit|0|UINT16|0x00000101 + +# DRAM Configuration +gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor|0|UINT32|0x00000068 +gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget|0|UINT32|0x00000069 +gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap|0|UINT32|0x0000006A +gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize|0|UINT16|0x0000006B +gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram|0|UINT32|0x0000006C +gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize|0|UINT16|0x0000006D +gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl|FALSE|BOOLEAN|0x= 0000006E +gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved|FALSE|BOOLEAN|0x0000006F +gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000070 +gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000071 + +# PEG RESET GPIO +gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl|FALSE|BOOLEAN|0x00000072 +gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort|FALSE|BOOLEAN|0x00000073 +gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo|0|UINT32|0x00000079 +gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo|0|UINT8|0x0000007A +gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo|0|UINT32|0x0000007B +gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive|FALSE|BOOLEAN|0x0000007C +gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo|0|UINT8|0x0000007D +gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo|0|UINT32|0x0000007E +gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive|FALSE|BOOLEAN|0x0000007F + +# SPD Address Table +gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099 +gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A +gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B +gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0000009C + +# CA Vref Configuration +gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig|0|UINT8|0x0000009D + +# USB 2.0 Port AFE +gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe|0|UINT32|0x000000BF +gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe|0|UINT32|0x000000C0 +gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe|0|UINT32|0x000000C1 +gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe|0|UINT32|0x000000C2 +gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe|0|UINT32|0x000000C3 +gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe|0|UINT32|0x000000C4 +gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe|0|UINT32|0x000000C5 +gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe|0|UINT32|0x000000C6 +gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe|0|UINT32|0x000000C7 +gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe|0|UINT32|0x000000C8 +gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe|0|UINT32|0x000000C9 +gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe|0|UINT32|0x000000CA +gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe|0|UINT32|0x000000CB +gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe|0|UINT32|0x000000CC +gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe|0|UINT32|0x000000CD +gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe|0|UINT32|0x000000CE + +# USB 2.0 Port Over Current Pin +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0|UINT8|0x000000CF +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0|UINT8|0x000000D0 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0|UINT8|0x000000D1 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0|UINT8|0x000000D2 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0|UINT8|0x000000D3 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0|UINT8|0x000000D4 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0|UINT8|0x000000D5 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0|UINT8|0x000000D6 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0|UINT8|0x000000D7 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0|UINT8|0x000000D8 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0|UINT8|0x000000D9 +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0|UINT8|0x000000DA +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0|UINT8|0x000000DB +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0|UINT8|0x000000DC +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0|UINT8|0x000000DD +gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0|UINT8|0x000000DE + +# USB 3.0 Port Over Current Pin +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0|UINT8|0x000000DF +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0|UINT8|0x000000E0 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0|UINT8|0x000000E1 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0|UINT8|0x000000E2 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0|UINT8|0x000000E3 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0|UINT8|0x000000E4 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0|UINT8|0x000000E5 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0|UINT8|0x000000E6 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0|UINT8|0x000000E7 +gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0|UINT8|0x000000E8 + +# Misc +gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent|FALSE|BOOLEAN|0x000000EC + +# TBT +gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel |0|BOOLEAN|0x000000F3 +gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad |0|UINT32|0x000000F4 +gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad |0|UINT32|0x000000F5 +gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport |0|UINT8|0x000000FA +gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI |0|UINT8|0x000000FB +gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify |0|UINT8|0x000000FC +gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq|0|UINT8|0x000000FD +gBoardModuleTokenSpaceGuid.PcdDTbtAspm |0|UINT8|0x000000FE +gBoardModuleTokenSpaceGuid.PcdDTbtLtr | 0 | UINT8| 0x00000116 +gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch |0|UINT8|0x000000FF +gBoardModuleTokenSpaceGuid.PcdRtd3Tbt |0|UINT8|0x00000100 +gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq |0|UINT8|0x0000010A +gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax |0|UINT8|0x00000107 +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd |0|UINT16|0x00000108 +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax |0|UINT8|0x00000109 + +# UCMC GPIO Table +gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable|0|UINT32|0x000000111 +gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize|0|UINT16|0x000000112 + +gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002 +gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003 +gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004 +gBoardModuleTokenSpaceGuid.PcdPciExpNative|0|UINT8|0x40000005 +gBoardModuleTokenSpaceGuid.PcdNativeAspmEnable|1|UINT8|0x40000006 +gBoardModuleTokenSpaceGuid.PcdPs2KbMsEnable|0|UINT8|0x40000009 +gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A +gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000B +gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x4000000C + +# 0: Type-C +# 1: Stacked-Jack +gBoardModuleTokenSpaceGuid.PcdAudioConnector|0|UINT8|0x40000012 + +gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013 + +# gIntelPeiGraphicsVbtGuid =3D {0x4ad46122, 0xffeb, 0x4a52, {0xbf, 0xb0, = 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}} +gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0xe= b, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID*|= 0x40000014 +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +# +# The PCD which indicates the Memory Slot Population. +# +gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType|FALSE|BOOLEAN|0x= 00101027 +gBoardModuleTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate|0|UINT64|0x0000= 0010 + +# Board GPIO Table +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem|0|UINT32|0x0= 01000115 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize|0|UINT16= |0x001000116 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem|0|UINT32|0x= 001000117 +gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize|0|UINT1= 6|0x001000118 +gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio|0x0|UINT32|0x001002= 0C +gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity|0x0|UINT8|0x0010022E +gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio|0x0|UINT32|0x0010022F +gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio|0x0|UINT32|0x00100230 +gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable|FALSE|BOOLEAN|0x00100231 +gBoardModuleTokenSpaceGuid.PcdWlanWakeGpio|0x0|UINT32|0x00100234 +gBoardModuleTokenSpaceGuid.PcdWlanRootPortNumber|0x0|UINT8|0x00100235 +gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround|FALSE|BOOLEAN|0x00100236 + +# UCMC GPIO Table +gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable|0|UINT32|0x00100033 +gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize|0|UINT16|0x00100034 + +# PEG RESET GPIO +gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad|0|UINT32|0x00000074 +gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive|FALSE|BOOLEAN|0x00000075 +gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad|0|UINT32|0x00000105 +gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive|FALSE|BOOLEAN|0x00000106 + +# PCIE RTD3 GPIO +gBoardModuleTokenSpaceGuid.PcdRootPortDev|0xFF|UINT8|0x00000076 +gBoardModuleTokenSpaceGuid.PcdRootPortFunc|0xFF|UINT8|0x00000077 +gBoardModuleTokenSpaceGuid.PcdRootPortIndex|0xFF|UINT8|0x00000104 +gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport|0|UINT8|0x00000078 + +gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport|0|UINT8|0x00000080 +gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo|0|UINT32|0x00000081 +gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo|0|UINT8|0x00000082 +gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo|0|UINT32|0x00000083 +gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive|FALSE|BOOLEAN|0x00000084 +gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo|0|UINT8|0x00000085 +gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo|0|UINT32|0x00000086 +gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive|FALSE|BOOLEAN|0x00000087 + +gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport|0|UINT8|0x00000088 +gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo|0|UINT32|0x00000089 +gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo|0|UINT8|0x0000008A +gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo|0|UINT32|0x0000008B +gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive|FALSE|BOOLEAN|0x0000008C +gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo|0|UINT8|0x0000008D +gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo|0|UINT32|0x0000008E +gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive|FALSE|BOOLEAN|0x0000008F +gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport|0|UINT8|0x00000130 +gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo|0|UINT32|0x00000131 +gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo|0|UINT8|0x00000132 +gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo|0|UINT32|0x00000133 +gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive|FALSE|BOOLEAN|0x00000134 +gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo|0|UINT8|0x00000135 +gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo|0|UINT32|0x00000136 +gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive|FALSE|BOOLEAN|0x00000137 + +# Root Port Clock Info +gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E +gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F +gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0 +gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1 +gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2 +gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3 +gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4 +gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5 +gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6 +gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7 +gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8 +gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9 +gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA +gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB +gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC +gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD + +# GPIO Group Tier +gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0|0|UINT32|0x000000E9 +gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1|0|UINT32|0x000000EA +gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2|0|UINT32|0x000000EB + +# Board related PCH PmConfig +gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl|FALSE|BOOLEAN|0x000000= F6 +gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport|FALSE|BOOLEAN|0x000000F7 +gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport|FALSE|BOOLEAN|0x000000F8 + +# Misc +gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent|FALSE|BOOLEAN|0x000000ED +gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable|FALSE|BOOLEAN|0x000000EE +gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent|FALSE|BOOLEAN|0x000000EF +gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio|0|UINT64|0x000000F0 +gBoardModuleTokenSpaceGuid.PcdMobileDramPresent|FALSE|BOOLEAN|0x000000F1 +gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable|FALSE|BOOLEAN|0x000000F2 +gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable|FALSE|BOOLEAN|0x000000F9 +#gBoardModuleTokenSpaceGuid.PcdxxxNotInUse|FALSE|BOOLEAN|0x000000FC + +#PlatformInfoPcd +gBoardModuleTokenSpaceGuid.PcdEnableVoltageMargining|FALSE|BOOLEAN|0x00101= 000 +gBoardModuleTokenSpaceGuid.PcdGfxCrbDetect|FALSE|BOOLEAN|0x00101001 +gBoardModuleTokenSpaceGuid.PcdHsioBoardPresent|FALSE|BOOLEAN|0x00101002 +gBoardModuleTokenSpaceGuid.PcdHsioBoardType|0x0|UINT8|0x00101003 +gBoardModuleTokenSpaceGuid.PcdWakeupType|0x0|UINT8|0x00101004 +gBoardModuleTokenSpaceGuid.PcdMfgMode|FALSE|BOOLEAN|0x00101005 +gBoardModuleTokenSpaceGuid.PcdBoardName|L"0123456789ABCDEF0123456789ABCDEF= "|VOID*|0x00101007 +gBoardModuleTokenSpaceGuid.PcdEcMajorRevision|0x0|UINT8|0x00101008 +gBoardModuleTokenSpaceGuid.PcdEcMinorRevision|0x0|UINT8|0x00101009 +gBoardModuleTokenSpaceGuid.PcdBiosVersion|L"012345678901234567890123456789= 0123456789"|VOID*|0x0010100E +gBoardModuleTokenSpaceGuid.PcdReleaseDate|L"01234567890123456789"|VOID*|0x= 0010100F +gBoardModuleTokenSpaceGuid.PcdReleaseTime|L"01234567890123456789"|VOID*|0x= 00101010 +gBoardModuleTokenSpaceGuid.PcdPlatformGeneration|0x0|UINT8|0x00101011 +gBoardModuleTokenSpaceGuid.PcdSpdPresent|FALSE|BOOLEAN|0x00101012 +gBoardModuleTokenSpaceGuid.PcdDockAttached|FALSE|BOOLEAN|0x00101013 +gBoardModuleTokenSpaceGuid.PcdPlatformType|0x0|UINT8|0x00101014 +gBoardModuleTokenSpaceGuid.PcdPlatformFlavor|0x0|UINT8|0x00101015 +gBoardModuleTokenSpaceGuid.PcdBoardRev|0x0|UINT8|0x00101016 +gBoardModuleTokenSpaceGuid.PcdBoardBomId|0x0|UINT8|0x00101017 +gBoardModuleTokenSpaceGuid.PcdBoardId|0x0|UINT8|0x00101018 +gBoardModuleTokenSpaceGuid.PcdBoardType|0x0|UINT8|0x00101019 +gBoardModuleTokenSpaceGuid.PcdEcPresent|FALSE|BOOLEAN|0x0010101A + +# PCH Misc Configuration +gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable|FALSE|BOOLEAN|0x00000061 +gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable|FALSE|BOOLEAN|0x00000065 +gBoardModuleTokenSpaceGuid.PcdSmbiosFabBoardName|0|UINT64|0x00000102 +gBoardModuleTokenSpaceGuid.PcdSmbiosMainSlotEntry|0|UINT64|0x00000103 +gBoardModuleTokenSpaceGuid.PcdUsbcEcPdNegotiation|FALSE|BOOLEAN|0x00000110 + +# Control PCD to dump default silicon policy +gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy|FALSE|BOOLEAN|0x= 00010064 + +# Pch SerialIo I2c Pads Termination +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm|0x1|UINT8|0x0= 0000020 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm|0x1|UINT8|0x0= 0000021 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm|0x1|UINT8|0x0= 0000022 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm|0x1|UINT8|0x0= 0000023 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm|0x1|UINT8|0x0= 0000030 +gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm|0x1|UINT8|0x0= 0000031 +# +# The PCD which holds the pointer of Smbios Platform Info table +# +gBoardModuleTokenSpaceGuid.PcdSmbiosPlatformInfo|0|UINT64|0x0010101B +# +# The PCD which used to enable / disable the code to use RVP Smbios Board = Info +# +gBoardModuleTokenSpaceGuid.PcdSmbiosBoardInfoEnable|FALSE|BOOLEAN|0x001010= 1C +# +# The PCD which holds the pointer of RVP Smbios Board Info +# +gBoardModuleTokenSpaceGuid.PcdSmbiosBoardInfo|0|UINT64|0x0010101D +# +# CoEngineering Custom Defaults PCD +# +gBoardModuleTokenSpaceGuid.PcdCoEngEnableCustomDefaults|0x0|UINT8|0x001002= 27 +# +# The PCD which is defined to enable/disable the SMBus Alert function. +# +gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable|FALSE|BOOLEAN|0x0010101E +# +# The PCD which is defined to enable/disable the SATA LED function. +# +gBoardModuleTokenSpaceGuid.PcdSataLedEnable|FALSE|BOOLEAN|0x0010101F +# +# The PCD which is defined to enable/disable the VR Alert function. +# +gBoardModuleTokenSpaceGuid.PcdVrAlertEnable|FALSE|BOOLEAN|0x00101020 +# +# The PCD which is defined to enable/disable the PCH thermal hot threshold= function. +# +gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable|FALSE|BOOLEAN|0x00101021 +# +# The PCD which is defined to enable/disable the memory thermal sensor GPI= O C/D function. +# +gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable|TRUE|BO= OLEAN|0x00101022 +gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable|TRUE|BO= OLEAN|0x00101023 +# +# The PCD defines the I2C bus number to which PSS chip connected. +# +gBoardModuleTokenSpaceGuid.PcdPssReadSN|FALSE|BOOLEAN|0x00101024 +gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber|0x04|UINT8|0x00101025 +gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress|0x6E|UINT8|0x00101026 +# +# The PCD defines the USB port number to which BLE connected. +# +gBoardModuleTokenSpaceGuid.PcdBleUsbPortNumber |0x0|UI= NT8|0x00101028 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF3Support |0x00|U= INT8|0x00100113 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF4Support |0x00|U= INT8|0x00100114 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF5Support |0x00|U= INT8|0x00100115 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF6Support |0x00|U= INT8|0x00100116 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF7Support |0x00|U= INT8|0x00100117 +gBoardModuleTokenSpaceGuid.PcdEcHotKeyF8Support |0x00|U= INT8|0x00100118 +gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport |FALSE|= BOOLEAN|0x00100119 +gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport |FALSE|= BOOLEAN|0x0010011A +gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport |FALSE|= BOOLEAN|0x0010011B +gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport |FALSE|= BOOLEAN|0x0010011C +gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport |FALSE|= BOOLEAN|0x0010011D +gBoardModuleTokenSpaceGuid.PcdAcDcAutoSwitchSupport |FALSE|= BOOLEAN|0x0010011F +gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin |0x00|U= INT32|0x00100120 +gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport |FALSE|= BOOLEAN|0x00100121 +gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport |FALSE|= BOOLEAN|0x00100122 +gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature |FALSE|= BOOLEAN|0x00100123 +gBoardModuleTokenSpaceGuid.PcdBatteryPresent |0x0|UI= NT8|0x00100124 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCSupport|FALSE|BOOLEAN|0x00100212 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCEcLess|FALSE|BOOLEAN|0x00100213 +gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature|0x0|UINT64|0x00100204 +gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile|0x0|UINT8|0x00100205 +gBoardModuleTokenSpaceGuid.PcdFingerPrintSleepGpio|0x0|UINT32|0x00100209 +gBoardModuleTokenSpaceGuid.PcdFingerPrintIrqGpio|0x0|UINT32|0x0010020A +gBoardModuleTokenSpaceGuid.PcdGnssResetGpio|0x0|UINT32|0x0010020B +gBoardModuleTokenSpaceGuid.PcdTouchpadIrqGpio|0x0|UINT32|0x0010020F +gBoardModuleTokenSpaceGuid.PcdTouchpanelIrqGpio|0x0|UINT32|0x00100210 + +gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecIrqGpio |0x0|UI= NT32|0x00100126 +gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber |0x0|UI= NT8|0x00100127 +gBoardModuleTokenSpaceGuid.PcdEcSmiGpio|0x0|UINT32|0x00100200 +gBoardModuleTokenSpaceGuid.PcdEcLowPowerExitGpio |0x0|UI= NT32|0x00100125 +gBoardModuleTokenSpaceGuid.PcdHidI2cIntPad|0x0|UINT32|0x00100201 +gBoardModuleTokenSpaceGuid.PcdDetectPs2KbOnCmdAck|FALSE|BOOLEAN|0x00100202 +gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride|FALSE|BOOLEAN|0x00100203 +gBoardModuleTokenSpaceGuid.PcdDDISelection|0x0|UINT8|0x00100215 +gBoardModuleTokenSpaceGuid.PcdGfxCrbDetectGpio|0x0|UINT64|0x00100217 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1|0x00|UINT8|0x00100039 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1Pch|0x00|UINT8|0x0010003A +gBoardModuleTokenSpaceGuid.PcdUsbCPort1Proterties|0x00|UINT8|0x0010003B +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2|0x00|UINT8|0x0010003C +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2Pch|0x00|UINT8|0x0010003D +gBoardModuleTokenSpaceGuid.PcdUsbCPort2Proterties|0x00|UINT8|0x0010003E +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3|0x00|UINT8|0x0010003F +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3Pch|0x00|UINT8|0x00100040 +gBoardModuleTokenSpaceGuid.PcdUsbCPort3Proterties|0x00|UINT8|0x00100041 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4|0x00|UINT8|0x00100042 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4Pch|0x00|UINT8|0x00100043 +gBoardModuleTokenSpaceGuid.PcdUsbCPort4Proterties|0x00|UINT8|0x00100044 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5|0x00|UINT8|0x00100045 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5Pch|0x00|UINT8|0x00100046 +gBoardModuleTokenSpaceGuid.PcdUsbCPort5Proterties|0x00|UINT8|0x00100047 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6|0x00|UINT8|0x00100048 +gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6Pch|0x00|UINT8|0x00100049 +gBoardModuleTokenSpaceGuid.PcdUsbCPort6Proterties|0x00|UINT8|0x0010004A +gBoardModuleTokenSpaceGuid.PcdMipiCam0LinkUsed |0x0|UI= NT8|0x00100128 +gBoardModuleTokenSpaceGuid.PcdMipiCam1LinkUsed |0x0|UI= NT8|0x00100129 +gBoardModuleTokenSpaceGuid.PcdMipiCam2LinkUsed |0x0|UI= NT8|0x0010012A +gBoardModuleTokenSpaceGuid.PcdMipiCam3LinkUsed |0x0|UI= NT8|0x0010012B + +# Super IO Pcd +gPlatformModuleTokenSpaceGuid.PcdH8S2113Present|TRUE|BOOLEAN|0xF0000100 +gPlatformModuleTokenSpaceGuid.PcdNat87393Present|TRUE|BOOLEAN|0xF0000104 +gPlatformModuleTokenSpaceGuid.PcdNct677FPresent|TRUE|BOOLEAN|0xF0000105 +gBoardModuleTokenSpaceGuid.PcdConvertableDockSupport |FALSE|= BOOLEAN|0x00100112 +gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin |0x00|U= INT32|0x00100111 +gBoardModuleTokenSpaceGuid.PcdRealBattery1Control |0x00|U= INT8|0x00100103 +gBoardModuleTokenSpaceGuid.PcdRealBattery2Control |0x00|U= INT8|0x00100104 + +gBoardModuleTokenSpaceGuid.PcdDimmPopulationError|FALSE|BOOLEAN|0x00100221 +gBoardModuleTokenSpaceGuid.PcdBtIrqGpio|0x0|UINT32|0x0010020E +gBoardModuleTokenSpaceGuid.PcdBtRfKillGpio|0x0|UINT32|0x0010020D +gBoardModuleTokenSpaceGuid.PcdWhlErbRtd3TableEnable|FALSE|BOOLEAN|0x001002= 2C +gBoardModuleTokenSpaceGuid.PcdTypeCPortsSupported|0x00|UINT8|0x0010004B +gBoardModuleTokenSpaceGuid.PcdMipiCamSensor |FALSE|= BOOLEAN|0x00100105 +gBoardModuleTokenSpaceGuid.PcdH8S2113SIO |FALSE|= BOOLEAN|0x0010010A +gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM |FALSE|= BOOLEAN|0x00100107 +gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO |FALSE|= BOOLEAN|0x00100108 +gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON |FALSE|= BOOLEAN|0x00100109 + +[PcdsDynamicEx] + +[PcdsDynamic, PcdsDynamicEx] + +[PcdsPatchableInModule] + +[PcdsFeatureFlag] +gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|0xF0000062 +gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport |TRUE|BOOLEAN|0xF0000000 +gBoardModuleTokenSpaceGuid.PcdTbtEnable |FALSE|BOOLEAN|0x0000001= 15 + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/DxeCheckIommuSupportLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fe= atures/Tbt/Include/Library/DxeCheckIommuSupportLib.h new file mode 100644 index 0000000000..4aae18cac4 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/D= xeCheckIommuSupportLib.h @@ -0,0 +1,43 @@ +/** @file + Header file for the DxeCheckIommuSupport library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_ +#define _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_ + +/** + Detect ME FW and Board Type and return the result via IommuSkuCheck. + + IommuSkuCheck + BIT0: Indicate system has a Corporate CSME firmware + BIT1: Indicate BIOS is running on a WHL RVP + BIT2: Indicate BIOS is running on a CFL-H RVP + BIT3: Indicate BIOS is running on a CFL-S 8+2 RVP + + @retval Return 0 means not support, otherwise value is defined by IommuS= kuCheck +**/ +UINT8 +DetectMeAndBoard ( + VOID + ); + +/** + DxeCheckIommuSupport + + Only WHL/CFL-H/CFL-S 8+2 Crop SKUs support Iommu. + This function will save sku information to PcdIommuSkuCheck. + BIOS will use PcdIommuSkuCheck and other factors to set PcdVTdPolicyProp= ertyMask on the next boot in PEI phase + + This function might perform a system reset. +**/ +EFI_STATUS +EFIAPI +DxeCheckIommuSupport ( + VOID + ); +#endif // _DXE_CHECK_IOMMU_SUPPORT_LIBRARY_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/DxeTbtPolicyLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/T= bt/Include/Library/DxeTbtPolicyLib.h new file mode 100644 index 0000000000..167cc8af83 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/D= xeTbtPolicyLib.h @@ -0,0 +1,49 @@ +/** @file + Prototype of the DxeTbtPolicyLib library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_TBT_POLICY_LIB_H_ +#define _DXE_TBT_POLICY_LIB_H_ + + +/** + Install TBT Policy. + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +InstallTbtPolicy ( + IN EFI_HANDLE ImageHandle + ); + +/** + Update Tbt Policy Callback. + + @param[in] Event A pointer to the Event that triggered the callb= ack. + @param[in] Context A pointer to private data registered with the c= allback function. + +**/ +VOID +EFIAPI +UpdateTbtPolicyCallback ( + VOID + ); + +/** + Print DXE TBT Policy +**/ +VOID +TbtPrintDxePolicyConfig ( + VOID + ); +#endif // _DXE_TBT_POLICY_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/DxeTbtSecurityLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features= /Tbt/Include/Library/DxeTbtSecurityLib.h new file mode 100644 index 0000000000..17337ceb0b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/D= xeTbtSecurityLib.h @@ -0,0 +1,131 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_SECURITY_LIB_H_ +#define _TBT_SECURITY_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TBT_SECURITY_EVENT_STRING "DMA Protection Disabled" +#define TBT_SECURITY_EVENT_STRING_LEN (sizeof (TBT_SECURITY_EV= ENT_STRING) - 1) + +#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING "Security Level is Downg= raded to 0" +#define TBT_SECURITY_LEVEL_DOWNGRADED_STRING_LEN (sizeof (TBT_SECURITY_LE= VEL_DOWNGRADED_STRING) - 1) + +#define GET_TBT_SECURITY_MODE 0 +#define SET_TBT_SECURITY_MODE 1 + +typedef struct { + UINT8 EnableVtd; + BOOLEAN SLDowngrade; +} PCR7_DATA; + +/** + TBT Security ExtendPCR7 CallBackFunction + If the firmware/BIOS has an option to enable and disable DMA protections= via a VT-d switch in BIOS options, then the shipping configuration must be= with VT-d protection enabled. + On every boot where VT-d/DMA protection is disabled, or will be disabled= , or configured to a lower security state, and a platform has a TPM enabled= , then the platform SHALL extend an EV_EFI_ACTION event into PCR[7] before = enabling external DMA. + The event string SHALL be "DMA Protection Disabled". The platform firmwa= re MUST log this measurement in the event log using the string "DMA Protect= ion Disabled" for the Event Data. + Measure and log launch of TBT Security, and extend the measurement resul= t into a specific PCR. + Extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA. = The event string SHALL be "DMA Protection Disabled". The platform firmware = MUST log this measurement in the event log using the string "DMA Protection= Disabled" for the Event Data. + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +ExtendPCR7CallBackFunction ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + TBT Security DisableBme CallBackFunction + + BIOS will disable BME and tear down the Thunderbolt DMAR tables at ExitB= ootServices + in order to hand off security of TBT hierarchies to the OS. + The BIOS is expected to either: Disable BME from power on till the OS st= arts configuring the devices and enabling BME Enable BME only for devices t= hat can be protected by VT-d in preboot environment, + but disable BME and tear down any Thunderbolt DMAR tables at ExitBootSer= vices() + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +TbtDisableBmeCallBackFunction ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +/** + TBT Security SetDmarOptIn CallBackFunction + + A new security feature will be supported to protect against Physical DMA= attacks over Thunderbolt connects. + In order to do this, they need a new flag added to the DMAR tables that = a DMA is only permitted into RMRR at ExitBootServices(). With this flag av= ailable, OS can then Bug Check if any DMA is requested outside of the RMRR = before OS supported device drivers are started. + ReadyToBoot callback routine to update DMAR BIT2 + Bit definition: DMA_CONTROL_GUARANTEE + If Set, the platform supports blocking all DMA outside of the regions de= fined in the RMRR structures from ExitBootServices() until OS supported dev= ice drivers are started. + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +VOID +EFIAPI +SetDmarOptInCallBackFunction ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +/** + The function install DisableBme protocol for TBT Shell validation +**/ +VOID +InstallDisableBmeProtocol ( + VOID + ); + +/** + Get or set Thunderbolt(TM) security mode + + @param[in] DelayTime - The delay time after do ForcePwr + @param[in] SecurityMode - TBT Security Level + @param[in] Gpio3ForcePwrEn - Force GPIO to power on or not + @param[in] DTbtController - Enable/Disable DTbtController + @param[in] MaxControllerNumber - Number of contorller + @param[in] Action - 0 =3D get, 1 =3D set + + @retval - Return security level +**/ +UINT8 +EFIAPI +GetSetSecurityMode ( + IN UINTN DelayTime, + IN UINT8 SecurityMode, + IN UINT8 Gpio3ForcePwrEn, + IN UINT8 *DTbtController, + IN UINT8 MaxControllerNumber, + IN UINT8 Action +); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/PeiCheckIommuSupportLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fe= atures/Tbt/Include/Library/PeiCheckIommuSupportLib.h new file mode 100644 index 0000000000..9afb36f011 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/P= eiCheckIommuSupportLib.h @@ -0,0 +1,21 @@ +/** @file + Header file for the PeiCheckIommuSupport library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_ +#define _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_ + +/** + Check Iommu Ability base on SKU type, CSME FW type, Vtd and setup option= s. +**/ +VOID +PeiCheckIommuSupport ( + VOID + ); + +#endif // _PEI_CHECK_IOMMU_SUPPORT_LIBRARY_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/PeiTbtPolicyLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/T= bt/Include/Library/PeiTbtPolicyLib.h new file mode 100644 index 0000000000..45bd8f38ed --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/P= eiTbtPolicyLib.h @@ -0,0 +1,43 @@ +/** @file + Prototype of the PeiTbtPolicyLib library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_TBT_POLICY_LIB_H_ +#define _PEI_TBT_POLICY_LIB_H_ + +/** + Install Tbt Policy + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +InstallPeiTbtPolicy ( + VOID + ); + +/** + Update PEI TBT Policy Callback +**/ +VOID +EFIAPI +UpdatePeiTbtPolicyCallback ( + VOID + ); + +/** + Print PEI TBT Policy +**/ +VOID +EFIAPI +TbtPrintPeiPolicyConfig ( + VOID + ); +#endif // _DXE_TBT_POLICY_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/PeiTbtTaskDispatchLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Feat= ures/Tbt/Include/Library/PeiTbtTaskDispatchLib.h new file mode 100644 index 0000000000..44ae01a3f7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/P= eiTbtTaskDispatchLib.h @@ -0,0 +1,61 @@ +/** @file + PEI TBT Task Dispatch library Header file + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PEI_TBT_TASK_DISPATCH_LIB_H__ +#define __PEI_TBT_TASK_DISPATCH_LIB_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef +EFI_STATUS +(EFIAPI *TBT_TASK) ( + PEI_TBT_POLICY *PeiTbtConfig +); + +typedef enum { + TBT_NULL, ///< All policy flags turned off. + TBT_NORMAL =3D (1 << 0), ///< Execute TBT function on cold reset. + TBT_S3 =3D (1 << 1), ///< Execute TBT function on S3 exit. + TBT_S4 =3D (1 << 2), ///< Execute TBT function on S4 exit. + TBT_ALL =3D MAX_UINTN ///< Execute TBT function always. +} TBT_BOOT_MODE; + +typedef struct { + TBT_TASK TbtTask; ///< Ptr to function to execute, with par= ameter list. + TBT_BOOT_MODE TbtBootModeFlag; ///< Call table base on TbtBootModeFlag + CHAR8 *String; ///< Output string describing this task. +} TBT_CALL_TABLE_ENTRY; + +/** + Covert the current EFI_BOOT_MODE to TBT_BOOT_MODE +**/ +TBT_BOOT_MODE +TbtGetBootMode ( + VOID +); + +/** + TbtTaskDistpach: Dispatch the TBT tasks according to TBT_CALL_TABLE_ENTRY + + @param[in] TBT_CALL_TABLE_ENTRY TbtCallTable + +**/ +VOID +TbtTaskDistpach ( + IN TBT_CALL_TABLE_ENTRY *TbtCallTable +); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Li= brary/TbtCommonLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/= Include/Library/TbtCommonLib.h new file mode 100644 index 0000000000..3e9e7c4b76 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Library/T= btCommonLib.h @@ -0,0 +1,261 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_COMMON_LIB_H_ +#define _TBT_COMMON_LIB_H_ + +#include +#include + +#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_RP 0 // @todo : Update when on= ce finalized +#define DEFAULT_PCI_BUS_NUMBER_ITBT_RP 0 +#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_RP 0x07 + +#define DEFAULT_PCI_SEGMENT_NUMBER_ITBT_DMA0 0 +#define DEFAULT_PCI_BUS_NUMBER_ITBT_DMA0 0 +#define DEFAULT_PCI_DEVICE_NUMBER_ITBT_DMA0 0x0D +#define DEFAULT_PCI_FUNCTION_NUMBER_ITBT_DMA0 0x02 + +#define DTBT_CONTROLLER 0x00 +#define DTBT_TYPE_PCH 0x01 +#define DTBT_TYPE_PEG 0x02 +#define ITBT_CONTROLLER 0x80 +#define TBT2PCIE_ITBT_R 0xEC +#define PCIE2TBT_ITBT_R 0xF0 +#define TBT2PCIE_DTBT_R 0x548 +#define PCIE2TBT_DTBT_R 0x54C + +#define INVALID_RP_CONTROLLER_TYPE 0xFF + +// +// Thunderbolt FW OS capability +// +#define NO_OS_NATIVE_SUPPORT 0 +#define OS_NATIVE_SUPPORT_ONLY 1 +#define OS_NATIVE_SUPPORT_RTD3 2 + +#define ITBT_SAVE_STATE_OFFSET BIT4 // Bits 4-7 is for ITBT (HIA0/1/2/Res= erved) +#define DTBT_SAVE_STATE_OFFSET BIT0 // Bits 0-3 is for DTBT (only bit 0 i= s in use) +/** +Get Tbt2Pcie Register Offset + +@param[in] Type ITBT (0x80) or DTBT (0x00) +@retval Register Register Variable +**/ + +#define GET_TBT2PCIE_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function= , RegisterAddress) \ + if (Type =3D=3D ITBT_CONTROLLER) { \ + RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func= tion, TBT2PCIE_ITBT_R); \ + } else { \ + RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func= tion, TBT2PCIE_DTBT_R); \ + } + +/** +Get Pcie2Tbt Register Offset + +@param[in] Type ITBT (0x80) or DTBT (0x00) +@retval Register Register Variable +**/ + +#define GET_PCIE2TBT_REGISTER_ADDRESS(Type, Segment, Bus, Device, Function= , RegisterAddress) \ + if (Type =3D=3D ITBT_CONTROLLER) { \ + RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func= tion, PCIE2TBT_ITBT_R); \ + } else { \ + RegisterAddress =3D PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Device, Func= tion, PCIE2TBT_DTBT_R); \ + } + +#define PCIE2TBT_VLD_B BIT0 +#define TBT2PCIE_DON_R BIT0 +#define TBT_MAIL_BOX_DELAY (100*1000) +#define TBT_5S_TIMEOUT 50 +#define TBT_1S_TIMEOUT 10 +#define TBT_3S_TIMEOUT 30 + +#define PCIE2TBT_GO2SX (0x02 << 1) +#define PCIE2TBT_GO2SX_NO_WAKE (0x03 << 1) +#define PCIE2TBT_SX_EXIT_TBT_CONNECTED (0x04 << 1) +#define PCIE2TBT_SX_EXIT_NO_TBT_CONNECTED (0x05 << 1) +#define PCIE2TBT_OS_UP (0x06 << 1) +#define PCIE2TBT_SET_SECURITY_LEVEL (0x08 << 1) +#define PCIE2TBT_GET_SECURITY_LEVEL (0x09 << 1) +#define PCIE2TBT_CM_AUTH_MODE_ENTER (0x10 << 1) +#define PCIE2TBT_CM_AUTH_MODE_EXIT (0x11 << 1) +#define PCIE2TBT_BOOT_ON (0x18 << 1) +#define PCIE2TBT_BOOT_OFF (0x19 << 1) +#define PCIE2TBT_USB_ON (0x19 << 1) +#define PCIE2TBT_GET_ENUMERATION_METHOD (0x1A << 1) +#define PCIE2TBT_SET_ENUMERATION_METHOD (0x1B << 1) +#define PCIE2TBT_POWER_CYCLE (0x1C << 1) +#define PCIE2TBT_PREBOOTACL (0x1E << 1) +#define CONNECT_TOPOLOGY_COMMAND (0x1F << 1) + +#define RESET_HR_BIT BIT0 +#define ENUMERATE_HR_BIT BIT1 +#ifndef AUTO +#define AUTO 0x0 +#endif + +// +//Thunder Bolt Device IDs +// + +// +// Alpine Ridge HR device IDs +// +#define AR_HR_2C 0x1576 +#define AR_HR_4C 0x1578 +#define AR_XHC 0x15B5 +#define AR_XHC_4C 0x15B6 +#define AR_HR_LP 0x15C0 +// +// Alpine Ridge C0 HR device IDs +// +#define AR_HR_C0_2C 0x15DA +#define AR_HR_C0_4C 0x15D3 +// +// Titan Ridge HR device IDs +// +#define TR_HR_2C 0x15E7 +#define TR_HR_4C 0x15EA +// +//End of Thunderbolt(TM) Device IDs +// + +typedef struct _DEV_ID { + UINT8 Segment; + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; +} DEV_ID; + +//@todo Seems to only be used by Platform/TBT/Smm/TbtSmm.inf +//@todo should refactor this to only be present in that driver +//@todo also definitions like this should never be in a .h file anyway +//@todo this is a quick hack to get things compiling for now +#ifdef __GNUC__ +#pragma GCC diagnostic warning "-Wunused-variable" +#endif + +/** +Based on the Security Mode Selection, BIOS drives FORCE_PWR. + +@param[in] GpioNumber +@param[in] Value +**/ +VOID +ForceDtbtPower( + IN UINT32 GpioNumber, + IN BOOLEAN Value +); + +/** + Get Security Level. + @param[in] Type ITBT (0x80) or DTBT (0x00) + @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT) + @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT) + @param[in] Function Function number for HIA (ITBT) or Host Router (DTB= T) + @param[in] Timeout Time out with 100 ms garnularity +**/ +UINT8 +GetSecLevel ( + IN BOOLEAN Type, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 Command, + IN UINT32 Timeout + ); + +/** + Set Security Level. + @param[in] Data Security State + @param[in] Type ITBT (0x80) or DTBT (0x00) + @param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT) + @param[in] Device Device number for HIA (ITBT) or Host Router (DTBT) + @param[in] Function Function number for HIA (ITBT) or Host Router (DTB= T) + @param[in] Timeout Time out with 100 ms garnularity +**/ +BOOLEAN +SetSecLevel ( + IN UINT8 Data, + IN BOOLEAN Type, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 Command, + IN UINT32 Timeout + ); + +/** +Execute TBT Mail Box Command + +@param[in] Command TBT Command +@param[in] Type ITBT (0x80) or DTBT (0x00) +@param[in] Bus Bus number for HIA (ITBT) or Host Router (DTBT) +@param[in] Device Device number for HIA (ITBT) or Host Router (DTBT) +@param[in] Function Function number for HIA (ITBT) or Host Router (DTBT) +@param[in] Timeout Time out with 100 ms garnularity +@Retval true if command executes succesfully +**/ +BOOLEAN +TbtSetPcie2TbtCommand( + IN UINT8 Command, + IN BOOLEAN Type, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT32 Timeout +); +/** + Check connected TBT controller is supported or not by DeviceID + + @param[in] DeviceID DeviceID of of TBT controller + + + @retval TRUE Valid DeviceID + @retval FALSE Invalid DeviceID +**/ + +BOOLEAN +IsTbtHostRouter ( + IN UINT16 DeviceID + ); + +/** + Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Po= rt physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device = number. + @param[out] RpFun Return corresponding root port functio= n number. + + @retval EFI_SUCCESS Root port device and function is retri= eved +**/ +EFI_STATUS +EFIAPI +GetDTbtRpDevFun( + IN BOOLEAN Type, + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFunc + ); + +/** + Internal function to Wait for Tbt2PcieDone Bit.to Set or clear + @param[in] CommandOffsetAddress Tbt2Pcie Register Address + @param[in] TimeOut Time out with 100 ms garnularity + @param[in] Tbt2PcieDone Wait condition (wait for Bit to Cl= ear/Set) + @param[out] *Tbt2PcieValue Function Register value +**/ +BOOLEAN +InternalWaitforCommandCompletion ( + IN UINT64 CommandOffsetAddress, + IN UINT32 TimeOut, + IN BOOLEAN Tbt2PcieDone, + OUT UINT32 *Tbt2PcieValue + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pp= i/PeiTbtPolicy.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Incl= ude/Ppi/PeiTbtPolicy.h new file mode 100644 index 0000000000..17d8a62f66 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Ppi/PeiTb= tPolicy.h @@ -0,0 +1,31 @@ +/** @file +TBT PEI Policy + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_TBT_POLICY_H_ +#define _PEI_TBT_POLICY_H_ + +#include + +#pragma pack(push, 1) + +#define PEI_TBT_POLICY_REVISION 1 + +/** + TBT PEI configuration\n + Revision 1: + - Initial version. +**/ +typedef struct _PEI_TBT_POLICY { + DTBT_COMMON_CONFIG DTbtCommonConfig; = ///< dTbt Common Configuration + DTBT_CONTROLLER_CONFIG DTbtControllerConfig [MAX_DTBT_CONTROLLER_NUMBER]= ; ///< dTbt Controller Configuration +} PEI_TBT_POLICY; + +#pragma pack(pop) + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= ivate/Library/PeiDTbtInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fea= tures/Tbt/Include/Private/Library/PeiDTbtInitLib.h new file mode 100644 index 0000000000..bb30c2c0ec --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Private/L= ibrary/PeiDTbtInitLib.h @@ -0,0 +1,130 @@ +/** @file + PEI DTBT Init Dispatch library Header file + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PEI_DTBT_INIT_LIB_H__ +#define __PEI_DTBT_INIT_LIB_H__ + +#include +#include + +extern TBT_CALL_TABLE_ENTRY DTbtCallTable[]; + +/** + Get Thunderbolt(TM) (TBT) PEI Policy Data. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtGetPeiTbtPolicyData ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Toggle related GPIO pin for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtToggleGPIO ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + set tPCH25 Timing to 10 ms for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtSetTPch25Timing ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Do ForcePower for DTBT Controller + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtForcePower ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Clear VGA Registers for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtClearVgaRegisters ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Exectue Mail box command "Boot On". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtBootOn ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Exectue Mail box command "USB On". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtUsbOn ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +/** + Exectue Mail box command "Sx Exit". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtSxExitFlow ( + IN PEI_TBT_POLICY *PeiTbtConfig +); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= ivate/Library/PeiTbtCommonInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPk= g/Features/Tbt/Include/Private/Library/PeiTbtCommonInitLib.h new file mode 100644 index 0000000000..0ed13fd300 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Private/L= ibrary/PeiTbtCommonInitLib.h @@ -0,0 +1,51 @@ +/** @file + PEI TBT Common Init Dispatch library Header file + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __PEI_TBT_COMMON_INIT_LIB_H__ +#define __PEI_TBT_COMMON_INIT_LIB_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +BOOLEAN +IsHostRouterPresentBeforeSleep( +IN UINT8 ControllerType, +IN UINT8 Controller +); + +VOID +TbtSetSxMode( +IN BOOLEAN Type, +IN UINT8 Bus, +IN UINT8 Device, +IN UINT8 Function, +IN UINT8 TbtBootOn +); + +VOID +TbtClearVgaRegisters( +IN UINTN Segment, +IN UINTN Bus, +IN UINTN Device, +IN UINTN Function +); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= otocol/DisableBmeProtocol.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Featur= es/Tbt/Include/Protocol/DisableBmeProtocol.h new file mode 100644 index 0000000000..1948c252f0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/= DisableBmeProtocol.h @@ -0,0 +1,36 @@ +/** @file + Definitions for DisableBmeProtocol + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DISABLE_TBT_BME_PROTOCOL_H_ +#define _DISABLE_TBT_BME_PROTOCOL_H_ + +typedef struct EFI_DISABLE_BME_PROTOCOL EFI_DISABLE_TBT_BME_PROTOCOL; + +/** + This is for disable TBT BME bit under shell environment + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. +**/ +typedef +VOID +(EFIAPI *DISABLE_BUS_MASTER_ENABLE) ( + IN EFI_EVENT Event, + IN VOID *Context + ); + + +struct EFI_DISABLE_BME_PROTOCOL { + DISABLE_BUS_MASTER_ENABLE DisableBme; +}; + +extern EFI_GUID gDxeDisableTbtBmeProtocolGuid; + + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= otocol/DxeTbtPolicy.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt= /Include/Protocol/DxeTbtPolicy.h new file mode 100644 index 0000000000..437f6a8401 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/= DxeTbtPolicy.h @@ -0,0 +1,137 @@ +/** @file +TBT DXE Policy + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_TBT_POLICY_H_ +#define _DXE_TBT_POLICY_H_ + +#include + +#pragma pack(push, 1) + +#define DXE_TBT_POLICY_REVISION 1 + +// +// TBT Common Data Structure +// +typedef struct _TBT_COMMON_CONFIG{ + /** + TBT Security Level + 0: SL0 No Security, 1: SL1 User Authorization, 2: SL2 Secure Co= nnect, 3: SL3 Display Port and USB + **/ + UINT32 SecurityMode : 3; + /** + BIOS W/A for Hot plug of 12V USB devices cause electrical noise on PCH= GPIOs + 0: Disabled, 1: Enabled + **/ + UINT32 Gpio5Filter : 1; + /** + WA for TR A0 OS_UP Command, it is only needed for TR A0 stepping + 0: Disabled, 1: Enabled + **/ + UINT32 TrA0OsupWa : 1; + /** + Send Go2SxNoWake or GoSxWake according to TbtWakeupSupport + 0: Disabled, 1: Enabled + **/ + UINT32 TbtWakeupSupport : 1; + /** + SMI TBT enumeration + 0: Disabled, 1: Enabled + **/ + UINT32 TbtHotSMI : 1; + /** + Notify PCIe RP after Hot-Plug/Hot-Unplug occurred. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtHotNotify : 1; + /** + CLK REQ for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtSetClkReq : 1; + /** + ASPM setting for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: L0s, 2: L1, 3: L0sL1 + **/ + UINT32 TbtAspm : 2; + /** + L1 SubState for for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: L1.1, 2: L1.1 & L1.2 + **/ + UINT32 TbtL1SubStates : 2; + /** + LTR for for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtLtr : 1; + /** + PTM for for all the PCIe device in TBT daisy chain. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtPtm : 1; + /** + TBT Dynamic AC/DC L1. + 0: Disabled, 1: Enabled + **/ + UINT32 TbtAcDcSwitch : 1; + /** + TBT RTD3 Support. + 0: Disabled, 1: Enabled + **/ + UINT32 Rtd3Tbt : 1; + /** + TBT ClkReq for RTD3 Flow. + 0: Disabled, 1: Enabled + **/ + UINT32 Rtd3TbtClkReq : 1; + /** + TBT Win10support for Tbt FW execution mode. + 0: Disabled, 1: Native, 2: Native + RTD3 + **/ + UINT32 Win10Support : 2; + /** + TbtVtdBaseSecurity + 0: Disabled, 1: Enabled + **/ + UINT32 TbtVtdBaseSecurity: 1; + /** + Control Iommu behavior in pre-boot + 0: Disabled Iommu, 1: Enable Iommu, Disable exception list, 2: = Enable Iommu, Enable exception list + **/ + UINT32 ControlIommu : 3; + UINT32 Rsvd0 : 8; ///< Reserved bits + UINT16 Rtd3TbtClkReqDelay; + UINT16 Rtd3TbtOffDelay; +} TBT_COMMON_CONFIG; + +// +// dTBT Resource Data Structure +// +typedef struct _DTBT_RESOURCE_CONFIG{ + UINT8 DTbtPcieExtraBusRsvd; ///< Preserve Bus resource for PCIe RP = that connect to dTBT Host Router + UINT16 DTbtPcieMemRsvd; ///< Preserve MEM resource for PCIe RP = that connect to dTBT Host Router + UINT8 DTbtPcieMemAddrRngMax; ///< Alignment of Preserve MEM resource= for PCIe RP that connect to dTBT Host Router + UINT16 DTbtPciePMemRsvd; ///< Preserve PMEM resource for PCIe RP= that connect to dTBT Host Router + UINT8 DTbtPciePMemAddrRngMax; ///< Alignment of Preserve PMEM resourc= e for PCIe RP that connect to dTBT Host Router + UINT8 Reserved[1]; ///< Reserved for DWORD alignment +} DTBT_RESOURCE_CONFIG; + +/** + TBT DXE configuration\n + Revision 1: + - Initial version. +**/ +typedef struct _DXE_TBT_POLICY_PROTOCOL { + TBT_COMMON_CONFIG TbtCommonConfig; = ///< Tbt Common Information + DTBT_RESOURCE_CONFIG DTbtResourceConfig[MAX_DTBT_CONTROLLER_NUMBER]; = ///< dTbt Resource Configuration +} DXE_TBT_POLICY_PROTOCOL; + +#pragma pack(pop) + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Pr= otocol/TbtNvsArea.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/I= nclude/Protocol/TbtNvsArea.h new file mode 100644 index 0000000000..e6654b4094 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Protocol/= TbtNvsArea.h @@ -0,0 +1,50 @@ +/** @file + This file defines the TBT NVS Area Protocol. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_NVS_AREA_H_ +#define _TBT_NVS_AREA_H_ + +// +// Platform NVS Area definition +// +#include + +// +// Includes +// +#define TBT_NVS_DEVICE_ENABLE 1 +#define TBT_NVS_DEVICE_DISABLE 0 + +// +// Forward reference for pure ANSI compatibility +// +typedef struct _TBT_NVS_AREA_PROTOCOL TBT_NVS_AREA_PROTOCOL; + +/// +/// Extern the GUID for protocol users. +/// +extern EFI_GUID gTbtNvsAreaProtocolGuid; + +/** + Making any TBT_NVS_AREA structure change after code frozen + will need to maintain backward compatibility, bump up + structure revision and update below history table\n + Revision 1: - Initial version.\n + Revision 2: - Adding TBT NVS AREA Revision, Deprecated DTbtCont= rollerEn0, DTbtControllerEn1.\n +**/ +#define TBT_NVS_AREA_REVISION 2 + +// +// Platform NVS Area Protocol +// +typedef struct _TBT_NVS_AREA_PROTOCOL { + TBT_NVS_AREA *Area; +} TBT_NVS_AREA_PROTOCOL; + +#endif // _TBT_NVS_AREA_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Tb= tBoardInfo.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/= TbtBoardInfo.h new file mode 100644 index 0000000000..bd5e577fbe --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtBoardI= nfo.h @@ -0,0 +1,23 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_INFO_GUID_H_ +#define _TBT_INFO_GUID_H_ +#include + +#pragma pack(1) +// +// TBT Info HOB +// +typedef struct _TBT_INFO_HOB { + EFI_HOB_GUID_TYPE EfiHobGuidType; + DTBT_COMMON_CONFIG DTbtCommonConfig; = ///< dTbt Common Configuration + DTBT_CONTROLLER_CONFIG DTbtControllerConfig [MAX_DTBT_CONTROLLER_NUMBER]= ; ///< dTbt Controller Configuration +} TBT_INFO_HOB; +#pragma pack() + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Tb= tNvsAreaDef.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include= /TbtNvsAreaDef.h new file mode 100644 index 0000000000..21e17b4609 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtNvsAre= aDef.h @@ -0,0 +1,68 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // + // Define TBT NVS Area operation region. + // + +#ifndef _TBT_NVS_AREA_DEF_H_ +#define _TBT_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + UINT8 ThunderboltSmiFunction; ///< Offset 0 Th= underbolt(TM) SMI Function Number + UINT8 ThunderboltHotSmi; ///< Offset 1 SM= I on Hot Plug for TBT devices + UINT8 TbtWin10Support; ///< Offset 2 Tb= tWin10Support + UINT8 TbtGpioFilter; ///< Offset 3 Gp= io filter to detect USB Hotplug event + UINT8 ThunderboltHotNotify; ///< Offset 4 No= tify on Hot Plug for TBT devices + UINT8 TbtSelector; ///< Offset 5 Th= underbolt(TM) Root port selector + UINT8 WAKFinished; ///< Offset 6 WA= K Finished + UINT8 DiscreteTbtSupport; ///< Offset 7 Th= underbolt(TM) support + UINT8 TbtAcpiRemovalSupport; ///< Offset 8 Tb= tAcpiRemovalSupport + UINT32 TbtFrcPwrEn; ///< Offset 9 Tb= tFrcPwrEn + UINT32 TbtFrcPwrGpioNo0; ///< Offset 13 Tb= tFrcPwrGpioNo + UINT8 TbtFrcPwrGpioLevel0; ///< Offset 17 Tb= tFrcPwrGpioLevel + UINT32 TbtCioPlugEventGpioNo0; ///< Offset 18 Tb= tCioPlugEventGpioNo + UINT32 TbtPcieRstGpioNo0; ///< Offset 22 Tb= tPcieRstGpioNo + UINT8 TbtPcieRstGpioLevel0; ///< Offset 26 Tb= tPcieRstGpioLevel + UINT8 CurrentDiscreteTbtRootPort; ///< Offset 27 Cu= rrent Port that has plug event + UINT8 RootportSelected0; ///< Offset 28 Ro= ot port Selected by the User + UINT8 RootportSelected0Type; ///< Offset 29 Ro= ot port Type + UINT8 RootportSelected1; ///< Offset 30 Ro= ot port Selected by the User + UINT8 RootportSelected1Type; ///< Offset 31 Ro= ot port Type + UINT8 RootportEnabled0; ///< Offset 32 Ro= ot port Enabled by the User + UINT8 RootportEnabled1; ///< Offset 33 Ro= ot port Enabled by the User + UINT32 TbtFrcPwrGpioNo1; ///< Offset 34 Tb= tFrcPwrGpioNo + UINT8 TbtFrcPwrGpioLevel1; ///< Offset 38 Tb= tFrcPwrGpioLevel + UINT32 TbtCioPlugEventGpioNo1; ///< Offset 39 Tb= tCioPlugEventGpioNo + UINT32 TbtPcieRstGpioNo1; ///< Offset 43 Tb= tPcieRstGpioNo + UINT8 TbtPcieRstGpioLevel1; ///< Offset 47 Tb= tPcieRstGpioLevel + UINT8 TBtCommonGpioSupport; ///< Offset 48 Se= t if Single GPIO is used for Multi/Different Controller Hot plug support + UINT8 CurrentDiscreteTbtRootPortType; ///< Offset 49 Ro= ot Port type for which SCI Triggered + UINT8 TrOsup; ///< Offset 50 Ti= tan Ridge Osup command + UINT8 TbtAcDcSwitch; ///< Offset 51 TB= T Dynamic AcDc L1 + UINT8 DTbtControllerEn0; ///< Offset 52 DT= btController0 is enabled or not. @deprecated since revision 2 + UINT8 DTbtControllerEn1; ///< Offset 53 DT= btController1 is enabled or not. @deprecated since revision 2 + UINT8 TbtAspm; ///< Offset 54 AS= PM setting for all the PCIe device in TBT daisy chain. + UINT8 TbtL1SubStates; ///< Offset 55 L1= SubState for for all the PCIe device in TBT daisy chain. + UINT8 TbtSetClkReq; ///< Offset 56 CL= K REQ for all the PCIe device in TBT daisy chain. + UINT8 TbtLtr; ///< Offset 57 LT= R for for all the PCIe device in TBT daisy chain. + UINT8 TbtPtm; ///< Offset 58 PT= M for for all the PCIe device in TBT daisy chain. + UINT8 TbtWakeupSupport; ///< Offset 59 Se= nd Go2SxNoWake or GoSxWake according to TbtWakeupSupport + UINT16 Rtd3TbtOffDelay; ///< Offset 60 Rt= d3TbtOffDelay TBT RTD3 Off Delay + UINT8 TbtSxWakeSwitchLogicEnable; ///< Offset 62 Tb= tSxWakeSwitchLogicEnable Set True if TBT_WAKE_N will be routed to PCH WakeB= at Sx entry point. HW logic is required. + UINT8 Rtd3TbtSupport; ///< Offset 63 En= able Rtd3 support for TBT. Corresponding to Rtd3Tbt in Setup. + UINT8 Rtd3TbtClkReq; ///< Offset 64 En= able TBT RTD3 CLKREQ mask. + UINT16 Rtd3TbtClkReqDelay; ///< Offset 65 TB= T RTD3 CLKREQ mask delay. + // + // Revision Field: + // + UINT8 TbtRevision; ///< Offset 67 Re= vison of TbtNvsArea +} TBT_NVS_AREA; + +#pragma pack(pop) +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/Tb= tPolicyCommonDefinition.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features= /Tbt/Include/TbtPolicyCommonDefinition.h new file mode 100644 index 0000000000..7771fc7a95 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Include/TbtPolicy= CommonDefinition.h @@ -0,0 +1,84 @@ +/** @file +TBT Policy Common definition. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_POLICY_COMMON_H_ +#define _TBT_POLICY_COMMON_H_ + +#include +#include + +#define MAX_DTBT_CONTROLLER_NUMBER 2 + +#define TYPE_PCIE 0x01 +#define TYPE_PEG 0x02 + +#pragma pack(push, 1) + +// +// dTBT Force Power GPIO Data Structure +// +typedef struct _DTBT_FORCE_POWER_GPIO_CONFIG { + GPIO_PAD GpioPad; ///< GPIO Pad Number + BOOLEAN GpioLevel; ///< 0 =3D Active Low; 1 =3D Act= ive High + UINT8 Reserved[3]; ///< Reserved for DWORD alignment +} DTBT_FORCE_POWER_GPIO_CONFIG; + +// +// dTBT CIO Plug Event GPIO Data Structure +// +typedef struct _DTBT_CIO_PLUG_EVENT_GPIO_CONFIG { + GPIO_PAD GpioPad; ///< GPIO Pad Number + UINT32 AcpiGpeSignature; ///< AcpiPlatform driver will ch= ange the XTBT method to the _Lxx or _Exx that we assign in this item. + BOOLEAN AcpiGpeSignaturePorting; ///< 0 =3D No porting required(f= or 2-tier GPI GPE event architecture), 1 =3D Porting required(for 1-tier GP= I GPE event architecture) + UINT8 Reserved[3]; ///< Reserved for DWORD alignment +} DTBT_CIO_PLUG_EVENT_GPIO_CONFIG; + +// +// dTBT PCIE Reset GPIO Data Structure +// +typedef struct _DTBT_PCIE_RESET_GPIO_CONFIG { + GPIO_PAD GpioPad; ///< GPIO Pad Number + BOOLEAN GpioLevel; ///< 0 =3D Active Low; 1 =3D Act= ive High + UINT8 Reserved[3]; ///< Reserved for DWORD alignment +} DTBT_PCIE_RESET_GPIO_CONFIG; + +// +// dTBT Controller Data Structure +// +typedef struct _DTBT_CONTROLLER_CONFIG { + UINT8 DTbtControllerEn; ///< Enable/Disable DT= btController. + UINT8 Type; ///< 01-Pcie RP, 02- P= EG,Reserved. + UINT8 PcieRpNumber; ///< RP Number/ PEG Po= rt (0,1,2) that connecet to dTBT controller. + DTBT_FORCE_POWER_GPIO_CONFIG ForcePwrGpio; ///< The GPIO pin that= can force dTBT Power On. + DTBT_CIO_PLUG_EVENT_GPIO_CONFIG CioPlugEventGpio; ///< The GPIO pin that= can generate Hot-Plug event. + DTBT_PCIE_RESET_GPIO_CONFIG PcieRstGpio; ///< The GPIO pin that= is use to perform Reset when platform enters to Sx, it is required for pla= tforms where PCI_RST pin connected to Tbt is controlled with GPIO + GPIO_PAD PdResetGpioPad; ///< PD HRESET GPIO Pa= d Number + GPIO_PAD PdSxEntryGpioPad; ///< PD SX Entry GPIO = Pad Number + GPIO_PAD PdSxAckGpioPad; ///< PD SX Ack GPIO Pa= d Number + UINT8 Reserved[1]; ///< Reserved for DWOR= D alignment +} DTBT_CONTROLLER_CONFIG; + +// +// dTBT Controller Data Structure +// +typedef struct _DTBT_COMMON_CONFIG { + UINT8 TbtBootOn; ///< Send BootOn Mailbox = command when TbtBootOn is enabled. + UINT8 TbtUsbOn; ///< Send UsbOn Mailbox c= ommand when TbtBootOn is enabled. + UINT8 Gpio3ForcePwr; ///< Force GPIO to power = on or not + UINT16 Gpio3ForcePwrDly; ///< The delay time after= do ForcePwr + BOOLEAN DTbtSharedGpioConfiguration; ///< Multiple DTBT contro= llers share the same GPIO pin + BOOLEAN PcieRstSupport; ///< 0 =3D Not Support, 1= =3D Supported. it is required for platforms where PCI_RST pin connected to= Tbt is controlled with GPIO + UINT8 SecurityMode; ///< 0: SL0 No Security, = 1: SL1 User Authorization, 2: SL2 Secure Connect, 3: SL3 Display Port and U= SB + UINT8 ControlIommu; ///< Control Iommu behavi= or in pre-boot, 0: Disabled Iommu, 1: Enable Iommu, Disable exception list,= 2: Enable Iommu, Enable exception list + UINT8 Reserved[3]; ///< Reserved for DWORD a= lignment +} DTBT_COMMON_CONFIG; + +#pragma pack(pop) + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvsA= reaDef.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvsAre= aDef.h new file mode 100644 index 0000000000..d8021e8c22 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvsAreaDef.h @@ -0,0 +1,118 @@ +/** @file + ACPI DSDT table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + + +#ifndef _GLOBAL_NVS_AREA_DEF_H_ +#define _GLOBAL_NVS_AREA_DEF_H_ + +#pragma pack (push,1) +typedef struct { + // + // Miscellaneous Dynamic Registers: + // + UINT16 OperatingSystem; ///< Offset 0 Op= erating System + UINT8 SmiFunction; ///< Offset 2 SM= I Function Call (ASL to SMI via I/O Trap) + UINT32 Port80DebugValue; ///< Offset 3 Po= rt 80 Debug Port Value + UINT8 PowerState; ///< Offset 7 Po= wer State (AC Mode =3D 1) + // + // Thermal Policy Registers: + // + UINT8 EnableDigitalThermalSensor; ///< Offset 8 Di= gital Thermal Sensor Enable + UINT8 DigitalThermalSensorSmiFunction; ///< Offset 9 DT= S SMI Function Call + // + // CPU Identification Registers: + // + UINT8 ApicEnable; ///< Offset 10 AP= IC Enabled by SBIOS (APIC Enabled =3D 1) + UINT8 ThreadCount; ///< Offset 11 Nu= mber of Enabled Threads + // + // PCIe Hot Plug + // + UINT8 PcieOSCControl; ///< Offset 12 PC= IE OSC Control + UINT8 NativePCIESupport; ///< Offset 13 Na= tive PCIE Setup Value + // + // Global Variables + // + UINT8 DisplaySupportFlag; ///< Offset 14 _D= OS Display Support Flag. + UINT8 InterruptModeFlag; ///< Offset 15 Gl= obal IOAPIC/8259 Interrupt Mode Flag. + UINT8 L01Counter; ///< Offset 16 Gl= obal L01 Counter. + UINT8 LtrEnable[24]; ///< Offset 17 La= tency Tolerance Reporting Enable + ///< Offset 18 La= tency Tolerance Reporting Enable + ///< Offset 19 La= tency Tolerance Reporting Enable + ///< Offset 20 La= tency Tolerance Reporting Enable + ///< Offset 21 La= tency Tolerance Reporting Enable + ///< Offset 22 La= tency Tolerance Reporting Enable + ///< Offset 23 La= tency Tolerance Reporting Enable + ///< Offset 24 La= tency Tolerance Reporting Enable + ///< Offset 25 La= tency Tolerance Reporting Enable + ///< Offset 26 La= tency Tolerance Reporting Enable + ///< Offset 27 La= tency Tolerance Reporting Enable + ///< Offset 28 La= tency Tolerance Reporting Enable + ///< Offset 29 La= tency Tolerance Reporting Enable + ///< Offset 30 La= tency Tolerance Reporting Enable + ///< Offset 31 La= tency Tolerance Reporting Enable + ///< Offset 32 La= tency Tolerance Reporting Enable + ///< Offset 33 La= tency Tolerance Reporting Enable + ///< Offset 34 La= tency Tolerance Reporting Enable + ///< Offset 35 La= tency Tolerance Reporting Enable + ///< Offset 36 La= tency Tolerance Reporting Enable + ///< Offset 37 La= tency Tolerance Reporting Enable + ///< Offset 38 La= tency Tolerance Reporting Enable + ///< Offset 39 La= tency Tolerance Reporting Enable + ///< Offset 40 La= tency Tolerance Reporting Enable + UINT8 ObffEnable[24]; ///< Offset 41 Op= timized Buffer Flush and Fill + ///< Offset 42 Op= timized Buffer Flush and Fill + ///< Offset 43 Op= timized Buffer Flush and Fill + ///< Offset 44 Op= timized Buffer Flush and Fill + ///< Offset 45 Op= timized Buffer Flush and Fill + ///< Offset 46 Op= timized Buffer Flush and Fill + ///< Offset 47 Op= timized Buffer Flush and Fill + ///< Offset 48 Op= timized Buffer Flush and Fill + ///< Offset 49 Op= timized Buffer Flush and Fill + ///< Offset 50 Op= timized Buffer Flush and Fill + ///< Offset 51 Op= timized Buffer Flush and Fill + ///< Offset 52 Op= timized Buffer Flush and Fill + ///< Offset 53 Op= timized Buffer Flush and Fill + ///< Offset 54 Op= timized Buffer Flush and Fill + ///< Offset 55 Op= timized Buffer Flush and Fill + ///< Offset 56 Op= timized Buffer Flush and Fill + ///< Offset 57 Op= timized Buffer Flush and Fill + ///< Offset 58 Op= timized Buffer Flush and Fill + ///< Offset 59 Op= timized Buffer Flush and Fill + ///< Offset 60 Op= timized Buffer Flush and Fill + ///< Offset 61 Op= timized Buffer Flush and Fill + ///< Offset 62 Op= timized Buffer Flush and Fill + ///< Offset 63 Op= timized Buffer Flush and Fill + ///< Offset 64 Op= timized Buffer Flush and Fill + UINT8 Rtd3Support; ///< Offset 65 Ru= ntime D3 support. + UINT8 LowPowerS0Idle; ///< Offset 66 Lo= w Power S0 Idle Enable + UINT8 VirtualGpioButtonSxBitmask; ///< Offset 67 Vi= rtual GPIO button Notify Sleep State Change + UINT8 PstateCapping; ///< Offset 68 P-= state Capping + UINT8 Ps2MouseEnable; ///< Offset 69 Ps= 2 Mouse Enable + UINT8 Ps2KbMsEnable; ///< Offset 70 Ps= 2 Keyboard and Mouse Enable + // + // Driver Mode + // + UINT32 GpioIrqRoute; ///< Offset 71 GP= IO IRQ + UINT8 PL1LimitCS; ///< Offset 75 se= t PL1 limit when entering CS + UINT16 PL1LimitCSValue; ///< Offset 76 PL= 1 limit value + UINT8 TenSecondPowerButtonEnable; ///< Offset 78 10= sec Power button support + UINT8 PciDelayOptimizationEcr; ///< Offset 79 Pc= i Delay Optimization Ecr + UINT8 TbtSupport; ///< Offset 80 Th= underbolt(TM) support + UINT8 TbtNativeOsHotPlug; ///< Offset 81 Tb= tNativeOsHotPlug + UINT8 TbtSelector; ///< Offset 82 Th= underbolt(TM) Root port selector + UINT8 TbtSelector1; ///< Offset 83 Th= underbolt(TM) Root port selector +} EFI_GLOBAL_NVS_AREA; + +#pragma pack(pop) +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/AttemptUsbFirst= .h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/AttemptUsbFirst.h new file mode 100644 index 0000000000..bbdeb71da5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/AttemptUsbFirst.h @@ -0,0 +1,51 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ATTEMPT_USB_FIRST_H_ +#define _ATTEMPT_USB_FIRST_H_ + +#pragma pack(1) +typedef struct _ATTEMPT_USB_FIRST_HOTKEY_INFO { + UINT8 RevisonId; // Structure Revision ID + UINT8 HotkeyTriggered; // Hot key status +} ATTEMPT_USB_FIRST_HOTKEY_INFO; +#pragma pack() + +#pragma pack(1) +typedef struct _ATTEMPT_USB_FIRST_VARIABLE { + UINT8 UsbBootPrior; +} ATTEMPT_USB_FIRST_VARIABLE; +#pragma pack() + +// +// Volatile variable definition for Attempt USB first features +// +#pragma pack(1) +typedef struct _ATTEMPT_USB_FIRST_RUNTIME_VARIABLE { + UINT8 RevisonId; // Structure Revision ID + UINT8 UsbFirstEnable; // Attempt USB First is enabled or not +} ATTEMPT_USB_FIRST_RUNTIME_VARIABLE; +#pragma pack() + +// +// Volatile variable definition for third party Default Enabling via UEFI = Variable. +// +#pragma pack(1) +typedef struct _ENABLE_CUSTOM_DEFAULTS{ + UINT32 EnableCustomDefaults; +} ENABLE_CUSTOM_DEFAULTS; +#pragma pack() + +#define COENG_DEFAULTS_UNKNOWN 0 +#define COENG_DEFAULTS_SUPPORTED 1 +#define COENG_DEFAULTS_VAR_EXITS 2 +#define COENG_DEFAULTS_VAR_SET 4 +#define COENG_DEFAULTS_AVAILABLE (COENG_DEFAULTS_SUPPORTED | COENG_DEFAULT= S_VAR_EXITS |COENG_DEFAULTS_VAR_SET) + +extern EFI_GUID gAttemptUsbFirstHotkeyInfoHobGuid; +extern EFI_GUID gAttemptUsbFirstRuntimeVarInfoGuid; +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/CpuSmm.h b/Plat= form/Intel/WhiskeylakeOpenBoardPkg/Include/CpuSmm.h new file mode 100644 index 0000000000..17ccd56373 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/CpuSmm.h @@ -0,0 +1,57 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPUSMM_H_ +#define _CPUSMM_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define CPUSMM_GUID { 0x90d93e09, 0x4e91, 0x4b3d, { 0x8c, 0x77, 0xc8, 0x2f= , 0xf1, 0xe, 0x3c, 0x81 }} +#define CPUSMM_SETUP_NAME L"CpuSmm" + +#pragma pack(1) +typedef struct { + UINT8 CpuSmmMsrSaveStateEnable; + UINT8 CpuSmmCodeAccessCheckEnable; + UINT8 CpuSmmUseDelayIndication; + UINT8 CpuSmmUseBlockIndication; + UINT8 CpuSmmUseSmmEnableIndication; + UINT8 CpuSmmProcTraceEnable; +} CPU_SMM; +#pragma pack() + +#ifndef OFFSET_OF +#ifdef __GNUC__ +#if __GNUC__ >=3D 4 +#define OFFSET_OF(TYPE, Field) ((UINTN) __builtin_offsetof(TYPE, Field)) +#endif +#endif +#endif + +#ifndef OFFSET_OF +#define OFFSET_OF(TYPE, Field) ((UINTN) &(((TYPE *)0)->Field)) +#endif + +#define VERIFY_OFFSET(TYPE, Field, Offset) extern UINT8 _VerifyOffset##TYP= E##Field[(OFFSET_OF(TYPE, Field) =3D=3D Offset) / (OFFSET_OF(TYPE, Field) = =3D=3D Offset)] + +// +// If TpmSupport/MorStae isn't in this offset, build failure (0 size array= or divided by 0) will be generated. +// Platform DSC file maps the two field to HII PCD so the offset value is = critical. +// +VERIFY_OFFSET (CPU_SMM, CpuSmmMsrSaveStateEnable, 0x0); +VERIFY_OFFSET (CPU_SMM, CpuSmmCodeAccessCheckEnable, 0x1); +VERIFY_OFFSET (CPU_SMM, CpuSmmUseDelayIndication, 0x2); +VERIFY_OFFSET (CPU_SMM, CpuSmmUseBlockIndication, 0x3); +VERIFY_OFFSET (CPU_SMM, CpuSmmUseSmmEnableIndication, 0x4); +VERIFY_OFFSET (CPU_SMM, CpuSmmProcTraceEnable, 0x5); + +/****** DO NOT WRITE BELOW THIS LINE *******/ +#ifdef __cplusplus +} +#endif +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/FirwmareConfigu= rations.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/FirwmareConfigur= ations.h new file mode 100644 index 0000000000..b7202a6b4a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/FirwmareConfigurations= .h @@ -0,0 +1,20 @@ +/** @file + This header file provides definitions of firmware configuration. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FIRMWARE_CONFIGURATION_H_ +#define _FIRMWARE_CONFIGURATION_H_ + +typedef enum { + FwConfigDefault =3D 0, + FwConfigProduction, + FwConfigTest, + FwConfigMax +} FW_CONFIG; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/GopConfigLib.h = b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/GopConfigLib.h new file mode 100644 index 0000000000..ed63b28adf --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/GopConfigLib.h @@ -0,0 +1,1766 @@ +/** @file +Header file for GOP Configuration Library + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GOP_CONFIG_LIB_H_ +#define _GOP_CONFIG_LIB_H_ + +#include +#include +#pragma pack(1) +#define GOP_CONFIG_VBT_REVISION 0xC1 + +#define ChildStruct_MAX 8 ///< Maximum numbe= r of child structures in VBT +#define CompressionStruct_MAX 2 ///< Maximum numbe= r of compression parameter structures in VBT. +#define NO_DEVICE 0x00 ///< Defines a nul= l display class. +#define DISPLAY_PORT_ONLY 0x68C6 ///< Defines a dis= play class of Integrated Display Port Only +#define DISPLAY_PORT_HDMI_DVI_COMPATIBLE 0x60D6 ///< Defines a dis= play class of Integrated DisplayPort with HDMI/DVI Compatible +#define DISPLAY_PORT_DVI_COMPATIBLE 0x68D6 ///< Defines a dis= play class of Integrated DisplayPort with DVI Compatible +#define HDMI_DVI 0x60D2 ///< Defines a dis= play class of Integrated HDMI/DVI +#define DVI_ONLY 0x68D2 ///< Defines a dis= play class of Integrated DVI Only +#define MIPI_ONLY 0x1400 +#define eDP_ONLY 0x1806 ///< Defines a dis= play class of eDP only +#define AUX_CHANNEL_A 0x40 +#define AUX_CHANNEL_B 0x10 +#define AUX_CHANNEL_C 0x20 +#define AUX_CHANNEL_D 0x30 +#define NO_PORT 0x00 ///< Defines a out= put port NA +#define HDMI_B 0x01 ///< Defines a out= put port HDMI-B +#define HDMI_C 0x02 ///< Defines a out= put port HDMI-C +#define HDMI_D 0x03 ///< Defines a out= put port HDMI-D +#define HDMI_F 0x0E ///< Defines a out= put port HDMI-D +#define DISPLAY_PORT_A 0x0A ///< Defines a out= put port DisplayPort A +#define DISPLAY_PORT_B 0x07 ///< Defines a out= put port DisplayPort B +#define DISPLAY_PORT_C 0x08 ///< Defines a out= put port DisplayPort C +#define DISPLAY_PORT_D 0x09 ///< Defines a out= put port DisplayPort D +#define DISPLAY_PORT_E 0x0B ///< Defines a out= put port DisplayPort E +#define DISPLAY_PORT_F 0x0D ///< Defines a out= put port DisplayPort F +#define PORT_MIPI_A 0x15 ///< Mipi Port A +#define PORT_MIPI_C 0x17 ///< Mipi Port C + +typedef struct { + UINT16 Dclk; // DClk in 10 KHz + UINT8 HActive; // HActive [7:0] + UINT8 HBlank; // HBlank [7:0] + UINT8 HA_HB_UpperNibble; // Upper nibble =3D HActive [11:8] + UINT8 VActive; // VActive [7:0] + UINT8 VBlank; // VBlank [7:0] + UINT8 VA_VB_UpperNibble; // Upper nibble =3D VActive [11:8] + UINT8 HSyncOffset; // HSync offset from blank start L= SB + UINT8 HPulseWidth; // HSync Pulse Width, LSB + UINT8 VsyncOffset_VpulseWidth_LSB; // Bits 7:4 =3D VSync offset [3:0] + UINT8 HSO_HSPW_V_High; // Bits 7:6 =3D HSync Offset [9:8] + UINT8 HorImageSize; // Horizontal Image Size + UINT8 VerImageSize; // Vertical Image Size + UINT8 HIS_VIS_High; // UpperLmtH_V Upper limits of H. = and V. image size + UINT8 HBorder; // Horizontal Border + UINT8 VBorder; // Vertical Border + UINT8 Flags; // Flags +} DTD_STRUCTURE; // 18 Bytes + +typedef struct { + UINT16 XRes; + UINT16 YRes; + UINT32 SerialNo; + UINT8 Week; + UINT8 Year; +} PID_DATA; // 10 Bytes + +// +// VBT Header +// +/** + This structure defines the VBT Header. +**/ +typedef struct { + UINT8 Product_String[20]; ///< "$VBT_Cannonlake" is the product string + UINT16 Version_Num; ///< Defines the VBT Header version number. + UINT16 Header_Size; ///< Defines the size of VBT Header. + UINT16 Table_Size; ///< Defines the size of complete VBT. + UINT8 Checksum; ///< Defines the checksum of entire VBT + UINT8 Reserved1; ///< Reserved field 1 of 1 byte. + UINT32 Bios_Data_Offset; ///< Defines the offset of VBT Data block. + UINT32 Aim_Data_Offset[4]; ///< 4 reserved pointers to VBT data blocks. +} VBT_HEADER; + +/** + This structure defines the VBT BIOS Data Block Header +**/ +typedef struct { + UINT8 BDB_Signature[16]; ///< Defines the Bios Data Block signature "= BIOS_DATA_BLOCK". + UINT16 BDB_Version; ///< Defines the VBT (data) version. + UINT16 BDB_Header_Size; ///< Defines the size of VBT Bios data block= header. + UINT16 BDB_Size; ///< Defines the size of Bios data block. +} VBT_BIOS_DATA_HEADER; + +/** + This structure defines the BMP Signon Message and Copyright Message Stru= cture +**/ +typedef struct { + UINT8 BlockId; ///< Defines Block ID : 254 + UINT16 BlockSize; ///< Defines the size of BMP Signon block. + + UINT16 Bmp_BIOS_Size; ///< Defines the BIOS size 32k/48k/64k. + UINT8 BIOS_Type; ///< Defines the type of BIOS desktop or mob= ile. + UINT8 RelStatus; ///< Defines the release status of the curre= nt GOP driver. + UINT8 BIOS_HW; ///< Defines the Hardware i.e. Cannonlake. + UINT8 INT_HW; ///< Defines the integrated hardware support= ed eDP/HDMI/DP. + UINT8 Build_Number[4]; ///< Defines the build number string. + UINT8 SignOn[155]; ///< Defines the sign on message. + UINT8 CopyRight[61]; ///< Defines the copyright message. +} BMP_STRUCTURE_SIGNON; + +/** + This structure defines the BMP General Bits +**/ +typedef struct { + UINT16 bmp_BIOS_CS; ///< Defines the start of BIOS code segment + UINT8 bmp_DOS_Boot_Mode; ///< Defines the mode number to set when D= OS is boot + UINT8 bmp_BW_Percent; ///< Set percentage of total memory BW + UINT8 bmp_Popup_Mem_Size; ///< Default Popup memory size in KB + UINT8 bmp_Resize_PCI_BIOS; ///< BIOS size granularity in 0.5 KB + UINT8 Switch_CRT_To_DDC2; ///< Obsolete field: Is the CRT already sw= itched to DDC2 + UINT8 bmp_Allow_Config; ///< Bit 1 : 1, Enable aspect ratio for DOS + ///< Bit 0 : 1, Allow boot to DVI even if = it is not attached. +} BMPGEN; + +/** + This structure defines Block 254 (BMP structure) +**/ +typedef struct { + BMP_STRUCTURE_SIGNON bmp_Signon_Message; ///< Instance of signon an= d copyright message structure + BMPGEN bmp_General_Bytes; ///< Instance of BMP Gener= al Bits structure. +} BLOCK254_BMP_Structure; + +/** + This structure defines Block 1 (General Bytes Definitions) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID (1) + UINT16 BlockSize; ///< Defines the size of General bytes definitio= n block. + + /** + BMP General Bit Definitions 1\n + Bit 7 =3D DVO A color flip bit + =3D 0, No DVO A color flip + =3D 1, Flip DVO A color + Bits 6:4 =3D Clear screen (CLS) after Signon + =3D 000, No CLS + =3D 001, 0.5 sec pause and then CLS + =3D 010, 1.0 sec pause and then CLS + =3D 011, 1.5 sec pause and then CLS + =3D 100, 2.0 sec pause and then CLS + =3D 101, 2.5 sec pause and then CLS + =3D 110, 3.0 sec pause and then CLS + =3D 111, 3.5 sec pause and then CLS + Bit 3 =3D 1 Enable Display Signon + Bit 2 =3D 1 Enable Flex-aim Support + Bits 1:0 =3D Flat panel fitting enabling + =3D 00, Centering + =3D 01, Reserved + =3D 10, Aspect scaling + =3D 11, Fullscreen + **/ + union { + UINT8 Value; + struct { + UINT8 PanelFitterEnabling:2; + UINT8 FlexAimSupportEnable:1; + UINT8 DisplaySignonEnable:1; + UINT8 ClearScreenTime:3; + UINT8 DvoAColorFlipEnable:1; + } Bits; + } bmp_Bits_1; + + /** + BMP General Bit Definitions\n + Bit 7 =3D Hot plug support + =3D 0, Hot plug disabled + =3D 1, Hot plug enabled + Bit 6 =3D Dynamic CD clock feature + =3D 0, Dynamic CD clock feature is disabled + =3D 1, Dynamic CD clock feature is enabled + Bit 5 =3D Underscan support for VGA timings + Bit 4 =3D Disable SSC in Dual Display Twin Mode. (This field is obsolete= now. Kept for VBIOS only.) + =3D 0, No + =3D 1, Yes + Bit 3 =3D LFP power state on override by 5f64h,08h + =3D 0, No Override + =3D 1, Override + Bit 2 =3D Internal LVDS SSC frequency. (This field is obsolete now. Kept= for VBIOS only.) + =3D 0, 96/120MHz + =3D 1, 100MHz + Bit 1 =3D internal LVDS SSC (Spread Spectrum Clock) (This field is obsol= ete now. Kept for VBIOS only.) + =3D 0, Disabled + =3D 1, Enabled + Bit 0 =3D KvmrSessionEnable. + =3D 0, Disabled + =3D 1, Enabled + **/ + union { + UINT8 Value; + struct { + UINT8 KvmrSessionEnable:1; + UINT8 Reserved_1:5; + UINT8 DynamicCdClockEnable:1; + UINT8 HotPlugEnable:1; + } Bits; + } bmp_Bits_2; + + /** + BMP General Bit Definitions 3\n + Bit 7 =3D Ignore strap status + =3D 0 Do not ignore + =3D 1 Ignore + Bit 6 =3D Panel Timing algorithm + =3D 0 Preferred timings + =3D 1 Best fit timings + Bit 5 Copy iLFP DTD to SDVO LVDS DTD + =3D 0 Don't copy DTD + =3D 1 Copy DTD to + Bit 4 =3D VBIOS normal/extd. DT mode + =3D 0 Normal mode + =3D 1 DUAL mode + Bit 3 =3D FDI RX Polarity + =3D 0 Normal + =3D 1 Inverted + Bit 2 =3D Enable 180 Degree Rotation + =3D 0 Disable + =3D 1 Enable + Bit 1 =3D Single DVI-I connector for CRT and DVI display: Obsolete field + =3D 0 Disabled + =3D 1 Enabled + Bit 0 =3D Smooth Vision + =3D 0 Disabled + =3D 1 Enabled + **/ + union { + UINT8 Value; + struct { + UINT8 Reserved1:1; + UINT8 SingleDviiCrtConnector:1; + UINT8 Enable180DegRotation:1; + UINT8 FdiRxPolarity:1; + UINT8 Reserved2:4; + } Bits; + } bmp_Bits_3; + + UINT8 Reserved; ///< Reserved field. It was Legacy_Monitor_Detect = in previous platforms. + + /** + Integrated display device support\n + Bits 7:6 =3D Reserved + Bit 5 =3D DP SSC Dongle Enable/Disable + Bit 4 =3D DP SSC Frequency. (This field is obsolete now. Kept for VBIOS = only.) + =3D 0, 96 MHz + =3D 1, 100 MHz + Bit 3 =3D DP SSC Enable + =3D 0, Disable + =3D 1, Enable + Bit 2 =3D Integrated EFP support + =3D 0, Disable + =3D 1, Enable + Bit 1 =3D Integrated TV support. (This field is obsolete now. Kept for V= BIOS only.) + =3D 0, Disable + =3D 1, Enable + Bit 0 =3D Integrated CRT support: Obsolete field + =3D 0, Disable + =3D 1, Enable + **/ + union { + UINT8 Value; + struct { + UINT8 CrtSupported:1; + UINT8 TvSupported:1; + UINT8 EfpSupported:1; + UINT8 DpSscEnable:1; + UINT8 DpSscFrequency:1; + UINT8 DpDongleSscEnable:1; + UINT8 Reserved1:2; + } Bits; + } Int_Displays_Support; +} VBT_GENERAL1_INFO; + +/** + This defines the Structure of PRD Boot Table Entry +**/ +typedef struct { + UINT8 AttachBits; ///< Bitmap representing the displays attached cur= rently. + UINT8 BootDev_PipeA; ///< Bitmap representing the display to boot on Pi= pe A. + UINT8 BootDev_PipeB; ///< Bitmap representing the display to boot on Pi= pe B. +} PRD_TABLE; + +/** + This defines the structure of Block 254 (PRD Boot Table/Child Device Lis= t) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID (254) + UINT16 BlockSize; ///< Defines the size of Block 254 + + PRD_TABLE PRDTable[16]; ///< Defines the Child devic= e list for enumerating child handles. + UINT16 PRD_Boot_Table_Number_Of_Entries; ///< Number of entries in ch= ild device list. +} PRD_BOOT_TABLE; + +/** + This defines the Structure for a CHILD_STRUCT (used for all the displays= ). +**/ +typedef struct { + UINT16 DeviceHandle; ///< Unique ID indicating the group of dis= play device (LFP/EFP1/EFP2/EFP3/EFP4). + UINT16 DeviceClass; ///< Indicates the class of display device. + UINT8 I2CSpeed; ///< Defines the I2C speed to be used for = I2C transaction. + /** + Defines the DP on board redriver configuration. + BIT[7] : Reserved + BIT[6] : Is On Board DP Redriver Present + 0 : No + 1 : Yes + BIT[5:3] : On Board Redriver VSwing Level + 0 : Level 0 + 1 : Level 1 + 2 : Level 2 + 3 : Level 3 + Others : Reserved + BIT[2:0] : On Board Redriver PreEmph Level + 0 : Level 0 + 1 : Level 1 + 2 : Level 2 + 3 : Level 3 + Others : Reserved + **/ + union{ + UINT8 Value; + struct { + UINT8 OnBoardPreEmphLevel:3; + UINT8 OnBoardVSwingLevel:3; + UINT8 OnBoardRedriverPresent:1; + UINT8 Reserved:1; + } Bits; + } DpOnBoardRedriver; + + /** + Defines the DP on dock redriver configuration. + BIT[7] : Reserved + BIT[6] : Is On Dock DP Redriver Present + 0 : No + 1 : Yes + BIT[5:3] : On Dock Redriver VSwing Level + 0 : Level 0 + 1 : Level 1 + 2 : Level 2 + 3 : Level 3 + Others : Reserved + BIT[2:0] : On Dock Redriver PreEmph Level + 0 : Level 0 + 1 : Level 1 + 2 : Level 2 + 3 : Level 3 + Others : Reserved + **/ + union { + UINT8 Value; + struct { + UINT8 OnDockPreEmphLevel:3; + UINT8 OnDockVSwingLevel:3; + UINT8 OnDockRedriverPresent:1; + UINT8 Reserved:1; + } Bits; + } DpOnDockRedriver; + + /** + + Defines the HDMI level shifter configuration. + BIT[7:5] : Hdmi Maximum data rate + BIT[4:0] : Hdmi Level shifter value + + **/ + union{ + UINT8 Value; + struct { + UINT8 HdmiLevelShifterValue:5; + UINT8 HdmiMaxDataRateBits:3; + } Bits; + } HdmiLevelShifterConfig; + + UINT16 EFPDTDBufferPointer; ///< Pointer to the DTD timing to be used = in case of edidless EFP. + + /** + Defines the first set of flags. + BIT[7-4] : Reserved + BIT[3] : Dual pipe ganged display support + 0 : Display uses a single pipe/port + 1 : Display uses two distinct pipes/ports. + BIT[2] : Compression Method Select + 0 : Compression using picture parameter set (PPS) + 1 : Compression using Capability parameter set (CPS) + BIT[1] : Compression enable/disable for this display. + 0 : Disabled + 1 : Enabled + BIT[0] : EDID less EFP Enable + 0 : Enable support for EDID less EFP. + 1 : Disable support for EDID less EFP. + **/ + union { + UINT8 Value; + struct { + UINT8 EdidlessEfpEnable:1; + UINT8 CompressionEnable:1; + UINT8 CompressionMethod:1; + UINT8 IsDualPortEnabled:1; + UINT8 Reserved:4; + } Bits; + } Flags0; + + /** + Defines the compression index field for the display. + BITS[7-4] : Reserved + BITS[3-0] : Compression Structure index in the block 55. + 0x0 : Index 0 in block 55 + 0x1 : Index 1 in block 55 + 0xF : Not Applicable. + Others : Reserved + **/ + union { + UINT8 Value; + struct { + UINT8 IndexInBlock55:4; + UINT8 Reserved:4; + } Bits; + } CompressionStructureIndex; + + UINT8 SlaveDdiPort; ///< The DVO port number of slave DDI to b= e used in case Flags0[3] =3D 1. + + UINT8 Reserved_1; ///< Reserved and might be used in other p= latforms. + UINT16 AddInOffset; ///< Obsolete field. + UINT8 DVOPort; ///< Specifies the port number of the disp= lay device represented in the device class. + UINT8 I2CBus; ///< Specifies the GMBUS or I2C pin pair f= or add in card. + UINT8 SlaveAddr; ///< Specifies the I2C address of the add = in card. + UINT8 DDCBus; ///< Specifies the GMBUS pin pair for EDID= read. + UINT16 TimingInfoPtr; ///< Pointer to the buffer where VBIOS sto= res the EDID of device. + UINT8 DVOCfg; ///< Obsolete field. + + /** + Flags 1\n + Bits 7:5 : Reserved + Bit 4 : HPD Sense Invert + 0 : Invert not required (default) + 1 : Invert required + Bit 3 : IBoost feature enable/disable. + 0 : IBoost feature is disabled. + 1 : IBoost feature is enabled. + Bit 2 : Hdmi 2.0 Motherboard Downsuppotred options + 0 : Motherboard Down chip not supported + 1 : Motherboard Down Chip Supported on the Board + Bit 1 : Lane Reversal feature. + 0 : Disable + 1 : Enable + Bit 0 : DP/HDMI routed to dock. + 0 : Disable + 1 : Enable + **/ + union { + UINT8 Value; + struct { + UINT8 DockablePort:1; + UINT8 EnableLaneReversal:1; + UINT8 OnBoardLsPconDonglePresent:1; + UINT8 IBoostEnable:1; + UINT8 IsHpdInverted:1; + UINT8 Reserved:3; + } Bits; + } Flags_1; + + UINT8 Compatibility; ///< Compatibility is used in VBIOS only. = It was used before device class was defined. + UINT8 AUX_Channel; ///< Specifies the aux channel to be used = for display port devices. + UINT8 Dongle_Detect; ///< Indicates whether dongle detect is en= abled or not. + UINT8 Capabilities; ///< Bits 1-0 indicate pipe capabilities w= hether display can be used on one pipe or both the pipes. + UINT8 DVOWiring; ///< Obsolete field. + UINT8 MipiBridgeType; ///< MIPI bridge type + UINT16 DeviceClassExtension; ///< Obsolete. + UINT8 DVOFunction; ///< Obsolete. + + /** + Flags 2 + Bits 7:4 : DP Port trace length from silicon to output port on the board + 0 : Default RVP length + 1 : Short trace length + 2 : Long trace length + Bits 3:2 : Reserved + Bit 1 : Indicates whether this port is Thunderbolt port or not. + 0 : No + 1 : Yes + Bit 0 : DP 2 lane RCR# 1024829: USB type C to enable 2 lane DP displ= ay + 0 : Disable + 1 : Enable + **/ + union { + UINT8 Value; + struct { + UINT8 UsbTypeCDongleEnabled:1; ///< Indicates whether this port i= s USB type C. + UINT8 IsThunderboltPort:1; ///< Indicates whether this port i= s Thunderbolt. (ICL+) + UINT8 Reserved:2; ///< Reserved for future use. + UINT8 DpPortTraceLength:4; ///< Dp port trace length from sil= icon to port. + } Bits; + } Flags_2; + UINT8 DP2XGpioIndex; ///< GPIO index number for the USB type C. + UINT16 DP2XGpioNumber; ///< GPIO number for USB type C. + + /** + IBoost magnitude field. + Bits 7:4 : DP Boost magnitude + 0 : 1 + 1 : 3 + 2 : 7 + Others : Reserved for WHL. + Bits 3:0 : HDMI Boost magnitude + 0 : 1 + 1 : 3 + 2 : 7 + Others : Reserved. + **/ + union { + UINT8 Value; + struct { + UINT8 DpEdpBoostMagnitude:4; + UINT8 HdmiBoostMagnitude:4; + } Bits; + } BoostMagnitude; +} CHILD_STRUCT; + +/** + This structure defines Block 2 (General Bytes Definitions) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 2. + UINT16 BlockSize; ///< Defines the size of VBT General Inf= o 2 Block. + + UINT8 bmp_CRT_DDC_GMBUS_Pin; ///< Obsolete field: Selects the C= RT DDC GMBUS pin pair. + UINT8 bmp_DPMS_Bits; ///< BMP DPMS Bit Definitions. + UINT16 bmp_Boot_Dev_Bits; ///< BMP Boot Device Bit Definitio= ns. + UINT8 SizeChild_Struct; ///< Size of the ChildStruc struct= ure. + + CHILD_STRUCT Child_Struct[ChildStruct_MAX]; ///< This array defines al= l the supported child structures. +} VBT_GENERAL2_INFO; + +/** + This defines the structure of Block 3 (Original Display Toggle List) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 3 + UINT16 BlockSize; ///< Defines the size of Original Displa= y Toggle List Block + UINT8 bmp_Display_Detect; ///< Display must be attached or not +} BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST; + +/** + This defines structure of a pointer table. +**/ +typedef struct { + UINT16 Offset; ///< Defines the offset of the table from start of= BIOS Data block. + UINT16 Size; ///< Defines the size of an entry of the table. +} BMP_TABLE_PTR; + +/** + This structure defines Block 252 (SBIOS Hooks and BMP Table Pointers). +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 252. + UINT16 BlockSize; ///< Defines the size of SBIOS Hooks b= lock. + UINT8 SbiosHooks[18]; ///< This array defines a series of SB= IOS hooks. Each entry represents one hook. + BMP_TABLE_PTR BmpTablePtr[26]; ///< This array defines pointers to al= l the important tables in the VBT. +} BLOCK252_SBIOS_Hook; + +/** + This defines the structure of MMIO boot table entry +**/ +typedef struct { + UINT32 Register; ///< Defines the MMIO offset of the register. + UINT32 Value; ///< Defines the default value of the register. +} MMIO_BOOT_TABLE; + +/** + This structure defines Block 6 (MMIO Register Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 6 + UINT16 BlockSize; ///< Defines the size of MMIO Regi= ster Table block. + UINT16 RegTableId; ///< Defines the ID for MMIO regis= ter table (0xFFFC). + UINT8 AccessFlag; ///< Defines the flag for data acc= ess size (02 for 4 byte read/write). + MMIO_BOOT_TABLE MMIOBootTable[14]; ///< Array containing the MMIO reg= ister table. + UINT16 TableEnd; ///< Special value describing End = of table (0xFFFF). +} BLOCK06_MMIO_REG_TABLE; + +/** + This structure defines Block 7 (IO SW Flag Register Table) +**/ +typedef struct { + UINT8 BlockId; ///< Defines Block ID (7). + UINT16 BlockSize; ///< Defines the size of IO SW Flag register t= able block. + UINT16 RegTableId; ///< Defines the ID for IO SW Flag register ta= ble (0xFFFE). + UINT8 GRIndexRegLsb; ///< Defines the read/write size. Value is 0xC= E meaning 1 byte without mask. + UINT8 IOSWFlagReg; ///< Defines the offset for the IO SW Flag reg= ister. + UINT8 Value; ///< Defines the data/value for the register. + UINT16 TableEnd; ///< Special value describing the end of table= (0xFFFF). +} BLOCK07_IOSWFLAG_REG_TABLE; + +/** + This structure defines the entry of SWF table. +**/ +typedef struct { + UINT32 Register; ///< Defines the MMIO offset of the SWF register. + UINT32 Value; ///< Defines the default value for the SWF register. +} SWF_TABLE; + +/** + This defines the structure of Block 8 (MMIO SW Flag Block). +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block ID : 8. + UINT16 BlockSize; ///< Defines the size of MMIO SWF register table= block. + UINT16 RegTableId; ///< Defines the ID for MMIO SWF register table = (0xFFFC). + UINT8 AccessFlag; ///< Defines the data access size. Value is 0x02= meaning 4 bytes read/write. + SWF_TABLE SWFTable[7]; ///< Array containing the MMIO SWF register tabl= e. + UINT16 TableEnd; ///< Special value describing end of table (0xFF= FF). +} BLOCK08_MMIOSWFLAG_REG_TABLE; + +/** + This structure defines the PSR feature table entry. +**/ +typedef struct { + UINT8 SRD_Enables; ///< Defines PSR features such as full link = enable/disable and whether aux is required to wake up. + UINT8 SRD_WaitTimes; ///< Defines lines to wait before link stand= by and idle frames to wait before SRD enable. + UINT16 SRD_TP1_WakeupTime; ///< TP 1 wake up time in multiples of 100. + UINT16 SRD_TP2_WakeupTime; ///< TP2/TP3 wake up time in multiples of 100 +} PSR_FEATURE_TABLE; + +/** + This defines the structure of Block 9 (PSR Features Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the block ID : 9 + UINT16 BlockSize; ///< Defines the size of PSR Fea= ture block. + PSR_FEATURE_TABLE PSRFeatureTable[16]; ///< Array containing the PSR Fe= ature table. +} BLOCK09_PSR_FEATURE; + +/** + This structure defines an entry of Mode Removal table. +**/ +typedef struct { + UINT16 XRes; ///< X resolution of the mode. + UINT16 YRes; ///< Y resolution of the mode. + UINT8 Bpp; ///< Bits per pixel of the mode. + UINT16 RRate; ///< Refresh rate of the mode. + UINT8 RFlags; ///< Flags specifying display type and functional = area where the mode is to be removed. + UINT16 PanelFlags; ///< Applicable to LFP only. Indicates which LFP p= anels the mode is to be removed. +} MODE_REMOVAL_TABLE_ENTRY; + +/** + This defines the structure of Block 10 (Mode Removal Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the Block I= D : 10. + UINT16 BlockSize; ///< Defines the size of= Mode Removal table block. + UINT8 EntrySize; ///< Defines the size of= one entry of mode removal table. + MODE_REMOVAL_TABLE_ENTRY ModeRemovalTable[20]; ///< Array containing th= e mode removal table. + UINT16 Terminator; ///< Special value indic= ating end of mode removal table (0xFFFF). +} BLOCK10_MODE_REMOVAL_TABLE; + +/** + This defines the structure of Block 12 (Driver Features Data Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 12 + UINT16 BlockSize; ///< Defines the size of Driver featur= es block. + + /** + This field defines the various driver related bits:\n + Bit 7 =3D Use 00000110h ID for Primary LFP + =3D 0, No + =3D 1, Yes + Bit 6 =3D Enable/Disable Sprite in Clone Mode + =3D 0, Disable + =3D 1, Enable + Bit 5 =3D Driver INT 15h hook + =3D 0, Disable + =3D 1, Enable + Bit 4 =3D Dual View Zoom + =3D 0, Disable + =3D 1, Enable + Bit 3 =3D Hot Plug DVO + =3D 0, Disable + =3D 1, Enable + Bit 2 =3D Allow display switching when in Full Screen DOS. + =3D 0, Block Display Switching + =3D 1, Allow Display Switching + Bit 1 =3D Block display switching when DVD active + =3D 0, No Block Display Switching + =3D 1, Block Display Switching + Bit 0 =3D Boot device algorithm + =3D 0, OS Default + =3D 1, Driver Default + **/ + UINT8 bmp_Driver_Bits; + UINT16 bmp_Driver_Boot_Mode_X; ///< X resolution of driver boot mode. + UINT16 bmp_Driver_Boot_Mode_Y; ///< Y resolution of driver boot mode. + UINT8 bmp_Driver_Boot_Mode_BPP; ///< Bits per pixel of driver boot mod= e. + UINT8 bmp_Driver_Boot_Mode_RR; ///< Refresh rate of driver boot mode. + + /** + This field defines the extended driver bits 1.\n + Bits [15:14] =3D Integrated HDMI configuration + =3D 00b, No Integrated HDMI + =3D 01b, Port-B Only + =3D 10b, Port-C Only + =3D 11b, Both Port-B and Port-C + Bits 13 =3D TV Hotplug + Bits [12:11] =3D LFP configuration + =3D 00b, No LVDS + =3D 01b, Integrated LVDS + =3D 10b, SDVO LVDS + =3D 11b, eDP + Bit 10 =3D Obsolete field: CRT hotplug + =3D 0, Disabled + =3D 1, Enabled (Default) + Bit 9 =3D SDVO device power down + =3D 0, Disabled (Default) + =3D 1, Enabled + Bit 8 =3D Preserve Aspect Ratio + =3D 0, Disabled (Default) + =3D 1, Enabled + Bit 7 =3D Display "Maintain Aspect Scaling" via CUI + =3D 0, No + =3D 1, Yes (Default) + Bit 6 =3D Sprite Display Assignment when Overlay is Active in Clone Mode: + =3D 0, Secondary + =3D 1, Primary + Bit 5 =3D Default Power Scheme user interface + =3D 0, CUI + =3D 1, 3rd Party Application + Bit 4 =3D NT 4.0 Dual Display Clone Support + =3D 0, Disable + =3D 1, Enable + Bit 3 =3D Default Render Clock Frequency + =3D 0, High Frequency + =3D 1, Low Frequency + Bit 2 =3D Dual-Frequency Graphics Technology + =3D 0, No + =3D 1, Yes + Bit 1 =3D Selective Mode Pruning + =3D 0, No + =3D 1, Yes + Bit 0 =3D Enable LFP as primary + =3D 0, Disable + =3D 1, Enable +**/ + UINT16 bmp_Ext_Driver_Bits; + + /** + This defines the driver flags related to CUI Hot key.\n + Bits [7:3] - Reserved + Bit 2 =3D Display Subsystem Enable/Disable + =3D 0, Enable (default Value) + =3D 1, Disable + Bit 1 =3D Embedded Platform + =3D 0, False + =3D 1, True + Bit 0 =3D Define CUI HotK Displays Statically + =3D 0, No + =3D 1, Yes + **/ + UINT8 bmp_Display_Detect_CUIHotK; + + UINT16 bmp_Legacy_CRT_Max_X; ///< Obsolete field: Defines the l= egacy CRT X resolution for driver boot mode. + UINT16 bmp_Legacy_CRT_Max_Y; ///< Obsolete field: Defines the l= egacy CRT Y resolution for driver boot mode. + UINT8 bmp_Legacy_CRT_Max_RR; ///< Obsolete field: Defines the l= egacy CRT refresh rate for driver boot mode. + + /** + This field defines the extended driver bits 2.\n + Bits [7:1] - Reserved + Bit 0 =3D Enable Internal Source Termination for HDMI + =3D 0, External Termination + =3D 1, Internal Termination + **/ + UINT8 bmp_Ext2_Driver_Bits; + + UINT8 bmp_VBT_Customization_Version; ///< Defines the customized VBT = version number. + + /** + This field defines all the driver feature flags.\n + Bit 15 =3D PC Features Field's Validity + =3D 0, Invalid + =3D 1, Valid + Bit 14 =3D Hpd_wake - HPD events are routed to display driver when syste= m is in S0ix/DC9 + =3D 0, Disable + =3D 1, Enable + Bit 13 =3D Assertive Display Technology (ADT) + =3D 0, Disable + =3D 1, Enable + Bit 12 =3D Dynamic Media Refresh Rate Switching (DMRRS) + =3D 0, Disable + =3D 1, Enable + Bit 11 =3D Dynamic Frames Per Second (DFPS) + =3D 0, Disable + =3D 1, Enable + Bit 10 =3D Intermediate Pixel Storage (IPS) + =3D 0, Disable + =3D 1, Enable + Bit 9 =3D Panel Self Refresh (PSR) + =3D 0, Disable + =3D 1, Enable + Bit 8 =3D Intel Turbo Boost Technology + =3D 0, Disable + =3D 1, Enable + Bit 7 =3D Graphics Power Modulation Technology (GPMT) + =3D 0, Disable + =3D 1, Enable + Bit 6 =3D Graphics Render Standby (RS) + =3D 0, Disable + =3D 1, Enable + Bit 5 =3D Intel Display Refresh Rate Switching (DRRS) + =3D 0, Disable + =3D 1, Enable + Bit 4 =3D Intel Automatic Display Brightness (ADB) + =3D 0, Disable + =3D 1, Enable + Bit 3 =3D DxgkDDI Backlight Control (DxgkDdiBLC) + =3D 0, Disable + =3D 1, Enable + Bit 2 =3D Intel Display Power Saving Technology (DPST) + =3D 0, Disable + =3D 1, Enable + Bit 1 =3D Intel Smart 2D Display Technology (S2DDT) + =3D 0, Disable + =3D 1, Enable + Bit 0 =3D Intel Rapid Memory Power Management (RMPM) + =3D 0, Disable + =3D 1, Enable + **/ + UINT16 bmp_Driver_Feature_Flags; +} BLOCK12_DRIVER_FEATURES; + +/** + This defines the structure of Block 13 (Driver Persistence Options) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 13 + UINT16 BlockSize; ///< Defines the size of Driver Persiste= nce options block. + + /** + Defines the various persistence options.\n + Bits [15:10] - Reserved + Bit 9 =3D Docking Persistence Algorithm + =3D 0, OS Default + =3D 1, Driver Default + Bit 8 =3D DVO Hot Plug Persistence on Mode + Bit 7 =3D EDID Persistence on Mode + Bit 6 =3D Hot Key Persistence on Mode + =3D 0, No + =3D 1, Yes + Bit 5 =3D Hot Key Persistence on RestorePipe + =3D 0, No + =3D 1, Yes + Bit 4 =3D Hot Key Persistence on RefreshRate + =3D 0, No + =3D 1, Yes + Bit 3 =3D Hot Key Persistence on MDS/Twin + =3D 0, No + =3D 1, Yes + Bit 2 =3D Power Management Persistence Algorithm + =3D 0, OS Default + =3D 1, Driver Default + Bit 1 =3D Lid Switch Persistence Algorithm + =3D 0, OS Default + =3D 1, Driver Default + Bit 0 =3D Hot Key Persistence Algorithm + =3D 0, OS Default + =3D 1, Driver Default + **/ + UINT16 PersistenceAlgorithm; + + UINT8 PersistMaxconfig; ///< Maximum mode persistence configurat= ions (10-200) +} BLOCK13_DRIVER_PERSISTENCE; + +/** + This defines the structure of Block 17 (SV Bits) +**/ +typedef struct { + UINT8 BlockId; ///< Defnies the unique Block ID : 17 + UINT16 BlockSize; ///< Defines the size of SV Bits block. + + /** + Bits [7:4] =3D Reserved + Bit3 =3D Allow VBlank/VblankScanline timeout hang + =3D 0, Disable + =3D 1, Enable + Bit2 =3D Special GMBus support + =3D 0, Disable + =3D 1, Enable + Bit1 =3D Skip program pipe timings when set VGA modes + =3D 0, Setmode skip DVO Update + =3D 1, Setmode updates DVO + Bit0 =3D Disable VGA fast arbiter + =3D 0, Enabled + =3D 1, Disabled + **/ + UINT8 SvBits1; + UINT8 SvBits2; ///< Reserved for future use. + UINT8 SvBits3; ///< Reserved for future use. + UINT8 SvBits4; ///< Reserved for future use. + UINT8 SvBits5; ///< Reserved for future use. + UINT8 SvBits6; ///< Reserved for future use. + UINT8 SvBits7; ///< Reserved for future use. + UINT8 SvBits8; ///< Reserved for future use. +} BLOCK17_SV_BITS; + +/** + This defines the structure of Block 18 (Driver Rotation) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 18 + UINT16 BlockSize; ///< Defines the size of Driver Rota= tion block. + UINT8 RotationFeatureSupport; ///< Rotation feature support field = used by driver. + UINT8 Reserved1; ///< Reserved for future use. + UINT16 Reserved2; ///< Reserved for future use. + UINT32 Reserved3; ///< Reserved for future use. + UINT32 Reserved4; ///< Reserved for future use. +} BLOCK18_DRIVER_ROTATION; + +/** + This structure defines an entry of OEM mode table. +**/ +typedef struct { + /** + Mode Flags: + Bits[7:3] =3D Reserved + Bit 2 =3D Enable/disable this OEM mode in GOP driver. + Bit 1 =3D Enable/disable this mode in Driver + Bit 0 =3D Enable/disable this mode in VBIOS + **/ + UINT8 ModeFlags; + + /** + Display Device Flags: + Bit 7 =3D LFP2 + Bit 6 =3D EFP2 + Bit 5 =3D EFP3 + Bit 4 =3D EFP4 + Bit 3 =3D LFP + Bit 2 =3D EFP + Bit 1 =3D Rsvd + Bit 0 =3D Rsvd + **/ + UINT8 DisplayFlags; + UINT16 XRes; ///< Defines the X resolution of the mode. + UINT16 YRes; ///< Defines the Y resolution of the mode. + + /** + Defines the bits per pixel of the mode. + Bit 7:3 =3D Reserved + Bit 2 =3D 32 BPP + Bit 1 =3D 16 BPP + Bit 0 =3D 8 BPP + **/ + UINT8 Bpp; + UINT8 RRate; ///< Defines the refresh rate of the mode. + DTD_STRUCTURE Dtd; ///< Defines the 18 byte timing config for the mod= e. +} OEM_MODE_ENTRY; + +/** + This defines the structure of Block 20 (OEM Mode Customization Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique block ID : 20 + UINT16 BlockSize; ///< Defines the size of OEM customiza= tion block. + UINT8 NumOfEntry; ///< Defines the number of entries in = OEM Mode table. + UINT8 EntrySize; ///< Defines the size of one entry of = OEM Mode table. + OEM_MODE_ENTRY OemModeTable[6]; ///< Array defining the OEM mode table. +} BLOCK20_OEM_CUSTOMIZATION; + +/** + This defines the structure of Block 26 (TV options) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 26 + UINT16 BlockSize; ///< Defines the size of TV Options bl= ock. + + /** + Defines the TV options: + Bit 15 =3D D-Conector Support + =3D 0, Disable + =3D 1, Enable + Bit 14 =3D Add 1776x1000 when 1080i is selected and add 1184x666 when = 720p is selected + =3D 0, Disable + =3D 1, Enable + Bit 13:12 Underscan/overscan for HDTV via DVI + =3D 00b, Enable Underscan and Overscan modes (Default) + =3D 01b, Enable only overscan modes + =3D 10b, Enable only underscan modes + Bits 11:2 =3D Reserved + Bit 1:0 =3D Underscan/overscan for HDTV via Component (YPrPb) + =3D 00b, Enable Underscan and Overscan modes (Default) + =3D 01b, Enable only overscan modes + =3D 10b, Enable only underscan modes + **/ + UINT16 bmp_TV_Options_1; +} BLOCK26_TV_OPTIONS; + +/** + This structure defines the eDP panel power sequencing parameters. +**/ +typedef struct { + UINT16 T3; ///< Panel Power-Up Delay. + UINT16 T8; ///< Panel Power-On to backlight Enable Delay. + UINT16 T9; ///< Backlight-Off to Power-Down Delay. + UINT16 T10; ///< Power-Down Delay. + UINT16 T12; ///< Power Cycle Delay. +} EDP_PWR_SEQ; + +/** + This structure defines the PWM<-->Backlight delays for a single eDP pane= l. +**/ +typedef struct { + UINT16 PwmOnToBacklightEnableDelay; ///< PWM on to backight enable= delay. + UINT16 BacklightDisableToPwmOffDelay; ///< Backlight disable to PWM = off delay. +} EDP_PWM_BACKLIGHT_DELAYS; + +/** + This defines FLT parameters for a single eDP panel. + Bits[15:12] : VSwing level + 0 : 0.4V (default) + 1 : 0.6V + 2 : 0.8V + 3 : 1.2V + Others : Reserved + Bits[11:8] : Pre-emphasis level + 0 : no pre-emphasis (default) + 1 : 3.5dB + 2 : 6dB + 3 : 9.5dB + Others : Reserved + Bits[7:4] : Lane count (port width) + 0 : x1 mode (default) + 1 : x2 mode + 2 : Reserved + 3 : x4 mode + Others : Reserved + Bits[3:0] : data rate + 0 : 1.62 Gbps + 1 : 2.7 Gbps + 2 : 5.4 Gbps + Others : Reserved +**/ +typedef union { + UINT16 Value; + struct { + UINT16 DataRate:4; + UINT16 LaneCount:4; + UINT16 PreEmphasisLevel:4; + UINT16 VSwingLevel:4; + } Bits; +} EDP_FAST_LINK_TRAINING_PARAMS; + +/** + This defines Full link training parameters for a single eDP panel. + Bits[7:4] : VSwing level + 0 : 0.4V (default) + 1 : 0.6V + 2 : 0.8V + 3 : 1.2V + Others : Reserved + Bits[3:0] : Pre-emphasis level + 0 : no pre-emphasis (default) + 1 : 3.5dB + 2 : 6dB + 3 : 9.5dB + Others : Reserved +**/ +typedef union { + UINT8 Value; + struct { + UINT8 PreEmphasisLevel:4; + UINT8 VSwingLevel:4; + } Bits; +} EDP_FULL_LINK_TRAINING_PARAMS; + +/** + This defines the structure of Apical Parameters for a single eDP panel. +**/ +typedef struct { + UINT32 PanelOui; ///< Apical IP specific field for Pane= l OUI + UINT32 DPCDBaseAddress; ///< Apical IP specific field for DPCD= Base address + UINT32 DPCDIrdidixControl0; ///< Apical IP specific field for DPCD= Idridix Control 0 + UINT32 DPCDOptionSelect; ///< Apical IP specific field for DPCD= option select + UINT32 DPCDBacklight; ///< Apical IP specific field for DPCD= backlight + UINT32 AmbientLight; ///< Apical IP specific field for Ambi= ent light + UINT32 BacklightScale; ///< Apical IP specific field for back= light scale +} EDP_APICAL_PARAMS; + +/** + This defines the structure of Block 27 (eDP Display Block) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 27 + UINT16 BlockSize; ///< Defines the size of eDP display VBT= block. + + EDP_PWR_SEQ eDP_PWR_SEQ[16]; ///< Array defining the panel power sequ= encing for all 16 eDP panels. + + /** + Defines the panel color depth in bits per pixel. 2 Bits for each Panel. + Bits[1:0] Panel color depth for Panel #1 + =3D 00, 18bpp + =3D 01, 24bpp + =3D 10, 30bpp + =3D 11, 36bpp + **/ + UINT32 eDP_Panel_Color_Depth; + + /** + Array containing the FLT parameters of 16 eDP panels. + **/ + EDP_FAST_LINK_TRAINING_PARAMS eDP_Fast_Link_Training_Params[16]; + + /** + This field defines the eDP sDRRS MSA Timing Delay for all 16 eDP panels.= 2 Bits for Each Panel. + Bits[1:0] for Panel #1 + =3D 00, Line 1 + =3D 01, Line 2 + =3D 10, Line 3 + =3D 11, Line 4 + **/ + UINT32 eDP_sDRRS_MSA_Delay; + + /** + Defines the S3D feature enable/disable for all 16 eDP panels. 1 Bit for = Each Panel. + Bits[0] for Panel #1 + =3D 0, S3D disabled for this panel + =3D 1, S3D enabled for this panel + **/ + UINT16 eDP_S3D_Feature; + + /** + Defines the T3 optimization enable/disable for all 16 panels. 1 Bit for = each panel. + Bits[0] =3D Panel #1 + =3D 0, T3 optimization disabled for this panel + =3D 1, T3 optimization enabled for this panel + **/ + UINT16 eDP_T3_Optmization; + + /** + Defines the Edp vswing and pre-emphasis for all 16 panels. 4 Bits for Ea= ch Panel + Bits[3:0] =3D Panel #1 + =3D 0, Use table 1 for this panel. + =3D 1, Use table 2 for this panel. + **/ + UINT64 VswingPreEmphasisTableNum; + + /** + Defines the Edp fast link training support on all 16 panels. 1 Bit for E= ach Panel + Bits[0] =3D Panel #1 + =3D 0, FastLinkTraining feature is disabled for this panel + =3D 1, FastLinkTraining feature is enabled for this panel + **/ + UINT16 EdpFastLinkTrainingSupportOnPanel; + + /** + Defines whether the Set power state at DPCD 600h is to be done in eDP en= able/disable sequence. + Bits[0] =3D Panel #1 + =3D 0, Set power state at DPCD 600h feature is disabled for this panel + =3D 1, Set power state at DPCD 600h feature is enabled for this panel + **/ + UINT16 SetPowerStateAtDPCD600h; //This is not used currently + + /** + Array defining the PWM <--> Backlight related delays for 16 panels. + **/ + EDP_PWM_BACKLIGHT_DELAYS eDP_Pwm_BackLight_Delays[16]; + + /** + Defines the Edp full link training support on all 16 panels. 1 Bit for E= ach Panel. + \verbatim + Bits[0] : Panel #1 + 0 : Initial vswing and pre-emphasis levels are not provided for Fu= ll link training + 1 : Initial vswing and pre-emphasis levels are provided for Full l= ink training + Bits 1 to 15 are for panel # 2 to 16. + \endverbatim + **/ + UINT16 InitialFullLinkTrainingParamsProvidedInVbt; + + /** + Array containing the initial Vswing and Pre-emphasis parameters for Fu= ll link training. + **/ + EDP_FULL_LINK_TRAINING_PARAMS eDP_Full_Link_Training_Params[16]; + + /** + Defines the Edp Apical assertive display IP support on all 16 panels. 1 = Bit for Each Panel. + Bit 0 : Panel #1 + 0 : Apical assertive display IP is disabled for this panel. + 1 : Apical assertive display IP is enabled for this panel. + Bits 1 to 15 are for panel # 2 to 16. + **/ + UINT16 IsApicalAssertiveDisplayIpEnable; + + /** + Array containing the Apical parameters for all 16 panels + **/ + EDP_APICAL_PARAMS eDP_Apcial_Params[16]; +} BLOCK27_EDP_FEATURES; + +/** + This defines the structure of Block 28 (Edidless EFP support DTD timings) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the uniqu= e Block ID : 28 + UINT16 BlockSize; ///< Defines the size = of Edidless EFP support block. + DTD_STRUCTURE Edidless_EFP_DTD_Struc[4]; ///< Array defining th= e DTD timing for 3 EFP devices. +} BLOCK28_EDIDLESS_EFP; + +/** +This defines the structure of toggle list entry. +**/ +typedef struct { + /** + Defines the display device selection for toggling + Bit 15 =3D EFP4.3 (Reserved for WHL) + Bit 14 =3D EFP3.3 + Bit 13 =3D EFP2.3 + Bit 12 =3D EFP1.3 + Bit 11 =3D EFP4.2 (Reserved for WHL) + Bit 10 =3D EFP3.2 + Bit 9 =3D EFP2.2 + Bit 8 =3D EFP1.2 + Bit 7 =3D LFP2 + Bit 6 =3D EFP2 + Bit 5 =3D EFP3 + Bit 4 =3D EFP4 + Bit 3 =3D LFP + Bit 2 =3D EFP + Bit 1 =3D TV + Bit 0 =3D CRT + **/ + UINT16 DisplayDevice; +} CNL_TOGGLE_LIST_ENTRY; + +/** + This defines the structure of Block 31 (Toggle Lists for Cannonlake) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Bl= ock ID : 31 + UINT16 BlockSize; ///< Defines the size of T= oggle List Block. + UINT16 NumOfEntry1; ///< Defines the number of= entries in toggle list 1. + UINT8 EntrySize1; ///< Defines the size of t= oggle list entry present in list 1. + CNL_TOGGLE_LIST_ENTRY ToggleList1Entry[16]; ///< Array defining the to= ggle list 1. + UINT16 NumOfEntry2; ///< Defines the number of= entries in toggle list 2. + UINT8 EntrySize2; ///< Defines the size of t= oggle list entry present in list 2. + CNL_TOGGLE_LIST_ENTRY ToggleList2Entry[8]; ///< Array defining the to= ggle list 2. + UINT16 NumOfEntry3; ///< Defines the number of= entries in toggle list 3. + UINT8 EntrySize3; ///< Defines the size of t= oggle list entry present in list 3. + CNL_TOGGLE_LIST_ENTRY ToggleList3Entry[8]; ///< Array defining the to= ggle list 3. + UINT16 NumOfEntry4; ///< Defines the number of= entries in toggle list 4. + UINT8 EntrySize4; ///< Defines the size of t= oggle list entry present in list 4. + CNL_TOGGLE_LIST_ENTRY ToggleList4Entry[8]; ///< Array defining the to= ggle list 4. +} BLOCK31_TOGGLE_LIST; + +/** + This defines the structure of Display device removal configuration entry. +**/ +typedef struct { + /** + Defines the display device configuration to be removed. + Bit 15 =3D EFP4.3 (Reserved for WHL) + Bit 14 =3D EFP3.3 + Bit 13 =3D EFP2.3 + Bit 12 =3D EFP1.3 + Bit 11 =3D EFP4.2 (Reserved for WHL) + Bit 10 =3D EFP3.2 + Bit 9 =3D EFP2.2 + Bit 8 =3D EFP1.2 + Bit 7 =3D LFP2 + Bit 6 =3D EFP2 + Bit 5 =3D EFP3 + Bit 4 =3D EFP4 + Bit 3 =3D LFP + Bit 2 =3D EFP + Bit 1 =3D TV + Bit 0 =3D CRT + **/ + UINT16 DisplayDeviceConfiguration; +} CNL_DISPLAY_CONFIGURATION_ENTRY; + +/** + This defines the structure of Block 32 (Display removal configuration Bl= ock) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the uni= que Block ID =3D 32 + UINT16 BlockSize; ///< Defines the siz= e of Display removal configuration block. + UINT8 NumOfEntry; ///< Defines the num= ber of entries in display removal configuraion table. + UINT8 EntrySize; ///< Defines the siz= e of 1 entry in display removal configuration table. + CNL_DISPLAY_CONFIGURATION_ENTRY RemoveDisplayConfiguration[15]; = ///< Array defining the display removal configuration table. +}BLOCK32_DISPLAY_CONFIGURATION_REMOVAL; + +/** + This defines the Local Flat panel basic details such as resolution and t= he various registers. +**/ +typedef struct { + UINT16 XRes; ///< X resolution of the panel. + UINT16 YRes; ///< Y resolution of the panel. + UINT32 LVDSDigDisReg; ///< MMIO offset of LFP digital display = port register. + UINT32 LVDSDigDisVal; ///< Value of LFP digital display port r= egister. + UINT32 OnSeqDelayReg; ///< MMIO offset of Panel power on seque= ncing delay register. + UINT32 OnSeqDelayVal; ///< Value of Panel power on sequencing = delay register. + UINT32 OffSeqDelayReg; ///< MMIO offset of Panel power off sequ= encing delay register. + UINT32 OffSeqDelayVal; ///< Value of Panel power off sequencing= delay register. + UINT32 CycleDelay_RefDivReg; ///< MMIO offset of Panel power cycle de= lay and reference divider register. + UINT32 CycleDelay_RefDivVal; ///< Value of Panel power cycle delay an= d reference divider register. + UINT16 Terminate; ///< Special value 0xFFFF indicating end= of data. +} FP_DATA; + +/** + This defines the structure consisting of all details for a single Local = Flat panel. +**/ +typedef struct { + FP_DATA FP_Data; ///< Instance of ::FP_DATA structure. + DTD_STRUCTURE DTD_Data; ///< Instance of ::DTD_STRUCTURE which conta= ins the DTD timings for the panel. + PID_DATA PID_Data; ///< Instance of ::PID_DATA structure which = contains panel related information used by driver. +} LVDS_FP_TABLE; + +/** + This structure defines all the details regarding Backlight control for L= FP. +**/ +typedef struct { + /** + Defines the backlight features for the panel. + Bits 7:6 =3D GMBus Speed: + =3D 00, 100 KHz + =3D 01, 50 KHz + =3D 10, 400 KHz + =3D 11, 1 MHz + Bits 5:3 =3D Inverter GPIO Pins + =3D 0, None + =3D 1, I2C GPIO pins + =3D 2, Analog CRT DDC pins + =3D 3, DVI/LVDS DDC GPIO pins + =3D 5, sDVO I2C GPIO pins + Bit 2 =3D Inverter Polarity (i2c & PWM) + =3D 0, Normal (0 =3D Minimum brightness) + =3D 1, Inverted (0 =3D Maximum brightness) + Bits 1:0 =3D BLC Inverter Type + =3D 00, None/External + =3D 01, i2c + =3D 10, PWM + =3D 11, Reserved + **/ + UINT8 BLC_Ftr; + + UINT16 PWM_Freq; ///< PWM inverter frequency in KHz + UINT8 Min_Brightness; ///< Minimum brightness in the range 0-255 + UINT8 I2C_Add; ///< I2C Inverter Slave Address + UINT8 I2C_Command; ///< I2C Inverter command code +} BLC; + +/** + This defines the structure of Block 40 (LFP Features) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 40 + UINT16 BlockSize; ///< Defines the size of LFP Features block. + + UINT8 bmp_Panel_type; ///< Defines the panel type of LFP. + UINT8 Skip1; ///< Obsoleted. + + /** + Capabilities byte: + Bit 15:7 =3D SW Workaround bits + Bit 6 =3D Panel EDID support + =3D 0, Disable + =3D 1, Enable + Bit 5 =3D Pixel dithering + =3D 0, Disable + =3D 1, Enable + Bit 4 =3D Panel Fitting ratio calc. + =3D 0 - Manual + =3D 1 - Automatic + Bit 3 =3D Panel Fitting Graphics mode + =3D 0, Bilinear + =3D 1, Enhanced + Bit 2 =3D Panel Fitting Text mode + =3D 0, Bilinear + =3D 1, Enhanced + Bit 1:0 =3D Panel Fitting Support + =3D 00, No panel fitting + =3D 01, Text panel fitting + =3D 10, GFX panel fitting + =3D 11, Text+GFX panel fitting + **/ + UINT16 bmp_LVDS_Capabilities; + + /** + Defines the channel type of LFP. 2 Bits for each Panel. + Bits [0:1] for Panel #1 + =3D 00, Automatic (algorithm) + =3D 01, Single Channel + =3D 10, Dual Channel + =3D 11, Reserved + **/ + UINT32 INT_LVDS_Panel_Channel_Bits; + + UINT16 Enable_SSC_Bit; ///< LVDS Spread Spectrum Clock + UINT16 SSC_Freq_Bit; ///< LVDS Spread Spectrum Clock Frequency + UINT16 Disable_SSC_DDT_Bit; ///< Disable SSC in Dual Display Twin + + /** + Defines the panel color depth. 1 Bits for each Panel. + Bits[0] for Panel #01 + =3D 0, 18bpp + =3D 1, 24bpp + **/ + UINT16 INT_Panel_Color_Depth; + + /** + Defines the Panel type. 2 Bits for each Panel. + Bits [0:1] for Panel #1 + =3D 00, Static DRRS + =3D 01, D2PO + =3D 10, Seamless + =3D 11, Reserved + **/ + UINT32 DPS_Panel_Type_Bits; + + /** + Defines the type of backlight control for the LFP. 2 bits for each Panel. + Bits [0:1] for Panel #1 + =3D 00, Default + =3D 01, CCFL backlight + =3D 10, LED backlight + =3D 11, Reserved + **/ + UINT32 BLT_Control_Type_Bits; + /** + Defines the LFP power enable flag in S0 state for all 16 panels. 1 Bit f= or Each Panel. + Bits[0] : Panel #1 + 0 : Do not keep LCDVCC on during S0 state. + 1 : Keep LCDVCC on during S0 state. + Bits 1 to 15 are for panel # 2 to 16. + **/ + UINT16 LcdvccOnDuringS0State; +} BLOCK40_LVDS_FEATURES; + +/** + This structure defines the second type of BMP table pointers. + This is used to store pointers to LFP Flat panel data, DTD and PID infor= mation. +**/ +typedef struct { + UINT16 Offset; ///< Offset of the table. + UINT8 Size; ///< Size of the table. +} BMP_TABLE_TYPE2_PTR; + +/** + This structure defines a set of 3 pointers for LFP display. + These pointers point to FP data, DTD and PID information respectively. +**/ +typedef struct { + BMP_TABLE_TYPE2_PTR FpTablePtr; ///< Pointer to FP Data of the LFP p= anel. + BMP_TABLE_TYPE2_PTR DtdTablePtr; ///< Pointer to DTD of the LFP panel. + BMP_TABLE_TYPE2_PTR PidTablePtr; ///< Pointer to the PID data of the = LFP panel. +} LFP_TABLE_POINTERS; + +/** + This defines the structure of Block 41 (LFP Table Pointers for FPDATA, D= TD and PID) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Bl= ock ID:41 + UINT16 BlockSize; ///< Defines the size of L= FP Table Pointer Block. + UINT8 NumOfEntries; ///< Defines the number of= entries in the Table. + LFP_TABLE_POINTERS LfpTablePointers[16]; ///< Array of ::LFP_TABLE_= POINTERS for all 16 panels. + UINT16 LfpPanelNameTableOffset; ///< Offset of LFP panel n= ames table. + UINT8 LfpPanelNameLength; ///< Length of a single LF= P panel's name. +} BLOCK41_LFP_TABLE_POINTERS; + +/** + This defines the structure of Block 42 (Complete LFP Panel Information) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique block ID := 42 + UINT16 BlockSize; ///< Defines the size of Complete = LFP panel information for all 16 panels. + LVDS_FP_TABLE LVDS_FP_Table[16]; ///< Array of ::LVDS_FP_TABLE cont= aining data of 16 panels. + UINT8 LFP_PANEL_NAMES[16][13];///< Array defining the panel name= s for all 16 panels. + + /** + 1 Bit for Each Panel + Bit0 =3D Scaling feature for panel 1. + =3D 0, Scaling feature is disabled for this panel. + =3D 1, Scaling feature is enabled for this panel. + **/ + UINT16 EnableScaling; //This is not used currently + + /** + Array defining DRRS minimum refresh rate. 1 Byte for Each Panel. + **/ + UINT8 Seamless_DRRS_Min_RR[16]; + + /** + Array defining Pixel Overlap Count. 1 Byte for Each Panel. + **/ + UINT8 PixelOverlapCount[16]; +} BLOCK42_LVDS_PANEL_INFO; + +typedef union { + /** + Backlight control parameters.\n + Bits 7:4 : PWM Controller Selection + 0 : Controller 0 + 1 : Controller 1 + 2 : Controller 2 + 3 : Controller 3 + Others : Reserved. + Bits 3:0 : PWM Source Selection + 0 : PMIC PWM + 1 : LPSS PWM + 2 : DISPLAY PWM + 3 : CABC PWM + Others : Reserved. + **/ + UINT8 Value; + struct { + UINT8 PwmSourceSelection:4; + UINT8 PwmControllerSelection:4; + } Bits; +} BKLT_CTRL_PARAMS; + +/** + This defines the structure of Block 43 (LFP Brightness Control) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block = ID : 43 + UINT16 BlockSize; ///< Defines the size of Brigh= tness control block. + + UINT8 SIZE_BLCStruc; ///< Defines the size of singl= e entry in Backlight control table for LFP. + BLC BLC_Struct[16]; ///< Array defining the backli= ght control for 16 LFP panels. + UINT8 Post_Brightness[16]; ///< Array defining the initia= l brightness for all 16 panels. + BKLT_CTRL_PARAMS Brightness_Control[16]; ///< Array defining the bright= ness control method for all 16 panels +} BLOCK43_LVDS_BLC; + +/** + This defines the structure of Block 44 (LFP Power Conservation Features) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique block ID : 44 + UINT16 BlockSize; ///< Defines the size of LFP Power Conservation = Features block. + union { + /** + Bit[7] : ALS Enable/Disable + 0 - Disable + 1 - Enable + Bit[6] : Display LACE support + 0 - Not supported + 1 - Supported + Bit[5] : Default Display LACE enabled status + 0 - Disabled + 1 - Enabled + Bit[4] : Reserved + Bit[3:1] : Power conservation preference level. + 4 is default in a range of 1 to 6. + Bit[0] : Reserved + **/ + UINT8 Value; + struct { + UINT8 Reserved:1; + UINT8 PwrConservation:3; + UINT8 Reserved_1:1; + UINT8 DefalutDisplayLaceEnable:1; + UINT8 DisplayLaceSupport:1; + UINT8 AlsEnable:1; + } Bits; + } LfpFeatureBits; + + UINT16 AlsData[10]; ///< Defines the main ALS data. + + union { + /** + Bit[7:3] : Reserved + Bit[2:0] : Aggressiveness Level Profile. + 000 - Minimum + 001 - Moderate + 010 - High + **/ + UINT8 Value; + struct { + UINT8 AggressionProfileLevel:3; + UINT8 Reserved:5; + } Bits; + } LaceAggressivenessProfile; ///< Defines the LACE Aggressiveness Profile +} BLOCK44_ALS; + +/** + This defines the structure of Black Frame Insertion table entry. +**/ +typedef struct { + /** + BFI Features\n + Bit[7-2] : Reserved\n + Bit[1] : Enable Brightness control in CUI\n + Bit[0] : Enable BFI in driver + **/ + UINT8 EnableBits; + UINT8 BrightnessNonBFI; ///< Brightness percentage in non BFI = mode +} BFI; + +/** + This defines the structure of Block 45 (Black Frame insertion Support fo= r LFP) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Block ID : 45 + UINT16 BlockSize; ///< Defines the size of Black frame= insertion support block. + UINT8 SIZE_BFIStruc; ///< Defines the size of 1 entry of = black frame data. + BFI BFI_Struct[16]; ///< Array defining the data of blac= k frame insertion for all 16 panels. +} BLOCK45_BFI_SUPPORT; + +/** + This structure defines the chromaticity information for a single LFP pan= el. +**/ +typedef struct { + /** + Defines the chromaticity feature enable bits + Bits 7:2 =3D Reserved + Bit 1 =3D Override EDID values for chromaticity if enabled, Instead = Use VBT values + =3D 0, Disable, Use the EDID values + =3D 1, Enable, Use the values from the VBT + Bit 0 =3D Enable chromaticity feature. EDID values will be used when= this feature is enabled. + =3D 0, Disable + =3D 1, Enable + **/ + UINT8 EnableBits; + + UINT8 Red_Green_1; ///< Red/green chormaticity coordinates at E= DID offset 19h + UINT8 Blue_White_1; ///< Blue/white chromatiity coordinates at E= DID offset 1Ah + UINT8 Red_X1; ///< Red x coordinate at EDID offset 1Bh + UINT8 Red_Y1; ///< Red x coordinate at EDID offset 1Ch + UINT8 Green_X1; ///< Green x coordinate at EDID offset 1Dh + UINT8 Green_Y1; ///< Green x coordinate at EDID offset 1Eh + UINT8 Blue_X1; ///< Blue x coordinate at EDID offset 1Fh + UINT8 Blue_Y1; ///< Blue x coordinate at EDID offset 20h + UINT8 White_X1; ///< White x coordinate at EDID offset 21h + UINT8 White_Y1; ///< White x coordinate at EDID offset 22h +} CHROMATICITY; + +/** + This structure defines the Luminance information for a single LFP panel. +**/ +typedef struct { + /** + Defines the chromaticity feature enable bits + Bits 7:2 : Reserved + Bit 1 : Enable Gamma feature. + : if enabled, use gamma values from this block. + 0 : Disable + 1 : Enable + Bit 0 : Enable Luminance feature. + : if enabled, use values from this block. + 0 : Disable + 1 : Enable + **/ + UINT8 EnableBits; + /** + Luminance info (refer DisplayID 2.0) + 2 byte value, encoded in IEEE 754 half-precision binary floating point= format + **/ + UINT16 MinLuminance; ///< Native minimum luminance + UINT16 MaxFullFrameLuminance; ///< Native maximum luminance (Full = Frame) + UINT16 MaxLuminance; ///< Native Maximum Luminance (1% Re= ctangular Coverage) + /** + Gamma EOTF + Gamma values range from 00h through FFh which will come from VBT. + Value shall define the gamma range, from 1.00 to 3.54. + Field Value =3D (Gamma (value from VBT) + 100) / 100 + + FFh =3D No gamma information shall be provided + **/ + UINT8 Gamma; + +}LUMINANCE_AND_GAMMA; + +/** + This defines the structure of Block 46 (Chromaticity Support) +**/ +typedef struct { + UINT8 BlockId; ///< Defines the unique Bloc= k ID : 46 + UINT16 BlockSize; ///< Defines the size of Chr= omaticity Block. + CHROMATICITY Chromaticity_Struct[16]; ///< Defines the chromaticit= y information for all 16 panels. + LUMINANCE_AND_GAMMA Luminance_Gamma_Struct[16]; ///< Defines the lum= ianance information for all 16 panels. +} BLOCK46_CHROMATICITY_SUPPORT; + +/** + This defines the structure of Block 51 (Fixed Mode Set) +**/ +typedef struct{ + UINT8 BlockId; ///< Defines the unique block ID : 51. + UINT16 BlockSize; ///< Defines the size of Fixed mode set feat= ure block. + UINT8 FeatureEnable; ///< Whether the fixed mode set feature is e= nabled/disabled. + UINT32 XRes; ///< X resolution of the fixed mode. + UINT32 YRes; ///< Y resolution of the fixed mode. +} BLOCK51_FIXED_MODE_SET; + +/** + This defines the Complete VBT Structure for generation purpose +**/ +typedef struct { + VBT_HEADER VbtHeader; + VBT_BIOS_DATA_HEADER VbtBdbHeader; + BLOCK254_BMP_Structure Block254BMPStructure; + VBT_GENERAL1_INFO VbtGen1Info; + PRD_BOOT_TABLE PrdBootTable; + VBT_GENERAL2_INFO VbtGen2Info; + BLOCK03_ORIGINAL_DISPLAY_TOGGLE_LIST Block03OriginalDisplayToggleLi= st; + BLOCK252_SBIOS_Hook Block252SbiosHook; + BLOCK06_MMIO_REG_TABLE Block06MmioRegTable; + BLOCK07_IOSWFLAG_REG_TABLE Block07IoswflagRegTable; + BLOCK08_MMIOSWFLAG_REG_TABLE Block08MmioswflagRegTable; + BLOCK09_PSR_FEATURE Block09PsrFeature; + BLOCK10_MODE_REMOVAL_TABLE Block10ModeRemovalTable; + BLOCK12_DRIVER_FEATURES Block12DriverFeatures; + BLOCK13_DRIVER_PERSISTENCE Block13DriverPersistence; + BLOCK17_SV_BITS Block17SvBits; + BLOCK18_DRIVER_ROTATION Block18DriverRotation; + BLOCK20_OEM_CUSTOMIZATION Block20OemCustomization; + BLOCK26_TV_OPTIONS Block26TVOptions; + BLOCK27_EDP_FEATURES Block27EDPFeatures; + BLOCK28_EDIDLESS_EFP Block28EdidlessEFP; + BLOCK31_TOGGLE_LIST Block31ToggleList; + BLOCK32_DISPLAY_CONFIGURATION_REMOVAL Block32DisplayConfigurationRem= oval; + BLOCK40_LVDS_FEATURES Block40LVDSFeatures; + BLOCK41_LFP_TABLE_POINTERS Block41LfpTablePointers; + BLOCK42_LVDS_PANEL_INFO Block42LvdsPanelInfo; + BLOCK43_LVDS_BLC Block43LVDSBlc; + BLOCK44_ALS Block44Als; + BLOCK46_CHROMATICITY_SUPPORT Block46ChromaticitySupport; + BLOCK51_FIXED_MODE_SET Block51FixedModeSet; +} VBT_TABLE_DATA; + +#pragma pack() + +/** + This function will update the VBT checksum. + + @param[in out] VbtPtr - Pointer to VBT table + + @retval none +**/ +VOID +UpdateVbtChecksum( + VBT_TABLE_DATA *VbtPtr +); + +/** + This function will update the VBT. + + @param[in] VbtPtr - Pointer to VBT Table + + @retval none +**/ +VOID +UpdateGopVbt ( + IN VBT_TABLE_DATA *VbtPtr +); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.= h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h new file mode 100644 index 0000000000..5bf2527963 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Guid/TcoWdtHob.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __TCO_WDT_HOB_H__ +#define __TCO_WDT_HOB_H__ + +#define TCO_WDT_HOB_GUID \ + { \ + 0x3e405418, 0xd8c, 0x4f1a, { 0xb0, 0x55, 0xbe, 0xf9, 0x8, 0x41, 0x46, = 0x8d } \ + } + +#ifndef _PEI_HOB_H_ +#ifndef __HOB__H__ +#ifndef __PI_HOB_H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + // + // Guid specific data goes here + // +} EFI_HOB_GUID_TYPE; +#endif +#endif +#endif + +typedef struct { + EFI_HOB_GUID_TYPE Header; + UINT8 TcoRebootHappened; +} TCO_WDT_HOB; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/IoExpander.h b/= Platform/Intel/WhiskeylakeOpenBoardPkg/Include/IoExpander.h new file mode 100644 index 0000000000..671e3c5cde --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/IoExpander.h @@ -0,0 +1,68 @@ +/** @file + GPIO definition table for WhiskeylakeURvp + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IO_EXPANDER_H_ +#define _IO_EXPANDER_H_ + +typedef struct { + UINT32 IoExpanderNumber : 1; // IO Expander Number (0/1) + UINT32 GpioPinNumber : 5; // GPIO Pin Number (0 to 23) + UINT32 GpioDirection : 1; // GPIO Pin Direction (Input/Output) + UINT32 GpioLevel : 1; // GPIO Pin Output Level (High/Low) + UINT32 GpioInversion : 1; // GPIO Pin Inversion (Enabled/Disabled) + UINT32 Reserved : 23; // Reserved +} IO_EXPANDER_GPIO_CONFIG; + +//WHL PCH LP GPIO Expander Number +#define IO_EXPANDER_0 0 +#define IO_EXPANDER_1 1 + +//WHL PCH LP GPIO Pin Mapping +#define IO_EXPANDER_GPIO_0 0 // P00 +#define IO_EXPANDER_GPIO_1 1 // P01 +#define IO_EXPANDER_GPIO_2 2 // P02 +#define IO_EXPANDER_GPIO_3 3 // P03 +#define IO_EXPANDER_GPIO_4 4 // P04 +#define IO_EXPANDER_GPIO_5 5 // P05 +#define IO_EXPANDER_GPIO_6 6 // P06 +#define IO_EXPANDER_GPIO_7 7 // P07 +#define IO_EXPANDER_GPIO_8 8 // P10 +#define IO_EXPANDER_GPIO_9 9 // P11 +#define IO_EXPANDER_GPIO_10 10 // P12 +#define IO_EXPANDER_GPIO_11 11 // P13 +#define IO_EXPANDER_GPIO_12 12 // P14 +#define IO_EXPANDER_GPIO_13 13 // P15 +#define IO_EXPANDER_GPIO_14 14 // P16 +#define IO_EXPANDER_GPIO_15 15 // P17 +#define IO_EXPANDER_GPIO_16 16 // P20 +#define IO_EXPANDER_GPIO_17 17 // P21 +#define IO_EXPANDER_GPIO_18 18 // P22 +#define IO_EXPANDER_GPIO_19 19 // P23 +#define IO_EXPANDER_GPIO_20 20 // P24 +#define IO_EXPANDER_GPIO_21 21 // P25 +#define IO_EXPANDER_GPIO_22 22 // P26 +#define IO_EXPANDER_GPIO_23 23 // P27 + +//WHL PCH LP GPIO Expander GPIO Direction +#define IO_EXPANDER_GPIO_OUTPUT 0 +#define IO_EXPANDER_GPIO_INPUT 1 + +//WHL PCH LP GPIO Expaner GPIO Output Level +#define IO_EXPANDER_GPO_LEVEL_LOW 0 +#define IO_EXPANDER_GPO_LEVEL_HIGH 1 + +//WHL PCH LP GPIO Expaner GPIO Inversion Status +#define IO_EXPANDER_GPI_INV_DISABLED 0 +#define IO_EXPANDER_GPI_INV_ENABLED 1 +#define IO_EXPANDER_GPIO_RESERVED 0x00 + +//GPIO Table Terminator +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeCpuP= olicyUpdateLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/D= xeCpuPolicyUpdateLib.h new file mode 100644 index 0000000000..5d5fba47ad --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeCpuPolicyUp= dateLib.h @@ -0,0 +1,75 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_CPU_POLICY_UPDATE_LIB_H_ +#define _DXE_CPU_POLICY_UPDATE_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include + +/** + + This function prints the CPU DXE phase policy. + + @param[in] DxeCpuPolicy - CPU DXE Policy protocol + +**/ +VOID +CpuDxePrintPolicyProtocol ( + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ); + +/** + +Routine Description: + + This function updates Dxe Cpu Policy Protocol + +Arguments: + + @param[in] DxeCpuPolicy The Cpu Policy protocol instance + +Returns: + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by th= is driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to = initialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnor= mally. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSiCpuPolicy ( + IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ); + +/** + + CpuInstallPolicyProtocol installs CPU Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol= instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +CpuInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeMePo= licyUpdateLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Dx= eMePolicyUpdateLib.h new file mode 100644 index 0000000000..9b960159ba --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeMePolicyUpd= ateLib.h @@ -0,0 +1,27 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_ME_POLICY_UPDATE_LIB_H_ +#define _DXE_ME_POLICY_UPDATE_LIB_H_ + +/** + Update the ME Policy Library + + @param[in] DxeMePolicy The pointer to get ME Policy proto= col instance + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by this= driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to in= itialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnorma= lly. + +**/ +EFI_STATUS +UpdateDxeMePolicy ( + IN OUT ME_POLICY_PROTOCOL *DxeMePolicy + ); + +#endif // _DXE_ME_POLICY_UPDATE_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePchP= olicyUpdateLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/D= xePchPolicyUpdateLib.h new file mode 100644 index 0000000000..84db68e65c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePchPolicyUp= dateLib.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_PCH_POLICY_UPDATE_LIB_H_ +#define _DXE_PCH_POLICY_UPDATE_LIB_H_ + +/** + Get data for platform policy from setup options. + + @param[in] PchPolicy The pointer to get PCH Policy protoco= l instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxePchPolicy ( + IN OUT PCH_POLICY_PROTOCOL *PchPolicy + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePoli= cyBoardConfigLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library= /DxePolicyBoardConfigLib.h new file mode 100644 index 0000000000..3bb941235c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxePolicyBoard= ConfigLib.h @@ -0,0 +1,30 @@ +/** @file + Header file for the DxePolicyBoardConfig Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_POLICY_BOARD_CONFIG_LIB_H_ +#define _DXE_POLICY_BOARD_CONFIG_LIB_H_ + +#include +#include + +/** + This function performs DXE SA Policy update by board configuration. + + @param[in, out] DxeSaPolicy DXE SA Policy + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicyBoardConfig ( + IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeSaPo= licyUpdateLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Dx= eSaPolicyUpdateLib.h new file mode 100644 index 0000000000..4279c0c6f1 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/DxeSaPolicyUpd= ateLib.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SA_POLICY_UPDATE_LIB_H_ +#define _DXE_SA_POLICY_UPDATE_LIB_H_ + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protocol = instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/FspPoli= cyInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/FspPol= icyInitLib.h new file mode 100644 index 0000000000..4709179ac6 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/FspPolicyInitL= ib.h @@ -0,0 +1,29 @@ +/** @file + Function prototype of FspPolicyInitLib. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _FSP_POLICY_INIT_LIB_H_ +#define _FSP_POLICY_INIT_LIB_H_ + +#include +#include +#include + +VOID +EFIAPI +FspPolicyInitPreMem ( + IN FSPM_UPD *FspmUpdDataPtr + ); + +VOID +EFIAPI +FspPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +#endif // _FSP_POLICY_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioChe= ckConflictLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Gp= ioCheckConflictLib.h new file mode 100644 index 0000000000..ba73cad63b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioCheckConfl= ictLib.h @@ -0,0 +1,46 @@ +/** @file + Header file for check Gpio PadMode conflict. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_CHECK_CONFLICT_LIB_H_ +#define _GPIO_CHECK_CONFLICT_LIB_H_ + +#include +#include +#include + +extern EFI_GUID gGpioCheckConflictHobGuid; + +typedef struct { + GPIO_PAD GpioPad; + UINT32 GpioPadMode:5; + UINT32 Reserved:27; +} GPIO_PAD_MODE_INFO; + +/** + Check Gpio PadMode conflict and report it. +**/ +VOID +GpioCheckConflict ( + VOID + ); + +/** + This libaray will create one Hob for each Gpio config table + without PadMode is GpioHardwareDefault + + @param[in] GpioDefinition Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries +**/ +VOID +CreateGpioCheckConflictHob ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ); + +#endif // _GPIO_CHECK_CONFLICT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioExp= anderLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioExp= anderLib.h new file mode 100644 index 0000000000..40ea4abc3d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/GpioExpanderLi= b.h @@ -0,0 +1,123 @@ +/** @file + Support for IO expander TCA6424. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_EXPANDER_LIB_H_ +#define _GPIO_EXPANDER_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include + +/** + Set the Direction value for the given Expander Gpio pin. + + This function is to Set the direction value for the GPIO + Pin within the giving Expander. + + @param[in] Expander Expander Value with in the Contoller + @param[in] Pin Pin with in the Expnader Value + @param[in] Value none +**/ +VOID +GpioExpSetDirection ( + IN UINT8 Expander, + IN UINT8 Pin, + IN UINT8 Direction + ); +/** + Set the input value for the given Expander Gpio pin. + + This function is to get the input value for the GPIO + Pin within the giving Expander. + + @param[in] Expander Expander Value with in the Contoller + @param[in] Pin Pin with in the Expnader Value + @param[in] Value none + +**/ +VOID +GpioExpSetPolarity ( + IN UINT8 Expander, + IN UINT8 Pin, + IN UINT8 Polarity + ); +/** + Set the Output value for the given Expander Gpio pin. + + This function is to Set the Output value for the GPIO + Pin within the giving Expander. + + @param[in] Expander Expander Value with in the Contoller + @param[in] Pin Pin with in the Expnader Value + @param[in] Value none + +**/ +VOID +GpioExpSetOutput ( + IN UINT8 Expander, + IN UINT8 Pin, + IN UINT8 Value + ); +/** + Returns the data from register value giving in the input. + + This function is to get the data from the Expander + Registers by following the I2C Protocol communication + + + @param[in] Bar0 Bar address of the SerialIo Controller + @param[in] Address Expander Value with in the Contoller + @param[in] Register Address of Input/Output/Configure/Polarity + registers with in the Expander + + @retval UINT8 Value returned from the register +**/ +UINT8 +GpioExpGetInput ( + IN UINT8 Expander, + IN UINT8 Pin + ); + +/** + Configures all registers of a single IO Expander in one go. + + @param[in] Expander Expander number (0/1) + @param[in] Direction Bit-encoded direction values. BIT0 is for pin0, = etc. 0=3Doutput, 1=3Dinput + @param[in] Polarity Bit-encoded input inversion values. BIT0 is for = pin0, etc. 0=3Dnormal, 1=3Dinversion + @param[in] Output Bit-encoded output state, ignores polarity, only= applicable if direction=3DINPUT. BIT0 is for pin0, etc. 0=3Dlow, 1=3Dhigh + +**/ +VOID +GpioExpBulkConfig ( + IN UINT8 Expander, + IN UINT32 Direction, + IN UINT32 Polarity, + IN UINT32 Output + ); + +/** + Returns the Controller on which GPIO expander is present. + + This function returns the Controller value + + @param[out] Controller Pointer to a Controller value on + which I2C expander is configured. + + @retval EFI_SUCCESS non. +**/ +EFI_STATUS +GpioExpGetController ( + OUT UINT8 *Controller + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/HdaVerb= TableLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/HdaVerb= TableLib.h new file mode 100644 index 0000000000..f08c88f114 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/HdaVerbTableLi= b.h @@ -0,0 +1,48 @@ +/** @file + + Header file for the Intel HD Audio Verb Table library. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _HDA_VERB_TABLE_LIB_H_ +#define _HDA_VERB_TABLE_LIB_H_ + +#include +#include + +enum HDAUDIO_CODEC_SELECT { + PchHdaCodecPlatformOnboard =3D 0, + PchHdaCodecExternalKit =3D 1 +}; + +/** + Add verb table function. + This function update the verb table number and verb table ptr of policy. + + @param[in] HdAudioConfig HD Audio config block + @param[out] VerbTableEntryNum Number of verb table entries + @param[out] HdaVerbTablePtr Pointer to the verb table +**/ +VOID +AddPlatformVerbTables ( + IN UINT8 CodecType, + OUT UINT8 *VerbTableEntryNum, + OUT UINT32 *HdaVerbTablePtr + ); + +/** + HDA VerbTable init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +HdaVerbTableInit( + IN UINT16 BoardId + ); + +#endif \ No newline at end of file diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/I2cAcce= ssLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/I2cAccessL= ib.h new file mode 100644 index 0000000000..cec045091b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/I2cAccessLib.h @@ -0,0 +1,34 @@ +/** @file + Support for IO expander TCA6424. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _I2C_ACCESS_LIB_H_ +#define _I2C_ACCESS_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include + +#define WAIT_1_SECOND 1600000000 //1.6 * 10^9 + +EFI_STATUS +I2cWriteRead ( + IN UINTN MmioBase, + IN UINT8 SlaveAddress, + IN UINT8 WriteLength, + IN UINT8 *WriteBuffer, + IN UINT8 ReadLength, + IN UINT8 *ReadBuffer, + IN UINT64 TimeBudget + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPlat= formLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPlatf= ormLib.h new file mode 100644 index 0000000000..d65586dbb9 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPlatformLib= .h @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PLATFORM_LIB_H_ +#define _PEI_PLATFORM_LIB_H_ + + + +#define PEI_DEVICE_DISABLED 0 +#define PEI_DEVICE_ENABLED 1 + +typedef struct { + UINT8 Register; + UINT32 Value; +} PCH_GPIO_DEV; + +// +// GPIO Initialization Data Structure +// +typedef struct{ + PCH_GPIO_DEV Use_Sel; + PCH_GPIO_DEV Use_Sel2; + PCH_GPIO_DEV Use_Sel3; + PCH_GPIO_DEV Io_Sel; + PCH_GPIO_DEV Io_Sel2; + PCH_GPIO_DEV Io_Sel3; + PCH_GPIO_DEV Lvl; + PCH_GPIO_DEV Lvl2; + PCH_GPIO_DEV Lvl3; + PCH_GPIO_DEV Inv; + PCH_GPIO_DEV Blink; + PCH_GPIO_DEV Rst_Sel; + PCH_GPIO_DEV Rst_Sel2; +} GPIO_INIT_STRUCT; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPoli= cyBoardConfigLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library= /PeiPolicyBoardConfigLib.h new file mode 100644 index 0000000000..fe947482dc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPolicyBoard= ConfigLib.h @@ -0,0 +1,141 @@ +/** @file + Header file for the PeiPolicyBoardConfig Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_POLICY_BOARD_CONFIG_LIB_H_ +#define _PEI_POLICY_BOARD_CONFIG_LIB_H_ + +#include + +/** + This function performs PEI CPU Pre-Memory Policy update by board configu= ration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + This function performs PEI ME Pre-Memory Policy update by board configur= ation. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + This function performs PEI PCH Pre-Memory Policy update by board configu= ration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + This function performs PEI SA Pre-Memory Policy update by board configur= ation. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); + +/** + This function performs PEI CPU Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs PEI ME Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs PEI PCH Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs PEI SA Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +/** + This function performs PEI SI Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPoli= cyInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPol= icyInitLib.h new file mode 100644 index 0000000000..15db1f1fbc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PeiPolicyInitL= ib.h @@ -0,0 +1,38 @@ +/** @file + Header file for the PolicyInitPei Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _POLICY_INIT_PEI_LIB_H_ +#define _POLICY_INIT_PEI_LIB_H_ + +/** + Initialize Intel PEI Platform Policy + + @param[in] FirmwareConfiguration It uses to skip specific policy init = that depends + on the 'FirmwareConfiguration' varaib= le. +**/ +VOID +EFIAPI +PeiPolicyInitPreMem ( + IN UINT8 FirmwareConfiguration + ); + +/** + Initialize Intel PEI Platform Policy + + @param[in] PeiServices General purpose services available to = every PEIM. + @param[in] FirmwareConfiguration It uses to skip specific policy init t= hat depends + on the 'FirmwareConfiguration' varaibl= e. +**/ +VOID +EFIAPI +PeiPolicyInit ( +// IN CONST EFI_PEI_SERVICES **PeiServices, + IN UINT8 FirmwareConfiguration + ); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Platfor= mInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/Platfor= mInitLib.h new file mode 100644 index 0000000000..f0da2db968 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Library/PlatformInitLi= b.h @@ -0,0 +1,23 @@ +/** @file + Function prototype of PlatformInitLib. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INIT_LIB_H_ +#define _PLATFORM_INIT_LIB_H_ + +VOID +PlatformLateInit ( + VOID + ); + +VOID +InitSerialPort ( + VOID + ); + +#endif // _PLATFORM_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PchHsioPtssTabl= es.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PchHsioPtssTables.h new file mode 100644 index 0000000000..8bf7deaa0c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PchHsioPtssTables.h @@ -0,0 +1,51 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef PCH_HSIO_PTSSTABLES_H_ +#define PCH_HSIO_PTSSTABLES_H_ + +#include + +/// +/// SATA PTSS Topology Types +/// +typedef enum { + PchSataTopoUnknown =3D 0x00, + PchSataTopoIsata, + PchSataTopoDirectConnect, + PchSataTopoFlex, + PchSataTopoM2 +} PCH_SATA_TOPOLOGY; + +/// +/// PCIe PTSS Topology Types +/// +typedef enum { + PchPcieTopoUnknown =3D 0x00, + PchPcieTopox1, + PchPcieTopox4, + PchPcieTopoSataE, + PchPcieTopoM2 +} PCH_PCIE_TOPOLOGY; + +/// +/// The PCH_SBI_PTSS_HSIO_TABLE block describes HSIO PTSS settings for PCH. +/// +typedef struct { + UINT8 LaneNum; + UINT8 PhyMode; + UINT16 Offset; + UINT32 Value; + UINT32 BitMask; +} PCH_SBI_PTSS_HSIO_TABLE; + +typedef struct { + PCH_SBI_PTSS_HSIO_TABLE PtssTable; + UINT16 Topology; +} HSIO_PTSS_TABLES; + +#endif // PCH_HSIO_PTSSTABLES_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverr= ideTable.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverr= ideTable.h new file mode 100644 index 0000000000..395d08779c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTabl= e.h @@ -0,0 +1,106 @@ +/** @file + PCIe Device Override Table + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _PCIE_DEVICE_OVERRIDE_TABLE_H_ +#define _PCIE_DEVICE_OVERRIDE_TABLE_H_ + +#include +#include + +#define PCI_CLASS_NETWORK 0x02 +#define PCI_CLASS_NETWORK_ETHERNET 0x00 +#define PCI_CLASS_NETWORK_OTHER 0x80 + +GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = =3D { + // + // Intel PRO/Wireless + // + { 0x8086, 0x422b, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x422c, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4238, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x4239, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WiMAX/WiFi Link + // + { 0x8086, 0x0082, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0085, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0083, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0084, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0086, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0087, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0088, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0089, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x008F, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0090, 0xff, 0xff, 0xff, PchPcieAspmL1, PchPcieL1L2Override, = 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak WLAN NIC + // + { 0x8086, 0x08AE, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08AF, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Crane Peak w/BT WLAN NIC + // + { 0x8086, 0x0896, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0897, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Kelsey Peak WiFi, WiMax + // + { 0x8086, 0x0885, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0886, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 105 + // + { 0x8086, 0x0894, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0895, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 135 + // + { 0x8086, 0x0892, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0893, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2200 + // + { 0x8086, 0x0890, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0891, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 2230 + // + { 0x8086, 0x0887, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x0888, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel Centrino Wireless-N 6235 + // + { 0x8086, 0x088E, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x088F, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel CampPeak 2 Wifi + // + { 0x8086, 0x08B5, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8086, 0x08B6, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + // + // Intel WilkinsPeak 1 Wifi + // + { 0x8086, 0x08B3, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, + { 0x8086, 0x08B4, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, + // + // Intel Wilkins Peak 2 Wifi + // + { 0x8086, 0x08B1, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, + { 0x8086, 0x08B2, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2AndL1SubstatesOverride, 0x0158, 0x0000000F, 0, 0, 0, = 0, 0 }, + // + // Intel Wilkins Peak PF Wifi + // + { 0x8086, 0x08B0, 0xff, PCI_CLASS_NETWORK, PCI_CLASS_NETWORK_OTHER, PchP= cieAspmL1, PchPcieL1L2Override, 0, 0, 0, 0, 0, 0, 0 }, + + // + // End of Table + // + { 0 } +}; + +#endif diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Platform.h b/Pl= atform/Intel/WhiskeylakeOpenBoardPkg/Include/Platform.h new file mode 100644 index 0000000000..ea96227e3d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Platform.h @@ -0,0 +1,33 @@ +/** @file + This header file provides platform specific definitions used + by other modules for platform specific initialization. + This is not suitable for consumption by ASL or VRF files. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_H_ +#define _PLATFORM_H_ + +//#include "CommonDefinitions.h" +#include "PchAccess.h" +#include "SaAccess.h" + +// +// Need minimum of 48MB during PEI phase for IAG and some buffer for boot. +// +#define PEI_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) = // 80MB + 256MB +#define PEI_RECOVERY_MIN_MEMORY_SIZE (10 * 0x800000 + 0x10000000) = // 80MB + 256MB + +#define FLASH_BLOCK_SIZE 0x10000 + +#define CPU_EXTERNAL_CLOCK_FREQ 0x64 +#define CPU_FREQUENCY_MODE_100 0x64 +#define FREQUENCY_RESOLUTION_3182 0xc6e +#define NDIVIDER_BASE_VALUE 0x19d +#define MDIVIDER_VALUE_13 0xd + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PlatformBoardId= .h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PlatformBoardId.h new file mode 100644 index 0000000000..3545b2a05c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PlatformBoardId.h @@ -0,0 +1,29 @@ +/** @file +Defines Platform BoardIds + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_BOARD_ID_H_ +#define _PLATFORM_BOARD_ID_H_ + +#define FlavorUnknown 0x0 +#define FlavorMobile 0x1 +#define FlavorDesktop 0x2 +#define FlavorWorkstation 0x3 +#define FlavorUpServer 0x4 +#define FlavorEmbedded 0x5 +#define FlavorPlatformMax 0x6 + +#define TypeUnknown 0x0 +#define TypeTrad 0x1 +#define TypeUltUlx 0x2 + +#define BoardIdWhiskeyLakeRvp 0x60 + +#define BoardIdUnknown1 0xffff + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Protocol/Global= NvsArea.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Protocol/GlobalN= vsArea.h new file mode 100644 index 0000000000..b64cfff9a2 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Protocol/GlobalNvsArea= .h @@ -0,0 +1,47 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GLOBAL_NVS_AREA_H_ +#define _GLOBAL_NVS_AREA_H_ + +// +// Includes +// +#define GLOBAL_NVS_DEVICE_ENABLE 1 +#define GLOBAL_NVS_DEVICE_DISABLE 0 + +// +// Forward reference for pure ANSI compatibility +// + +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL EFI_GLOBAL_NVS_AREA_PROTOCOL; + +// +// Global NVS Area Protocol GUID +// +#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \ +{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xd= c } + +#define GLOBAL_NVS_AREA_REVISION 16 +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid; + +// +// Global NVS Area definition +// +#include + +// +// Global NVS Area Protocol +// +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL { + EFI_GLOBAL_NVS_AREA *Area; +} EFI_GLOBAL_NVS_AREA_PROTOCOL; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Setup.h b/Platf= orm/Intel/WhiskeylakeOpenBoardPkg/Include/Setup.h new file mode 100644 index 0000000000..6dd6795a52 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Setup.h @@ -0,0 +1,144 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __SETUP__H__ +#define __SETUP__H__ + +#ifndef MDEPKG_NDEBUG +#define DEBUG_INTERFACE_FORM_ENABLE +#endif // MDEPKG_NDEBUG +// +// Form class guid for the forms those will be showed on first front page. +// +#define FRONT_PAGE_GUID { 0xe58809f8, 0xfbc1, 0x48e2, { 0x88, 0x3a,= 0xa3, 0xf, 0xdc, 0x4b, 0x44, 0x1e } } +// +// Form class guid for the forms those will be showed on boot maintenance = manager menu. +// +#define BOOT_MAINTENANCE_GUID { 0xb2dedc91, 0xd59f, 0x48d2, { 0x89, 0x8a,= 0x12, 0x49, 0xc, 0x74, 0xa4, 0xe0 } } + +// VFR common Definitions +#define INVENTORY(Name,Value) \ + text \ + help =3D STRING_TOKEN(STR_EMPTY), \ + text =3D Name, \ + text =3D Value, \ + flags =3D 0, \ + key =3D 0; + +#define SUBTITLE(Text) subtitle text =3D Text; +#define SEPARATOR SUBTITLE(STRING_TOKEN(STR_EMPTY)) + +#define INTERACTIVE_TEXT(HelpToken, CaptionToken, ValueToken, Key)\ + grayoutif TRUE;\ + oneof varid =3D SETUP_DATA.InteractiveText,\ + questionid =3D Key,\ + prompt =3D CaptionToken,\ + help =3D HelpToken,\ + option text =3D ValueToken, value =3D 0, flags =3D INTERACTIVE = | DEFAULT;\ + refresh interval =3D 1 \ + endoneof;\ + endif; + +#define SUPPRESS_GRAYOUT_ENDIF endif; endif; +#define DEFAULT_FLAG + +#define SYSTEM_ACCESS_KEY_ID 0xF000 +// +// System Access defintions. +// +#define SYSTEM_ACCESS_GUID \ + { 0xE770BB69, 0xBCB4, 0x4D04, { 0x9E, 0x97, 0x23, 0xFF, 0x94, 0x56, 0xFE,= 0xAC }} + +#define SYSTEM_PASSWORD_ADMIN 0 +#define SYSTEM_PASSWORD_USER 1 +#define ADMIN_PW_CLEAR 0 +#define ADMIN_PW_SET 1 + + +typedef struct _SYSTEM_ACCESS +{ + // + // Passwords + // + UINT8 Access; +} SYSTEM_ACCESS; + +// +// Record the password status. +// +typedef struct { + UINT8 AdminName; + UINT8 UserName; +} EFI_PASSWORD_STATUS; + +// +// Config Data +// +typedef struct { + UINT8 SerialDebug; + UINT8 SerialDebugBaudRate; + UINT8 RamDebugInterface; + UINT8 UartDebugInterface; + UINT8 Usb3DebugInterface; + UINT8 SerialIoDebugInterface; + UINT8 TraceHubDebugInterface; +} DEBUG_CONFIG_DATA; + +// +// Config Data Hob +// +#define DEBUG_CONFIG_DATA_HOB DEBUG_CONFIG_DATA + +// +// Secure Boot Data +// +typedef struct{ + UINT8 SecureBoot; +} SECURE_BOOT_VARIABLE; + +#pragma pack() + +// +// Varstore statement +// Setup is EfiVarStore that is related to EFI variable with attribute 0x07 +// (EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARI= ABLE_RUNTIME_ACCESS) +// +#define SETUP_DATA_VARSTORE\ + efivarstore SETUP_DATA, varid =3D 1,\ + attribute =3D 0x7, name =3D Setup, guid =3D SETUP_GUID; +#define SA_SETUP_VARSTORE\ + efivarstore SA_SETUP, varid =3D 2,\ + attribute =3D 0x7, name =3D SaSetup, guid =3D SA_SETUP_GUID; +#define CPU_SETUP_VARSTORE\ + efivarstore CPU_SETUP, varid =3D 3,\ + attribute =3D 0x7, name =3D CpuSetup, guid =3D CPU_SETUP_GUID; +#define ME_SETUP_VARSTORE\ + efivarstore ME_SETUP, varid =3D 4,\ + attribute =3D 0x7, name =3D MeSetup, guid =3D ME_SETUP_GUID; +#define PCH_SETUP_VARSTORE\ + efivarstore PCH_SETUP, varid =3D 5,\ + attribute =3D 0x7, name =3D PchSetup, guid =3D PCH_SETUP_GUID; +#define SI_SETUP_VARSTORE\ + efivarstore SI_SETUP, varid =3D 6,\ + attribute =3D 0x7, name =3D SiSetup, guid =3D SI_SETUP_GUID; +#ifdef DEBUG_INTERFACE_FORM_ENABLE +#define DEBUG_CONFIG_DATA_ID 0xF001 +#define DEBUG_CONFIG_DATA_VARSTORE\ + efivarstore DEBUG_CONFIG_DATA, varid =3D DEBUG_CONFIG_DATA_ID,\ + attribute =3D 0x7, name =3D DebugConfigData, guid =3D DEBUG_CONFIG= _GUID; +#endif // DEBUG_INTERFACE_FORM_ENABLE +#define SYSTEM_ACCESS_VARSTORE\ + varstore SYSTEM_ACCESS, varid =3D SYSTEM_ACCESS_KEY_ID,\ + name =3D SystemAccess, guid =3D SYSTEM_ACCESS_GUID; +#define SYSTEM_PASSWORD_VARSTORE\ + varstore EFI_PASSWORD_STATUS,\ + name =3D PasswordStatus, guid =3D SYSTEM_ACCESS_GUID; + +#define BOOT_FLOW_CONDITION_RECOVERY 2 +#define BOOT_FLOW_CONDITION_FIRST_BOOT 4 + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/SioRegs.h b/Pla= tform/Intel/WhiskeylakeOpenBoardPkg/Include/SioRegs.h new file mode 100644 index 0000000000..4ce85de5bd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/SioRegs.h @@ -0,0 +1,157 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SIO_REG_H_ +#define _SIO_REG_H_ + +#define REG_LOGICAL_DEVICE 0x07 +#define ACTIVATE 0x30 + +#define BASE_ADDRESS_HIGH0 0x60 +#define BASE_ADDRESS_LOW0 0x61 +#define BASE_ADDRESS_HIGH1 0x62 +#define BASE_ADDRESS_LOW1 0x63 +#define BASE_ADDRESS_HIGH2 0x64 +#define BASE_ADDRESS_LOW2 0x65 +#define BASE_ADDRESS_HIGH3 0x66 +#define BASE_ADDRESS_LOW3 0x67 +#define PRIMARY_INTERRUPT_SELECT 0x70 +#define WAKEUP_ON_IRQ_EN 0x70 +#define INTERRUPT_TYPE 0x71 +#define DMA_CHANNEL_SELECT0 0x74 +#define DMA_CHANNEL_SELECT1 0x75 + + + +// +//Port address for PILOT - III +// +#define PILOTIII_CHIP_ID 0x03 +#define PILOTIII_SIO_INDEX_PORT 0x04E +#define PILOTIII_SIO_DATA_PORT (PILOTIII_SIO_INDEX_PORT+1) + +#define PILOTIII_UNLOCK 0x5A +#define PILOTIII_LOCK 0xA5 + +// +// logical device in PILOT-III +// +#define PILOTIII_SIO_PSR 0x00 +#define PILOTIII_SIO_COM2 0x01 +#define PILOTIII_SIO_COM1 0x02 +#define PILOTIII_SIO_SWCP 0x03 +#define PILOTIII_SIO_GPIO 0x04 +#define PILOTIII_SIO_WDT 0x05 +#define PILOTIII_SIO_KCS3 0x08 +#define PILOTIII_SIO_KCS4 0x09 +#define PILOTIII_SIO_KCS5 0x0A +#define PILOTIII_SIO_BT 0x0B +#define PILOTIII_SIO_SMIC 0x0C +#define PILOTIII_SIO_MAILBOX 0x0D +#define PILOTIII_SIO_RTC 0x0E +#define PILOTIII_SIO_SPI 0x0F +#define PILOTIII_SIO_TAP 0x10 +// +// Regisgers for Pilot-III +// +#define PILOTIII_CHIP_ID_REG 0x20 +#define PILOTIII_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define PILOTIII_ACTIVATE ACTIVATE +#define PILOTIII_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define PILOTIII_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define PILOTIII_BASE_ADDRESS_HIGH1 BASE_ADDRESS_HIGH1 +#define PILOTIII_BASE_ADDRESS_LOW1 BASE_ADDRESS_LOW1 +#define PILOTIII_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT + +// +// Port address for PC8374 +// +#define PC8374_SIO_INDEX_PORT 0x02E +#define PC8374_SIO_DATA_PORT (PC8374_SIO_INDEX_PORT+1) + +// +// Logical device in PC8374 +// +#define PC8374_SIO_FLOPPY 0x00 +#define PC8374_SIO_PARA 0x01 +#define PC8374_SIO_COM2 0x02 +#define PC8374_SIO_COM1 0x03 +#define PC8374_SIO_MOUSE 0x05 +#define PC8374_SIO_KYBD 0x06 +#define PC8374_SIO_GPIO 0x07 + +// +// Registers specific for PC8374 +// +#define PC8374_CLOCK_SELECT 0x2D +#define PC8374_CLOCK_CONFIG 0x29 + +// +// Registers for PC8374 +// +#define PC8374_LOGICAL_DEVICE REG_LOGICAL_DEVICE +#define PC8374_ACTIVATE ACTIVATE +#define PC8374_BASE_ADDRESS_HIGH0 BASE_ADDRESS_HIGH0 +#define PC8374_BASE_ADDRESS_LOW0 BASE_ADDRESS_LOW0 +#define PC8374_PRIMARY_INTERRUPT_SELECT PRIMARY_INTERRUPT_SELECT +#define PC8374_DMA_CHANNEL_SELECT DMA_CHANNEL_SELECT0 + +#define PC87427_SERVERIO_CNF2 0x22 + + +// +// Pilot III Mailbox Data Register definitions +// +#define MBDAT00_OFFSET 0x00 +#define MBDAT01_OFFSET 0x01 +#define MBDAT02_OFFSET 0x02 +#define MBDAT03_OFFSET 0x03 +#define MBDAT04_OFFSET 0x04 +#define MBDAT05_OFFSET 0x05 +#define MBDAT06_OFFSET 0x06 +#define MBDAT07_OFFSET 0x07 +#define MBDAT08_OFFSET 0x08 +#define MBDAT09_OFFSET 0x09 +#define MBDAT10_OFFSET 0x0A +#define MBDAT11_OFFSET 0x0B +#define MBDAT12_OFFSET 0x0C +#define MBDAT13_OFFSET 0x0D +#define MBDAT14_OFFSET 0x0E +#define MBDAT15_OFFSET 0x0F +#define MBST0_OFFSET 0x10 +#define MBST1_OFFSET 0x11 +#define MBBINT_OFFSET 0x12 + +// +// Mailbox Bit definitions... +// +#define MBBINT_MBBIST_BIT 0x80 +// If both are there, use the default one +// +#define W83527_EXIST BIT2 +#define PC8374_EXIST BIT1 +#define PILOTIII_EXIST BIT0 +#define DEFAULT_SIO PILOTIII_EXIST +#define DEFAULT_KDB PC8374_EXIST + +#define IPMI_DEFAULT_SMM_IO_BASE 0xca2 +// +// For Pilot III +// + +#define PILOTIII_SWC_BASE_ADDRESS 0xA00 +#define PILOTIII_PM1b_EVT_BLK_BASE_ADDRESS 0x0A80 +#define PILOTIII_PM1b_CNT_BLK_BASE_ADDRESS 0x0A84 +#define PILOTIII_GPE1_BLK_BASE_ADDRESS 0x0A86 +#define PILOTIII_KCS3_DATA_BASE_ADDRESS 0x0CA4 +#define PILOTIII_KCS3_CMD_BASE_ADDRESS 0x0CA5 +#define PILOTIII_KCS4_DATA_BASE_ADDRESS 0x0CA2 +#define PILOTIII_KCS4_CMD_BASE_ADDRESS 0x0CA3 +#define PILOTIII_MAILBOX_BASE_ADDRESS 0x0600 +#define PILOTIII_MAILBOX_MASK 0xFFE0 +#define BMC_KCS_BASE_ADDRESS 0x0CA0 +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvs.= asl b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl new file mode 100644 index 0000000000..af753e1dce --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Include/Acpi/GlobalNvs.asl @@ -0,0 +1,112 @@ +/** @file + ACPI DSDT table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + // Define a Global region of ACPI NVS Region that may be used for any + // type of implementation. The starting offset and size will be fixed + // up by the System BIOS during POST. Note that the Size must be a word + // in size to be fixed up correctly. + + OperationRegion(GNVS,SystemMemory,0xFFFF0000,0xAA55) + Field(GNVS,AnyAcc,Lock,Preserve) + { + // + // Miscellaneous Dynamic Registers: + // + Offset(0), OSYS, 16, // Offset(0), Operating System + Offset(2), SMIF, 8, // Offset(2), SMI Function Call (ASL to SM= I via I/O Trap) + Offset(3), P80D, 32, // Offset(3), Port 80 Debug Port Value + Offset(7), PWRS, 8, // Offset(7), Power State (AC Mode =3D 1) + // + // Thermal Policy Registers: + // + Offset(8), DTSE, 8, // Offset(8), Digital Thermal Sensor Enable + Offset(9), DTSF, 8, // Offset(9), DTS SMI Function Call + // + // CPU Identification Registers: + // + Offset(10), APIC, 8, // Offset(10), APIC Enabled by SBIOS (APIC = Enabled =3D 1) + Offset(11), TCNT, 8, // Offset(11), Number of Enabled Threads + // + // PCIe Hot Plug + // + Offset(12), OSCC, 8, // Offset(12), PCIE OSC Control + Offset(13), NEXP, 8, // Offset(13), Native PCIE Setup Value + // + // Global Variables + // + Offset(14), DSEN, 8, // Offset(14), _DOS Display Support Flag. + Offset(15), GPIC, 8, // Offset(15), Global IOAPIC/8259 Interrupt= Mode Flag. + Offset(16), L01C, 8, // Offset(16), Global L01 Counter. + Offset(17), LTR1, 8, // Offset(17), Latency Tolerance Reporting = Enable + Offset(18), LTR2, 8, // Offset(18), Latency Tolerance Reporting = Enable + Offset(19), LTR3, 8, // Offset(19), Latency Tolerance Reporting = Enable + Offset(20), LTR4, 8, // Offset(20), Latency Tolerance Reporting = Enable + Offset(21), LTR5, 8, // Offset(21), Latency Tolerance Reporting = Enable + Offset(22), LTR6, 8, // Offset(22), Latency Tolerance Reporting = Enable + Offset(23), LTR7, 8, // Offset(23), Latency Tolerance Reporting = Enable + Offset(24), LTR8, 8, // Offset(24), Latency Tolerance Reporting = Enable + Offset(25), LTR9, 8, // Offset(25), Latency Tolerance Reporting = Enable + Offset(26), LTRA, 8, // Offset(26), Latency Tolerance Reporting = Enable + Offset(27), LTRB, 8, // Offset(27), Latency Tolerance Reporting = Enable + Offset(28), LTRC, 8, // Offset(28), Latency Tolerance Reporting = Enable + Offset(29), LTRD, 8, // Offset(29), Latency Tolerance Reporting = Enable + Offset(30), LTRE, 8, // Offset(30), Latency Tolerance Reporting = Enable + Offset(31), LTRF, 8, // Offset(31), Latency Tolerance Reporting = Enable + Offset(32), LTRG, 8, // Offset(32), Latency Tolerance Reporting = Enable + Offset(33), LTRH, 8, // Offset(33), Latency Tolerance Reporting = Enable + Offset(34), LTRI, 8, // Offset(34), Latency Tolerance Reporting = Enable + Offset(35), LTRJ, 8, // Offset(35), Latency Tolerance Reporting = Enable + Offset(36), LTRK, 8, // Offset(36), Latency Tolerance Reporting = Enable + Offset(37), LTRL, 8, // Offset(37), Latency Tolerance Reporting = Enable + Offset(38), LTRM, 8, // Offset(38), Latency Tolerance Reporting = Enable + Offset(39), LTRN, 8, // Offset(39), Latency Tolerance Reporting = Enable + Offset(40), LTRO, 8, // Offset(40), Latency Tolerance Reporting = Enable + Offset(41), OBF1, 8, // Offset(41), Optimized Buffer Flush and F= ill + Offset(42), OBF2, 8, // Offset(42), Optimized Buffer Flush and F= ill + Offset(43), OBF3, 8, // Offset(43), Optimized Buffer Flush and F= ill + Offset(44), OBF4, 8, // Offset(44), Optimized Buffer Flush and F= ill + Offset(45), OBF5, 8, // Offset(45), Optimized Buffer Flush and F= ill + Offset(46), OBF6, 8, // Offset(46), Optimized Buffer Flush and F= ill + Offset(47), OBF7, 8, // Offset(47), Optimized Buffer Flush and F= ill + Offset(48), OBF8, 8, // Offset(48), Optimized Buffer Flush and F= ill + Offset(49), OBF9, 8, // Offset(49), Optimized Buffer Flush and F= ill + Offset(50), OBFA, 8, // Offset(50), Optimized Buffer Flush and F= ill + Offset(51), OBFB, 8, // Offset(51), Optimized Buffer Flush and F= ill + Offset(52), OBFC, 8, // Offset(52), Optimized Buffer Flush and F= ill + Offset(53), OBFD, 8, // Offset(53), Optimized Buffer Flush and F= ill + Offset(54), OBFE, 8, // Offset(54), Optimized Buffer Flush and F= ill + Offset(55), OBFF, 8, // Offset(55), Optimized Buffer Flush and F= ill + Offset(56), OBFG, 8, // Offset(56), Optimized Buffer Flush and F= ill + Offset(57), OBFH, 8, // Offset(57), Optimized Buffer Flush and F= ill + Offset(58), OBFI, 8, // Offset(58), Optimized Buffer Flush and F= ill + Offset(59), OBFJ, 8, // Offset(59), Optimized Buffer Flush and F= ill + Offset(60), OBFK, 8, // Offset(60), Optimized Buffer Flush and F= ill + Offset(61), OBFL, 8, // Offset(61), Optimized Buffer Flush and F= ill + Offset(62), OBFM, 8, // Offset(62), Optimized Buffer Flush and F= ill + Offset(63), OBFN, 8, // Offset(63), Optimized Buffer Flush and F= ill + Offset(64), OBFO, 8, // Offset(64), Optimized Buffer Flush and F= ill + Offset(65), RTD3, 8, // Offset(65), Runtime D3 support. + Offset(66), S0ID, 8, // Offset(66), Low Power S0 Idle Enable + Offset(67), GBSX, 8, // Offset(67), Virtual GPIO button Notify S= leep State Change + Offset(68), PSCP, 8, // Offset(68), P-state Capping + Offset(69), P2ME, 8, // Offset(69), Ps2 Mouse Enable + Offset(70), P2MK, 8, // Offset(70), Ps2 Keyboard and Mouse Enable + // + // Driver Mode + // + Offset(71), GIRQ, 32, // Offset(71), GPIO IRQ + Offset(75), PLCS, 8, // Offset(75), set PL1 limit when entering = CS + Offset(76), PLVL, 16, // Offset(76), PL1 limit value + Offset(78), PB1E, 8, // Offset(78), 10sec Power button support + Offset(79), ECR1, 8, // Offset(79), Pci Delay Optimization Ecr + Offset(80), TBTS, 8, // Offset(80), Thunderbolt(TM) support + Offset(81), TNAT, 8, // Offset(81), TbtNativeOsHotPlug + Offset(82), TBSE, 8, // Offset(82), Thunderbolt(TM) Root port se= lector + Offset(83), TBS1, 8, // Offset(83), Thunderbolt(TM) Root port se= lector + } + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45908): https://edk2.groups.io/g/devel/message/45908 Mute This Topic: https://groups.io/mt/32918202/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45909+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45909+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001031; cv=none; d=zoho.com; s=zohoarc; b=TZaTME+XO4l75KQ3VcTAOme/tNnvzmNxzKtTt2Np8uz78kdl2yT/mqwe8nBwQOb6aaOgiALdcV8SinsjabbeGKMrt8qDj13qSdo+oOOcOZmBCpNl8PaTGOzp369hIjQSh6lgkHstm1NEfCIAb3xc8lldGi7MWKQvJLGusEQbYgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001031; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=R11r2kA6QcBPWz22+J3G+2h3R4CbCkFKA8faTZO8P0M=; b=MjMudKA4z+IYxxgqnWI3tCfiZI0vdIqv2QTMR3OBX6PxvcE8wpqpkzGrSl3L3chtp9QScW6BO231Mwi8zu4glVS0tDdabos7V7bFq5nGGNt8LK0jEDU8KkAS7f5OGjMpXPvOfwnuB/432XNRnobUFlGmuVZV5cBHG3KYDbZBDA4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45909+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156600103135816.26224535877384; Fri, 16 Aug 2019 17:17:11 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:10 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:16:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319355" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:58 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 32/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add headers Date: Fri, 16 Aug 2019 17:15:58 -0700 Message-Id: <20190817001603.30632-33-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001031; bh=cYu8E+YsH/x6Ps9C73up11gGGA1PnpltXrs8XfKb+mk=; h=Cc:Date:From:Reply-To:Subject:To; b=xVV2JIwTkX1kUnyxAZVkjDIJp+U0AbP8fyEumC3wMp9C1j6goUE8ALeaY4rGiASLII1 rP0VH9EBIwsncZkJOUjQWWvAXOaQjai4cJ8blwn/e+kpGq9tPVxxj6VlkZOyMYVWSFAV0 2SaGHtawcAj0GDPnAeiqrJAeOxvbzKKhPlE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 Header files for the WhiskeylakeURvp board instance. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatform= HookLib.h | 131 ++++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPlatform= Lib.h | 40 ++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformBoa= rdConfig.h | 105 ++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PlatformInf= o.h | 44 +++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whiskeylake= URvpId.h | 12 ++ 5 files changed, 332 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /PeiPlatformHookLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeU= Rvp/Include/PeiPlatformHookLib.h new file mode 100644 index 0000000000..bd849b9ee2 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPla= tformHookLib.h @@ -0,0 +1,131 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PLATFORM_HOOK_LIB_H_ +#define _PEI_PLATFORM_HOOK_LIB_H_ + +#include +#include +#include + + +//EC Command to provide one byte of debug indication +#define BSSB_DEBUG_INDICATION 0xAE +/** + Configure EC for specific devices + + @param[in] PchLan - The PchLan of PCH_SETUP variable. + @param[in] BootMode - The current boot mode. +**/ +VOID +EcInit ( + IN UINT8 PchLan, + IN EFI_BOOT_MODE BootMode + ); + +/** + Checks if Premium PMIC present + + @retval TRUE if present + @retval FALSE it discrete/other PMIC +**/ +BOOLEAN +IsPremiumPmicPresent ( + VOID + ); + +/** + Pmic Programming to supprort LPAL Feature + + @retval NONE +**/ +VOID +PremiumPmicDisableSlpS0Voltage ( + VOID + ); + +/** +Pmic Programming to supprort LPAL Feature + @retval NONE +**/ +VOID +PremiumPmicEnableSlpS0Voltage( + VOID + ); + +/** + Do platform specific programming pre-memory. For example, EC init, Chips= et programming + + @retval Status +**/ +EFI_STATUS +PlatformSpecificInitPreMem ( + VOID + ); + +/** + Do platform specific programming post-memory. + + @retval Status +**/ +EFI_STATUS +PlatformSpecificInit ( + VOID + ); + +/** + Configure GPIO and SIO Before Memory is ready. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitPreMem ( + VOID + ); + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + VOID + ); + +/** +Voltage Margining Routine + +@retval EFI_SUCCESS Operation success +**/ +EFI_STATUS +VoltageMarginingRoutine( + VOID + ); + +/** + Detect recovery mode + + @retval EFI_SUCCESS System in Recovery Mode + @retval EFI_UNSUPPORTED System doesn't support Recovery Mode + @retval EFI_NOT_FOUND System is not in Recovery Mode +**/ +EFI_STATUS +IsRecoveryMode ( + VOID + ); + +/** + Early board Configuration before Memory is ready. + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitEarlyPreMem ( + VOID + ); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /PeiPlatformLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/= Include/PeiPlatformLib.h new file mode 100644 index 0000000000..d65586dbb9 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/PeiPla= tformLib.h @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PLATFORM_LIB_H_ +#define _PEI_PLATFORM_LIB_H_ + + + +#define PEI_DEVICE_DISABLED 0 +#define PEI_DEVICE_ENABLED 1 + +typedef struct { + UINT8 Register; + UINT32 Value; +} PCH_GPIO_DEV; + +// +// GPIO Initialization Data Structure +// +typedef struct{ + PCH_GPIO_DEV Use_Sel; + PCH_GPIO_DEV Use_Sel2; + PCH_GPIO_DEV Use_Sel3; + PCH_GPIO_DEV Io_Sel; + PCH_GPIO_DEV Io_Sel2; + PCH_GPIO_DEV Io_Sel3; + PCH_GPIO_DEV Lvl; + PCH_GPIO_DEV Lvl2; + PCH_GPIO_DEV Lvl3; + PCH_GPIO_DEV Inv; + PCH_GPIO_DEV Blink; + PCH_GPIO_DEV Rst_Sel; + PCH_GPIO_DEV Rst_Sel2; +} GPIO_INIT_STRUCT; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /PlatformBoardConfig.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whiskeylake= URvp/Include/PlatformBoardConfig.h new file mode 100644 index 0000000000..44b4059f8e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Platfo= rmBoardConfig.h @@ -0,0 +1,105 @@ +/** @file + Header file for Platform Boards Configurations. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_BOARD_CONFIG_H +#define _PLATFORM_BOARD_CONFIG_H + +#include +#include +#include +#include +#include + +#define IS_ALIGNED(addr, size) (((addr) & (size - 1)) ? 0 : 1) +#define ALIGN16(size) (IS_ALIGNED(size, 16) ? size : ((size + 16)= & 0xFFF0)) + +#define BOARD_CONFIG_BLOCK_PEI_PREMEM_VERSION 0x00000001 +#define BOARD_CONFIG_BLOCK_PEI_POSTMEM_VERSION 0x00000001 +#define BOARD_CONFIG_BLOCK_DXE_VERSION 0x00000001 +#define BOARD_NO_BATTERY_SUPPORT 0 +#define BOARD_REAL_BATTERY_SUPPORTED BIT0 +#define BOARD_VIRTUAL_BATTERY_SUPPORTED BIT1 + +#pragma pack(1) + +typedef struct { + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header +} BOARD_CONFIG_BLOCK; + +typedef struct { + UINT8 GpioSupport; + UINT32 WakeGpioNo; + UINT8 HoldRstExpanderNo; + UINT32 HoldRstGpioNo; + BOOLEAN HoldRstActive; + UINT8 PwrEnableExpanderNo; + UINT32 PwrEnableGpioNo; + BOOLEAN PwrEnableActive; +} SWITCH_GRAPHIC_GPIO; + +typedef struct { + UINT8 ClkReqNumber : 4; + UINT8 ClkReqSupported : 1; + UINT8 DeviceResetPadActiveHigh : 1; + UINT32 DeviceResetPad; +} ROOT_PORT_CLK_INFO; + +typedef struct { + UINT8 Section; + UINT8 Pin; +} EXPANDER_GPIO_CONFIG; + +typedef enum { + BoardGpioTypePch, + BoardGpioTypeExpander, + BoardGpioTypeNotSupported =3D 0xFF +} BOARD_GPIO_TYPE; + +typedef struct { + UINT8 Type; + UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG + union { + UINT32 Pin; + EXPANDER_GPIO_CONFIG Expander; + } u; +} BOARD_GPIO_CONFIG; + +// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAG= E from PCH RC. +#define NOT_USED 0xFF +#define FREE_RUNNING 0x80 +#define LAN_CLOCK 0x70 +#define PCIE_PEG 0x40 +#define PCIE_PCH 0x00 + +typedef struct { + UINT32 ClockUsage; + UINT32 ClkReqSupported; +} PCIE_CLOCK_CONFIG; + +typedef union { + UINT64 Blob; + BOARD_GPIO_CONFIG BoardGpioConfig; + ROOT_PORT_CLK_INFO Info; + PCIE_CLOCK_CONFIG PcieClock; +} PCD64_BLOB; + +typedef union { + UINT32 Blob; + USB20_AFE Info; +} PCD32_BLOB; + +#ifndef IO_EXPANDER_DISABLED +#define IO_EXPANDER_DISABLED 0xFF +#endif + +#define SPD_DATA_SIZE 512 + +#pragma pack() + +#endif // _PLATFORM_BOARD_CONFIG_H + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /PlatformInfo.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/In= clude/PlatformInfo.h new file mode 100644 index 0000000000..0e0b6c4f6c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Platfo= rmInfo.h @@ -0,0 +1,44 @@ +/** @file + GUID used for Platform Info Data entries in the HOB list. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PLATFORM_INFO_H_ +#define _PLATFORM_INFO_H_ + +#pragma pack(1) + +/// +/// PCH_GPIO_PAD is equivalent to GPIO_PAD which is defined in GpioConfig.h +/// +typedef UINT32 PCH_GPIO_PAD; //Copied from GpioConfig.h (need to change it= based on include) + +typedef struct { +UINT8 Expander; +UINT8 Pin; +UINT16 Reserved; // Reserved for future use +} IO_EXPANDER_PAD; + +typedef union { +PCH_GPIO_PAD PchGpio; +IO_EXPANDER_PAD IoExpGpio; +} GPIO_PAD_CONFIG; + +typedef struct { +UINT8 GpioType; // 0: Disabled (no GPIO support), 1: PCH= , 2: I/O Expander +UINT8 Reserved[3]; // Reserved for future use +GPIO_PAD_CONFIG GpioData; +} PACKED_GPIO_CONFIG; + +typedef union { +PACKED_GPIO_CONFIG PackedGpio; +UINT64 Data64; +} COMMON_GPIO_CONFIG; + +#pragma pack() + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /WhiskeylakeURvpId.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeUR= vp/Include/WhiskeylakeURvpId.h new file mode 100644 index 0000000000..7d44acccc1 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whiske= ylakeURvpId.h @@ -0,0 +1,12 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _WHISKEYLAKE_ERB_ID_H_ +#define _WHISKEYLAKE_ERB_ID_H_ + +#define BoardIdWhiskeyLakeRvp 0x60 +#endif // _WHISKEYLAKE_RVP3_ID_H_ + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45909): https://edk2.groups.io/g/devel/message/45909 Mute This Topic: https://groups.io/mt/32918203/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45910+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45910+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001033; cv=none; d=zoho.com; s=zohoarc; b=OMXtDc5LoCRZah4PrqnJKBv0xiijA6mqdGOQSjttGC7jddMt2QWVaIYAKi8OJ0KZ7uPRNTGHqbAAS5WvaETTfobbyhiRpaRIC1ljxhWL4VrX5BrSNraGG/8uZ8XeSvWVUltfOOn6d7bsXtwMVGjSApqmO71b93+Ni3eTsMUN6fA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001033; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=MNMFJgDxecdKDOfgHtQZZQ9/GOc70PqDI+TDr9HWSbs=; b=NhxvtRbenR/ub+BnLW9rWyKcNNP7ECK0MOBYqIOxjhMHvQ7YWkCIpkJDuu0uWeMbGv+2NhH57jEL5YRNI0hUApG1h9XEFfaNCa/0kO/sowP4mfmiP0hPqg5PR+LyZSqs50lyC+h3XDzoWwPUWLbG088kr0+IWTmbISWa9BDSbFA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45910+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001033039311.8741940856048; Fri, 16 Aug 2019 17:17:13 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:11 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:17:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319365" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:58 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 33/37] WhiskeylakeOpenBoardPkg: Add library instances Date: Fri, 16 Aug 2019 17:15:59 -0700 Message-Id: <20190817001603.30632-34-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001032; bh=HsG6kyuZbRQSCmaGg7Bv2uouGKASNbBFfKy47dXK+3Y=; h=Cc:Date:From:Reply-To:Subject:To; b=dzd0ZLKil0SxTjuTbIiuLjz9y7vhAXQaqaa10/1vjuFDB4KSqiAi0qaBFVg1wE7hCU6 lbWXnY+UBLr8SL6H79cMV+aWjAnYI9nnoAvgP/+t2YCyLh0wL1xOzhDECneEaIKhJVmYA 4MKdCiGgpX5hcSHCOqoIQ7N35gNhV4Alb2M= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 Common package library instances. * BaseAcpiTimerLib - Support for ACPI timer services. * BaseGpioExpanderLib - Support for the TCA6424 IO expander. * DxePolicyUpdateLib - Policy update in DXE. * DxeTbtPolicyLib - DXE Thunderbolt policy initialization. * PeiDTbtInitLib - PEI discrete Thunderbolt initialization services. * PeiFspPolicyInitLib - PEI Intel FSP policy initialization. * PeiI2cAccessLib - Provides I2C read and write services. * PeiPolicyInitLib - Policy initialization in PEI. * PeiPolicyUpdateLib - Policy update in PEI. * PeiSiliconPolicyUpdateLibFsp - PEI FSP silicon policy initialization. * PeiTbtPolicyLib - PEI Thunderbolt policy initialization. * SecFspWrapperPlatformSecLib - FSP wrapper PlatformSecLib instance. * TbtCommonLib - Common Thunderbolt services. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLi= b/DxeTbtPolicyLib.inf | 43 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCo= mmonLib/TbtCommonLib.inf | 60 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLi= b/PeiTbtPolicyLib.inf | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTb= tInitLib/PeiDTbtInitLib.inf | 45 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPolicyInitLib.inf | 161 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 139 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecFspWrapperPlatformSecLib.inf | 97 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerL= ib.inf | 54 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpi= oExpanderLib.inf | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVe= rbTableLib.inf | 67 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAcces= sLib.inf | 39 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xePolicyUpdateLib.inf | 58 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= PolicyInitLib.inf | 61 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPolicyUpdateLib.inf | 272 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLi= b/DxeTbtPolicyLibrary.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLi= b/PeiTbtPolicyLibrary.h | 19 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPolicyInitLib.h | 234 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiMiscPolicyUpdate.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiPchPolicyUpdate.h | 28 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSaPolicyUpdate.h | 30 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/FsptCoreUpd.h | 40 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/Ia32/Fsp.h | 43 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PchHdaVe= rbTables.h | 3014 ++++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeMePolicyUpdate.h | 91 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeSaPolicyUpdate.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= CpuPolicyInit.h | 37 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= MePolicyInit.h | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= PolicyInit.h | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= SaPolicyInit.h | 58 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= SiPolicyInit.h | 22 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiCpuPolicyUpdate.h | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiMePolicyUpdate.h | 14 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPchPolicyUpdate.h | 25 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSaPolicyUpdate.h | 53 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSiPolicyUpdate.h | 19 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPolicyLi= b/DxeTbtPolicyLib.c | 148 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmmTbtCo= mmonLib/TbtCommonLib.c | 316 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPolicyLi= b/PeiTbtPolicyLib.c | 206 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/PeiDTb= tInitLib/PeiDTbtInitLib.c | 567 ++++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspCpuPolicyInitLib.c | 461 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspMePolicyInitLib.c | 121 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspMiscUpdInitLib.c | 77 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPchPolicyInitLib.c | 736 +++++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspPolicyInitLib.c | 223 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspSaPolicyInitLib.c | 848 ++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspSecurityPolicyInitLib.c | 70 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInit= Lib/PeiFspSiPolicyInitLib.c | 95 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiFspMiscUpdUpdateLib.c | 100 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiFspPolicyUpdateLib.c | 124 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiPchPolicyUpdate.c | 60 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiPchPolicyUpdatePreMem.c | 39 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSaPolicyUpdate.c | 85 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicy= UpdateLibFsp/PeiSaPolicyUpdatePreMem.c | 87 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/FspWrapperPlatformSecLib.c | 163 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/PlatformInit.c | 54 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecGetPerformance.c | 90 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecPlatformInformation.c | 79 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecRamInitData.c | 37 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/SecTempRamDone.c | 48 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerL= ib.c | 48 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpi= oExpanderLib.c | 310 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVe= rbTableLib.c | 132 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2cAcces= sLib.c | 115 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeCpuPolicyUpdate.c | 88 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeMePolicyUpdate.c | 105 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xePchPolicyUpdate.c | 39 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdateLib/D= xeSaPolicyUpdate.c | 57 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= PolicyInit.c | 65 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= PolicyInitPreMem.c | 60 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLib/Pei= SaPolicyInit.c | 114 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiCpuPolicyUpdate.c | 80 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiCpuPolicyUpdatePreMem.c | 108 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiMePolicyUpdate.c | 49 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiMePolicyUpdatePreMem.c | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPchPolicyUpdate.c | 523 ++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiPchPolicyUpdatePreMem.c | 113 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSaPolicyUpdate.c | 242 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSaPolicyUpdatePreMem.c | 221 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/P= eiSiPolicyUpdate.c | 168 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/Ia32/PeiCoreEntry.nasm | 130 + Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/Ia32/SecEntry.nasm | 361 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPla= tformSecLib/Ia32/Stack.nasm | 72 + Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiTimerL= ib.uni | 15 + 83 files changed, 13144 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Dx= eTbtPolicyLib/DxeTbtPolicyLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.inf new file mode 100644 index 0000000000..0d2a6cceeb --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for Tbt functionality +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeTbtPolicyLib +FILE_GUID =3D 28ABF346-4E52-4BD3-b1FF-63BA7563C9D4 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D DxeTbtPolicyLib + + +[LibraryClasses] +BaseMemoryLib +UefiRuntimeServicesTableLib +UefiBootServicesTableLib +DebugLib +PostCodeLib +HobLib + +[Packages] +MdePkg/MdePkg.dec +CoffeelakeSiliconPkg/SiPkg.dec +WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec +[Sources] +DxeTbtPolicyLib.c + + +[Guids] +gEfiEndOfDxeEventGroupGuid +gTbtInfoHobGuid + +[Protocols] +gDxeTbtPolicyProtocolGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iDxeSmmTbtCommonLib/TbtCommonLib.inf b/Platform/Intel/WhiskeylakeOpenBoardP= kg/Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.inf new file mode 100644 index 0000000000..f2330b5b71 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmm= TbtCommonLib/TbtCommonLib.inf @@ -0,0 +1,60 @@ +## @file +# Component information file for Tbt common library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D TbtCommonLib + FILE_GUID =3D 5F03614E-CB56-40B1-9989-A09E25BBA294 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D TbtCommonLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[LibraryClasses] + DebugLib + PchPcieRpLib + PciSegmentLib + TimerLib + BaseLib + GpioLib + GpioExpanderLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + + +[Pcd] +gBoardModuleTokenSpaceGuid.PcdDTbtSecurityMode ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtAspm ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdRtd3Tbt ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax ## CONSUMES +gBoardModuleTokenSpaceGuid.PcdDTbtPcieRpNumber + +[Sources] + TbtCommonLib.c + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iTbtPolicyLib/PeiTbtPolicyLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.inf new file mode 100644 index 0000000000..b74e641e16 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.inf @@ -0,0 +1,51 @@ +## @file +# Component description file for Tbt policy +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiTbtPolicyLib +FILE_GUID =3D 4A95FDBB-2535-49eb-9A79-D56D24257106 +VERSION_STRING =3D 1.0 +MODULE_TYPE =3D PEIM +LIBRARY_CLASS =3D PeiTbtPolicyLib + + +[LibraryClasses] +BaseMemoryLib +PeiServicesLib +PeiServicesTablePointerLib +MemoryAllocationLib +DebugLib +PostCodeLib +HobLib +GpioLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Pcd] +gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad ## CONSUMES + +[Sources] +PeiTbtPolicyLib.c + +[Guids] +gTbtInfoHobGuid + +[Ppis] +gEfiPeiReadOnlyVariable2PpiGuid +gPeiTbtPolicyPpiGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pr= ivate/PeiDTbtInitLib/PeiDTbtInitLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.inf new file mode 100644 index 0000000000..8e0dbe73ce --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P= eiDTbtInitLib/PeiDTbtInitLib.inf @@ -0,0 +1,45 @@ +## @file +# Component description file for PEI DTBT Init library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiDTbtInitLib + FILE_GUID =3D 06768A8D-8152-403f-83C1-59584FD2B438 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiDTbtInitLib + +[LibraryClasses] + PeiServicesLib + DebugLib + PcdLib + TbtCommonLib + PciSegmentLib + PeiTbtPolicyLib + PchPmcLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Ppis] + gPeiTbtPolicyPpiGuid ## CONSUMES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + #gClientCommonModuleTokenSpaceGuid.PcdTbtSupport ## PRODUCES + +[Sources] + PeiDTbtInitLib.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf new file mode 100644 index 0000000000..bd39cd60b7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPolicyInitLib.inf @@ -0,0 +1,161 @@ +## @file +# Library functions for Fsp Policy Initialization Library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiFspPolicyInitLib + FILE_GUID =3D 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + PeiFspPolicyInitLib.c + PeiFspSiPolicyInitLib.c + PeiFspPchPolicyInitLib.c + PeiFspCpuPolicyInitLib.c + PeiFspMePolicyInitLib.c + PeiFspSaPolicyInitLib.c + PeiFspSecurityPolicyInitLib.c + PeiFspMiscUpdInitLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + IoLib + PeiServicesLib + SmbusLib + ConfigBlockLib + PcdLib + MemoryAllocationLib + PchInfoLib + SpiLib + +[Pcd] + gSiPkgTokenSpaceGuid.PcdTsegSize + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES + +[Ppis] + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + gEfiSecPlatformInformation2PpiGuid ## CONSUMES + gEfiSecPlatformInformationPpiGuid ## CONSUMES + +[Guids] + gPchTraceHubPreMemConfigGuid ## CONSUMES + gSmbusPreMemConfigGuid ## CONSUMES + gDciPreMemConfigGuid ## CONSUMES + gPcieRpPreMemConfigGuid ## CONSUMES + gHdAudioPreMemConfigGuid ## CONSUMES + gIshPreMemConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gLpcPreMemConfigGuid ## CONSUMES + gPchGeneralPreMemConfigGuid ## CONSUMES + gWatchDogPreMemConfigGuid ## CONSUMES + gLanConfigGuid ## CONSUMES + gPcieRpConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gHdAudioConfigGuid ## CONSUMES + gScsConfigGuid ## CONSUMES + gIshConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gUsbConfigGuid ## CONSUMES + gSerialIoConfigGuid ## CONSUMES + gInterruptConfigGuid ## CONSUMES + gLockDownConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## PRODUCES + gSaMiscPeiConfigGuid ## PRODUCES + gMemoryConfigGuid ## CONSUMES + gMemoryConfigNoCrcGuid ## CONSUMES + gSwitchableGraphicsConfigGuid ## CONSUMES + gGraphicsPeiPreMemConfigGuid ## CONSUMES + gSaPciePeiPreMemConfigGuid ## CONSUMES + gSaMiscPeiConfigGuid ## CONSUMES + gSaPciePeiConfigGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gCpuTraceHubConfigGuid ## CONSUMES + gIpuPreMemConfigGuid ## CONSUMES + gCnviConfigGuid ## CONSUMES + gHsioConfigGuid ## CONSUMES + gEspiConfigGuid ## CONSUMES + gGnaConfigGuid ## CONSUMES + gVtdConfigGuid ## CONSUMES + gSaOverclockingPreMemConfigGuid ## CONSUMES + gMePeiPreMemConfigGuid ## CONSUMES + gMePeiConfigGuid ## CONSUMES + gDmiConfigGuid ## CONSUMES + gFlashProtectionConfigGuid ## CONSUMES + gIoApicConfigGuid ## CONSUMES + gPmConfigGuid ## CONSUMES + gP2sbConfigGuid ## CONSUMES + gPchGeneralConfigGuid ## CONSUMES + gSerialIrqConfigGuid ## CONSUMES + gThermalConfigGuid ## CONSUMES + gCpuSecurityPreMemConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gCpuOverclockingPreMemConfigGuid ## CONSUMES + gCpuConfigLibPreMemConfigGuid ## CONSUMES + gCpuPowerMgmtBasicConfigGuid ## CONSUMES + gCpuPowerMgmtCustomConfigGuid ## CONSUMES + gCpuTestConfigGuid ## CONSUMES + gCpuPidTestConfigGuid ## CONSUMES + gCpuPowerMgmtTestConfigGuid ## CONSUMES + gFspNonVolatileStorageHobGuid ## CONSUMES + gSmramCpuDataHeaderGuid ## CONSUMES + gFspReservedMemoryResourceHobTsegGuid ## CONSUMES + gSiConfigGuid ## CONSUMES + gDebugConfigHobGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel/= WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/Pei= SiliconPolicyUpdateLibFsp.inf new file mode 100644 index 0000000000..994cf93e33 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -0,0 +1,139 @@ +## @file +# Provide FSP wrapper platform related function. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SiliconPolicyUpdateLibFsp + FILE_GUID =3D 4E83003B-49A9-459E-AAA6-1CA3C6D04FB2 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyUpdateLib + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + PeiFspPolicyUpdateLib.c + PeiPchPolicyUpdatePreMem.c + PeiPchPolicyUpdate.c + PeiSaPolicyUpdatePreMem.c + PeiSaPolicyUpdate.c + PeiFspMiscUpdUpdateLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + CoffeeLakeFspBinPkg/CoffeeLakeFspBinPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses.IA32] + FspWrapperApiLib + OcWdtLib + PchResetLib + FspWrapperPlatformLib + BaseMemoryLib + CpuPlatformLib + DebugLib + HdaVerbTableLib + HobLib + IoLib + PcdLib + PostCodeLib + SmbusLib + ConfigBlockLib + PeiSaPolicyLib + PchGbeLib + PchInfoLib + PchHsioLib + PchPcieRpLib + MemoryAllocationLib + DebugPrintErrorLevelLib + SiPolicyLib + PchGbeLib + TimerLib + GpioLib + PeiLib + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmmbaseSwSmi ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowLpHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificHHsioPtssTable2Size + + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + +[Guids] + gFspNonVolatileStorageHobGuid ## CONSUMES + gTianoLogoGuid ## CONSUMES + gEfiMemoryOverwriteControlDataGuid + +[Depex] + gEdkiiVTdInfoPpiGuid diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/Wh= iskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFsp= WrapperPlatformSecLib.inf new file mode 100644 index 0000000000..06489a6336 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecFspWrapperPlatformSecLib.inf @@ -0,0 +1,97 @@ +## @file +# Provide FSP wrapper platform sec related function. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SecFspWrapperPlatformSecLib + FILE_GUID =3D 4E1C4F95-90EA-47de-9ACC-B8920189A1F5 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformSecLib + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspWrapperPlatformSecLib.c + SecRamInitData.c + SecPlatformInformation.c + SecGetPerformance.c + SecTempRamDone.c + PlatformInit.c + +[Sources.IA32] + Ia32/SecEntry.nasm + Ia32/PeiCoreEntry.nasm + Ia32/Stack.nasm + Ia32/Fsp.h + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + LocalApicLib + SerialPortLib + FspWrapperPlatformLib + FspWrapperApiLib + BoardInitLib + SecBoardInitLib + TestPointCheckLib + IoLib + +[Ppis] + gEfiSecPlatformInformationPpiGuid ## CONSUMES + gPeiSecPerformancePpiGuid ## CONSUMES + gTopOfTemporaryRamPpiGuid ## PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## C= ONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONS= UMES + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress + +[FixedPcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/Ba= seAcpiTimerLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTim= erLib/BaseAcpiTimerLib.inf new file mode 100644 index 0000000000..e7eef24906 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiT= imerLib.inf @@ -0,0 +1,54 @@ +## @file +# Base ACPI Timer Library +# +# Provides basic timer support using the ACPI timer hardware. The perfor= mance +# counter features are provided by the processors time stamp counter. +# +# Note: The implementation uses the lower 24-bits of the ACPI timer and +# is compatible with both 24-bit and 32-bit ACPI timers. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseAcpiTimerLib + FILE_GUID =3D 564DE85F-049E-4481-BF7A-CA04D2788CF9 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TimerLib|SEC PEI_CORE PEIM + CONSTRUCTOR =3D AcpiTimerLibConstructor + MODULE_UNI_FILE =3D BaseAcpiTimerLib.uni + +[Sources] + AcpiTimerLib.c + BaseAcpiTimerLib.c + +[Packages] + MdePkg/MdePkg.dec + PcAtChipsetPkg/PcAtChipsetPkg.dec + UefiCpuPkg/UefiCpuPkg.dec ## OVERRIDE + +[LibraryClasses] + BaseLib + PcdLib + PciLib + IoLib + DebugLib + +[Pcd] + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset ## CONSU= MES + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask ## CONSU= MES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpande= rLib/BaseGpioExpanderLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Libra= ry/BaseGpioExpanderLib/BaseGpioExpanderLib.inf new file mode 100644 index 0000000000..ef5ede18cc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf @@ -0,0 +1,36 @@ +## @file +# Library producing Gpio Expander functionality. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BaseGpioExpanderLib + FILE_GUID =3D D10AE2A4-782E-427E-92FB-BB74505ED329 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D GpioExpanderLib + +[LibraryClasses] + BaseLib + IoLib + DebugLib + TimerLib + PchSerialIoLib + I2cAccessLib + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + BaseGpioExpanderLib.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PeiHdaVerbTableLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library= /PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf new file mode 100644 index 0000000000..3c017577b6 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.inf @@ -0,0 +1,67 @@ +## @file +# PEI Intel HD Audio Verb Table library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiHdaVerbTableLib + FILE_GUID =3D 821486A2-CF3B-4D24-BC45-AFE40D9737EB + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D HdaVerbTableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + PeiHdaVerbTableLib.c + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + MemoryAllocationLib + PcdLib + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdHdaVerbTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdExtHdaVerbTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdCommonHdaVerbTable3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdDisplayAudioHdaVerbTable ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib= /PeiI2cAccessLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2= cAccessLib/PeiI2cAccessLib.inf new file mode 100644 index 0000000000..887cbf84f8 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2c= AccessLib.inf @@ -0,0 +1,39 @@ +## @file +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiI2cAccessLib + FILE_GUID =3D 72CD3A7B-FEA5-4F5E-9165-4DD12187BB13 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PeiI2cAccessLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + TimerLib + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + SecurityPkg/SecurityPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiI2cAccessLib.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxePolicyUpdateLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Policy/Library/DxePolicyUpdateLib/DxePolicyUpdateLib.inf new file mode 100644 index 0000000000..16653f38bd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxePolicyUpdateLib.inf @@ -0,0 +1,58 @@ +## @file +# Component description file for DXE DxePolicyUpdateLib Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D DxePolicyUpdateLib + FILE_GUID =3D 690B3786-D215-4ABB-9EF2-7A80128560E0 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D DxePolicyUpdateLib|DXE_DRIVER + +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + DxeMePolicyUpdate.c + DxeSaPolicyUpdate.c + DxePchPolicyUpdate.c + DxeCpuPolicyUpdate.c + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseLib + BaseMemoryLib + PcdLib + DebugLib + IoLib + CpuPlatformLib + HobLib + ConfigBlockLib + PciSegmentLib + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + +[Guids] + gEfiGlobalVariableGuid ## CONSUMES + gEfiEndOfDxeEventGroupGuid ## CONSUMES + gMeInfoSetupGuid ## PRODUCES + gMePolicyHobGuid ## CONSUMES + gCpuSetupVariableGuid ## CONSUMES + gPchSetupVariableGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiPolicyInitLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Poli= cy/Library/PeiPolicyInitLib/PeiPolicyInitLib.inf new file mode 100644 index 0000000000..293abf1904 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiPolicyInitLib.inf @@ -0,0 +1,61 @@ +## @file +# Component description file for PeiPolicyInit library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPolicyInitLib + FILE_GUID =3D B494DF39-A5F8-48A1-B2D0-EF523AD91C55 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPolicyInitLib + +[LibraryClasses] + BaseMemoryLib + BaseLib + CpuPlatformLib + DebugLib + DebugPrintErrorLevelLib + HobLib + IoLib + MemoryAllocationLib + PeiServicesLib + PeiPolicyBoardConfigLib + PeiPolicyUpdateLib + PostCodeLib + SmbusLib + ConfigBlockLib + SiPolicyLib + TimerLib + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDumpDefaultSiliconPolicy ## CONSUMES + + +[Sources] + PeiPolicyInitPreMem.c + PeiPolicyInit.c + PeiPolicyInit.h + PeiCpuPolicyInit.h + PeiMePolicyInit.h + PeiSaPolicyInit.c + PeiSaPolicyInit.h + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPolicyUpdateLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/= Policy/Library/PeiPolicyUpdateLib/PeiPolicyUpdateLib.inf new file mode 100644 index 0000000000..3095a7333e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPolicyUpdateLib.inf @@ -0,0 +1,272 @@ +## @file +# Module Information file for PEI PolicyUpdateLib Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPolicyUpdateLib + FILE_GUID =3D 6EA9585C-3C15-47DA-9FFC-25E9E4EA4D0C + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPolicyUpdateLib|PEIM PEI_CORE SEC + +[LibraryClasses] + HobLib + BaseCryptLib + CpuPlatformLib + IoLib + PeiSaPolicyLib + ConfigBlockLib + PchGbeLib + PchInfoLib + PchPcieRpLib + HdaVerbTableLib + MemoryAllocationLib + PeiServicesTablePointerLib + PcdLib + Tpm2CommandLib + Tpm12CommandLib + Tpm2DeviceLib + Tpm12DeviceLib + PmcLib + SataLib + PchInfoLib + PciSegmentLib + SiPolicyLib + PeiServicesLib + SpiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + SecurityPkg/SecurityPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize ## CONSUMES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGttMmAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGmAdrAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdBoardBomId ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit ## CONSUMES + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CONSUMES + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## CONSUMES + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive ## CONSUMES + + # PCIE RTD3 GPIO + gBoardModuleTokenSpaceGuid.PcdRootPortDev ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdRootPortFunc ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdRootPortIndex ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive ## CONSUMES + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES + + # CA Vref Configuration + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMobileDramPresent ## CONSUMES + + # PCIe Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe ## CONSUMES + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 ## CONSUMES + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 ## CONSUMES + + # Pch SerialIo I2c Pads Termination + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c0PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c1PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c2PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c3PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c4PadInternalTerm ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchSerialIoI2c5PadInternalTerm ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdEcPresent + + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSmbusAlertEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSataLedEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdVrAlertEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPchThermalHotEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioCPmsyncEnable ## C= ONSUMES + gBoardModuleTokenSpaceGuid.PcdMemoryThermalSensorGpioDPmsyncEnable ## C= ONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid ## C= ONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## C= ONSUMES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CO= NSUMES + +[Sources] + PeiPchPolicyUpdatePreMem.c + PeiPchPolicyUpdate.c + PeiCpuPolicyUpdatePreMem.c + PeiCpuPolicyUpdate.c + PeiMePolicyUpdatePreMem.c + PeiMePolicyUpdate.c + PeiSaPolicyUpdate.c + PeiSaPolicyUpdatePreMem.c + PeiSiPolicyUpdate.c + +[Ppis] + gWdtPpiGuid ## CONSUMES + gPchSpiPpiGuid ## CONSUMES + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + gPeiTbtPolicyPpiGuid ## CONSUMES + +[Guids] + gTianoLogoGuid ## CONSUMES + gSiConfigGuid ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Dx= eTbtPolicyLib/DxeTbtPolicyLibrary.h b/Platform/Intel/WhiskeylakeOpenBoardPk= g/Features/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLibrary.h new file mode 100644 index 0000000000..a88385f36f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLibrary.h @@ -0,0 +1,25 @@ +/** @file + Header file for the DxeTBTPolicy library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_TBT_POLICY_LIBRARY_H_ +#define _DXE_TBT_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include + +#endif // _DXE_TBT_POLICY_LIBRARY_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iTbtPolicyLib/PeiTbtPolicyLibrary.h b/Platform/Intel/WhiskeylakeOpenBoardPk= g/Features/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLibrary.h new file mode 100644 index 0000000000..462bf780e3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLibrary.h @@ -0,0 +1,19 @@ +/** @file + Header file for the PeiTBTPolicy library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_TBT_POLICY_LIBRARY_H_ +#define _PEI_TBT_POLICY_LIBRARY_H_ + +#include +#include +#include +#include +#include + +#endif // _PEI_TBT_POLICY_LIBRARY_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.h b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h new file mode 100644 index 0000000000..52f9fbed8b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPolicyInitLib.h @@ -0,0 +1,234 @@ +/** @file + Internal header file for Fsp Policy Initialization Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_FSP_POLICY_INIT_LIB_H_ +#define _PEI_FSP_POLICY_INIT_LIB_H_ + +#include + +#include +#include +#include + +#include +#include +#include +#include + +/** + Performs FSP SI PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP SI PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP CPU PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** +Performs FSP Security PEI Policy initialization. + +@param[in][out] FspmUpd Pointer to FSP UPD Data. + +@retval EFI_SUCCESS FSP UPD Data is updated. +@retval EFI_NOT_FOUND Fail to locate required PPI. +@retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSecurityPolicyInitPreMem( +IN OUT FSPM_UPD *FspmUpd +); + +/** + Performs FSP ME PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP ME PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** + Performs FSP CPU PEI Policy post memory initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ); + +/** +Performs FSP Security PEI Policy post memory initialization. + +@param[in][out] FspsUpd Pointer to FSP UPD Data. + +@retval EFI_SUCCESS FSP UPD Data is updated. +@retval EFI_NOT_FOUND Fail to locate required PPI. +@retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSecurityPolicyInit( +IN OUT FSPS_UPD *FspsUpd +); + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ); + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +#endif // _PEI_FSP_POLICY_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiMiscPolicyUpdate.h b/Platform/Intel/Whiskeylake= OpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiMiscPolicyU= pdate.h new file mode 100644 index 0000000000..a0c8f2dae7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiMiscPolicyUpdate.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_MISC_POLICY_UPDATE_H_ +#define _PEI_MISC_POLICY_UPDATE_H_ + +#include + +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ); + +#endif diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h b/Platform/Intel/WhiskeylakeO= penBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpd= ate.h new file mode 100644 index 0000000000..1ff16e2f32 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiPchPolicyUpdate.h @@ -0,0 +1,28 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PCH_POLICY_UPDATE_H_ +#define _PEI_PCH_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h b/Platform/Intel/WhiskeylakeOp= enBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdat= e.h new file mode 100644 index 0000000000..9b8c28c469 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSaPolicyUpdate.h @@ -0,0 +1,30 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SA_POLICY_UPDATE_H_ +#define _PEI_SA_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include +#include + +#include +#include +#include + +extern EFI_GUID gTianoLogoGuid; + +#endif + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/FsptCoreUpd.h b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FsptCoreUpd.h new file mode 100644 index 0000000000..e7b5ed952b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/FsptCoreUpd.h @@ -0,0 +1,40 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __FSPT_CORE_UPD_H__ +#define __FSPT_CORE_UPD_H__ + +#pragma pack(1) + +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionSize; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionSize; + +/** Offset 0x0030 +**/ + UINT8 Reserved[16]; +} FSPT_CORE_UPD; + +#pragma pack() + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/Ia32/Fsp.h b/Platform/Intel/WhiskeylakeOpenBoardPkg= /FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Fsp.h new file mode 100644 index 0000000000..1c88285a1d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/Ia32/Fsp.h @@ -0,0 +1,43 @@ +/** @file + Fsp related definitions + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __FSP_H__ +#define __FSP_H__ + +// +// Fv Header +// +#define FVH_SIGINATURE_OFFSET 0x28 +#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH +#define FVH_HEADER_LENGTH_OFFSET 0x30 +#define FVH_EXTHEADER_OFFSET_OFFSET 0x34 +#define FVH_EXTHEADER_SIZE_OFFSET 0x10 + +// +// Ffs Header +// +#define FSP_HEADER_GUID_DWORD1 0x912740BE +#define FSP_HEADER_GUID_DWORD2 0x47342284 +#define FSP_HEADER_GUID_DWORD3 0xB08471B9 +#define FSP_HEADER_GUID_DWORD4 0x0C3F3527 +#define FFS_HEADER_SIZE_VALUE 0x18 + +// +// Section Header +// +#define SECTION_HEADER_TYPE_OFFSET 0x03 +#define RAW_SECTION_HEADER_SIZE_VALUE 0x04 + +// +// Fsp Header +// +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PchHdaVerbTables.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/Pei= HdaVerbTableLib/PchHdaVerbTables.h new file mode 100644 index 0000000000..0d26e8ad7a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pch= HdaVerbTables.h @@ -0,0 +1,3014 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_VERB_TABLES_H_ +#define _PCH_HDA_VERB_TABLES_H_ + +#include + +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: CFL Display Audio Codec + // Revision ID =3D 0xFF + // Codec Vendor: 0x8086280B + // + 0x8086, 0x280B, + 0xFF, 0xFF, + // + // Display Audio Verb Table + // + // For GEN9, the Vendor Node ID is 08h + // Port to be exposed to the inbox driver in the vanilla mode: PORT C - = BIT[7:6] =3D 01b + 0x00878140, + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010 + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020 + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030 + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + // Disable the third converter and third Pin (NID 08h) + 0x00878140 +); + +// +//codecs verb tables +// +HDAUDIO_VERB_TABLE HdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40622005 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D20, + 0x01D71E62, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + // + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +); // HdaVerbTableAlc700 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc701 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC701) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0701 + // + 0x10EC, 0x0701, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC701 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40610041 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC1124 + 0x00172024, + 0x00172111, + 0x001722EC, + 0x00172310, + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C41, + 0x01D71D00, + 0x01D71E61, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B +); // HdaVerbTableAlc701 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc274 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC274) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0274 + // + 0x10EC, 0x0274, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC274 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6 + //The number of verb command block : 16 + + // NID 0x12 : 0x40000000 + // NID 0x13 : 0x411111F0 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x411111F0 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11020 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40451B05 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211010 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //,DA Codec Subsystem ID : 0x10EC10F6 + 0x001720F6, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + //Pin widget 0x14 - NPC + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S_OUT2 + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S_OUT1 + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + //Pin widget 0x18 - I2S_IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C20, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D1B, + 0x01D71E45, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C10, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205006F, + 0x02042C0B, + //Widget node 0x20 - 1 : + 0x02050035, + 0x02048968, + 0x05B50001, + 0x05B48540, + //Widget node 0x20 - 2 : + 0x05850000, + 0x05843888, + 0x05850000, + 0x05843888, + //Widget node 0x20 - 3 : + 0x0205004A, + 0x0204201B, + 0x0205004A, + 0x0204201B +); //HdaVerbTableAlc274 + +// +// CFL S Audio Codec +// +STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_IN= IT ( + // + // VerbTable: (Realtek ALC700) CFL S RVP + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C + //The number of verb command block : 17 + + // NID 0x12 : 0x90A60130 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x03011010 + // NID 0x17 : 0x90170120 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A1103E + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x03A11040 + // NID 0x1D : 0x40600001 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x0421102F + // NID 0x29 : 0x411111F0 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC112C + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C30, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671C10, + 0x01671D10, + 0x01671E01, + 0x01671F03, + //Pin widget 0x17 - I2S-OUT + 0x01771C20, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C3E, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71C40, + 0x01B71D10, + 0x01B71EA1, + 0x01B71F03, + //Pin widget 0x1D - PC-BEEP + 0x01D71C01, + 0x01D71D00, + 0x01D71E60, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of= NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14) + 0x0205006B, + 0x02044260, + 0x0205006B, + 0x02044260, + //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700 + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent co= ntrol + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 4 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + + //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove ALC= 1305 EQ setting + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x02042213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); + + +// +// WHL codecs verb tables +// +HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) WHL RVP + // Revision ID =3D 0xff + // Codec Verb Table for WHL PCH boards + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x02A19040 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40638029 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x02211020 + // NID 0x29 : 0x411111F0 + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C40, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C29, + 0x01D71D80, + 0x01D71E63, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F02, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + + //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 byp= ass DAC02 DRE(NID5B bit14) + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + + //Widget node 0x20 -2: + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + + //Widget node 0x20 - 3 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + + //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove ALC= 1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x0204E213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204422E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); // WhlHdaVerbTableAlc700 + +#endif // _PCH_HDA_VERB_TABLES_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeMePolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/DxePolicyUpdateLib/DxeMePolicyUpdate.h new file mode 100644 index 0000000000..8cbcace075 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeMePolicyUpdate.h @@ -0,0 +1,91 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_ME_POLICY_UPDATE_H_ +#define _DXE_ME_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PLATFORM_BOOT_TABLE_PTR_TYPE 0x1001 +#define PLATFORM_BOOT_RECORD_TYPE 0x1022 +// +// Timeout values based on HPET +// +#define HECI_MSG_DELAY 2000000 ///< show warning msg and = stay for 2 seconds. +#define CONVERSION_MULTIPLIER 1000000 ///< msec to nanosec multi= plier +#define PLATFORM_BOOT_TABLE_SIGNATURE SIGNATURE_32 ('P', 'B', 'P', 'T') + +// +// Platform Boot Performance Table Record +// + +typedef struct { + UINT16 Type; + UINT8 Length; + UINT8 Revision; + UINT32 Reserved; + UINT64 TimestampDelta1; + UINT64 TimestampDelta2; + UINT64 TimestampDelta3; +} PLATFORM_BOOT_TABLE_RECORD; + +// +// Platform boot Performance Table +// + +typedef struct { + EFI_ACPI_COMMON_HEADER Header; + PLATFORM_BOOT_TABLE_RECORD PlatformBoot; +} PLATFORM_BOOT_PERFORMANCE_TABLE; + +/** + Update ME Policy while MePlatformProtocol is installed. + + @param[in] MePolicyInstance Instance of ME Policy Protocol + +**/ +VOID +UpdateMePolicyFromMeSetup ( + IN ME_POLICY_PROTOCOL *MePolicyInstance + ); + +/** + Update ME Policy if Setup variable exists. + + @param[in, out] MePolicyInstance Instance of ME Policy Protocol + +**/ +VOID +UpdateMePolicyFromSetup ( + IN OUT ME_POLICY_PROTOCOL *MePolicyInstance + ); + +/** + Functions performs HECI exchange with FW to update MePolicy settings. + + @param[in] Event A pointer to the Event that triggered the callb= ack. + @param[in] Context A pointer to private data registered with the c= allback function. + +**/ +VOID +EFIAPI +UpdateMeSetupCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeSaPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.h new file mode 100644 index 0000000000..4521d83567 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeSaPolicyUpdate.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_SA_POLICY_UPDATE_H_ +#define _DXE_SA_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiCpuPolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy= /Library/PeiPolicyInitLib/PeiCpuPolicyInit.h new file mode 100644 index 0000000000..25c5213c2d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiCpuPolicyInit.h @@ -0,0 +1,37 @@ +/** @file + Header file for the PeiCpuPolicyInit. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_CPU_POLICY_INIT_H_ +#define _PEI_CPU_POLICY_INIT_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + This function performs CPU PEI Policy initialization in PreMem. + + @param[in, out] SiPreMemPolicyPpi The Si Pre-Mem Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiMePolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/= Library/PeiPolicyInitLib/PeiMePolicyInit.h new file mode 100644 index 0000000000..7f3fde9fd8 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiMePolicyInit.h @@ -0,0 +1,23 @@ +/** @file + Header file for the PeiMePolicyInit + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_ME_POLICY_INIT_H_ +#define _PEI_ME_POLICY_INIT_H_ + +#include +#include +#include +#include + +#include +#include +#include +#include + +#endif // _PEI_ME_POLICY_INIT_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiPolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Li= brary/PeiPolicyInitLib/PeiPolicyInit.h new file mode 100644 index 0000000000..9c18f85735 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiPolicyInit.h @@ -0,0 +1,23 @@ +/** @file + Header file for the PolicyInitPei PEIM. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_POLICY_INIT_H_ +#define _PEI_POLICY_INIT_H_ + +#include +#include +#include + +#include "PeiCpuPolicyInit.h" +#include "PeiMePolicyInit.h" +#include "PeiSaPolicyInit.h" +#include "PeiSiPolicyInit.h" +#include +#include +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiSaPolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/= Library/PeiPolicyInitLib/PeiSaPolicyInit.h new file mode 100644 index 0000000000..83b18bf533 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiSaPolicyInit.h @@ -0,0 +1,58 @@ +/** @file + Header file for the SaPolicyInitPei PEIM. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_POLICY_INIT_PEI_H_ +#define _SA_POLICY_INIT_PEI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Functions +// +/** +PCIe GPIO Write + +@param[in] Gpio - GPIO Number +@param[in] Active - GPIO Active Information; High/Low +@param[in] Level - Write GPIO value (0/1) + +**/ +VOID +PcieGpioWrite( +IN UINT32 Gpio, +IN BOOLEAN Active, +IN BOOLEAN Level +); + +/** +PcieCardResetWorkAround performs PCIe Card reset on root port + +@param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY_PPI + +@retval EFI_SUCCESS The policy is installed and initialized. +**/ +EFI_STATUS +PcieCardResetWorkAround( +IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi +); +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiSiPolicyInit.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/= Library/PeiPolicyInitLib/PeiSiPolicyInit.h new file mode 100644 index 0000000000..1a28f426d6 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiSiPolicyInit.h @@ -0,0 +1,22 @@ +/** @file + Header file for the PeiSiPolicyInit + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SI_POLICY_INIT_PEI_H_ +#define _SI_POLICY_INIT_PEI_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +#endif // _SI_POLICY_INIT_PEI_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiCpuPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.h new file mode 100644 index 0000000000..254e58edb7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiCpuPolicyUpdate.h @@ -0,0 +1,32 @@ +/** @file + Header file for PEI CpuPolicyUpdate. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_CPU_POLICY_UPDATE_H_ +#define _PEI_CPU_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiMePolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.h new file mode 100644 index 0000000000..37cd373c78 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiMePolicyUpdate.h @@ -0,0 +1,14 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_ME_POLICY_UPDATE_H_ +#define _PEI_ME_POLICY_UPDATE_H_ + +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPchPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.h new file mode 100644 index 0000000000..5a69852801 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPchPolicyUpdate.h @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_PCH_POLICY_UPDATE_H_ +#define _PEI_PCH_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSaPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.h new file mode 100644 index 0000000000..8cf24ed24d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSaPolicyUpdate.h @@ -0,0 +1,53 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SA_POLICY_UPDATE_H_ +#define _PEI_SA_POLICY_UPDATE_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include +#include +#include "PeiPchPolicyUpdate.h" +#include +#include +#include + +#define WDT_TIMEOUT 60 + +// BClk Frequency Limitations (in Hz) +#define BCLK_MAX 538000000 +#define BCLK_100 100000000 +#define BCLK_GRANULARITY 1000000 +#define BCLK_100_KHZ 100000 + + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ); + +#endif + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSiPolicyUpdate.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.h new file mode 100644 index 0000000000..38ea081166 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSiPolicyUpdate.h @@ -0,0 +1,19 @@ +/** @file + Header file for PEI SiPolicyUpdate. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_SI_POLICY_UPDATE_H_ +#define _PEI_SI_POLICY_UPDATE_H_ + +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Dx= eTbtPolicyLib/DxeTbtPolicyLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fe= atures/Tbt/Library/DxeTbtPolicyLib/DxeTbtPolicyLib.c new file mode 100644 index 0000000000..c185cda4ce --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.c @@ -0,0 +1,148 @@ +/** @file + This file is DxeTbtPolicyLib library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include + + +/** + Update Tbt Policy Callback +**/ + +VOID +EFIAPI +UpdateTbtPolicyCallback ( + VOID + ) +{ + EFI_STATUS Status; + DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; + + DxeTbtConfig =3D NULL; + Status =3D EFI_NOT_FOUND; + DEBUG ((DEBUG_INFO, "UpdateTbtPolicyCallback\n")); + + Status =3D gBS->LocateProtocol ( + &gDxeTbtPolicyProtocolGuid, + NULL, + (VOID **) &DxeTbtConfig + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n")); + } else { + + } + + return; +} + +/** + Print DXE TBT Policy +**/ +VOID +TbtPrintDxePolicyConfig ( + VOID + ) +{ + EFI_STATUS Status; + UINT8 Index; + DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; + + DEBUG ((DEBUG_INFO, "TbtPrintDxePolicyConfig Start\n")); + + DxeTbtConfig =3D NULL; + Status =3D EFI_NOT_FOUND; + Status =3D gBS->LocateProtocol ( + &gDxeTbtPolicyProtocolGuid, + NULL, + (VOID **) &DxeTbtConfig + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " gDxeTbtPolicyProtocolGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + // + // Print DTBT Policy + // + DEBUG ((DEBUG_ERROR, " =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D DXE TBT POLICY =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D \n")); + for (Index =3D 0; Index < MAX_DTBT_CONTROLLER_NUMBER; Index++) { + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieExtr= aBusRsvd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcie= ExtraBusRsvd)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemR= svd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPcieMemRs= vd)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPcieMemA= ddrRngMax =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPci= eMemAddrRngMax)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMem= Rsvd =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPciePMem= Rsvd)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->DTbtResourceConfig[%x].DTbtPciePMem= AddrRngMax =3D %x\n", Index, DxeTbtConfig->DTbtResourceConfig[Index].DTbtPc= iePMemAddrRngMax)); + } + + // + // Print TBT Common Policy + // + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAspm =3D %x\n", Dx= eTbtConfig->TbtCommonConfig.TbtAspm)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtL1SubStates =3D %x= \n", DxeTbtConfig->TbtCommonConfig.TbtL1SubStates)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotNotify =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.TbtHotNotify)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtHotSMI =3D %x\n", = DxeTbtConfig->TbtCommonConfig.TbtHotSMI)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtLtr =3D %x\n", Dxe= TbtConfig->TbtCommonConfig.TbtLtr)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtPtm =3D %x\n", Dxe= TbtConfig->TbtCommonConfig.TbtPtm)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtSetClkReq =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.TbtSetClkReq)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport =3D = %x\n", DxeTbtConfig->TbtCommonConfig.TbtWakeupSupport)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.SecurityMode =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.SecurityMode)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Gpio5Filter =3D %x\n"= , DxeTbtConfig->TbtCommonConfig.Gpio5Filter)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TrA0OsupWa =3D %x\n",= DxeTbtConfig->TbtCommonConfig.TrA0OsupWa)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch =3D %x\= n", DxeTbtConfig->TbtCommonConfig.TbtAcDcSwitch)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3Tbt =3D %x\n", Dx= eTbtConfig->TbtCommonConfig.Rtd3Tbt)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay =3D %= x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtOffDelay)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq =3D %x\= n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReq)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay = =3D %x\n", DxeTbtConfig->TbtCommonConfig.Rtd3TbtClkReqDelay)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.Win10Support =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.Win10Support)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity = =3D %x\n", DxeTbtConfig->TbtCommonConfig.TbtVtdBaseSecurity)); + DEBUG ((DEBUG_INFO, "DxeTbtConfig->TbtCommonConfig.ControlIommu =3D %x\n= ", DxeTbtConfig->TbtCommonConfig.ControlIommu)); + return; +} + +/** + Install Tbt Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +InstallTbtPolicy ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + DXE_TBT_POLICY_PROTOCOL *DxeTbtPolicy; + + DEBUG ((DEBUG_INFO, "Install DXE TBT Policy\n")); + + DxeTbtPolicy =3D NULL; + //Alloc memory for DxeTbtPolicy + DxeTbtPolicy =3D (DXE_TBT_POLICY_PROTOCOL *) AllocateZeroPool (sizeof (D= XE_TBT_POLICY_PROTOCOL)); + if (DxeTbtPolicy =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status =3D gBS->InstallProtocolInterface ( + &ImageHandle, + &gDxeTbtPolicyProtocolGuid, + EFI_NATIVE_INTERFACE, + DxeTbtPolicy + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Install Tbt Secure Boot List protocol failed\n")= ); + } + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iDxeSmmTbtCommonLib/TbtCommonLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg= /Features/Tbt/Library/PeiDxeSmmTbtCommonLib/TbtCommonLib.c new file mode 100644 index 0000000000..690c9acf95 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiDxeSmm= TbtCommonLib/TbtCommonLib.c @@ -0,0 +1,316 @@ +/** @file + PeiTbtInit library implementition with empty functions. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Selects the proper TBT Root port to assign resources + based on the user input value + + @param[in] SetupData Pointer to Setup data + + @retval TbtSelectorChosen Rootport number. +**/ +VOID +GetRootporttoSetResourcesforTbt ( + IN UINTN RpIndex, + OUT UINT8 *RsvdExtraBusNum, + OUT UINT16 *RsvdPcieMegaMem, + OUT UINT8 *PcieMemAddrRngMax, + OUT UINT16 *RsvdPciePMegaMem, + OUT UINT8 *PciePMemAddrRngMax, + OUT BOOLEAN *SetResourceforTbt + ) +{ + UINTN TbtRpNumber; + TbtRpNumber =3D (UINTN) PcdGet8 (PcdDTbtPcieRpNumber); + + if (RpIndex =3D=3D (TbtRpNumber - 1)) { + *RsvdExtraBusNum =3D PcdGet8 (PcdDTbtPcieExtraBusRsvd); + *RsvdPcieMegaMem =3D PcdGet16 (PcdDTbtPcieMemRsvd); + *PcieMemAddrRngMax =3D PcdGet8 (PcdDTbtPcieMemAddrRngMax); + *RsvdPciePMegaMem =3D PcdGet16 (PcdDTbtPciePMemRsvd); + *PciePMemAddrRngMax =3D PcdGet8 (PcdDTbtPciePMemAddrRngMax); + *SetResourceforTbt =3D TRUE; + } + else { + *SetResourceforTbt =3D FALSE; + } + } + +/** + Internal function to Wait for Tbt2PcieDone Bit.to Set or clear + @param[in] CommandOffsetAddress Tbt2Pcie Register Address + @param[in] TimeOut Time out with 100 ms garnularity + @param[in] Tbt2PcieDone Wait condition (wait for Bit to Cl= ear/Set) + @param[out] *Tbt2PcieValue Function Register value +**/ +BOOLEAN +InternalWaitforCommandCompletion( + IN UINT64 CommandOffsetAddress, + IN UINT32 TimeOut, + IN BOOLEAN Tbt2PcieDone, + OUT UINT32 *Tbt2PcieValue + ) +{ + BOOLEAN ReturnFlag; + UINT32 Tbt2PcieCheck; + + ReturnFlag =3D FALSE; + while (TimeOut-- > 0) { + *Tbt2PcieValue =3D PciSegmentRead32 (CommandOffsetAddress); + + if (0xFFFFFFFF =3D=3D *Tbt2PcieValue ) { + // + // Device is not here return now + // + ReturnFlag =3D FALSE; + break; + } + + if(Tbt2PcieDone) { + Tbt2PcieCheck =3D *Tbt2PcieValue & TBT2PCIE_DON_R; + } else { + Tbt2PcieCheck =3D !(*Tbt2PcieValue & TBT2PCIE_DON_R); + } + + if (Tbt2PcieCheck) { + ReturnFlag =3D TRUE; + break; + } + + MicroSecondDelay(TBT_MAIL_BOX_DELAY); + } + return ReturnFlag; +} +/** + Get Security Level. + @param[in] Bus Bus number Host Router (DTBT) + @param[in] Device Device number for Host Router (DTBT) + @param[in] Function Function number for Host Router (DTBT) + @param[in] Command Command for Host Router (DTBT) + @param[in] Timeout Time out with 100 ms garnularity +**/ +UINT8 +GetSecLevel ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 Command, + IN UINT32 Timeout + ) +{ + UINT64 Pcie2Tbt; + UINT64 Tbt2Pcie; + UINT32 RegisterValue; + UINT8 ReturnFlag; + + ReturnFlag =3D 0xFF; + + DEBUG ((DEBUG_INFO, "GetSecLevel() \n")); + + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) + + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); + + if(InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE, &RegisterVa= lue)) { + ReturnFlag =3D (UINT8) (0xFF & (RegisterValue >> 8)); + } + + PciSegmentWrite32 (Pcie2Tbt, 0); + + InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValu= e); + DEBUG ((DEBUG_INFO, "Security Level configured to %x \n", ReturnFlag)); + + return ReturnFlag; +} + +/** + Set Security Level. + @param[in] Data Security State + @param[in] Bus Bus number for Host Router (DTBT) + @param[in] Device Device number for Host Router (DTBT) + @param[in] Function Function number for Host Router (DTBT) + @param[in] Command Command for Host Router (DTBT) + @param[in] Timeout Time out with 100 ms garnularity +**/ +BOOLEAN +SetSecLevel ( + IN UINT8 Data, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 Command, + IN UINT32 Timeout + ) +{ + UINT64 Pcie2Tbt; + UINT64 Tbt2Pcie; + UINT32 RegisterValue; + BOOLEAN ReturnFlag; + + ReturnFlag =3D FALSE; + + DEBUG ((DEBUG_INFO, "SetSecLevel() \n")); + + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) + + PciSegmentWrite32 (Pcie2Tbt, (Data << 8) | Command | PCIE2TBT_VLD_B); + + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,= &RegisterValue); + DEBUG ((DEBUG_INFO, "RegisterValue %x \n", RegisterValue)); + PciSegmentWrite32 (Pcie2Tbt, 0); + + InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, FALSE, &RegisterValu= e); + DEBUG ((DEBUG_INFO, "Return value %x \n", ReturnFlag)); + return ReturnFlag; +} + +/** +Based on the Security Mode Selection, BIOS drives FORCE_PWR. + +@param[in] GpioNumber +@param[in] Value +**/ +VOID +ForceDtbtPower( + IN UINT8 GpioAccessType, + IN UINT8 Expander, + IN UINT32 GpioNumber, + IN BOOLEAN Value +) +{ + if (GpioAccessType =3D=3D 0x01) { + // PCH + GpioSetOutputValue (GpioNumber, (UINT32)Value); + } else if (GpioAccessType =3D=3D 0x02) { + // IoExpander {TCA6424A} + GpioExpSetOutput (Expander, (UINT8)GpioNumber, (UINT8)Value); + } +} + +/** +Execute TBT Mail Box Command + +@param[in] Command TBT Command +@param[in] Bus Bus number for Host Router (DTBT) +@param[in] Device Device number for Host Router (DTBT) +@param[in] Function Function number for Host Router (DTBT) +@param[in] Timeout Time out with 100 ms garnularity +@Retval true if command executes succesfully +**/ +BOOLEAN +TbtSetPcie2TbtCommand( + IN UINT8 Command, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT32 Timeout +) +{ + UINT64 Pcie2Tbt; + UINT64 Tbt2Pcie; + UINT32 RegisterValue; + BOOLEAN ReturnFlag; + + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) + + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); + + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE= , &RegisterValue); + + PciSegmentWrite32(Pcie2Tbt, 0); + + return ReturnFlag; +} +/** + Get Pch/Peg Pcie Root Port Device and Function Number for TBT by Root Po= rt physical Number + + @param[in] RpNumber Root port physical number. (0-based) + @param[out] RpDev Return corresponding root port device = number. + @param[out] RpFun Return corresponding root port functio= n number. + + @retval EFI_SUCCESS Root port device and function is retri= eved + @retval EFI_INVALID_PARAMETER If Invalid Root Port Number or TYPE is= Passed +**/ +EFI_STATUS +EFIAPI +GetDTbtRpDevFun ( + IN BOOLEAN Type, + IN UINTN RpNumber, + OUT UINTN *RpDev, + OUT UINTN *RpFunc + ) +{ + EFI_STATUS Status; + UINTN TbtRpDev; + UINTN TbtRpFunc; + + Status =3D EFI_INVALID_PARAMETER; // Update the Status to EFI_SUCCESS if= valid input found. + // + // PCH-H can support up to 24 root ports. PEG0,PEG1 and PEG2 will be + // with device number 0x1 and Function number 0,1 and 2 respectively. + // + if (Type =3D=3D DTBT_TYPE_PEG) + { + // + // PEG Rootport + // + if (RpNumber <=3D 2) { + *RpDev =3D 0x01; + *RpFunc =3D RpNumber; + Status =3D EFI_SUCCESS; + } + } + if (Type =3D=3D DTBT_TYPE_PCH) + { + // + // PCH Rootport + // + if (RpNumber <=3D 23) { + Status =3D GetPchPcieRpDevFun (RpNumber, &TbtRpDev, &TbtRpFunc); + *RpDev =3D TbtRpDev; + *RpFunc =3D TbtRpFunc; + } + } + + ASSERT_EFI_ERROR (Status); + return Status; +} + +BOOLEAN +IsTbtHostRouter ( + IN UINT16 DeviceID + ) +{ + switch (DeviceID) { + case AR_HR_2C: + case AR_HR_4C: + case AR_HR_LP: + case AR_HR_C0_2C: + case AR_HR_C0_4C: + case TR_HR_2C: + case TR_HR_4C: + return TRUE; + } + + return FALSE; +} // IsTbtHostRouter + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pe= iTbtPolicyLib/PeiTbtPolicyLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Fe= atures/Tbt/Library/PeiTbtPolicyLib/PeiTbtPolicyLib.c new file mode 100644 index 0000000000..ffd8416660 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/PeiTbtPol= icyLib/PeiTbtPolicyLib.c @@ -0,0 +1,206 @@ +/** @file + This file is PeiTbtPolicyLib library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Update PEI TBT Policy Callback +**/ +VOID +EFIAPI +UpdatePeiTbtPolicy ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + PEI_TBT_POLICY *PeiTbtConfig; + + PeiTbtConfig =3D NULL; + Status =3D EFI_NOT_FOUND; + + DEBUG ((DEBUG_INFO, "UpdatePeiTbtPolicy \n")); + + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **) &VariableServices + ); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesLocatePpi ( + &gPeiTbtPolicyPpiGuid, + 0, + NULL, + (VOID **) &PeiTbtConfig + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + + // + // Update DTBT Policy + // + PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn =3D PcdGet8 (PcdDTb= tControllerEn); + if (PcdGet8 (PcdDTbtControllerType) =3D=3D TYPE_PEG) + { + PeiTbtConfig-> DTbtControllerConfig.Type =3D (UINT8) TYPE_PEG; + PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D 1; // PEG RP 1 (F= unction no. 0) + } + else { + PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber =3D PcdGet8 (PcdDTbtP= cieRpNumber); + PeiTbtConfig-> DTbtControllerConfig.Type =3D PcdGet8 (PcdDTbtControlle= rType); + } + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D (GPIO_PA= D) PcdGet32 (PcdDTbtCioPlugEventGpioPad); + if (GpioCheckFor2Tier(PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpi= o.GpioPad)) { + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo= rting =3D 0; + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = =3D SIGNATURE_32('X', 'T', 'B', 'T'); + } + else { + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePo= rting =3D 1; + // + // Update Signature based on platform GPIO. + // + PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature = =3D SIGNATURE_32('X', 'T', 'B', 'T'); + } + PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D PcdGet8 (PcdDTbtBootOn); + PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D PcdGet8 (PcdDTbtUsbOn); + PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D PcdGet8 (PcdDTbtGpio3Fo= rcePwr); + PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D PcdGet16 (PcdDTbtGpi= o3ForcePwrDly); + + return; +} + +/** + Print PEI TBT Policy +**/ +VOID +EFIAPI +TbtPrintPeiPolicyConfig ( + VOID + ) +{ + DEBUG_CODE_BEGIN (); + EFI_STATUS Status; + PEI_TBT_POLICY *PeiTbtConfig; + + PeiTbtConfig =3D NULL; + Status =3D EFI_NOT_FOUND; + DEBUG ((DEBUG_INFO, "TbtPrintPolicyConfig Start\n")); + + Status =3D PeiServicesLocatePpi ( + &gPeiTbtPolicyPpiGuid, + 0, + NULL, + (VOID **) &PeiTbtConfig + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + + // + // Print DTBT Policy + // + DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print B= EGIN -----------------\n")); + DEBUG ((DEBUG_INFO, "Revision : 0x%x\n", PEI_TBT_POLICY_REVISION)); + DEBUG ((DEBUG_INFO, "------------------------ PEI_TBT_CONFIG ----------= -------\n")); + DEBUG ((DEBUG_INFO, " Revision : %d\n", PEI_TBT_POLICY_REVISION)); + + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.DTbtControllerEn= =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.Type =3D %x\n", = PeiTbtConfig-> DTbtControllerConfig.Type)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRpNumber =3D= %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.Gpi= oPad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.ForcePwrGpio.Gpi= oLevel =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioLeve= l)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.Gpio= Pad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioPad)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.PcieRstGpio.Gpio= Level =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.PcieRstGpio.GpioLevel)= ); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .GpioPad =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.Gp= ioPad)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .AcpiGpeSignature =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.CioPlugEve= ntGpio.AcpiGpeSignature)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtControllerConfig.CioPlugEventGpio= .AcpiGpeSignaturePorting =3D %x\n", PeiTbtConfig-> DTbtControllerConfig.Cio= PlugEventGpio.AcpiGpeSignaturePorting)); + + + // + // Print DTBT Common Policy + // + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D %x\n",= PeiTbtConfig->DTbtCommonConfig.TbtBootOn)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.TbtUsbOn =3D %x\n", = PeiTbtConfig->DTbtCommonConfig.TbtUsbOn)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr =3D %x= \n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly =3D= %x\n", PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfig= uration =3D %x\n", PeiTbtConfig->DTbtCommonConfig.DTbtSharedGpioConfigurati= on)); + DEBUG ((DEBUG_INFO, "PeiTbtConfig->DTbtCommonConfig.PcieRstSupport =3D %= x\n", PeiTbtConfig->DTbtCommonConfig.PcieRstSupport)); + + DEBUG ((DEBUG_INFO, "\n------------------------ TBT Policy (PEI) Print E= ND -----------------\n")); + DEBUG_CODE_END (); + + return; +} + +/** + Install Tbt Policy + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +InstallPeiTbtPolicy ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PeiTbtPolicyPpiDesc; + PEI_TBT_POLICY *PeiTbtConfig; + + DEBUG ((DEBUG_INFO, "Install PEI TBT Policy\n")); + + PeiTbtConfig =3D NULL; + + // + // Allocate memory for PeiTbtPolicyPpiDesc + // + PeiTbtPolicyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (siz= eof (EFI_PEI_PPI_DESCRIPTOR)); + ASSERT (PeiTbtPolicyPpiDesc !=3D NULL); + if (PeiTbtPolicyPpiDesc =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Allocate memory and initialize all default to zero for PeiTbtPolicy + // + PeiTbtConfig =3D (PEI_TBT_POLICY *) AllocateZeroPool (sizeof (PEI_TBT_PO= LICY)); + ASSERT (PeiTbtConfig !=3D NULL); + if (PeiTbtConfig =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Initialize PPI + // + PeiTbtPolicyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_= DESCRIPTOR_TERMINATE_LIST; + PeiTbtPolicyPpiDesc->Guid =3D &gPeiTbtPolicyPpiGuid; + PeiTbtPolicyPpiDesc->Ppi =3D PeiTbtConfig; + + Status =3D PeiServicesInstallPpi (PeiTbtPolicyPpiDesc); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Install PEI TBT Policy failed\n")); + } + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Pr= ivate/PeiDTbtInitLib/PeiDTbtInitLib.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/Features/Tbt/Library/Private/PeiDTbtInitLib/PeiDTbtInitLib.c new file mode 100644 index 0000000000..f33ddebdb3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Library/Private/P= eiDTbtInitLib/PeiDTbtInitLib.c @@ -0,0 +1,567 @@ +/** @file + Thunderbolt(TM) Pei Library + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** +Is host router (For dTBT) or End Point (For iTBT) present before sleep + +@param[in] ControllerType - DTBT_CONTROLLER or ITBT_CONTROLLER +@param[in] Controller - Controller begin offset of CMOS + +@Retval TRUE There is a TBT HostRouter presented before sleep +@Retval FALSE There is no TBT HostRouter presented before sleep + +BOOLEAN +IsHostRouterPresentBeforeSleep( +IN UINT8 ControllerType, +IN UINT8 Controller +) +{ + UINT8 SavedState; + + SavedState =3D (UINT8)GetTbtHostRouterStatus(); + if (ControllerType =3D=3D DTBT_CONTROLLER){ + return ((SavedState & (DTBT_SAVE_STATE_OFFSET << Controller)) =3D=3D (= DTBT_SAVE_STATE_OFFSET << Controller)); + } else { + if (ControllerType =3D=3D ITBT_CONTROLLER) { + return ((SavedState & (ITBT_SAVE_STATE_OFFSET << Controller)) =3D=3D= (ITBT_SAVE_STATE_OFFSET << Controller)); + } + } + return 0; +} +**/ + +/** +Execute TBT PCIE2TBT_SX_EXIT_TBT_CONNECTED Mail Box Command for S4 mode wi= th PreBootAclEnable + +@param[in] Bus Bus number for Host Router (DTBT) +@param[in] Device Device number for Host Router (DTBT) +@param[in] Function Function number for Host Router (DTBT) +@param[in] Timeout Time out with 100 ms garnularity +@Retval true if command executes succesfully +**/ +BOOLEAN +TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT32 Timeout +) +{ + UINT64 Pcie2Tbt; + UINT64 Tbt2Pcie; + UINT32 RegisterValue; + BOOLEAN ReturnFlag; + UINT32 Command; + + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + GET_PCIE2TBT_REGISTER_ADDRESS(0, Bus, Device, Function, Pcie2Tbt) + +// If PreBootAcl is Enable, we need to enable DATA bit while sending SX EX= IT MAIL BOX Command + Command =3D (1 << 8) | PCIE2TBT_SX_EXIT_TBT_CONNECTED; + PciSegmentWrite32 (Pcie2Tbt, Command | PCIE2TBT_VLD_B); + + ReturnFlag =3D InternalWaitforCommandCompletion(Tbt2Pcie, Timeout, TRUE,= &RegisterValue); + + PciSegmentWrite32(Pcie2Tbt, 0); + + return ReturnFlag; +} + +/** +Set the Sleep Mode if the HR is up. +@param[in] Bus Bus number for Host Router (DTBT) +@param[in] Device Device number for Host Router (DTBT) +@param[in] Function Function number for Host Router (DTBT) +**/ +VOID +TbtSetSxMode( +IN UINT8 Bus, +IN UINT8 Device, +IN UINT8 Function, +IN UINT8 TbtBootOn +) +{ + UINT64 TbtUsDevId; + UINT64 Tbt2Pcie; + UINT32 RegVal; + UINT32 MaxLoopCount; + UINTN Delay; + UINT8 RetCode; + EFI_BOOT_MODE BootMode; + EFI_STATUS Status; + + TbtUsDevId =3D PCI_SEGMENT_LIB_ADDRESS(0, Bus, Device, Function, 0); + GET_TBT2PCIE_REGISTER_ADDRESS(0, Bus, Device, Function, Tbt2Pcie) + + MaxLoopCount =3D TBT_5S_TIMEOUT; // Wait 5 sec + Delay =3D 100 * 1000; + RetCode =3D 0x62; + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + if ((BootMode =3D=3D BOOT_ON_S4_RESUME) && (TbtBootOn =3D=3D 2)) { + MaxLoopCount =3D TBT_3S_TIMEOUT; + if (!TbtSetPcie2TbtSxExitCommandWithPreBootAclEnable(Bus, Device, Func= tion, MaxLoopCount)) { + // + // Nothing to wait, HR is not responsive + // + return; + } + } + else { + if (!TbtSetPcie2TbtCommand(PCIE2TBT_SX_EXIT_TBT_CONNECTED, Bus, Device= , Function, MaxLoopCount)) { + // + // Nothing to wait, HR is not responsive + // + return; + } + } + + DEBUG((DEBUG_INFO, "Wait for Dev ID !=3D 0xFF\n")); + + while (MaxLoopCount-- > 0) { + // + // Check what HR still here + // + RegVal =3D PciSegmentRead32(Tbt2Pcie); + if (0xFFFFFFFF =3D=3D RegVal) { + RetCode =3D 0x6F; + break; + } + // + // Check completion of TBT link + // + RegVal =3D PciSegmentRead32(TbtUsDevId); + if (0xFFFFFFFF !=3D RegVal) { + RetCode =3D 0x61; + break; + } + + MicroSecondDelay(Delay); + } + + DEBUG((DEBUG_INFO, "Return code =3D 0x%x\n", RetCode)); +} +/** + set tPCH25 Timing to 10 ms for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtSetTPch25Timing ( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + DEBUG ((DEBUG_INFO, "DTbtSetTPch25Timing call Inside\n")); + UINT32 PchPwrmBase; + + // + //During boot, reboot and wake tPCH25 Timing should be set to 10 ms + // + MmioOr32 ( + (UINTN) (PchPwrmBase + R_PCH_PWRM_CFG), + (BIT0 | BIT1) + ); + + DEBUG((DEBUG_INFO, "DTbtSetTPch25Timing call Return\n")); + return EFI_SUCCESS; +} + +/** + Do ForcePower for DTBT Controller + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtForcePower ( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + + DEBUG ((DEBUG_INFO, "DTbtForcePower call Inside\n")); + + if (PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwr) { + DEBUG((DEBUG_INFO, "ForcePwrGpio.GpioPad =3D %x \n", PeiTbtConfig-= > DTbtControllerConfig.ForcePwrGpio.GpioPad)); + ForceDtbtPower(PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Gp= ioAccessType,PeiTbtConfig-> DTbtControllerConfig.ForcePwrGpio.Expander, Pei= TbtConfig-> DTbtControllerConfig.ForcePwrGpio.GpioPad, PeiTbtConfig-> DTbtC= ontrollerConfig.ForcePwrGpio.GpioLevel); + DEBUG((DEBUG_INFO, "ForceDtbtPower asserted \n")); + MicroSecondDelay(PeiTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly *= 1000); + DEBUG((DEBUG_INFO, "Delay after ForceDtbtPower =3D 0x%x ms \n", Pe= iTbtConfig->DTbtCommonConfig.Gpio3ForcePwrDly)); + } + + DEBUG ((DEBUG_INFO, "DTbtForcePower call Return\n")); + return EFI_SUCCESS; +} + +/** + Clear VGA Registers for DTBT. + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtClearVgaRegisters ( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + UINTN RpDev; + UINTN RpFunc; + EFI_STATUS Status; + UINT64 BridngeBaseAddress; + UINT16 Data16; + + DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Inside\n")); + + Status =3D EFI_SUCCESS; + + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type, Pei= TbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR(Status); + // + // VGA Enable and VGA 16-bit decode registers of Bridge control register= of Root port where + // Host router resides should be cleaned + // + + BridngeBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0, (UINT32)RpDev, (UIN= T32)RpFunc, 0); + Data16 =3D PciSegmentRead16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGI= STER_OFFSET); + Data16 &=3D (~(EFI_PCI_BRIDGE_CONTROL_VGA | EFI_PCI_BRIDGE_CONTROL_VGA_1= 6)); + PciSegmentWrite16(BridngeBaseAddress + PCI_BRIDGE_CONTROL_REGISTER_OFFSE= T, Data16); + + DEBUG ((DEBUG_INFO, "DTbtClearVgaRegisters call Return\n")); + return Status; +} + +/** + Exectue Mail box command "Boot On". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtBootOn( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + EFI_STATUS Status; + UINT32 OrgBusNumberConfiguration; + UINTN RpDev; + UINTN RpFunc; + + DEBUG((DEBUG_INFO, "DTbtBootOn call Inside\n")); + + Status =3D EFI_SUCCESS; + + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR(Status); + OrgBusNumberConfiguration =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDR= ESS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); + // + // Set Sec/Sub buses to 0xF0 + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); + // + //When Thunderbolt(TM) boot [TbtBootOn] is enabled in bios setup we = need to do the below: + //Bios should send "Boot On" message through PCIE2TBT register + //The Boot On command as described above would include the command a= nd acknowledge from FW (with the default timeout in BIOS), + //once the Boot On command is completed it is guaranteed that the Al= pineRidge(AR) device is there and the PCI tunneling was done by FW, + //next step from BIOS is enumeration using SMI + // + + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) { + // + // Exectue Mail box command "Boot On / Pre-Boot ACL" + // + //Command may be executed only during boot/reboot and not during S= x exit flow + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 1) { + if (!TbtSetPcie2TbtCommand(PCIE2TBT_BOOT_ON, 0xF0, 0, 0, TBT_5S_= TIMEOUT)) { + // + // Nothing to wait, HR is not responsive + // + DEBUG((DEBUG_INFO, " DTbtBootOn - Boot On message sent= failed \n")); + } + } + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2) { + if (!TbtSetPcie2TbtCommand(PCIE2TBT_PREBOOTACL, 0xF0, 0, 0, TBT_= 3S_TIMEOUT)) { + // + // Nothing to wait, HR is not responsive + // + DEBUG((DEBUG_INFO, " DTbtBootOn - Pre-Boot ACL message= sent failed \n")); + } + } + } + // + // Reset Sec/Sub buses to original value + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); + + DEBUG((DEBUG_INFO, "DTbtBootOn call Return\n")); + return Status; +} + +/** + Exectue Mail box command "USB On". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtUsbOn( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + EFI_STATUS Status; + UINTN RpDev; + UINTN RpFunc; + UINT32 OrgBusNumberConfiguration; + UINT64 TbtBaseAddress; + UINT32 MaxWaitIter; + UINT32 RegVal; + EFI_BOOT_MODE BootMode; + + DEBUG((DEBUG_INFO, "DTbtUsbOn call Inside\n")); + + Status =3D EFI_SUCCESS; + + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR(Status); + OrgBusNumberConfiguration =3D PciSegmentRead32(PCI_SEGMENT_LIB_ADDRE= SS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); + // + // Set Sec/Sub buses to 0xF0 + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); + + // + //When Thunderbolt(TM) Usb boot [TbtUsbOn] is enabled in bios setup = we need to do the below: + //Bios should send "Usb On" message through PCIE2TBT register + //The Usb On command as described above would include the command an= d acknowledge from FW (with the default timeout in BIOS), + //once the Usb On command is completed it is guaranteed that the Alp= ineRidge(AR) device is there and the PCI tunneling was done by FW, + //next step from BIOS is enumeration using SMI + // + if (PeiTbtConfig->DTbtCommonConfig.TbtUsbOn) { + if (PeiTbtConfig->DTbtCommonConfig.TbtBootOn > 0) { + MaxWaitIter =3D 50; // Wait 5 sec + TbtBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(0, 0xF0, 0, 0, 0); + // + // Driver clears the PCIe2TBT Valid bit to support two consicuti= ve mailbox commands + // + PciSegmentWrite32(TbtBaseAddress + PCIE2TBT_DTBT_R, 0); + DEBUG((DEBUG_INFO, "TbtBaseAddress + PCIE2TBT_DTBT_R =3D 0x%lx \= n", TbtBaseAddress + PCIE2TBT_DTBT_R)); + while (MaxWaitIter-- > 0) { + RegVal =3D PciSegmentRead32(TbtBaseAddress + TBT2PCIE_DTBT_R); + if (0xFFFFFFFF =3D=3D RegVal) { + // + // Device is not here return now + // + DEBUG((DEBUG_INFO, "TBT device is not present \n")); + break; + } + + if (!(RegVal & TBT2PCIE_DON_R)) { + break; + } + MicroSecondDelay(100 * 1000); + } + } + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + // + // Exectue Mail box command "Usb On" + // + //Command may be executed only during boot/reboot and not during S= 3 exit flow + //In case of S4 Exit send USB ON cmd only if Host Router was inact= ive/not present during S4 entry + if ((BootMode =3D=3D BOOT_ON_S4_RESUME) ) { + // USB_ON cmd not required + } else { + if (!TbtSetPcie2TbtCommand(PCIE2TBT_USB_ON, 0xF0, 0, 0, TBT_5S_T= IMEOUT)) { + // + // Nothing to wait, HR is not responsive + // + DEBUG((DEBUG_INFO, " TbtBootSupport - Usb On message s= ent failed \n")); + } + } + } + // + // Reset Sec/Sub buses to original value + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); + + DEBUG((DEBUG_INFO, "DTbtUsbOn call return\n")); + return Status; +} + +/** + Exectue Mail box command "Sx Exit". + + @param[in] PEI_TBT_POLICY PeiTbtConfig + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_UNSUPPORTED dTBT is not supported. +**/ +EFI_STATUS +EFIAPI +DTbtSxExitFlow( + IN PEI_TBT_POLICY *PeiTbtConfig +) +{ + EFI_STATUS Status; + UINT32 OrgBusNumberConfiguration; + UINTN RpDev; + UINTN RpFunc; + UINT32 Count; + + DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Inside\n")); + + Status =3D EFI_SUCCESS; + Count =3D 0; + + Status =3D GetDTbtRpDevFun(PeiTbtConfig-> DTbtControllerConfig.Type,= PeiTbtConfig-> DTbtControllerConfig.PcieRpNumber - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR(Status); + OrgBusNumberConfiguration =3D PciSegmentRead32(PCI_SEGMENT_LIB_ADDRE= SS (0, 0, RpDev, RpFunc, PCI_BRIDGE_PRIMARY_BUS_REGISTER_OFFSET)); + // + // Set Sec/Sub buses to 0xF0 + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), 0x00F0F000); + + if ( (PeiTbtConfig->DTbtCommonConfig.TbtBootOn =3D=3D 2)) { + // + // WA: When system with TBT 3.1 device, resume SX system need to w= ait device ready. In document that maximum time out should be 500ms. + // + while (PciSegmentRead32(PCI_SEGMENT_LIB_ADDRESS(0, 0xf0, 0x0, 0x0,= 0x08)) =3D=3D 0xffffffff) { //End Device will be with Device Number 0x0, F= unction Number 0x0. + MicroSecondDelay(STALL_ONE_MICRO_SECOND * 1000); // 1000usec + Count++; + if (Count > 10000) { //Allowing Max Delay of 10 sec for CFL-S bo= ard. + break; + } + } + + // + // Upon wake, if BIOS saved pre-Sx Host Router state as active (sy= stem went to sleep with + // attached devices), BIOS should: + // 1. Execute "Sx_Exit_TBT_Connected" mailbox command. + // 2. If procedure above returns true, BIOS should perform "wait f= or fast link bring-up" loop + // 3. Continue regular wake flow. + // + // + // Exectue Mail box command and perform "wait for fast link bring-= up" loop + // + TbtSetSxMode(0xF0, 0, 0, PeiTbtConfig->DTbtCommonConfig.TbtBootOn); + } + // + // Reset Sec/Sub buses to original value + // + PciSegmentWrite32(PCI_SEGMENT_LIB_ADDRESS (0, 0, RpDev, RpFunc, PCI_= BRIDGE_PRIMARY_BUS_REGISTER_OFFSET), OrgBusNumberConfiguration); + + DEBUG((DEBUG_INFO, "DTbtSxExitFlow call Return\n")); + return Status; +} + + +/** + Initialize Thunderbolt(TM) + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ +EFI_STATUS +EFIAPI +TbtInit ( + VOID + ) +{ + EFI_STATUS Status; + PEI_TBT_POLICY *PeiTbtConfig; + + // + // Get the TBT Policy + // + Status =3D PeiServicesLocatePpi ( + &gPeiTbtPolicyPpiGuid, + 0, + NULL, + (VOID **) &PeiTbtConfig + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + // + // Exectue Mail box command "Boot On" + // + Status =3D DTbtBootOn (PeiTbtConfig); + // + // Exectue Mail box command "Usb On" + // + Status =3D DTbtUsbOn (PeiTbtConfig); + // + //During boot, reboot and wake (bits [1:0]) of PCH PM_CFG register shou= ld be + //set to 11b - 10 ms (default value is 0b - 10 us) + // + Status =3D DTbtSetTPch25Timing (PeiTbtConfig); + // + // Configure Tbt Force Power + // + Status =3D DTbtForcePower (PeiTbtConfig); + // + // VGA Enable and VGA 16-bit decode registers of Bridge control register= of Root port where + // Host router resides should be cleaned + // + Status =3D DTbtClearVgaRegisters (PeiTbtConfig); + // + // Upon wake, if BIOS saved pre-Sx Host Router state as active (system w= ent to sleep with + // attached devices), BIOS should: + // 1. Execute "Sx_Exit_TBT_Connected" mailbox command. + // 2. If procedure above returns true, BIOS should perform "wait for fas= t link bring-up" loop + // 3. Continue regular wake flow. + // + Status =3D DTbtSxExitFlow (PeiTbtConfig); + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspCpuPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c new file mode 100644 index 0000000000..f38901f2ae --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspCpuPolicyInitLib.c @@ -0,0 +1,461 @@ +/** @file + Implementation of Fsp CPU Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP CPU PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n= ")); + + // + // Locate SiPreMemPolicyPpi + // + SiPreMemPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclocking= PreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre= MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); + ASSERT_EFI_ERROR (Status); + + /// + /// + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n")= ); + + // + // Overclocking PreMem policies + // + FspmUpd->FspmConfig.OcSupport =3D (UINT8) CpuOverClockingP= reMemConfig->OcSupport; + FspmUpd->FspmConfig.OcLock =3D (UINT8) CpuOverClockingP= reMemConfig->OcLock; + FspmUpd->FspmConfig.CoreMaxOcRatio =3D (UINT8) CpuOverClockingP= reMemConfig->CoreMaxOcRatio; + FspmUpd->FspmConfig.CoreVoltageMode =3D (UINT8) CpuOverClockingP= reMemConfig->CoreVoltageMode; + FspmUpd->FspmConfig.CoreVoltageOverride =3D (UINT16) CpuOverClocking= PreMemConfig->CoreVoltageOverride; + FspmUpd->FspmConfig.CoreVoltageAdaptive =3D (UINT16) CpuOverClocking= PreMemConfig->CoreVoltageAdaptive; + FspmUpd->FspmConfig.CoreVoltageOffset =3D (UINT16) CpuOverClocking= PreMemConfig->CoreVoltageOffset; + FspmUpd->FspmConfig.CorePllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->CorePllVoltageOffset; + FspmUpd->FspmConfig.RingMaxOcRatio =3D (UINT8) CpuOverClockingP= reMemConfig->RingMaxOcRatio; + FspmUpd->FspmConfig.RingVoltageOverride =3D (UINT16) CpuOverClocking= PreMemConfig->RingVoltageOverride; + FspmUpd->FspmConfig.RingVoltageAdaptive =3D (UINT16) CpuOverClocking= PreMemConfig->RingVoltageAdaptive; + FspmUpd->FspmConfig.RingVoltageOffset =3D (UINT16) CpuOverClocking= PreMemConfig->RingVoltageOffset; + FspmUpd->FspmConfig.RingPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->RingPllVoltageOffset; + FspmUpd->FspmConfig.GtPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->GtPllVoltageOffset; + FspmUpd->FspmConfig.RingPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->RingPllVoltageOffset; + FspmUpd->FspmConfig.SaPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->SaPllVoltageOffset; + FspmUpd->FspmConfig.McPllVoltageOffset =3D (UINT8) CpuOverClockingP= reMemConfig->McPllVoltageOffset; + FspmUpd->FspmConfig.RingDownBin =3D (UINT8) CpuOverClockingP= reMemConfig->RingDownBin; + FspmUpd->FspmConfig.RingVoltageMode =3D (UINT8) CpuOverClockingP= reMemConfig->RingVoltageMode; + FspmUpd->FspmConfig.Avx2RatioOffset =3D (UINT8) CpuOverClockingP= reMemConfig->Avx2RatioOffset; + FspmUpd->FspmConfig.Avx3RatioOffset =3D (UINT8) CpuOverClockingP= reMemConfig->Avx3RatioOffset; + FspmUpd->FspmConfig.BclkAdaptiveVoltage =3D (UINT8) CpuOverClockingP= reMemConfig->BclkAdaptiveVoltage; + FspmUpd->FspmConfig.TjMaxOffset =3D (UINT8) CpuOverClockingP= reMemConfig->TjMaxOffset; + FspmUpd->FspmConfig.TvbRatioClipping =3D (UINT8) CpuOverClockingP= reMemConfig->TvbRatioClipping; + FspmUpd->FspmConfig.TvbVoltageOptimization =3D (UINT8) CpuOverClockingP= reMemConfig->TvbVoltageOptimization; + + // + // Cpu Config Lib policies + // + FspmUpd->FspmConfig.HyperThreading =3D (UINT8) CpuConfigLibPr= eMemConfig->HyperThreading; + FspmUpd->FspmConfig.BootFrequency =3D (UINT8) CpuConfigLibPr= eMemConfig->BootFrequency; + FspmUpd->FspmConfig.ActiveCoreCount =3D (UINT8) CpuConfigLibPr= eMemConfig->ActiveCoreCount; + FspmUpd->FspmConfig.JtagC10PowerGateDisable =3D (UINT8) CpuConfigLibPr= eMemConfig->JtagC10PowerGateDisable; + FspmUpd->FspmConfig.FClkFrequency =3D (UINT8) CpuConfigLibPr= eMemConfig->FClkFrequency; + FspmUpd->FspmConfig.BistOnReset =3D (UINT8) CpuConfigLibPr= eMemConfig->BistOnReset; + FspmUpd->FspmConfig.VmxEnable =3D (UINT8) CpuConfigLibPr= eMemConfig->VmxEnable; + FspmUpd->FspmConfig.CpuRatio =3D (UINT8) CpuConfigLibPr= eMemConfig->CpuRatio; + FspmUpd->FspmConfig.PeciSxReset =3D (UINT8) CpuConfigLibPr= eMemConfig->PeciSxReset; + FspmUpd->FspmConfig.PeciC10Reset =3D (UINT8) CpuConfigLibPr= eMemConfig->PeciC10Reset; + FspmUpd->FspmConfig.SkipMpInit =3D (UINT8) CpuConfigLibPr= eMemConfig->SkipMpInit; + FspmUpd->FspmConfig.DpSscMarginEnable =3D (UINT8) CpuConfigLibPr= eMemConfig->DpSscMarginEnable; + + // + // DisableMtrrProgram <1> Disable Mtrrs program. <0> Program Mtrrs in FSP + // + FspmUpd->FspmConfig.DisableMtrrProgram =3D (UINT8) 0; + + return EFI_SUCCESS; +} + +/** + This routine is used to get Sec Platform Information Record2 Pointer. + + @param[in] PeiServices Pointer to the PEI services table + + @retval GetSecPlatformInformation2 - The pointer of Sec Platform Informat= ion Record2 Pointer. + **/ + +EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformation2( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_SEC_PLATFORM_INFORMATION2_PPI *SecPlatformInformation2Ppi; + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2 =3D NULL; + UINT64 InformationSize; + EFI_STATUS Status; + + // + // Get BIST information from Sec Platform Information2 Ppi firstly + // + Status =3D PeiServicesLocatePpi ( + &gEfiSecPlatformInformation2PpiGuid, // GUID + 0, // Instance + NULL, // EFI_PEI_PPI_DESCRIP= TOR + (VOID ** ) &SecPlatformInformation2Ppi // PPI + ); + + DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi2 Status - %x\n",= Status)); + if (EFI_ERROR(Status)) { + return NULL; + } + + InformationSize =3D 0; + + Status =3D SecPlatformInformation2Ppi->PlatformInformation2 ( + (CONST EFI_PEI_SERVICES **) PeiS= ervices, + &InformationSize, + SecPlatformInformation2 + ); + + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + if (Status !=3D EFI_BUFFER_TOO_SMALL) { + return NULL; + } + + SecPlatformInformation2 =3D AllocatePool((UINTN)InformationSize); + ASSERT (SecPlatformInformation2 !=3D NULL); + if (SecPlatformInformation2 =3D=3D NULL) { + return NULL; + } + + // + // Retrieve BIST data from SecPlatform2 + // + Status =3D SecPlatformInformation2Ppi->PlatformInformation2 ( + PeiServices, + &InformationSize, + SecPlatformInformation2 + ); + DEBUG((DEBUG_INFO, "SecPlatformInformation2Ppi->PlatformInformation2 Sta= tus - %x\n", Status)); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return NULL; + } + + return SecPlatformInformation2; +} + +/** + This routine is used to get Sec Platform Information Record Pointer. + + @param[in] PeiServices Pointer to the PEI services table + + @retval GetSecPlatformInformation2 - The pointer of Sec Platform Informat= ion Record Pointer. + **/ +EFI_SEC_PLATFORM_INFORMATION_RECORD2 * GetSecPlatformInformationInfoInForm= at2( + IN EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_SEC_PLATFORM_INFORMATION_PPI *SecPlatformInformationPpi; + EFI_SEC_PLATFORM_INFORMATION_RECORD *SecPlatformInformation =3D NULL; + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2; + UINT64 InformationSize; + EFI_STATUS Status; + + // + // Get BIST information from Sec Platform Information + // + Status =3D PeiServicesLocatePpi ( + &gEfiSecPlatformInformationPpiGuid, // GUID + 0, // Instance + NULL, // EFI_PEI_PPI_DESCRIP= TOR + (VOID ** ) &SecPlatformInformationPpi // PPI + ); + + DEBUG((DEBUG_INFO, "LocatePpi SecPlatformInformationPpi Status - %x\n", = Status)); + if (EFI_ERROR(Status)) { + return NULL; + } + + InformationSize =3D 0; + Status =3D SecPlatformInformationPpi->PlatformInformation ( + (CONST EFI_PEI_SERVICES **) PeiSe= rvices, + &InformationSize, + SecPlatformInformation + ); + + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + if (Status !=3D EFI_BUFFER_TOO_SMALL) { + return NULL; + } + + SecPlatformInformation =3D AllocatePool((UINTN)InformationSize); + ASSERT (SecPlatformInformation !=3D NULL); + if (SecPlatformInformation =3D=3D NULL) { + return NULL; + } + + // + // Retrieve BIST data from SecPlatform + // + Status =3D SecPlatformInformationPpi->PlatformInformation ( + PeiServices, + &InformationSize, + SecPlatformInformation + ); + DEBUG((DEBUG_INFO, "FSP SecPlatformInformation2Ppi->PlatformInformation= Status - %x\n", Status)); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return NULL; + } + + SecPlatformInformation2 =3D AllocatePool(sizeof (EFI_SEC_PLATFORM_INFORM= ATION_RECORD2)); + ASSERT (SecPlatformInformation2 !=3D NULL); + if (SecPlatformInformation2 =3D=3D NULL) { + return NULL; + } + + SecPlatformInformation2->NumberOfCpus =3D 1; + SecPlatformInformation2->CpuInstance[0].CpuLocation =3D 0; + SecPlatformInformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32= =3D SecPlatformInformation->x64HealthFlags.Uint32; + + FreePool(SecPlatformInformation); + + return SecPlatformInformation2; +} + + +/** + Performs FSP CPU PEI Policy post memory initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspCpuPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + CPU_CONFIG *CpuConfig; + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CPU_TEST_CONFIG *CpuTestConfig; + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + UINTN Index; + EFI_SEC_PLATFORM_INFORMATION_RECORD2 *SecPlatformInformation2; + EFI_PEI_SERVICES **PeiServices; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy\n")); + PeiServices =3D (EFI_PEI_SERVICES **)GetPeiServicesTablePointer (); + // + // Locate gSiPolicyPpiGuid + // + SiPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConf= igGuid, (VOID *) &CpuPowerMgmtBasicConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtCustomCon= figGuid, (VOID *) &CpuPowerMgmtCustomConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuTestConfigGuid, (V= OID *) &CpuTestConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtTestConfi= gGuid, (VOID *) &CpuPowerMgmtTestConfig); + ASSERT_EFI_ERROR (Status); + /// + ///Production RC Policies + /// + + FspsUpd->FspsConfig.AesEnable =3D (UINT8) CpuConfig->Aes= Enable; + FspsUpd->FspsConfig.DebugInterfaceEnable =3D (UINT8) CpuConfig->Deb= ugInterfaceEnable; + + FspsUpd->FspsConfig.TurboMode =3D (UINT8) CpuPowerMgmtBa= sicConfig->TurboMode; + + /// + /// Test RC Policies + /// + FspsUpd->FspsTestConfig.MlcStreamerPrefetcher =3D (UINT8) CpuTestCo= nfig->MlcStreamerPrefetcher; + FspsUpd->FspsTestConfig.MlcSpatialPrefetcher =3D (UINT8) CpuTestCo= nfig->MlcSpatialPrefetcher; + FspsUpd->FspsTestConfig.MonitorMwaitEnable =3D (UINT8) CpuTestCo= nfig->MonitorMwaitEnable; + FspsUpd->FspsTestConfig.DebugInterfaceLockEnable =3D (UINT8) CpuTestCo= nfig->DebugInterfaceLockEnable; + FspsUpd->FspsTestConfig.ApIdleManner =3D PcdGet8 (PcdCpuAp= LoopMode); + FspsUpd->FspsTestConfig.ProcessorTraceOutputScheme =3D (UINT8) CpuTestCo= nfig->ProcessorTraceOutputScheme; + FspsUpd->FspsTestConfig.ProcessorTraceEnable =3D (UINT8) CpuTestCo= nfig->ProcessorTraceEnable; + FspsUpd->FspsTestConfig.ProcessorTraceMemBase =3D CpuTestConfig->Pr= ocessorTraceMemBase; + FspsUpd->FspsTestConfig.ProcessorTraceMemLength =3D (UINT32) CpuTestC= onfig->ProcessorTraceMemLength; + FspsUpd->FspsTestConfig.VoltageOptimization =3D (UINT8) CpuTestCo= nfig->VoltageOptimization; + FspsUpd->FspsTestConfig.ThreeStrikeCounterDisable =3D (UINT8) CpuTestCo= nfig->ThreeStrikeCounterDisable; + FspsUpd->FspsTestConfig.MachineCheckEnable =3D (UINT8) CpuTestCo= nfig->MachineCheckEnable; + FspsUpd->FspsTestConfig.CpuWakeUpTimer =3D (UINT8) CpuTestCo= nfig->CpuWakeUpTimer; + + FspsUpd->FspsTestConfig.OneCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->OneCoreRatioLimit; + FspsUpd->FspsTestConfig.TwoCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->TwoCoreRatioLimit; + FspsUpd->FspsTestConfig.ThreeCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->ThreeCoreRatioLimit; + FspsUpd->FspsTestConfig.FourCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->FourCoreRatioLimit; + FspsUpd->FspsTestConfig.FiveCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->FiveCoreRatioLimit; + FspsUpd->FspsTestConfig.SixCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->SixCoreRatioLimit; + FspsUpd->FspsTestConfig.SevenCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->SevenCoreRatioLimit; + FspsUpd->FspsTestConfig.EightCoreRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->EightCoreRatioLimit; + FspsUpd->FspsTestConfig.Hwp =3D (UINT8) CpuPowerM= gmtBasicConfig->Hwp; + FspsUpd->FspsTestConfig.HdcControl =3D (UINT8) CpuPowerM= gmtBasicConfig->HdcControl; + FspsUpd->FspsTestConfig.PowerLimit1Time =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit1Time; + FspsUpd->FspsTestConfig.PowerLimit2 =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit2; + FspsUpd->FspsTestConfig.TurboPowerLimitLock =3D (UINT8) CpuPowerM= gmtBasicConfig->TurboPowerLimitLock; + FspsUpd->FspsTestConfig.PowerLimit3Time =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit3Time; + FspsUpd->FspsTestConfig.PowerLimit3DutyCycle =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit3DutyCycle; + FspsUpd->FspsTestConfig.PowerLimit3Lock =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit3Lock; + FspsUpd->FspsTestConfig.PowerLimit4Lock =3D (UINT8) CpuPowerM= gmtBasicConfig->PowerLimit4Lock; + FspsUpd->FspsTestConfig.TccActivationOffset =3D (UINT8) CpuPowerM= gmtBasicConfig->TccActivationOffset; + FspsUpd->FspsTestConfig.TccOffsetClamp =3D (UINT8) CpuPowerM= gmtBasicConfig->TccOffsetClamp; + FspsUpd->FspsTestConfig.TccOffsetLock =3D (UINT8) CpuPowerM= gmtBasicConfig->TccOffsetLock; + FspsUpd->FspsTestConfig.PowerLimit1 =3D (UINT32) (CpuPowe= rMgmtBasicConfig->PowerLimit1 * 125); + FspsUpd->FspsTestConfig.PowerLimit2Power =3D (UINT32) (CpuPowe= rMgmtBasicConfig->PowerLimit2Power * 125); + FspsUpd->FspsTestConfig.PowerLimit3 =3D (UINT32) (CpuPowe= rMgmtBasicConfig->PowerLimit3 * 125); + FspsUpd->FspsTestConfig.PowerLimit4 =3D (UINT32) (CpuPowe= rMgmtBasicConfig->PowerLimit4 * 125); + FspsUpd->FspsTestConfig.TccOffsetTimeWindowForRatl =3D (UINT32) CpuPower= MgmtBasicConfig->TccOffsetTimeWindowForRatl; + FspsUpd->FspsTestConfig.HwpInterruptControl =3D (UINT8) CpuPowerM= gmtBasicConfig->HwpInterruptControl; + FspsUpd->FspsTestConfig.EnableItbm =3D (UINT8) CpuPowerM= gmtBasicConfig->EnableItbm; + FspsUpd->FspsTestConfig.EnableItbmDriver =3D (UINT8) CpuPowerM= gmtBasicConfig->EnableItbmDriver; + FspsUpd->FspsTestConfig.MinRingRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->MinRingRatioLimit; + FspsUpd->FspsTestConfig.MaxRingRatioLimit =3D (UINT8) CpuPowerM= gmtBasicConfig->MaxRingRatioLimit; + FspsUpd->FspsTestConfig.NumberOfEntries =3D (UINT8) CpuPower= MgmtCustomConfig->CustomRatioTable.NumberOfEntries; + FspsUpd->FspsTestConfig.Custom1PowerLimit1Time =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom2PowerLimit1Time =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom3PowerLimit1Time =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1Time; + FspsUpd->FspsTestConfig.Custom1TurboActivationRatio =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[0].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.Custom2TurboActivationRatio =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[1].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.Custom3TurboActivationRatio =3D (UINT8) CpuPower= MgmtCustomConfig->CustomConfigTdpTable[2].CustomTurboActivationRatio; + FspsUpd->FspsTestConfig.ConfigTdpLock =3D (UINT8) CpuPower= MgmtCustomConfig->ConfigTdpLock; + FspsUpd->FspsTestConfig.ConfigTdpBios =3D (UINT8) CpuPower= MgmtCustomConfig->ConfigTdpBios; + FspsUpd->FspsTestConfig.MaxRatio =3D (UINT8) CpuPower= MgmtCustomConfig->CustomRatioTable.MaxRatio; + for (Index =3D 0; Index < CpuPowerMgmtCustomConfig->CustomRatioTable.Num= berOfEntries; Index++) { + FspsUpd->FspsTestConfig.StateRatio[Index] =3D (UINT8) CpuPower= MgmtCustomConfig->CustomRatioTable.StateRatio[Index]; + } + for (Index =3D 0; Index < MAX_16_CUSTOM_RATIO_TABLE_ENTRIES; Index++) { + FspsUpd->FspsTestConfig.StateRatioMax16[Index] =3D (UINT8) CpuPower= MgmtCustomConfig->CustomRatioTable.StateRatioMax16[Index]; + } + FspsUpd->FspsTestConfig.Custom1PowerLimit1 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom1PowerLimit2 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[0].CustomPowerLimit2 * 125); + FspsUpd->FspsTestConfig.Custom2PowerLimit1 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom2PowerLimit2 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[1].CustomPowerLimit2 * 125); + FspsUpd->FspsTestConfig.Custom3PowerLimit1 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit1 * 125); + FspsUpd->FspsTestConfig.Custom3PowerLimit2 =3D (UINT32) (CpuPow= erMgmtCustomConfig->CustomConfigTdpTable[2].CustomPowerLimit2 * 125); + + FspsUpd->FspsTestConfig.Eist =3D (UINT8) CpuPow= erMgmtTestConfig->Eist; + FspsUpd->FspsTestConfig.EnergyEfficientPState =3D (UINT8) CpuPow= erMgmtTestConfig->EnergyEfficientPState; + FspsUpd->FspsTestConfig.EnergyEfficientTurbo =3D (UINT8) CpuPow= erMgmtTestConfig->EnergyEfficientTurbo; + FspsUpd->FspsTestConfig.TStates =3D (UINT8) CpuPow= erMgmtTestConfig->TStates; + FspsUpd->FspsTestConfig.BiProcHot =3D (UINT8) CpuPow= erMgmtTestConfig->BiProcHot; + FspsUpd->FspsTestConfig.DisableProcHotOut =3D (UINT8) CpuPow= erMgmtTestConfig->DisableProcHotOut; + FspsUpd->FspsTestConfig.ProcHotResponse =3D (UINT8) CpuPow= erMgmtTestConfig->ProcHotResponse; + FspsUpd->FspsTestConfig.DisableVrThermalAlert =3D (UINT8) CpuPow= erMgmtTestConfig->DisableVrThermalAlert; + FspsUpd->FspsTestConfig.AutoThermalReporting =3D (UINT8) CpuPow= erMgmtTestConfig->AutoThermalReporting; + FspsUpd->FspsTestConfig.ThermalMonitor =3D (UINT8) CpuPow= erMgmtTestConfig->ThermalMonitor; + FspsUpd->FspsTestConfig.Cx =3D (UINT8) CpuPow= erMgmtTestConfig->Cx; + FspsUpd->FspsTestConfig.PmgCstCfgCtrlLock =3D (UINT8) CpuPow= erMgmtTestConfig->PmgCstCfgCtrlLock; + FspsUpd->FspsTestConfig.C1e =3D (UINT8) CpuPow= erMgmtTestConfig->C1e; + FspsUpd->FspsTestConfig.C1StateAutoDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->C1AutoDemotion; + FspsUpd->FspsTestConfig.C1StateUnDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->C1UnDemotion; + FspsUpd->FspsTestConfig.C3StateAutoDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->C3AutoDemotion; + FspsUpd->FspsTestConfig.C3StateUnDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->C3UnDemotion; + FspsUpd->FspsTestConfig.CstateLatencyControl0TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl0TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl0Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl0Irtl; + FspsUpd->FspsTestConfig.PkgCStateDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->PkgCStateDemotion; + FspsUpd->FspsTestConfig.PkgCStateUnDemotion =3D (UINT8) CpuPow= erMgmtTestConfig->PkgCStateUnDemotion; + FspsUpd->FspsTestConfig.CStatePreWake =3D (UINT8) CpuPow= erMgmtTestConfig->CStatePreWake; + FspsUpd->FspsTestConfig.TimedMwait =3D (UINT8) CpuPow= erMgmtTestConfig->TimedMwait; + FspsUpd->FspsTestConfig.CstCfgCtrIoMwaitRedirection =3D (UINT8) CpuPow= erMgmtTestConfig->CstCfgCtrIoMwaitRedirection; + FspsUpd->FspsTestConfig.PkgCStateLimit =3D (UINT8) CpuPow= erMgmtTestConfig->PkgCStateLimit; + FspsUpd->FspsTestConfig.CstateLatencyControl1TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl1TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl2TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl2TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl3TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl3TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl4TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl4TimeUnit; + FspsUpd->FspsTestConfig.CstateLatencyControl5TimeUnit =3D (UINT8) CpuPow= erMgmtTestConfig->CstateLatencyControl5TimeUnit; + FspsUpd->FspsTestConfig.PpmIrmSetting =3D (UINT8) CpuPow= erMgmtTestConfig->PpmIrmSetting; + FspsUpd->FspsTestConfig.ProcHotLock =3D (UINT8) CpuPow= erMgmtTestConfig->ProcHotLock; + FspsUpd->FspsTestConfig.RaceToHalt =3D (UINT8) CpuPow= erMgmtTestConfig->RaceToHalt; + FspsUpd->FspsTestConfig.ConfigTdpLevel =3D (UINT8) CpuPow= erMgmtTestConfig->ConfigTdpLevel; + FspsUpd->FspsTestConfig.CstateLatencyControl1Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl1Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl2Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl2Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl3Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl3Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl4Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl4Irtl; + FspsUpd->FspsTestConfig.CstateLatencyControl5Irtl =3D (UINT16) CpuPo= werMgmtTestConfig->CstateLatencyControl5Irtl; + + // + // Get BIST information from Sec Platform Information + // + SecPlatformInformation2 =3D GetSecPlatformInformation2 (PeiServices); + if (SecPlatformInformation2 =3D=3D NULL) { + SecPlatformInformation2 =3D GetSecPlatformInformationInfoInFormat2 (Pe= iServices); + } + + ASSERT (SecPlatformInformation2 !=3D NULL); + + if (SecPlatformInformation2 !=3D NULL) { + FspsUpd->FspsConfig.CpuBistData =3D (UINT32)SecPlatformInformation2; + DEBUG((DEBUG_INFO, "SecPlatformInformation NumberOfCpus - %x\n", SecPl= atformInformation2->NumberOfCpus)); + DEBUG ((DEBUG_INFO, "SecPlatformInformation BIST - %x\n", SecPlatformI= nformation2->CpuInstance[0].InfoRecord.x64HealthFlags.Uint32)); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspMePolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c new file mode 100644 index 0000000000..97d9842aff --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspMePolicyInitLib.c @@ -0,0 +1,121 @@ +/** @file + Implementation of Fsp Me Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Performs FSP ME PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; + + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n")); + + // + // Locate gSiPreMemPolicyPpi + // + SiPreMemPolicy =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gMePeiPreMemConfigG= uid, (VOID *) &MePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + FspmUpd->FspmConfig.HeciTimeouts =3D (UINT8) MePei= PreMemConfig->HeciTimeouts; + // + // Test policies + // + FspmUpd->FspmTestConfig.DidInitStat =3D (UINT8) MePeiP= reMemConfig->DidInitStat; + FspmUpd->FspmTestConfig.DisableCpuReplacedPolling =3D (UINT8) MePeiP= reMemConfig->DisableCpuReplacedPolling; + FspmUpd->FspmTestConfig.SendDidMsg =3D (UINT8) MePeiP= reMemConfig->SendDidMsg; + FspmUpd->FspmTestConfig.DisableHeciRetry =3D (UINT8) MePeiP= reMemConfig->DisableHeciRetry; + FspmUpd->FspmTestConfig.DisableMessageCheck =3D (UINT8) MePeiP= reMemConfig->DisableMessageCheck; + FspmUpd->FspmTestConfig.SkipMbpHob =3D (UINT8) MePeiP= reMemConfig->SkipMbpHob; + + FspmUpd->FspmTestConfig.HeciCommunication2 =3D (UINT8) MePeiP= reMemConfig->HeciCommunication2; + FspmUpd->FspmTestConfig.KtDeviceEnable =3D (UINT8) MePeiP= reMemConfig->KtDeviceEnable; + + FspmUpd->FspmConfig.Heci1BarAddress =3D MePeiPreMemCon= fig->Heci1BarAddress; + FspmUpd->FspmConfig.Heci2BarAddress =3D MePeiPreMemCon= fig->Heci2BarAddress; + FspmUpd->FspmConfig.Heci3BarAddress =3D MePeiPreMemCon= fig->Heci3BarAddress; + + return EFI_SUCCESS; +} + +/** + Performs FSP ME PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspMePolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + ME_PEI_CONFIG *MePeiConfig; + + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n")); + // + // Locate gSiPolicyPpiGuid + // + SiPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI= D *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + + FspsUpd->FspsConfig.Heci3Enabled =3D (UINT8) MePeiConfi= g->Heci3Enabled; + FspsUpd->FspsConfig.MeUnconfigOnRtcClear =3D (UINT8) MePeiConfi= g->MeUnconfigOnRtcClear; + + // + // Test policies + // + FspsUpd->FspsTestConfig.MctpBroadcastCycle =3D (UINT8) MePeiConfi= g->MctpBroadcastCycle; + FspsUpd->FspsTestConfig.EndOfPostMessage =3D (UINT8) MePeiConfi= g->EndOfPostMessage; + FspsUpd->FspsTestConfig.DisableD0I3SettingForHeci =3D (UINT8) MePeiConfi= g->DisableD0I3SettingForHeci; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspMiscUpdInitLib.c b/Platform/Intel/WhiskeylakeOpenBoar= dPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c new file mode 100644 index 0000000000..9545e3df0b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspMiscUpdInitLib.c @@ -0,0 +1,77 @@ +/** @file + Implementation of Fsp Misc UPD Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#define STATUS_CODE_USE_RAM BIT0 +#define STATUS_CODE_USE_ISA_SERIAL BIT1 +#define STATUS_CODE_USE_USB BIT2 +#define STATUS_CODE_USE_USB3 BIT3 +#define STATUS_CODE_USE_SERIALIO BIT4 +#define STATUS_CODE_USE_TRACEHUB BIT5 +#define STATUS_CODE_CMOS_INVALID BIT6 +#define STATUS_CODE_CMOS_VALID BIT7 +/** + Performs FSP Misc UPD initialization. + + @param[in][out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + DEBUG_CONFIG_DATA_HOB *DebugConfigData; + UINT8 DebugInterfaces; + + FspmUpd->FspmArchUpd.StackBase =3D (VOID *)(UINTN)(PcdGet32(PcdTemporary= RamBase) + PcdGet32(PcdTemporaryRamSize) - (PcdGet32(PcdFspTemporaryRamSize= ) + PcdGet32(PcdFspReservedBufferSize))); + FspmUpd->FspmArchUpd.StackSize =3D PcdGet32(PcdFspTemporaryRamSize); + + Status =3D PeiServicesGetBootMode (&(FspmUpd->FspmArchUpd.BootMode)); + if (EFI_ERROR (Status)) { + FspmUpd->FspmArchUpd.BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + } + + FspmUpd->FspmArchUpd.BootLoaderTolumSize =3D 0x0; + + // + // Initialize DebugConfigData + // + DebugInterfaces =3D 0x00; + Hob.Guid =3D GetFirstGuidHob (&gDebugConfigHobGuid); + if (Hob.Guid !=3D NULL) { + DebugConfigData =3D (DEBUG_CONFIG_DATA_HOB *) GET_GUID_HOB_DATA (Hob.G= uid); + if (DebugConfigData !=3D NULL) { + // Debug Interfaces + if (DebugConfigData->RamDebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_RAM; } + if (DebugConfigData->UartDebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_ISA_SERIAL; } + if (DebugConfigData->Usb3DebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_USB3; } + if (DebugConfigData->SerialIoDebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_SERIALIO; } + if (DebugConfigData->TraceHubDebugInterface) { DebugInterfaces |=3D = STATUS_CODE_USE_TRACEHUB; } + FspmUpd->FspmConfig.PcdDebugInterfaceFlags =3D DebugInterfaces; + // Serial debug message baud rate + FspmUpd->FspmConfig.PcdSerialDebugBaudRate =3D DebugConfigData->Ser= ialDebugBaudRate; + //Serial debug message level + FspmUpd->FspmConfig.PcdSerialDebugLevel =3D DebugConfigData->Ser= ialDebug; + } + } + DEBUG ((DEBUG_INFO, "FspmConfig.PcdDebugInterfaceFlags is 0x%X\n", FspmU= pd->FspmConfig.PcdDebugInterfaceFlags)); + DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugBaudRate is 0x%X\= n", FspmUpd->FspmConfig.PcdSerialDebugBaudRate)); + DEBUG ((DEBUG_INFO, "FspmUpd->FspmConfig.PcdSerialDebugLevel is 0x%X\n",= FspmUpd->FspmConfig.PcdSerialDebugLevel)); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPchPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c new file mode 100644 index 0000000000..e2022929cd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPchPolicyInitLib.c @@ -0,0 +1,736 @@ +/** @file + Implementation of Fsp PCH Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN MaxPcieRootPorts; + SI_PREMEM_POLICY_PPI *SiPreMemPolicy; + PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig; + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; + PCH_HSIO_PCIE_PREMEM_CONFIG *HsioPciePreMemConfig; + PCH_HSIO_SATA_PREMEM_CONFIG *HsioSataPreMemConfig; + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + PCH_WDT_PREMEM_CONFIG *WdtPreMemConfig; + PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; + PCH_ISH_PREMEM_CONFIG *IshPreMemConfig; + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicyPreMem\n")); + DEBUG((DEBUG_INFO | DEBUG_INIT, "FspmUpd =3D 0x%x\n", FspmUpd)); + // + // Locate PchPreMemPolicyPpi + // + SiPreMemPolicy =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemC= onfigGuid, (VOID *) &PchTraceHubPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigG= uid, (VOID *) &SmbusPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGui= d, (VOID *) &DciPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioPciePreMemConf= igGuid, (VOID *) &HsioPciePreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHsioSataPreMemConf= igGuid, (VOID *) &HsioSataPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGui= d, (VOID *) &LpcPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemCo= nfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConf= igGuid, (VOID *) &WdtPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfig= Guid, (VOID *) &PcieRpPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfi= gGuid, (VOID *) &HdaPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGui= d, (VOID *) &IshPreMemConfig); + ASSERT_EFI_ERROR (Status); + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ UpdatePeiPchPolicyPreMem\n")); + // + // Update PCIE RP policies + // +// MaxPcieRootPorts =3D 16; + + MaxPcieRootPorts =3D GetPchMaxPciePortNum (); +// MaxPcieRootPorts =3D 16; + FspmUpd->FspmConfig.PcieRpEnableMask =3D PcieRpPreMemConfig->RpEnabledMa= sk & ((1 << MaxPcieRootPorts) - 1); + FspmUpd->FspmConfig.PcieImrEnabled =3D PcieRpPreMemConfig->PcieImrEnable= d; + FspmUpd->FspmConfig.PcieImrSize =3D PcieRpPreMemConfig->PcieImrSize; + FspmUpd->FspmConfig.ImrRpSelection =3D PcieRpPreMemConfig->ImrRpSelectio= n; + // + // Update TraceHub policies + // + FspmUpd->FspmConfig.PchTraceHubMode =3D (UINT8) PchTraceHubPreMemConfig-= >EnableMode; + FspmUpd->FspmConfig.PchTraceHubMemReg0Size =3D (UINT8) PchTraceHubPreMem= Config->MemReg0Size; + FspmUpd->FspmConfig.PchTraceHubMemReg1Size =3D (UINT8) PchTraceHubPreMem= Config->MemReg1Size; + + // + // Update Smbus policies + // + FspmUpd->FspmConfig.SmbusEnable =3D (UINT8)SmbusPreMemConfig->Enable; + FspmUpd->FspmConfig.SmbusArpEnable =3D (UINT8)SmbusPreMemConfig->ArpEnab= le; + FspmUpd->FspmTestConfig.SmbusDynamicPowerGating =3D (UINT8)SmbusPreMemCo= nfig->DynamicPowerGating; + FspmUpd->FspmTestConfig.SmbusSpdWriteDisable =3D (UINT8)SmbusPreMemConfi= g->SpdWriteDisable; + FspmUpd->FspmConfig.PchSmbAlertEnable =3D (UINT8)SmbusPreMemConfig->SmbA= lertEnable; + FspmUpd->FspmConfig.PchSmbusIoBase =3D (UINT16)SmbusPreMemConfig->SmbusI= oBase; + FspmUpd->FspmConfig.PchNumRsvdSmbusAddresses =3D (UINT8)SmbusPreMemConfi= g->NumRsvdSmbusAddresses; + FspmUpd->FspmConfig.RsvdSmbusAddressTablePtr =3D (UINT32)SmbusPreMemConf= ig->RsvdSmbusAddressTable; + + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ1 UpdatePeiPchPolicyPreMem\n")); + // + // Update Dci policies + // + FspmUpd->FspmConfig.PlatformDebugConsent =3D (UINT8)DciPreMemConfig->Pla= tformDebugConsent; + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ11 UpdatePeiPchPolicyPreMem\n")); + FspmUpd->FspmConfig.DciUsb3TypecUfpDbg =3D (UINT8)DciPreMemConfig->DciUs= b3TypecUfpDbg; + // + // Update HSIO PCIE policies + // + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { + FspmUpd->FspmConfig.PchPcieHsioRxSetCtleEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtleEnable; + FspmUpd->FspmConfig.PchPcieHsioRxSetCtle[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioRxSetCtle; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmpEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DownscaleAmp[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmpEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DownscaleAmp[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmpEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmpEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen3DownscaleAmp[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen3DownscaleAmp; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmphEnable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmphEnable; + FspmUpd->FspmConfig.PchPcieHsioTxGen1DeEmph[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen1DeEmph; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5Enable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5Enable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph3p5[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph3p5; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0Enable[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0Enable; + FspmUpd->FspmConfig.PchPcieHsioTxGen2DeEmph6p0[Index] =3D (U= INT8)HsioPciePreMemConfig->Lane[Index].HsioTxGen2DeEmph6p0; + } + + // + // Update HSIO SATA policies + // + for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index ++) { + FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMagEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen1EqBoostMag[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen1EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMagEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen2EqBoostMag[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen2EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMagEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMagEnable; + FspmUpd->FspmConfig.PchSataHsioRxGen3EqBoostMag[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioRxGen3EqBoostMag; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmpEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen1DownscaleAmp[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmpEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen2DownscaleAmp[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmpEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmpEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen3DownscaleAmp[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DownscaleAmp; + FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmphEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen1DeEmph[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen1DeEmph; + FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmphEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen2DeEmph[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen2DeEmph; + FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmphEnable[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmphEnable; + FspmUpd->FspmConfig.PchSataHsioTxGen3DeEmph[Index] =3D (U= INT8)HsioSataPreMemConfig->PortLane[Index].HsioTxGen3DeEmph; + } + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ2 UpdatePeiPchPolicyPreMem\n")); + // Update LPC policies + // + FspmUpd->FspmConfig.PchLpcEnhancePort8xhDecoding =3D (UINT8)LpcPreMemCon= fig->EnhancePort8xhDecoding; + + // + // Update Pch General Premem policies + // + FspmUpd->FspmConfig.PchPort80Route =3D (UINT8)PchGeneralPreMemConfig->Po= rt80Route; + + // + // Update Wdt policies + // + FspmUpd->FspmTestConfig.WdtDisableAndLock =3D (UINT8)WdtPreMemConfig->Di= sableAndLock; + + // + // HdAudioConfig + // + FspmUpd->FspmConfig.PchHdaEnable =3D (UINT8)HdaPreMemConfig->Enable; + + // + // IshConfig + // + FspmUpd->FspmConfig.PchIshEnable =3D (UINT8)IshPreMemConfig->Enable; + + DEBUG((DEBUG_INFO | DEBUG_INIT, "WYQ3 UpdatePeiPchPolicyPreMem\n")); + return EFI_SUCCESS; +} + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + UINTN Index; + UINTN MaxPcieRootPorts; + UINT8 Data8; + SI_POLICY_PPI *SiPolicy; + PCH_LAN_CONFIG *LanConfig; + PCH_HDAUDIO_CONFIG *HdAudioConfig; + PCH_SCS_CONFIG *ScsConfig; + PCH_ISH_CONFIG *IshConfig; + PCH_SATA_CONFIG *SataConfig; + USB_CONFIG *UsbConfig; + PCH_SERIAL_IO_CONFIG *SerialIoConfig; + PCH_INTERRUPT_CONFIG *InterruptConfig; + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + PCH_CNVI_CONFIG *CnviConfig; + PCH_HSIO_CONFIG *HsioConfig; + PCH_ESPI_CONFIG *EspiConfig; + PCH_PCIE_CONFIG *PcieRpConfig; + PCH_DMI_CONFIG *DmiConfig; + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_P2SB_CONFIG *P2sbConfig; + PCH_GENERAL_CONFIG *PchGeneralConfig; + PCH_PM_CONFIG *PmConfig; + PCH_LPC_SIRQ_CONFIG *PchSerialIrqConfig; + PCH_THERMAL_CONFIG *PchThermalConfig; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n")); + // + // Locate SiPolicyPpi + // + SiPolicy =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) = &LanConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID= *) &HdAudioConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) = &ScsConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) = &IshConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *)= &SataConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) = &UsbConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOI= D *) &SerialIoConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VO= ID *) &InterruptConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOI= D *) &LockDownConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID = *) &PcieRpConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) = &DmiConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGui= d, (VOID *) &FlashProtectionConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID = *) &IoApicConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gP2sbConfigGuid, (VOID *)= &P2sbConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (V= OID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &= PmConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VO= ID *) &PchSerialIrqConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID= *) &PchThermalConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *)= &CnviConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHsioConfigGuid, (VOID *)= &HsioConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *)= &EspiConfig); + ASSERT_EFI_ERROR (Status); + + // + // Update LAN policies + // + FspsUpd->FspsConfig.PchLanEnable =3D (UINT8)LanConfig->Enable; + FspsUpd->FspsConfig.PchLanLtrEnable =3D (UINT8)LanConfig->LtrEnabl= e; + + // + // Update HDA policies + // + FspsUpd->FspsConfig.PchHdaDspEnable =3D (UINT8)HdAudioConfig= ->DspEnable; + FspsUpd->FspsConfig.PchHdaPme =3D (UINT8)HdAudioConfig= ->Pme; + FspsUpd->FspsConfig.PchHdaVcType =3D (UINT8)HdAudioConfig= ->VcType; + FspsUpd->FspsConfig.PchHdaLinkFrequency =3D (UINT8)HdAudioConfig= ->HdAudioLinkFrequency; + FspsUpd->FspsConfig.PchHdaIDispLinkFrequency =3D (UINT8)HdAudioConfig= ->IDispLinkFrequency; + FspsUpd->FspsConfig.PchHdaIDispLinkTmode =3D (UINT8)HdAudioConfig= ->IDispLinkTmode; + FspsUpd->FspsConfig.PchHdaDspUaaCompliance =3D (UINT8)HdAudioConfig= ->DspUaaCompliance; + FspsUpd->FspsConfig.PchHdaIDispCodecDisconnect =3D (UINT8)HdAudioConfig= ->IDispCodecDisconnect; + FspsUpd->FspsConfig.PchHdaCodecSxWakeCapability =3D (UINT8)HdAudioConfig= ->CodecSxWakeCapability; + FspsUpd->FspsTestConfig.PchHdaResetWaitTimer =3D (UINT16)HdAudioConfi= g->ResetWaitTimer; + FspsUpd->FspsConfig.PchHdaVerbTableEntryNum =3D HdAudioConfig->VerbT= ableEntryNum; + FspsUpd->FspsConfig.PchHdaVerbTablePtr =3D HdAudioConfig->VerbT= ablePtr; + FspsUpd->FspsConfig.PchHdaAudioLinkHda =3D (UINT8)HdAudioConfig= ->AudioLinkHda; + FspsUpd->FspsConfig.PchHdaAudioLinkDmic0 =3D (UINT8)HdAudioConfig= ->AudioLinkDmic0; + FspsUpd->FspsConfig.PchHdaAudioLinkDmic1 =3D (UINT8)HdAudioConfig= ->AudioLinkDmic1; + FspsUpd->FspsConfig.PchHdaAudioLinkSsp0 =3D (UINT8)HdAudioConfig= ->AudioLinkSsp0; + FspsUpd->FspsConfig.PchHdaAudioLinkSsp1 =3D (UINT8)HdAudioConfig= ->AudioLinkSsp1; + FspsUpd->FspsConfig.PchHdaAudioLinkSsp2 =3D (UINT8)HdAudioConfig= ->AudioLinkSsp2; + FspsUpd->FspsConfig.PchHdaAudioLinkSndw1 =3D (UINT8)HdAudioConfig= ->AudioLinkSndw1; + FspsUpd->FspsConfig.PchHdaAudioLinkSndw2 =3D (UINT8)HdAudioConfig= ->AudioLinkSndw2; + FspsUpd->FspsConfig.PchHdaAudioLinkSndw3 =3D (UINT8)HdAudioConfig= ->AudioLinkSndw3; + FspsUpd->FspsConfig.PchHdaAudioLinkSndw4 =3D (UINT8)HdAudioConfig= ->AudioLinkSndw4; + FspsUpd->FspsConfig.PchHdaSndwBufferRcomp =3D (UINT8)HdAudioConfig= ->SndwBufferRcomp; + + // + // Update SCS policies + // + FspsUpd->FspsConfig.ScsEmmcEnabled =3D (UINT8)ScsConfig->ScsEmmcEnabled; + FspsUpd->FspsConfig.ScsEmmcHs400Enabled =3D (UINT8)ScsConfig->ScsEmmcHs4= 00Enabled; + FspsUpd->FspsConfig.ScsSdCardEnabled =3D (UINT8)ScsConfig->ScsSdcardEnab= led; + FspsUpd->FspsConfig.SdCardPowerEnableActiveHigh =3D (UINT8)ScsConfig->Sd= CardPowerEnableActiveHigh; +#ifdef CFL_SIMICS + FspsUpd->FspsConfig.ScsUfsEnabled =3D 0; +#else + FspsUpd->FspsConfig.ScsUfsEnabled =3D (UINT8)ScsConfig->ScsUfsEnabled; +#endif + FspsUpd->FspsConfig.PchScsEmmcHs400TuningRequired =3D (UINT8)ScsConfig->= ScsEmmcHs400TuningRequired; + FspsUpd->FspsConfig.PchScsEmmcHs400DllDataValid =3D (UINT8)ScsConfig->= ScsEmmcHs400DllDataValid; + FspsUpd->FspsConfig.PchScsEmmcHs400RxStrobeDll1 =3D (UINT8)ScsConfig->= ScsEmmcHs400RxStrobeDll1; + FspsUpd->FspsConfig.PchScsEmmcHs400TxDataDll =3D (UINT8)ScsConfig->= ScsEmmcHs400TxDataDll; + FspsUpd->FspsConfig.PchScsEmmcHs400DriverStrength =3D (UINT8)ScsConfig->= ScsEmmcHs400DriverStrength; + + // + // Update ISH policies + // + FspsUpd->FspsConfig.PchIshSpiGpioAssign =3D (UINT8)IshConfig->SpiGpioA= ssign; + FspsUpd->FspsConfig.PchIshUart0GpioAssign =3D (UINT8)IshConfig->Uart0Gpi= oAssign; + FspsUpd->FspsConfig.PchIshUart1GpioAssign =3D (UINT8)IshConfig->Uart1Gpi= oAssign; + FspsUpd->FspsConfig.PchIshI2c0GpioAssign =3D (UINT8)IshConfig->I2c0Gpio= Assign; + FspsUpd->FspsConfig.PchIshI2c1GpioAssign =3D (UINT8)IshConfig->I2c1Gpio= Assign; + FspsUpd->FspsConfig.PchIshI2c2GpioAssign =3D (UINT8)IshConfig->I2c2Gpio= Assign; + FspsUpd->FspsConfig.PchIshGp0GpioAssign =3D (UINT8)IshConfig->Gp0GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp1GpioAssign =3D (UINT8)IshConfig->Gp1GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp2GpioAssign =3D (UINT8)IshConfig->Gp2GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp3GpioAssign =3D (UINT8)IshConfig->Gp3GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp4GpioAssign =3D (UINT8)IshConfig->Gp4GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp5GpioAssign =3D (UINT8)IshConfig->Gp5GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp6GpioAssign =3D (UINT8)IshConfig->Gp6GpioA= ssign; + FspsUpd->FspsConfig.PchIshGp7GpioAssign =3D (UINT8)IshConfig->Gp7GpioA= ssign; + FspsUpd->FspsConfig.PchIshPdtUnlock =3D (UINT8)IshConfig->PdtUnloc= k; + + // + // Update PCIE RP RootPort policies + // + MaxPcieRootPorts =3D GetPchMaxPciePortNum (); + FspsUpd->FspsConfig.PcieRpDpcMask =3D 0; + FspsUpd->FspsConfig.PcieRpDpcExtensionsMask =3D 0; + FspsUpd->FspsConfig.PcieRpPtmMask =3D 0; + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { + FspsUpd->FspsConfig.PcieRpHotPlug[Index] =3D (UINT8)PcieRpConfig->Root= Port[Index].HotPlug; + FspsUpd->FspsConfig.PcieRpSlotImplemented[Index] =3D (UINT8)PcieRpConf= ig->RootPort[Index].SlotImplemented; + FspsUpd->FspsConfig.PcieRpPmSci[Index] =3D (UINT8)PcieRpConfig->RootPo= rt[Index].PmSci; + FspsUpd->FspsConfig.PcieRpExtSync[Index] =3D (UINT8)PcieRpConfig->Root= Port[Index].ExtSync; + FspsUpd->FspsConfig.PcieRpTransmitterHalfSwing[Index] =3D (UINT8)PcieR= pConfig->RootPort[Index].TransmitterHalfSwing; + FspsUpd->FspsConfig.PcieRpClkReqDetect[Index] =3D (UINT8)PcieRpConfig-= >RootPort[Index].ClkReqDetect; + FspsUpd->FspsConfig.PcieRpAdvancedErrorReporting[Index] =3D (UINT8)Pci= eRpConfig->RootPort[Index].AdvancedErrorReporting; + FspsUpd->FspsConfig.PcieRpUnsupportedRequestReport[Index] =3D (UINT8)P= cieRpConfig->RootPort[Index].UnsupportedRequestReport; + FspsUpd->FspsConfig.PcieRpFatalErrorReport[Index] =3D (UINT8)PcieRpCon= fig->RootPort[Index].FatalErrorReport; + FspsUpd->FspsConfig.PcieRpNoFatalErrorReport[Index] =3D (UINT8)PcieRpC= onfig->RootPort[Index].NoFatalErrorReport; + FspsUpd->FspsConfig.PcieRpCorrectableErrorReport[Index] =3D (UINT8)Pci= eRpConfig->RootPort[Index].CorrectableErrorReport; + FspsUpd->FspsConfig.PcieRpSystemErrorOnFatalError[Index] =3D (UINT8)Pc= ieRpConfig->RootPort[Index].SystemErrorOnFatalError; + FspsUpd->FspsConfig.PcieRpSystemErrorOnNonFatalError[Index] =3D (UINT8= )PcieRpConfig->RootPort[Index].SystemErrorOnNonFatalError; + FspsUpd->FspsConfig.PcieRpSystemErrorOnCorrectableError[Index] =3D (UI= NT8)PcieRpConfig->RootPort[Index].SystemErrorOnCorrectableError; + FspsUpd->FspsConfig.PcieRpMaxPayload[Index] =3D (UINT8)PcieRpConfig->R= ootPort[Index].MaxPayload; + if (PcieRpConfig->RootPort[Index].DpcEnabled) { + FspsUpd->FspsConfig.PcieRpDpcMask |=3D (BIT0<RootPort[Index].RpDpcExtensionsEnabled) { + FspsUpd->FspsConfig.PcieRpDpcExtensionsMask |=3D (BIT0<RootPort[Index].PtmEnabled) { + FspsUpd->FspsConfig.PcieRpPtmMask |=3D (BIT0<FspsConfig.PcieRpPcieSpeed[Index] =3D (UINT8)PcieRpConfig->Ro= otPort[Index].PcieSpeed; + FspsUpd->FspsConfig.PcieRpGen3EqPh3Method[Index] =3D (UINT8)PcieRpConf= ig->RootPort[Index].Gen3EqPh3Method; + FspsUpd->FspsConfig.PcieRpPhysicalSlotNumber[Index] =3D (UINT8)PcieRpC= onfig->RootPort[Index].PhysicalSlotNumber; + FspsUpd->FspsConfig.PcieRpCompletionTimeout[Index] =3D (UINT8)PcieRpCo= nfig->RootPort[Index].CompletionTimeout; + FspsUpd->FspsConfig.PcieRpAspm[Index] =3D (UINT8)PcieRpConfig->RootPor= t[Index].Aspm; + FspsUpd->FspsConfig.PcieRpL1Substates[Index] =3D (UINT8)PcieRpConfig->= RootPort[Index].L1Substates; + FspsUpd->FspsConfig.PcieRpLtrEnable[Index] =3D (UINT8)PcieRpConfig->Ro= otPort[Index].LtrEnable; + FspsUpd->FspsConfig.PcieRpLtrConfigLock[Index] =3D (UINT8)PcieRpConfig= ->RootPort[Index].LtrConfigLock; + FspsUpd->FspsConfig.PcieRpAcsEnabled[Index] =3D (UINT8)PcieRpConfig->R= ootPort[Index].AcsEnabled; + FspsUpd->FspsConfig.PcieRpDetectTimeoutMs[Index] =3D (UINT16)PcieRpCon= fig->RootPort[Index].DetectTimeoutMs; + FspsUpd->FspsConfig.PcieRootPortGen2PllL1CgDisable[Index] =3D (UINT8)P= cieRpConfig->RootPort[Index].PcieRootPortGen2PllL1CgDisable; + + FspsUpd->FspsTestConfig.PcieRpLtrMaxSnoopLatency[Index] =3D (UINT16)Pc= ieRpConfig->RootPort[Index].LtrMaxSnoopLatency; + FspsUpd->FspsTestConfig.PcieRpLtrMaxNoSnoopLatency[Index] =3D (UINT16)= PcieRpConfig->RootPort[Index].LtrMaxNoSnoopLatency; + + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMode[Index] =3D (UIN= T8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMode; + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideMultiplier[Index] = =3D (UINT8)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideMultiplier; + FspsUpd->FspsTestConfig.PcieRpSnoopLatencyOverrideValue[Index] =3D (UI= NT16)PcieRpConfig->RootPort[Index].SnoopLatencyOverrideValue; + + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMode[Index] =3D (= UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMode; + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideMultiplier[Index]= =3D (UINT8)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideMultiplier; + FspsUpd->FspsTestConfig.PcieRpNonSnoopLatencyOverrideValue[Index] =3D = (UINT16)PcieRpConfig->RootPort[Index].NonSnoopLatencyOverrideValue; + + FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitScale[Index] =3D (UINT8)Pc= ieRpConfig->RootPort[Index].SlotPowerLimitScale; + FspsUpd->FspsTestConfig.PcieRpSlotPowerLimitValue[Index] =3D (UINT16)P= cieRpConfig->RootPort[Index].SlotPowerLimitValue; + FspsUpd->FspsTestConfig.PcieRpUptp[Index] =3D (UINT8)PcieRpConfig->Roo= tPort[Index].Uptp; + FspsUpd->FspsTestConfig.PcieRpDptp[Index] =3D (UINT8)PcieRpConfig->Roo= tPort[Index].Dptp; + + } + for (Index =3D 0; Index < GetPchMaxPcieClockNum (); Index ++) { + FspsUpd->FspsConfig.PcieClkSrcUsage[Index] =3D PcieRpConfig->PcieClock= [Index].Usage; + FspsUpd->FspsConfig.PcieClkSrcClkReq[Index] =3D PcieRpConfig->PcieCloc= k[Index].ClkReq; + } + + // + // Update PCIE RP EqPh3LaneParam policies + // + for (Index =3D 0; Index < MaxPcieRootPorts; Index ++) { + FspsUpd->FspsConfig.PcieEqPh3LaneParamCm[Index] =3D (UINT8)PcieRpConfi= g->EqPh3LaneParam[Index].Cm; + FspsUpd->FspsConfig.PcieEqPh3LaneParamCp[Index] =3D (UINT8)PcieRpConfi= g->EqPh3LaneParam[Index].Cp; + } + + // + // Update PCIE RP SwEqCoeffList policies + // + for (Index =3D 0; Index < PCH_PCIE_SWEQ_COEFFS_MAX; Index ++) { + FspsUpd->FspsConfig.PcieSwEqCoeffListCm[Index] =3D (UINT8)PcieRpConfig= ->SwEqCoeffList[Index].Cm; + FspsUpd->FspsConfig.PcieSwEqCoeffListCp[Index] =3D (UINT8)PcieRpConfig= ->SwEqCoeffList[Index].Cp; + } + + // + // Update PCIE RP policies + // + FspsUpd->FspsTestConfig.PcieEnablePort8xhDecode =3D (UINT8)PcieRp= Config->EnablePort8xhDecode; + FspsUpd->FspsTestConfig.PchPciePort8xhDecodePortIndex =3D (UINT8)PcieRp= Config->PchPciePort8xhDecodePortIndex; + FspsUpd->FspsConfig.PcieDisableRootPortClockGating =3D (UINT8)PcieRpConf= ig->DisableRootPortClockGating; + FspsUpd->FspsConfig.PcieEnablePeerMemoryWrite =3D (UINT8)PcieRpConf= ig->EnablePeerMemoryWrite; + FspsUpd->FspsConfig.PcieComplianceTestMode =3D (UINT8)PcieRpConf= ig->ComplianceTestMode; + FspsUpd->FspsConfig.PcieRpFunctionSwap =3D (UINT8)PcieRpConf= ig->RpFunctionSwap; + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D PcieRpConfig->Pci= eDeviceOverrideTablePtr; + + // + // Update Sata Policies + // + FspsUpd->FspsConfig.SataEnable =3D (UINT8)SataConfig= ->Enable; + FspsUpd->FspsTestConfig.SataTestMode =3D (UINT8)SataConfig= ->TestMode; + FspsUpd->FspsConfig.SataSalpSupport =3D (UINT8)SataConfig= ->SalpSupport; + FspsUpd->FspsConfig.SataPwrOptEnable =3D (UINT8)SataConfig->PwrOptEnable; + FspsUpd->FspsConfig.EsataSpeedLimit =3D (UINT8)SataConfig->EsataSpeedLi= mit; + FspsUpd->FspsConfig.SataLedEnable =3D (UINT8)SataConfig->LedEnable; + FspsUpd->FspsConfig.SataMode =3D (UINT8)SataConfig->SataMode; + FspsUpd->FspsConfig.SataSpeedLimit =3D (UINT8)SataConfig->SpeedLimit; + + for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index++) { + FspsUpd->FspsConfig.SataPortsEnable[Index] =3D (UINT8)SataConfig->Port= Settings[Index].Enable; + FspsUpd->FspsConfig.SataPortsHotPlug[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].HotPlug; + FspsUpd->FspsConfig.SataPortsInterlockSw[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].InterlockSw; + FspsUpd->FspsConfig.SataPortsExternal[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].External; + FspsUpd->FspsConfig.SataPortsSpinUp[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].SpinUp; + FspsUpd->FspsConfig.SataPortsSolidStateDrive[Index] =3D (UINT8)SataCo= nfig->PortSettings[Index].SolidStateDrive; + FspsUpd->FspsConfig.SataPortsDevSlp[Index] =3D (UINT8)SataConfig->Port= Settings[Index].DevSlp; + FspsUpd->FspsConfig.SataPortsEnableDitoConfig[Index] =3D (UINT8)SataCo= nfig->PortSettings[Index].EnableDitoConfig; + FspsUpd->FspsConfig.SataPortsDmVal[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].DmVal; + FspsUpd->FspsConfig.SataPortsDitoVal[Index] =3D (UINT16)SataConfig= ->PortSettings[Index].DitoVal; + FspsUpd->FspsConfig.SataPortsZpOdd[Index] =3D (UINT8)SataConfig-= >PortSettings[Index].ZpOdd; + } + + FspsUpd->FspsConfig.SataRstRaidDeviceId =3D (UINT8)SataConfig= ->Rst.RaidDeviceId; + FspsUpd->FspsConfig.SataRstInterrupt =3D (UINT8)SataConfig= ->Rst.SataRstInterrupt; + FspsUpd->FspsConfig.SataRstRaid0 =3D (UINT8)SataConfig= ->Rst.Raid0; + FspsUpd->FspsConfig.SataRstRaid1 =3D (UINT8)SataConfig= ->Rst.Raid1; + FspsUpd->FspsConfig.SataRstRaid10 =3D (UINT8)SataConfig= ->Rst.Raid10; + FspsUpd->FspsConfig.SataRstRaid5 =3D (UINT8)SataConfig= ->Rst.Raid5; + FspsUpd->FspsConfig.SataRstIrrt =3D (UINT8)SataConfig= ->Rst.Irrt; + FspsUpd->FspsConfig.SataRstOromUiBanner =3D (UINT8)SataConfig= ->Rst.OromUiBanner; + FspsUpd->FspsConfig.SataRstOromUiDelay =3D (UINT8)SataConfig= ->Rst.OromUiDelay; + FspsUpd->FspsConfig.SataRstHddUnlock =3D (UINT8)SataConfig= ->Rst.HddUnlock; + FspsUpd->FspsConfig.SataRstLedLocate =3D (UINT8)SataConfig= ->Rst.LedLocate; + FspsUpd->FspsConfig.SataRstIrrtOnly =3D (UINT8)SataConfig= ->Rst.IrrtOnly; + FspsUpd->FspsConfig.SataRstSmartStorage =3D (UINT8)SataConfig= ->Rst.SmartStorage; + FspsUpd->FspsConfig.SataRstOptaneMemory =3D (UINT8)SataConfig= ->Rst.OptaneMemory; + FspsUpd->FspsConfig.SataRstLegacyOrom =3D (UINT8)SataConfig= ->Rst.LegacyOrom; + FspsUpd->FspsConfig.SataRstCpuAttachedStorage =3D (UINT8)SataConfig= ->Rst.CpuAttachedStorage; + + for (Index =3D 0; Index < PCH_MAX_RST_PCIE_STORAGE_CR; Index++) { + FspsUpd->FspsConfig.SataRstPcieEnable[Index] =3D (UINT8)Sata= Config->RstPcieStorageRemap[Index].Enable; + FspsUpd->FspsConfig.SataRstPcieStoragePort[Index] =3D (UINT8)Sata= Config->RstPcieStorageRemap[Index].RstPcieStoragePort; + FspsUpd->FspsConfig.SataRstPcieDeviceResetDelay[Index] =3D (UINT8)Sata= Config->RstPcieStorageRemap[Index].DeviceResetDelay; + } + + FspsUpd->FspsConfig.SataP0T1M =3D (UINT8)SataConfig->ThermalT= hrottling.P0T1M; + FspsUpd->FspsConfig.SataP0T2M =3D (UINT8)SataConfig->ThermalT= hrottling.P0T2M; + FspsUpd->FspsConfig.SataP0T3M =3D (UINT8)SataConfig->ThermalT= hrottling.P0T3M; + FspsUpd->FspsConfig.SataP0TDisp =3D (UINT8)SataConfig->ThermalT= hrottling.P0TDisp; + FspsUpd->FspsConfig.SataP1T1M =3D (UINT8)SataConfig->ThermalT= hrottling.P1T1M; + FspsUpd->FspsConfig.SataP1T2M =3D (UINT8)SataConfig->ThermalT= hrottling.P1T2M; + FspsUpd->FspsConfig.SataP1T3M =3D (UINT8)SataConfig->ThermalT= hrottling.P1T3M; + FspsUpd->FspsConfig.SataP1TDisp =3D (UINT8)SataConfig->ThermalT= hrottling.P1TDisp; + FspsUpd->FspsConfig.SataP0Tinact =3D (UINT8)SataConfig->ThermalT= hrottling.P0Tinact; + FspsUpd->FspsConfig.SataP0TDispFinit =3D (UINT8)SataConfig->ThermalT= hrottling.P0TDispFinit; + FspsUpd->FspsConfig.SataP1Tinact =3D (UINT8)SataConfig->ThermalT= hrottling.P1Tinact; + FspsUpd->FspsConfig.SataP1TDispFinit =3D (UINT8)SataConfig->ThermalT= hrottling.P1TDispFinit; + FspsUpd->FspsConfig.SataThermalSuggestedSetting =3D (UINT8)SataConfig->T= hermalThrottling.SuggestedSetting; + + // + // Update USB policies + // + FspsUpd->FspsConfig.PchEnableComplianceMode =3D (UINT8)UsbConf= ig->EnableComplianceMode; + FspsUpd->FspsConfig.UsbPdoProgramming =3D (UINT8)UsbConf= ig->PdoProgramming; + FspsUpd->FspsConfig.PchUsbOverCurrentEnable =3D (UINT8)UsbConf= ig->OverCurrentEnable; + FspsUpd->FspsConfig.PchUsb2PhySusPgEnable =3D (UINT8)UsbConf= ig->Usb2PhySusPgEnable; + FspsUpd->FspsTestConfig.PchXhciOcLock =3D (UINT8)UsbConf= ig->XhciOcLock; + for (Index =3D 0; Index < PCH_MAX_USB2_PORTS; Index++) { + FspsUpd->FspsConfig.PortUsb20Enable[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Enable; + FspsUpd->FspsConfig.Usb2OverCurrentPin[Index] =3D (UINT8)UsbConfig->Po= rtUsb20[Index].OverCurrentPin; + FspsUpd->FspsConfig.Usb2AfePetxiset[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Afe.Petxiset; + FspsUpd->FspsConfig.Usb2AfeTxiset[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Afe.Txiset; + FspsUpd->FspsConfig.Usb2AfePredeemp[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Afe.Predeemp; + FspsUpd->FspsConfig.Usb2AfePehalfbit[Index] =3D (UINT8)UsbConfig->Port= Usb20[Index].Afe.Pehalfbit; + } + for (Index =3D 0; Index < PCH_MAX_USB3_PORTS; Index++) { + FspsUpd->FspsConfig.PortUsb30Enable[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].Enable; + FspsUpd->FspsConfig.Usb3OverCurrentPin[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].OverCurrentPin; + FspsUpd->FspsConfig.Usb3HsioTxDeEmphEnable[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].HsioTxDeEmphEnable; + FspsUpd->FspsConfig.Usb3HsioTxDeEmph[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].HsioTxDeEmph; + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmpEnable[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].HsioTxDownscaleAmpEnable; + FspsUpd->FspsConfig.Usb3HsioTxDownscaleAmp[Index] =3D (UINT8)Usb= Config->PortUsb30[Index].HsioTxDownscaleAmp; + + Data8 =3D 0; + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfgEna= ble ? B_XHCI_HSIO_CTRL_ADAPT_OFFSET_CFG_EN : 0; + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelNEnable ? B_= XHCI_HSIO_FILTER_SELECT_N_EN : 0; + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelPEnable ? B_= XHCI_HSIO_FILTER_SELECT_P_EN : 0; + Data8 |=3D UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnResE= nable ? B_XHCI_HSIO_LFPS_CFG_PULLUP_DWN_RES_EN : 0; + FspsUpd->FspsConfig.PchUsbHsioRxTuningEnable[Index] =3D Data8; + + Data8 =3D ((UsbConfig->PortUsb30HsioRx[Index].HsioCtrlAdaptOffsetCfg &= 0x1F) << N_XHCI_UPD_HSIO_CTRL_ADAPT_OFFSET_CFG) | + ((UsbConfig->PortUsb30HsioRx[Index].HsioOlfpsCfgPullUpDwnRes &= 0x7) << N_XHCI_UPD_HSIO_LFPS_CFG_PULLUP_DWN_RES); + FspsUpd->FspsConfig.PchUsbHsioRxTuningParameters[Index] =3D Data8; + + Data8 =3D ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelN & 0x7) <<= N_XHCI_UPD_HSIO_FILTER_SELECT_N) | + ((UsbConfig->PortUsb30HsioRx[Index].HsioFilterSelP & 0x7) << N= _XHCI_UPD_HSIO_FILTER_SELECT_P); + FspsUpd->FspsConfig.PchUsbHsioFilterSel[Index] =3D Data8; + } + + FspsUpd->FspsConfig.XdciEnable =3D (UINT8)UsbConfig->XdciConfig.Enab= le; + + // + // Update SerialIo policies + // + for (Index =3D 0; Index < GetPchMaxSerialIoControllersNum (); Index++) { + FspsUpd->FspsConfig.SerialIoDevMode[Index] =3D SerialIoConfig->DevMode= [Index]; + } + for (Index =3D 0; Index < GetPchMaxSerialIoSpiControllersNum (); Index++= ) { + FspsUpd->FspsConfig.SerialIoSpiCsPolarity[Index] =3D SerialIoConfig->S= piCsPolarity[Index]; + } + for (Index =3D 0; Index < GetPchMaxSerialIoUartControllersNum (); Index+= +) { + FspsUpd->FspsConfig.SerialIoUartHwFlowCtrl[Index] =3D SerialIoConfig->= UartHwFlowCtrl[Index]; + } + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++= ) { + FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index] =3D SerialIoC= onfig->I2cPadsTermination[Index]; + } + + FspsUpd->FspsConfig.SerialIoDebugUartNumber =3D (UINT8)SerialIo= Config->DebugUartNumber; + FspsUpd->FspsConfig.SerialIoEnableDebugUartAfterPost =3D (UINT8)SerialIo= Config->EnableDebugUartAfterPost; + FspsUpd->FspsConfig.SerialIoUart0PinMuxing =3D (UINT8)SerialIo= Config->Uart0PinMuxing; + + // + // Update Interrupt policies + // + FspsUpd->FspsConfig.DevIntConfigPtr =3D (UINT32)InterruptConfig->DevIntC= onfig; + FspsUpd->FspsConfig.NumOfDevIntConfig =3D InterruptConfig->NumOfDevIntCo= nfig; + for (Index =3D 0; Index < PCH_MAX_PXRC_CONFIG; Index ++) { + FspsUpd->FspsConfig.PxRcConfig[Index] =3D (UINT8)InterruptConfig->PxRc= Config[Index]; + } + FspsUpd->FspsConfig.GpioIrqRoute =3D (UINT8)InterruptConfig->GpioIrqRout= e; + FspsUpd->FspsConfig.SciIrqSelect =3D (UINT8)InterruptConfig->SciIrqSelec= t; + FspsUpd->FspsConfig.TcoIrqSelect =3D (UINT8)InterruptConfig->TcoIrqSelec= t; + FspsUpd->FspsConfig.TcoIrqEnable =3D (UINT8)InterruptConfig->TcoIrqEnabl= e; + + // + // Update LockDown policies + // + FspsUpd->FspsTestConfig.PchLockDownGlobalSmi =3D (UINT8)LockDownConf= ig->GlobalSmi; + FspsUpd->FspsTestConfig.PchLockDownBiosInterface =3D (UINT8)LockDownConf= ig->BiosInterface; + FspsUpd->FspsConfig.PchLockDownBiosLock =3D (UINT8)LockDownConf= ig->BiosLock; + FspsUpd->FspsConfig.PchLockDownRtcMemoryLock =3D (UINT8)LockDownConf= ig->RtcMemoryLock; + FspsUpd->FspsTestConfig.PchUnlockGpioPads =3D (UINT8)LockDownConf= ig->UnlockGpioPads; + + // + // Update Dmi policies + // + FspsUpd->FspsConfig.PchPwrOptEnable =3D (UINT8)DmiConfig->PwrOptEnable; + FspsUpd->FspsConfig.PchDmiAspmCtrl =3D (UINT8)DmiConfig->DmiAspmCtrl; + + // + // Update Flash Protection policies + // + for (Index =3D 0; Index < PCH_FLASH_PROTECTED_RANGES; Index ++) { + FspsUpd->FspsConfig.PchWriteProtectionEnable[Index] =3D (UINT8)FlashPr= otectionConfig->ProtectRange[Index].WriteProtectionEnable; + FspsUpd->FspsConfig.PchReadProtectionEnable[Index] =3D (UINT8)FlashPr= otectionConfig->ProtectRange[Index].ReadProtectionEnable; + FspsUpd->FspsConfig.PchProtectedRangeLimit[Index] =3D (UINT16)FlashPr= otectionConfig->ProtectRange[Index].ProtectedRangeLimit; + FspsUpd->FspsConfig.PchProtectedRangeBase[Index] =3D (UINT16)FlashPr= otectionConfig->ProtectRange[Index].ProtectedRangeBase; + } + + // + // Update IO Apic policies + // + FspsUpd->FspsConfig.PchIoApicEntry24_119 =3D (UINT8)IoApicConfig->= IoApicEntry24_119; + FspsUpd->FspsConfig.Enable8254ClockGating =3D (UINT8)IoApicConfig->= Enable8254ClockGating; + FspsUpd->FspsConfig.Enable8254ClockGatingOnS3 =3D (UINT8)IoApicConfig->= Enable8254ClockGatingOnS3; + FspsUpd->FspsConfig.PchIoApicId =3D (UINT8)IoApicConfig->= IoApicId; + + // + // Update P2sb policies + // + FspsUpd->FspsTestConfig.PchSbAccessUnlock =3D (UINT8)P2sbConfig->SbAcce= ssUnlock; + + // + // Update Pch General policies + // + FspsUpd->FspsConfig.PchCrid =3D (UINT8)PchGeneralConfig->C= rid; + FspsUpd->FspsConfig.PchLegacyIoLowLatency =3D (UINT8)PchGeneralConfig->L= egacyIoLowLatency; + + // + // Update Pm policies + // + FspsUpd->FspsConfig.PchPmPmeB0S5Dis =3D (UINT8)PmConfig->WakeCon= fig.PmeB0S5Dis; + FspsUpd->FspsConfig.PchPmWolEnableOverride =3D (UINT8)PmConfig->WakeCon= fig.WolEnableOverride; + FspsUpd->FspsConfig.PchPmPcieWakeFromDeepSx =3D (UINT8)PmConfig->WakeCon= fig.PcieWakeFromDeepSx; + FspsUpd->FspsConfig.PchPmWoWlanEnable =3D (UINT8)PmConfig->WakeCon= fig.WoWlanEnable; + FspsUpd->FspsConfig.PchPmWoWlanDeepSxEnable =3D (UINT8)PmConfig->WakeCon= fig.WoWlanDeepSxEnable; + FspsUpd->FspsConfig.PchPmLanWakeFromDeepSx =3D (UINT8)PmConfig->WakeCon= fig.LanWakeFromDeepSx; + + FspsUpd->FspsConfig.PchPmDeepSxPol =3D (UINT8)PmConfig->PchDeep= SxPol; + FspsUpd->FspsConfig.PchPmSlpS3MinAssert =3D (UINT8)PmConfig->PchSlpS= 3MinAssert; + FspsUpd->FspsConfig.PchPmSlpS4MinAssert =3D (UINT8)PmConfig->PchSlpS= 4MinAssert; + FspsUpd->FspsConfig.PchPmSlpSusMinAssert =3D (UINT8)PmConfig->PchSlpS= usMinAssert; + FspsUpd->FspsConfig.PchPmSlpAMinAssert =3D (UINT8)PmConfig->PchSlpA= MinAssert; + FspsUpd->FspsConfig.PchPmLpcClockRun =3D (UINT8)PmConfig->LpcCloc= kRun; + FspsUpd->FspsConfig.PchPmSlpStrchSusUp =3D (UINT8)PmConfig->SlpStrc= hSusUp; + FspsUpd->FspsConfig.PchPmSlpLanLowDc =3D (UINT8)PmConfig->SlpLanL= owDc; + FspsUpd->FspsConfig.PchPmPwrBtnOverridePeriod =3D (UINT8)PmConfig->PwrBt= nOverridePeriod; + FspsUpd->FspsTestConfig.PchPmDisableEnergyReport =3D (UINT8)PmConfig->D= isableEnergyReport; + FspsUpd->FspsConfig.PchPmDisableDsxAcPresentPulldown =3D (UINT8)PmConfig= ->DisableDsxAcPresentPulldown; + FspsUpd->FspsConfig.PchPmDisableNativePowerButton =3D (UINT8)PmConfig= ->DisableNativePowerButton; + FspsUpd->FspsConfig.PmcPowerButtonDebounce =3D PmConfig->PowerButtonDeb= ounce; + FspsUpd->FspsConfig.PchPmSlpS0Enable =3D (UINT8)PmConfig->SlpS0En= able; + FspsUpd->FspsConfig.PchPmMeWakeSts =3D (UINT8)PmConfig->MeWakeS= ts; + FspsUpd->FspsConfig.PchPmWolOvrWkSts =3D (UINT8)PmConfig->WolOvrW= kSts; + FspsUpd->FspsConfig.EnableTcoTimer =3D (UINT8)PmConfig->EnableT= coTimer; + FspsUpd->FspsConfig.PchPmVrAlert =3D (UINT8)PmConfig->VrAlert; + FspsUpd->FspsConfig.PchPmPwrCycDur =3D (UINT8)PmConfig->PchPwrC= ycDur; + FspsUpd->FspsConfig.PchPmPciePllSsc =3D (UINT8)PmConfig->PciePll= Ssc; + FspsUpd->FspsConfig.PchPmSlpS0VmRuntimeControl =3D (UINT8)PmConfig->SlpS= 0VmRuntimeControl; + FspsUpd->FspsConfig.PchPmSlpS0Vm070VSupport =3D (UINT8)PmConfig->SlpS0= Vm070VSupport; + FspsUpd->FspsConfig.PchPmSlpS0Vm075VSupport =3D (UINT8)PmConfig->SlpS0= Vm075VSupport; + FspsUpd->FspsConfig.SlpS0Override =3D (UINT8)PmConfig->SlpS0= Override; + FspsUpd->FspsConfig.SlpS0DisQForDebug =3D (UINT8)PmConfig->SlpS0= DisQForDebug; + FspsUpd->FspsConfig.PmcDbgMsgEn =3D (UINT8)PmConfig->PmcDb= gMsgEn; + FspsUpd->FspsConfig.PsOnEnable =3D (UINT8)PmConfig->PsOnE= nable; + FspsUpd->FspsConfig.PmcCpuC10GatePinEnable =3D (UINT8)PmConfig->CpuC1= 0GatePinEnable; + FspsUpd->FspsConfig.PmcModPhySusPgEnable =3D (UINT8)PmConfig->ModPh= ySusPgEnable; + FspsUpd->FspsConfig.SlpS0WithGbeSupport =3D (UINT8)PmConfig->SlpS0= WithGbeSupport; + // + // Update Pch Serial IRQ policies + // + FspsUpd->FspsConfig.PchSirqEnable =3D (UINT8)PchSerialIrqConfig->S= irqEnable; + FspsUpd->FspsConfig.PchSirqMode =3D (UINT8)PchSerialIrqConfig->S= irqMode; + FspsUpd->FspsConfig.PchStartFramePulse =3D (UINT8)PchSerialIrqConfig->S= tartFramePulse; + // + // Update Pch Thermal policies + // + FspsUpd->FspsConfig.PchTsmicLock =3D (UINT8)PchThermalConfig->Tsm= icLock; + FspsUpd->FspsConfig.PchHotEnable =3D (UINT8)PchThermalConfig->Pch= HotEnable; + + FspsUpd->FspsConfig.PchT0Level =3D (UINT16)PchThermalConfig->TT= Levels.T0Level; + FspsUpd->FspsConfig.PchT1Level =3D (UINT16)PchThermalConfig->TT= Levels.T1Level; + FspsUpd->FspsConfig.PchT2Level =3D (UINT16)PchThermalConfig->TT= Levels.T2Level; + FspsUpd->FspsConfig.PchTTEnable =3D (UINT8)PchThermalConfig->TTL= evels.TTEnable; + FspsUpd->FspsConfig.PchTTState13Enable =3D (UINT8)PchThermalConfig->TTL= evels.TTState13Enable; + FspsUpd->FspsConfig.PchTTLock =3D (UINT8)PchThermalConfig->TTL= evels.TTLock; + FspsUpd->FspsConfig.TTSuggestedSetting =3D (UINT8)PchThermalConfig->TTL= evels.SuggestedSetting; + FspsUpd->FspsConfig.TTCrossThrottling =3D (UINT8)PchThermalConfig->TTL= evels.PchCrossThrottling; + + FspsUpd->FspsConfig.PchDmiTsawEn =3D (UINT8)PchThermalConfig->Dmi= HaAWC.DmiTsawEn; + FspsUpd->FspsConfig.DmiSuggestedSetting =3D (UINT8)PchThermalConfig->Dmi= HaAWC.SuggestedSetting; + FspsUpd->FspsConfig.DmiTS0TW =3D (UINT8)PchThermalConfig->Dmi= HaAWC.TS0TW; + FspsUpd->FspsConfig.DmiTS1TW =3D (UINT8)PchThermalConfig->Dmi= HaAWC.TS1TW; + FspsUpd->FspsConfig.DmiTS2TW =3D (UINT8)PchThermalConfig->Dmi= HaAWC.TS2TW; + FspsUpd->FspsConfig.DmiTS3TW =3D (UINT8)PchThermalConfig->Dmi= HaAWC.TS3TW; + + FspsUpd->FspsConfig.PchMemoryThrottlingEnable =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.Enable; + FspsUpd->FspsConfig.PchMemoryPmsyncEnable[0] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[0].PmsyncEnable; + FspsUpd->FspsConfig.PchMemoryPmsyncEnable[1] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[1].PmsyncEnable; + FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[0] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[0].C0TransmitEnable; + FspsUpd->FspsConfig.PchMemoryC0TransmitEnable[1] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[1].C0TransmitEnable; + FspsUpd->FspsConfig.PchMemoryPinSelection[0] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[0].PinSelection; + FspsUpd->FspsConfig.PchMemoryPinSelection[1] =3D (UINT8)PchThermalCo= nfig->MemoryThrottling.TsGpioPinSetting[1].PinSelection; + + FspsUpd->FspsConfig.PchTemperatureHotLevel =3D (UINT16)PchThermalConfig-= >PchHotLevel; + + // + // Update Pch CNVi policies + // + FspsUpd->FspsConfig.PchCnviMode =3D (UINT8)CnviConfig->Mode; + FspsUpd->FspsConfig.PchCnviMfUart1Type =3D (UINT8)CnviConfig->MfUart1Typ= e; + + // + // Update Pch HSIO policies + // + FspsUpd->FspsConfig.ChipsetInitBinPtr =3D HsioConfig->ChipsetInitBinPtr; + FspsUpd->FspsConfig.ChipsetInitBinLen =3D HsioConfig->ChipsetInitBinLen; + + // + // Update Pch Espi policies + // + FspsUpd->FspsConfig.PchEspiLgmrEnable =3D (UINT8)EspiConfig->LgmrEnable; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c new file mode 100644 index 0000000000..ce34325781 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspPolicyInitLib.c @@ -0,0 +1,223 @@ +/** @file + Instance of Fsp Policy Initialization Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +VOID +EFIAPI +FspPolicyInitPreMem( + IN FSPM_UPD *FspmUpdDataPtr +); + +VOID * +EFIAPI +SiliconPolicyInitPreMem( + IN OUT VOID *FspmUpd +) +{ + FspPolicyInitPreMem((FSPM_UPD *)FspmUpd); + return FspmUpd; +} + +RETURN_STATUS +EFIAPI +SiliconPolicyDonePreMem( + IN VOID *FspmUpd +) +{ + EFI_STATUS Status; + + Status =3D SpiServiceInit(); + ASSERT_EFI_ERROR(Status); + + return RETURN_SUCCESS; +} + +/** + Performs FSP PEI Policy Pre-memory initialization. + + @param[in] FspmUpdDataPtr Pointer to FSPM UPD data. +**/ +VOID +EFIAPI +FspPolicyInitPreMem ( + IN FSPM_UPD *FspmUpdDataPtr + ) +{ + EFI_STATUS Status; + + // + // SI Pei Fsp Policy Initialization + // + Status =3D PeiFspSiPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy in Pre-Memory Initiali= zation fail, Status =3D %r\n", Status)); + } + + // + // PCH Pei Fsp Policy Initialization + // + Status =3D PeiFspPchPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initial= ization fail, Status =3D %r\n", Status)); + } + + // + // Cpu Pei Fsp Policy Initialization + // + Status =3D PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initial= ization fail, Status =3D %r\n", Status)); + } + + // + // Security Pei Fsp Policy Initialization + // + Status =3D PeiFspSecurityPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy in Pre-Memory In= itialization fail, Status =3D %r\n", Status)); + } + + // + // ME Pei Fsp Policy Initialization + // + Status =3D PeiFspMePolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy in Pre-Memory Initiali= zation fail, Status =3D %r\n", Status)); + } + + // + // SystemAgent Pei Fsp Policy Initialization + // + Status =3D PeiFspSaPolicyInitPreMem (FspmUpdDataPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory= Initialization fail, Status =3D %r\n", Status)); + } + + // + // Other Upd Initialization + // + Status =3D PeiFspMiscUpdInitPreMem (FspmUpdDataPtr); + +} + +/** + Performs FSP PEI Policy initialization. + + @param[in][out] FspsUpd Pointer UPD data region + +**/ +VOID +EFIAPI +FspPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + + // + // SI Pei Fsp Policy Initialization + // + Status =3D PeiFspSiPolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - SI Pei Fsp Policy iInitialization fail, = Status =3D %r\n", Status)); + } + + // + // PCH Pei Fsp Policy Initialization + // + Status =3D PeiFspPchPolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy iInitialization fail,= Status =3D %r\n", Status)); + } + + // + // ME Pei Fsp Policy Initialization + // + Status =3D PeiFspMePolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy Initialization fail, S= tatus =3D %r\n", Status)); + } + + // + // SystemAgent Pei Fsp Policy Initialization + // + Status =3D PeiFspSaPolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy Initializatio= n fail, Status =3D %r\n", Status)); + } + + // + // Cpu Pei Fsp Policy Initialization + // + Status =3D PeiFspCpuPolicyInit (FspsUpd); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy Initialization fail, = Status =3D %r\n", Status)); + } + + // + // Security Pei Fsp Policy Initialization + // + Status =3D PeiFspSecurityPolicyInit(FspsUpd); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy Initialization fa= il, Status =3D %r\n", Status)); + } + +} + +/** +Performs silicon post-mem policy initialization. + +The meaning of Policy is defined by silicon code. +It could be the raw data, a handle, a PPI, etc. + +The returned data must be used as input data for SiliconPolicyDonePostMem(= ), +and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem(). + +1) In FSP path, the input Policy should be FspsUpd. +Value of FspsUpd has been initialized by FSP binary default value. +Only a subset of FspsUpd needs to be updated for different silicon sku. +The return data is same FspsUpd. + +2) In non-FSP path, the input policy could be NULL. +The return data is the initialized policy. + +@param[in, out] Policy Pointer to policy. + +@return the initialized policy. +**/ +VOID * +EFIAPI +SiliconPolicyInitPostMem( + IN OUT VOID *FspsUpd +) +{ + FspPolicyInit((FSPS_UPD *)FspsUpd); + return FspsUpd; +} + +/* +The silicon post-mem policy is finalized. +Silicon code can do initialization based upon the policy data. + +The input Policy must be returned by SiliconPolicyInitPostMem(). + +@param[in] Policy Pointer to policy. + +@retval EFI_SUCCESS The policy is handled consumed by silicon code. +*/ +EFI_STATUS +EFIAPI +SiliconPolicyDonePostMem( + IN OUT VOID *FspsUpd +) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspSaPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c new file mode 100644 index 0000000000..0bfc379386 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspSaPolicyInitLib.c @@ -0,0 +1,848 @@ +/** @file + Implementation of Fsp SA Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#define MAX_SPD_PAGE_COUNT (2) +#define MAX_SPD_PAGE_SIZE (256) +#define MAX_SPD_SIZE (MAX_SPD_PAGE_SIZE * MAX_SPD_PAGE_COU= NT) +#define SPD_PAGE_ADDRESS_0 (0x6C) +#define SPD_PAGE_ADDRESS_1 (0x6E) +#define SPD_DDR3_SDRAM_TYPE_OFFSET (0x02) +#define SPD_DDR3_SDRAM_TYPE_NUMBER (0x0B) +#define SPD_DDR4_SDRAM_TYPE_NUMBER (0x0C) +#define SPD_LPDDR3_SDRAM_TYPE_NUMBER (0xF1) +#define SPD_JEDEC_LPDDR3_SDRAM_TYPE_NUMBER (0x0F) +#define XMP_ID_STRING (0x4A0C) +#define SPD3_MANUF_START (117) +#define SPD3_MANUF_END (127) +#define SPD4_MANUF_START (320) +#define SPD4_MANUF_END (328) +#define SPDLP_MANUF_START (320) +#define SPDLP_MANUF_END (328) + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr3Table[] =3D { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 41, (1 << SpdCold),}, + { 60, 63, (1 << SpdCold),}, + { SPD3_MANUF_START, SPD3_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 128, 145, (1 << SpdCold),}, + { 39, 59, (1 << SpdCold),}, + { 64, 125, (1 << SpdCold),}, + { 176, 179, (1 << SpdCold),}, + { 180, 184, (1 << SpdCold),}, + { 185, 215, (1 << SpdCold),}, + { 220, 250, (1 << SpdCold),}, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdDdr4Table[] =3D { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 40, (1 << SpdCold),}, + { 117, 131, (1 << SpdCold),}, + { SPD4_MANUF_START, SPD4_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 329, 348, (1 << SpdCold),}, + { 32, 119, (1 << SpdCold),}, + { 126, 255, (1 << SpdCold),}, + { 349, 383, (1 << SpdCold),}, + { 384, 387, (1 << SpdCold),}, + { 388, 389, (1 << SpdCold),}, + { 393, 431, (1 << SpdCold),}, + { 440, 478, (1 << SpdCold),}, +}; + +GLOBAL_REMOVE_IF_UNREFERENCED const SPD_OFFSET_TABLE mSpdLpddrTable[] =3D { + { 0, 1, (1 << SpdCold),}, + { 2, 2, (1 << SpdCold) | (1 << SpdFast),}, + { 3, 32, (1 << SpdCold),}, + { 120, 130, (1 << SpdCold),}, + { SPDLP_MANUF_START, SPDLP_MANUF_END, (1 << SpdCold) | (1 << SpdFast),}, + { 329, 348, (1 << SpdCold),}, + { 31, 121, (1 << SpdCold),}, + { 126, 255, (1 << SpdCold),}, + { 349, 383, (1 << SpdCold),}, + { 384, 387, (1 << SpdCold),}, + { 388, 389, (1 << SpdCold),}, + { 393, 431, (1 << SpdCold),}, + { 440, 478, (1 << SpdCold),}, +}; + + +/** + Update Spd Data + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + @param[in] MemConfigNoCrc Pointer to Mem Config No Crc. + @param[in] MiscPeiPreMemConfig Pointer to Misc Config. + + @retval EFI_SUCCESS The function completes successfully + @retval Other The function fail +**/ +VOID +EFIAPI +InternalUpdateSpdInfo ( + IN OUT FSPM_UPD *FspmUpd, + IN MEMORY_CONFIG_NO_CRC *MemConfigNoCrc, + IN SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig + ) +{ + + DEBUG ((DEBUG_INFO, "Updating UPD:Memory Spd Pointers...\n")); + if ((FspmUpd =3D=3D NULL) || (MemConfigNoCrc =3D=3D NULL) || (MiscPeiPre= MemConfig =3D=3D NULL)) { + DEBUG ((DEBUG_ERROR, "EFI_INVALID_PARAMETER.\n")); + DEBUG ((DEBUG_ERROR, "Fail to access SPD from SiPolicyPpi\n")); + return; + } + + // + // Update MemorySpdPtrXX if SpdAddressTable is zero + // + if (MiscPeiPreMemConfig->SpdAddressTable[0] =3D=3D 0x0) { + FspmUpd->FspmConfig.MemorySpdPtr00 =3D (UINT32)MemConfigNoCrc->SpdData= ->SpdData; + } else { + FspmUpd->FspmConfig.SpdAddressTable[0] =3D MiscPeiPreMemConfig->SpdAdd= ressTable[0]; + } + + if (MiscPeiPreMemConfig->SpdAddressTable[1] =3D=3D 0x0) { + FspmUpd->FspmConfig.MemorySpdPtr01 =3D (UINT32)MemConfigNoCrc->SpdData= ->SpdData + (1 * SA_MC_MAX_SPD_SIZE); + } else { + FspmUpd->FspmConfig.SpdAddressTable[1] =3D MiscPeiPreMemConfig->SpdAdd= ressTable[1]; + } + + if (MiscPeiPreMemConfig->SpdAddressTable[2] =3D=3D 0x0) { + FspmUpd->FspmConfig.MemorySpdPtr10 =3D (UINT32)MemConfigNoCrc->SpdData= ->SpdData + (2 * SA_MC_MAX_SPD_SIZE); + } else { + FspmUpd->FspmConfig.SpdAddressTable[2] =3D MiscPeiPreMemConfig->SpdAdd= ressTable[2]; + } + + if (MiscPeiPreMemConfig->SpdAddressTable[3] =3D=3D 0x0) { + FspmUpd->FspmConfig.MemorySpdPtr11 =3D (UINT32)MemConfigNoCrc->SpdData= ->SpdData + (3 * SA_MC_MAX_SPD_SIZE); + } else { + FspmUpd->FspmConfig.SpdAddressTable[3] =3D MiscPeiPreMemConfig->SpdAdd= ressTable[3]; + } + + DEBUG ((DEBUG_INFO, "UPD:MemorySpdPtr Updated\n")); +} + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ) +{ + EFI_STATUS Status; + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; + EFI_FV_FILE_INFO FvFileInfo; + PEI_CORE_INSTANCE *PrivateData; + UINTN CurrentFv; + PEI_CORE_FV_HANDLE *CoreFvHandle; + EFI_PEI_FILE_HANDLE VbtFileHandle; + EFI_GUID *VbtGuid; + EFI_COMMON_SECTION_HEADER *Section; + CONST EFI_PEI_SERVICES **PeiServices; + + PeiServices =3D GetPeiServicesTablePointer (); + + PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices); + + Status =3D PeiServicesLocatePpi ( + &gEfiFirmwareFileSystem2Guid, + 0, + NULL, + (VOID **) &FvPpi + ); + ASSERT_EFI_ERROR (Status); + + CurrentFv =3D PrivateData->CurrentPeimFvCount; + CoreFvHandle =3D &(PrivateData->Fv[CurrentFv]); + + Status =3D FvPpi->FindFileByName (FvPpi, &NameGuid, &CoreFvHandle->FvHan= dle, &VbtFileHandle); + if (!EFI_ERROR(Status) && VbtFileHandle !=3D NULL) { + + DEBUG ((DEBUG_INFO, "Find SectionByType \n")); + + Status =3D FvPpi->FindSectionByType (FvPpi, EFI_SECTION_RAW, VbtFileHa= ndle, (VOID **) &VbtGuid); + if (!EFI_ERROR (Status)) { + + DEBUG ((DEBUG_INFO, "GetFileInfo \n")); + + Status =3D FvPpi->GetFileInfo (FvPpi, VbtFileHandle, &FvFileInfo); + Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer; + + if (IS_SECTION2 (Section)) { + ASSERT (SECTION2_SIZE (Section) > 0x00FFFFFF); + *Size =3D SECTION2_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEA= DER2); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER= 2)); + } else { + *Size =3D SECTION_SIZE (Section) - sizeof (EFI_COMMON_SECTION_HEAD= ER); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER= )); + } + } + } + + return EFI_SUCCESS; +} + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + MEMORY_CONFIGURATION *MemConfig; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig; + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData; + GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig; + OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig; + VTD_CONFIG *Vtd; + IPU_PREMEM_CONFIG *IpuPreMemPolicy; + UINT8 Index; + VOID *Buffer; + + SiPreMemPolicyPpi =3D NULL; + MiscPeiPreMemConfig =3D NULL; + MemConfig =3D NULL; + MemConfigNoCrc =3D NULL; + PciePeiPreMemConfig =3D NULL; + SgGpioData =3D NULL; + GtPreMemConfig =3D NULL; + OcPreMemConfig =3D NULL; + Vtd =3D NULL; + IpuPreMemPolicy =3D NULL; + + + + // + // Locate SiPreMemPolicyPpi + // + Status =3D PeiServicesLocatePpi( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + if ((Status =3D=3D EFI_SUCCESS) && (SiPreMemPolicyPpi !=3D NULL)) { + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreM= emConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigN= oCrcGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigG= uid, (VOID *) &MemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPr= eMemConfigGuid, (VOID *) &GtPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreM= emConfigGuid, (VOID *) &PciePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSwitchableGra= phicsConfigGuid, (VOID *) &SgGpioData); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid= , (VOID *) &Vtd); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConf= igGuid, (VOID *) &IpuPreMemPolicy); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaOverclockin= gPreMemConfigGuid, (VOID *) &OcPreMemConfig); + ASSERT_EFI_ERROR (Status); + + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings= ...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 1= 2, 12); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffe= r + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp = Target Settings...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); + } + + // + // Update UPD:MemorySpdPtrXX and SpdAddressTable + // + InternalUpdateSpdInfo (FspmUpd, MemConfigNoCrc, MiscPeiPreMemConfig); + + // + // Update UPD:MemorySpdDataLen + // + FspmUpd->FspmConfig.MemorySpdDataLen =3D SA_MC_MAX_SPD_SIZE; + + if (MemConfigNoCrc !=3D NULL) { + // + // Update UPD:PlatformMemorySize + // + // + // @todo: This value is used since #183932. Revisit. + // + FspmUpd->FspmConfig.PlatformMemorySize =3D MemConfigNoCrc->PlatformMe= morySize; + FspmUpd->FspmConfig.CleanMemory =3D (UINT8) MemConfigNoCrc->Cl= eanMemory; + FspmUpd->FspmConfig.MemTestOnWarmBoot =3D (UINT8) MemConfigNoCrc->Me= mTestOnWarmBoot; + } + + if (MemConfig !=3D NULL) { + // + // Update UPD:DqPinsInterleaved + // + FspmUpd->FspmConfig.DqPinsInterleaved =3D (UINT8) MemConfig->DqPin= sInterleaved; + + FspmUpd->FspmConfig.ProbelessTrace =3D MemConfig->ProbelessTrac= e; + FspmUpd->FspmConfig.GdxcIotSize =3D MemConfig->GdxcIotSize; + FspmUpd->FspmConfig.GdxcMotSize =3D MemConfig->GdxcMotSize; + FspmUpd->FspmConfig.DualDimmPerChannelBoardType =3D(UINT8) MemConfig->= DualDimmPerChannelBoardType; + FspmUpd->FspmConfig.Ddr4MixedUDimm2DpcLimit =3D(UINT8) MemConfig->= Ddr4MixedUDimm2DpcLimit; + // + // Update UPD:CaVrefConfig + // + FspmUpd->FspmConfig.CaVrefConfig =3D MemConfig->CaVrefConfig; + FspmUpd->FspmConfig.SaGv =3D MemConfig->SaGv; + FspmUpd->FspmConfig.FreqSaGvLow =3D MemConfig->FreqSaGvLow; + FspmUpd->FspmConfig.FreqSaGvMid =3D MemConfig->FreqSaGvMid; + FspmUpd->FspmConfig.RMT =3D (UINT8) MemConfig->RMT; + FspmUpd->FspmConfig.DdrFreqLimit =3D MemConfig->DdrFreqLimit; + + FspmUpd->FspmConfig.SpdProfileSelected =3D MemConfig->SpdProfileSel= ected; + FspmUpd->FspmConfig.VddVoltage =3D MemConfig->VddVoltage; + FspmUpd->FspmConfig.RefClk =3D MemConfig->RefClk; + FspmUpd->FspmConfig.Ratio =3D MemConfig->Ratio; + FspmUpd->FspmConfig.OddRatioMode =3D (UINT8) MemConfig->OddRa= tioMode; + FspmUpd->FspmConfig.tCL =3D (UINT8) MemConfig->tCL; + FspmUpd->FspmConfig.tCWL =3D (UINT8) MemConfig->tCWL; + FspmUpd->FspmConfig.tFAW =3D MemConfig->tFAW; + FspmUpd->FspmConfig.tRAS =3D MemConfig->tRAS; + FspmUpd->FspmConfig.tRCDtRP =3D (UINT8) MemConfig->tRCDt= RP; + FspmUpd->FspmConfig.tREFI =3D MemConfig->tREFI; + FspmUpd->FspmConfig.tRFC =3D MemConfig->tRFC; + FspmUpd->FspmConfig.tRRD =3D (UINT8) MemConfig->tRRD; + FspmUpd->FspmConfig.tRTP =3D (UINT8) MemConfig->tRTP; + FspmUpd->FspmConfig.tWR =3D (UINT8) MemConfig->tWR; + FspmUpd->FspmConfig.tWTR =3D (UINT8) MemConfig->tWTR; + FspmUpd->FspmConfig.NModeSupport =3D MemConfig->NModeSupport; + FspmUpd->FspmConfig.DllBwEn0 =3D MemConfig->DllBwEn0; + FspmUpd->FspmConfig.DllBwEn1 =3D MemConfig->DllBwEn1; + FspmUpd->FspmConfig.DllBwEn2 =3D MemConfig->DllBwEn2; + FspmUpd->FspmConfig.DllBwEn3 =3D MemConfig->DllBwEn3; + FspmUpd->FspmConfig.MrcSafeConfig =3D (UINT8) MemConfig->MrcSa= feConfig; // Typecasting as MrcSafeConfig is of UINT32 in MEMORY_CONFIGURAT= ION + FspmUpd->FspmConfig.LpDdrDqDqsReTraining =3D (UINT8) MemConfig->Lp4Dq= sOscEn; + FspmUpd->FspmConfig.RmtPerTask =3D (UINT8) MemConfig->RmtPe= rTask; + FspmUpd->FspmConfig.TrainTrace =3D (UINT8) MemConfig->Train= Trace; + FspmUpd->FspmConfig.ScramblerSupport =3D (UINT8) MemConfig->Scram= blerSupport; + FspmUpd->FspmConfig.SafeMode =3D (UINT8) MemConfig->SafeM= ode; + + // + // Update UPD:SmramMask and DisableDimmChannel + // + FspmUpd->FspmConfig.SmramMask =3D MemConfig->SmramMask; + FspmUpd->FspmConfig.DisableDimmChannel0 =3D MemConfig->DisableDimm= Channel[0]; + FspmUpd->FspmConfig.DisableDimmChannel1 =3D MemConfig->DisableDimm= Channel[1]; + FspmUpd->FspmConfig.HobBufferSize =3D MemConfig->HobBufferSi= ze; + + FspmUpd->FspmConfig.ECT =3D (UINT8) MemConfig->ECT; + FspmUpd->FspmConfig.SOT =3D (UINT8) MemConfig->SOT; + FspmUpd->FspmConfig.ERDMPRTC2D =3D (UINT8) MemConfig->ERD= MPRTC2D; + FspmUpd->FspmConfig.RDMPRT =3D (UINT8) MemConfig->RDM= PRT; + FspmUpd->FspmConfig.RCVET =3D (UINT8) MemConfig->RCV= ET; + FspmUpd->FspmConfig.JWRL =3D (UINT8) MemConfig->JWR= L; + FspmUpd->FspmConfig.EWRTC2D =3D (UINT8) MemConfig->EWR= TC2D; + FspmUpd->FspmConfig.ERDTC2D =3D (UINT8) MemConfig->ERD= TC2D; + FspmUpd->FspmConfig.WRTC1D =3D (UINT8) MemConfig->WRT= C1D; + FspmUpd->FspmConfig.WRVC1D =3D (UINT8) MemConfig->WRV= C1D; + FspmUpd->FspmConfig.RDTC1D =3D (UINT8) MemConfig->RDT= C1D; + FspmUpd->FspmConfig.DIMMODTT =3D (UINT8) MemConfig->DIM= MODTT; + FspmUpd->FspmConfig.DIMMRONT =3D (UINT8) MemConfig->DIM= MRONT; + FspmUpd->FspmConfig.WRSRT =3D (UINT8) MemConfig->WRS= RT; + FspmUpd->FspmConfig.RDODTT =3D (UINT8) MemConfig->RDO= DTT; + FspmUpd->FspmConfig.RDEQT =3D (UINT8) MemConfig->RDE= QT; + FspmUpd->FspmConfig.RDAPT =3D (UINT8) MemConfig->RDA= PT; + FspmUpd->FspmConfig.WRTC2D =3D (UINT8) MemConfig->WRT= C2D; + FspmUpd->FspmConfig.RDTC2D =3D (UINT8) MemConfig->RDT= C2D; + FspmUpd->FspmConfig.WRVC2D =3D (UINT8) MemConfig->WRV= C2D; + FspmUpd->FspmConfig.RDVC2D =3D (UINT8) MemConfig->RDV= C2D; + FspmUpd->FspmConfig.CMDVC =3D (UINT8) MemConfig->CMD= VC; + FspmUpd->FspmConfig.LCT =3D (UINT8) MemConfig->LCT; + FspmUpd->FspmConfig.RTL =3D (UINT8) MemConfig->RTL; + FspmUpd->FspmConfig.TAT =3D (UINT8) MemConfig->TAT; + FspmUpd->FspmConfig.RCVENC1D =3D (UINT8) MemConfig->RCV= ENC1D; + FspmUpd->FspmConfig.RMT =3D (UINT8) MemConfig->RMT; + FspmUpd->FspmConfig.MEMTST =3D (UINT8) MemConfig->MEM= TST; + FspmUpd->FspmConfig.ALIASCHK =3D (UINT8) MemConfig->ALI= ASCHK; + FspmUpd->FspmConfig.RMC =3D (UINT8) MemConfig->RMC; + FspmUpd->FspmConfig.WRDSUDT =3D (UINT8) MemConfig->WRD= SUDT; + FspmUpd->FspmConfig.EnBER =3D (UINT8) MemConfig->EnB= ER; + FspmUpd->FspmConfig.EccSupport =3D (UINT8) MemConfig->Ecc= Support; + FspmUpd->FspmConfig.RemapEnable =3D (UINT8) MemConfig->Rem= apEnable; + FspmUpd->FspmConfig.ScramblerSupport =3D (UINT8) MemConfig->Scr= amblerSupport; + FspmUpd->FspmConfig.MrcFastBoot =3D (UINT8) MemConfig->Mrc= FastBoot; + FspmUpd->FspmConfig.RankInterleave =3D (UINT8) MemConfig->Ran= kInterleave; + FspmUpd->FspmConfig.EnhancedInterleave =3D (UINT8) MemConfig->Enh= ancedInterleave; + FspmUpd->FspmConfig.MemoryTrace =3D (UINT8) MemConfig->Mem= oryTrace; + FspmUpd->FspmConfig.ChHashEnable =3D (UINT8) MemConfig->ChH= ashEnable; + FspmUpd->FspmConfig.EnableExtts =3D (UINT8) MemConfig->Ena= bleExtts; + FspmUpd->FspmConfig.EnableCltm =3D (UINT8) MemConfig->Ena= bleCltm; + FspmUpd->FspmConfig.EnableOltm =3D (UINT8) MemConfig->Ena= bleOltm; + FspmUpd->FspmConfig.EnablePwrDn =3D (UINT8) MemConfig->Ena= blePwrDn; + FspmUpd->FspmConfig.EnablePwrDnLpddr =3D (UINT8) MemConfig->Ena= blePwrDnLpddr; + FspmUpd->FspmConfig.UserPowerWeightsEn =3D (UINT8) MemConfig->Use= rPowerWeightsEn; + FspmUpd->FspmConfig.RaplLim2Lock =3D (UINT8) MemConfig->Rap= lLim2Lock; + FspmUpd->FspmConfig.RaplLim2Ena =3D (UINT8) MemConfig->Rap= lLim2Ena; + FspmUpd->FspmConfig.RaplLim1Ena =3D (UINT8) MemConfig->Rap= lLim1Ena; + FspmUpd->FspmConfig.SrefCfgEna =3D (UINT8) MemConfig->Sre= fCfgEna; + FspmUpd->FspmConfig.ThrtCkeMinDefeatLpddr =3D (UINT8) MemConfig->Thr= tCkeMinDefeatLpddr; + FspmUpd->FspmConfig.ThrtCkeMinDefeat =3D (UINT8) MemConfig->Thr= tCkeMinDefeat; + FspmUpd->FspmConfig.RhPrevention =3D (UINT8) MemConfig->RhP= revention; + FspmUpd->FspmConfig.ExitOnFailure =3D (UINT8) MemConfig->Exi= tOnFailure; + FspmUpd->FspmConfig.DdrThermalSensor =3D (UINT8) MemConfig->Ddr= ThermalSensor; + FspmUpd->FspmConfig.Ddr4DdpSharedClock =3D (UINT8) MemConfig->Ddr= 4DdpSharedClock; + FspmUpd->FspmConfig.Ddr4DdpSharedZq =3D (UINT8) MemConfig->Sha= redZqPin; + FspmUpd->FspmConfig.BClkFrequency =3D MemConfig->BClkFrequen= cy; + FspmUpd->FspmConfig.ChHashInterleaveBit =3D MemConfig->ChHashInter= leaveBit; + FspmUpd->FspmConfig.ChHashMask =3D MemConfig->ChHashMask; + FspmUpd->FspmConfig.EnergyScaleFact =3D MemConfig->EnergyScale= Fact; + FspmUpd->FspmConfig.Idd3n =3D MemConfig->Idd3n; + FspmUpd->FspmConfig.Idd3p =3D MemConfig->Idd3p; + FspmUpd->FspmConfig.CMDSR =3D (UINT8) MemConfig->CMD= SR; + FspmUpd->FspmConfig.CMDDSEQ =3D (UINT8) MemConfig->CMD= DSEQ; + FspmUpd->FspmConfig.CMDNORM =3D (UINT8) MemConfig->CMD= NORM; + FspmUpd->FspmConfig.EWRDSEQ =3D (UINT8) MemConfig->EWR= DSEQ; + FspmUpd->FspmConfig.FreqSaGvLow =3D MemConfig->FreqSaGvLow; + FspmUpd->FspmConfig.RhActProbability =3D MemConfig->RhActProbab= ility; + FspmUpd->FspmConfig.RaplLim2WindX =3D MemConfig->RaplLim2Win= dX; + FspmUpd->FspmConfig.RaplLim2WindY =3D MemConfig->RaplLim2Win= dY; + FspmUpd->FspmConfig.RaplLim1WindX =3D MemConfig->RaplLim1Win= dX; + FspmUpd->FspmConfig.RaplLim1WindY =3D MemConfig->RaplLim1Win= dY; + FspmUpd->FspmConfig.RaplLim2Pwr =3D MemConfig->RaplLim2Pwr; + FspmUpd->FspmConfig.RaplLim1Pwr =3D MemConfig->RaplLim1Pwr; + FspmUpd->FspmConfig.WarmThresholdCh0Dimm0 =3D MemConfig->WarmThresho= ldCh0Dimm0; + FspmUpd->FspmConfig.WarmThresholdCh0Dimm1 =3D MemConfig->WarmThresho= ldCh0Dimm1; + FspmUpd->FspmConfig.WarmThresholdCh1Dimm0 =3D MemConfig->WarmThresho= ldCh1Dimm0; + FspmUpd->FspmConfig.WarmThresholdCh1Dimm1 =3D MemConfig->WarmThresho= ldCh1Dimm1; + FspmUpd->FspmConfig.HotThresholdCh0Dimm0 =3D MemConfig->HotThreshol= dCh0Dimm0; + FspmUpd->FspmConfig.HotThresholdCh0Dimm1 =3D MemConfig->HotThreshol= dCh0Dimm1; + FspmUpd->FspmConfig.HotThresholdCh1Dimm0 =3D MemConfig->HotThreshol= dCh1Dimm0; + FspmUpd->FspmConfig.HotThresholdCh1Dimm1 =3D MemConfig->HotThreshol= dCh1Dimm1; + FspmUpd->FspmConfig.WarmBudgetCh0Dimm0 =3D MemConfig->WarmBudgetC= h0Dimm0; + FspmUpd->FspmConfig.WarmBudgetCh0Dimm1 =3D MemConfig->WarmBudgetC= h0Dimm1; + FspmUpd->FspmConfig.WarmBudgetCh1Dimm0 =3D MemConfig->WarmBudgetC= h1Dimm0; + FspmUpd->FspmConfig.WarmBudgetCh1Dimm1 =3D MemConfig->WarmBudgetC= h1Dimm1; + FspmUpd->FspmConfig.HotBudgetCh0Dimm0 =3D MemConfig->HotBudgetCh= 0Dimm0; + FspmUpd->FspmConfig.HotBudgetCh0Dimm1 =3D MemConfig->HotBudgetCh= 0Dimm1; + FspmUpd->FspmConfig.HotBudgetCh1Dimm0 =3D MemConfig->HotBudgetCh= 1Dimm0; + FspmUpd->FspmConfig.HotBudgetCh1Dimm1 =3D MemConfig->HotBudgetCh= 1Dimm1; + FspmUpd->FspmConfig.IdleEnergyCh0Dimm0 =3D MemConfig->IdleEnergyC= h0Dimm0; + FspmUpd->FspmConfig.IdleEnergyCh0Dimm1 =3D MemConfig->IdleEnergyC= h0Dimm1; + FspmUpd->FspmConfig.IdleEnergyCh1Dimm0 =3D MemConfig->IdleEnergyC= h1Dimm0; + FspmUpd->FspmConfig.IdleEnergyCh1Dimm1 =3D MemConfig->IdleEnergyC= h1Dimm1; + FspmUpd->FspmConfig.PdEnergyCh0Dimm0 =3D MemConfig->PdEnergyCh0= Dimm0; + FspmUpd->FspmConfig.PdEnergyCh0Dimm1 =3D MemConfig->PdEnergyCh0= Dimm1; + FspmUpd->FspmConfig.PdEnergyCh1Dimm0 =3D MemConfig->PdEnergyCh1= Dimm0; + FspmUpd->FspmConfig.PdEnergyCh1Dimm1 =3D MemConfig->PdEnergyCh1= Dimm1; + FspmUpd->FspmConfig.ActEnergyCh0Dimm0 =3D MemConfig->ActEnergyCh= 0Dimm0; + FspmUpd->FspmConfig.ActEnergyCh0Dimm1 =3D MemConfig->ActEnergyCh= 0Dimm1; + FspmUpd->FspmConfig.ActEnergyCh1Dimm0 =3D MemConfig->ActEnergyCh= 1Dimm0; + FspmUpd->FspmConfig.ActEnergyCh1Dimm1 =3D MemConfig->ActEnergyCh= 1Dimm1; + FspmUpd->FspmConfig.RdEnergyCh0Dimm0 =3D MemConfig->RdEnergyCh0= Dimm0; + FspmUpd->FspmConfig.RdEnergyCh0Dimm1 =3D MemConfig->RdEnergyCh0= Dimm1; + FspmUpd->FspmConfig.RdEnergyCh1Dimm0 =3D MemConfig->RdEnergyCh1= Dimm0; + FspmUpd->FspmConfig.RdEnergyCh1Dimm1 =3D MemConfig->RdEnergyCh1= Dimm1; + FspmUpd->FspmConfig.WrEnergyCh0Dimm0 =3D MemConfig->WrEnergyCh0= Dimm0; + FspmUpd->FspmConfig.WrEnergyCh0Dimm1 =3D MemConfig->WrEnergyCh0= Dimm1; + FspmUpd->FspmConfig.WrEnergyCh1Dimm0 =3D MemConfig->WrEnergyCh1= Dimm0; + FspmUpd->FspmConfig.WrEnergyCh1Dimm1 =3D MemConfig->WrEnergyCh1= Dimm1; + FspmUpd->FspmConfig.ThrtCkeMinTmr =3D MemConfig->ThrtCkeMinT= mr; + FspmUpd->FspmConfig.CkeRankMapping =3D MemConfig->CkeRankMapp= ing; + FspmUpd->FspmConfig.CaVrefConfig =3D MemConfig->CaVrefConfi= g; + FspmUpd->FspmConfig.RaplPwrFlCh1 =3D MemConfig->RaplPwrFlCh= 1; + FspmUpd->FspmConfig.RaplPwrFlCh0 =3D MemConfig->RaplPwrFlCh= 0; + FspmUpd->FspmConfig.EnCmdRate =3D MemConfig->EnCmdRate; + FspmUpd->FspmConfig.Refresh2X =3D MemConfig->Refresh2X; + FspmUpd->FspmConfig.EpgEnable =3D MemConfig->EpgEnable; + FspmUpd->FspmConfig.RhSolution =3D MemConfig->RhSolution; + FspmUpd->FspmConfig.UserThresholdEnable =3D MemConfig->UserThresho= ldEnable; + FspmUpd->FspmConfig.UserBudgetEnable =3D MemConfig->UserBudgetE= nable; + FspmUpd->FspmConfig.TsodTcritMax =3D MemConfig->TsodTcritMa= x; + FspmUpd->FspmConfig.TsodEventMode =3D MemConfig->TsodEventMo= de; + FspmUpd->FspmConfig.TsodEventPolarity =3D MemConfig->TsodEventPo= larity; + FspmUpd->FspmConfig.TsodCriticalEventOnly =3D MemConfig->TsodCritica= lEventOnly; + FspmUpd->FspmConfig.TsodEventOutputControl =3D MemConfig->TsodEventOu= tputControl; + FspmUpd->FspmConfig.TsodAlarmwindowLockBit =3D MemConfig->TsodAlarmwi= ndowLockBit; + FspmUpd->FspmConfig.TsodCriticaltripLockBit =3D MemConfig->TsodCritica= ltripLockBit; + FspmUpd->FspmConfig.TsodShutdownMode =3D MemConfig->TsodShutdow= nMode; + FspmUpd->FspmConfig.TsodThigMax =3D MemConfig->TsodThigMax; + FspmUpd->FspmConfig.TsodManualEnable =3D MemConfig->TsodManualE= nable; + FspmUpd->FspmConfig.IsvtIoPort =3D MemConfig->IsvtIoPort; + FspmUpd->FspmConfig.ForceOltmOrRefresh2x =3D MemConfig->ForceOltmOr= Refresh2x; + FspmUpd->FspmConfig.PwdwnIdleCounter =3D MemConfig->PwdwnIdleCo= unter; + FspmUpd->FspmConfig.CmdRanksTerminated =3D MemConfig->CmdRanksTer= minated; + FspmUpd->FspmConfig.GdxcEnable =3D MemConfig->GdxcEnable; + FspmUpd->FspmConfig.RMTLoopCount =3D MemConfig->RMTLoopCoun= t; + + // DDR4 Memory Timings + FspmUpd->FspmTestConfig.tRRD_L =3D (UINT8) MemConfig->tRRD_L; + FspmUpd->FspmTestConfig.tRRD_S =3D (UINT8) MemConfig->tRRD_S; + FspmUpd->FspmTestConfig.tWTR_L =3D (UINT8) MemConfig->tWTR_L; + FspmUpd->FspmTestConfig.tWTR_S =3D (UINT8) MemConfig->tWTR_S; + + // TurnAround Timing + // Read-to-Read + FspmUpd->FspmTestConfig.tRd2RdSG =3D MemConfig->tRd2RdSG; + FspmUpd->FspmTestConfig.tRd2RdDG =3D MemConfig->tRd2RdDG; + FspmUpd->FspmTestConfig.tRd2RdDR =3D MemConfig->tRd2RdDR; + FspmUpd->FspmTestConfig.tRd2RdDD =3D MemConfig->tRd2RdDD; + // Write-to-Read + FspmUpd->FspmTestConfig.tWr2RdSG =3D MemConfig->tWr2RdSG; + FspmUpd->FspmTestConfig.tWr2RdDG =3D MemConfig->tWr2RdDG; + FspmUpd->FspmTestConfig.tWr2RdDR =3D MemConfig->tWr2RdDR; + FspmUpd->FspmTestConfig.tWr2RdDD =3D MemConfig->tWr2RdDD; + // Write-to-Write + FspmUpd->FspmTestConfig.tWr2WrSG =3D MemConfig->tWr2WrSG; + FspmUpd->FspmTestConfig.tWr2WrDG =3D MemConfig->tWr2WrDG; + FspmUpd->FspmTestConfig.tWr2WrDR =3D MemConfig->tWr2WrDR; + FspmUpd->FspmTestConfig.tWr2WrDD =3D MemConfig->tWr2WrDD; + // Read-to-Write + FspmUpd->FspmTestConfig.tRd2WrSG =3D MemConfig->tRd2WrSG; + FspmUpd->FspmTestConfig.tRd2WrDG =3D MemConfig->tRd2WrDG; + FspmUpd->FspmTestConfig.tRd2WrDR =3D MemConfig->tRd2WrDR; + FspmUpd->FspmTestConfig.tRd2WrDD =3D MemConfig->tRd2WrDD; + } + + if (MiscPeiPreMemConfig !=3D NULL) { + FspmUpd->FspmConfig.IedSize =3D MiscPeiPreMemConfig->Ied= Size; + FspmUpd->FspmConfig.UserBd =3D MiscPeiPreMemConfig->Use= rBd; + FspmUpd->FspmConfig.SgDelayAfterPwrEn =3D MiscPeiPreMemConfig->SgD= elayAfterPwrEn; + FspmUpd->FspmConfig.SgDelayAfterHoldReset =3D MiscPeiPreMemConfig->SgD= elayAfterHoldReset; + FspmUpd->FspmConfig.MmioSize =3D MiscPeiPreMemConfig->Mmi= oSize; + FspmUpd->FspmConfig.MmioSizeAdjustment =3D MiscPeiPreMemConfig->Mmi= oSizeAdjustment; + FspmUpd->FspmConfig.TsegSize =3D MiscPeiPreMemConfig->Tse= gSize; + + FspmUpd->FspmTestConfig.SkipExtGfxScan =3D (UINT8) MiscPeiPr= eMemConfig->SkipExtGfxScan; + FspmUpd->FspmTestConfig.BdatEnable =3D (UINT8) MiscPeiPr= eMemConfig->BdatEnable; + FspmUpd->FspmTestConfig.BdatTestType =3D (UINT8) MiscPeiPr= eMemConfig->BdatTestType; + FspmUpd->FspmTestConfig.ScanExtGfxForLegacyOpRom =3D (UINT8) MiscPeiPr= eMemConfig->ScanExtGfxForLegacyOpRom; + FspmUpd->FspmTestConfig.LockPTMregs =3D (UINT8) MiscPeiPr= eMemConfig->LockPTMregs; + } + + if (Vtd !=3D NULL) { + FspmUpd->FspmConfig.X2ApicOptOut =3D (UINT8) Vtd->X2ApicOptOut; + FspmUpd->FspmConfig.VtdBaseAddress[0] =3D Vtd->BaseAddress[0]; + FspmUpd->FspmConfig.VtdBaseAddress[1] =3D Vtd->BaseAddress[1]; + FspmUpd->FspmConfig.VtdBaseAddress[2] =3D Vtd->BaseAddress[2]; + FspmUpd->FspmTestConfig.VtdDisable =3D (UINT8) Vtd->VtdDisable; + } + + if (PciePeiPreMemConfig !=3D NULL) { + FspmUpd->FspmConfig.DmiGen3ProgramStaticEq =3D (UINT8) PciePeiPreMemCo= nfig->DmiGen3ProgramStaticEq; + FspmUpd->FspmConfig.Peg0Enable =3D (UINT8) PciePeiPreMemConfig->Peg0En= able; + FspmUpd->FspmConfig.Peg1Enable =3D (UINT8) PciePeiPreMemConfig->Peg1En= able; + FspmUpd->FspmConfig.Peg2Enable =3D (UINT8) PciePeiPreMemConfig->Peg2En= able; + FspmUpd->FspmConfig.Peg3Enable =3D (UINT8) PciePeiPreMemConfig->Peg3En= able; + FspmUpd->FspmConfig.Peg0MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->= Peg0MaxLinkSpeed; + FspmUpd->FspmConfig.Peg1MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->= Peg1MaxLinkSpeed; + FspmUpd->FspmConfig.Peg2MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->= Peg2MaxLinkSpeed; + FspmUpd->FspmConfig.Peg3MaxLinkSpeed =3D (UINT8) PciePeiPreMemConfig->= Peg3MaxLinkSpeed; + FspmUpd->FspmConfig.Peg0MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->= Peg0MaxLinkWidth; + FspmUpd->FspmConfig.Peg1MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->= Peg1MaxLinkWidth; + FspmUpd->FspmConfig.Peg2MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->= Peg2MaxLinkWidth; + FspmUpd->FspmConfig.Peg3MaxLinkWidth =3D (UINT8) PciePeiPreMemConfig->= Peg3MaxLinkWidth; + FspmUpd->FspmConfig.Peg0PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem= Config->Peg0PowerDownUnusedLanes; + FspmUpd->FspmConfig.Peg1PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem= Config->Peg1PowerDownUnusedLanes; + FspmUpd->FspmConfig.Peg2PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem= Config->Peg2PowerDownUnusedLanes; + FspmUpd->FspmConfig.Peg3PowerDownUnusedLanes =3D (UINT8) PciePeiPreMem= Config->Peg3PowerDownUnusedLanes; + FspmUpd->FspmConfig.InitPcieAspmAfterOprom =3D (UINT8) PciePeiPreMemCo= nfig->InitPcieAspmAfterOprom; + FspmUpd->FspmConfig.PegDisableSpreadSpectrumClocking =3D (UINT8) PcieP= eiPreMemConfig->PegDisableSpreadSpectrumClocking; + for (Index =3D 0; Index < SA_DMI_MAX_LANE; Index++) { + FspmUpd->FspmConfig.DmiGen3RootPortPreset[Index] =3D PciePeiPreMemCo= nfig->DmiGen3RootPortPreset[Index]; + FspmUpd->FspmConfig.DmiGen3EndPointPreset[Index] =3D PciePeiPreMemCo= nfig->DmiGen3EndPointPreset[Index]; + FspmUpd->FspmConfig.DmiGen3EndPointHint[Index] =3D PciePeiPreMemConf= ig->DmiGen3EndPointHint[Index]; + } + for (Index =3D 0; Index < SA_DMI_MAX_BUNDLE; Index++) { + FspmUpd->FspmConfig.DmiGen3RxCtlePeaking[Index] =3D PciePeiPreMemCon= fig->DmiGen3RxCtlePeaking[Index]; + } + for (Index =3D 0; Index < SA_PEG_MAX_BUNDLE ; Index++) { + FspmUpd->FspmConfig.PegGen3RxCtlePeaking[Index] =3D PciePeiPreMemCon= fig->PegGen3RxCtlePeaking[Index]; + } + FspmUpd->FspmConfig.PegDataPtr =3D (UINT32) PciePeiPreMemConfig->PegDa= taPtr; + CopyMem((VOID *)FspmUpd->FspmConfig.PegGpioData, &PciePeiPreMemConfig-= >PegGpioData, sizeof (PEG_GPIO_DATA)); + FspmUpd->FspmConfig.DmiDeEmphasis =3D PciePeiPreMemConfig->DmiDeEmphas= is; + + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + FspmUpd->FspmConfig.PegRootPortHPE[Index] =3D PciePeiPreMemConfig->P= egRootPortHPE[Index]; + } + FspmUpd->FspmTestConfig.DmiMaxLinkSpeed =3D (UINT8) PciePeiPreMemC= onfig->DmiMaxLinkSpeed; + FspmUpd->FspmTestConfig.DmiGen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->DmiGen3EqPh2Enable; + FspmUpd->FspmTestConfig.DmiGen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->DmiGen3EqPh3Method; + FspmUpd->FspmTestConfig.Peg0Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->Peg0Gen3EqPh2Enable; + FspmUpd->FspmTestConfig.Peg1Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->Peg1Gen3EqPh2Enable; + FspmUpd->FspmTestConfig.Peg2Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->Peg2Gen3EqPh2Enable; + FspmUpd->FspmTestConfig.Peg3Gen3EqPh2Enable =3D (UINT8) PciePeiPreMemC= onfig->Peg3Gen3EqPh2Enable; + FspmUpd->FspmTestConfig.Peg0Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->Peg0Gen3EqPh3Method; + FspmUpd->FspmTestConfig.Peg1Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->Peg1Gen3EqPh3Method; + FspmUpd->FspmTestConfig.Peg2Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->Peg2Gen3EqPh3Method; + FspmUpd->FspmTestConfig.Peg3Gen3EqPh3Method =3D (UINT8) PciePeiPreMemC= onfig->Peg3Gen3EqPh3Method; + FspmUpd->FspmTestConfig.PegGen3ProgramStaticEq =3D (UINT8) PciePeiPreM= emConfig->PegGen3ProgramStaticEq; + FspmUpd->FspmTestConfig.Gen3SwEqAlwaysAttempt =3D (UINT8) PciePeiPreMe= mConfig->Gen3SwEqAlwaysAttempt; + FspmUpd->FspmTestConfig.Gen3SwEqNumberOfPresets =3D (UINT8) PciePeiPre= MemConfig->Gen3SwEqNumberOfPresets; + FspmUpd->FspmTestConfig.Gen3SwEqEnableVocTest =3D (UINT8) PciePeiPreMe= mConfig->Gen3SwEqEnableVocTest; + FspmUpd->FspmTestConfig.PegRxCemTestingMode =3D (UINT8) PciePeiPreMemC= onfig->PegRxCemTestingMode; + FspmUpd->FspmTestConfig.PegRxCemLoopbackLane =3D (UINT8) PciePeiPreMem= Config->PegRxCemLoopbackLane; + FspmUpd->FspmTestConfig.PegGenerateBdatMarginTable =3D (UINT8) PciePei= PreMemConfig->PegGenerateBdatMarginTable; + FspmUpd->FspmTestConfig.PegRxCemNonProtocolAwareness =3D (UINT8) PcieP= eiPreMemConfig->PegRxCemNonProtocolAwareness; + FspmUpd->FspmTestConfig.PegGen3RxCtleOverride =3D (UINT8) PciePeiPreMe= mConfig->PegGen3RxCtleOverride; + for (Index =3D 0; Index < SA_PEG_MAX_LANE; Index++) { + FspmUpd->FspmTestConfig.PegGen3RootPortPreset[Index] =3D PciePeiPreM= emConfig->PegGen3RootPortPreset[Index]; + FspmUpd->FspmTestConfig.PegGen3EndPointPreset[Index] =3D PciePeiPreM= emConfig->PegGen3EndPointPreset[Index]; + FspmUpd->FspmTestConfig.PegGen3EndPointHint[Index] =3D PciePeiPreMem= Config->PegGen3EndPointHint[Index]; + } + FspmUpd->FspmTestConfig.Gen3SwEqJitterDwellTime =3D PciePeiPreMemConfi= g->Gen3SwEqJitterDwellTime; + FspmUpd->FspmTestConfig.Gen3SwEqJitterErrorTarget =3D PciePeiPreMemCon= fig->Gen3SwEqJitterErrorTarget; + FspmUpd->FspmTestConfig.Gen3SwEqVocDwellTime =3D PciePeiPreMemConfig->= Gen3SwEqVocDwellTime; + FspmUpd->FspmTestConfig.Gen3SwEqVocErrorTarget =3D PciePeiPreMemConfig= ->Gen3SwEqVocErrorTarget; + } + + if (GtPreMemConfig !=3D NULL) { + FspmUpd->FspmConfig.PrimaryDisplay =3D (UINT8) GtPreMemConfig->Primary= Display; + FspmUpd->FspmConfig.InternalGfx =3D (UINT8) GtPreMemConfig->InternalGr= aphics; + FspmUpd->FspmConfig.IgdDvmt50PreAlloc =3D (UINT8) GtPreMemConfig->IgdD= vmt50PreAlloc; + FspmUpd->FspmConfig.ApertureSize =3D (UINT8) GtPreMemConfig->ApertureS= ize; + FspmUpd->FspmConfig.GttMmAdr =3D GtPreMemConfig->GttMmAdr; + FspmUpd->FspmConfig.GmAdr =3D GtPreMemConfig->GmAdr; + FspmUpd->FspmConfig.GttSize =3D GtPreMemConfig->GttSize; + FspmUpd->FspmConfig.PsmiRegionSize =3D (UINT8) GtPreMemConfig->PsmiReg= ionSize; + FspmUpd->FspmConfig.GtPsmiSupport =3D (UINT8)GtPreMemConfig->GtPsmiSup= port; + FspmUpd->FspmTestConfig.PanelPowerEnable =3D (UINT8) GtPreMemConfig->P= anelPowerEnable; + FspmUpd->FspmTestConfig.DeltaT12PowerCycleDelayPreMem =3D (UINT16) GtP= reMemConfig->DeltaT12PowerCycleDelayPreMem; + } + + if (SgGpioData !=3D NULL) { + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie0Gpio, &SgGpioData->SaR= td3Pcie0Gpio, sizeof (SA_PCIE_RTD3_GPIO)); + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie1Gpio, &SgGpioData->SaR= td3Pcie1Gpio, sizeof (SA_PCIE_RTD3_GPIO)); + CopyMem((VOID *) FspmUpd->FspmConfig.SaRtd3Pcie2Gpio, &SgGpioData->SaR= td3Pcie2Gpio, sizeof (SA_PCIE_RTD3_GPIO)); + FspmUpd->FspmConfig.RootPortIndex =3D SgGpioData->RootPortIndex; + } + + if (IpuPreMemPolicy !=3D NULL) { + FspmUpd->FspmConfig.SaIpuEnable =3D (UINT8) IpuPreMemPolicy->SaIpuEnab= le; + FspmUpd->FspmConfig.SaIpuImrConfiguration =3D (UINT8) IpuPreMemPolicy-= >SaIpuImrConfiguration; + } + + if (OcPreMemConfig !=3D NULL) { + FspmUpd->FspmConfig.SaOcSupport =3D (UINT8) OcPreMemConfig->OcSupport; + FspmUpd->FspmConfig.RealtimeMemoryTiming =3D (UINT8) OcPreMemConfig->R= ealtimeMemoryTiming; + FspmUpd->FspmConfig.GtVoltageMode =3D (UINT8) OcPreMemConfig->GtVoltag= eMode; + FspmUpd->FspmConfig.GtMaxOcRatio =3D OcPreMemConfig->GtMaxOcRatio; + FspmUpd->FspmConfig.GtVoltageOffset =3D OcPreMemConfig->GtVoltageOffse= t; + FspmUpd->FspmConfig.GtVoltageOverride =3D OcPreMemConfig->GtVoltageOve= rride; + FspmUpd->FspmConfig.GtExtraTurboVoltage =3D OcPreMemConfig->GtExtraTur= boVoltage; + FspmUpd->FspmConfig.SaVoltageOffset =3D OcPreMemConfig->SaVoltageOffse= t; + FspmUpd->FspmConfig.GtusMaxOcRatio =3D OcPreMemConfig->GtusMaxOcRatio; + FspmUpd->FspmConfig.GtusVoltageMode =3D (UINT8) OcPreMemConfig->GtusVo= ltageMode; + FspmUpd->FspmConfig.GtusVoltageOffset =3D OcPreMemConfig->GtusVoltageO= ffset; + FspmUpd->FspmConfig.GtusVoltageOverride =3D OcPreMemConfig->GtusVoltag= eOverride; + FspmUpd->FspmConfig.GtusExtraTurboVoltage =3D OcPreMemConfig->GtusExtr= aTurboVoltage; + } + + + + + return EFI_SUCCESS; +} + + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + SA_MISC_PEI_CONFIG *MiscPeiConfig; + GRAPHICS_PEI_CONFIG *GtConfig; + PCIE_PEI_CONFIG *PciePeiConfig; + GNA_CONFIG *GnaConfig; + UINT8 Index; + EFI_BOOT_MODE BootMode; + + MiscPeiConfig =3D NULL; + GtConfig =3D NULL; + PciePeiConfig =3D NULL; + GnaConfig =3D NULL; + + // + // @todo This could be cleared up after FSP provides ExitBootServices No= tifyPhase. + // + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // + // Locate SiPolicyPpi + // + SiPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPpi + ); + if ((Status =3D=3D EFI_SUCCESS) && (SiPolicyPpi !=3D NULL)) { + MiscPeiConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid= , (VOID *) &MiscPeiConfig); + ASSERT_EFI_ERROR (Status); + + GtConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGu= id, (VOID *) &GtConfig); + ASSERT_EFI_ERROR (Status); + + GnaConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOI= D *) &GnaConfig); + ASSERT_EFI_ERROR (Status); + + PciePeiConfig =3D NULL; + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid= , (VOID *) &PciePeiConfig); + ASSERT_EFI_ERROR (Status); + + } + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n")); + + + if (MiscPeiConfig !=3D NULL) { + FspsUpd->FspsConfig.Device4Enable =3D (UINT8) MiscPeiConfig->Device4En= able; + FspsUpd->FspsConfig.CridEnable =3D (UINT8) MiscPeiConfig->CridEnable; + FspsUpd->FspsTestConfig.ChapDeviceEnable =3D (UINT8) MiscPeiConfig->Ch= apDeviceEnable; + FspsUpd->FspsTestConfig.SkipPamLock =3D (UINT8) MiscPeiConfig->SkipPam= Lock; + FspsUpd->FspsTestConfig.EdramTestMode =3D (UINT8) MiscPeiConfig->Edram= TestMode; + } + + if (PciePeiConfig !=3D NULL) { + FspsUpd->FspsConfig.DmiAspm =3D (UINT8) PciePeiConfig->DmiAspm; + FspsUpd->FspsTestConfig.DmiExtSync =3D (UINT8) PciePeiConfig->DmiExtSy= nc; + FspsUpd->FspsTestConfig.DmiIot =3D (UINT8) PciePeiConfig->DmiIot; + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) { + FspsUpd->FspsConfig.PegDeEmphasis[Index] =3D PciePeiConfig->PegDeEmp= hasis[Index]; + FspsUpd->FspsConfig.PegSlotPowerLimitValue[Index] =3D PciePeiConfig-= >PegSlotPowerLimitValue[Index]; + FspsUpd->FspsConfig.PegSlotPowerLimitScale[Index] =3D PciePeiConfig-= >PegSlotPowerLimitScale[Index]; + FspsUpd->FspsConfig.PegPhysicalSlotNumber[Index] =3D PciePeiConfig->= PegPhysicalSlotNumber[Index]; + FspsUpd->FspsTestConfig.PegMaxPayload[Index] =3D PciePeiConfig->PegM= axPayload[Index]; + } + } + + if (GtConfig !=3D NULL) { + FspsUpd->FspsConfig.PavpEnable =3D (UINT8) GtConfig->PavpEnable; + FspsUpd->FspsConfig.CdClock =3D (UINT8) GtConfig->CdClock; + FspsUpd->FspsTestConfig.RenderStandby =3D (UINT8) GtConfig->RenderStan= dby; + FspsUpd->FspsTestConfig.PmSupport =3D (UINT8) GtConfig->PmSupport; + FspsUpd->FspsTestConfig.CdynmaxClampEnable =3D (UINT8) GtConfig->Cdynm= axClampEnable; + FspsUpd->FspsTestConfig.GtFreqMax =3D (UINT8) GtConfig->GtFreqMax; + FspsUpd->FspsTestConfig.DisableTurboGt =3D (UINT8) GtConfig->DisableTu= rboGt; + FspsUpd->FspsConfig.SkipS3CdClockInit =3D (UINT8)GtConfig->SkipS3CdClo= ckInit; + + // + // For FSP, FspsUpd->FspsConfig.PeiGraphicsPeimInit is always enabled = as default. + // + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D (UINT8) GtConfig->PeiGraph= icsPeimInit; // SA: InternalOnly: For Internal validation we still need to = enable both Enable/Disable Cases + + // + // Update UPD: VBT & LogoPtr + // + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32) NULL; + } else { + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32) GtConfig->Graphic= sConfigPtr; + } + DEBUG(( DEBUG_INFO, "VbtPtr from GraphicsPeiConfig is 0x%x\n", FspsUpd= ->FspsConfig.GraphicsConfigPtr)); + + FspsUpd->FspsConfig.LogoPtr =3D (UINT32) GtConfig->LogoPtr; + FspsUpd->FspsConfig.LogoSize =3D GtConfig->LogoSize; + DEBUG(( DEBUG_INFO, "LogoPtr from PeiFspSaPolicyInit GraphicsPeiConfig= is 0x%x\n", FspsUpd->FspsConfig.LogoPtr)); + DEBUG(( DEBUG_INFO, "LogoSize from PeiFspSaPolicyInit GraphicsPeiConfi= g is 0x%x\n", FspsUpd->FspsConfig.LogoSize)); + + FspsUpd->FspsConfig.BltBufferAddress =3D (UINT32) GtConfig->BltBuffer= Address; + FspsUpd->FspsConfig.BltBufferSize =3D (UINT32) GtConfig->BltBuffer= Size; + + // + // Update DDI/DDC configuration + // + FspsUpd->FspsConfig.DdiPortEdp =3D GtConfig->DdiConfiguration.DdiPortE= dp; + FspsUpd->FspsConfig.DdiPortBHpd =3D GtConfig->DdiConfiguration.DdiPort= BHpd; + FspsUpd->FspsConfig.DdiPortCHpd =3D GtConfig->DdiConfiguration.DdiPort= CHpd; + FspsUpd->FspsConfig.DdiPortDHpd =3D GtConfig->DdiConfiguration.DdiPort= DHpd; + FspsUpd->FspsConfig.DdiPortFHpd =3D GtConfig->DdiConfiguration.DdiPort= FHpd; + FspsUpd->FspsConfig.DdiPortBDdc =3D GtConfig->DdiConfiguration.DdiPort= BDdc; + FspsUpd->FspsConfig.DdiPortCDdc =3D GtConfig->DdiConfiguration.DdiPort= CDdc; + FspsUpd->FspsConfig.DdiPortDDdc =3D GtConfig->DdiConfiguration.DdiPort= DDdc; + FspsUpd->FspsConfig.DdiPortFDdc =3D GtConfig->DdiConfiguration.DdiPort= FDdc; + + } + + if (GnaConfig !=3D NULL) { + FspsUpd->FspsConfig.GnaEnable =3D (UINT8) GnaConfig->GnaEnable; +#ifdef TESTMENU_FLAG +#endif // TESTMENU_FLAG + } + + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspSecurityPolicyInitLib.c b/Platform/Intel/WhiskeylakeO= penBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInit= Lib.c new file mode 100644 index 0000000000..80d20d74a9 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspSecurityPolicyInitLib.c @@ -0,0 +1,70 @@ +/** @file + Implementation of Fsp Security Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Performs FSP Security PEI Policy initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSecurityPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem Star= t\n")); + + // + // Locate SiPreMemPolicyPpi + // + SiPreMemPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem End\= n")); + + return EFI_SUCCESS; +} + +/** + Performs FSP Security PEI Policy post memory initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSecurityPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiF= spPolicyInitLib/PeiFspSiPolicyInitLib.c b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c new file mode 100644 index 0000000000..98658782aa --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic= yInitLib/PeiFspSiPolicyInitLib.c @@ -0,0 +1,95 @@ +/** @file + Implementation of Fsp SI Policy Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +/** + Performs FSP SI PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInitPreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + // + // Locate SiPreMemPolicyPpi + // + SiPreMemPolicyPpi =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} + +/** + Performs FSP SI PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSiPolicyInit ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicy; + SI_CONFIG *SiConfig; + + // + // Locate SiPolicyPpi + // + SiPolicy =3D NULL; + Status =3D PeiServicesLocatePpi ( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPolicy + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &= SiConfig); + ASSERT_EFI_ERROR (Status); + + // + // Update SiConfig policies + // + FspsUpd->FspsConfig.SiCsmFlag =3D (UINT8)SiConfig->CsmFla= g; + FspsUpd->FspsConfig.SiSsidTablePtr =3D (UINT32)(UINTN)SiConfig= ->SsidTablePtr; + FspsUpd->FspsConfig.SiNumberOfSsidTableEntry =3D (UINT16)SiConfig->Numbe= rOfSsidTableEntry; + FspsUpd->FspsConfig.TraceHubMemBase =3D SiConfig->TraceHubMemB= ase; + + return EFI_SUCCESS; +} + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/Whiskeyl= akeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscU= pdUpdateLib.c new file mode 100644 index 0000000000..a341a58930 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -0,0 +1,100 @@ +/** @file + Implementation of Fsp Misc UPD Initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include "PeiMiscPolicyUpdate.h" + +/** + Performs FSP Misc UPD initialization. + + @param[in,out] FspmUpd Pointer to FSPM_UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND An instance of gEfiPeiReadOnly= Variable2PpiGuid + could not be located. + @retval EFI_OUT_OF_RESOURCES Insufficent resources to alloc= ate a memory buffer. +**/ +EFI_STATUS +EFIAPI +PeiFspMiscUpdUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + UINTN VariableSize; + VOID *MemorySavedData; + + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **) &VariableServices + ); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + VariableSize =3D 0; + MemorySavedData =3D NULL; + Status =3D VariableServices->GetVariable ( + VariableServices, + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + NULL, + &VariableSize, + MemorySavedData + ); + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { + MemorySavedData =3D AllocatePool (VariableSize); + if (MemorySavedData =3D=3D NULL) { + ASSERT (MemorySavedData !=3D NULL); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, "VariableSize is 0x%x\n", VariableSize)); + Status =3D VariableServices->GetVariable ( + VariableServices, + L"MemoryConfig", + &gFspNonVolatileStorageHobGuid, + NULL, + &VariableSize, + MemorySavedData + ); + if (Status =3D=3D EFI_SUCCESS) { + FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData; + } else { + DEBUG ((DEBUG_ERROR, "Fail to retrieve Variable:\"MemoryConfig\" gMe= moryConfigVariableGuid, Status =3D %r\n", Status)); + ASSERT_EFI_ERROR (Status); + } + } + FspmUpd->FspmArchUpd.NvsBufferPtr =3D MemorySavedData; + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c b/Platform/Intel/Whiskeyla= keOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicy= UpdateLib.c new file mode 100644 index 0000000000..5119e934a2 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiFspPolicyUpdateLib.c @@ -0,0 +1,124 @@ +/** @file + Provide FSP wrapper platform related function. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "PeiMiscPolicyUpdate.h" + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ); + +VOID +InternalPrintVariableData ( + IN UINT8 *Data8, + IN UINTN DataSize + ) +{ + UINTN Index; + + for (Index =3D 0; Index < DataSize; Index++) { + if (Index % 0x10 =3D=3D 0) { + DEBUG ((DEBUG_INFO, "\n%08X:", Index)); + } + DEBUG ((DEBUG_INFO, " %02X", *Data8++)); + } + DEBUG ((DEBUG_INFO, "\n")); +} + +/** + Performs silicon pre-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePreMem(). + + 1) In FSP path, the input Policy should be FspmUpd. + A platform may use this API to update the FSPM UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPM UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePreMem ( + IN OUT VOID *FspmUpd + ) +{ + FSPM_UPD *FspmUpdDataPtr; + + FspmUpdDataPtr =3D FspmUpd; + + PeiFspMiscUpdUpdatePreMem (FspmUpdDataPtr); + InternalPrintVariableData ((VOID *) FspmUpdDataPtr, sizeof (FSPM_UPD)); + + return FspmUpd; +} + +/** + Performs silicon post-mem policy update. + + The meaning of Policy is defined by silicon code. + It could be the raw data, a handle, a PPI, etc. + + The input Policy must be returned by SiliconPolicyDonePostMem(). + + 1) In FSP path, the input Policy should be FspsUpd. + A platform may use this API to update the FSPS UPD policy initialized + by the silicon module or the default UPD data. + The output of FSPS UPD data from this API is the final UPD data. + + 2) In non-FSP path, the board may use additional way to get + the silicon policy data field based upon the input Policy. + + @param[in, out] Policy Pointer to policy. + + @return the updated policy. +**/ +VOID * +EFIAPI +SiliconPolicyUpdatePostMem ( + IN OUT VOID *FspsUpd + ) +{ + FSPS_UPD *FspsUpdDataPtr; + + FspsUpdDataPtr =3D FspsUpd; + + PeiFspPchPolicyUpdate (FspsUpd); + InternalPrintVariableData ((VOID * )FspsUpdDataPtr, sizeof (FSPS_UPD)); + + return FspsUpd; +} diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c b/Platform/Intel/WhiskeylakeO= penBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpd= ate.c new file mode 100644 index 0000000000..455467dc25 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiPchPolicyUpdate.c @@ -0,0 +1,60 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP PCH PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + FspsUpd->FspsConfig.PchPcieDeviceOverrideTablePtr =3D (UINT32) mPcieDevi= ceTable; + + AddPlatformVerbTables ( + PchHdaCodecPlatformOnboard, + &(FspsUpd->FspsConfig.PchHdaVerbTableEntryNum), + &(FspsUpd->FspsConfig.PchHdaVerbTablePtr) + ); + +DEBUG_CODE_BEGIN(); +if ((PcdGet8 (PcdSerialIoUartDebugEnable) =3D=3D 1) && + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 = (PcdSerialIoUartNumber)] =3D=3D PchSerialIoDisabled ) { + FspsUpd->FspsConfig.SerialIoDevMode[PchSerialIoIndexUart0 + PcdGet8 (P= cdSerialIoUartNumber)] =3D PchSerialIoHidden; + } +DEBUG_CODE_END(); + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/Whiske= ylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPol= icyUpdatePreMem.c new file mode 100644 index 0000000000..cbb818c875 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,39 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP PCH PEI Policy pre mem initialization. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspPchPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/WhiskeylakeOp= enBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdat= e.c new file mode 100644 index 0000000000..2114479030 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -0,0 +1,85 @@ +/** @file +Do Platform Stage System Agent initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Performs FSP SA PEI Policy initialization. + + @param[in][out] FspsUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdate ( + IN OUT FSPS_UPD *FspsUpd + ) +{ + VOID *Buffer; + VOID *MemBuffer; + UINT32 Size; + + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; + + Size =3D 0; + Buffer =3D NULL; + PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_WARN, "Could not locate VBT\n")); + } else { + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32)(UINTN)MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + FspsUpd->FspsConfig.GraphicsConfigPtr =3D 0; + } + } + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", F= spsUpd->FspsConfig.GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size= )); + + Size =3D 0; + Buffer =3D NULL; + PeiGetSectionFromAnyFv (&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, = &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } else { + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + FspsUpd->FspsConfig.LogoPtr =3D (UINT32)(UINTN)MemBuffer; + FspsUpd->FspsConfig.LogoSize =3D Size; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + FspsUpd->FspsConfig.LogoPtr =3D 0; + FspsUpd->FspsConfig.LogoSize =3D 0; + } + } + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", FspsU= pd->FspsConfig.LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", Fsps= Upd->FspsConfig.LogoSize)); + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/Whiskey= lakeOpenBoardPkg/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolic= yUpdatePreMem.c new file mode 100644 index 0000000000..946182864e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiSiliconP= olicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,87 @@ +/** @file +Do Platform Stage System Agent initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Performs FSP SA PEI Policy initialization in pre-memory. + + @param[in][out] FspmUpd Pointer to FSP UPD Data. + + @retval EFI_SUCCESS FSP UPD Data is updated. + @retval EFI_NOT_FOUND Fail to locate required PPI. + @retval Other FSP UPD Data update process fail. +**/ +EFI_STATUS +EFIAPI +PeiFspSaPolicyUpdatePreMem ( + IN OUT FSPM_UPD *FspmUpd + ) +{ + VOID *Buffer; + + // + // If SpdAddressTable are not all 0, it means DIMM slots implemented and + // MemorySpdPtr* already updated by reading SPD from DIMM in SiliconPoli= cyInitPreMem. + // + // If SpdAddressTable all 0, this is memory down design and hardcoded Sp= dData + // should be applied to MemorySpdPtr*. + // + if ((PcdGet8 (PcdMrcSpdAddressTable0) =3D=3D 0) && (PcdGet8 (PcdMrcSpdAd= dressTable1) =3D=3D 0) + && (PcdGet8 (PcdMrcSpdAddressTable2) =3D=3D 0) && (PcdGet8 (PcdMrcSp= dAddressTable3) =3D=3D 0)) { + DEBUG ((DEBUG_INFO, "Overriding SPD data for down memory.\n")); + CopyMem ( + (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr00, + (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), + PcdGet16 (PcdMrcSpdDataSize) + ); + CopyMem ( + (VOID *) (UINTN) FspmUpd->FspmConfig.MemorySpdPtr10, + (VOID *) (UINTN) PcdGet32 (PcdMrcSpdData), + PcdGet16 (PcdMrcSpdDataSize) + ); + } + + DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings= ...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh0, Buffer, 12); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqByteMapCh1, (UINT8*) Buffer + 1= 2, 12); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqsMapCpu2Dram); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh0, Buffer, 8); + CopyMem ((VOID *)FspmUpd->FspmConfig.DqsMapCpu2DramCh1, (UINT8*) Buffe= r + 8, 8); + } + + DEBUG((DEBUG_INFO, "Updating Dq Pins Interleaved,Rcomp Resistor & Rcomp = Target Settings...\n")); + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompResistor); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompResistor, Buffer, 6); + } + Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcRcompTarget); + if (Buffer) { + CopyMem ((VOID *)FspmUpd->FspmConfig.RcompTarget, Buffer, 10); + } + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/Whiskey= lakeOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/FspWrapperP= latformSecLib.c new file mode 100644 index 0000000000..a767289bc5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/FspWrapperPlatformSecLib.c @@ -0,0 +1,163 @@ +/** @file + Provide FSP wrapper platform sec related function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/** + This interface conveys state information out of the Security (SEC) phase= into PEI. + + @param[in] PeiServices Pointer to the PEI Services Tab= le. + @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer. + @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ); + +/** + This interface conveys performance information out of the Security (SEC)= phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an= optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the + PEI Foundation. As such, if the platform supports collecting performance= data in SEC, + this information is encapsulated into the data structure abstracted by t= his service. + This information is collected for the boot-strap processor (BSP) on IA-3= 2. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI. + @param[out] Performance The pointer to performance data collected in SE= C phase. + + @retval EFI_SUCCESS The data was successfully returned. + +**/ +EFI_STATUS +EFIAPI +SecGetPerformance ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_SEC_PERFORMANCE_PPI *This, + OUT FIRMWARE_SEC_PERFORMANCE *Performance + ); + +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi =3D { + SecGetPerformance +}; + +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gTopOfTemporaryRamPpiGuid, + NULL // To be patched later. + }, + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gPeiSecPerformancePpiGuid, + &mSecPerformancePpi + }, +}; + +#define LEGACY_8259_MASK_REGISTER_MASTER 0x21 +#define LEGACY_8259_MASK_REGISTER_SLAVE 0xA1 +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER 0x4D0 +#define LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE 0x4D1 + +/** + Write to mask and edge/level triggered registers of master and slave 825= 9 PICs. + + @param[in] Mask low byte for master PIC mask register, + high byte for slave PIC mask register. + @param[in] EdgeLevel low byte for master PIC edge/level triggered regi= ster, + high byte for slave PIC edge/level triggered regi= ster. + +**/ +VOID +Interrupt8259WriteMask ( + IN UINT16 Mask, + IN UINT16 EdgeLevel + ) +{ + IoWrite8 (LEGACY_8259_MASK_REGISTER_MASTER, (UINT8) Mask); + IoWrite8 (LEGACY_8259_MASK_REGISTER_SLAVE, (UINT8) (Mask >> 8)); + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_MASTER, (UINT8) Edge= Level); + IoWrite8 (LEGACY_8259_EDGE_LEVEL_TRIGGERED_REGISTER_SLAVE, (UINT8) (Edge= Level >> 8)); +} + +/** + A developer supplied function to perform platform specific operations. + + It's a developer supplied function to perform any operations appropriate= to a + given platform. It's invoked just before passing control to PEI core by = SEC + core. Platform developer may modify the SecCoreData passed to PEI Core. + It returns a platform specific PPI list that platform wishes to pass to = PEI core. + The Generic SEC core module will merge this list to join the final list = passed to + PEI core. + + @param[in,out] SecCoreData The same parameter as passing to PE= I core. It + could be overridden by this functio= n. + + @return The platform specific PPI list to be passed to PEI core or + NULL if there is no need of such platform specific PPI list. + +**/ +EFI_PEI_PPI_DESCRIPTOR * +EFIAPI +SecPlatformMain ( + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData + ) +{ + EFI_PEI_PPI_DESCRIPTOR *PpiList; + + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCo= reData->BootFirmwareVolumeBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCo= reData->BootFirmwareVolumeSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCo= reData->TemporaryRamBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCo= reData->TemporaryRamSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCo= reData->PeiTemporaryRamBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCo= reData->PeiTemporaryRamSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCo= reData->StackBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCo= reData->StackSize)); + + InitializeApicTimer (0, (UINT32) -1, TRUE, 5); + + // + // Set all 8259 interrupts to edge triggered and disabled + // + Interrupt8259WriteMask (0xFFFF, 0x0000); + + // + // Use middle of Heap as temp buffer, it will be copied by caller. + // Do not use Stack, because it will cause wrong calculation on stack by= PeiCore + // + PpiList =3D (VOID *)((UINTN)SecCoreData->PeiTemporaryRamBase + (UINTN)Se= cCoreData->PeiTemporaryRamSize/2); + CopyMem (PpiList, mPeiSecPlatformPpi, sizeof(mPeiSecPlatformPpi)); + + // + // Patch TopOfTemporaryRamPpi + // + PpiList[0].Ppi =3D (VOID *)((UINTN)SecCoreData->TemporaryRamBase + SecCo= reData->TemporaryRamSize); + + return PpiList; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/PlatformInit.c b/Platform/Intel/WhiskeylakeOpenBoar= dPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/PlatformInit.c new file mode 100644 index 0000000000..06ca63c19a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/PlatformInit.c @@ -0,0 +1,54 @@ +/** @file + Provide platform init function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Platform initialization. + + @param[in] FspHobList HobList produced by FSP. + @param[in] StartOfRange Start of temporary RAM. + @param[in] EndOfRange End of temporary RAM. +**/ +VOID +EFIAPI +PlatformInit ( + IN VOID *FspHobList, + IN VOID *StartOfRange, + IN VOID *EndOfRange + ) +{ + /// + /// Halt the TCO timer as early as possible + /// + IoWrite16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT, B_TCO_IO_TC= O1_CNT_TMR_HLT); + + // + // Platform initialization + // Enable Serial port here + // + if (PcdGetBool(PcdSecSerialPortDebugEnable)) { + SerialPortInitialize (); + } + + DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n")); + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList)); + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange)); + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange)); + + BoardAfterTempRamInit (); + + TestPointTempMemoryFunction (StartOfRange, EndOfRange); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecGetPerformance.c b/Platform/Intel/WhiskeylakeOpe= nBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c new file mode 100644 index 0000000000..67bdd232bb --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecGetPerformance.c @@ -0,0 +1,90 @@ +/** @file + Sample to provide SecGetPerformance function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include +#include + +/** + This interface conveys performance information out of the Security (SEC)= phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an= optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the + PEI Foundation. As such, if the platform supports collecting performance= data in SEC, + this information is encapsulated into the data structure abstracted by t= his service. + This information is collected for the boot-strap processor (BSP) on IA-3= 2. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI. + @param[out] Performance The pointer to performance data collected in SE= C phase. + + @retval EFI_SUCCESS The data was successfully returned. + +**/ +EFI_STATUS +EFIAPI +SecGetPerformance ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_SEC_PERFORMANCE_PPI *This, + OUT FIRMWARE_SEC_PERFORMANCE *Performance + ) +{ + UINT32 Size; + UINT32 Count; + UINT32 TopOfTemporaryRam; + UINT64 Ticker; + VOID *TopOfTemporaryRamPpi; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SecGetPerformance\n")); + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gTopOfTemporaryRamPpiGuid, + 0, + NULL, + (VOID **) &TopOfTemporaryRamPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + // + // |--------------| <- TopOfTemporaryRam - BL + // | List Ptr | + // |--------------| + // | BL RAM Start | + // |--------------| + // | BL RAM End | + // |--------------| + // |Number of BSPs| + // |--------------| + // | BIST | + // |--------------| + // | .... | + // |--------------| + // | TSC[63:32] | + // |--------------| + // | TSC[31:00] | + // |--------------| + // + TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof(UINT3= 2); + TopOfTemporaryRam -=3D sizeof(UINT32) * 2; + Count =3D *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (U= INT32)); + Size =3D Count * sizeof (UINT32); + + Ticker =3D *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze - sizeof (UINT32) * 2); + Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecPlatformInformation.c b/Platform/Intel/Whiskeyla= keOpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformIn= formation.c new file mode 100644 index 0000000000..e05daa8784 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecPlatformInformation.c @@ -0,0 +1,79 @@ +/** @file + Provide SecPlatformInformation function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include + +/** + This interface conveys state information out of the Security (SEC) phase= into PEI. + + @param[in] PeiServices Pointer to the PEI Services Tab= le. + @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer. + @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ) +{ + UINT32 *Bist; + UINT32 Size; + UINT32 Count; + UINT32 TopOfTemporaryRam; + VOID *TopOfTemporaryRamPpi; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n")); + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gTopOfTemporaryRamPpiGuid, + 0, + NULL, + (VOID **) &TopOfTemporaryRamPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + // + // The entries of BIST information, together with the number of them, + // reside in the bottom of stack, left untouched by normal stack operati= on. + // This routine copies the BIST information to the buffer pointed by + // PlatformInformationRecord for output. + // + TopOfTemporaryRam =3D (UINT32)(UINTN)TopOfTemporaryRamPpi - sizeof (UINT= 32); + TopOfTemporaryRam -=3D sizeof(UINT32) * 2; + Count =3D *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (U= INT32))); + Size =3D Count * sizeof (IA32_HANDOFF_STATUS); + + if ((*StructureSize) < (UINT64) Size) { + *StructureSize =3D Size; + return EFI_BUFFER_TOO_SMALL; + } + + *StructureSize =3D Size; + Bist =3D (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze); + + CopyMem (PlatformInformationRecord, Bist, Size); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecRamInitData.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecRamInitData.c new file mode 100644 index 0000000000..04f12a9438 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecRamInitData.c @@ -0,0 +1,37 @@ +/** @file + Provide TempRamInitParams data. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include "FsptCoreUpd.h" + +typedef struct { + FSP_UPD_HEADER FspUpdHeader; + FSPT_CORE_UPD FsptCoreUpd; +} FSPT_UPD_CORE_DATA; + +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr =3D { + { + 0x4450555F54505346, + 0x00, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }, + { + ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchAddress) + FixedPcdGet32 (= PcdFlashMicrocodeOffset)), + ((UINT32)FixedPcdGet64 (PcdCpuMicrocodePatchRegionSize) - FixedPcdGet3= 2 (PcdFlashMicrocodeOffset)), + 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used. + FixedPcdGet32 (PcdFlashCodeCacheSize), + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + } +}; + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/SecTempRamDone.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecTempRamDone.c new file mode 100644 index 0000000000..6d65d7d23f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/SecTempRamDone.c @@ -0,0 +1,48 @@ +/** @file + Provide SecTemporaryRamDone function. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +/** +This interface disables temporary memory in SEC Phase. +**/ +VOID +EFIAPI +SecPlatformDisableTemporaryMemory ( + VOID + ) +{ + EFI_STATUS Status; + VOID *TempRamExitParam; + + DEBUG((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n")); + + Status =3D BoardInitBeforeTempRamExit (); + ASSERT_EFI_ERROR (Status); + + TempRamExitParam =3D UpdateTempRamExitParam (); + Status =3D CallTempRamExit (TempRamExitParam); + DEBUG((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status)); + ASSERT_EFI_ERROR(Status); + + Status =3D BoardInitAfterTempRamExit (); + ASSERT_EFI_ERROR (Status); + + return ; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/Ba= seAcpiTimerLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimer= Lib/BaseAcpiTimerLib.c new file mode 100644 index 0000000000..7bdb3943e5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiT= imerLib.c @@ -0,0 +1,48 @@ +/** @file + ACPI Timer implements one instance of Timer Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +/** + Calculate TSC frequency. + + The TSC counting frequency is determined by comparing how far it counts + during a 101.4 us period as determined by the ACPI timer. + The ACPI timer is used because it counts at a known frequency. + The TSC is sampled, followed by waiting 363 counts of the ACPI timer, + or 101.4 us. The TSC is then sampled again. The difference multiplied by + 9861 is the TSC frequency. There will be a small error because of the + overhead of reading the ACPI timer. An attempt is made to determine and + compensate for this error. + + @return The number of TSC counts per second. + +**/ +UINT64 +InternalCalculateTscFrequency ( + VOID + ); + +/** + Internal function to retrieves the 64-bit frequency in Hz. + + Internal function to retrieves the 64-bit frequency in Hz. + + @return The frequency in Hz. + +**/ +UINT64 +InternalGetPerformanceCounterFrequency ( + VOID + ) +{ + return InternalCalculateTscFrequency (); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpande= rLib/BaseGpioExpanderLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library= /BaseGpioExpanderLib/BaseGpioExpanderLib.c new file mode 100644 index 0000000000..8498952888 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.c @@ -0,0 +1,310 @@ +/** @file + Support for IO expander TCA6424. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +// +// Addresses of registers inside expander +// +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mInputRegister[3] =3D {0x0,0x1,0x2= }; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mOutputRegister[3] =3D {0x4,0x5,0x6= }; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mConfigRegister[3] =3D {0xC,0xD,0xE= }; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mPolarityRegister[3] =3D {0x8,0x9,0xA= }; + +#define PCH_SERIAL_IO_I2C4 4 +#define TCA6424_I2C_ADDRESS 0x22 +#define PINS_PER_REGISTER 8 +#define GPIO_EXP_PIN_DIRECTION_OUT 1 +#define GPIO_EXP_PIN_DIRECTION_IN 0 +#define GPIO_EXP_PIN_POLARITY_NORMAL 0 +#define GPIO_EXP_PIN_POLARITY_INVERTED 1 +#define GPIO_EXP_SET_OUTPUT 0 +#define GPIO_EXP_SET_DIR 1 +#define GPIO_EXP_GET_INPUT 2 +#define GPIO_EXP_SET_POLARITY 3 +#define AUTO_INCREMENT 0x80 + +/** + Returns the Controller on which GPIO expander is present. + + This function returns the Controller value + + @param[out] Controller Pointer to a Controller value on + which I2C expander is configured. + + @retval EFI_SUCCESS non. +**/ +EFI_STATUS +GpioExpGetController ( + OUT UINT8 *Controller + ) +{ + *Controller =3D PCH_SERIAL_IO_I2C4; + return EFI_SUCCESS; +} + +/** + Returns the data from register value giving in the input. + + This function is to get the data from the Expander + Registers by following the I2C Protocol communication + + + @param[in] Bar0 Bar address of the SerialIo Controller + @param[in] Address Expander Value with in the Contoller + @param[in] Register Address of Input/Output/Configure/Polarity + registers with in the Expander + + @retval UINT8 Value returned from the register +**/ +UINT8 +GpioExpGetRegister ( + IN UINTN Bar0, + IN UINT8 Address, + IN UINT8 Register + ) +{ + EFI_STATUS Status; + UINT8 WriBuf[1]; + UINT8 ReBuf[1] =3D {0}; + + WriBuf[0] =3D Register; + Status =3D I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 1, WriBuf, 1= , ReBuf, WAIT_1_SECOND); + + return ReBuf[0]; +} +/** + Set the input register to a give value mentioned in the function. + + This function is to Programm the data value to the Expander + Register by following the I2C Protocol communication. + + @param[in] Bar0 Bar address of the SerialIo Controller + @param[in] Address Expander Value with in the Contoller + @param[in] Register Address of Input/Output/Configure/Polarity + registers with in the Expander + @param[in] Value Value to set in the mentioned the register +**/ +VOID +GpioExpSetRegister ( + IN UINTN Bar0, + IN UINT8 Address, + IN UINT8 Register, + IN UINT8 Value + ) +{ + EFI_STATUS Status; + UINT8 WriBuf[2]; + + WriBuf[0] =3D Register; + WriBuf[1] =3D Value; + Status =3D I2cWriteRead( Bar0, TCA6424_I2C_ADDRESS+Address, 2, WriBuf, 0= , NULL, WAIT_1_SECOND); + +} +/** + Set the input register to a give value mentioned in the function. + + This function is to update the status of the Gpio Expander + pin based on the input Operation value of the caller.This + function calculates the exact address of the register with + the help of the Register Bank + + @param[in] Controller SerialIo Controller value + @param[in] Expander Expander Value with in the Contoller + @param[in] Pin Pin with in the Expnader Value + @param[in] Value none + @param[in] Operation Type of operation (Setoutput/Setdirection + /Getinput/Setpolarity) + @retval UINT8 Final Value returned from the register +**/ +UINT8 +GpioExpDecodeRegAccess ( + IN UINT8 Controller, + IN UINT8 Expander, + IN UINT8 Pin, + IN UINT8 Value, + IN UINT8 Operation + ) +{ + UINT8* RegisterBank; + UINT8 OldValue; + UINT8 NewValue; + UINT8 RegisterAddress; + UINT8 PinNumber; + UINT8 ReturnValue =3D 0; + + DEBUG ((DEBUG_INFO, "GpioExpDecodeRegAccess() %x:%x:%x:%x:%x\n", Control= ler, Expander, Pin, Value, Operation)); + ASSERT(Controller<6); + ASSERT(Expander<2); + ASSERT(Pin<24); + ASSERT(Value<2); + ASSERT(Operation<4); + // + // Find the register Address value based on the OPeration + // + switch(Operation) { + case GPIO_EXP_SET_OUTPUT: + RegisterBank =3D mOutputRegister; + break; + case GPIO_EXP_SET_DIR: + RegisterBank =3D mConfigRegister; + break; + case GPIO_EXP_GET_INPUT: + RegisterBank =3D mInputRegister; + break; + case GPIO_EXP_SET_POLARITY: + RegisterBank =3D mPolarityRegister; + break; + default: + ASSERT(FALSE); + return 0; + } + // + // Each bit of register represents each Pin + // calaulate the register address and Pinnumber(offset with in register) + // + if (Pin >=3D 24) { + // + // Avoid out-of-bound usage of RegisterBank + // + return 0; + } + + RegisterAddress =3D RegisterBank[(Pin/PINS_PER_REGISTER)]; + PinNumber =3D Pin%PINS_PER_REGISTER; + + OldValue =3D GpioExpGetRegister(FindSerialIoBar(Controller, 0), Expander= , RegisterAddress); + // + // If it to get the data ,just returned otherwise mark the input value a= nd write the register + // + if (Operation =3D=3D GPIO_EXP_GET_INPUT) { + ReturnValue =3D 0x1 & (OldValue>>PinNumber); + } else { + NewValue =3D OldValue; + NewValue &=3D ~(BIT0<>8) & 0xFF; + WriteBuf[3] =3D (Output>>16) & 0xFF; + I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); + WriteBuf[0] =3D mPolarityRegister[0] + AUTO_INCREMENT; + WriteBuf[1] =3D Polarity & 0xFF; + WriteBuf[2] =3D (Polarity>>8) & 0xFF; + WriteBuf[3] =3D (Polarity>>16) & 0xFF; + I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); + WriteBuf[0] =3D mConfigRegister[0] + AUTO_INCREMENT; + WriteBuf[1] =3D Direction & 0xFF; + WriteBuf[2] =3D (Direction>>8) & 0xFF; + WriteBuf[3] =3D (Direction>>16) & 0xFF; + I2cWriteRead( FindSerialIoBar(Controller,0), TCA6424_I2C_ADDRESS+Expande= r, 4, WriteBuf, 0, NULL, WAIT_1_SECOND); + +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTable= Lib/PeiHdaVerbTableLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/P= eiHdaVerbTableLib/PeiHdaVerbTableLib.c new file mode 100644 index 0000000000..b8afd791f0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.c @@ -0,0 +1,132 @@ +/** @file + This file is SampleCode of the library for Intel HD Audio Verb Table con= figuration. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include "PchHdaVerbTables.h" + +/** + Add verb table helper function. + This function calculates verbtable number and shows verb table informati= on. + + @param[in,out] VerbTableEntryNum Input current VerbTable number and= output the number after adding new table + @param[in,out] VerbTableArray Pointer to array of VerbTable + @param[in] VerbTable VerbTable which is going to add in= to array +**/ +STATIC +VOID +InternalAddVerbTable ( + IN OUT UINT8 *VerbTableEntryNum, + IN OUT UINT32 *VerbTableArray, + IN HDAUDIO_VERB_TABLE *VerbTable + ) +{ + if (VerbTable =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "InternalAddVerbTable wrong input: VerbTable =3D= =3D NULL\n")); + return; + } + + VerbTableArray[*VerbTableEntryNum] =3D (UINT32) VerbTable; + *VerbTableEntryNum +=3D 1; + + DEBUG ((DEBUG_INFO, + "HDA: Add verb table for vendor =3D 0x%04X devId =3D 0x%04X (size =3D = %d DWords)\n", + VerbTable->Header.VendorId, + VerbTable->Header.DeviceId, + VerbTable->Header.DataDwords) + ); +} + +/** + Add verb table function. + This function update the verb table number and verb table ptr of policy. + + @param[in] HdAudioConfig HD Audio config block + @param[out] VerbTableEntryNum Number of verb table entries + @param[out] HdaVerbTablePtr Pointer to the verb table +**/ +VOID +AddPlatformVerbTables ( + IN UINT8 CodecType, + OUT UINT8 *VerbTableEntryNum, + OUT UINT32 *HdaVerbTablePtr + ) +{ + UINT8 VerbTableEntries; + UINT32 VerbTableArray[6]; + UINT32 *VerbTablePtr; + + VerbTableEntries =3D 0; + + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UINTN= ) PcdGet32 (PcdDisplayAudioHdaVerbTable)); + + if (CodecType =3D=3D PchHdaCodecPlatformOnboard) { + DEBUG ((DEBUG_INFO, "HDA Policy: Onboard codec selected\n")); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdHdaVerbTable)); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdHdaVerbTable2)); + } else { + DEBUG ((DEBUG_INFO, "HDA Policy: External codec kit selected\n")); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdCommonHdaVerbTable1)); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdCommonHdaVerbTable2)); + InternalAddVerbTable (&VerbTableEntries, VerbTableArray, (VOID *) (UIN= TN) PcdGet32 (PcdCommonHdaVerbTable3)); + } + + *VerbTableEntryNum =3D VerbTableEntries; + + VerbTablePtr =3D (UINT32 *) AllocateZeroPool (sizeof (UINT32) * VerbTabl= eEntries); + CopyMem (VerbTablePtr, VerbTableArray, sizeof (UINT32) * VerbTableEntrie= s); + *HdaVerbTablePtr =3D (UINT32) VerbTablePtr; +} + +/** + HDA VerbTable init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +HdaVerbTableInit ( + IN UINT16 BoardId + ) +{ + HDAUDIO_VERB_TABLE *VerbTable; + HDAUDIO_VERB_TABLE *VerbTable2; + + VerbTable =3D NULL; + VerbTable2 =3D NULL; + + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + VerbTable =3D &WhlHdaVerbTableAlc700; + break; + + default: + DEBUG ((DEBUG_INFO, "HDA: Init default verb tables (Realtek ALC700 a= nd ALC701)\n")); + VerbTable =3D &HdaVerbTableAlc700; + VerbTable2 =3D &HdaVerbTableAlc701; + break; + } + + PcdSet32S (PcdHdaVerbTable, (UINT32) VerbTable); + PcdSet32S (PcdHdaVerbTable2, (UINT32) VerbTable2); + PcdSet32S (PcdDisplayAudioHdaVerbTable, (UINT32) &HdaVerbTableDisplayAud= io); + + // Codecs - Realtek ALC700, ALC701, ALC274 (external - connected via HDA= header) + PcdSet32S (PcdCommonHdaVerbTable1, (UINT32) &HdaVerbTableAlc700); + PcdSet32S (PcdCommonHdaVerbTable2, (UINT32) &HdaVerbTableAlc701); + PcdSet32S (PcdCommonHdaVerbTable3, (UINT32) &HdaVerbTableAlc274); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib= /PeiI2cAccessLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cA= ccessLib/PeiI2cAccessLib.c new file mode 100644 index 0000000000..70f531daca --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiI2cAccessLib/PeiI2c= AccessLib.c @@ -0,0 +1,115 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +EFI_STATUS +I2cWriteRead ( + IN UINTN MmioBase, + IN UINT8 SlaveAddress, + IN UINT8 WriteLength, + IN UINT8 *WriteBuffer, + IN UINT8 ReadLength, + IN UINT8 *ReadBuffer, + IN UINT64 TimeBudget + //TODO: add Speed parameter + ) +{ + UINT8 ReadsNeeded =3D ReadLength; + UINT64 CutOffTime; + + if ((WriteLength =3D=3D 0 && ReadLength =3D=3D 0) || + (WriteLength !=3D 0 && WriteBuffer =3D=3D NULL) || + (ReadLength !=3D 0 && ReadBuffer =3D=3D NULL) ) { + DEBUG ((DEBUG_ERROR, "I2cWR Invalid Parameters\n")); + return EFI_INVALID_PARAMETER; + } + + // + // Sanity checks to verify the I2C controller is alive + // Conveniently, ICON register's values of 0 or FFFFFFFF indicate + // I2c controller is out-of-order: either disabled, in D3 or in reset. + // + if (MmioRead32(MmioBase+R_IC_CON) =3D=3D 0xFFFFFFFF || MmioRead32(MmioBa= se+R_IC_CON) =3D=3D 0x0) { + DEBUG ((DEBUG_ERROR, "I2cWR Device Error\n")); + return EFI_DEVICE_ERROR; + } + + MmioWrite32(MmioBase+R_IC_ENABLE, 0x0); + MmioRead32(MmioBase+0x40); + MmioRead32(MmioBase+R_IC_CLR_TX_ABRT); + MmioWrite32(MmioBase+R_IC_SDA_HOLD, 0x001C001C); + // + // Set I2C Bus Speed at 400 kHz for GPIO Expander + // + MmioWrite32(MmioBase + R_IC_FS_SCL_HCNT, 128); + MmioWrite32(MmioBase + R_IC_FS_SCL_LCNT, 160); + MmioWrite32(MmioBase + R_IC_TAR, SlaveAddress); + MmioWrite32(MmioBase + R_IC_CON, B_IC_MASTER_MODE | V_IC_SPEED_FAST | B_= IC_RESTART_EN | B_IC_SLAVE_DISABLE ); + MmioWrite32(MmioBase+R_IC_ENABLE, 0x1); + CutOffTime =3D AsmReadTsc() + TimeBudget; + + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D0 ) { + if (AsmReadTsc() > CutOffTime) { + DEBUG ((DEBUG_ERROR, "I2cWR timeout\n")); + return EFI_TIMEOUT; + } + } + + while(1) { + if(MmioRead32(MmioBase+R_IC_INTR_STAT) & B_IC_INTR_TX_ABRT) { + DEBUG ((DEBUG_ERROR, "I2cWR Transfer aborted, reason =3D 0x%08x\n",M= mioRead32(MmioBase+R_IC_TX_ABRT_SOURCE))); + MmioRead32(MmioBase+R_IC_CLR_TX_ABRT); + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} + return EFI_DEVICE_ERROR; + } + if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_TFNF) { + if (WriteLength > 1) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer); + WriteBuffer++; + WriteLength--; + } else if (WriteLength=3D=3D1 && ReadLength !=3D 0) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer); + WriteBuffer++; + WriteLength--; + } else if (WriteLength=3D=3D1 && ReadLength =3D=3D 0) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, *WriteBuffer | B_IC_CMD_STOP); + WriteBuffer++; + WriteLength--; + } else if (ReadLength > 1) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ); + ReadLength--; + } else if (ReadLength =3D=3D 1) { + MmioWrite32(MmioBase+R_IC_DATA_CMD, B_IC_CMD_READ|B_IC_CMD_STOP); + ReadLength--; + } + } + + if (ReadsNeeded) { + if (MmioRead32(MmioBase+R_IC_STATUS) & B_IC_STATUS_RFNE) { + *ReadBuffer =3D (UINT8)MmioRead32(MmioBase+R_IC_DATA_CMD); + ReadBuffer++; + ReadsNeeded--; + } + } + if (WriteLength=3D=3D0 && ReadsNeeded=3D=3D0 && !(MmioRead32(MmioBase+= R_IC_STATUS)&B_IC_STATUS_ACTIVITY)) { + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} + DEBUG ((DEBUG_INFO, "I2cWR success\n")); + return EFI_SUCCESS; + } + if (AsmReadTsc() > CutOffTime) { + MmioAnd32(MmioBase+R_IC_ENABLE, 0xFFFFFFFE); + while ( (MmioRead32(MmioBase+R_IC_ENABLE_STATUS) & 1)=3D=3D1 ) {} + DEBUG ((DEBUG_ERROR, "I2cWR wrong ENST value\n")); + return EFI_TIMEOUT; + } + + } +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeCpuPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/DxePolicyUpdateLib/DxeCpuPolicyUpdate.c new file mode 100644 index 0000000000..7b9a32b3f5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeCpuPolicyUpdate.c @@ -0,0 +1,88 @@ +/** @file + This file is the library for CPU DXE Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + This function prints the CPU DXE phase policy. + + @param[in] DxeCpuPolicy - CPU DXE Policy protocol +**/ +VOID +CpuDxePrintPolicyProtocol ( + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ) +{ + DEBUG_CODE_BEGIN (); + DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print B= EGIN -----------------\n")); + DEBUG ((DEBUG_INFO, "Revision : %x\n", DxeCpuPolicy->Revision)); + ASSERT (DxeCpuPolicy->Revision =3D=3D DXE_CPU_POLICY_PROTOCOL_REVISION); + DEBUG ((DEBUG_INFO, "\n------------------------ CPU_DXE_CONFIG ---------= --------\n")); + DEBUG ((DEBUG_INFO, "EnableDts : %x\n", DxeCpuPolicy->EnableDts)); + DEBUG ((DEBUG_INFO, "\n------------------------ CPU Policy (DXE) print E= ND -----------------\n")); + DEBUG_CODE_END (); +} + +/** + Get data for CPU policy from setup options. + + @param[in] DxeCpuPolicy The pointer to get CPU Policy proto= col instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSiCpuPolicy ( + IN OUT DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ) +{ + return EFI_SUCCESS; +} + +/** + CpuInstallPolicyProtocol installs CPU Policy. + While installed, RC assumes the Policy is ready and finalized. So please= update and override + any setting before calling this function. + + @param[in] ImageHandle Image handle of this driver. + @param[in] DxeCpuPolicy The pointer to CPU Policy Protocol= instance + + @retval EFI_SUCCESS The policy is installed. + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer + +**/ +EFI_STATUS +EFIAPI +CpuInstallPolicyProtocol ( + IN EFI_HANDLE ImageHandle, + IN DXE_CPU_POLICY_PROTOCOL *DxeCpuPolicy + ) +{ + EFI_STATUS Status; + + /// + /// Print CPU DXE Policy + /// + CpuDxePrintPolicyProtocol(DxeCpuPolicy); + + /// + /// Install the DXE_CPU_POLICY_PROTOCOL interface + /// + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gDxeCpuPolicyProtocolGuid, + DxeCpuPolicy, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeMePolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/DxePolicyUpdateLib/DxeMePolicyUpdate.c new file mode 100644 index 0000000000..863df3328c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeMePolicyUpdate.c @@ -0,0 +1,105 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "DxeMePolicyUpdate.h" + +// +// Record version +// +#define RECORD_REVISION_1 0x01 +#define MAX_FW_UPDATE_BIOS_SELECTIONS 2 + +// +// Function implementations executed during policy initialization phase +// + +/** + Update the ME Policy Library + + @param[in, out] DxeMePolicy The pointer to get ME Policy proto= col instance + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_UNSUPPORTED The chipset is unsupported by this= driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to in= itialize the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnorma= lly. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeMePolicy ( + IN OUT ME_POLICY_PROTOCOL *DxeMePolicy + ) +{ + EFI_STATUS Status; + EFI_EVENT EndOfDxeEvent; + + DEBUG ((DEBUG_INFO, "UpdateDxeMePolicy\n")); + UpdateMePolicyFromSetup (DxeMePolicy); + UpdateMePolicyFromMeSetup (DxeMePolicy); + + // + // Register End of DXE event + // + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + UpdateMeSetupCallback, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + +/** + Update ME Policy while MePlatformProtocol is installed. + + @param[in] MePolicyInstance Instance of ME Policy Protocol + +**/ +VOID +UpdateMePolicyFromMeSetup ( + IN ME_POLICY_PROTOCOL *MePolicyInstance + ) +{ + +} + +/** + Update ME Policy if Setup variable exists. + + @param[in, out] MePolicyInstance Instance of ME Policy Protocol + +**/ +VOID +UpdateMePolicyFromSetup ( + IN OUT ME_POLICY_PROTOCOL *MePolicyInstance + ) +{ + +} + +/** + Functions performs HECI exchange with FW to update MePolicy settings. + + @param[in] Event A pointer to the Event that triggered the callb= ack. + @param[in] Context A pointer to private data registered with the c= allback function. + +**/ +VOID +EFIAPI +UpdateMeSetupCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + gBS->CloseEvent (Event); + + return; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxePchPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/DxePolicyUpdateLib/DxePchPolicyUpdate.c new file mode 100644 index 0000000000..7945986aaa --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxePchPolicyUpdate.c @@ -0,0 +1,39 @@ +/** @file + This file is the library for PCH DXE Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Get data for PCH policy from setup options. + + @param[in] PchPolicy The pointer to get PCH Policy proto= col instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxePchPolicy ( + IN OUT PCH_POLICY_PROTOCOL *PchPolicy + ) +{ + EFI_STATUS Status; + PCH_HDAUDIO_DXE_CONFIG *HdAudioDxeConfig; + + Status =3D GetConfigBlock ((VOID *)PchPolicy, &gHdAudioDxeConfigGuid, (V= OID *)&HdAudioDxeConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolic= yUpdateLib/DxeSaPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/DxePolicyUpdateLib/DxeSaPolicyUpdate.c new file mode 100644 index 0000000000..af4c76bcd0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/DxePolicyUpdate= Lib/DxeSaPolicyUpdate.c @@ -0,0 +1,57 @@ +/** @file + This file is the library for SA DXE Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + Get data for platform policy from setup options. + + @param[in] SaPolicy The pointer to get SA Policy protoc= ol instance + + @retval EFI_SUCCESS Operation success. + +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicy ( + IN OUT SA_POLICY_PROTOCOL *SaPolicy + ) +{ + EFI_STATUS Status; + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig; + PCIE_DXE_CONFIG *PcieDxeConfig; + MISC_DXE_CONFIG *MiscDxeConfig; + MEMORY_DXE_CONFIG *MemoryDxeConfig; + + GraphicsDxeConfig =3D NULL; + PcieDxeConfig =3D NULL; + MiscDxeConfig =3D NULL; + MemoryDxeConfig =3D NULL; + // + // Get requisite IP Config Blocks which needs to be used here + // + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gGraphicsDxeConfigGuid, (V= OID *)&GraphicsDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMiscDxeConfigGuid, (VOID = *)&MiscDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gPcieDxeConfigGuid, (VOID = *)&PcieDxeConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *)SaPolicy, &gMemoryDxeConfigGuid, (VOI= D *)&MemoryDxeConfig); + ASSERT_EFI_ERROR (Status); + + PcieDxeConfig->PegAspmL0s[0] =3D 3; + PcieDxeConfig->PegAspmL0s[1] =3D 3; + PcieDxeConfig->PegAspmL0s[2] =3D 3; + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiPolicyInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Li= brary/PeiPolicyInitLib/PeiPolicyInit.c new file mode 100644 index 0000000000..93be38a832 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiPolicyInit.c @@ -0,0 +1,65 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyInit.h" + +/** + Initialize Intel PEI Platform Policy + + @param[in] PeiServices General purpose services available to = every PEIM. + @param[in] FirmwareConfiguration It uses to skip specific policy init t= hat depends + on the 'FirmwareConfiguration' varaibl= e. +**/ +VOID +EFIAPI +PeiPolicyInit ( + IN UINT8 FirmwareConfiguration + ) +{ + EFI_STATUS Status; + SI_POLICY_PPI *SiPolicyPpi; + + // + // Call SiCreateConfigBlocks to initialize Silicon Policy structure + // and get all Intel default policy settings. + // + Status =3D SiCreateConfigBlocks (&SiPolicyPpi); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return; + } + + if (PcdGetBool (PcdDumpDefaultSiliconPolicy)) { + DEBUG ((DEBUG_INFO, "Dump Default Silicon Policy...\n")); + DumpSiPolicy (SiPolicyPpi); + } + + // + // Update policy by board configuration + // + UpdatePeiSiPolicyBoardConfig (SiPolicyPpi); + UpdatePeiPchPolicyBoardConfig (SiPolicyPpi); + UpdatePeiSaPolicyBoardConfig (SiPolicyPpi); + UpdatePeiCpuPolicyBoardConfig (SiPolicyPpi); + UpdatePeiMePolicyBoardConfig (SiPolicyPpi); + + UpdatePeiSiPolicy(SiPolicyPpi); + UpdatePeiPchPolicy(SiPolicyPpi); + UpdatePeiSaPolicy(SiPolicyPpi); + UpdatePeiCpuPolicy(SiPolicyPpi); + UpdatePeiMePolicy(SiPolicyPpi); + + // + // Install SiPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D SiInstallPolicyPpi (SiPolicyPpi); + ASSERT_EFI_ERROR (Status); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiPolicyInitPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyInitLib/PeiPolicyInitPreMem.c new file mode 100644 index 0000000000..9f8014b72a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiPolicyInitPreMem.c @@ -0,0 +1,60 @@ +/** @file + This file is SampleCode for Intel PEI Platform Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyInit.h" + +/** + Initialize Intel PEI Platform Policy + + @param[in] FirmwareConfiguration It uses to skip specific policy init = that depends + on the 'FirmwareConfiguration' varaib= le. +**/ +VOID +EFIAPI +PeiPolicyInitPreMem ( + IN UINT8 FirmwareConfiguration + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Start in Pre-Memo= ry...\n")); + // + // Call SiCreatePreMemConfigBlocks to initialize platform policy structu= re + // and get all intel default policy settings. + // + Status =3D SiCreatePreMemConfigBlocks (&SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + // + // Update policy by board configuration + // + UpdatePeiPchPolicyBoardConfigPreMem (SiPreMemPolicyPpi); + UpdatePeiMePolicyBoardConfigPreMem (SiPreMemPolicyPpi); + UpdatePeiSaPolicyBoardConfigPreMem (SiPreMemPolicyPpi); + UpdatePeiCpuPolicyBoardConfigPreMem (SiPreMemPolicyPpi); + + // + // Update and override all platform related and customized settings belo= w. + // + UpdatePeiPchPolicyPreMem (SiPreMemPolicyPpi); + UpdatePeiMePolicyPreMem (SiPreMemPolicyPpi); + UpdatePeiSaPolicyPreMem (SiPreMemPolicyPpi); + UpdatePeiCpuPolicyPreMem (SiPreMemPolicyPpi); + + // + // Install SiPreMemPolicyPpi. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D SiPreMemInstallPolicyPpi (SiPreMemPolicyPpi); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memor= y\n")); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yInitLib/PeiSaPolicyInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/= Library/PeiPolicyInitLib/PeiSaPolicyInit.c new file mode 100644 index 0000000000..922bcd135f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyInitLi= b/PeiSaPolicyInit.c @@ -0,0 +1,114 @@ +/** @file + This file is SampleCode for Intel SA PEI Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyInit.h" + + +/** + PcieCardResetWorkAround performs PCIe Card reset on root port + + @param[in out] SiPreMemPolicyPpi SI_PREMEM_POLICY_PPI + + @retval EFI_SUCCESS The policy is installed and initialized. +**/ +EFI_STATUS + PcieCardResetWorkAround ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData; + + Status =3D GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSaMiscPeiPreMemCo= nfigGuid, (VOID *)&MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *)SiPreMemPolicyPpi, &gSwitchableGraphic= sConfigGuid, (VOID *)&SgGpioData); + ASSERT_EFI_ERROR(Status); + + if (SgGpioData->SaRtd3Pcie0Gpio.GpioSupport !=3D NotSupported) { + /// + /// dGPU is present. + /// If PCIe Mode or SG Muxless + /// Power on MXM + /// Configure GPIOs to drive MXM in PCIe mode or SG Muxle= ss + /// else + /// Do Nothing + /// + if ((MiscPeiPreMemConfig->SgMode =3D=3D SgModeMuxless) || + (MiscPeiPreMemConfig->SgMode =3D=3D SgModeDgpu)) { + DEBUG((DEBUG_INFO, "Configure GPIOs for driving the dGPU.\n")); + /// + /// Drive DGPU HOLD RST Enable to make sure we hold reset + /// + PcieGpioWrite ( + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo, + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active, + GP_ENABLE + ); + /// + /// wait 100ms + /// + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STAL= L_ONE_MILLI_SECOND); + + /// + /// Drive DGPU PWR EN to Power On MXM + /// + PcieGpioWrite ( + SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.GpioNo, + SgGpioData->SaRtd3Pcie0Gpio.PwrEnable.Active, + GP_ENABLE + ); + /// + /// wait 300ms + /// + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterPwrEn) * STALL_ON= E_MILLI_SECOND); + + /// + /// Drive DGPU HOLD RST Disabled to remove reset + /// + PcieGpioWrite ( + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.GpioNo, + SgGpioData->SaRtd3Pcie0Gpio.HoldRst.Active, + GP_DISABLE + ); + /// + /// wait 100ms + /// + MicroSecondDelay((MiscPeiPreMemConfig->SgDelayAfterHoldReset) * STAL= L_ONE_MILLI_SECOND); + } + } + return EFI_SUCCESS; +} + +/** + PCIe GPIO Write + + @param[in] Gpio - GPIO Number + @param[in] Active - GPIO Active Information; High/Low + @param[in] Level - Write GPIO value (0/1) + +**/ +VOID +PcieGpioWrite ( + IN UINT32 Gpio, + IN BOOLEAN Active, + IN BOOLEAN Level + ) +{ + EFI_STATUS Status; + + if (Active =3D=3D 0) { + Level =3D (~Level) & 0x1; + } + Status =3D GpioSetOutputValue(Gpio, (UINT32)Level); + if (Status !=3D EFI_SUCCESS) { + return; + } +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiCpuPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdate.c new file mode 100644 index 0000000000..144480a83d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiCpuPolicyUpdate.c @@ -0,0 +1,80 @@ +/** @file + CPU PEI Policy Update & initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyUpdate.h" +#include +#include +#include +#include + +/** + This function performs CPU PEI Policy initialization. + + @param[in] SiPolicyPpi The SI Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initial= ize the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + CPU_CONFIG *CpuConfig; + CPU_POWER_MGMT_BASIC_CONFIG *CpuPowerMgmtBasicConfig; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_POWER_MGMT_CUSTOM_CONFIG *CpuPowerMgmtCustomConfig; + CPU_POWER_MGMT_TEST_CONFIG *CpuPowerMgmtTestConfig; + CPU_TEST_CONFIG *CpuTestConfig; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuPowerMgmtBasicConf= igGuid, (VOID *) &CpuPowerMgmtBasicConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuPowerMgmtCustomConfi= gGuid, (VOID *)&CpuPowerMgmtCustomConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuTestConfigGuid, (VOI= D *)&CpuTestConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gCpuPowerMgmtTestConfigG= uid, (VOID *)&CpuPowerMgmtTestConfig); + ASSERT_EFI_ERROR(Status); + + // + // Init Power Management Policy Variables + // + CpuPowerMgmtBasicConfig->HwpInterruptControl =3D 1; + CpuPowerMgmtCustomConfig->CustomRatioTable.MaxRatio =3D 0x4; + CpuPowerMgmtBasicConfig->OneCoreRatioLimit =3D 0x22; + CpuPowerMgmtBasicConfig->TwoCoreRatioLimit =3D 0x22; + CpuPowerMgmtBasicConfig->ThreeCoreRatioLimit =3D 0x22; + CpuPowerMgmtBasicConfig->FourCoreRatioLimit =3D 0x22; + CpuPowerMgmtBasicConfig->FiveCoreRatioLimit =3D 0; + CpuPowerMgmtBasicConfig->SixCoreRatioLimit =3D 0; + CpuPowerMgmtBasicConfig->SevenCoreRatioLimit =3D 0; + CpuPowerMgmtBasicConfig->EightCoreRatioLimit =3D 0; + CpuPowerMgmtBasicConfig->Hwp =3D 0x1; + CpuTestConfig->CpuWakeUpTimer =3D 1; + CpuPowerMgmtTestConfig->AutoThermalReporting =3D 0; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiCpuPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/Policy/Library/PeiPolicyUpdateLib/PeiCpuPolicyUpdatePreMem.c new file mode 100644 index 0000000000..bce02a9c5a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiCpuPolicyUpdatePreMem.c @@ -0,0 +1,108 @@ +/** @file + This file is SampleCode of the library for Intel CPU PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiCpuPolicyUpdate.h" +#include +#include +#include +#include +#include + +/** + Check on the processor if SGX is supported. + + @retval True if SGX supported or FALSE if not +**/ +BOOLEAN +IsSgxCapSupported ( + VOID + ) +{ + EFI_CPUID_REGISTER CpuidRegs; + + /// + /// Processor support SGX feature by reading CPUID.(EAX=3D7,ECX=3D0):EBX= [2] + /// + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, &CpuidRegs.RegEa= x,&CpuidRegs.RegEbx,&CpuidRegs.RegEcx,&CpuidRegs.RegEdx); + + /// + /// SGX feature is supported only on WHL and later, + /// with CPUID.(EAX=3D7,ECX=3D0):EBX[2]=3D1 + /// PRMRR configuration enabled, MSR IA32_MTRRCAP (FEh) [12] =3D=3D 1 + /// + if ((CpuidRegs.RegEbx & BIT2) && (AsmReadMsr64 (MSR_IA32_MTRRCAP) & BIT1= 2)) { + return TRUE; + } + + return FALSE; +} + +/** + This function performs CPU PEI Policy initialization in Pre-memory. + + @param[in] SiPreMemPolicyPpi The SI Pre-Mem Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initial= ize the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig; + CPU_OVERCLOCKING_PREMEM_CONFIG *CpuOverClockingPreMemConfig; + UINT32 PchSpiBar0; + UINT32 MaxLogicProcessors; + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre= MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuOverclocking= PreMemConfigGuid, (VOID *) &CpuOverClockingPreMemConfig); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "UpdatePeiCpuPolicyPreMem Start\n")); + + // + // Get current boot mode + // + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + SpiServiceInit (); + + PchSpiBar0 =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_SPI, + PCI_FUNCTION_NUMBER_PCH_SPI, + R_SPI_CFG_BAR0 + )); + PchSpiBar0 &=3D ~(B_SPI_CFG_BAR0_MASK); + + if (PchSpiBar0 =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "ERROR : PchSpiBar0 is invalid!\n")); + ASSERT (FALSE); + } + + CpuConfigLibPreMemConfig->PeciC10Reset =3D 0; + CpuConfigLibPreMemConfig->CpuRatio =3D 0; + /// + /// Set PcdCpuMaxLogicalProcessorNumber to max number of logical process= ors enabled + /// Read MSR_CORE_THREAD_COUNT (0x35) to check the total active Threads + /// + MaxLogicProcessors =3D (UINT32) (AsmReadMsr64 (MSR_CORE_THREAD_COUNT) & = B_THREAD_COUNT_MASK); + DEBUG ((DEBUG_INFO, "MaxLogicProcessors =3D %d\n", MaxLogicProcessors)); + PcdSet32S (PcdCpuMaxLogicalProcessorNumber, MaxLogicProcessors); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiMePolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdate.c new file mode 100644 index 0000000000..e557f04971 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiMePolicyUpdate.c @@ -0,0 +1,49 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiMePolicyUpdate.h" +#include +#include +#include +#include +#include + +/** + Update the ME Policy Library + + @param[in, out] SiPolicyPpi The pointer to SiPolicyPpi + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +UpdatePeiMePolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + ME_PEI_CONFIG *MePeiConfig; + + DEBUG ((DEBUG_INFO, "UpdatePeiMePolicy\n")); + + Status =3D EFI_SUCCESS; + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI= D *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + if (!PmcIsRtcBatteryGood ()) { + // + // For non coin battery design, this can be skipped. + // + MePeiConfig->MeUnconfigOnRtcClear =3D 2; + } + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiMePolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoardP= kg/Policy/Library/PeiPolicyUpdateLib/PeiMePolicyUpdatePreMem.c new file mode 100644 index 0000000000..de9849b807 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiMePolicyUpdatePreMem.c @@ -0,0 +1,32 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiMePolicyUpdate.h" +#include +#include +#include + +/** + Update the ME Policy Library + + @param[in] SiPreMemPolicyPpi The pointer to SiPreMemPolicyPpi + + @retval EFI_SUCCESS Update complete. +**/ +EFI_STATUS +UpdatePeiMePolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "UpdatePeiMePolicyPreMem\n")); + + Status =3D EFI_SUCCESS; + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPchPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Po= licy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c new file mode 100644 index 0000000000..3e44c6cc29 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPchPolicyUpdate.c @@ -0,0 +1,523 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +UpdatePcieClockInfo ( + PCH_PCIE_CONFIG *PcieRpConfig, + UINTN Index, + UINT64 Data + ) +{ + PCD64_BLOB Pcd64; + + Pcd64.Blob =3D Data; + DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Suppor= ted %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupport= ed)); + + PcieRpConfig->PcieClock[Index].Usage =3D (UINT8)Pcd64.PcieClock.ClockUsa= ge; + if (Pcd64.PcieClock.ClkReqSupported) { + PcieRpConfig->PcieClock[Index].ClkReq =3D (UINT8)Index; + } else { + PcieRpConfig->PcieClock[Index].ClkReq =3D 0xFF; + } +} + +/** + This is helper function for getting I2C Pads Internal Termination settin= gs from Pcd + + @param[in] Index I2C Controller Index +**/ +UINT8 +GetSerialIoI2cPadsTerminationFromPcd ( + IN UINT8 Index +) +{ + switch (Index) { + case 0: + return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm); + case 1: + return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm); + case 2: + return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm); + case 3: + return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm); + case 4: + return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm); + case 5: + return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm); + default: + ASSERT (FALSE); // Invalid I2C Controller Index + } + return 0; +} +/** + This is a helper function for updating USB Policy according to Blob data + + @param[in] UsbConfig Pointer to USB_CONFIG data buffer + @param[in] PortIndex USB Port index + @param[in] Data32 Blob containing USB2 Afe (PCD32_BLOB) data +**/ +VOID +UpdateUsb20AfePolicy ( + IN USB_CONFIG *UsbConfig, + IN UINT8 PortIndex, + UINT32 Data32 +) +{ + PCD32_BLOB Pcd32; + Pcd32.Blob =3D Data32; + + if (PortIndex < MAX_USB2_PORTS && Pcd32.Info.Petxiset !=3D 0) { + UsbConfig->PortUsb20[PortIndex].Afe.Petxiset =3D Pcd32.Info.Petxis= et; + UsbConfig->PortUsb20[PortIndex].Afe.Txiset =3D Pcd32.Info.Txiset; + UsbConfig->PortUsb20[PortIndex].Afe.Predeemp =3D Pcd32.Info.Predee= mp; + UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit =3D Pcd32.Info.Pehalf= bit; + } +} + +/** + This function updates USB Policy per port OC Pin number + + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer + @param[in] PortIndex USB Port index + @param[in] Pin OverCurrent pin number +**/ +VOID +UpdateUsb20OverCurrentPolicy ( + IN USB_CONFIG *UsbConfig, + IN UINT8 PortIndex, + UINT8 Pin +) +{ + if (PortIndex < MAX_USB2_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin = =3D=3D UsbOverCurrentPinSkip))) { + UsbConfig->PortUsb20[PortIndex].OverCurrentPin =3D Pin; + } else { + if (PortIndex >=3D MAX_USB2_PORTS) { + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number= %d is not a valid USB2 port number\n", PortIndex)); + } else { + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurr= ent pin specified USB2 port %d\n", PortIndex)); + } + } +} + +/** + This function updates USB Policy per port OC Pin number + + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer + @param[in] PortIndex USB Port index + @param[in] Pin OverCurrent pin number +**/ +VOID +UpdateUsb30OverCurrentPolicy ( + IN USB_CONFIG *UsbConfig, + IN UINT8 PortIndex, + UINT8 Pin +) +{ + if (PortIndex < MAX_USB3_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin = =3D=3D UsbOverCurrentPinSkip))) { + UsbConfig->PortUsb30[PortIndex].OverCurrentPin =3D Pin; + } else { + if (PortIndex >=3D MAX_USB2_PORTS) { + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number= %d is not a valid USB3 port number\n", PortIndex)); + } else { + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurr= ent pin specified USB3 port %d\n", PortIndex)); + } + } +} + +/** + This function performs PCH USB Platform Policy initialization + + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer + @param[in] PchSetup Pointer to PCH_SETUP data buffer +**/ +VOID +UpdatePchUsbConfig ( + IN USB_CONFIG *UsbConfig + ) +{ + UINTN PortIndex; + + UsbConfig->OverCurrentEnable =3D TRUE; + + for (PortIndex =3D 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortI= ndex++) { + UsbConfig->PortUsb20[PortIndex].Enable =3D TRUE; + } + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex= ++) { + UsbConfig->PortUsb30[PortIndex].Enable =3D TRUE; + } + + UsbConfig->XdciConfig.Enable =3D FALSE; + + + // + // USB2 AFE settings. + // + UpdateUsb20AfePolicy (UsbConfig, 0, PcdGet32 (PcdUsb20Port0Afe)); + UpdateUsb20AfePolicy (UsbConfig, 1, PcdGet32 (PcdUsb20Port1Afe)); + UpdateUsb20AfePolicy (UsbConfig, 2, PcdGet32 (PcdUsb20Port2Afe)); + UpdateUsb20AfePolicy (UsbConfig, 3, PcdGet32 (PcdUsb20Port3Afe)); + UpdateUsb20AfePolicy (UsbConfig, 4, PcdGet32 (PcdUsb20Port4Afe)); + UpdateUsb20AfePolicy (UsbConfig, 5, PcdGet32 (PcdUsb20Port5Afe)); + UpdateUsb20AfePolicy (UsbConfig, 6, PcdGet32 (PcdUsb20Port6Afe)); + UpdateUsb20AfePolicy (UsbConfig, 7, PcdGet32 (PcdUsb20Port7Afe)); + UpdateUsb20AfePolicy (UsbConfig, 8, PcdGet32 (PcdUsb20Port8Afe)); + UpdateUsb20AfePolicy (UsbConfig, 9, PcdGet32 (PcdUsb20Port9Afe)); + UpdateUsb20AfePolicy (UsbConfig,10, PcdGet32 (PcdUsb20Port10Afe)); + UpdateUsb20AfePolicy (UsbConfig,11, PcdGet32 (PcdUsb20Port11Afe)); + UpdateUsb20AfePolicy (UsbConfig,12, PcdGet32 (PcdUsb20Port12Afe)); + UpdateUsb20AfePolicy (UsbConfig,13, PcdGet32 (PcdUsb20Port13Afe)); + UpdateUsb20AfePolicy (UsbConfig,14, PcdGet32 (PcdUsb20Port14Afe)); + UpdateUsb20AfePolicy (UsbConfig,15, PcdGet32 (PcdUsb20Port15Afe)); + + // + // Platform Board programming per the layout of each port. + // + UpdateUsb20OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrent= PinPort0)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrent= PinPort1)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrent= PinPort2)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrent= PinPort3)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrent= PinPort4)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrent= PinPort5)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrent= PinPort6)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrent= PinPort7)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrent= PinPort8)); + UpdateUsb20OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrent= PinPort9)); + UpdateUsb20OverCurrentPolicy (UsbConfig,10, PcdGet8 (PcdUsb20OverCurrent= PinPort10)); + UpdateUsb20OverCurrentPolicy (UsbConfig,11, PcdGet8 (PcdUsb20OverCurrent= PinPort11)); + UpdateUsb20OverCurrentPolicy (UsbConfig,12, PcdGet8 (PcdUsb20OverCurrent= PinPort12)); + UpdateUsb20OverCurrentPolicy (UsbConfig,13, PcdGet8 (PcdUsb20OverCurrent= PinPort13)); + UpdateUsb20OverCurrentPolicy (UsbConfig,14, PcdGet8 (PcdUsb20OverCurrent= PinPort14)); + UpdateUsb20OverCurrentPolicy (UsbConfig,15, PcdGet8 (PcdUsb20OverCurrent= PinPort15)); + + UpdateUsb30OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrent= PinPort0)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrent= PinPort1)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrent= PinPort2)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrent= PinPort3)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrent= PinPort4)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrent= PinPort5)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrent= PinPort6)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrent= PinPort7)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrent= PinPort8)); + UpdateUsb30OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrent= PinPort9)); + +} + +/** + Return if input ImageGuid belongs to system FMP GUID list. + + @param[in] ImageGuid A pointer to GUID + + @retval TRUE ImageGuid is in the list of PcdSystemFmpCapsuleImageTypeId= Guid + @retval FALSE ImageGuid is not in the list of PcdSystemFmpCapsuleImageTy= peIdGuid +**/ +BOOLEAN +IsSystemFmpGuid ( + IN GUID *ImageGuid + ) +{ + GUID *Guid; + UINTN Count; + UINTN Index; + + Guid =3D PcdGetPtr (PcdSystemFmpCapsuleImageTypeIdGuid); + Count =3D PcdGetSize (PcdSystemFmpCapsuleImageTypeIdGuid) / sizeof (GUID= ); + + for (Index =3D 0; Index < Count; Index++, Guid++) { + if (CompareGuid (ImageGuid, Guid)) { + return TRUE; + } + } + + return FALSE; +} + +/** + This function performs PCH PEI Policy initialization. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicy ( + IN OUT SI_POLICY_PPI *SiPolicy + ) +{ + EFI_STATUS Status; + UINT8 Index; + DMI_HW_WIDTH_CONTROL *DmiHaAWC; + UINT16 LpcDid; + PCH_GENERAL_CONFIG *PchGeneralConfig; + PCH_PCIE_CONFIG *PcieRpConfig; + PCH_SATA_CONFIG *SataConfig; + PCH_IOAPIC_CONFIG *IoApicConfig; + PCH_DMI_CONFIG *DmiConfig; + PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig; + PCH_HDAUDIO_CONFIG *HdAudioConfig; + PCH_INTERRUPT_CONFIG *InterruptConfig; + PCH_ISH_CONFIG *IshConfig; + PCH_LAN_CONFIG *LanConfig; + PCH_LOCK_DOWN_CONFIG *LockDownConfig; + PCH_PM_CONFIG *PmConfig; + PCH_SCS_CONFIG *ScsConfig; + PCH_SERIAL_IO_CONFIG *SerialIoConfig; + PCH_LPC_SIRQ_CONFIG *SerialIrqConfig; + PCH_THERMAL_CONFIG *ThermalConfig; + USB_CONFIG *UsbConfig; + PCH_ESPI_CONFIG *EspiConfig; + PCH_CNVI_CONFIG *CnviConfig; + PEI_TBT_POLICY *PeiTbtPolicy; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (V= OID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID = *) &PcieRpConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *)= &SataConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID = *) &IoApicConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) = &DmiConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGui= d, (VOID *) &FlashProtectionConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID= *) &HdAudioConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VO= ID *) &InterruptConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) = &IshConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) = &LanConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOI= D *) &LockDownConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &= PmConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) = &ScsConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOI= D *) &SerialIoConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VO= ID *) &SerialIrqConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID= *) &ThermalConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) = &UsbConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *)= &EspiConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *)= &CnviConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **) &SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + + PeiTbtPolicy =3D NULL; + LpcDid =3D PchGetLpcDid (); + + DmiConfig->PwrOptEnable =3D TRUE; + PmConfig->PchSlpS3MinAssert =3D 0; + PmConfig->PchSlpS4MinAssert =3D 0; + PmConfig->PchSlpSusMinAssert =3D 0; + PmConfig->PchSlpAMinAssert =3D 0; + + SataConfig->ThermalThrottling.P1T3M =3D 3; + SataConfig->ThermalThrottling.P1T2M =3D 2; + SataConfig->ThermalThrottling.P1T1M =3D 1; + SataConfig->ThermalThrottling.P0T3M =3D 3; + SataConfig->ThermalThrottling.P0T2M =3D 2; + SataConfig->ThermalThrottling.P0T1M =3D 1; + + UpdatePcieClockInfo (PcieRpConfig, 0, PcdGet64 (PcdPcieClock0)); + UpdatePcieClockInfo (PcieRpConfig, 1, PcdGet64 (PcdPcieClock1)); + UpdatePcieClockInfo (PcieRpConfig, 2, PcdGet64 (PcdPcieClock2)); + UpdatePcieClockInfo (PcieRpConfig, 3, PcdGet64 (PcdPcieClock3)); + UpdatePcieClockInfo (PcieRpConfig, 4, PcdGet64 (PcdPcieClock4)); + UpdatePcieClockInfo (PcieRpConfig, 5, PcdGet64 (PcdPcieClock5)); + UpdatePcieClockInfo (PcieRpConfig, 6, PcdGet64 (PcdPcieClock6)); + UpdatePcieClockInfo (PcieRpConfig, 7, PcdGet64 (PcdPcieClock7)); + UpdatePcieClockInfo (PcieRpConfig, 8, PcdGet64 (PcdPcieClock8)); + UpdatePcieClockInfo (PcieRpConfig, 9, PcdGet64 (PcdPcieClock9)); + UpdatePcieClockInfo (PcieRpConfig, 10, PcdGet64 (PcdPcieClock10)); + UpdatePcieClockInfo (PcieRpConfig, 11, PcdGet64 (PcdPcieClock11)); + UpdatePcieClockInfo (PcieRpConfig, 12, PcdGet64 (PcdPcieClock12)); + UpdatePcieClockInfo (PcieRpConfig, 13, PcdGet64 (PcdPcieClock13)); + UpdatePcieClockInfo (PcieRpConfig, 14, PcdGet64 (PcdPcieClock14)); + UpdatePcieClockInfo (PcieRpConfig, 15, PcdGet64 (PcdPcieClock15)); + + PcieRpConfig->PcieDeviceOverrideTablePtr =3D (UINT32) mPcieDeviceTable; + PcieRpConfig->RootPort[0].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[1].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[2].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[3].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[4].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[5].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[6].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[7].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[8].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[9].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[10].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[11].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[12].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[13].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[14].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[15].ClkReqDetect =3D TRUE; + PcieRpConfig->RootPort[0].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[1].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[2].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[3].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[4].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[5].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[6].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[7].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[8].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[9].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[10].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[11].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[12].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[13].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[14].AdvancedErrorReporting =3D TRUE; + PcieRpConfig->RootPort[15].AdvancedErrorReporting =3D TRUE; + + // + // Install HDA Link/iDisplay Codec Verb Table + // + AddPlatformVerbTables ( + PchHdaCodecPlatformOnboard, + &(HdAudioConfig->VerbTableEntryNum), + &(HdAudioConfig->VerbTablePtr) + ); + + LockDownConfig->BiosLock =3D FALSE; + LockDownConfig->BiosInterface =3D FALSE; + + // + // IOAPIC Config + // +// IoApicConfig->IoApicEntry24_119 =3D PchSetup.PchIoApic24119Entries; + // + // To support SLP_S0, it's required to disable 8254 timer. + // Note that CSM may require this option to be disabled for correct oper= ation. + // Once 8254 timer disabled, some legacy OPROM and legacy OS will fail w= hile using 8254 timer. + // For some OS environment that it needs to set 8254CGE in late state it= should + // set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in S= MM later. + // This is also required during S3 resume. + // + // The Enable8254ClockGatingOnS3 is only applicable when Enable8254Clock= Gating is disabled. + // If Enable8254ClockGating is enabled, RC will do 8254 CGE programming = on S3 as well. + // else, RC will do the programming on S3 when Enable8254ClockGatingOnS3= is enabled. + // This avoids the SMI requirement for the programming. + // + // If S0ix is not enabled, then disable 8254CGE for leagcy boot case. + // + IoApicConfig->Enable8254ClockGating =3D FALSE; + IoApicConfig->Enable8254ClockGatingOnS3 =3D FALSE; + + // + // SerialIo Config + // + SerialIoConfig->DevMode[0] =3D 1; + SerialIoConfig->DevMode[1] =3D 1; + SerialIoConfig->DevMode[2] =3D 0; + SerialIoConfig->DevMode[3] =3D 0; + SerialIoConfig->DevMode[4] =3D 1; + SerialIoConfig->DevMode[5] =3D 0; + SerialIoConfig->DevMode[6] =3D 0; + SerialIoConfig->DevMode[7] =3D 0; + SerialIoConfig->DevMode[8] =3D 0; + SerialIoConfig->DevMode[9] =3D 0; + SerialIoConfig->DevMode[10] =3D 0; + SerialIoConfig->DevMode[11] =3D 3; + + SerialIoConfig->Uart0PinMuxing =3D 1; + SerialIoConfig->SpiCsPolarity[0] =3D 1; + SerialIoConfig->SpiCsPolarity[1] =3D 0; + SerialIoConfig->SpiCsPolarity[2] =3D 0; + + SerialIoConfig->UartHwFlowCtrl[0] =3D 1; + SerialIoConfig->UartHwFlowCtrl[1] =3D 1; + SerialIoConfig->UartHwFlowCtrl[2] =3D 1; + // + // I2C4 and I2C5 don't exist in SPT-H chipset + // + if (IsPchH ()) { + SerialIoConfig->DevMode[PchSerialIoIndexI2C4] =3D PchSerialIoDisabled; + SerialIoConfig->DevMode[PchSerialIoIndexI2C5] =3D PchSerialIoDisabled; + } + + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++= ) { + SerialIoConfig->I2cPadsTermination[Index] =3D GetSerialIoI2cPadsTermin= ationFromPcd (Index); + } + + PmConfig->SlpS0Override =3D 2; //PchSetup.SlpS0O= verride; + PmConfig->SlpS0DisQForDebug =3D 3; //PchSetup.SlpS0= DisQForDebug; + PmConfig->SlpS0Vm075VSupport =3D 1; // PcdGetBool(Pcd= SlpS0Vm075VSupport); + PmConfig->CpuC10GatePinEnable =3D 1; + + // + // Thermal Config + // + ThermalConfig->TsmicLock =3D TRUE; + ThermalConfig->PchHotEnable =3D PcdGetBool (PcdPchThermalHotEnabl= e); + + DmiHaAWC =3D &ThermalConfig->DmiHaAWC; + DmiHaAWC->TS3TW =3D 0; + DmiHaAWC->TS2TW =3D 1; + DmiHaAWC->TS1TW =3D 2; + DmiHaAWC->TS0TW =3D 3; + // + // Update Pch Usb Config + // + UpdatePchUsbConfig ( + UsbConfig + ); + + ScsConfig->ScsUfsEnabled =3D 0; + ScsConfig->ScsEmmcHs400Enabled =3D 1; + ScsConfig->ScsEmmcHs400TuningRequired =3D TRUE; + + IshConfig->I2c0GpioAssign =3D 1; + IshConfig->I2c1GpioAssign =3D 1; + IshConfig->Gp0GpioAssign =3D 1; + IshConfig->Gp1GpioAssign =3D 1; + IshConfig->Gp2GpioAssign =3D 1; + IshConfig->Gp3GpioAssign =3D 1; + IshConfig->Gp4GpioAssign =3D 1; + IshConfig->Gp5GpioAssign =3D 1; + IshConfig->Gp6GpioAssign =3D 1; + + return Status; +} diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiPchPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdatePreMem.c new file mode 100644 index 0000000000..968df0f55c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiPchPolicyUpdatePreMem.c @@ -0,0 +1,113 @@ +/** @file + This file is SampleCode of the library for Intel PCH PEI Policy initiali= zation. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPchPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Sawtooth Peak +// Single SPD EEPROM at 0xA2 serves both C0D0 and C1D0 (LPDDR is 1DPC only) +// +#define DIMM_SMB_SPD_P0C0D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C0D1_STP 0xA0 +#define DIMM_SMB_SPD_P0C1D0_STP 0xA2 +#define DIMM_SMB_SPD_P0C1D1_STP 0xA0 + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mSmbusSTPRsvdAddresses[] =3D { + DIMM_SMB_SPD_P0C0D0_STP, + DIMM_SMB_SPD_P0C0D1_STP, + DIMM_SMB_SPD_P0C1D0_STP, + DIMM_SMB_SPD_P0C1D1_STP +}; + + +/** + This function performs PCH PEI Policy initialization. + + @param[in, out] SiPreMemPolicy The SI PREMEM Policy PPI instance + + @retval EFI_SUCCESS The PPI is installed and initialized. + @retval EFI ERRORS The PPI is not successfully installed. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicy + ) +{ + EFI_STATUS Status; + UINT8 *SmBusReservedTable; + UINT8 SmBusReservedNum; + + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + PCH_TRACE_HUB_PREMEM_CONFIG *PchTraceHubPreMemConfig; + PCH_SMBUS_PREMEM_CONFIG *SmbusPreMemConfig; + PCH_LPC_PREMEM_CONFIG *LpcPreMemConfig; + PCH_WDT_PREMEM_CONFIG *WatchDogPreMemConfig; + PCH_DCI_PREMEM_CONFIG *DciPreMemConfig; + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig; + PCH_HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig; + PCH_ISH_PREMEM_CONFIG *IshPreMemConfig; + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchGeneralPreMemCo= nfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPchTraceHubPreMemC= onfigGuid, (VOID *) &PchTraceHubPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gSmbusPreMemConfigG= uid, (VOID *) &SmbusPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gLpcPreMemConfigGui= d, (VOID *) &LpcPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gWatchDogPreMemConf= igGuid, (VOID *) &WatchDogPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gDciPreMemConfigGui= d, (VOID *) &DciPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfig= Guid, (VOID *) &PcieRpPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfi= gGuid, (VOID *) &HdaPreMemConfig); + ASSERT_EFI_ERROR (Status); + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gIshPreMemConfigGui= d, (VOID *) &IshPreMemConfig); + ASSERT_EFI_ERROR (Status); + + DciPreMemConfig->DciUsb3TypecUfpDbg =3D 2; + PchTraceHubPreMemConfig->MemReg0Size =3D 3; + PchTraceHubPreMemConfig->MemReg1Size =3D 3; + // + // SMBUS + // + SmbusPreMemConfig->Enable =3D TRUE; + SmbusPreMemConfig->SmbAlertEnable =3D PcdGetBool (PcdSmbusAlertEnable); + // + // SMBUS reserved addresses + // + SmBusReservedTable =3D NULL; + SmBusReservedNum =3D 0; + SmbusPreMemConfig->SmbusIoBase =3D PcdGet16 (PcdSmbusBaseAddress); + SmBusReservedTable =3D mSmbusSTPRsvdAddresses; + SmBusReservedNum =3D sizeof (mSmbusSTPRsvdAddresses); + + if (SmBusReservedTable !=3D NULL) { + SmbusPreMemConfig->NumRsvdSmbusAddresses =3D SmBusReservedNum; + CopyMem ( + SmbusPreMemConfig->RsvdSmbusAddressTable, + SmBusReservedTable, + SmBusReservedNum + ); + } + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSaPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdate.c new file mode 100644 index 0000000000..c1ac7d890f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSaPolicyUpdate.c @@ -0,0 +1,242 @@ +/** @file +Do Platform Stage System Agent initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + UpdatePeiSaPolicy performs SA PEI Policy initialization + + @param[in out] SiPolicyPpi - SI_POLICY PPI + + @retval EFI_SUCCESS The policy is installed and initialized. +**/ +EFI_STATUS +UpdatePeiSaPolicy ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + EFI_GUID FileGuid; + VOID *Buffer; + UINT8 SaDisplayConfigTable[9] =3D {0}; + VOID *MemBuffer; + BMP_IMAGE_HEADER *BmpHeader; + UINT64 BltBufferSize; + UINT32 Size; + GRAPHICS_PEI_CONFIG *GtConfig; + GNA_CONFIG *GnaConfig; + WDT_PPI *gWdtPei; + PCIE_PEI_CONFIG *PciePeiConfig; + SA_MISC_PEI_CONFIG *MiscPeiConfig; + EFI_BOOT_MODE BootMode; + + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); + + Size =3D 0; + MemBuffer =3D NULL; + BmpHeader =3D NULL; + BltBufferSize =3D 0; + GtConfig =3D NULL; + GnaConfig =3D NULL; + + Status =3D GetConfigBlock((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid,= (VOID *)&GtConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPolicyPpi, &gGnaConfigGuid, (VOID *= )&GnaConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaPciePeiConfigGuid, = (VOID *)&PciePeiConfig); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid, = (VOID *)&MiscPeiConfig); + ASSERT_EFI_ERROR (Status); + + + // + // Locate WDT_PPI (ICC WDT PPI) + // + gWdtPei =3D NULL; + Status =3D PeiServicesLocatePpi( + &gWdtPpiGuid, + 0, + NULL, + (VOID **) &gWdtPei + ); + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + if (!EFI_ERROR (Status)) { + Buffer =3D NULL; + + CopyMem(&FileGuid, PcdGetPtr(PcdIntelGraphicsVbtFileGuid), sizeof(File= Guid)); + PeiGetSectionFromFv(FileGuid, &Buffer, &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Could not locate VBT\n")); + } + + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->GraphicsConfigPtr =3D MemBuffer; + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying VBT.\n")); + GtConfig->GraphicsConfigPtr =3D NULL; + } + + GtConfig->PeiGraphicsPeimInit =3D 1; + + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromFv is 0x%x\n", G= tConfig->GraphicsConfigPtr)); + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromFv is 0x%x\n", Size= )); + + PeiGetSectionFromFv (gTianoLogoGuid, &Buffer, &Size); + if (Buffer =3D=3D NULL) { + DEBUG((DEBUG_WARN, "Could not locate Logo\n")); + } + + MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)); + if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { + CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); + GtConfig->LogoPtr =3D MemBuffer; + GtConfig->LogoSize =3D Size; + + // + // Calculate the BltBuffer needed size. + // + BmpHeader =3D (BMP_IMAGE_HEADER *) GtConfig->LogoPtr; + + if (BmpHeader->CharB =3D=3D 'B' && BmpHeader->CharM =3D=3D 'M') { + BltBufferSize =3D MultU64x32 ((UINT64) BmpHeader->PixelWidth, BmpH= eader->PixelHeight); + if (BltBufferSize < DivU64x32 ((UINTN) ~0, sizeof (EFI_GRAPHICS_OU= TPUT_BLT_PIXEL))) { + BltBufferSize =3D MultU64x32 (BltBufferSize, sizeof (EFI_GRAPHIC= S_OUTPUT_BLT_PIXEL)); + GtConfig->BltBufferSize =3D (UINT32) BltBufferSize; + GtConfig->BltBufferAddress =3D (VOID *) AllocatePages (EFI_SIZE_= TO_PAGES ((UINTN)GtConfig->BltBufferSize)); + } else { + DEBUG ((DEBUG_ERROR, "Blt Buffer Size overflow.\n")); + ASSERT (FALSE); + } + } else { + DEBUG ((DEBUG_ERROR, "Wrong Bmp Image Header.\n")); + ASSERT (FALSE); + } + + } else { + DEBUG((DEBUG_WARN, "Error in locating / copying LogoPtr.\n")); + GtConfig->LogoPtr =3D NULL; + GtConfig->LogoSize =3D 0; + } + + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromFv is 0x%x\n", GtCon= fig->LogoPtr)); + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromFv is 0x%x\n", GtCo= nfig->LogoSize)); + + // + // Display DDI Initialization ( default Native GPIO as per board durin= g AUTO case) + // + if (PcdGet32 (PcdSaDisplayConfigTable) !=3D 0) { + CopyMem (SaDisplayConfigTable, (VOID *) (UINTN) PcdGet32 (PcdSaDispl= ayConfigTable), (UINTN)PcdGet16 (PcdSaDisplayConfigTableSize)); + GtConfig->DdiConfiguration.DdiPortEdp =3D SaDisplayConfigTable[0= ]; + GtConfig->DdiConfiguration.DdiPortBHpd =3D SaDisplayConfigTable[1= ]; + GtConfig->DdiConfiguration.DdiPortCHpd =3D SaDisplayConfigTable[2= ]; + GtConfig->DdiConfiguration.DdiPortDHpd =3D SaDisplayConfigTable[3= ]; + GtConfig->DdiConfiguration.DdiPortFHpd =3D SaDisplayConfigTable[4= ]; + GtConfig->DdiConfiguration.DdiPortBDdc =3D SaDisplayConfigTable[5= ]; + GtConfig->DdiConfiguration.DdiPortCDdc =3D SaDisplayConfigTable[6= ]; + GtConfig->DdiConfiguration.DdiPortDDdc =3D SaDisplayConfigTable[7= ]; + GtConfig->DdiConfiguration.DdiPortFDdc =3D SaDisplayConfigTable[8= ]; + } + } + + PciePeiConfig->DmiAspm =3D 0x3; + + return EFI_SUCCESS; +} + +/** + PeiGetSectionFromFv finds the file in FV and gets file Address and Size + + @param[in] NameGuid - File GUID + @param[out] Address - Pointer to the File Address + @param[out] Size - Pointer to File Size + + @retval EFI_SUCCESS Successfull in reading the section fr= om FV +**/ +EFI_STATUS +EFIAPI +PeiGetSectionFromFv ( + IN CONST EFI_GUID NameGuid, + OUT VOID **Address, + OUT UINT32 *Size + ) +{ + EFI_STATUS Status; + EFI_PEI_FIRMWARE_VOLUME_PPI *FvPpi; + EFI_FV_FILE_INFO FvFileInfo; + PEI_CORE_INSTANCE *PrivateData; + UINTN CurrentFv; + PEI_CORE_FV_HANDLE *CoreFvHandle; + EFI_PEI_FILE_HANDLE VbtFileHandle; + EFI_GUID *VbtGuid; + EFI_COMMON_SECTION_HEADER *Section; + CONST EFI_PEI_SERVICES **PeiServices; + + PeiServices =3D GetPeiServicesTablePointer(); + + PrivateData =3D PEI_CORE_INSTANCE_FROM_PS_THIS(PeiServices); + + Status =3D PeiServicesLocatePpi( + &gEfiFirmwareFileSystem2Guid, + 0, + NULL, + (VOID **)&FvPpi + ); + ASSERT_EFI_ERROR(Status); + + CurrentFv =3D PrivateData->CurrentPeimFvCount; + CoreFvHandle =3D &(PrivateData->Fv[CurrentFv]); + + Status =3D FvPpi->FindFileByName(FvPpi, &NameGuid, &CoreFvHandle->FvHand= le, &VbtFileHandle); + if (!EFI_ERROR(Status) && VbtFileHandle !=3D NULL) { + + DEBUG((DEBUG_INFO, "Find SectionByType \n")); + + Status =3D FvPpi->FindSectionByType(FvPpi, EFI_SECTION_RAW, VbtFileHan= dle, (VOID **)&VbtGuid); + if (!EFI_ERROR(Status)) { + + DEBUG((DEBUG_INFO, "GetFileInfo \n")); + + Status =3D FvPpi->GetFileInfo(FvPpi, VbtFileHandle, &FvFileInfo); + Section =3D (EFI_COMMON_SECTION_HEADER *)FvFileInfo.Buffer; + + if (IS_SECTION2(Section)) { + ASSERT(SECTION2_SIZE(Section) > 0x00FFFFFF); + *Size =3D SECTION2_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEAD= ER2); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER= 2)); + } else { + *Size =3D SECTION_SIZE(Section) - sizeof (EFI_COMMON_SECTION_HEADE= R); + *Address =3D ((UINT8 *)Section + sizeof (EFI_COMMON_SECTION_HEADER= )); + } + } + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/WhiskeylakeOpenBoardP= kg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c new file mode 100644 index 0000000000..3dc455ab29 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSaPolicyUpdatePreMem.c @@ -0,0 +1,221 @@ +/** @file +Do Platform Stage System Agent initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSaPolicyUpdate.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +/// +/// Memory Reserved should be between 125% to 150% of the Current required= memory +/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resum= e issues. +/// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTy= peInformation[] =3D { + { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory= Size) }, // ASL + { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize= ) }, // ACPI NVS (including S3 related) + { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz= e) }, // BIOS Reserved (including S3 related) + { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize)= }, // Runtime Service Data + { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize)= }, // Runtime Service Code + { EfiMaxMemoryType, 0 } +}; + + +/** + UpdatePeiSaPolicyPreMem performs SA PEI Policy initialization + + @param[in out] SiPreMemPolicyPpi - SI_PREMEM_POLICY PPI + + @retval EFI_SUCCESS The policy is installed and initialized. +**/ +EFI_STATUS +UpdatePeiSaPolicyPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig =3D NULL; + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc =3D NULL; + SA_MEMORY_RCOMP *RcompData; + WDT_PPI *gWdtPei; + UINT8 Index; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; + EFI_BOOT_MODE BootMode; + UINT8 MorControl; + UINT32 TraceHubTotalMemSize; + GRAPHICS_PEI_PREMEM_CONFIG *GtPreMemConfig =3D NULL; + MEMORY_CONFIGURATION *MemConfig =3D NULL; + PCIE_PEI_PREMEM_CONFIG *PciePeiPreMemConfig =3D NULL; + SWITCHABLE_GRAPHICS_CONFIG *SgGpioData =3D NULL; + IPU_PREMEM_CONFIG *IpuPreMemPolicy =3D NULL; + OVERCLOCKING_PREMEM_CONFIG *OcPreMemConfig =3D NULL; + VTD_CONFIG *Vtd =3D NULL; + UINT32 ProcessorTraceTotalMemSize; + UINT16 AdjustedMmioSize; + CPU_FAMILY CpuFamilyId; + CPU_STEPPING CpuStepping; + + TraceHubTotalMemSize =3D 0; + ProcessorTraceTotalMemSize =3D 0; + AdjustedMmioSize =3D PcdGet16 (PcdSaMiscMmioSizeAdjustment); + CpuFamilyId =3D GetCpuFamily(); + CpuStepping =3D GetCpuStepping(); + + DEBUG((DEBUG_INFO, "Entering Get Config Block function call from UpdateP= eiSaPolicyPreMem\n")); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC= onfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gGraphicsPeiPreMe= mConfigGuid, (VOID *) &GtPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigGuid= , (VOID *) &MemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaPciePeiPreMemC= onfigGuid, (VOID *) &PciePeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSwitchableGraphi= csConfigGuid, (VOID *) &SgGpioData); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gIpuPreMemConfigG= uid, (VOID *) &IpuPreMemPolicy); + ASSERT_EFI_ERROR (Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gMemoryConfigNoCr= cGuid, (VOID *) &MemConfigNoCrc); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaOverclockingPr= eMemConfigGuid, (VOID *) &OcPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gVtdConfigGuid, (= VOID *)&Vtd); + ASSERT_EFI_ERROR(Status); + + + RcompData =3D MemConfigNoCrc->RcompData; + + // + // Locate WDT_PPI (ICC WDT PPI) + // + gWdtPei =3D NULL; + Status =3D PeiServicesLocatePpi( + &gWdtPpiGuid, + 0, + NULL, + (VOID **) &gWdtPei + ); + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + MiscPeiPreMemConfig->S3DataPtr =3D NULL; + MorControl =3D 0; + MiscPeiPreMemConfig->UserBd =3D 0; // It's a CRB mobile board by default= (btCRBMB) + + PcdSetBoolS (PcdMobileDramPresent, (BOOLEAN) (MemConfig->MobilePlatform)= ); + MiscPeiPreMemConfig->SpdAddressTable[0] =3D PcdGet8 (PcdMrcSpdAddressTab= le0); + MiscPeiPreMemConfig->SpdAddressTable[1] =3D PcdGet8 (PcdMrcSpdAddressTab= le1); + MiscPeiPreMemConfig->SpdAddressTable[2] =3D PcdGet8 (PcdMrcSpdAddressTab= le2); + MiscPeiPreMemConfig->SpdAddressTable[3] =3D PcdGet8 (PcdMrcSpdAddressTab= le3); + MemConfig->CaVrefConfig =3D PcdGet8 (PcdMrcCaVrefConfig); + MemConfig->DualDimmPerChannelBoardType =3D PcdGetBool (PcdDualDimmPerCh= annelBoardType); + if (PcdGet32 (PcdMrcRcompResistor)) { + CopyMem((VOID *)RcompData->RcompResistor, (VOID *) (UINTN) PcdGet32 (P= cdMrcRcompResistor), sizeof (RcompData->RcompResistor)); + } + if (PcdGet32 (PcdMrcRcompTarget)) { + CopyMem((VOID *)RcompData->RcompTarget, (VOID *) (UINTN) PcdGet32 (Pcd= MrcRcompTarget), sizeof (RcompData->RcompTarget)); + } + if (PcdGet32 (PcdMrcDqByteMap)) { + CopyMem((VOID *)MemConfigNoCrc->DqByteMap, (VOID *) (UINTN) PcdGet32 (= PcdMrcDqByteMap), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MRC_ITERATION_MAX= * 2); + } + if (PcdGet32 (PcdMrcDqsMapCpu2Dram)) { + CopyMem((VOID *)MemConfigNoCrc->DqsMap, (VOID *) (UINTN) PcdGet32 (Pcd= MrcDqsMapCpu2Dram), sizeof (UINT8)* SA_MC_MAX_CHANNELS * SA_MC_MAX_BYTES_NO= _ECC); + } + if (PcdGetBool (PcdMrcDqPinsInterleavedControl)) { + MemConfig->DqPinsInterleaved =3D PcdGetBool (PcdMrcDqPinsInterleaved); + } + if (PcdGet32 (PcdMrcSpdData)) { + CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[0][0], (VOID *) (UINT= N) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE); + CopyMem((VOID *)MemConfigNoCrc->SpdData->SpdData[1][0], (VOID *) (UINT= N) PcdGet32 (PcdMrcSpdData), SPD_DATA_SIZE); + } + + MiscPeiPreMemConfig->MchBar =3D (UINTN) PcdGet64 (PcdMchBaseAddress); + MiscPeiPreMemConfig->DmiBar =3D (UINTN) PcdGet64 (PcdDmiBaseAddress); + MiscPeiPreMemConfig->EpBar =3D (UINTN) PcdGet64 (PcdEpBaseAddress); + MiscPeiPreMemConfig->EdramBar =3D (UINTN) PcdGet64 (PcdEdramBaseAddress); + MiscPeiPreMemConfig->SmbusBar =3D PcdGet16(PcdSmbusBaseAddress); + MiscPeiPreMemConfig->TsegSize =3D PcdGet32(PcdTsegSize); + MiscPeiPreMemConfig->UserBd =3D PcdGet8 (PcdSaMiscUserBd); + MiscPeiPreMemConfig->MmioSizeAdjustment =3D PcdGet16 (PcdSaMiscMmioSizeA= djustment); + if (PcdGetBool (PcdPegGpioResetControl)) { + PciePeiPreMemConfig->PegGpioData.GpioSupport =3D PcdGetBool (PcdPegGpi= oResetSupoort); + } else { + + } + PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.GpioPad =3D PcdGet32 (P= cdPeg0ResetGpioPad); + PciePeiPreMemConfig->PegGpioData.SaPeg0ResetGpio.Active =3D PcdGetBool = (PcdPeg0ResetGpioActive); + + PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.GpioPad =3D PcdGet32 (P= cdPeg3ResetGpioPad); + PciePeiPreMemConfig->PegGpioData.SaPeg3ResetGpio.Active =3D PcdGetBool = (PcdPeg3ResetGpioActive); + + MemConfig->CkeRankMapping =3D 0xAA; + /// + /// Initialize the VTD Configuration + /// + Vtd->VtdDisable =3D 0; + + MemConfig->RMT =3D 1; + MemConfig->UserPowerWeightsEn =3D 0; + MemConfig->RaplLim2WindY =3D 0x0A; + MemConfig->ExitOnFailure =3D 1; + + MemConfigNoCrc->PlatformMemorySize =3D PEI_MIN_MEMORY_SIZE + TraceHubTot= alMemSize + ProcessorTraceTotalMemSize; + DataSize =3D sizeof (mDefaultMemoryTypeInformation); + CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize); + + if (BootMode !=3D BOOT_IN_RECOVERY_MODE) { + for (Index =3D 0; Index < DataSize / sizeof (EFI_MEMORY_TYPE_INFORMATI= ON); Index++) { + MemConfigNoCrc->PlatformMemorySize +=3D MemoryData[Index].NumberOfPa= ges * EFI_PAGE_SIZE; + } + + OcPreMemConfig->GtMaxOcRatio =3D 0; + OcPreMemConfig->GtVoltageMode =3D 0; + OcPreMemConfig->GtVoltageOverride =3D 0; + OcPreMemConfig->GtExtraTurboVoltage =3D 0; + OcPreMemConfig->GtVoltageOffset =3D 0; + OcPreMemConfig->SaVoltageOffset =3D 0; + OcPreMemConfig->GtusMaxOcRatio =3D 0; + OcPreMemConfig->GtusVoltageMode =3D 0; + OcPreMemConfig->GtusVoltageOverride =3D 0; + OcPreMemConfig->GtusExtraTurboVoltage =3D 0; + OcPreMemConfig->GtusVoltageOffset =3D 0; + + /// + /// Build the GUID'd HOB for DXE + /// + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + MemoryData, + DataSize + ); + } + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolic= yUpdateLib/PeiSiPolicyUpdate.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Pol= icy/Library/PeiPolicyUpdateLib/PeiSiPolicyUpdate.c new file mode 100644 index 0000000000..3efbe2ccbd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdate= Lib/PeiSiPolicyUpdate.c @@ -0,0 +1,168 @@ +/** @file + This file is SampleCode of the library for Intel Silicon PEI + Platform Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiSiPolicyUpdate.h" +#include +#include +#include +#include +#include + +STATIC SVID_SID_INIT_ENTRY mCdfSsidTablePtr[] =3D { + // + // SA Device(s) + // + {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + // + // PCH Device(s) + // + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, PCI_DE= VICE_NUMBER_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, PCI_DE= VICE_NUMBER_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, PCI_DE= VICE_NUMBER_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, PCI_DE= VICE_NUMBER_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_1, PCI_DE= VICE_NUMBER_CDF_PCH_SATA_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_2, PCI_DE= VICE_NUMBER_CDF_PCH_SATA_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_CDF_PCH_SATA_3, PCI_DE= VICE_NUMBER_CDF_PCH_SATA_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, PCI_DE= VICE_NUMBER_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, PCI_DE= VICE_NUMBER_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, PCI_DE= VICE_NUMBER_PCH_TRACE_HUB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, PCI_DE= VICE_NUMBER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, PCI_DE= VICE_NUMBER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, PCI_DE= VICE_NUMBER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_S= EGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PC= I_DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_P= CI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, +}; + +STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[] =3D { + // + // SA Device(s) + // + {{{PCI_SVID_OFFSET, SA_MC_FUN, SA_MC_DEV, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG0_FUN_NUM, SA_PEG0_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG1_FUN_NUM, SA_PEG1_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{R_SA_PEG_SS_OFFSET, SA_PEG2_FUN_NUM, SA_PEG2_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_IGD_FUN_0, SA_IGD_DEV, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_IPU_FUN_NUM, SA_IPU_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SA_GNA_FUN_NUM, SA_GNA_DEV_NUM, SA_MC_BUS, 0,= SA_SEG_NUM, 0}}, {0, 0},0}, + // + // PCH Device(s) + // + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LPC, PCI_DEVICE_NUMBE= R_PCH_LPC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_P2SB, PCI_DEVICE_NUMBE= R_PCH_P2SB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_PMC, PCI_DEVICE_NUMBE= R_PCH_PMC, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_HDA, PCI_DEVICE_NUMBE= R_PCH_HDA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SATA, PCI_DEVICE_NUMBE= R_PCH_SATA, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SMBUS, PCI_DEVICE_NUMBE= R_PCH_SMBUS, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SPI, PCI_DEVICE_NUMBE= R_PCH_SPI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH= , 0}}, {0, 0},0}, + // + // Skip PCH LAN controller + // PCH LAN SVID/SID may be loaded automatically from the NVM Word 0Ch/0B= h upon power up or reset + // depending on the "Load Subsystem ID" bit field in NVM word 0Ah + // + //{{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_LAN, PCI_DEVICE_NUM= BER_PCH_LAN, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_P= CH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_TRACE_HUB, PCI_DEVICE= _NUMBER_PCH_TRACE_HUB, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_UART0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_UART1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_SPI0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_SPI1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SE= GMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_CNL_SCS_SDCARD, PCI_DEVICE_= NUMBER_PCH_CNL_SCS_SDCARD, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGME= NT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XHCI, PCI_DEVICE_NUMB= ER_PCH_XHCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE= R_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_XDCI, PCI_DEVICE_NUMB= ER_PCH_XDCI, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE= R_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_THERMAL, PCI_DEVICE_NUMB= ER_PCH_THERMAL, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBE= R_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_ISH, PCI_DEVI= CE_NUMBER_PCH_ISH, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_1, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_2, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_3, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_4, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_5, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_6, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_7, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_8, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_9, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_10, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_11, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_12, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_13, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_14, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_15, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_16, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_17, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_18, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_19, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_20, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_21, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_22, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_23, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{R_PCH_PCIE_CFG_SVID, PCI_FUNCTION_NUMBER_PCH_PCIE_ROOT_PORT_24, PCI_= DEVICE_NUMBER_PCH_PCIE_DEVICE_3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI= _SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C0, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C1, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C3, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_UART2, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C5, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4, PCI_DEVICE= _NUMBER_PCH_SERIAL_IO_I2C4, DEFAULT_PCI_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEG= MENT_NUMBER_PCH, 0}}, {0, 0},0}, + // + // ME Device(s) + // + {{{PCI_SVID_OFFSET, HECI_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, HECI2_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, IDER_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, SOL_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, HECI3_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0}, + {{{PCI_SVID_OFFSET, HECI4_FUNCTION_NUMBER, ME_DEVICE_NUMBER, DEFAULT_PC= I_BUS_NUMBER_PCH, 0, DEFAULT_PCI_SEGMENT_NUMBER_PCH, 0}}, {0, 0},0} +}; + +/** + This function performs Silicon PEI Policy initialization. + + @param[in] SiPolicy The Silicon Policy PPI instance + + @retval EFI_SUCCESS The function completed successfully +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicy ( + IN OUT SI_POLICY_PPI *SiPolicy + ) +{ + EFI_STATUS Status; + SI_CONFIG *SiConfig; + + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSiConfigGuid, (VOID *) &= SiConfig); + ASSERT_EFI_ERROR (Status); + + SiConfig->CsmFlag =3D 0; + + if (IsCdfPch ()) { + SiConfig->SsidTablePtr =3D (UINT32*)(UINTN) mCdfSsidTablePtr; + SiConfig->NumberOfSsidTableEntry =3D (sizeof (mCdfSsidTablePtr) / size= of (SVID_SID_INIT_ENTRY)); + } else { + SiConfig->SsidTablePtr =3D (UINT32*)(UINTN) mSsidTablePtr; + SiConfig->NumberOfSsidTableEntry =3D (sizeof (mSsidTablePtr) / sizeof = (SVID_SID_INIT_ENTRY)); + } + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/Whiskeylake= OpenBoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEnt= ry.nasm new file mode 100644 index 0000000000..5c5b788085 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/Ia32/PeiCoreEntry.nasm @@ -0,0 +1,130 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; PeiCoreEntry.nasm +; +; Abstract: +; +; Find and call SecStartup +; +;-------------------------------------------------------------------------= ----- + +SECTION .text + +extern ASM_PFX(SecStartup) +extern ASM_PFX(PlatformInit) + +global ASM_PFX(CallPeiCoreEntryPoint) +ASM_PFX(CallPeiCoreEntryPoint): + ; + ; Obtain the hob list pointer + ; + mov eax, [esp+4] + ; + ; Obtain the stack information + ; ECX: start of range + ; EDX: end of range + ; + mov ecx, [esp+8] + mov edx, [esp+0xC] + + ; + ; Platform init + ; + pushad + push edx + push ecx + push eax + call ASM_PFX(PlatformInit) + pop eax + pop eax + pop eax + popad + + ; + ; Set stack top pointer + ; + mov esp, edx + + ; + ; Push the hob list pointer + ; + push eax + + ; + ; Save the value + ; ECX: start of range + ; EDX: end of range + ; + mov ebp, esp + push ecx + push edx + + ; + ; Push processor count to stack first, then BIST status (AP then BSP) + ; + mov eax, 1 + cpuid + shr ebx, 16 + and ebx, 0xFF + cmp bl, 1 + jae PushProcessorCount + + ; + ; Some processors report 0 logical processors. Effectively 0 =3D 1. + ; So we fix up the processor count + ; + inc ebx + +PushProcessorCount: + push ebx + + ; + ; We need to implement a long-term solution for BIST capture. For now, = we just copy BSP BIST + ; for all processor threads + ; + xor ecx, ecx + mov cl, bl +PushBist: + movd eax, mm0 + push eax + loop PushBist + + ; Save Time-Stamp Counter + movd eax, mm5 + push eax + + movd eax, mm6 + push eax + + ; + ; Pass entry point of the PEI core + ; + mov edi, 0xFFFFFFE0 + push DWORD [edi] + + ; + ; Pass BFV into the PEI Core + ; + mov edi, 0xFFFFFFFC + push DWORD [edi] + + ; + ; Pass stack size into the PEI Core + ; + mov ecx, [ebp - 4] + mov edx, [ebp - 8] + push ecx ; RamBase + + sub edx, ecx + push edx ; RamSize + + ; + ; Pass Control into the PEI Core + ; + call ASM_PFX(SecStartup) + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/WhiskeylakeOpen= BoardPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm new file mode 100644 index 0000000000..7f6d771e41 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/Ia32/SecEntry.nasm @@ -0,0 +1,361 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; Module Name: +; +; SecEntry.nasm +; +; Abstract: +; +; This is the code that goes from real-mode to protected mode. +; It consumes the reset vector, calls TempRamInit API from FSP binary. +; +;-------------------------------------------------------------------------= ----- + +#include "Fsp.h" + +SECTION .text + +extern ASM_PFX(CallPeiCoreEntryPoint) +extern ASM_PFX(FsptUpdDataPtr) +extern ASM_PFX(BoardBeforeTempRamInit) +; Pcds +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) +extern ASM_PFX(PcdGet32 (PcdFsptBaseAddress)) + +;-------------------------------------------------------------------------= --- +; +; Procedure: _ModuleEntryPoint +; +; Input: None +; +; Output: None +; +; Destroys: Assume all registers +; +; Description: +; +; Transition to non-paged flat-model protected mode from a +; hard-coded GDT that provides exactly two descriptors. +; This is a bare bones transition to protected mode only +; used for a while in PEI and possibly DXE. +; +; After enabling protected mode, a far jump is executed to +; transfer to PEI using the newly loaded GDT. +; +; Return: None +; +; MMX Usage: +; MM0 =3D BIST State +; MM5 =3D Save time-stamp counter value high32bit +; MM6 =3D Save time-stamp counter value low32bit. +; +;-------------------------------------------------------------------------= --- + +BITS 16 +align 4 +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + fninit ; clear any pending Floating point= exceptions + ; + ; Store the BIST value in mm0 + ; + movd mm0, eax + cli + + ; + ; Check INIT# is asserted by port 0xCF9 + ; + mov dx, 0CF9h + in al, dx + cmp al, 04h + jnz NotWarmStart + + + ; + ; @note Issue warm reset, since if CPU only reset is issued not all MSRs= are restored to their defaults + ; + mov dx, 0CF9h + mov al, 06h + out dx, al + +NotWarmStart: + ; + ; Save time-stamp counter value + ; rdtsc load 64bit time-stamp counter to EDX:EAX + ; + rdtsc + movd mm5, edx + movd mm6, eax + + ; + ; Load the GDT table in GdtDesc + ; + mov esi, GdtDesc + DB 66h + lgdt [cs:si] + + ; + ; Transition to 16 bit protected mode + ; + mov eax, cr0 ; Get control register 0 + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #= 1) + mov cr0, eax ; Activate protected mode + + mov eax, cr4 ; Get control register 4 + or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCP= T bit (bit #10) + mov cr4, eax + + ; + ; Now we're in 16 bit protected mode + ; Set up the selectors for 32 bit protected mode entry + ; + mov ax, SYS_DATA_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + ; + ; Transition to Flat 32 bit protected mode + ; The jump to a far pointer causes the transition to 32 bit mode + ; + mov esi, ProtectedModeEntryLinearAddress + jmp dword far [cs:si] + +;-------------------------------------------------------------------------= --- +; +; Procedure: ProtectedModeEntryPoint +; +; Input: None +; +; Output: None +; +; Destroys: Assume all registers +; +; Description: +; +; This function handles: +; Call two basic APIs from FSP binary +; Initializes stack with some early data (BIST, PEI entry, etc) +; +; Return: None +; +;-------------------------------------------------------------------------= --- + +BITS 32 +align 4 +ProtectedModeEntryPoint: + ; + ; Early board hooks + ; + mov esp, BoardBeforeTempRamInitRet + jmp ASM_PFX(BoardBeforeTempRamInit) + +BoardBeforeTempRamInitRet: + + ; Find the fsp info header + mov edi, [ASM_PFX(PcdGet32 (PcdFsptBaseAddress))] + + mov eax, dword [edi + FVH_SIGINATURE_OFFSET] + cmp eax, FVH_SIGINATURE_VALID_VALUE + jnz FspHeaderNotFound + + xor eax, eax + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET] + cmp ax, 0 + jnz FspFvExtHeaderExist + + xor eax, eax + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header + add edi, eax + jmp FspCheckFfsHeader + +FspFvExtHeaderExist: + add edi, eax + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header + add edi, eax + + ; Round up to 8 byte alignment + mov eax, edi + and al, 07h + jz FspCheckFfsHeader + + and edi, 0FFFFFFF8h + add edi, 08h + +FspCheckFfsHeader: + ; Check the ffs guid + mov eax, dword [edi] + cmp eax, FSP_HEADER_GUID_DWORD1 + jnz FspHeaderNotFound + + mov eax, dword [edi + 4] + cmp eax, FSP_HEADER_GUID_DWORD2 + jnz FspHeaderNotFound + + mov eax, dword [edi + 8] + cmp eax, FSP_HEADER_GUID_DWORD3 + jnz FspHeaderNotFound + + mov eax, dword [edi + 0Ch] + cmp eax, FSP_HEADER_GUID_DWORD4 + jnz FspHeaderNotFound + + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header + + ; Check the section type as raw section + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET] + cmp al, 019h + jnz FspHeaderNotFound + + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header + jmp FspHeaderFound + +FspHeaderNotFound: + jmp $ + +FspHeaderFound: + ; Get the fsp TempRamInit Api address + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] + + ; Setup the hardcode stack + mov esp, TempRamInitStack + + ; Call the fsp TempRamInit Api + jmp eax + +TempRamInitDone: + cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for= Microcode Update not found. + je CallSecFspInit ;If microcode not found, don't hang, but continu= e. + + cmp eax, 0 ;Check if EFI_SUCCESS retuned. + jnz FspApiFailed + + ; ECX: start of range + ; EDX: end of range +CallSecFspInit: + sub edx, [ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize))] ; TemporaryRam= for FSP + xor eax, eax + mov esp, edx + + ; Align the stack at DWORD + add esp, 3 + and esp, 0FFFFFFFCh + + push edx + push ecx + push eax ; zero - no hob list yet + call ASM_PFX(CallPeiCoreEntryPoint) + +FspApiFailed: + jmp $ + +align 10h +TempRamInitStack: + DD TempRamInitDone + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams + +; +; ROM-based Global-Descriptor Table for the Tiano PEI Phase +; +align 16 +global ASM_PFX(BootGdtTable) + +; +; GDT[0]: 0x00: Null entry, never used. +; +NULL_SEL EQU $ - GDT_BASE ; Selector [0] +GDT_BASE: +ASM_PFX(BootGdtTable): + DD 0 + DD 0 +; +; Linear data segment descriptor +; +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 092h ; present, ring 0, data, expand-up= , writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; Linear code segment descriptor +; +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 09Bh ; present, ring 0, data, expand-up= , not-writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; System data segment descriptor +; +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 093h ; present, ring 0, data, expand-up= , not-writable + DB 0CFh ; page-granular, 32-bit + DB 0 + +; +; System code segment descriptor +; +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 09Ah ; present, ring 0, data, expand-up= , writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; Spare segment descriptor +; +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0Eh ; Changed from F000 to E000. + DB 09Bh ; present, ring 0, code, expand-up= , writable + DB 00h ; byte-granular, 16-bit + DB 0 +; +; Spare segment descriptor +; +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 093h ; present, ring 0, data, expand-up= , not-writable + DB 00h ; byte-granular, 16-bit + DB 0 + +; +; Spare segment descriptor +; +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38] + DW 0 ; limit 0 + DW 0 ; base 0 + DB 0 + DB 0 ; present, ring 0, data, expand-up= , writable + DB 0 ; page-granular, 32-bit + DB 0 +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes + +; +; GDT Descriptor +; +GdtDesc: ; GDT descriptor + DW GDT_SIZE - 1 ; GDT limit + DD GDT_BASE ; GDT base address + + +ProtectedModeEntryLinearAddress: +ProtectedModeEntryLinear: + DD ProtectedModeEntryPoint ; Offset of our 32 bit code + DW LINEAR_CODE_SEL diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecF= spWrapperPlatformSecLib/Ia32/Stack.nasm b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/Ia32/Stack.nasm new file mode 100644 index 0000000000..47db32d64c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/SecFspWrapp= erPlatformSecLib/Ia32/Stack.nasm @@ -0,0 +1,72 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; Abstract: +; +; Switch the stack from temporary memory to permanent memory. +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; EFIAPI +; SecSwitchStack ( +; UINT32 TemporaryMemoryBase, +; UINT32 PermanentMemoryBase +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(SecSwitchStack) +ASM_PFX(SecSwitchStack): + ; + ; Save three register: eax, ebx, ecx + ; + push eax + push ebx + push ecx + push edx + + ; + ; !!CAUTION!! this function address's is pushed into stack after + ; migration of whole temporary memory, so need save it to permanent + ; memory at first! + ; + + mov ebx, [esp + 20] ; Save the first parameter + mov ecx, [esp + 24] ; Save the second parameter + + ; + ; Save this function's return address into permanent memory at first. + ; Then, Fixup the esp point to permanent memory + ; + mov eax, esp + sub eax, ebx + add eax, ecx + mov edx, dword [esp] ; copy pushed register's value to perma= nent memory + mov dword [eax], edx + mov edx, dword [esp + 4] + mov dword [eax + 4], edx + mov edx, dword [esp + 8] + mov dword [eax + 8], edx + mov edx, dword [esp + 12] + mov dword [eax + 12], edx + mov edx, dword [esp + 16] ; Update this function's return address= into permanent memory + mov dword [eax + 16], edx + mov esp, eax ; From now, esp is pointed to perma= nent memory + + ; + ; Fixup the ebp point to permanent memory + ; + mov eax, ebp + sub eax, ebx + add eax, ecx + mov ebp, eax ; From now, ebp is pointed to permanent = memory + + pop edx + pop ecx + pop ebx + pop eax + ret + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/Ba= seAcpiTimerLib.uni b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTim= erLib/BaseAcpiTimerLib.uni new file mode 100644 index 0000000000..33b4be68db --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/BaseAcpiT= imerLib.uni @@ -0,0 +1,15 @@ +/** @file + Base ACPI Timer Library + Provides basic timer support using the ACPI timer hardware. The perform= ance + counter features are provided by the processors time stamp counter. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#string STR_MODULE_ABSTRACT #language en-US "ACPI Timer Librar= y" + +#string STR_MODULE_DESCRIPTION #language en-US "Provides basic ti= mer support using the ACPI timer hardware." + + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45910): https://edk2.groups.io/g/devel/message/45910 Mute This Topic: https://groups.io/mt/32918204/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45911+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45911+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001034; cv=none; d=zoho.com; s=zohoarc; b=cykmv9Drpabax9YyD80VNOvw2n3u7PEz7sbSC6LOxnhEQl28xpT4a6YCQsPH5wahzUSjx3QfyRZS6kvoTBzQlCGtn7GXFpjARZ3BvcsP7gsBZJWYtV7KZiwHyUuT71n5IdUTaH/v+9PQtpq/vQt6ck+Nil0ng8ByW5yOyVmuiGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001034; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=YlxCY2Ha5dcl+eH8g896G8fDwnYC/j6KW947hJnD8E0=; b=ExBOvtyRis6monNw89y/ZUN3IuRO1poJ1mUmY2jkTPoIp3lSvMcKpAxFsjh35XOhqsNfA+67zQAhKDSczHA1YFzVBteEZK+4wQnk8kJRKeTdu3L0Bj2Ro/tPd7lU/GAXnevvs/5s/iA6NZz8LAxV3p7P3E2ZNNdbEl7EvKoH+uw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45911+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001034013564.2834192380442; Fri, 16 Aug 2019 17:17:14 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:12 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:17:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319372" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:16:59 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 34/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add library instances Date: Fri, 16 Aug 2019 17:16:00 -0700 Message-Id: <20190817001603.30632-35-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001033; bh=rxjhMqEptlONPOXClzOHPYnGgZmYoGqiLLPWS9LLd90=; h=Cc:Date:From:Reply-To:Subject:To; b=LEJkXr6AGdGM5fprsfPmIw25g33LEOdVPOjciB2EHPeSrcj/8BXZv9RNQu9QUiRd//X 57/9lW5R+uLhhFT3wgWTZKTW2afgwdZ6DxxUx6H6IwlO8OSzCeohujZfHnLEoCbrlc9UB aze3LPFd/X6P4XSkts0yiL2NcvCJ2Tg4Ryk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 WhiskeylakeURvp library instances. * BaseFuncLib - Board-specific VBT update routines. * BaseGpioCheckConflictLib - Identifies GPIO pad conflicts. * BaseGpioCheckConflictLibNull - NULL library instance. * BasePlatformHookLib - Serial port initialization support. * DxePolicyBoardConfigLib - Board-specific silicon policy configuration in DXE. * PeiBoardInitPostMemLib - PEI post-memory board-specific initialization. This library implements board APIs declared in MinPlatformPkg. * PeiBoardInitPreMemLib - PEI pre-memory board-specific initialization. This library implements board APIs declared in MinPlatformPkg. * PeiMultiBoardInitPostMemLib - PEI post-memory multi-board initialization. This library implements board APIs declared in MinPlatformPkg. * PeiMultiBoardInitPreMemLib - PEI pre-memory multi-board initialization. This library implements board APIs declared in MinPlatformPkg. * PeiPlatformHookLib - PEI board instance-specifc GPIO init. * PeiPolicyBoardConfigLib - Board instance-specific policy init in PEI. * SmmBoardAcpiEnableLib - Board instance-specific SMM ACPI enable support. * SmmMultiBoardAcpiSupportLib - Multi-board ACPI support in SMM. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib= /BaseFuncLib.inf | 33 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioChe= ckConflictLib/BaseGpioCheckConflictLib.inf | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioChe= ckConflictLibNull/BaseGpioCheckConflictLibNull.inf | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatfor= mHookLib/BasePlatformHookLib.inf | 53 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmBoardAcpiEnableLib.inf | 50 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmMultiBoardAcpiSupportLib.inf | 50 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiBoardInitPostMemLib.inf | 53 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiBoardInitPreMemLib.inf | 116 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPostMemLib.inf | 202 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPreMemLib.inf | 296 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBo= ardConfigLib/DxePolicyBoardConfigLib.inf | 44 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatform= HookLib/PeiPlatformHooklib.inf | 94 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiPolicyBoardConfigLib.inf | 70 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardFunc.h | 18 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardInitLib.h | 20 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardSaConfigPreMem.h | 90 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/GpioTableDefault.h | 225 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/GpioTableWhlUDdr4.h | 284 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/GpioTableWhlUDdr4PreMem.h | 59 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PchHdaVerbTables.h | 3014 +++++++++++++++++= +++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiWhiskeylakeURvpInitLib.h | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBo= ardConfigLib/DxePolicyBoardConfig.h | 20 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiPolicyBoardConfig.h | 23 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFuncLib= /Gop.c | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioChe= ckConflictLib/BaseGpioCheckConflictLib.c | 137 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioChe= ckConflictLibNull/BaseGpioCheckConflictLibNull.c | 37 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePlatfor= mHookLib/BasePlatformHookLib.c | 156 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmBoardAcpiEnableLib.c | 63 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmMultiBoardAcpiSupportLib.c | 82 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmSiliconAcpiEnableLib.c | 170 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLi= b/SmmWhiskeylakeURvpAcpiEnableLib.c | 40 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardFunc.c | 19 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardFuncInit.c | 27 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardFuncInitPreMem.c | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardPchInitPreMemLib.c | 398 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/BoardSaInitPreMemLib.c | 282 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiBoardInitPostMemLib.c | 40 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiBoardInitPreMemLib.c | 106 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPostMemLib.c | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiMultiBoardInitPreMemLib.c | 83 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiWhiskeylakeURvpDetect.c | 63 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiWhiskeylakeURvpInitPostMemLib.c | 432 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/PeiWhiskeylakeURvpInitPreMemLib.c | 636 +++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLi= b/WhiskeylakeURvpHsioPtssTables.c | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBo= ardConfigLib/DxeSaPolicyBoardConfig.c | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPlatform= HookLib/PeiPlatformHooklib.c | 299 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiCpuPolicyBoardConfig.c | 48 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiCpuPolicyBoardConfigPreMem.c | 29 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiMePolicyBoardConfig.c | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiMePolicyBoardConfigPreMem.c | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiPchPolicyBoardConfig.c | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiPchPolicyBoardConfigPreMem.c | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiSaPolicyBoardConfig.c | 35 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiSaPolicyBoardConfigPreMem.c | 36 + Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBo= ardConfigLib/PeiSiPolicyBoardConfig.c | 27 + 55 files changed, 8499 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BaseFuncLib/BaseFuncLib.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whisk= eylakeURvp/Library/BaseFuncLib/BaseFuncLib.inf new file mode 100644 index 0000000000..0ccc73b99f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFu= ncLib/BaseFuncLib.inf @@ -0,0 +1,33 @@ +## @file +# Component information file for Board Functions Library. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BaseBoardFuncInitLib + FILE_GUID =3D 7ad17b6c-b9b6-4d88-85c4-7366a2bd12a3 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|PEIM + +[LibraryClasses] + BaseLib + DebugLib + +[Packages] + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + Gop.c + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf b/Platform/Intel/Whi= skeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseG= pioCheckConflictLib.inf new file mode 100644 index 0000000000..5014faf664 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGp= ioCheckConflictLib/BaseGpioCheckConflictLib.inf @@ -0,0 +1,35 @@ +## @file +# Component information file for BaseGpioCheckConflictLib. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BaseGpioCheckConflictLib + FILE_GUID =3D C19A848A-F013-4DBF-9C23-F0F74DEA6F14 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D GpioCheckConflictLib + +[LibraryClasses] + DebugLib + HobLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + BaseGpioCheckConflictLib.c + +[Guids] + gGpioCheckConflictHobGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf b/Platform/I= ntel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictL= ibNull/BaseGpioCheckConflictLibNull.inf new file mode 100644 index 0000000000..d9b242b3fc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGp= ioCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf @@ -0,0 +1,32 @@ +## @file +# Component information file for BaseGpioCheckConflictLib. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BaseGpioCheckConflictLibNull + FILE_GUID =3D C19A848A-F013-4DBF-9C23-F0F74DEA6F14 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D GpioCheckConflictLib + +[LibraryClasses] + DebugLib + HobLib + GpioLib + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + BaseGpioCheckConflictLibNull.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BasePlatformHookLib/BasePlatformHookLib.inf b/Platform/Intel/WhiskeylakeOp= enBoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.= inf new file mode 100644 index 0000000000..143bb89c63 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePl= atformHookLib/BasePlatformHookLib.inf @@ -0,0 +1,53 @@ +## @file +# Platform Hook Library instance for Whiskeylake Mobile/Desktop CRB. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D BasePlatformHookLib + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D PlatformHookLib +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciSegmentLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioDataDefaultPort ## CONSU= MES + gPlatformModuleTokenSpaceGuid.PcdDesktopLpcSioIndexDefaultPort ## CONSU= MES + +[FixedPcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES + +[Sources] + BasePlatformHookLib.c + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmBoardAcpiEnableLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf new file mode 100644 index 0000000000..8ad32a55dc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmBoardAcpiEnableLib.inf @@ -0,0 +1,50 @@ +## @file +# Platform Hook Library instance for Whiskeylake Mobile/Desktop CRB. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmBoardAcpiEnableLib + FILE_GUID =3D 549E69AE-D3B3-485B-9C17-AF16E20A58AD + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D BoardAcpiEnableLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + MmPciLib + PchCycleDecodingLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + +[Protocols] + +[Sources] + SmmWhiskeylakeURvpAcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmBoardAcpiEnableLib.c + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/WhiskeylakeO= penBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLi= b.inf new file mode 100644 index 0000000000..27001c3b7f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmMultiBoardAcpiSupportLib.inf @@ -0,0 +1,50 @@ +## @file +# Platform Hook Library instance for Whiskeylake Mobile/Desktop CRB. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmWhiskeylakeURvpMultiBoardAcpiSuppo= rtLib + FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D SmmWhiskeylakeURvpMultiBoardAcpiSuppo= rtLibConstructor + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[LibraryClasses] + BaseLib + IoLib + PciLib + PmcLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdSmcExtSmiBitPosition ## CONSUMES + +[Protocols] + +[Sources] + SmmWhiskeylakeURvpAcpiEnableLib.c + SmmSiliconAcpiEnableLib.c + SmmMultiBoardAcpiSupportLib.c + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..a8c4869e96 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPostMemLib.inf @@ -0,0 +1,53 @@ +## @file +# Component information file for WhiskeylakeURvpInitLib in PEI post memory= phase. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardPostMemInitLib + FILE_GUID =3D 7fcc3900-d38d-419f-826b-72481e8b5509 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + HdaVerbTableLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + SecurityPkg/SecurityPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiWhiskeylakeURvpInitPostMemLib.c + PeiBoardInitPostMemLib.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..9361c3df3e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPreMemLib.inf @@ -0,0 +1,116 @@ +## @file +# Component information file for PEI WhiskeylakeURvp Board Init Pre-Mem Li= brary +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiBoardInitPreMemLib + FILE_GUID =3D ec3675bc-1470-417d-826e-37378140213d + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D BoardInitLib + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiWhiskeylakeURvpDetect.c + PeiWhiskeylakeURvpInitPreMemLib.c + WhiskeylakeURvpHsioPtssTables.c + PeiBoardInitPreMemLib.c + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/WhiskeylakeO= penBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLi= b.inf new file mode 100644 index 0000000000..4831735dc5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPostMemLib.inf @@ -0,0 +1,202 @@ +## @file +# Component information file for WhiskeylakeURvpInitLib in PEI post memory= phase. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiWhiskeylakeURvpMultiBoardInitLib + FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF9017499280 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D PeiWhiskeylakeURvpMultiBoardInitLibCo= nstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + GpioExpanderLib + PcdLib + MultiBoardInitSupportLib + HdaVerbTableLib + PeiPlatformHookLib + PeiPolicyInitLib + PchInfoLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + SecurityPkg/SecurityPkg.dec + +[Sources] + PeiWhiskeylakeURvpInitPostMemLib.c + PeiMultiBoardInitPostMemLib.c + BoardFunc.c + BoardFuncInit.c + +[FixedPcd] + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel + + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize + + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTable + gBoardModuleTokenSpaceGuid.PcdBoardUcmcGpioTableSize + + #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + # Board Init Table List + + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + + # WWAN Full Card Power Off and reset pins + gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio + gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio + gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio + gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl + gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive + + # PCIE RTD3 GPIO + gBoardModuleTokenSpaceGuid.PcdRootPortDev + gBoardModuleTokenSpaceGuid.PcdRootPortFunc + gBoardModuleTokenSpaceGuid.PcdRootPortIndex + + gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive + + gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive + + gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive + + # CA Vref Configuration + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + + # PCIe Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0 + gBoardModuleTokenSpaceGuid.PcdPcieClock1 + gBoardModuleTokenSpaceGuid.PcdPcieClock2 + gBoardModuleTokenSpaceGuid.PcdPcieClock3 + gBoardModuleTokenSpaceGuid.PcdPcieClock4 + gBoardModuleTokenSpaceGuid.PcdPcieClock5 + gBoardModuleTokenSpaceGuid.PcdPcieClock6 + gBoardModuleTokenSpaceGuid.PcdPcieClock7 + gBoardModuleTokenSpaceGuid.PcdPcieClock8 + gBoardModuleTokenSpaceGuid.PcdPcieClock9 + gBoardModuleTokenSpaceGuid.PcdPcieClock10 + gBoardModuleTokenSpaceGuid.PcdPcieClock11 + gBoardModuleTokenSpaceGuid.PcdPcieClock12 + gBoardModuleTokenSpaceGuid.PcdPcieClock13 + gBoardModuleTokenSpaceGuid.PcdPcieClock14 + gBoardModuleTokenSpaceGuid.PcdPcieClock15 + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + # Pch PmConfig Policy + gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport + + # Misc + gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent + gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable + gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent + gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio + gBoardModuleTokenSpaceGuid.PcdMobileDramPresent + gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable + + + gBoardModuleTokenSpaceGuid.PcdSpdPresent + gBoardModuleTokenSpaceGuid.PcdBoardRev + gBoardModuleTokenSpaceGuid.PcdBoardBomId + gBoardModuleTokenSpaceGuid.PcdPlatformType + gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType + + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2 ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable + gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable + # TPM interrupt + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum + +[Guids] + gAttemptUsbFirstHotkeyInfoHobGuid ## CONSUMES + gCnlPchLpChipsetInitTableDxGuid ## CONSUMES diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/WhiskeylakeOp= enBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.= inf new file mode 100644 index 0000000000..6affc3180e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPreMemLib.inf @@ -0,0 +1,296 @@ +## @file +# Component information file for PEI WhiskeylakeURvp Board Init Pre-Mem Li= brary +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiWhiskeylakeURvpMultiBoardInitPreMe= mLib + FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574F + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D PeiWhiskeylakeURvpMultiBoardInitPreMe= mLibConstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PcdLib + MultiBoardInitSupportLib + StallPpiLib + PchResetLib + PeiPlatformHookLib + PlatformHookLib + PeiPolicyInitLib + OcWdtLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiWhiskeylakeURvpInitPreMemLib.c + WhiskeylakeURvpHsioPtssTables.c + PeiMultiBoardInitPreMemLib.c + PeiWhiskeylakeURvpDetect.c + BoardSaInitPreMemLib.c + BoardPchInitPreMemLib.c + BoardFuncInitPreMem.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid + gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES + gEfiPeiResetPpiGuid ## PRODUCES + +[Guids] + gPchGeneralPreMemConfigGuid ## CONSUMES + gTcoWdtHobGuid ## CONSUMES + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort + + # PCH-LP HSIO PTSS Table + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2 + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable1Size + gBoardModuleTokenSpaceGuid.PcdSpecificLpHsioPtssTable2Size + + # PCH-H HSIO PTSS Table + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1 + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2 + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable1Size + #gBoardModuleTokenSpaceGuid.PcdUnknowHHsioPtssTable2Size + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd + gBoardModuleTokenSpaceGuid.PcdMrcRcompResistor + gBoardModuleTokenSpaceGuid.PcdMrcRcompTarget + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMap + gBoardModuleTokenSpaceGuid.PcdMrcDqByteMapSize + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram + gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize + gBoardModuleTokenSpaceGuid.PcdMrcSpdData + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie0PwrEnableActive + + + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port0Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port1Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port2Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port3Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port4Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port5Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port6Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port7Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port8Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port9Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 + + # Misc + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent + + #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + # Board Init Table List + + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + + # WWAN Full Card Power Off and reset pins + gBoardModuleTokenSpaceGuid.PcdWwanFullCardPowerOffGpio + gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio + gBoardModuleTokenSpaceGuid.PcdWwanPerstGpio + gBoardModuleTokenSpaceGuid.PcdWwanPerstGpioPolarity + + # SA Misc Config + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved + gBoardModuleTokenSpaceGuid.PcdSaDdrFreqLimit + + # Display DDI + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTable ## PRODUCES + gBoardModuleTokenSpaceGuid.PcdSaDisplayConfigTableSize ## PRODUCES + + # PEG Reset By GPIO + gBoardModuleTokenSpaceGuid.PcdPegGpioResetControl + gBoardModuleTokenSpaceGuid.PcdPegGpioResetSupoort + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioPad + gBoardModuleTokenSpaceGuid.PcdPeg0ResetGpioActive + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioPad + gBoardModuleTokenSpaceGuid.PcdPeg3ResetGpioActive + + # PCIE RTD3 GPIO + gBoardModuleTokenSpaceGuid.PcdRootPortDev + gBoardModuleTokenSpaceGuid.PcdRootPortFunc + gBoardModuleTokenSpaceGuid.PcdRootPortIndex + + gBoardModuleTokenSpaceGuid.PcdPcie0GpioSupport + + gBoardModuleTokenSpaceGuid.PcdPcie1GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie1WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie1PwrEnableActive + + gBoardModuleTokenSpaceGuid.PcdPcie2GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie2WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie2PwrEnableActive + + gBoardModuleTokenSpaceGuid.PcdPcie3GpioSupport + gBoardModuleTokenSpaceGuid.PcdPcie3WakeGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3HoldRstActive + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableExpanderNo + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableGpioNo + gBoardModuleTokenSpaceGuid.PcdPcie3PwrEnableActive + + # CA Vref Configuration + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + + # PCIe Clock Info + gBoardModuleTokenSpaceGuid.PcdPcieClock0 + gBoardModuleTokenSpaceGuid.PcdPcieClock1 + gBoardModuleTokenSpaceGuid.PcdPcieClock2 + gBoardModuleTokenSpaceGuid.PcdPcieClock3 + gBoardModuleTokenSpaceGuid.PcdPcieClock4 + gBoardModuleTokenSpaceGuid.PcdPcieClock5 + gBoardModuleTokenSpaceGuid.PcdPcieClock6 + gBoardModuleTokenSpaceGuid.PcdPcieClock7 + gBoardModuleTokenSpaceGuid.PcdPcieClock8 + gBoardModuleTokenSpaceGuid.PcdPcieClock9 + gBoardModuleTokenSpaceGuid.PcdPcieClock10 + gBoardModuleTokenSpaceGuid.PcdPcieClock11 + gBoardModuleTokenSpaceGuid.PcdPcieClock12 + gBoardModuleTokenSpaceGuid.PcdPcieClock13 + gBoardModuleTokenSpaceGuid.PcdPcieClock14 + gBoardModuleTokenSpaceGuid.PcdPcieClock15 + + # USB 2.0 Port AFE + gBoardModuleTokenSpaceGuid.PcdUsb20Port10Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port11Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port12Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port13Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port14Afe + gBoardModuleTokenSpaceGuid.PcdUsb20Port15Afe + + # USB 2.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 + + # USB 3.0 Port Over Current Pin + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 + + # Pch PmConfig Policy + gBoardModuleTokenSpaceGuid.PcdSlpS0VmRuntimeControl + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm070VSupport + gBoardModuleTokenSpaceGuid.PcdSlpS0Vm075VSupport + + # Misc + gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent + gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable + gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent + gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio + gBoardModuleTokenSpaceGuid.PcdMobileDramPresent + gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable + + + gBoardModuleTokenSpaceGuid.PcdSpdPresent + gBoardModuleTokenSpaceGuid.PcdBoardRev + gBoardModuleTokenSpaceGuid.PcdBoardBomId + gBoardModuleTokenSpaceGuid.PcdPlatformType + gBoardModuleTokenSpaceGuid.PcdDualDimmPerChannelBoardType + + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable + gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround ## PRODUCES + gSiPkgTokenSpaceGuid.PcdTcoBaseAddress + + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdMchBaseAddress ## CONSUMES + gSiPkgTokenSpaceGuid.PcdMchMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGdxcBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdGdxcMmioSize ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdApicLocalAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdApicLocalMmioSize ## CONSUMES + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /DxePolicyBoardConfigLib/DxePolicyBoardConfigLib.inf b/Platform/Intel/Whisk= eylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolic= yBoardConfigLib.inf new file mode 100644 index 0000000000..2c9af5b9a3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePol= icyBoardConfigLib/DxePolicyBoardConfigLib.inf @@ -0,0 +1,44 @@ +## @file +# Module Information file for DxePolicyBoardConfigLib Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DxePolicyBoardConfigLib + FILE_GUID =3D 17836E9F-7188-4640-80A3-B4441585FFE9 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + LIBRARY_CLASS =3D DxePolicyUpdateLib|DXE_DRIVER + +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + DxeSaPolicyBoardConfig.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseLib + BaseMemoryLib + PcdLib + DebugLib + HobLib + ConfigBlockLib + +[Guids] + gMemoryDxeConfigGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhiskeylakeOpen= BoardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..079fb70ecb --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPla= tformHookLib/PeiPlatformHooklib.inf @@ -0,0 +1,94 @@ +## @file +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPlatformHookLib + FILE_GUID =3D AD901798-B0DA-4B20-B90C-283F886E76D0 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SEC + +[LibraryClasses] + DebugLib + BaseMemoryLib + IoLib + HobLib + PcdLib + TimerLib + PchCycleDecodingLib + GpioLib + CpuPlatformLib + PeiServicesLib + ConfigBlockLib + PeiSaPolicyLib + GpioExpanderLib + PmcLib + PchPcrLib + PciSegmentLib + GpioCheckConflictLib + +[Packages] + MdePkg/MdePkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdDebugUsbUartEnable ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdMipiCamGpioEnable ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2 ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable2Size ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTableSize ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2 ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdGpioExpanderTable2Size ## CONSU= MES + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableTouchPanel ## CONSU= MES + + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOnEarlyPreMemSize + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMem + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableWwanOffEarlyPreMemSize + + # GPIO Group Tier + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw0 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw1 ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdGpioGroupToGpeDw2 ## CONSUMES + + # Misc + gBoardModuleTokenSpaceGuid.PcdIoExpanderPresent ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdPc8374SioKbcPresent ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdOddPowerInitEnable ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdIvCamInitPresent ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdRecoveryModeGpio ## CONSUMES + gBoardModuleTokenSpaceGuid.PcdCpuVboostEnable ## CONSUMES + + gBoardModuleTokenSpaceGuid.PcdWwanBbrstGpio + gBoardModuleTokenSpaceGuid.PcdPcieWwanEnable + gBoardModuleTokenSpaceGuid.PcdWwanResetWorkaround + +[Sources] + PeiPlatformHooklib.c + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + gSiPolicyPpiGuid ## CONSUMES + +[Guids] + gSaDataHobGuid ## CONSUMES + gEfiGlobalVariableGuid ## CONSUMES + gGpioCheckConflictHobGuid ## CONSUMES + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiPolicyBoardConfigLib.inf b/Platform/Intel/Whisk= eylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolic= yBoardConfigLib.inf new file mode 100644 index 0000000000..65e66ccb62 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiPolicyBoardConfigLib.inf @@ -0,0 +1,70 @@ +## @file +# Module Information file for PeiPolicyBoardConfigLib Library +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiPolicyBoardConfigLib + FILE_GUID =3D B1E959E3-9DCA-4D6F-938C-420C3BF5D820 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D PeiPolicyBoardConfigLib|PEIM PEI_CORE= SEC + +[Sources] + PeiCpuPolicyBoardConfigPreMem.c + PeiCpuPolicyBoardConfig.c + PeiMePolicyBoardConfigPreMem.c + PeiMePolicyBoardConfig.c + PeiPchPolicyBoardConfigPreMem.c + PeiPchPolicyBoardConfig.c + PeiSaPolicyBoardConfigPreMem.c + PeiSaPolicyBoardConfig.c + PeiSiPolicyBoardConfig.c + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + SecurityPkg/SecurityPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + PcdLib + DebugLib + HobLib + ConfigBlockLib + IoLib + BaseCryptLib + BaseMemoryLib + +[Guids] + gCpuSecurityPreMemConfigGuid ## CONSUMES + gMePeiPreMemConfigGuid ## CONSUMES + gPchGeneralPreMemConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gPchGeneralConfigGuid ## CONSUMES + gEfiTpmDeviceInstanceTpm20DtpmGuid + gEfiTpmDeviceInstanceTpm12Guid + +[Ppis] + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES + +[Pcd] + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdDmiBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEpBaseAddress ## CONSUMES + gPlatformModuleTokenSpaceGuid.PcdEdramBaseAddress ## CONSUMES + gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = ## CONSUMES + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardFunc.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whiskeyl= akeURvp/Library/BoardInitLib/BoardFunc.h new file mode 100644 index 0000000000..eca492e72d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFunc.h @@ -0,0 +1,18 @@ +/** @file + Header file for Board Hook function intance. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BOARD_FUNC_H_ +#define _BOARD_FUNC_H_ + +EFI_STATUS +PeiBoardSpecificInitPostMemNull ( + VOID + ); + +#endif // _BOARD_FUNC_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whisk= eylakeURvp/Library/BoardInitLib/BoardInitLib.h new file mode 100644 index 0000000000..5435b4a6e3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardInitLib.h @@ -0,0 +1,20 @@ +/** @file + Header file for board Init function for Post Memory Init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_LIB_H_ +#define _PEI_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include + +#endif // _PEI_BOARD_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardSaConfigPreMem.h b/Platform/Intel/WhiskeylakeOpenBoardPk= g/WhiskeylakeURvp/Library/BoardInitLib/BoardSaConfigPreMem.h new file mode 100644 index 0000000000..41c798a082 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardSaConfigPreMem.h @@ -0,0 +1,90 @@ +/** @file + PEI Boards Configurations for PreMem phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _BOARD_SA_CONFIG_PRE_MEM_H_ +#define _BOARD_SA_CONFIG_PRE_MEM_H_ + +#include +#include // for MRC Configurati= on +#include // for PCIE RTD3 GPIO +#include // for GPIO definition +#include +#include // for Root Port number +#include // for Root Port number + +// +// The following section contains board-specific CMD/CTL/CLK and DQ/DQS ma= pping, needed for LPDDR3/LPDDR4 +// + +// +// DQByteMap[0] - ClkDQByteMap: +// If clock is per rank, program to [0xFF, 0xFF] +// If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] +// If clock is shared by 2 ranks but does not go to all bytes, +// Entry[i] defines which DQ bytes Group i services +// DQByteMap[1] - CmdNDQByteMap: Entry[0] is CmdN/CAA and Entry[1] is CmdN= /CAB +// DQByteMap[2] - CmdSDQByteMap: Entry[0] is CmdS/CAA and Entry[1] is CmdS= /CAB +// DQByteMap[3] - CkeDQByteMap : Entry[0] is CKE /CAA and Entry[1] is CKE = /CAB +// For DDR, DQByteMap[3:1] =3D [0xFF, 0] +// DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] since we have= 1 CTL / rank +// Variable only exists to make the code eas= ier to use +// DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] since we have= 1 CA Vref +// Variable only exists to make the code eas= ier to use +// +// +// DQ byte mapping to CMD/CTL/CLK, from the CPU side - for WHL RVP3, WHL S= DS - used by WHL/WHL MRC +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqByteMapWhlUDdr4Rvp[2][6][2] = =3D { + // Channel 0: + { + { 0x0F, 0xF0 }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4] + { 0x00, 0xF0 }, // CmdN does not have CAA, CAB goes to Bytes[7:4] + { 0x0F, 0xF0 }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4] + { 0x0F, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0xFF, 0x00 } // CA Vref is one for all bytes + }, + // Channel 1: + { + { 0x33, 0xCC }, // CLK0 goes to package 0 - Bytes[3:0], CLK1 goes to p= ackage 1 - Bytes[7:4] + { 0x00, 0xCC }, // CmdN does not have CAA, CAB goes to Bytes[7:4] + { 0x33, 0xCC }, // CmdS CAA goes to Bytes[3:0], CmdS CAB goes to Byte[= 7:4] + { 0x33, 0x00 }, // CKE CAA goes to Bytes[3:0], CKE does not have CAB + { 0xFF, 0x00 }, // CTL (CS) goes to all bytes + { 0xFF, 0x00 } // CA Vref is one for all bytes + } +}; + +// +// DQS byte swizzling between CPU and DRAM +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mDqsMapCpu2DramWhlUDdr4Rvp[2][8]= =3D { + { 0, 1, 3, 2, 4, 5, 6, 7 }, // Channel 0 + { 1, 0, 4, 5, 2, 3, 6, 7 } // Channel 1 +}; + +// +// DQS byte swizzling between CPU and DRAM +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 DqsMapCpu2DramWhlUmDvp[2][8] =3D= { + { 0, 3, 1, 2, 7, 5, 6, 4 }, // Channel 0 + { 0, 2, 1, 3, 6, 4, 7, 5 } // Channel 1 +}; + +// +// Reference RCOMP resistors on motherboard +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorCflUDdr4Interposer= [SA_MRC_MAX_RCOMP] =3D { 121, 81, 100 }; + +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetWhlUDdr4Interposer[S= A_MRC_MAX_RCOMP_TARGETS] =3D { 100, 40, 20, 20, 26 }; + +#endif // _BOARD_SA_CONFIG_PRE_MEM_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/GpioTableDefault.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/W= hiskeylakeURvp/Library/BoardInitLib/GpioTableDefault.h new file mode 100644 index 0000000000..a943d5bd04 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableDefault.h @@ -0,0 +1,225 @@ +/** @file + GPIO definition table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GPIO_TABLE_DEFAULT_H_ +#define _GPIO_TABLE_DEFAULT_H_ + +#include +#include +#include + +#define END_OF_GPIO_TABLE 0xFFFFFFFF + +// +// CNL U DRR4 Board GPIO table configuration is used as default +// + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTableDefault[] =3D +{ +// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, = GPIRoutConfig, PadRstCfg, Term, + //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, + //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_0 + //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_1 + //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_CSB + //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPPC_A6_SERIRQ + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntEdge | GpioIntSci, GpioHostDeepReset, GpioTermWpu= 20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N + //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, + //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwn= Gpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //eSPI_CLK + //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi= oDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTer= mNone }}, + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTerm= Wpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N + // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, Gp= ioTermNone }}, //SLATEMODE_HALLOUT + {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL= _SLOT1 + //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOw= nGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRese= t, GpioTermNone }}, //eSPI_Reset + {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SP= KR_PD_N + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WFC= AM_PWREN + //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SD_PWREN + //(RC control) {GPIO_CNL_LP_GPP_A18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //ACCEL_INT + //(RC control) {GPIO_CNL_LP_GPP_A19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //ALS_INT + //(RC control) {GPIO_CNL_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //HUMAN_PRESENCE_INT + //(RC control) {GPIO_CNL_LP_GPP_A21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //HALL_SENSOR_INT + //(RC control) {GPIO_CNL_LP_GPP_A22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //IVCAM_WAKE + //(RC control) {GPIO_CNL_LP_GPP_A23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermWpu20K }}, //SHARED_INT + //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe= rmNone }}, //CORE_VID0 + //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe= rmNone }}, //CORE_VID0 + {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, Gp= ioPadConfigUnlock | GpioOutputStateUnlock } }, //BT_UART_WAKE + {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, Gp= ioPadConfigUnlock | GpioOutputStateUnlock }}, //FORCE_PAD_INT + {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gpi= oOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioPadConfigUnlock= } }, //BT_DISABLE_N + //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //WWAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //PCIE_NAND_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //LAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //WLAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //PCIE_SLOT1_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ + {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, + //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa= ult, GpioTermNone }}, //PM_SLP_S0_N + //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa= ult, GpioTermNone }}, //PLT_RST_N + {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_= PWR_EN + //(CSME Pad) {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefau= lt, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNon= e }}, //NFC_DFU + { GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, = GpioPadConfigUnlock } }, //FPS_INT_N + { GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, G= pioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnloc= k} }, //FPS_RESET_N + {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TBT_CIO_PWR_EN + //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_CS_FPS + //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_CLK_FPS + //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_MISO_FPS + //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_MOSI_FPS + {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone}}, //E= C_SLP_S0_CS_N + //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //SMB_CLK + //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //SMB_DATA + {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone }}, //WIFI_RF_= KILL_N + //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SML0_CLK + //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SML0_DATA + {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTerm= None, GpioPadConfigUnlock }}, //WIFI_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefaul= t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, + //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefaul= t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, + { GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu2= 0K } }, //CODEC_INT_N + { GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K= , GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N + {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //TBT_= FORCE_PWR + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermWpu2= 0K, GpioPadConfigUnlock } }, //IVCAM_WAKE_N + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NAN= D_RST_N + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_PWREN_N + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_PW= REN_N + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R= ST_N + //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C1_SCL + //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_RXD + //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_TXD + //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_RTS + //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_CTS + //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_CS0_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_CLK_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_MISO + //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_MOSI + //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRes= et, GpioTermNone }}, //IMGCLKOUT + //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C1_SCL + {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL= 2_RST_N + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermN= one, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioPlatformReset, GpioTe= rmWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio,= GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermN= one }}, //NFC_RST_N + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PWREN + {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PN= L_RST_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio,= GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //NFC_INT_N + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNon= e, GpioPadConfigUnlock }}, //WIGIG_WAKE_N + //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_CLK_1 + //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_DATA_1 + //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_CLK_0 + //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_DATA_0 + {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnDefault, GpioD= irInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNon= e }}, //SPI1_TCH_PNL_IO2 + {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnDefault, GpioD= irInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNon= e }}, //SPI1_TCH_PNL_IO3 + //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset,= GpioTermNone }}, //SSP_MCLK + //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, = GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, = GpioTermWpu20K }}, //Reserved for SATA/PCIE detect + //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformRe= set, GpioTermNone }}, //M.2_SSD_DET + {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Rese= rved for SATA HP val + {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone}= }, //EC_SMI_N + {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone= , GpioPadConfigUnlock }}, //DGPU_PWROK + //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla= tformReset, GpioTermNone }}, //SSD_DEVSLP + //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla= tformReset, GpioTermNone }}, //HDD_DEVSLP + {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn= , GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTe= rmNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N + //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefa= ult, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset,= GpioTermNone }}, //SATA_LED_N + //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefa= ult, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gpi= oTermNone }}, //BSSB_CLK + //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDef= ault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, //BSSB_DI + //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //USB_OC_2 + //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //USB_OC_3 + //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_HPD + //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_HPD_EC + //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_HPD + //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI4_HPD + //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //EDP_HPD + //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_CTRL_DATA + //(Not used){GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault= , GpioDirIn, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTe= rmNone }}, //GPP_F0_COEX3 + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SAT= A_HDD_PWREN + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF_C= LK_EN + //(RC control) {GPIO_CNL_LP_GPP_F4, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul= t, GpioTermNone }}, //CNV_BRI_DT_UART0_RTSB + //(RC control) {GPIO_CNL_LP_GPP_F5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul= t, GpioTermNone }}, //CNV_BRI_RSP_UART0_RXD + //(RC control) {GPIO_CNL_LP_GPP_F6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul= t, GpioTermNone }}, //CNV_RGI_DT_UART0_TXD + //(RC control) {GPIO_CNL_LP_GPP_F7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefaul= t, GpioTermNone }}, //CNV_RGI_RSP_UART0_CTSB + {GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDi= rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon= e }}, //CNV_MFUART2_RXD + {GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDi= rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon= e }}, //CNV_MFUART2_TXD + + //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be= used at IsRecoveryMode() + {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermNone}}, //B= IOS_REC + + //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F11_EMMC_CMD + //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F12_EMMC_DATA0 + //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F13_EMMC_DATA1 + //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F14_EMMC_DATA2 + //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F15_EMMC_DATA3 + //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F16_EMMC_DATA4 + //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F17_EMMC_DATA5 + //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F18_EMMC_DATA6 + //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F19_EMMC_DATA7 + //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F20_EMMC_RCLK + //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F21_EMMC_CLK + //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F22_EMMC_RESETB + //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi= oDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTerm= None }}, //GPP_F_23 + //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_0_SD3_CMD + //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P + //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N + //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_3_SD3_D2 + //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_4_SD3_D3 + {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_G_5_SD3_CDB + //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNone }}, //GPP_G_6_SD3_CLK + {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= d20K }}, //GPP_G_7_SD3_WP + //{GPIO_CNL_LP_GPP_H0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPP_H_0_SSP2_SCLK + //{GPIO_CNL_LP_GPP_H1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPP_H_1_SSP2_SFRM + //{GPIO_CNL_LP_GPP_H2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPP_H_2_SSP2_TXD + //{GPIO_CNL_LP_GPP_H3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPP_H_3_SSP2_RXD + //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_4_I2C2_SDA + //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_5_I2C2_SCL + //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_6_I2C3_SDA + //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_7_I2C3_SCL + //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_8_I2C4_SDA + //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_9_I2C4_SCL + {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_PWREN + {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_RECOVERY + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IR= IS_STROBE + {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_MUX_SEL0 + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadU= nlock }}, //UF_CAM_PRIVACY_LED + {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I= VCAM_KEY + //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //DDI4_CTRL_CLK + //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //DDI4_CTRL_DATA + //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOw= nGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //VCCIO_LPM + {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I= VCAM_MUX_SEL1 + //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //IMGCLKOUT_WF_CAM + //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GPP_H21 + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //WF= _CAM_RST + //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GPP_H23 + //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_BATLOW_N + //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //BC_ACOK + //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LAN_WAKE + //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_PWRBTN_N + //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S3_N + //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S4_N + //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //SLP_A_N + //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDi= rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon= e }}, //GPD_7 + //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //SUS_CLK + //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_WLAN_N + //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S5_N + //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LANPHY_EN + {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDir= Default, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd= 20K }}, // 20K PD for PECI +}; + +GLOBAL_REMOVE_IF_UNREFERENCED GPIO_INIT_CONFIG mGpioTablePreMemDefault[] = =3D +{ + {END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, = GpioOutDefault, GpioIntDis, GpioDswReset, GpioTermNone}},//Marking End of= Table +}; + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/GpioTableWhlUDdr4.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/= WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4.h new file mode 100644 index 0000000000..86b7cb3717 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableWhlUDdr4.h @@ -0,0 +1,284 @@ +/** @file + GPIO definition table for WhiskeyLake U Ddr4 RVP + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ +#define _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ + +#include +#include +#include + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4_0[] =3D +{ +// Pmode, GPI_IS, GpioDir, GPIOTxState, RxEvCfg, = GPIRoutConfig, PadRstCfg, Term, + //{GPIO_CNL_LP_GPP_A0, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, + //{GPIO_CNL_LP_GPP_A1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_0 + //{GPIO_CNL_LP_GPP_A2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_1 + //{GPIO_CNL_LP_GPP_A3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A4, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_IO_2 + //{GPIO_CNL_LP_GPP_A5, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //eSPI_CSB + //{GPIO_CNL_LP_GPP_A6, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, //GPPC_A6_SERIRQ + // TPM interrupt + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K,= GpioPadConfigUnlock }}, //SPI_TPM_INT_N + //{GPIO_CNL_LP_GPP_A8, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTerm= None }}, + //(Default HW) {GPIO_CNL_LP_GPP_A9, { GpioPadModeNative2, GpioHostOwn= Gpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //eSPI_CLK + //{GPIO_CNL_LP_GPP_A10, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi= oDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTer= mNone }}, + //{GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= Inv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTe= rmWpu20K, GpioPadConfigUnlock }}, //WWAN_WAKE_N + // (RC control) {GPIO_CNL_LP_GPP_A12, { GpioPadModeNative2, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, Gp= ioTermNone }}, //SLATEMODE_HALLOUT + {GPIO_CNL_LP_GPP_A13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone } }, //DGPU_SEL= _SLOT1 + //(Default HW) {GPIO_CNL_LP_GPP_A14, { GpioPadModeNative2, GpioHostOw= nGpio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRese= t, GpioTermNone }}, //eSPI_Reset + {GPIO_CNL_LP_GPP_A15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //SP= KR_PD_N + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K, GpioPadUnlock = }}, //WFCAM_PWREN + //(RC control) {GPIO_CNL_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SD_PWREN + //A18-A23 -> Under GPIO table for GPIO Termination -20K WPU + {GPIO_CNL_LP_GPP_A18, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //ACCEL_INT + {GPIO_CNL_LP_GPP_A19, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //ALS_INT + {GPIO_CNL_LP_GPP_A20, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //HUMAN_PRESENCE_INT + {GPIO_CNL_LP_GPP_A21, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //HALL_SENSOR_INT + {GPIO_CNL_LP_GPP_A22, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //IVCAM_WAKE + {GPIO_CNL_LP_GPP_A23, { GpioHardwareDefault, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //SHARED_INT + //(Not used) {GPIO_CNL_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe= rmNone }}, //CORE_VID0 + //(Not used) {GPIO_CNL_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirOut, GpioOutDefault, GpioIntDis, GpioResetDefault, GpioTe= rmNone }}, //CORE_VID0 + {GPIO_CNL_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermNone, Gp= ioPadUnlock } }, //BT_UART_WAKE + {GPIO_CNL_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpio= OutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, Gp= ioPadUnlock }}, //FORCE_PAD_INT + {GPIO_CNL_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gpi= oOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone , GpioOutputStateUnlo= ck} }, //BT_DISABLE_N + //(RC control) {GPIO_CNL_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //WWAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //PCIE_NAND_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //LAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //WLAN_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //PCIE_SLOT1_CLK_REQ + //(RC control) {GPIO_CNL_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //PCIE_SLOT2_CLK_REQ + {GPIO_CNL_LP_GPP_B11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, + //(Default HW) {GPIO_CNL_LP_GPP_B12, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa= ult, GpioTermNone }}, //PM_SLP_S0_N + //(Default HW) {GPIO_CNL_LP_GPP_B13, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefa= ult, GpioTermNone }}, //PLT_RST_N + {GPIO_CNL_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //TCH_PNL_= PWR_EN + //B15 -Unused pin -> Under GPIO table for GPIO Termination - Input sensi= ng disable + {GPIO_CNL_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNo= ne, GpioOutHigh, GpioIntLevel, GpioResumeReset, GpioTermNone }}, //For= mer NFC_DFU + {GPIO_CNL_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gpi= oOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTermNone, G= pioPadConfigUnlock } }, //FPS_INT_N + {GPIO_CNL_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigUnlock= } }, //FPS_RESET_N + {GPIO_CNL_LP_GPP_B18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, Gp= ioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TBT_CIO_PWR_EN + //(RC control) {GPIO_CNL_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_CS_FPS + //(RC control) {GPIO_CNL_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_CLK_FPS + //(RC control) {GPIO_CNL_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_MISO_FPS + //(RC control) {GPIO_CNL_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GSPI1_MOSI_FPS + {GPIO_CNL_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTermNone, GpioPa= dUnlock }}, //EC_SLP_S0_CS_N + //(RC control) {GPIO_CNL_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //SMB_CLK + //(RC control) {GPIO_CNL_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset= , GpioTermNone }}, //SMB_DATA + {GPIO_CNL_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNone, GpioOutputStat= eUnlock }}, //WIFI_RF_KILL_N + //(CSME Pad) {GPIO_CNL_LP_GPP_C3, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SML0_CLK + //(CSME Pad) {GPIO_CNL_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, = GpioTermNone }}, //SML0_DATA + {GPIO_CNL_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTerm= None, GpioPadConfigUnlock }}, //WIFI_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnDefaul= t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, + //(Not used) {GPIO_CNL_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnDefaul= t, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, + { GPIO_CNL_LP_GPP_C8, { GpioPadModeGpio, GpioHostOwnAcpi , GpioDirIn , G= pioOutDefault , GpioIntLevel | GpioIntApic , GpioPlatformReset, GpioTermWpu= 20K } }, //CODEC_INT_N + { GPIO_CNL_LP_GPP_C9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault, GpioIntEdge | GpioIntSci, GpioPlatformReset, GpioTermWpu20K= , GpioPadConfigUnlock }}, //TBT_CIO_PLUG_EVENT_N + {GPIO_CNL_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadUn= lock }}, //TBT_FORCE_PWR + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,= GpioOutDefault, GpioIntLevel | GpioIntSci, GpioHostDeepReset, GpioTermWpu2= 0K, GpioPadConfigUnlock } }, //IVCAM_WAKE_N + //move to premem phase for early power turn on + // {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir= Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE= _NAND_RST_N + // {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir= Out, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCI= E_NAND_PWREN_N + // {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir= Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT= 1_PWREN_N + // {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDir= Out, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT= 1_RST_N + + //Only clear Reset pins in Post-Mem + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_RST_N + //{GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1= _RST_N + + //(RC control) {GPIO_CNL_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //I2C1_SCL + //(RC control) {GPIO_CNL_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_RXD + //(RC control) {GPIO_CNL_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_TXD + //(RC control) {GPIO_CNL_LP_GPP_C22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_RTS + //(RC control) {GPIO_CNL_LP_GPP_C23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //UART2_CTS + //(CSME Pad) {GPIO_CNL_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_CS0_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_CLK_N + //(CSME Pad) {GPIO_CNL_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_MISO + //(CSME Pad) {GPIO_CNL_LP_GPP_D3, { GpioPadModeNative1, GpioHostOwnDef= ault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //SPI1_TCH_PNL_MOSI + //(RC control) {GPIO_CNL_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRes= et, GpioTermNone }}, //IMGCLKOUT + //(RC control) {GPIO_CNL_LP_GPP_D5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C0_SDA + //(RC control) {GPIO_CNL_LP_GPP_D6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C0_SCL + //(RC control) {GPIO_CNL_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C1_SDA + //(RC control) {GPIO_CNL_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset= , GpioTermNone }}, //ISH_I2C1_SCL + {GPIO_CNL_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PNL= 2_RST_N + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntEdge | GpioIntApic, GpioPlatformReset, GpioTermN= one, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + {GPIO_CNL_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v , GpioOutDefault, GpioIntLevel| GpioIntSci, GpioHostDeepReset, GpioTe= rmWpu20K, GpioPadConfigUnlock }}, //SLOT1_WAKE_N + //(Not used) {GPIO_CNL_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio,= GpioDirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermN= one }}, //Former NFC_RST_N + //{GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone }}, //WWAN_PW= REN + {GPIO_CNL_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone }}, //TCH_PN= L_RST_N + //(Not used) {GPIO_CNL_LP_GPP_D15, { GpioPadModeGpio, GpioHostOwnGpio,= GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //Former NFC_INT_N + //{GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn= , GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermN= one, GpioPadConfigUnlock }}, //WIGIG_WAKE_N + //(RC control) {GPIO_CNL_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_CLK_1 + //(RC control) {GPIO_CNL_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_DATA_1 + //(RC control) {GPIO_CNL_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_CLK_0 + //(RC control) {GPIO_CNL_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //DMIC_DATA_0 + //(CSME control) {GPIO_CNL_LP_GPP_D21, { GpioPadModeNative1, GpioHostO= wnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //SPI1_TCH_PNL_IO2 + //(CSME control) {GPIO_CNL_LP_GPP_D22, { GpioPadModeNative1, GpioHostO= wnDefault, GpioDirInOut, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //SPI1_TCH_PNL_IO3 + //(RC control) {GPIO_CNL_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioHostDeepReset,= GpioTermNone }}, //SSP_MCLK + //(Not used) {GPIO_CNL_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, = GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, = GpioTermWpu20K }}, //Reserved for SATA/PCIE detect + //(RC control) {GPIO_CNL_LP_GPP_E1, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformRe= set, GpioTermNone }}, //M.2_SSD_DET + {GPIO_CNL_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermWpu20K}}, //Rese= rved for SATA HP val + {GPIO_CNL_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntEdge|GpioIntSmi, GpioPlatformReset, GpioTermNone,= GpioPadUnlock}}, //EC_SMI_N + {GPIO_CNL_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntLevel|GpioIntSci, GpioPlatformReset, GpioTermNone= , GpioPadConfigUnlock }}, //DGPU_PWROK + //(RC control) {GPIO_CNL_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla= tformReset, GpioTermNone }}, //SSD_DEVSLP + //(RC control) {GPIO_CNL_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnD= efault, GpioDirIn, GpioOutDefault, GpioIntLevel|GpioIntDefault, GpioPla= tformReset, GpioTermNone }}, //HDD_DEVSLP + {GPIO_CNL_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn= , GpioOutDefault, GpioIntEdge|GpioIntDefault, GpioPlatformReset, GpioTe= rmNone, GpioPadConfigUnlock }}, //TCH_PNL_INT_N + //(RC control) {GPIO_CNL_LP_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefa= ult, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformReset,= GpioTermNone }}, //SATA_LED_N + //(RC control) {GPIO_CNL_LP_GPP_E9, { GpioPadModeGpio, GpioHostOwnDefa= ult, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gpi= oTermNone }}, //BSSB_CLK + //(RC control) {GPIO_CNL_LP_GPP_E10, { GpioPadModeGpio, GpioHostOwnDef= ault, GpioDirIn, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, Gp= ioTermNone }}, //BSSB_DI + //(RC control) {GPIO_CNL_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //USB_OC_2 + //(RC control) {GPIO_CNL_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioHostDeepRe= set, GpioTermNone }}, //USB_OC_3 + //(RC control) {GPIO_CNL_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_HPD + //(RC control) {GPIO_CNL_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_HPD_EC + //(RC control) {GPIO_CNL_LP_GPP_E15, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_HPD + //(RC control) {GPIO_CNL_LP_GPP_E16, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI4_HPD + //(RC control) {GPIO_CNL_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //EDP_HPD + //(RC control) {GPIO_CNL_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI1_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI2_CTRL_DATA + //(RC control) {GPIO_CNL_LP_GPP_E22, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_CTRL_CLK + //(RC control) {GPIO_CNL_LP_GPP_E23, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //DDI3_CTRL_DATA + //F0- unused pin-Input Sensing disable F4-F7 -> Under GPIO table for GP= IO Termination -20K WPU + {GPIO_CNL_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirNo= ne, GpioOutHigh, GpioIntLevel, GpioResumeReset, GpioTermNone }}, //GPP= _F0_COEX3 + //{GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermWpu20K }}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K }}, //S= ATA_HDD_PWREN + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, = GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K, GpioPadU= nlock }}, //WF_CLK_EN + {GPIO_CNL_LP_GPP_F4, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //CNV_BRI_DT_UART0_RTSB + {GPIO_CNL_LP_GPP_F5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //CNV_BRI_RSP_UART0_RXD + {GPIO_CNL_LP_GPP_F6, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //CNV_RGI_DT_UART0_TXD + {GPIO_CNL_LP_GPP_F7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //CNV_RGI_RSP_UART0_CTSB + //{GPIO_CNL_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //CNV_MFUART2_RXD + //{GPIO_CNL_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermW= pu20K }}, //CNV_MFUART2_TXD + + //Also need to assign same GPIO pin to PcdRecoveryModeGpio which will be= used at IsRecoveryMode() + {GPIO_CNL_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, = GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTermWpu20K}}, /= /BIOS_REC + + //(RC control) {GPIO_CNL_LP_GPP_F11, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F11_EMMC_CMD + //(RC control) {GPIO_CNL_LP_GPP_F12, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F12_EMMC_DATA0 + //(RC control) {GPIO_CNL_LP_GPP_F13, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F13_EMMC_DATA1 + //(RC control) {GPIO_CNL_LP_GPP_F14, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F14_EMMC_DATA2 + //(RC control) {GPIO_CNL_LP_GPP_F15, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F15_EMMC_DATA3 + //(RC control) {GPIO_CNL_LP_GPP_F16, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F16_EMMC_DATA4 + //(RC control) {GPIO_CNL_LP_GPP_F17, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F17_EMMC_DATA5 + //(RC control) {GPIO_CNL_LP_GPP_F18, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F18_EMMC_DATA6 + //(RC control) {GPIO_CNL_LP_GPP_F19, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F19_EMMC_DATA7 + //(RC control) {GPIO_CNL_LP_GPP_F20, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F20_EMMC_RCLK + //(RC control) {GPIO_CNL_LP_GPP_F21, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F21_EMMC_CLK + //(RC control) {GPIO_CNL_LP_GPP_F22, { GpioPadModeNative1, GpioHostOw= nDefault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformR= eset, GpioTermNone }}, //GPP_F22_EMMC_RESETB + //{GPIO_CNL_LP_GPP_F23, { GpioPadModeNotUsed, GpioHostOwnDefault, Gpi= oDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTerm= None }}, //GPP_F_23 + //(RC control) {GPIO_CNL_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_0_SD3_CMD + //(RC control) {GPIO_CNL_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_1_SD3_D0_SD4_RCLK_P + //(RC control) {GPIO_CNL_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_2_SD3_D1_SD4_RCLK_N + //(RC control) {GPIO_CNL_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_3_SD3_D2 + //(RC control) {GPIO_CNL_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNative }}, //GPP_G_4_SD3_D3 + {GPIO_CNL_LP_GPP_G5, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_G_5_SD3_CDB + //(Default HW) {GPIO_CNL_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefau= lt, GpioTermNone }}, //GPP_G_6_SD3_CLK + {GPIO_CNL_LP_GPP_G7, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= d20K }}, //GPP_G_7_SD3_WP + //H0-H3 -> Under GPIO table for GPIO Termination -20K WPU + {GPIO_CNL_LP_GPP_H0, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_H_0_SSP2_SCLK + {GPIO_CNL_LP_GPP_H1, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_H_1_SSP2_SFRM + {GPIO_CNL_LP_GPP_H2, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_H_2_SSP2_TXD + {GPIO_CNL_LP_GPP_H3, { GpioHardwareDefault, GpioHostOwnDefault, GpioD= irDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermWp= u20K }}, //GPP_H_3_SSP2_RXD + //(RC control) {GPIO_CNL_LP_GPP_H4, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_4_I2C2_SDA + //(RC control) {GPIO_CNL_LP_GPP_H5, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_5_I2C2_SCL + //(RC control) {GPIO_CNL_LP_GPP_H6, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_6_I2C3_SDA + //(RC control) {GPIO_CNL_LP_GPP_H7, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_7_I2C3_SCL + //(RC control) {GPIO_CNL_LP_GPP_H8, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_8_I2C4_SDA + //(RC control) {GPIO_CNL_LP_GPP_H9, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //GPP_H_9_I2C4_SCL + {GPIO_CNL_LP_GPP_H10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_PWREN + {GPIO_CNL_LP_GPP_H11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_RECOVERY + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IR= IS_STROBE + {GPIO_CNL_LP_GPP_H13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //IV= CAM_MUX_SEL0 + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadU= nlock }}, //UF_CAM_PRIVACY_LED + {GPIO_CNL_LP_GPP_H15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I= VCAM_KEY + //(Not used) {GPIO_CNL_LP_GPP_H16, { GpioPadModeNative1, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //DDI4_CTRL_CLK + //(Not used) {GPIO_CNL_LP_GPP_H17, { GpioPadModeNative1, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //DDI4_CTRL_DATA + //(Default HW) {GPIO_CNL_LP_GPP_H18, { GpioPadModeNative1, GpioHostOw= nGpio, GpioDirOut, GpioOutDefault, GpioIntDefault, GpioPlatformReset, = GpioTermNone }}, //VCCIO_LPM + {GPIO_CNL_LP_GPP_H19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone }}, //I= VCAM_MUX_SEL1 + //(RC control) {GPIO_CNL_LP_GPP_H20, { GpioPadModeNative1, GpioHostOwn= Default, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRe= set, GpioTermNone }}, //IMGCLKOUT_WF_CAM + //(Not used) {GPIO_CNL_LP_GPP_H21, { GpioPadModeNotUsed, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GPP_H21 + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTermNone, GpioPadU= nlock }}, //WF_CAM_RST + //(Not used) {GPIO_CNL_LP_GPP_H23, { GpioPadModeNotUsed, GpioHostOwnDe= fault, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioPlatformRese= t, GpioTermNone }}, //GPP_H23 + //(Default HW) {GPIO_CNL_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_BATLOW_N + //(Default HW) {GPIO_CNL_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //BC_ACOK + //(Default HW) {GPIO_CNL_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LAN_WAKE + //(Default HW) {GPIO_CNL_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_PWRBTN_N + //(Default HW) {GPIO_CNL_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S3_N + //(Default HW) {GPIO_CNL_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S4_N + //(Default HW) {GPIO_CNL_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //SLP_A_N + //{GPIO_CNL_LP_GPD7, { GpioPadModeNotUsed, GpioHostOwnDefault, GpioDi= rDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, GpioTermNon= e }}, //GPD_7 + //(Default HW) {GPIO_CNL_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //SUS_CLK + //(Default HW) {GPIO_CNL_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGp= io, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_WLAN_N + //(Default HW) {GPIO_CNL_LP_GPD10, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //PM_SLP_S5_N + //(Default HW) {GPIO_CNL_LP_GPD11, { GpioPadModeNative1, GpioHostOwnG= pio, GpioDirDefault, GpioOutDefault, GpioIntDefault, GpioResetDefault, = GpioTermNone }}, //LANPHY_EN + {GPIO_CNL_LP_PECI, { GpioHardwareDefault, GpioHostOwnDefault, GpioDir= Default, GpioOutDefault, GpioIntDefault, GpioHostDeepReset, GpioTermWpd= 20K }}, // 20K PD for PECI +}; + +static GPIO_INIT_CONFIG mGpioTableCflUDdr4[] =3D { + // Pmode, GPI_IS, GpioD= ir, GPIOTxState, RxEvCfg/GPIRoutConfig, PadRstCfg, = Term, + // WiGig start + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, Gpio= DirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, G= pioTermWpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, Gpio= DirOut, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, G= pioTermWpu20K }}, //M.2_WIGIG_RF_KILL_N / IVCAM_WAKE_N on CNL U + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDi= rInInv, GpioOutHigh, GpioIntLevel | GpioIntSci, GpioHostDeepReset, G= pioTermNone, GpioPadConfigUnlock }}, //WIGIG_PEWAKE_R_N / WF_CAM_RST on CN= L U + //WiGig end + // Camera start + {GPIO_CNL_LP_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirD= efault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, G= pioTermNone }}, //Camera / RC Control on CNL U + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, Gpio= DirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, G= pioTermNone }}, //Camera / IRIS_STROBE on CNL U + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, Gpio= DirOut, GpioOutHigh, GpioIntDefault, GpioPlatformReset, G= pioTermNone }}, //Camera / UF_CAM_PRIVACY_LED on CNL U + {GPIO_CNL_LP_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirD= efault, GpioOutDefault, GpioIntDefault, GpioPlatformReset, G= pioTermNone }}, //Camera / RC Control on CNL U + // Camera end + // Touch start + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDi= rInInv, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, G= pioTermWpu20K, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + // Touch end + {GPIO_CNL_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDi= rInInv, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, G= pioTermWpu20K, GpioPadConfigUnlock }}, //SMC_RUNTIME_SCI_N + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, G= pioTermNone}}, //SLOT1_RST_N + // TPM interrupt + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, Gpi= oDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, G= pioTermWpu20K, GpioPadConfigUnlock } }, //SPI_TPM_INT_N = = // Unused start + {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, G= pioTermNone }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, G= pioTermNone }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, G= pioTermNone }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, G= pioTermWpu20K }}, //Unused so disabled / WF_CLK_EN on CNL U + {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, G= pioTermNone }}, //Unused so disabled / Not used on CNL U + {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioD= irNone, GpioOutDefault, GpioIntDis, GpioPlatformReset, G= pioTermNone }} //Unused so disabled / Not used on CNL U + // Unused end +}; + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4[] =3D { + // Pmode, GPI_IS, GpioD= ir, GPIOTxState, RxEvCfg/GPIRoutConfig, PadRstCfg, = Term, + // WiGig start + {GPIO_CNL_LP_GPP_A16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTerm= Wpu20K }}, //M.2_WIGIG_PWREN / WFCAM_PWREN on CNL U + {GPIO_CNL_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioHostDeepReset, GpioTerm= Wpu20K }}, //M.2_WIGIG_RF_KILL_N / IVCAM_WAKE_N on CNL U + // WiGig end + // Camera start + {GPIO_CNL_LP_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirDefaul= t, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTerm= None }}, //Camera / RC Control on CNL U + {GPIO_CNL_LP_GPP_H12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTerm= None }}, //Camera / IRIS_STROBE on CNL U + {GPIO_CNL_LP_GPP_H14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDefault, GpioPlatformReset, GpioTerm= None }}, //Camera / UF_CAM_PRIVACY_LED on CNL U + {GPIO_CNL_LP_GPP_H20, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirDefaul= t, GpioOutDefault, GpioIntDefault, GpioPlatformReset, GpioTerm= None }}, //Camera / RC Control on CNL U + // Camera end + // Touch start + {GPIO_CNL_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioPlatformReset, GpioTerm= Wpu20K, GpioPadConfigUnlock }}, //TCH_PNL2_INT_N + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTerm= None}}, //SLOT1_RST_N + // Touch end + {GPIO_CNL_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel | GpioIntSci, GpioPlatformReset, GpioTerm= Wpu20K, GpioPadConfigUnlock }}, //SMC_RUNTIME_SCI_N + // TBT start + {GPIO_CNL_LP_GPP_H22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOu= t, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTerm= None }}, //TBT_CIO_PWR_EN + // TBT end + // TPM interrupt + {GPIO_CNL_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirI= n, GpioOutDefault, GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTerm= Wpu20K, GpioPadConfigUnlock }}, //SPI_TPM_INT_N + // Unused start + {GPIO_CNL_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTerm= None }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTerm= None }}, //Unused so disabled / RC Control on CNL U + {GPIO_CNL_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNon= e, GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTerm= Wpu20K }} //Unused so disabled / WF_CLK_EN on CNL U + // Unused end +}; + + +#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/GpioTableWhlUDdr4PreMem.h b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/WhiskeylakeURvp/Library/BoardInitLib/GpioTableWhlUDdr4PreMem.h new file mode 100644 index 0000000000..01a6599564 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/GpioTableWhlUDdr4PreMem.h @@ -0,0 +1,59 @@ +/** @file + GPIO definition table for WhiskeyLake U Ddr4 RVP Pre-Memory + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ +#define _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ + +#include +#include +#include + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4PreMem[] =3D +{ + {GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_R= ST_N + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_P= WREN_N + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_RST_N + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_PWREN_N +}; + +static GPIO_INIT_CONFIG mGpioTableWhlTbtRvpPreMem[] =3D +{ + // do not reset SLOT1 due to TR AIC card cannot be reset in S3/S4 resume. + //{GPIO_CNL_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOu= t, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1= _RST_N + {GPIO_CNL_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //SLOT1_P= WREN_N + {GPIO_CNL_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_RST_N + {GPIO_CNL_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone}}, //PCIE_NA= ND_PWREN_N +}; + + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOnEarlyPreMem[] =3D +{ + // Turn on WWAN power and de-assert reset pins by default + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu2= 0K, GpioPadConfigUnlock}}, //WWAN_WAKE_N + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_FCP_OFF + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS + {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_PERST + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL + {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_DISABLE_N +}; + +static GPIO_INIT_CONFIG mGpioTableWhlUDdr4WwanOffEarlyPreMem[] =3D +{ + // Assert reset pins and then turn off WWAN power + {GPIO_CNL_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermWpu2= 0K, GpioPadConfigUnlock}}, //WWAN_WAKE_N + {GPIO_CNL_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_FCP_OFF + {GPIO_CNL_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_RST_N + {GPIO_CNL_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_PERST + {GPIO_CNL_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutLow, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //EN_V3.3A_WWAN_LS + {GPIO_CNL_LP_GPP_H16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_WAKE_CTRL + {GPIO_CNL_LP_GPP_H17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioResumeReset, GpioTermNone= , GpioOutputStateUnlock}}, //WWAN_DISABLE_N +}; + +#endif // _CANNONLAKE_U_DDR4_GPIO_TABLE_PRE_MEM_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PchHdaVerbTables.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/W= hiskeylakeURvp/Library/BoardInitLib/PchHdaVerbTables.h new file mode 100644 index 0000000000..0d26e8ad7a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PchHdaVerbTables.h @@ -0,0 +1,3014 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_HDA_VERB_TABLES_H_ +#define _PCH_HDA_VERB_TABLES_H_ + +#include + +HDAUDIO_VERB_TABLE HdaVerbTableDisplayAudio =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: CFL Display Audio Codec + // Revision ID =3D 0xFF + // Codec Vendor: 0x8086280B + // + 0x8086, 0x280B, + 0xFF, 0xFF, + // + // Display Audio Verb Table + // + // For GEN9, the Vendor Node ID is 08h + // Port to be exposed to the inbox driver in the vanilla mode: PORT C - = BIT[7:6] =3D 01b + 0x00878140, + // Pin Widget 5 - PORT B - Configuration Default: 0x18560010 + 0x00571C10, + 0x00571D00, + 0x00571E56, + 0x00571F18, + // Pin Widget 6 - PORT C - Configuration Default: 0x18560020 + 0x00671C20, + 0x00671D00, + 0x00671E56, + 0x00671F18, + // Pin Widget 7 - PORT D - Configuration Default: 0x18560030 + 0x00771C30, + 0x00771D00, + 0x00771E56, + 0x00771F18, + // Disable the third converter and third Pin (NID 08h) + 0x00878140 +); + +// +//codecs verb tables +// +HDAUDIO_VERB_TABLE HdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40622005 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D20, + 0x01D71E62, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B, + + + //Widget node 0X20 for ALC1305 20160603 update + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + // + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401FA, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204DE23, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403F5, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x0204AF1B, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E0A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204368E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204800F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02044848, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050000, + 0x02043330, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050000, + 0x02043333, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x020402EC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02044909, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x020440B0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040047, + 0x02050028, + 0x02040C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040048, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040049, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004A, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040001, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024 +); // HdaVerbTableAlc700 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc701 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC701) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0701 + // + 0x10EC, 0x0701, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC701 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0701&SUBSYS_10EC1124 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11030 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40610041 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211020 + // NID 0x29 : 0x411111F0 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC1124 + 0x00172024, + 0x00172111, + 0x001722EC, + 0x00172310, + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C30, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C41, + 0x01D71D00, + 0x01D71E61, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 1 : + 0x05850000, + 0x05843888, + 0x0205006F, + 0x02042C0B +); // HdaVerbTableAlc701 + +HDAUDIO_VERB_TABLE HdaVerbTableAlc274 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC274) + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0274 + // + 0x10EC, 0x0274, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.0 + //Realtek HD Audio Codec : ALC274 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0274&SUBSYS_10EC10F6 + //The number of verb command block : 16 + + // NID 0x12 : 0x40000000 + // NID 0x13 : 0x411111F0 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x411111F0 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A11020 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40451B05 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x04211010 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //,DA Codec Subsystem ID : 0x10EC10F6 + 0x001720F6, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C00, + 0x01271D00, + 0x01271E00, + 0x01271F40, + //Pin widget 0x13 - DMIC + 0x01371CF0, + 0x01371D11, + 0x01371E11, + 0x01371F41, + //Pin widget 0x14 - NPC + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S_OUT2 + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S_OUT1 + 0x01771CF0, + 0x01771D11, + 0x01771E11, + 0x01771F41, + //Pin widget 0x18 - I2S_IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C20, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C05, + 0x01D71D1B, + 0x01D71E45, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C10, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Widget node 0x20 : + 0x02050045, + 0x02045289, + 0x0205006F, + 0x02042C0B, + //Widget node 0x20 - 1 : + 0x02050035, + 0x02048968, + 0x05B50001, + 0x05B48540, + //Widget node 0x20 - 2 : + 0x05850000, + 0x05843888, + 0x05850000, + 0x05843888, + //Widget node 0x20 - 3 : + 0x0205004A, + 0x0204201B, + 0x0205004A, + 0x0204201B +); //HdaVerbTableAlc274 + +// +// CFL S Audio Codec +// +STATIC HDAUDIO_VERB_TABLE CflSHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_IN= IT ( + // + // VerbTable: (Realtek ALC700) CFL S RVP + // Revision ID =3D 0xff + // Codec Verb Table + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC112C + //The number of verb command block : 17 + + // NID 0x12 : 0x90A60130 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x03011010 + // NID 0x17 : 0x90170120 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x04A1103E + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x03A11040 + // NID 0x1D : 0x40600001 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x0421102F + // NID 0x29 : 0x411111F0 + + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC112C + 0x0017202C, + 0x00172111, + 0x001722EC, + 0x00172310, + + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271C30, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671C10, + 0x01671D10, + 0x01671E01, + 0x01671F03, + //Pin widget 0x17 - I2S-OUT + 0x01771C20, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C3E, + 0x01971D10, + 0x01971EA1, + 0x01971F04, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71C40, + 0x01B71D10, + 0x01B71EA1, + 0x01B71F03, + //Pin widget 0x1D - PC-BEEP + 0x01D71C01, + 0x01D71D00, + 0x01D71E60, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C2F, + 0x02171D10, + 0x02171E21, + 0x02171F04, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + //Widget node 0x20 - 1 : LINE2-VREFO( MIC2-vrefo-R) base on verb_707h of= NID 1Bh , HP-JD gating MIC2-vrefo-L, bypass DAC02 DRE(NID5B bit14) + 0x0205006B, + 0x02044260, + 0x0205006B, + 0x02044260, + //Widget node 0x20 - 2 : //remove NID 58 realted setting for ALC700 + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + //Widget node 0x20 -3 : MIC2-Vrefo-R and MIC2-vrefo-L to independent co= ntrol + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + //Widget node 0x20 - 4 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + //Widget node 0x20 - 5 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + + //Widget node 0X20 for ALC1305 20181023 update 2W/4ohm to remove ALC= 1305 EQ setting + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x02042213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204C22E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); + + +// +// WHL codecs verb tables +// +HDAUDIO_VERB_TABLE WhlHdaVerbTableAlc700 =3D HDAUDIO_VERB_TABLE_INIT ( + // + // VerbTable: (Realtek ALC700) WHL RVP + // Revision ID =3D 0xff + // Codec Verb Table for WHL PCH boards + // Codec Address: CAd value (0/1/2) + // Codec Vendor: 0x10EC0700 + // + 0x10EC, 0x0700, + 0xFF, 0xFF, + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + // + // Realtek Semiconductor Corp. + // + //=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D + + //Realtek High Definition Audio Configuration - Version : 5.0.3.1 + //Realtek HD Audio Codec : ALC700 + //PCI PnP ID : PCI\VEN_8086&DEV_2668&SUBSYS_72708086 + //HDA Codec PnP ID : HDAUDIO\FUNC_01&VEN_10EC&DEV_0700&SUBSYS_10EC10F2 + //The number of verb command block : 17 + + // NID 0x12 : 0x411111F0 + // NID 0x13 : 0x40000000 + // NID 0x14 : 0x411111F0 + // NID 0x15 : 0x411111F0 + // NID 0x16 : 0x411111F0 + // NID 0x17 : 0x90170110 + // NID 0x18 : 0x411111F0 + // NID 0x19 : 0x02A19040 + // NID 0x1A : 0x411111F0 + // NID 0x1B : 0x411111F0 + // NID 0x1D : 0x40638029 + // NID 0x1E : 0x411111F0 + // NID 0x1F : 0x411111F0 + // NID 0x21 : 0x02211020 + // NID 0x29 : 0x411111F0 + + //=3D=3D=3D=3D=3D HDA Codec Subsystem ID Verb-table =3D=3D=3D=3D=3D + //HDA Codec Subsystem ID : 0x10EC10F2 + 0x001720F2, + 0x00172110, + 0x001722EC, + 0x00172310, + + //=3D=3D=3D=3D=3D Pin Widget Verb-table =3D=3D=3D=3D=3D + //Widget node 0x01 : + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + 0x0017FF00, + //Pin widget 0x12 - DMIC + 0x01271CF0, + 0x01271D11, + 0x01271E11, + 0x01271F41, + //Pin widget 0x13 - DMIC + 0x01371C00, + 0x01371D00, + 0x01371E00, + 0x01371F40, + //Pin widget 0x14 - FRONT (Port-D) + 0x01471CF0, + 0x01471D11, + 0x01471E11, + 0x01471F41, + //Pin widget 0x15 - I2S-OUT + 0x01571CF0, + 0x01571D11, + 0x01571E11, + 0x01571F41, + //Pin widget 0x16 - LINE3 (Port-B) + 0x01671CF0, + 0x01671D11, + 0x01671E11, + 0x01671F41, + //Pin widget 0x17 - I2S-OUT + 0x01771C10, + 0x01771D01, + 0x01771E17, + 0x01771F90, + //Pin widget 0x18 - I2S-IN + 0x01871CF0, + 0x01871D11, + 0x01871E11, + 0x01871F41, + //Pin widget 0x19 - MIC2 (Port-F) + 0x01971C40, + 0x01971D90, + 0x01971EA1, + 0x01971F02, + //Pin widget 0x1A - LINE1 (Port-C) + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + //Pin widget 0x1B - LINE2 (Port-E) + 0x01B71CF0, + 0x01B71D11, + 0x01B71E11, + 0x01B71F41, + //Pin widget 0x1D - PC-BEEP + 0x01D71C29, + 0x01D71D80, + 0x01D71E63, + 0x01D71F40, + //Pin widget 0x1E - S/PDIF-OUT + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + //Pin widget 0x1F - S/PDIF-IN + 0x01F71CF0, + 0x01F71D11, + 0x01F71E11, + 0x01F71F41, + //Pin widget 0x21 - HP-OUT (Port-I) + 0x02171C20, + 0x02171D10, + 0x02171E21, + 0x02171F02, + //Pin widget 0x29 - I2S-IN + 0x02971CF0, + 0x02971D11, + 0x02971E11, + 0x02971F41, + //Widget node 0x20 - 0 FAKE JD unplug + 0x02050008, + 0x0204A80F, + 0x02050008, + 0x0204A80F, + + //Widget node 0x20 - 1 : //remove NID 58 realted setting for ALC700 byp= ass DAC02 DRE(NID5B bit14) + 0x05B50010, + 0x05B45C1D, + 0x0205006F, + 0x02040F8B, //Zeek, 0F8Bh + + //Widget node 0x20 -2: + 0x02050045, + 0x02045089, + 0x0205004A, + 0x0204201B, + + //Widget node 0x20 - 3 From JD detect + 0x02050008, + 0x0204A807, + 0x02050008, + 0x0204A807, + + //Widget node 0x20 - 4 Pull high ALC700 GPIO5 for AMP1305 PD pin and en= able I2S BCLK first + 0x02050090, + 0x02040424, + 0x00171620, + 0x00171720, + + 0x00171520, + 0x01770740, + 0x01770740, + 0x01770740, + + //Widget node 0x20 for ALC1305 20181105 update 2W/4ohm to remove ALC= 1305 EQ setting and enable ALC1305 silencet detect to prevent I2S noise + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040000, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02045548, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02041000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040600, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FFD0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02040DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x0204005D, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040442, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040005, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040006, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040008, + 0x02050028, + 0x0204B000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204002E, + 0x02050028, + 0x02040800, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C3, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204D4A0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400CC, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204400A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x020400C1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040320, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040039, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003B, + 0x02050028, + 0x0204FFFF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x020400C0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCF0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040080, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040880, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCE0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FCA0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003C, + 0x02050028, + 0x0204FC20, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040006, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040080, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C0, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C1, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C2, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C3, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C4, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C5, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C6, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C7, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C8, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400C9, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CA, + 0x02050028, + 0x020401F0, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CB, + 0x02050028, + 0x0204C1C7, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CC, + 0x02050028, + 0x02041C00, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CD, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CE, + 0x02050028, + 0x02040200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400CF, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D0, + 0x02050028, + 0x020403E1, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D1, + 0x02050028, + 0x02040F5A, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D2, + 0x02050028, + 0x02041E1E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x020400D3, + 0x02050028, + 0x0204083F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040062, + 0x02050028, + 0x02048000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040063, + 0x02050028, + 0x02045F5F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040064, + 0x02050028, + 0x02042000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040065, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040066, + 0x02050028, + 0x02044004, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040067, + 0x02050028, + 0x02040802, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040068, + 0x02050028, + 0x0204890F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040069, + 0x02050028, + 0x0204E021, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040070, + 0x02050028, + 0x02048012, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040071, + 0x02050028, + 0x02043450, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040072, + 0x02050028, + 0x02040123, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040073, + 0x02050028, + 0x02044543, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040074, + 0x02050028, + 0x02042100, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040075, + 0x02050028, + 0x02044321, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040076, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040050, + 0x02050028, + 0x02048200, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040051, + 0x02050028, + 0x02040707, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040052, + 0x02050028, + 0x02044090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006A, + 0x02050028, + 0x02040090, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204006C, + 0x02050028, + 0x0204721F, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040012, + 0x02050028, + 0x0204DFDF, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204009E, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040004, + 0x02050028, + 0x02040500, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040060, + 0x02050028, + 0x0204E213, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003A, + 0x02050028, + 0x02041DFE, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204003F, + 0x02050028, + 0x02043000, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040040, + 0x02050028, + 0x0204000C, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x02040046, + 0x02050028, + 0x0204422E, + 0x02050029, + 0x0204B024, + + 0x02050024, + 0x02040010, + 0x02050026, + 0x0204004B, + 0x02050028, + 0x02040000, + 0x02050029, + 0x0204B024 +); // WhlHdaVerbTableAlc700 + +#endif // _PCH_HDA_VERB_TABLES_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiWhiskeylakeURvpInitLib.h b/Platform/Intel/WhiskeylakeOpenB= oardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h new file mode 100644 index 0000000000..89c780cc0b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpInitLib.h @@ -0,0 +1,41 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_ +#define _PEI_WHISKEYLAKE_RVP3_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern const UINT8 mDqByteMapSklRvp3[2][6][2]; +extern const UINT8 mDqsMapCpu2DramSklRvp3[2][8]; +extern const UINT8 mSkylakeRvp3Spd110[]; +extern const UINT16 mSkylakeRvp3Spd110Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[]; +extern UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size; +extern HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[]; +extern UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size; + +extern GPIO_INIT_CONFIG mGpioTableLpddr3Rvp3UcmcDevice[]; +extern UINT16 mGpioTableLpddr3Rvp3UcmcDeviceSize; + +extern IO_EXPANDER_GPIO_CONFIG mGpioTableIoExpander[]; +extern UINT16 mGpioTableIoExpanderSize; +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3Touchpanel; +extern GPIO_INIT_CONFIG mGpioTableLpDdr3Rvp3[]; +extern UINT16 mGpioTableLpDdr3Rvp3Size; + +#endif // _PEI_Whiskeylake_RVP3_BOARD_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /DxePolicyBoardConfigLib/DxePolicyBoardConfig.h b/Platform/Intel/Whiskeylak= eOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxePolicyBoar= dConfig.h new file mode 100644 index 0000000000..a6d48e906d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePol= icyBoardConfigLib/DxePolicyBoardConfig.h @@ -0,0 +1,20 @@ +/** @file + Header file for DxePolicyBoardConfig library instance. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_POLICY_BOARD_CONFIG_H_ +#define _DXE_POLICY_BOARD_CONFIG_H_ + +#include +#include +#include +#include +#include + + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiPolicyBoardConfig.h b/Platform/Intel/Whiskeylak= eOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPolicyBoar= dConfig.h new file mode 100644 index 0000000000..03c27f2a41 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiPolicyBoardConfig.h @@ -0,0 +1,23 @@ +/** @file + Header file for PeiPolicyBoardConfig library instance. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_POLICY_BOARD_CONFIG_H_ +#define _PEI_POLICY_BOARD_CONFIG_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BaseFuncLib/Gop.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp= /Library/BaseFuncLib/Gop.c new file mode 100644 index 0000000000..01b3df984a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseFu= ncLib/Gop.c @@ -0,0 +1,41 @@ +/** @file + Others Board's PCD function hook. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +// +// Null function for nothing GOP VBT update. +// +VOID +EFIAPI +GopVbtSpecificUpdateNull ( + IN CHILD_STRUCT **ChildStructPtr + ) +{ + return; +} + +// +// for CFL U DDR4 +// +VOID +EFIAPI +CflUDdr4GopVbtSpecificUpdate( + IN CHILD_STRUCT **ChildStructPtr +) +{ + ChildStructPtr[1]->DeviceClass =3D DISPLAY_PORT_ONLY; + ChildStructPtr[1]->DVOPort =3D DISPLAY_PORT_B; + ChildStructPtr[2]->DeviceClass =3D DISPLAY_PORT_HDMI_DVI_COMPATIBLE; + ChildStructPtr[2]->DVOPort =3D DISPLAY_PORT_C; + ChildStructPtr[2]->AUX_Channel =3D AUX_CHANNEL_C; + ChildStructPtr[3]->DeviceClass =3D NO_DEVICE; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.c b/Platform/Intel/Whisk= eylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib/BaseGpi= oCheckConflictLib.c new file mode 100644 index 0000000000..7ebf8f8fdc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGp= ioCheckConflictLib/BaseGpioCheckConflictLib.c @@ -0,0 +1,137 @@ +/** @file + Implementation of BaseGpioCheckConflictLib. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +/** + Check Gpio PadMode conflict and report it. + + @retval none. +**/ +VOID +GpioCheckConflict ( + VOID + ) +{ + EFI_HOB_GUID_TYPE *GpioCheckConflictHob; + GPIO_PAD_MODE_INFO *GpioCheckConflictHobData; + UINT32 HobDataSize; + UINT32 GpioCount; + UINT32 GpioIndex; + GPIO_CONFIG GpioActualConfig; + + GpioCheckConflictHob =3D NULL; + GpioCheckConflictHobData =3D NULL; + + DEBUG ((DEBUG_INFO, "GpioCheckConflict Start..\n")); + + // + //Use Guid to find HOB. + // + GpioCheckConflictHob =3D (EFI_HOB_GUID_TYPE *) GetFirstGuidHob (&gGpioCh= eckConflictHobGuid); + if (GpioCheckConflictHob =3D=3D NULL) { + DEBUG ((DEBUG_INFO, "[Gpio Hob Check] Can't find Gpio Hob.\n")); + } else { + while (GpioCheckConflictHob !=3D NULL) { + // + // Find the Data area pointer and Data size from the Hob + // + GpioCheckConflictHobData =3D (GPIO_PAD_MODE_INFO *) GET_GUID_HOB_DAT= A (GpioCheckConflictHob); + HobDataSize =3D GET_GUID_HOB_DATA_SIZE (GpioCheckConflictHob); + + GpioCount =3D HobDataSize / sizeof (GPIO_PAD_MODE_INFO); + DEBUG ((DEBUG_INFO, "[Hob Check] Hob : GpioCount =3D %d\n", GpioCou= nt)); + + // + // Probe Gpio entries in Hob and compare which are conflicted + // + for (GpioIndex =3D 0; GpioIndex < GpioCount ; GpioIndex++) { + GpioGetPadConfig (GpioCheckConflictHobData[GpioIndex].GpioPad, &Gp= ioActualConfig); + if (GpioCheckConflictHobData[GpioIndex].GpioPadMode !=3D GpioActua= lConfig.PadMode) { + DEBUG ((DEBUG_ERROR, "[Gpio Check] Identified conflict on pad %a= \n", GpioName (GpioCheckConflictHobData[GpioIndex].GpioPad))); + } + } + // + // Find next Hob and return the Hob pointer by the specific Hob Guid + // + GpioCheckConflictHob =3D GET_NEXT_HOB (GpioCheckConflictHob); + GpioCheckConflictHob =3D GetNextGuidHob (&gGpioCheckConflictHobGuid,= GpioCheckConflictHob); + } + + DEBUG ((DEBUG_INFO, "GpioCheckConflict End.\n")); + } + + return; +} + +/** + This libaray will create one Hob for each Gpio config table + without PadMode is GpioHardwareDefault + + @param[in] GpioDefinition Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + + @retval none. +**/ +VOID +CreateGpioCheckConflictHob ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + + UINT32 Index; + UINT32 GpioIndex; + GPIO_PAD_MODE_INFO *GpioCheckConflictHobData; + UINT16 GpioCount; + + GpioCount =3D 0; + GpioIndex =3D 0; + + DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob Start \n")); + + for (Index =3D 0; Index < GpioTableCount ; Index++) { + if (GpioDefinition[Index].GpioConfig.PadMode =3D=3D GpioHardwareDefaul= t) { + continue; + } else { + // + // Calculate how big size the Hob Data needs + // + GpioCount++; + } + } + + // + // Build a HOB tagged with a GUID for identification and returns + // the start address of GUID HOB data. + // + GpioCheckConflictHobData =3D (GPIO_PAD_MODE_INFO *) BuildGuidHob (&gGpio= CheckConflictHobGuid , GpioCount * sizeof (GPIO_PAD_MODE_INFO)); + + // + // Record Non Default Gpio entries to the Hob + // + for (Index =3D 0; Index < GpioTableCount; Index++) { + if (GpioDefinition[Index].GpioConfig.PadMode =3D=3D GpioHardwareDefaul= t) { + continue; + } else { + GpioCheckConflictHobData[GpioIndex].GpioPad =3D GpioDefinition[Index= ].GpioPad; + GpioCheckConflictHobData[GpioIndex].GpioPadMode =3D GpioDefinition[I= ndex].GpioConfig.PadMode; + GpioIndex++; + } + } + + DEBUG ((DEBUG_INFO, "CreateGpioCheckConflictHob End \n")); + return; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BaseGpioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c b/Platform/Int= el/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGpioCheckConflictLib= Null/BaseGpioCheckConflictLibNull.c new file mode 100644 index 0000000000..178ce1a124 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BaseGp= ioCheckConflictLibNull/BaseGpioCheckConflictLibNull.c @@ -0,0 +1,37 @@ +/** @file + Implementation of BaseGpioCheckConflicLibNull. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +/** + Check Gpio PadMode conflict and report it. +**/ +VOID +GpioCheckConflict ( + VOID + ) +{ + return; +} + +/** + This libaray will create one Hob for each Gpio config table + without PadMode is GpioHardwareDefault + + @param[in] GpioDefinition Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries +**/ +VOID +CreateGpioCheckConflictHob ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + return; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/WhiskeylakeOpen= BoardPkg/WhiskeylakeURvp/Library/BasePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..24c6fa6277 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BasePl= atformHookLib/BasePlatformHookLib.c @@ -0,0 +1,156 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F + +#define IT8628_ENTER_CONFIG_WRITE_SEQ_0 0x87 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_1 0x01 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_2 0x55 +#define IT8628_ENTER_CONFIG_WRITE_SEQ_3 0x55 +#define IT8628_EXIT_CONFIG 0x2 +#define IT8628_CHIPID_BYTE1 0x86 +#define IT8628_CHIPID_BYTE2 0x28 + +typedef struct { + UINT8 Register; + UINT8 Value; +} EFI_SIO_TABLE; + +// +// IT8628 +// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = =3D { + {0x023, 0x09}, // Clock Selection register + {0x007, 0x01}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select + {0x030, 0x01}, // Serial Port 1 Activate + {0x007, 0x02}, // Com1 Logical Device Number select + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select + {0x030, 0x01} // Serial Port 2 Activate +}; + +/** + Check whether the IT8628 SIO present on LPC. If yes, enable its serial p= orts +**/ +STATIC +VOID +It8628SioSerialPortInit ( + VOID + ) +{ + UINT8 ChipId0; + UINT8 ChipId1; + UINT16 LpcIoDecondeRangeSet; + UINT16 LpcIoDecoodeSet; + UINT8 Index; + UINT64 LpcBaseAddr; + + ChipId0 =3D 0; + ChipId1 =3D 0; + LpcIoDecondeRangeSet =3D 0; + LpcIoDecoodeSet =3D 0; + + // + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2= Eh/2Fh. + // + LpcBaseAddr =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + LpcIoDecondeRangeSet =3D (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_= CFG_IOD); + LpcIoDecoodeSet =3D (UINT16) PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_I= OE); + PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOD), (LpcIoDecondeRangeSet = | ((V_LPC_CFG_IOD_COMB_2F8 << 4) | V_LPC_CFG_IOD_COMA_3F8))); + PciSegmentWrite16 ((LpcBaseAddr + R_LPC_CFG_IOE), (LpcIoDecoodeSet | (B_= LPC_CFG_IOE_SE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE|B_LPC_CFG_IOE_KE))); + + // + // Enter MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_0); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_1); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_2); + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_3); + + // + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21) + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20); + ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21); + ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2); + + // + // Enable Serial Port 1, Port 2 + // + if ((ChipId0 =3D=3D IT8628_CHIPID_BYTE1) && (ChipId1 =3D=3D IT8628_CHIPI= D_BYTE2)) { + for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof = (EFI_SIO_TABLE); Index++) { + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[In= dex].Register); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Ind= ex].Value); + } + } + + // + // Exit MB PnP Mode + // + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_EXIT_CONFIG); + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, IT8628_EXIT_CONFIG); + + return; +} + +/** + Performs platform specific initialization required for the CPU to access + the hardware associated with a SerialPortLib instance. This function do= es + not initialize the serial port hardware itself. Instead, it initializes + hardware devices that are required for the CPU to access the serial port + hardware. This function may be called more than once. + + @retval RETURN_SUCCESS The platform specific initialization succee= ded. + @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed. + +**/ +RETURN_STATUS +EFIAPI +PlatformHookSerialPortInitialize ( + VOID + ) +{ + // + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E= h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h. + // + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange)); + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding)); + + // Configure Sio IT8628 + It8628SioSerialPortInit (); + + return RETURN_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmBoardAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c new file mode 100644 index 0000000000..e7acbda03a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmBoardAcpiEnableLib.c @@ -0,0 +1,63 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +BoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return WhiskeylakeURvpBoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +BoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return WhiskeylakeURvpBoardDisableAcpi (DisableSci); +} + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/WhiskeylakeOpe= nBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c new file mode 100644 index 0000000000..978e367cda --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmMultiBoardAcpiSupportLib.c @@ -0,0 +1,82 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ); + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpMultiBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + SiliconEnableAcpi (EnableSci); + return WhiskeylakeURvpBoardEnableAcpi (EnableSci); +} + +EFI_STATUS +EFIAPI +WhiskeylakeURvpMultiBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + SiliconDisableAcpi (DisableSci); + return WhiskeylakeURvpBoardDisableAcpi (DisableSci); +} + +BOARD_ACPI_ENABLE_FUNC mWhiskeylakeURvpBoardAcpiEnableFunc =3D { + WhiskeylakeURvpMultiBoardEnableAcpi, + WhiskeylakeURvpMultiBoardDisableAcpi, +}; + +EFI_STATUS +EFIAPI +SmmWhiskeylakeURvpMultiBoardAcpiSupportLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () =3D=3D BoardIdWhiskeyLakeRvp) { + return RegisterBoardAcpiEnableFunc (&mWhiskeylakeURvpBoardAcpiEnableFu= nc); + } + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/WhiskeylakeOpenBoa= rdPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..9daceaa25c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmSiliconAcpiEnableLib.c @@ -0,0 +1,170 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Clear Port 80h + + SMI handler to enable ACPI mode + + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI + + Disables the SW SMI Timer. + ACPI events are disabled and ACPI event status is cleared. + SCI mode is then enabled. + + Clear SLP SMI status + Enable SLP SMI + + Disable SW SMI Timer + + Clear all ACPI event status and disable all ACPI events + + Disable PM sources except power button + Clear status bits + + Disable GPE0 sources + Clear status bits + + Disable GPE1 sources + Clear status bits + + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + + Enable SCI +**/ +EFI_STATUS +EFIAPI +SiliconEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + + UINT32 OutputValue; + UINT32 SmiEn; + UINT32 SmiSts; + UINT32 ULKMC; + UINTN LpcBaseAddress; + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + // + // Get the ACPI Base Address + // + AcpiBaseAddr =3D PmcGetAcpiBase(); + // + // BIOS must also ensure that CF9GR is cleared and locked before handing= control to the + // OS in order to prevent the host from issuing global resets and resett= ing ME + // + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Res= et + // MmioWrite32 ( + // PmcBaseAddress + R_PCH_PMC_ETR3), + // PmInit); + + // + // Clear Port 80h + // + IoWrite8 (0x80, 0); + + // + // Disable SW SMI Timer and clean the status + // + SmiEn =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN); + SmiEn &=3D ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |= B_ACPI_IO_SMI_EN_LEGACY_USB); + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn); + + SmiSts =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS); + SmiSts |=3D B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | = B_ACPI_IO_SMI_EN_LEGACY_USB; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts); + + // + // Disable port 60/64 SMI trap if they are enabled + // + ULKMC =3D MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_UL= KMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC= _64WEN | B_LPC_CFG_ULKMC_A20PASSEN); + MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC); + + // + // Disable PM sources except power button + // + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN); + + // + // Clear PM status except Power Button status for RapidStart Resume + // + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF); + + // + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4) + // + IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD); + IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0); + + // + // Write ALT_GPI_SMI_EN to disable GPI1 (SMC_EXTSMI#) + // + OutputValue =3D IoRead32 (AcpiBaseAddr + 0x38); + OutputValue =3D OutputValue & ~(1 << (UINTN) PcdGet8 (PcdSmcExtSmiBitPos= ition)); + IoWrite32 (AcpiBaseAddr + 0x38, OutputValue); + + // + // Enable SCI + // + if (EnableSci) { + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT); + Pm1Cnt |=3D B_ACPI_IO_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +SiliconDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + + UINT16 AcpiBaseAddr; + UINT32 Pm1Cnt; + + // + // Get the ACPI Base Address + // + AcpiBaseAddr =3D PmcGetAcpiBase(); + // + // Disable SCI + // + if (DisableSci) { + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT); + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SCI_EN; + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c b/Platform/Intel/Whiskeylak= eOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEn= ableLib.c new file mode 100644 index 0000000000..97a3fae51b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA= cpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c @@ -0,0 +1,40 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardEnableAcpi ( + IN BOOLEAN EnableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDisableAcpi ( + IN BOOLEAN DisableSci + ) +{ + // enable additional board register + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardFunc.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whiskeyl= akeURvp/Library/BoardInitLib/BoardFunc.c new file mode 100644 index 0000000000..7a2fed9904 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFunc.c @@ -0,0 +1,19 @@ +/** @file + Board's PCD function hook. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +EFI_STATUS +PeiBoardSpecificInitPostMemNull ( + VOID + ) +{ + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardFuncInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whis= keylakeURvp/Library/BoardInitLib/BoardFuncInit.c new file mode 100644 index 0000000000..5104329825 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFuncInit.c @@ -0,0 +1,27 @@ +/** @file + Source code for the board configuration init function in Post Memory ini= t phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include "BoardFunc.h" + +/** + Board's PCD function hook init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardFunctionInit ( + IN UINT16 BoardId +) +{ + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardFuncInitPreMem.c b/Platform/Intel/WhiskeylakeOpenBoardPk= g/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c new file mode 100644 index 0000000000..3a42a9bd03 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardFuncInitPreMem.c @@ -0,0 +1,41 @@ +/** @file + Source code for the board configuration init function in Post Memory ini= t phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include +// +// Null function for nothing GOP VBT update. +// +VOID +GopVbtSpecificUpdateNull( + IN CHILD_STRUCT **ChildStructPtr +); +// +// for CFL U DDR4 +// +VOID +CflUDdr4GopVbtSpecificUpdate( + IN CHILD_STRUCT **ChildStructPtr +); +/** + Board's PCD function hook init function for PEI post memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardFunctionInitPreMem ( + IN UINT16 BoardId + ) +{ + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c new file mode 100644 index 0000000000..458a73f892 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardPchInitPreMemLib.c @@ -0,0 +1,398 @@ +/** @file + Source code for the board PCH configuration Pcd init functions for Pre-Mm= eory Init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include +#include +#include // for USB 20 AFE & Root Port Clk = Info. +#include "GpioTableWhlUDdr4PreMem.h" +#include + +/** + Board Root Port Clock Info configuration init function for PEI pre-memor= y phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +RootPortClkInfoInit ( + IN UINT16 BoardId + ) +{ + PCD64_BLOB *Clock; + UINT32 Index; + + Clock =3D AllocateZeroPool (16 * sizeof (PCD64_BLOB)); + ASSERT (Clock !=3D NULL); + if (Clock =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + // + // The default clock assignment will be FREE_RUNNING, which corresponds = to PchClockUsageUnspecified + // This is safe but power-consuming setting. If Platform code doesn't co= ntain port-clock map for a given board, + // the clocks will keep on running anyway, allowing PCIe devices to oper= ate. Downside is that clocks will + // continue to draw power. To prevent this, remember to provide port-clo= ck map for every board. + // + for (Index =3D 0; Index < 16; Index++) { + Clock[Index].PcieClock.ClkReqSupported =3D TRUE; + Clock[Index].PcieClock.ClockUsage =3D FREE_RUNNING; + } + + /// + /// Assign ClkReq signal to root port. (Base 0) + /// For LP, Set 0 - 5 + /// For H, Set 0 - 15 + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port. + /// + switch (BoardId) { + // CLKREQ + case BoardIdWhiskeyLakeRvp: + Clock[0].PcieClock.ClockUsage =3D PCIE_PCH + 1; + Clock[1].PcieClock.ClockUsage =3D PCIE_PCH + 8; + Clock[2].PcieClock.ClockUsage =3D LAN_CLOCK; + Clock[3].PcieClock.ClockUsage =3D PCIE_PCH + 13; + Clock[4].PcieClock.ClockUsage =3D PCIE_PCH + 4; + Clock[5].PcieClock.ClockUsage =3D PCIE_PCH + 14; + break; + + default: + break; + } + + PcdSet64S (PcdPcieClock0, Clock[ 0].Blob); + PcdSet64S (PcdPcieClock1, Clock[ 1].Blob); + PcdSet64S (PcdPcieClock2, Clock[ 2].Blob); + PcdSet64S (PcdPcieClock3, Clock[ 3].Blob); + PcdSet64S (PcdPcieClock4, Clock[ 4].Blob); + PcdSet64S (PcdPcieClock5, Clock[ 5].Blob); + PcdSet64S (PcdPcieClock6, Clock[ 6].Blob); + PcdSet64S (PcdPcieClock7, Clock[ 7].Blob); + PcdSet64S (PcdPcieClock8, Clock[ 8].Blob); + PcdSet64S (PcdPcieClock9, Clock[ 9].Blob); + PcdSet64S (PcdPcieClock10, Clock[10].Blob); + PcdSet64S (PcdPcieClock11, Clock[11].Blob); + PcdSet64S (PcdPcieClock12, Clock[12].Blob); + PcdSet64S (PcdPcieClock13, Clock[13].Blob); + PcdSet64S (PcdPcieClock14, Clock[14].Blob); + PcdSet64S (PcdPcieClock15, Clock[15].Blob); + + return EFI_SUCCESS; +} + +/** + Board USB related configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +UsbConfigInit ( + IN UINT16 BoardId + ) +{ + PCD32_BLOB *UsbPort20Afe; + + UsbPort20Afe =3D AllocateZeroPool (PCH_MAX_USB2_PORTS * sizeof (PCD32_BL= OB)); + ASSERT (UsbPort20Afe !=3D NULL); + if (UsbPort20Afe =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // USB2 AFE settings. + // + UsbPort20Afe[0].Info.Petxiset =3D 7; + UsbPort20Afe[0].Info.Txiset =3D 5; + UsbPort20Afe[0].Info.Predeemp =3D 3; + UsbPort20Afe[0].Info.Pehalfbit =3D 0; + + UsbPort20Afe[1].Info.Petxiset =3D 7; + UsbPort20Afe[1].Info.Txiset =3D 5; + UsbPort20Afe[1].Info.Predeemp =3D 3; + UsbPort20Afe[1].Info.Pehalfbit =3D 0; + + UsbPort20Afe[2].Info.Petxiset =3D 7; + UsbPort20Afe[2].Info.Txiset =3D 5; + UsbPort20Afe[2].Info.Predeemp =3D 3; + UsbPort20Afe[2].Info.Pehalfbit =3D 0; + + UsbPort20Afe[3].Info.Petxiset =3D 7; + UsbPort20Afe[3].Info.Txiset =3D 5; + UsbPort20Afe[3].Info.Predeemp =3D 3; + UsbPort20Afe[3].Info.Pehalfbit =3D 0; + + UsbPort20Afe[4].Info.Petxiset =3D 7; + UsbPort20Afe[4].Info.Txiset =3D 5; + UsbPort20Afe[4].Info.Predeemp =3D 3; + UsbPort20Afe[4].Info.Pehalfbit =3D 0; + + UsbPort20Afe[5].Info.Petxiset =3D 7; + UsbPort20Afe[5].Info.Txiset =3D 5; + UsbPort20Afe[5].Info.Predeemp =3D 3; + UsbPort20Afe[5].Info.Pehalfbit =3D 0; + + UsbPort20Afe[6].Info.Petxiset =3D 7; + UsbPort20Afe[6].Info.Txiset =3D 5; + UsbPort20Afe[6].Info.Predeemp =3D 3; + UsbPort20Afe[6].Info.Pehalfbit =3D 0; + + UsbPort20Afe[7].Info.Petxiset =3D 7; + UsbPort20Afe[7].Info.Txiset =3D 5; + UsbPort20Afe[7].Info.Predeemp =3D 3; + UsbPort20Afe[7].Info.Pehalfbit =3D 0; + + UsbPort20Afe[8].Info.Petxiset =3D 7; + UsbPort20Afe[8].Info.Txiset =3D 5; + UsbPort20Afe[8].Info.Predeemp =3D 3; + UsbPort20Afe[8].Info.Pehalfbit =3D 0; + + UsbPort20Afe[9].Info.Petxiset =3D 7; + UsbPort20Afe[9].Info.Txiset =3D 5; + UsbPort20Afe[9].Info.Predeemp =3D 3; + UsbPort20Afe[9].Info.Pehalfbit =3D 0; + + // + // USB Port Over Current Pin + // + PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinMax); + + PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinMax); + PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinMax); + + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S (PcdUsb20OverCurrentPinPort0, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort1, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort2, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort3, UsbOverCurrentPin2); + PcdSet8S (PcdUsb20OverCurrentPinPort4, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort5, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort6, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort7, UsbOverCurrentPin3); + PcdSet8S (PcdUsb20OverCurrentPinPort8, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort9, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort10, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort11, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort12, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort13, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort14, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb20OverCurrentPinPort15, UsbOverCurrentPinSkip); + + PcdSet8S (PcdUsb30OverCurrentPinPort0, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort1, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort2, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort3, UsbOverCurrentPin2); + PcdSet8S (PcdUsb30OverCurrentPinPort4, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort5, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort6, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort7, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort8, UsbOverCurrentPinSkip); + PcdSet8S (PcdUsb30OverCurrentPinPort9, UsbOverCurrentPinSkip); + + // USB2.0 AFE settings + UsbPort20Afe[0].Info.Petxiset =3D 6; + UsbPort20Afe[0].Info.Txiset =3D 0; + UsbPort20Afe[0].Info.Predeemp =3D 3; + UsbPort20Afe[0].Info.Pehalfbit =3D 0; + + UsbPort20Afe[1].Info.Petxiset =3D 6; + UsbPort20Afe[1].Info.Txiset =3D 0; + UsbPort20Afe[1].Info.Predeemp =3D 3; + UsbPort20Afe[1].Info.Pehalfbit =3D 0; + + UsbPort20Afe[2].Info.Petxiset =3D 6; + UsbPort20Afe[2].Info.Txiset =3D 0; + UsbPort20Afe[2].Info.Predeemp =3D 3; + UsbPort20Afe[2].Info.Pehalfbit =3D 0; + + UsbPort20Afe[3].Info.Petxiset =3D 6; + UsbPort20Afe[3].Info.Txiset =3D 0; + UsbPort20Afe[3].Info.Predeemp =3D 3; + UsbPort20Afe[3].Info.Pehalfbit =3D 0; + + UsbPort20Afe[4].Info.Petxiset =3D 6; + UsbPort20Afe[4].Info.Txiset =3D 0; + UsbPort20Afe[4].Info.Predeemp =3D 3; + UsbPort20Afe[4].Info.Pehalfbit =3D 0; + + UsbPort20Afe[5].Info.Petxiset =3D 6; + UsbPort20Afe[5].Info.Txiset =3D 0; + UsbPort20Afe[5].Info.Predeemp =3D 3; + UsbPort20Afe[5].Info.Pehalfbit =3D 0; + + UsbPort20Afe[6].Info.Petxiset =3D 6; + UsbPort20Afe[6].Info.Txiset =3D 0; + UsbPort20Afe[6].Info.Predeemp =3D 3; + UsbPort20Afe[6].Info.Pehalfbit =3D 0; + + UsbPort20Afe[7].Info.Petxiset =3D 6; + UsbPort20Afe[7].Info.Txiset =3D 0; + UsbPort20Afe[7].Info.Predeemp =3D 3; + UsbPort20Afe[7].Info.Pehalfbit =3D 0; + + UsbPort20Afe[8].Info.Petxiset =3D 6; + UsbPort20Afe[8].Info.Txiset =3D 0; + UsbPort20Afe[8].Info.Predeemp =3D 3; + UsbPort20Afe[8].Info.Pehalfbit =3D 0; + + UsbPort20Afe[9].Info.Petxiset =3D 6; + UsbPort20Afe[9].Info.Txiset =3D 0; + UsbPort20Afe[9].Info.Predeemp =3D 3; + UsbPort20Afe[9].Info.Pehalfbit =3D 0; + break; + } + + // + // Save USB2.0 AFE blobs + // + PcdSet32S (PcdUsb20Port0Afe, UsbPort20Afe[ 0].Blob); + PcdSet32S (PcdUsb20Port1Afe, UsbPort20Afe[ 1].Blob); + PcdSet32S (PcdUsb20Port2Afe, UsbPort20Afe[ 2].Blob); + PcdSet32S (PcdUsb20Port3Afe, UsbPort20Afe[ 3].Blob); + PcdSet32S (PcdUsb20Port4Afe, UsbPort20Afe[ 4].Blob); + PcdSet32S (PcdUsb20Port5Afe, UsbPort20Afe[ 5].Blob); + PcdSet32S (PcdUsb20Port6Afe, UsbPort20Afe[ 6].Blob); + PcdSet32S (PcdUsb20Port7Afe, UsbPort20Afe[ 7].Blob); + PcdSet32S (PcdUsb20Port8Afe, UsbPort20Afe[ 8].Blob); + PcdSet32S (PcdUsb20Port9Afe, UsbPort20Afe[ 9].Blob); + PcdSet32S (PcdUsb20Port10Afe, UsbPort20Afe[10].Blob); + PcdSet32S (PcdUsb20Port11Afe, UsbPort20Afe[11].Blob); + PcdSet32S (PcdUsb20Port12Afe, UsbPort20Afe[12].Blob); + PcdSet32S (PcdUsb20Port13Afe, UsbPort20Afe[13].Blob); + PcdSet32S (PcdUsb20Port14Afe, UsbPort20Afe[14].Blob); + PcdSet32S (PcdUsb20Port15Afe, UsbPort20Afe[15].Blob); + + return EFI_SUCCESS; +} + +/** + Board GPIO Group Tier configuration init function for PEI pre-memory pha= se. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +GpioGroupTierInit ( + IN UINT16 BoardId + ) +{ + // + // GPIO Group Tier + // + + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdGpioGroupToGpeDw0, GPIO_CNL_LP_GROUP_GPP_G); + PcdSet32S (PcdGpioGroupToGpeDw1, GPIO_CNL_LP_GROUP_SPI); + PcdSet32S (PcdGpioGroupToGpeDw2, GPIO_CNL_LP_GROUP_GPP_E); + break; + + default: + PcdSet32S (PcdGpioGroupToGpeDw0, 0); + PcdSet32S (PcdGpioGroupToGpeDw1, 0); + PcdSet32S (PcdGpioGroupToGpeDw2, 0); + break; + } + + return EFI_SUCCESS; +} + +/** + GPIO init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +GpioTablePreMemInit ( + IN UINT16 BoardId + ) +{ + // + // GPIO Table Init. + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTableWhlUDdr4PreMem= ); + PcdSet16S (PcdBoardGpioTablePreMemSize, sizeof (mGpioTableWhlUDdr4Pr= eMem) / sizeof (GPIO_INIT_CONFIG)); + PcdSet32S (PcdBoardGpioTableWwanOnEarlyPreMem, (UINTN) mGpioTableWhl= UDdr4WwanOnEarlyPreMem); + PcdSet16S (PcdBoardGpioTableWwanOnEarlyPreMemSize, sizeof (mGpioTabl= eWhlUDdr4WwanOnEarlyPreMem) / sizeof (GPIO_INIT_CONFIG)); + PcdSet32S (PcdBoardGpioTableWwanOffEarlyPreMem, (UINTN) mGpioTableWh= lUDdr4WwanOffEarlyPreMem); + PcdSet16S (PcdBoardGpioTableWwanOffEarlyPreMemSize, sizeof (mGpioTab= leWhlUDdr4WwanOffEarlyPreMem) / sizeof (GPIO_INIT_CONFIG)); + break; + + default: + break; + } + + return EFI_SUCCESS; +} + +/** + PmConfig init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +PchPmConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update PmCofig policy: output voltage of VCCPRIMCORE RAIL when SLP_S0= # is asserted based on board HW design + // 1) Discete VR or Non Premium PMIC: 0.75V (PcdSlpS0Vm075VSupport) + // 2) Premium PMIC: runtime control for voltage (PcdSlpS0VmRuntimeContro= l) + // Only applys to board with PCH-LP. Board with Discrete PCH doesn't nee= d this setting. + // + switch (BoardId) { + // Discrete VR solution + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE); + PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE); + PcdSetBoolS (PcdSlpS0Vm075VSupport, TRUE); + break; + + default: + PcdSetBoolS (PcdSlpS0VmRuntimeControl, FALSE); + PcdSetBoolS (PcdSlpS0Vm070VSupport, FALSE); + PcdSetBoolS (PcdSlpS0Vm075VSupport, FALSE); + break; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoardP= kg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c new file mode 100644 index 0000000000..17f12c117d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/BoardSaInitPreMemLib.c @@ -0,0 +1,282 @@ +/** @file + Source code for the board SA configuration Pcd init functions in Pre-Memo= ry init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include "BoardSaConfigPreMem.h" +#include +#include +#include "SaPolicyCommon.h" + +// +// Display DDI settings for WHL ERB +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mWhlErbRowDisplayDdiConfig[9] = =3D { + DdiPortAEdp, // DDI Port A Config : DdiPortADisabled =3D Disabled, D= diPortAEdp =3D eDP, DdiPortAMipiDsi =3D MIPI DSI + DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable =3D Disable, DdiHpdEn= able =3D Enable HPD + DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable =3D Disable, DdiHpdEn= able =3D Enable HPD + DdiHpdDisable, // DDI Port D HPD : DdiHpdDisable =3D Disable, DdiHpdEn= able =3D Enable HPD + DdiHpdDisable, // DDI Port F HPD : DdiHpdDisable =3D Disable, DdiHpdEn= able =3D Enable HPD + DdiDdcEnable, // DDI Port B DDC : DdiDisable =3D Disable, DdiDdcEnabl= e =3D Enable DDC + DdiDdcEnable, // DDI Port C DDC : DdiDisable =3D Disable, DdiDdcEnabl= e =3D Enable DDC + DdiDdcEnable, // DDI Port D DDC : DdiDisable =3D Disable, DdiDdcEnabl= e =3D Enable DDC + DdiDisable // DDI Port F DDC : DdiDisable =3D Disable, DdiDdcEnabl= e =3D Enable DDC +}; + +/** + MRC configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaMiscConfigInit ( + IN UINT16 BoardId + ) +{ + // + // UserBd + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + // + // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUs= er4 for ULT platforms. + // This is required to skip Memory voltage programming based on GPIO= 's in MRC + // + PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platf= orm + break; + + default: + // MiscPeiPreMemConfig.UserBd =3D 0 by default. + break; + } + + PcdSet16S (PcdSaDdrFreqLimit, 0); + + return EFI_SUCCESS; +} + +/** + Board Memory Init related configuration init function for PEI pre-memory= phase. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +MrcConfigInit ( + IN UINT16 BoardId + ) +{ + CPU_FAMILY CpuFamilyId; + CPU_STEPPING CpuStepping; + + CpuFamilyId =3D GetCpuFamily(); + CpuStepping =3D GetCpuStepping(); + + if (CpuFamilyId =3D=3D EnumCpuCflDtHalo) { + PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE); + } else { + PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE); + } + + // + // Example policy for DIMM slots implementation boards: + // 1. Assign Smbus address of DIMMs and SpdData will be updated later + // by reading from DIMM SPD. + // 2. No need to apply hardcoded SpdData buffers here for such board. + // + // Whiskey Lake U RVP has removable DIMM slots. + // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to = 0. + // Example: + // PcdMrcSpdData =3D 0 + // PcdMrcSpdDataSize =3D 0 + // PcdMrcSpdAddressTable0 =3D 0xA0 + // PcdMrcSpdAddressTable1 =3D 0xA2 + // PcdMrcSpdAddressTable2 =3D 0xA4 + // PcdMrcSpdAddressTable3 =3D 0xA6 + // + // If a board has soldered down memory. It should use the following set= tings. + // Example: + // PcdMrcSpdAddressTable0 =3D 0 + // PcdMrcSpdAddressTable1 =3D 0 + // PcdMrcSpdAddressTable2 =3D 0 + // PcdMrcSpdAddressTable3 =3D 0 + // PcdMrcSpdData =3D static data buffer + // PcdMrcSpdDataSize =3D sizeof (static data buffer) + // + + // + // SPD Address Table + // + PcdSet32S (PcdMrcSpdData, 0); + PcdSet16S (PcdMrcSpdDataSize, 0); + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0); + PcdSet8S (PcdMrcSpdAddressTable1, 0xA2); + PcdSet8S (PcdMrcSpdAddressTable2, 0xA4); + PcdSet8S (PcdMrcSpdAddressTable3, 0xA6); + + // + // DRAM SPD Data & related configuration + // + // Setting the PCD's to default value (WHL RVP3). It will be overriden t= o board specific settings below. + PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapWhlUDdr4Rvp); + PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapWhlUDdr4Rvp)); + PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramWhlUDdr4Rvp); + PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramWhlUDdr4Rvp)= ); + + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorCflUDdr4Interpo= ser); + PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetWhlUDdr4Interposer); + PcdSetBoolS (PcdMrcDqPinsInterleavedControl, TRUE); + PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE); + break; + + default: + break; + } + + // + // CA Vref routing: board-dependent + // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L) + // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used) + // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4) + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards + break; + + default: + PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards + break; + } + + return EFI_SUCCESS; +} + +/** + Board SA related GPIO configuration init function for PEI pre-memory pha= se. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaGpioConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update board's GPIO for PEG slot reset + // + PcdSetBoolS (PcdPegGpioResetControl, TRUE); + PcdSetBoolS (PcdPegGpioResetSupoort, FALSE); + PcdSet32S (PcdPeg0ResetGpioPad, 0); + PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE); + PcdSet32S (PcdPeg3ResetGpioPad, 0); + PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE); + + // + // PCIE RTD3 GPIO + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S(PcdRootPortIndex, 4); + PcdSet8S (PcdPcie0GpioSupport, PchGpio); + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15); + PcdSetBoolS (PcdPcie0HoldRstActive, FALSE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie1GpioSupport, NotSupported); + PcdSet32S (PcdPcie1WakeGpioNo, 0); + PcdSet8S (PcdPcie1HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie1HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie1HoldRstActive, FALSE); + PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie1PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie2GpioSupport, NotSupported); + PcdSet32S (PcdPcie2WakeGpioNo, 0); + PcdSet8S (PcdPcie2HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie2HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie2HoldRstActive, FALSE); + PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie2PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE); + break; + + default: + PcdSet8S(PcdRootPortIndex, 0xFF); + PcdSet8S (PcdPcie0GpioSupport, NotSupported); + PcdSet32S (PcdPcie0WakeGpioNo, 0); + PcdSet8S (PcdPcie0HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie0HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie0HoldRstActive, FALSE); + PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie0PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie1GpioSupport, NotSupported); + PcdSet32S (PcdPcie1WakeGpioNo, 0); + PcdSet8S (PcdPcie1HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie1HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie1HoldRstActive, FALSE); + PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie1PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE); + + PcdSet8S (PcdPcie2GpioSupport, NotSupported); + PcdSet32S (PcdPcie2WakeGpioNo, 0); + PcdSet8S (PcdPcie2HoldRstExpanderNo, 0); + PcdSet32S (PcdPcie2HoldRstGpioNo, 0); + PcdSetBoolS (PcdPcie2HoldRstActive, FALSE); + PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0); + PcdSet32S (PcdPcie2PwrEnableGpioNo, 0); + PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE); + break; + } + + return EFI_SUCCESS; +} + +/** + SA Display DDI configuration init function for PEI pre-memory phase. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +SaDisplayConfigInit ( + IN UINT16 BoardId + ) +{ + // + // Update Display DDI Config + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mWhlErbRowDisplayDdiConf= ig); + PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mWhlErbRowDisplayDdi= Config)); + break; + + default: + break; + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiBoardInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpenBoar= dPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.c new file mode 100644 index 0000000000..c52d4eceed --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPostMemLib.c @@ -0,0 +1,40 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeSiliconInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardInitBeforeSiliconInit ( + VOID + ) +{ + WhiskeylakeURvpBoardInitBeforeSiliconInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterSiliconInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiBoardInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpenBoard= Pkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPreMemLib.c new file mode 100644 index 0000000000..1283a4c80a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiBoardInitPreMemLib.c @@ -0,0 +1,106 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +WhiskeylakeURvpBoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeMemoryInit ( + VOID + ); + +EFI_STATUS +EFIAPI +BoardDetect ( + VOID + ) +{ + WhiskeylakeURvpBoardDetect (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardDebugInit ( + VOID + ) +{ + WhiskeylakeURvpBoardDebugInit (); + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +BoardBootModeDetect ( + VOID + ) +{ + return WhiskeylakeURvpBoardBootModeDetect (); +} + +EFI_STATUS +EFIAPI +BoardInitBeforeMemoryInit ( + VOID + ) +{ + WhiskeylakeURvpBoardInitBeforeMemoryInit (); + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterMemoryInit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitBeforeTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +BoardInitAfterTempRamExit ( + VOID + ) +{ + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/WhiskeylakeOpe= nBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c new file mode 100644 index 0000000000..965110a5a5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPostMemLib.c @@ -0,0 +1,41 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeSiliconInit ( + VOID + ); + +BOARD_POST_MEM_INIT_FUNC mWhiskeylakeURvpBoardInitFunc =3D { + WhiskeylakeURvpBoardInitBeforeSiliconInit, + NULL, // BoardInitAfterSiliconInit +}; + +EFI_STATUS +EFIAPI +PeiWhiskeylakeURvpMultiBoardInitLibConstructor ( + VOID + ) +{ + if (LibPcdGetSku () =3D=3D BoardIdWhiskeyLakeRvp) { + return RegisterBoardPostMemInit (&mWhiskeylakeURvpBoardInitFunc); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/WhiskeylakeOpen= BoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c new file mode 100644 index 0000000000..a2a6efe506 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiMultiBoardInitPreMemLib.c @@ -0,0 +1,83 @@ +/** @file + Platform Hook Library instances + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpMultiBoardDetect ( + VOID + ); + +EFI_BOOT_MODE +EFIAPI +WhiskeylakeURvpBoardBootModeDetect ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDebugInit ( + VOID + ); + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeMemoryInit ( + VOID + ); + +BOARD_DETECT_FUNC mWhiskeylakeURvpBoardDetectFunc =3D { + WhiskeylakeURvpMultiBoardDetect +}; + +BOARD_PRE_MEM_INIT_FUNC mWhiskeylakeURvpBoardPreMemInitFunc =3D { + WhiskeylakeURvpBoardDebugInit, + WhiskeylakeURvpBoardBootModeDetect, + WhiskeylakeURvpBoardInitBeforeMemoryInit, + NULL, // BoardInitAfterMemoryInit + NULL, // BoardInitBeforeTempRamExit + NULL, // BoardInitAfterTempRamExit +}; + +EFI_STATUS +EFIAPI +WhiskeylakeURvpMultiBoardDetect ( + VOID + ) +{ + WhiskeylakeURvpBoardDetect (); + if (LibPcdGetSku () =3D=3D BoardIdWhiskeyLakeRvp) { + RegisterBoardPreMemInit (&mWhiskeylakeURvpBoardPreMemInitFunc); + } + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +PeiWhiskeylakeURvpMultiBoardInitPreMemLibConstructor ( + VOID + ) +{ + return RegisterBoardDetect (&mWhiskeylakeURvpBoardDetectFunc); +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiWhiskeylakeURvpDetect.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c new file mode 100644 index 0000000000..0adbed7f53 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpDetect.c @@ -0,0 +1,63 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiWhiskeylakeURvpInitLib.h" + +#include +#include + +BOOLEAN +WhiskeylakeURvp( + VOID + ) +{ + return TRUE; +} + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDetect ( + VOID + ) +{ + if (LibPcdGetSku () !=3D 0) { + return EFI_SUCCESS; + } + + DEBUG ((EFI_D_INFO, "WhiskeylakeURvpDetectionCallback\n")); + + if (WhiskeylakeURvp()) { + LibPcdSetSku (BoardIdWhiskeyLakeRvp); + + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku())); + ASSERT (LibPcdGetSku() =3D=3D BoardIdWhiskeyLakeRvp); + } + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c b/Platform/Intel/Whiskeyla= keOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitP= ostMemLib.c new file mode 100644 index 0000000000..80b0a97612 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpInitPostMemLib.c @@ -0,0 +1,432 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "PeiWhiskeylakeURvpInitLib.h" +#include "GpioTableDefault.h" +#include "GpioTableWhlUDdr4.h" +#include +#include +#include +#include +#include + +EFI_STATUS +BoardFunctionInit( + IN UINT16 BoardId +); + +/** +GPIO init function for PEI post memory phase. + +@param[in] BoardId An unsigned integrer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardGpioInit( + IN UINT16 BoardId +) +{ + // + // GPIO Table Init. + // + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableWhlUDdr4_0); + PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableWhlUDdr4_0) / size= of(GPIO_INIT_CONFIG)); + PcdSet32S(PcdBoardGpioTable2, (UINTN)mGpioTableWhlUDdr4); + PcdSet16S(PcdBoardGpioTable2Size, sizeof(mGpioTableWhlUDdr4) / sizeo= f(GPIO_INIT_CONFIG)); + break; + + default: + DEBUG((DEBUG_INFO, "For Unknown Board ID..Use Default GPIO Table...\= n")); + PcdSet32S(PcdBoardGpioTable, (UINTN)mGpioTableDefault); + PcdSet16S(PcdBoardGpioTableSize, sizeof(mGpioTableDefault) / sizeof(= GPIO_INIT_CONFIG)); + break; + } + + return EFI_SUCCESS; +} + +/** +Touch panel GPIO init function for PEI post memory phase. + +@param[in] BoardId An unsigned integrer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +TouchPanelGpioInit( + IN UINT16 BoardId +) +{ + switch (BoardId) { + default: + PcdSet32S(PcdBoardGpioTableTouchPanel, 0); + break; + } + return EFI_SUCCESS; +} + +/** +Misc. init function for PEI post memory phase. + +@param[in] BoardId An unsigned integrer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardMiscInit( + IN UINT16 BoardId +) +{ + PcdSetBoolS(PcdDebugUsbUartEnable, FALSE); + + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + + PcdSetBoolS(PcdMipiCamGpioEnable, TRUE); + break; + + default: + PcdSetBoolS(PcdMipiCamGpioEnable, FALSE); + break; + } + + return EFI_SUCCESS; +} + +/** +Security GPIO init function for PEI post memory phase. + +@param[in] BoardId An unsigned integrer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardSecurityInit ( + IN UINT16 BoardId +) +{ + switch (BoardId) { + + case BoardIdWhiskeyLakeRvp: + + // TPM interrupt connects to GPIO_CNL_H_GPP_A_7 + PcdSet32S (PcdTpm2CurrentIrqNum, 0x1F); + break; + + } + + return EFI_SUCCESS; +} + +/** +WhiskeyLake board configuration init function for PEI post memory phase. + +@param[in] Content pointer to the buffer contain init information for bo= ard init. + +@retval EFI_SUCCESS The function completed successfully. +@retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +BoardConfigInit( + VOID +) +{ + EFI_STATUS Status; + UINT16 BoardId; + + BoardId =3D BoardIdWhiskeyLakeRvp; + + Status =3D BoardGpioInit(BoardId); + Status =3D TouchPanelGpioInit(BoardId); + Status =3D HdaVerbTableInit(BoardId); + Status =3D BoardMiscInit(BoardId); + Status =3D BoardFunctionInit(BoardId); + Status =3D BoardSecurityInit(BoardId); + + return EFI_SUCCESS; +} + +//@todo Review this functionality and if it is required for WHL SDS +/** +Create the HOB for hotkey status for 'Attempt USB First' feature + +@retval EFI_SUCCESS HOB Creating successful. +@retval Others HOB Creating failed. +**/ +EFI_STATUS +CreateAttemptUsbFirstHotkeyInfoHob( + VOID +) +{ + EFI_STATUS Status; + ATTEMPT_USB_FIRST_HOTKEY_INFO AttemptUsbFirstHotkeyInfo; + + Status =3D EFI_SUCCESS; + + ZeroMem( + &AttemptUsbFirstHotkeyInfo, + sizeof(AttemptUsbFirstHotkeyInfo) + ); + + AttemptUsbFirstHotkeyInfo.RevisonId =3D 0; + AttemptUsbFirstHotkeyInfo.HotkeyTriggered =3D FALSE; + + /// + /// Build HOB for Attempt USB First feature + /// + BuildGuidDataHob( + &gAttemptUsbFirstHotkeyInfoHobGuid, + &(AttemptUsbFirstHotkeyInfo), + sizeof(ATTEMPT_USB_FIRST_HOTKEY_INFO) + ); + + return Status; +} + +/** +Search and identify the physical address of a +file module inside the FW_BINARIES_FV_SIGNED FV + +@retval EFI_SUCCESS If address has been found +@retval Others If address has not been found +**/ +EFI_STATUS +FindModuleInFlash2( + IN EFI_FIRMWARE_VOLUME_HEADER *FvHeader, + IN EFI_GUID *GuidPtr, + IN OUT UINT32 *ModulePtr, + IN OUT UINT32 *ModuleSize +) +{ + EFI_FFS_FILE_HEADER *FfsHeader; + EFI_FV_FILE_INFO FileInfo; + EFI_PEI_FILE_HANDLE FileHandle; + EFI_COMMON_SECTION_HEADER *SectionHeader; + VOID *FileBuffer; + EFI_STATUS Status; + + FfsHeader =3D NULL; + FileHandle =3D NULL; + SectionHeader =3D NULL; + FileBuffer =3D NULL; + + while (TRUE) { + // + // Locate FV_IMAGE file type in the FW_BINARIES_FV_SIGNED firmware vol= ume + // + Status =3D PeiServicesFfsFindNextFile(EFI_FV_FILETYPE_FIRMWARE_VOLUME_= IMAGE, FvHeader, &FileHandle); + if (EFI_ERROR(Status)) { + // unable to find FV_IMAGE file in this FV + break; + } + + FfsHeader =3D (EFI_FFS_FILE_HEADER*)FileHandle; + DEBUG((DEBUG_INFO, "FfsHeader 0x%X:\n", FfsHeader)); + DEBUG((DEBUG_INFO, " Name =3D 0x%g\n", &FfsHeader->Name)); + DEBUG((DEBUG_INFO, " Type =3D 0x%X\n", FfsHeader->Type)); + if (IS_FFS_FILE2(FfsHeader)) { + DEBUG((DEBUG_INFO, " Size =3D 0x%X\n", FFS_FILE2_SIZE(FfsHeader))); + } + else { + DEBUG((DEBUG_INFO, " Size =3D 0x%X\n", FFS_FILE_SIZE(FfsHeader))); + } + + // + // Locate FW_BINARIES_FV FV_IMAGE Section + // + Status =3D PeiServicesFfsFindSectionData(EFI_SECTION_FIRMWARE_VOLUME_I= MAGE, FileHandle, &FileBuffer); + if (EFI_ERROR(Status)) { + // continue to search for the next FV_IMAGE file + DEBUG((DEBUG_INFO, "FW_BINARIES_FV section not found. Status =3D %r\= n", Status)); + continue; + } + + SectionHeader =3D (EFI_COMMON_SECTION_HEADER *)FileBuffer; + DEBUG((DEBUG_INFO, "GUIDED SectionHeader 0x%X:\n", + (UINT32)(UINT8 *)SectionHeader)); + if (IS_SECTION2(SectionHeader)) { + DEBUG((DEBUG_INFO, " Guid =3D 0x%g\n", + &((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->SectionDefinitionGu= id)); + DEBUG((DEBUG_INFO, " DataOfset =3D 0x%X\n", + ((EFI_GUID_DEFINED_SECTION2 *)SectionHeader)->DataOffset)); + } + else { + DEBUG((DEBUG_INFO, " Guid =3D 0x%g\n", + &((EFI_GUID_DEFINED_SECTION *)SectionHeader)->SectionDefinitionGui= d)); + DEBUG((DEBUG_INFO, " DataOfset =3D 0x%X\n", + ((EFI_GUID_DEFINED_SECTION *)SectionHeader)->DataOffset)); + } + DEBUG((DEBUG_INFO, " Type =3D 0x%X\n", SectionHeader->Type)); + + // + // Locate Firmware File System file within Firmware Volume + // + Status =3D PeiServicesFfsFindFileByName(GuidPtr, FileBuffer, (VOID **)= &FfsHeader); + if (EFI_ERROR(Status)) { + // continue to search for the next FV_IMAGE file + DEBUG((DEBUG_INFO, "Module not found. Status =3D %r\n", Status)); + continue; + } + + *ModulePtr =3D (UINT32)((UINT8 *)FfsHeader + sizeof(EFI_FFS_FILE_HEADE= R)); + + // + // Get File Information + // + Status =3D PeiServicesFfsGetFileInfo(FfsHeader, &FileInfo); + if (!EFI_ERROR(Status)) { + *ModuleSize =3D (UINT32)FileInfo.BufferSize; + DEBUG((DEBUG_INFO, "Module {0x%g} found at =3D 0x%X, Size =3D 0x%X\n= ", + &FfsHeader->Name, *ModulePtr, *ModuleSize)); + return Status; + } + } + + return EFI_NOT_FOUND; +} + +/** +Get the ChipsetInit Binary pointer. + +@retval EFI_SUCCESS - ChipsetInit Binary found. +@retval EFI_NOT_FOUND - ChipsetInit Binary not found. +**/ +EFI_STATUS +UpdateChipsetInitPtr( + VOID +) +{ + EFI_STATUS Status; + PCH_STEPPING PchStep; + EFI_FIRMWARE_VOLUME_HEADER *FvHeader; + EFI_GUID *ChipsetInitBinaryGuidPtr; + SI_POLICY_PPI *SiPolicyPpi; + PCH_HSIO_CONFIG *HsioConfig; + UINT32 ModuleAddr; + UINT32 ModuleSize; + + ModuleAddr =3D 0; + ModuleSize =3D 0; + PchStep =3D PchStepping(); + + Status =3D PeiServicesLocatePpi( + &gSiPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPolicyPpi + ); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *)SiPolicyPpi, &gHsioConfigGuid, (VOID *= )&HsioConfig); + ASSERT_EFI_ERROR(Status); + + ChipsetInitBinaryGuidPtr =3D NULL; + if (IsPchLp()) { + switch (PchStep) { + case PCH_D0: + case PCH_D1: + ChipsetInitBinaryGuidPtr =3D &gCnlPchLpChipsetInitTableDxGuid; + DEBUG((DEBUG_INFO, "Using CnlPchLpChipsetInitTable_Dx table \n")); + break; + default: + return EFI_NOT_FOUND; + } + } + else { + return EFI_NOT_FOUND; + } + + // + // Locate Firmware Volume header + // + // FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *)(UINTN)GetFvBinaryBase(); + FvHeader =3D (EFI_FIRMWARE_VOLUME_HEADER *) FixedPcdGet32(PcdFlashFvPost= MemoryBase); + Status =3D FindModuleInFlash2(FvHeader, ChipsetInitBinaryGuidPtr, &Modul= eAddr, &ModuleSize); + // + // Get ChipsetInit Binary Pointer + // + HsioConfig->ChipsetInitBinPtr =3D ModuleAddr; + + // + // Get File Size + // + HsioConfig->ChipsetInitBinLen =3D ModuleSize; + + DEBUG((DEBUG_INFO, "ChipsetInit Binary Location: %x\n", HsioConfig->Chip= setInitBinPtr)); + DEBUG((DEBUG_INFO, "ChipsetInit Binary Size: %x\n", HsioConfig->ChipsetI= nitBinLen)); + + return Status; +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeSiliconInit ( + VOID + ) +{ + EFI_STATUS Status; + UINT8 FwConfig; + + BoardConfigInit(); + // + // Configure GPIO and SIO + // + Status =3D BoardInit(); + ASSERT_EFI_ERROR(Status); + + FwConfig =3D FwConfigProduction; + PeiPolicyInit(FwConfig); + + // + // Create USB Boot First hotkey information HOB + // + CreateAttemptUsbFirstHotkeyInfoHob(); + + // + // Initializing Platform Specific Programming + // + Status =3D PlatformSpecificInit(); + ASSERT_EFI_ERROR(Status); + + // + // Update ChipsetInitPtr + // + Status =3D UpdateChipsetInitPtr(); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c b/Platform/Intel/Whiskeylak= eOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPr= eMemLib.c new file mode 100644 index 0000000000..519a5be216 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/PeiWhiskeylakeURvpInitPreMemLib.c @@ -0,0 +1,636 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "PeiWhiskeylakeURvpInitLib.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/// +/// Reset Generator I/O Port +/// +#define RESET_GENERATOR_PORT 0xCF9 + +typedef struct { + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 Length; +} MEMORY_MAP; + +// +// Reference RCOMP resistors on motherboard - for WHL RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp1[SA_MRC_MAX= _RCOMP] =3D { 200, 81, 162 }; + +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for WH= L RVP1 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_R= COMP_TARGETS] =3D { 100, 40, 40, 23, 40 }; + +GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] =3D { + { FixedPcdGet64(PcdApicLocalAddress), FixedPcdGet32(PcdApicLocalMmioSize= ) }, + { FixedPcdGet64(PcdMchBaseAddress), FixedPcdGet32(PcdMchMmioSize) }, + { FixedPcdGet64(PcdDmiBaseAddress), FixedPcdGet32(PcdDmiMmioSize) }, + { FixedPcdGet64(PcdEpBaseAddress), FixedPcdGet32(PcdEpMmioSize) }, + { FixedPcdGet64(PcdGdxcBaseAddress), FixedPcdGet32(PcdGdxcMmioSize) } +}; + +EFI_STATUS +MrcConfigInit( + IN UINT16 BoardId +); + +EFI_STATUS +SaGpioConfigInit( + IN UINT16 BoardId +); + +EFI_STATUS + SaMiscConfigInit( +IN UINT16 BoardId +); + +EFI_STATUS + RootPortClkInfoInit( +IN UINT16 BoardId +); + +EFI_STATUS + UsbConfigInit( +IN UINT16 BoardId +); + +EFI_STATUS +GpioGroupTierInit( + IN UINT16 BoardId +); + +EFI_STATUS +GpioTablePreMemInit( + IN UINT16 BoardId +); + +EFI_STATUS +PchPmConfigInit( + IN UINT16 BoardId +); + +EFI_STATUS +SaDisplayConfigInit( + IN UINT16 BoardId +); + +EFI_STATUS +BoardFunctionInitPreMem( + IN UINT16 BoardId +); + +EFI_STATUS +EFIAPI +PlatformInitPreMemCallBack( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +); + +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotify( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +); + +EFI_STATUS +EFIAPI +PchReset( + IN CONST EFI_PEI_SERVICES **PeiServices +); + +static EFI_PEI_RESET_PPI mResetPpi =3D { + PchReset +}; + +static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] =3D { + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiResetPpiGuid, + &mResetPpi + } +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEfiPeiReadOnlyVariable2PpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack +}; + +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEfiPeiMemoryDiscoveredPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify +}; + +/** +Board misc init function for PEI pre-memory phase. + +@param[in] BoardId An unsigned integer represent the board id. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardMiscInitPreMem( + IN UINT16 BoardId +) +{ + PCD64_BLOB PcdData; + + // + // RecoveryMode GPIO + // + PcdData.Blob =3D 0; + PcdData.BoardGpioConfig.Type =3D BoardGpioTypeNotSupported; + + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdData.BoardGpioConfig.Type =3D BoardGpioTypePch; + PcdData.BoardGpioConfig.u.Pin =3D GPIO_CNL_LP_GPP_F10; + break; + + default: + break; + } + + // + // Configure WWAN Full Card Power Off and reset pins + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + // + // According to board default settings, GPP_D16 is used to enable/di= sable modem + // power. An alternative way to contol modem power is to toggle FCP_= OFF via GPP_D13 + // but board rework is required. + // + PcdSet32S(PcdWwanFullCardPowerOffGpio, GPIO_CNL_LP_GPP_D16); + PcdSet32S(PcdWwanBbrstGpio, GPIO_CNL_LP_GPP_F1); + PcdSet32S(PcdWwanPerstGpio, GPIO_CNL_LP_GPP_E15); + PcdSet8S(PcdWwanPerstGpioPolarity, 1); + break; + + default: + break; + } + + PcdSet64S(PcdRecoveryModeGpio, PcdData.Blob); + + // + // Pc8374SioKbc Present + // + PcdSetBoolS(PcdPc8374SioKbcPresent, FALSE); + + return EFI_SUCCESS; +} + +//@todo it should be moved to Si Pkg. +/** +Early Platform PCH initialization +**/ +VOID +EarlyPlatformPchInit( + VOID +) +{ + UINT8 Data8; + UINT8 TcoRebootHappened; + TCO_WDT_HOB *TcoWdtHobPtr; + EFI_STATUS Status; + + /// + /// Read the Second TO status bit + /// + Data8 =3D IoRead8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS); + if ((Data8 & B_TCO_IO_TCO2_STS_SECOND_TO) =3D=3D B_TCO_IO_TCO2_STS_SECON= D_TO) { + TcoRebootHappened =3D 1; + DEBUG((DEBUG_INFO, "PlatformInitPreMem - TCO Second TO status bit is s= et. This might be a TCO reboot\n")); + } + else { + TcoRebootHappened =3D 0; + } + + /// + /// Create HOB + /// + Status =3D PeiServicesCreateHob(EFI_HOB_TYPE_GUID_EXTENSION, sizeof(TCO_= WDT_HOB), (VOID **)&TcoWdtHobPtr); + if (!EFI_ERROR(Status)) { + TcoWdtHobPtr->Header.Name =3D gTcoWdtHobGuid; + TcoWdtHobPtr->TcoRebootHappened =3D TcoRebootHappened; + } + + /// + /// Clear the Second TO status bit + /// + IoWrite8(PcdGet16(PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO2_= STS_SECOND_TO); +} + +/** +Board init function for PEI pre-memory phase. + +@param Content pointer to the buffer contain init information for board = init. + +@retval EFI_SUCCESS The function completed successfully. +@retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +BoardConfigInitPreMem( + VOID +) +{ + EFI_STATUS Status; + UINT16 BoardId; + + BoardId =3D BoardIdWhiskeyLakeRvp; + + Status =3D MrcConfigInit(BoardId); + Status =3D SaGpioConfigInit(BoardId); + Status =3D SaMiscConfigInit(BoardId); + Status =3D RootPortClkInfoInit(BoardId); + Status =3D UsbConfigInit(BoardId); + Status =3D GpioGroupTierInit(BoardId); + Status =3D GpioTablePreMemInit(BoardId); + Status =3D PchPmConfigInit(BoardId); + Status =3D BoardMiscInitPreMem(BoardId); + Status =3D SaDisplayConfigInit(BoardId); + Status =3D BoardFunctionInitPreMem(BoardId); + + return EFI_SUCCESS; +} + +/** +This function handles PlatformInit task after PeiReadOnlyVariable2 PPI pro= duced + +@param[in] PeiServices Pointer to PEI Services Table. +@param[in] NotifyDesc Pointer to the descriptor for the Notification e= vent that + caused this function to execute. +@param[in] Ppi Pointer to the PPI data associated with this fun= ction. + +@retval EFI_SUCCESS The function completes successfully +@retval others +**/ +EFI_STATUS +EFIAPI +PlatformInitPreMemCallBack( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +) +{ + EFI_STATUS Status; + UINT16 ABase; + UINT8 FwConfig; + UINT8 SynchDelay; + + // + // Init Board Config Pcd. + // + BoardConfigInitPreMem(); + + DEBUG((DEBUG_ERROR, "Fail to get System Configuration and set the config= uration to production mode!\n")); + FwConfig =3D FwConfigProduction; + SynchDelay =3D 0; + PcdSetBoolS(PcdPcieWwanEnable, FALSE); + PcdSetBoolS(PcdWwanResetWorkaround, FALSE); + + // + // Early Board Configuration before memory is ready. + // + Status =3D BoardInitEarlyPreMem(); + ASSERT_EFI_ERROR(Status); + + /// + /// If there was unexpected reset but no WDT expiration and no resume fr= om S3/S4, + /// clear unexpected reset status and enforce expiration. This is to inf= orm Firmware + /// which has no access to unexpected reset status bit, that something w= ent wrong. + /// + OcWdtResetCheck(); + + Status =3D OcWdtInit(); + ASSERT_EFI_ERROR(Status); + + // + // Initialize Intel PEI Platform Policy + // + PeiPolicyInitPreMem(FwConfig); + + /// + /// Configure GPIO and SIO + /// + Status =3D BoardInitPreMem(); + ASSERT_EFI_ERROR(Status); + + ABase =3D PmcGetAcpiBase(); + + /// + /// Clear all pending SMI. On S3 clear power button enable so it will no= t generate an SMI. + /// + IoWrite16(ABase + R_ACPI_IO_PM1_EN, 0); + IoWrite32(ABase + R_ACPI_IO_GPE0_EN_127_96, 0); + + /// + /// Install Pre Memory PPIs + /// + Status =3D PeiServicesInstallPpi(&mPreMemPpiList[0]); + ASSERT_EFI_ERROR(Status); + + return Status; +} + +/** +Provide hard reset PPI service. +To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9= ). + +@param[in] PeiServices General purpose services available to every = PEIM. + +@retval Not return System reset occured. +@retval EFI_DEVICE_ERROR Device error, could not reset the system. +**/ +EFI_STATUS +EFIAPI +PchReset( + IN CONST EFI_PEI_SERVICES **PeiServices +) +{ + DEBUG((DEBUG_INFO, "Perform Cold Reset\n")); + IoWrite8(RESET_GENERATOR_PORT, 0x0E); + + CpuDeadLoop(); + + /// + /// System reset occured, should never reach at this line. + /// + ASSERT_EFI_ERROR(EFI_DEVICE_ERROR); + + return EFI_DEVICE_ERROR; +} + +/** +Install Firmware Volume Hob's once there is main memory + +@param[in] PeiServices General purpose services available to every = PEIM. +@param[in] NotifyDescriptor Notify that this module published. +@param[in] Ppi PPI that was installed. + +@retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotify( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi +) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINTN Index; + UINT8 PhysicalAddressBits; + UINT32 RegEax; + MEMORY_MAP PcieMmioMap; + + Index =3D 0; + + Status =3D PeiServicesGetBootMode(&BootMode); + ASSERT_EFI_ERROR(Status); + + AsmCpuid(0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000008) { + AsmCpuid(0x80000008, &RegEax, NULL, NULL, NULL); + PhysicalAddressBits =3D (UINT8)RegEax; + } + else { + PhysicalAddressBits =3D 36; + } + + /// + /// Create a CPU hand-off information + /// + BuildCpuHob(PhysicalAddressBits, 16); + + /// + /// Build Memory Mapped IO Resource which is used to build E820 Table in= LegacyBios. + /// + PcieMmioMap.BaseAddress =3D FixedPcdGet64(PcdPciExpressBaseAddress); + PcieMmioMap.Length =3D PcdGet32(PcdPciExpressRegionLength); + + BuildResourceDescriptorHob( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + PcieMmioMap.BaseAddress, + PcieMmioMap.Length + ); + BuildMemoryAllocationHob( + PcieMmioMap.BaseAddress, + PcieMmioMap.Length, + EfiMemoryMappedIO + ); + for (Index =3D 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP)); Index+= +) { + BuildResourceDescriptorHob( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + MmioMap[Index].BaseAddress, + MmioMap[Index].Length + ); + BuildMemoryAllocationHob( + MmioMap[Index].BaseAddress, + MmioMap[Index].Length, + EfiMemoryMappedIO + ); + } + + // + // Report resource HOB for flash FV + // + BuildResourceDescriptorHob( + EFI_RESOURCE_MEMORY_MAPPED_IO, + (EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE), + (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress), + (UINTN)FixedPcdGet32(PcdFlashAreaSize) + ); + BuildMemoryAllocationHob( + (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress), + (UINTN)FixedPcdGet32(PcdFlashAreaSize), + EfiMemoryMappedIO + ); + + BuildFvHob( + (UINTN)FixedPcdGet32(PcdFlashAreaBaseAddress), + (UINTN)FixedPcdGet32(PcdFlashAreaSize) + ); + + return Status; +} + + +/** + Board configuration init function for PEI pre-memory phase. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_INVALID_PARAMETER The parameter is NULL. +**/ +EFI_STATUS +EFIAPI +WhiskeylakeURvpInitPreMem ( + VOID + ) +{ + EFI_STATUS Status; + + /// + /// Install Stall PPI + /// + Status =3D InstallStallPpi(); + ASSERT_EFI_ERROR(Status); + + ///@todo it should be moved to Si Pkg. + /// + /// Do Early PCH init + /// + EarlyPlatformPchInit(); + + // + // Install PCH RESET PPI and EFI RESET2 PeiService + // + Status =3D PchInitializeReset(); + ASSERT_EFI_ERROR(Status); + + /// + /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI= produced + /// + Status =3D PeiServicesNotifyPpi(&mPreMemNotifyList); + + /// + /// After code reorangized, memorycallback will run because the PPI is a= lready + /// installed when code run to here, it is supposed that the InstallEfiM= emory is + /// done before. + /// + Status =3D PeiServicesNotifyPpi(&mMemDiscoveredNotifyList); + + return EFI_SUCCESS; +} + +/** + Configure GPIO and SIO before memory ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardInitBeforeMemoryInit ( + VOID + ) +{ + WhiskeylakeURvpInitPreMem (); + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +WhiskeylakeURvpBoardDebugInit ( + VOID + ) +{ + UINT64 LpcBaseAddress; + + /// + /// LPC I/O Configuration + /// + PchLpcIoDecodeRangesSet( + (V_LPC_CFG_IOD_LPT_378 << N_LPC_CFG_IOD_LPT) | + (V_LPC_CFG_IOD_COMB_3E8 << N_LPC_CFG_IOD_COMB) | + (V_LPC_CFG_IOD_COMA_3F8 << N_LPC_CFG_IOD_COMA) + ); + + PchLpcIoEnableDecodingSet( + B_LPC_CFG_IOE_ME2 | + B_LPC_CFG_IOE_SE | + B_LPC_CFG_IOE_ME1 | + B_LPC_CFG_IOE_KE | + B_LPC_CFG_IOE_HGE | + B_LPC_CFG_IOE_LGE | + B_LPC_CFG_IOE_FDE | + B_LPC_CFG_IOE_PPE | + B_LPC_CFG_IOE_CBE | + B_LPC_CFG_IOE_CAE + ); + + /// + /// Enable LPC IO decode for EC access + /// + LpcBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + PCI_DEVICE_NUMBER_PCH_LPC, + PCI_FUNCTION_NUMBER_PCH_LPC, + 0 + ); + + return EFI_SUCCESS; +} + +EFI_BOOT_MODE +EFIAPI +WhiskeylakeURvpBoardBootModeDetect ( + VOID + ) +{ + return BOOT_WITH_FULL_CONFIGURATION; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /BoardInitLib/WhiskeylakeURvpHsioPtssTables.c b/Platform/Intel/WhiskeylakeO= penBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpHsioPtssTab= les.c new file mode 100644 index 0000000000..8d8ca835bc --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI= nitLib/WhiskeylakeURvpHsioPtssTables.c @@ -0,0 +1,32 @@ +/** @file + WhiskeylakeURvp HSIO PTSS H File + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef WHISKEYLAKE_RVP3_HSIO_PTSS_H_ +#define WHISKEYLAKE_RVP3_HSIO_PTSS_H_ + +#include + +#ifndef HSIO_PTSS_TABLE_SIZE +#define HSIO_PTSS_TABLE_SIZE(A) A##_Size =3D sizeof (A) / sizeof (HSIO_PTS= S_TABLES) +#endif + +//BoardId WhiskeylakeURvp +HSIO_PTSS_TABLES PchLpHsioPtss_Cx_WhiskeylakeURvp[] =3D { + {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0} +}; + +UINT16 PchLpHsioPtss_Cx_WhiskeylakeURvp_Size =3D sizeof(PchLpHsioPtss_Cx_W= hiskeylakeURvp) / sizeof(HSIO_PTSS_TABLES); + +HSIO_PTSS_TABLES PchLpHsioPtss_Bx_WhiskeylakeURvp[] =3D { + {{14, 0, 0xa0, 0x00000000, (UINT32) ~0x3F3F00}, 0}, +}; + +UINT16 PchLpHsioPtss_Bx_WhiskeylakeURvp_Size =3D sizeof(PchLpHsioPtss_Bx_W= hiskeylakeURvp) / sizeof(HSIO_PTSS_TABLES); + +#endif // WHISKEYLAKE_RVP3_HSIO_PTSS_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /DxePolicyBoardConfigLib/DxeSaPolicyBoardConfig.c b/Platform/Intel/Whiskeyl= akeOpenBoardPkg/WhiskeylakeURvp/Library/DxePolicyBoardConfigLib/DxeSaPolicy= BoardConfig.c new file mode 100644 index 0000000000..d2c26eb163 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/DxePol= icyBoardConfigLib/DxeSaPolicyBoardConfig.c @@ -0,0 +1,35 @@ +/** @file + Intel DXE SA Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "DxePolicyBoardConfig.h" + +/** + This function performs DXE SA Policy update by board configuration. + + @param[in, out] DxeSaPolicy DXE SA Policy + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdateDxeSaPolicyBoardConfig ( + IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy + ) +{ + EFI_STATUS Status; + MEMORY_DXE_CONFIG *MemoryDxeConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in DXE\n")); + + Status =3D GetConfigBlock ((VOID *)DxeSaPolicy, &gMemoryDxeConfigGuid, (= VOID *)&MemoryDxeConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/WhiskeylakeOpenBo= ardPkg/WhiskeylakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..c495a3a401 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPla= tformHookLib/PeiPlatformHooklib.c @@ -0,0 +1,299 @@ +/** @file + PEI Library Functions. Initialize GPIOs + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680 + +#define RECOVERY_MODE_GPIO_PIN 0 // = Platform specific @todo use PCD + +#define MANUFACTURE_MODE_GPIO_PIN 0 // = Platform specific @todo use PCD + +/** + Configures GPIO + + @param[in] GpioTable Point to Platform Gpio table + @param[in] GpioTableCount Number of Gpio table entries + +**/ +VOID +ConfigureGpio ( + IN GPIO_INIT_CONFIG *GpioDefinition, + IN UINT16 GpioTableCount + ) +{ + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n")); + + + CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount); + + + GpioConfigurePads (GpioTableCount, GpioDefinition); + + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n")); +} + +/** + Configure GPIO group GPE tier. + + @retval none. +**/ +VOID +GpioGroupTierInitHook( + VOID + ) +{ + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n")); + + if (PcdGet32 (PcdGpioGroupToGpeDw0)) { + GpioSetGroupToGpeDwX (PcdGet32 (PcdGpioGroupToGpeDw0), + PcdGet32 (PcdGpioGroupToGpeDw1), + PcdGet32 (PcdGpioGroupToGpeDw2)); + } + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n")); +} + +/** + Configure single GPIO pad for touchpanel interrupt +**/ +VOID +TouchpanelGpioInit ( + VOID + ) +{ + GPIO_INIT_CONFIG* TouchpanelPad; + GPIO_PAD_OWN PadOwnVal; + + PadOwnVal =3D 0; + TouchpanelPad =3D (VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableTouchPanel= ); + if (TouchpanelPad !=3D NULL) { + GpioGetPadOwnership (TouchpanelPad->GpioPad, &PadOwnVal); + if (PadOwnVal =3D=3D GpioPadOwnHost) { + GpioConfigurePads (1, TouchpanelPad); + } + } +} + +/** + Configure GPIO Before Memory is not ready. + +**/ +VOID +GpioInitPreMem ( + VOID + ) +{ + if (PcdGet32 (PcdBoardGpioTablePreMem) !=3D 0 && PcdGet16 (PcdBoardGpioT= ablePreMemSize) !=3D 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTablePreMem), (U= INTN) PcdGet16 (PcdBoardGpioTablePreMemSize)); + } +} + +/** + Basic GPIO configuration before memory is ready + +**/ +VOID +GpioInitEarlyPreMem ( + VOID + ) +{ + GPIO_CONFIG BbrstConfig; + UINT32 WwanBbrstGpio; + + WwanBbrstGpio =3D PcdGet32 (PcdWwanBbrstGpio); + + if (WwanBbrstGpio) { + // + // BIOS needs to put modem in OFF state for the two scenarios below. + // 1. Modem RESET# is not asserted via PLTRST# in the previous sleep s= tate + // 2. Modem is disabled via setup option + // + GpioGetPadConfig (WwanBbrstGpio, &BbrstConfig); + if ((PcdGetBool (PcdPcieWwanEnable) =3D=3D FALSE) || + (PcdGetBool (PcdWwanResetWorkaround) =3D=3D TRUE && + BbrstConfig.Direction =3D=3D GpioDirOut && + BbrstConfig.OutputState =3D=3D GpioOutHigh)) { + // + // Assert FULL_CARD_POWER_OFF#, RESET# and PERST# GPIOs + // + if (PcdGet32 (PcdBoardGpioTableWwanOffEarlyPreMem) !=3D 0 && PcdGet1= 6 (PcdBoardGpioTableWwanOffEarlyPreMemSize) !=3D 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOff= EarlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOffEarlyPreMemSize)); + } + if (PcdGetBool (PcdPcieWwanEnable) =3D=3D TRUE && PcdGetBool (PcdWwa= nResetWorkaround) =3D=3D TRUE) { + MicroSecondDelay (1 * 1000); // Delay by 1ms + } + } + + // + // Turn ON modem power and de-assert RESET# and PERST# GPIOs + // + if (PcdGetBool (PcdPcieWwanEnable) =3D=3D TRUE) { + if (PcdGet32 (PcdBoardGpioTableWwanOnEarlyPreMem) !=3D 0 && PcdGet16= (PcdBoardGpioTableWwanOnEarlyPreMemSize) !=3D 0) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTableWwanOnE= arlyPreMem), (UINTN) PcdGet16 (PcdBoardGpioTableWwanOnEarlyPreMemSize)); + } + } + } +} + +/** + Configure GPIO + +**/ +VOID +GpioInit ( + VOID + ) +{ + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) Pc= dGet16 (PcdBoardGpioTableSize)); + + if (PcdGet32 (PcdBoardGpioTable2)) { + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable2), (UINTN)= PcdGet16 (PcdBoardGpioTable2Size)); + } + + TouchpanelGpioInit(); + + // + // Lock pads after initializing platform GPIO. + // Pads which were requested to be unlocked during configuration + // will not be locked. + // + GpioLockPads (); + + return; +} + +/** + Configure Super IO + +**/ +VOID +SioInit ( + VOID + ) +{ + // + // Program and Enable Default Super IO Configuration Port Addresses and = range + // + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x1= 0); + + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10); + return; +} + +/** + Configure GPIO and SIO before memory ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitPreMem ( + VOID + ) +{ + // + // Obtain Platform Info from HOB. + // + GpioInitPreMem (); + GpioGroupTierInitHook (); + SioInit (); + + return EFI_SUCCESS; +} + +/** + Configure GPIO and SIO + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInit ( + VOID + ) +{ + + GpioInit (); + + return EFI_SUCCESS; +} + +/** + Do platform specific programming post-memory. + + @retval EFI_SUCCESS The function completed successfully. +**/ + +EFI_STATUS +PlatformSpecificInit ( + VOID + ) +{ + GPIO_CONFIG GpioConfig; + + if (IsCnlPch ()) { + + // + // Tristate unused pins by audio link mode. + // + ZeroMem(&GpioConfig, sizeof(GPIO_CONFIG)); + GpioConfig.PadMode =3D GpioPadModeGpio; + GpioConfig.HostSoftPadOwn =3D GpioHostOwnGpio; + GpioConfig.Direction =3D GpioDirNone; + GpioConfig.OutputState =3D GpioOutDefault; + GpioConfig.InterruptConfig =3D GpioIntDis; + GpioConfig.PowerConfig =3D GpioPlatformReset; + GpioConfig.ElectricalConfig =3D GpioTermNone; + + GpioSetPadConfig (GPIO_CNL_LP_SSP1_SFRM, &GpioConfig); + GpioSetPadConfig (GPIO_CNL_LP_SSP1_TXD, &GpioConfig); + + } + + return EFI_SUCCESS; +} + +/** + Early Board Configuration before memory is ready + + @retval EFI_SUCCESS Operation success. +**/ +EFI_STATUS +BoardInitEarlyPreMem ( + VOID + ) +{ + GpioInitEarlyPreMem (); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfig.c b/Platform/Intel/Whiskey= lakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiCpuPoli= cyBoardConfig.c new file mode 100644 index 0000000000..e437814b10 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiCpuPolicyBoardConfig.c @@ -0,0 +1,48 @@ +/** @file + Intel PEI CPU Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI CPU Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + CPU_CONFIG *CpuConfig; + + DEBUG((DEBUG_INFO, "Updating CPU Policy by board config in Post Mem\n")); + + Status =3D PeiServicesLocatePpi( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC= onfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gCpuConfigGuid, (VOID = *) &CpuConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c b/Platform/Intel/W= hiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiC= puPolicyBoardConfigPreMem.c new file mode 100644 index 0000000000..3797df0856 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiCpuPolicyBoardConfigPreMem.c @@ -0,0 +1,29 @@ +/** @file + Intel PEI CPU Pre-Memory Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" +#include + +/** + This function performs PEI CPU Pre-Memory Policy update by board configu= ration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiCpuPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiMePolicyBoardConfig.c b/Platform/Intel/Whiskeyl= akeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMePolicy= BoardConfig.c new file mode 100644 index 0000000000..843fe4accd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiMePolicyBoardConfig.c @@ -0,0 +1,35 @@ +/** @file + Intel PEI ME Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI ME Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + ME_PEI_CONFIG *MePeiConfig; + + DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Post Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gMePeiConfigGuid, (VOI= D *) &MePeiConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c b/Platform/Intel/Wh= iskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiMe= PolicyBoardConfigPreMem.c new file mode 100644 index 0000000000..79c93455a6 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiMePolicyBoardConfigPreMem.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI ME Pre-Memory Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI ME Pre-Memory Policy update by board configur= ation. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiMePolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + ME_PEI_PREMEM_CONFIG *MePeiPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating ME Policy by board config in Pre Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMePeiPreMemConf= igGuid, (VOID *) &MePeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfig.c b/Platform/Intel/Whiskey= lakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiPchPoli= cyBoardConfig.c new file mode 100644 index 0000000000..5dbc412879 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiPchPolicyBoardConfig.c @@ -0,0 +1,35 @@ +/** @file + Intel PEI PCH Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI PCH Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + PCH_GENERAL_CONFIG *PchGeneralConfig; + + DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Post Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gPchGeneralConfigGuid,= (VOID *) &PchGeneralConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c b/Platform/Intel/W= hiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiP= chPolicyBoardConfigPreMem.c new file mode 100644 index 0000000000..1080015029 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiPchPolicyBoardConfigPreMem.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI PCH Pre-Memory Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI PCH Pre-Memory Policy update by board configu= ration. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiPchPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + PCH_GENERAL_PREMEM_CONFIG *PchGeneralPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating PCH Policy by board config in Pre Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gPchGeneralPreMe= mConfigGuid, (VOID *) &PchGeneralPreMemConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfig.c b/Platform/Intel/Whiskeyl= akeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSaPolicy= BoardConfig.c new file mode 100644 index 0000000000..d1d964aea7 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiSaPolicyBoardConfig.c @@ -0,0 +1,35 @@ +/** @file + Intel PEI SA Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI SA Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + EFI_STATUS Status; + GRAPHICS_PEI_CONFIG *GtConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Post Mem\n")); + + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGuid= , (VOID *)&GtConfig); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c b/Platform/Intel/Wh= iskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSa= PolicyBoardConfigPreMem.c new file mode 100644 index 0000000000..34fca7fac3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiSaPolicyBoardConfigPreMem.c @@ -0,0 +1,36 @@ +/** @file + Intel PEI SA Pre-Memory Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI SA Pre-Memory Policy update by board configur= ation. + + @param[in, out] SiPolicy The SI PreMem Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSaPolicyBoardConfigPreMem ( + IN OUT SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi + ) +{ + EFI_STATUS Status; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + + DEBUG((DEBUG_INFO, "Updating SA Policy by board config in Pre Mem\n")); + + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreMemC= onfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR(Status); + + return Status; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library= /PeiPolicyBoardConfigLib/PeiSiPolicyBoardConfig.c b/Platform/Intel/Whiskeyl= akeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPolicyBoardConfigLib/PeiSiPolicy= BoardConfig.c new file mode 100644 index 0000000000..f5f38910a8 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/PeiPol= icyBoardConfigLib/PeiSiPolicyBoardConfig.c @@ -0,0 +1,27 @@ +/** @file + Intel PEI SA Policy update by board configuration + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiPolicyBoardConfig.h" + +/** + This function performs PEI SI Policy update by board configuration. + + @param[in, out] SiPolicy The SI Policy PPI instance + + @retval EFI_SUCCESS The SI Policy is successfully updated. + @retval Others The SI Policy is not successfully update= d. +**/ +EFI_STATUS +EFIAPI +UpdatePeiSiPolicyBoardConfig ( + IN OUT SI_POLICY_PPI *SiPolicyPpi + ) +{ + return EFI_SUCCESS; +} + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45911): https://edk2.groups.io/g/devel/message/45911 Mute This Topic: https://groups.io/mt/32918205/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45913+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45913+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001035; cv=none; d=zoho.com; s=zohoarc; b=jJqaPiVzuIiBPjObQbszvWkwHJe4MkoxajQP3QlqHKxCFjN6gtub+dUwrJB6NpTBQFBiv4mfYEbm2dOiZsAe7Clk3IVMxqBZ4tNF6g2aEx4I/zSxj1j4eRd4W8sYIuw2+Zv/5U8qgFee9lE7Fe2YmC0csG1kOw+Xeg7OSUdz30w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001035; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=cBfxc88V/wzrXst7nb4w3iM3eP978aYcXhc41uFgWvs=; b=eVQ14kx4pLwivRz/q0yeUKW0Wi0JGy8DIatWGuimD5U1bWPhixr4cpC9++AHx6TuXe2KnqP570W5KjH/7Sbm/20ZHXeFTXDn9TLYnxD+A6Z5fgqTe1pj0ysBuE2hfY66AayfAad/oAZECwcOjqCKb/OUCd1O7YnNr1FuK+Ml9O0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45913+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001035161450.36990393614883; Fri, 16 Aug 2019 17:17:15 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:13 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:17:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319379" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:17:00 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 35/37] WhiskeylakeOpenBoardPkg: Add modules Date: Fri, 16 Aug 2019 17:16:01 -0700 Message-Id: <20190817001603.30632-36-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001034; bh=6hQaJfEr7q7nE7jgOsi+WrutYpaiKhvj/uLKD5cJF6g=; h=Cc:Date:From:Reply-To:Subject:To; b=NiG5uhl8ezi+XXJ3YSaK1xN7mu5r+yuIy8vidiTfoVT+zAhAw5/sgpzV1/f0uJKpQvf JsBL419rlRL6JVx7HgRTtpsgQlxqIcrOMfvBXmb5IRIBibcwAAPl60wedbgCkgEJ/fuE4 jUaaEzkcsWXw3o7r6nk6VZnSKKttT8coJhU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 Modules shared across board instances. * BoardAcpiDxe - Performs DXE board ACPI initialization. * PciHotPlug - Performs PCI-e resource configuration. * PeiTbtInit - Initializes Thunderbolt policy in PEI. * PolicyInitDxe - Initializes policy in DXE. * TbtDxe - Performs Thunderbolt initialization in DXE. * TbtSmm - Performs Thunderbolt initialization in SMM. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf = | 71 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.inf = | 62 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.inf= | 51 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit= .inf | 47 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf= | 80 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.= inf | 176 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.h = | 130 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHand= ler.h | 180 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.h= | 32 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitD= xe.h | 38 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitD= xe.h | 41 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitD= xe.h | 52 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.= h | 45 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDx= e.h | 56 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyI= nitDxe.h | 37 + Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit.c = | 96 + Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe.c = | 290 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug.c = | 353 ++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDxe.c = | 228 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTbtInit= .c | 211 +++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmiHand= ler.c | 1609 +++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.c = | 1765 ++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/AcpiTimerLib.c= | 394 ++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c= | 612 +++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicyInitD= xe.c | 46 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicyInitD= xe.c | 174 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicyInitD= xe.c | 55 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyInitDxe.= c | 88 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyInitDx= e.c | 60 + Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPolicyI= nitDxe.c | 46 + Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.asl = | 20 + Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL = | 37 + Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus.asl = | 516 ++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree.asl = | 309 ++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platform.asl= | 76 + Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3PcieTbt= .asl | 405 +++++ Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl = | 1877 ++++++++++++++++++++ 37 files changed, 10365 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Board= AcpiDxe.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Boar= dAcpiDxe.inf new file mode 100644 index 0000000000..2bbc3cb9e2 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe= .inf @@ -0,0 +1,71 @@ +## @file +# Component information file for AcpiPlatform module +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D BoardAcpiDxe + FILE_GUID =3D E269E77D-6163-4F5D-8E59-21EAF114D307 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InstallAcpiBoard + +[Sources.common] + BoardAcpiDxe.c + AcpiGnvsInit.c + Dsdt/DSDT.ASL + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + PcAtChipsetPkg/PcAtChipsetPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + BaseLib + DebugLib + IoLib + PcdLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseMemoryLib + HobLib + AslUpdateLib + BoardAcpiTableLib + +[Protocols] + gEfiAcpiTableProtocolGuid ## CONSUMES + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + gEfiMpServiceProtocolGuid ## CONSUMES + gEfiGlobalNvsAreaProtocolGuid + +[Pcd] + gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress + + gBoardModuleTokenSpaceGuid.PcdAcpiSleepState + gBoardModuleTokenSpaceGuid.PcdAcpiHibernate + gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle + gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints + gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints + gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints + +[Depex] + gEfiAcpiTableProtocolGuid AND + gEfiFirmwareVolume2ProtocolGuid AND + gEfiPciRootBridgeIoProtocolGuid AND + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/Pci= HotPlug.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/Pc= iHotPlug.inf new file mode 100644 index 0000000000..dd4e41a409 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug= .inf @@ -0,0 +1,62 @@ +## @file +# This module will perform specific PCI-Express devices +# resource configuration. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PciHotPlug + FILE_GUID =3D 3022E512-B94A-4F12-806D-7EF1177899D8 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + ENTRY_POINT =3D PciHotPlug +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseMemoryLib + MemoryAllocationLib + DevicePathLib + DebugLib + UefiLib + HobLib + PchPcieRpLib + ConfigBlockLib + TbtCommonLib + +[Packages] + MdePkg/MdePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PciHotPlug.c + PciHotPlug.h + +[Protocols] + gEfiPciHotPlugInitProtocolGuid ## PRODUCES + gSaPolicyProtocolGuid ## CONSUMES + +[Guids] + gEfiHobListGuid ## CONSUMES + gPcieRpConfigGuid ## CONSUMES + +[Pcd] + +[Depex] + gDxeTbtPolicyProtocolGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Dx= e/TbtDxe.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/= Dxe/TbtDxe.inf new file mode 100644 index 0000000000..5160bb1dbb --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDx= e.inf @@ -0,0 +1,51 @@ +## @file +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D TbtDxe + FILE_GUID =3D 19C9762C-3A88-41B0-906F-8C4C2895A887 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + ENTRY_POINT =3D TbtDxeEntryPoint + +[LibraryClasses] + DebugLib + BaseMemoryLib + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + UefiDriverEntryPoint + HobLib + UefiLib + TbtCommonLib + DxeTbtPolicyLib + AslUpdateLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + TbtDxe.c + +[Protocols] + gTbtNvsAreaProtocolGuid ## CONSUMES + gDxeTbtPolicyProtocolGuid + +[Guids] + gTbtInfoHobGuid ## CONSUMES + +[Depex] + gEfiVariableWriteArchProtocolGuid AND + gEfiVariableArchProtocolGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Pe= i/PeiTbtInit.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtI= nit/Pei/PeiTbtInit.inf new file mode 100644 index 0000000000..07962ffa10 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTb= tInit.inf @@ -0,0 +1,47 @@ +## @file +# Component information file for the TBT Init PEI module. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiTbtInit + FILE_GUID =3D 90BF2BFB-F998-4cbc-AD72-008D4D047A4B + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D TbtInitEntryPoint + +[LibraryClasses] + PeimEntryPoint + DebugLib + HobLib + PeiServicesLib + PeiTbtPolicyLib + PeiDTbtInitLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Sources] + PeiTbtInit.c + +[Guids] + gTbtInfoHobGuid ## CONSUMES + +[Ppis] + gEfiEndOfPeiSignalPpiGuid ## CONSUMES + gPeiTbtPolicyBoardInitDonePpiGuid ## CONSUMES + +[Depex] + gEfiPeiMemoryDiscoveredPpiGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Sm= m/TbtSmm.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/= Smm/TbtSmm.inf new file mode 100644 index 0000000000..3d4e6ceea0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm= m.inf @@ -0,0 +1,80 @@ +## @file +# Component information file for the ThunderBolt Smm module. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D TbtSmm + FILE_GUID =3D 5BDCD685-D80A-42E6-9867-A84CCE7F828E + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_SMM_DRIVER + PI_SPECIFICATION_VERSION =3D 1.10 + ENTRY_POINT =3D TbtSmmEntryPoint + +[LibraryClasses] + UefiDriverEntryPoint + BaseLib + BaseMemoryLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + IoLib + PciExpressLib + HobLib + ReportStatusCodeLib + PciSegmentLib + UefiLib + SmmServicesTableLib + GpioLib + PchInfoLib + TbtCommonLib + PchPmcLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + +[Pcd] +# gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + +[FixedPcd] + gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES + +[Sources] + TbtSmiHandler.h + TbtSmiHandler.c + TbtSmm.c + +[Protocols] + gTbtNvsAreaProtocolGuid ## CONSUMES + gEfiSmmSxDispatch2ProtocolGuid ## CONSUMES + gEfiSmmSwDispatch2ProtocolGuid ## CONSUMES + gEfiSmmVariableProtocolGuid ## CONSUMES + gDxeTbtPolicyProtocolGuid + +[Guids] + gTbtInfoHobGuid ## CONSUMES + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES + +[Depex] + gEfiSmmBase2ProtocolGuid AND + gEfiSmmSxDispatch2ProtocolGuid AND + gEfiSmmSwDispatch2ProtocolGuid AND + gEfiGlobalNvsAreaProtocolGuid AND + gEfiVariableWriteArchProtocolGuid AND + gEfiVariableArchProtocolGuid AND + gEfiSmmVariableProtocolGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Po= licyInitDxe.inf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitD= xe/PolicyInitDxe.inf new file mode 100644 index 0000000000..65c531a532 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.inf @@ -0,0 +1,176 @@ +## @file +# Module Information file for the PolicyInit DXE driver. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PolicyInitDxe + FILE_GUID =3D 490D0119-4448-440D-8F5C-F58FB53EE057 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + ENTRY_POINT =3D PolicyInitDxeEntryPoint + +[LibraryClasses] + BaseLib + BaseMemoryLib + CpuPlatformLib + DebugLib + DxeServicesTableLib + IoLib + MemoryAllocationLib + DxeSaPolicyLib + DxePchPolicyLib + PcdLib + DxePolicyBoardConfigLib + DxePolicyUpdateLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiLib + UefiRuntimeServicesTableLib + ConfigBlockLib + DevicePathLib + DxeTbtPolicyLib + PchPcieRpLib + +[Packages] + MdePkg/MdePkg.dec + CoffeelakeSiliconPkg/SiPkg.dec + WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ##= CONSUMES + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase ##= CONSUMES + gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize ##= CONSUMES + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable + gBoardModuleTokenSpaceGuid.PcdPlatformFlavor + gBoardModuleTokenSpaceGuid.PcdPlatformType + gBoardModuleTokenSpaceGuid.PcdEcPresent + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid + gBoardModuleTokenSpaceGuid.PcdTbtEnable + gSiPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable ##= CONSUMES + gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable ##= CONSUMES + gSiPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication ##= CONSUMES + gSiPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication ##= CONSUMES + gSiPkgTokenSpaceGuid.PcdCpuSmmUseSmmEnableIndication ##= CONSUMES + + gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeUpSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonVolumeDownSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonHomeButtonSupport + gBoardModuleTokenSpaceGuid.PcdVirtualButtonRotationLockSupport + gBoardModuleTokenSpaceGuid.PcdSlateModeSwitchSupport + gBoardModuleTokenSpaceGuid.PcdAcDcAutoSwitchSupport + gBoardModuleTokenSpaceGuid.PcdPmPowerButtonGpioPin + gBoardModuleTokenSpaceGuid.PcdAcpiEnableAllButtonSupport + gBoardModuleTokenSpaceGuid.PcdAcpiHidDriverButtonSupport + gBoardModuleTokenSpaceGuid.PcdTsOnDimmTemperature + gBoardModuleTokenSpaceGuid.PcdBatteryPresent + + gBoardModuleTokenSpaceGuid.PcdUsbTypeCSupport + gBoardModuleTokenSpaceGuid.PcdUsbTypeCEcLess + gBoardModuleTokenSpaceGuid.PcdEcHotKeyF3Support + gBoardModuleTokenSpaceGuid.PcdEcHotKeyF4Support + gBoardModuleTokenSpaceGuid.PcdEcHotKeyF5Support + gBoardModuleTokenSpaceGuid.PcdEcHotKeyF6Support + gBoardModuleTokenSpaceGuid.PcdEcHotKeyF7Support + gBoardModuleTokenSpaceGuid.PcdEcHotKeyF8Support + + # + # PSS Board Configuration. + # + gBoardModuleTokenSpaceGuid.PcdPssReadSN + gBoardModuleTokenSpaceGuid.PcdPssI2cBusNumber + gBoardModuleTokenSpaceGuid.PcdPssI2cSlaveAddress + + gBoardModuleTokenSpaceGuid.PcdXhciAcpiTableSignature + gBoardModuleTokenSpaceGuid.PcdPreferredPmProfile + gBoardModuleTokenSpaceGuid.PcdFingerPrintSleepGpio + gBoardModuleTokenSpaceGuid.PcdFingerPrintIrqGpio + gBoardModuleTokenSpaceGuid.PcdGnssResetGpio + gBoardModuleTokenSpaceGuid.PcdTouchpadIrqGpio + gBoardModuleTokenSpaceGuid.PcdTouchpanelIrqGpio + + gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecIrqGpio + gBoardModuleTokenSpaceGuid.PcdHdaI2sCodecI2cBusNumber + gBoardModuleTokenSpaceGuid.PcdBleUsbPortNumber + gBoardModuleTokenSpaceGuid.PcdEcSmiGpio + gBoardModuleTokenSpaceGuid.PcdEcLowPowerExitGpio + gBoardModuleTokenSpaceGuid.PcdHidI2cIntPad + gBoardModuleTokenSpaceGuid.PcdDetectPs2KbOnCmdAck + gBoardModuleTokenSpaceGuid.PcdSpdAddressOverride + gBoardModuleTokenSpaceGuid.PcdDDISelection + gBoardModuleTokenSpaceGuid.PcdGfxCrbDetectGpio + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1 + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort1Pch + gBoardModuleTokenSpaceGuid.PcdUsbCPort1Proterties + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2 + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort2Pch + gBoardModuleTokenSpaceGuid.PcdUsbCPort2Proterties + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3 + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort3Pch + gBoardModuleTokenSpaceGuid.PcdUsbCPort3Proterties + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4 + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort4Pch + gBoardModuleTokenSpaceGuid.PcdUsbCPort4Proterties + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5 + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort5Pch + gBoardModuleTokenSpaceGuid.PcdUsbCPort5Proterties + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6 + gBoardModuleTokenSpaceGuid.PcdUsbTypeCPort6Pch + gBoardModuleTokenSpaceGuid.PcdUsbCPort6Proterties + gBoardModuleTokenSpaceGuid.PcdMipiCam0LinkUsed + gBoardModuleTokenSpaceGuid.PcdMipiCam1LinkUsed + gBoardModuleTokenSpaceGuid.PcdMipiCam2LinkUsed + gBoardModuleTokenSpaceGuid.PcdMipiCam3LinkUsed + gPlatformModuleTokenSpaceGuid.PcdH8S2113Present + gPlatformModuleTokenSpaceGuid.PcdNat87393Present + gPlatformModuleTokenSpaceGuid.PcdNct677FPresent + gBoardModuleTokenSpaceGuid.PcdConvertableDockSupport + gBoardModuleTokenSpaceGuid.PcdSmcRuntimeSciPin + gBoardModuleTokenSpaceGuid.PcdRealBattery1Control + gBoardModuleTokenSpaceGuid.PcdRealBattery2Control + gBoardModuleTokenSpaceGuid.PcdDimmPopulationError + gBoardModuleTokenSpaceGuid.PcdBtIrqGpio + gBoardModuleTokenSpaceGuid.PcdBtRfKillGpio + gBoardModuleTokenSpaceGuid.PcdWhlErbRtd3TableEnable + gBoardModuleTokenSpaceGuid.PcdTypeCPortsSupported + gBoardModuleTokenSpaceGuid.PcdMipiCamSensor + gBoardModuleTokenSpaceGuid.PcdH8S2113SIO + gBoardModuleTokenSpaceGuid.PcdNCT6776FCOM + gBoardModuleTokenSpaceGuid.PcdNCT6776FSIO + gBoardModuleTokenSpaceGuid.PcdNCT6776FHWMON + gBoardModuleTokenSpaceGuid.PcdGpioTier2WakeEnable + gBoardModuleTokenSpaceGuid.PcdFunctionGopVbtSpecificUpdate + +[Sources] + PolicyInitDxe.c + SaPolicyInitDxe.c + SiliconPolicyInitDxe.c + GopPolicyInitDxe.c + PchPolicyInitDxe.c + CpuPolicyInitDxe.c + BoardInitLib.c + +[Protocols] + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES + gDxeMePolicyGuid ## PRODUCES + gSaPolicyProtocolGuid ## CONSUMES + gPchPolicyProtocolGuid ## CONSUMES + gDxeSiPolicyProtocolGuid ## PRODUCES + gGopPolicyProtocolGuid ## PRODUCES + gDxeCpuPolicyProtocolGuid ## PRODUCES + +[Guids] + gCpuSmmGuid ## CONSUMES + gSiMemoryInfoDataGuid + +[Depex] + gEfiVariableArchProtocolGuid + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/Pci= HotPlug.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/PciH= otPlug.h new file mode 100644 index 0000000000..f57bfb8c26 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug= .h @@ -0,0 +1,130 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCI_HOT_PLUG_H_ +#define _PCI_HOT_PLUG_H_ + +// +// External include files do NOT need to be explicitly specified in real E= DKII +// environment +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('G', 'U', 'L',= 'P') + +#define ACPI \ + { \ + { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH))= , (UINT8) \ + ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (0x0A03), 0 \ + } + +#define PCI(device, function) \ + { \ + { HARDWARE_DEVICE_PATH, HW_PCI_DP, { (UINT8) (sizeof (PCI_DEVICE_PATH)= ), (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) } }, \ + (UINTN) function, (UINTN) device \ + } + +#define END \ + { \ + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PAT= H_LENGTH, 0 } \ + } + +#define LPC(eisaid, function) \ + { \ + { ACPI_DEVICE_PATH, ACPI_DP, { (UINT8) (sizeof (ACPI_HID_DEVICE_PATH))= , (UINT8) \ + ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) } }, EISA_PNP_ID (eisaid), fu= nction \ + } + +typedef struct PCIE_HOT_PLUG_DEVICE_PATH { + ACPI_HID_DEVICE_PATH PciRootBridgeNode; + PCI_DEVICE_PATH PciRootPortNode; + EFI_DEVICE_PATH_PROTOCOL EndDeviceNode; +} PCIE_HOT_PLUG_DEVICE_PATH; + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; // Handle for protocol this driv= er installs on + EFI_PCI_HOT_PLUG_INIT_PROTOCOL HotPlugInitProtocol; +} PCI_HOT_PLUG_INSTANCE; + +/** + This procedure returns a list of Root Hot Plug controllers that require + initialization during boot process + + @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLU= G_INIT protocol. + @param[out] HpcCount The number of Root HPCs returned. + @param[out] HpcList The list of Root HPCs. HpcCount defines the number= of elements in this list. + + @retval EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +GetRootHpcList ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *PhpcCount, + OUT EFI_HPC_LOCATION **PhpcList + ); + +/** + This procedure Initializes one Root Hot Plug Controller + This process may casue initialization of its subordinate buses + + @param[in] This The pointer to the instance of the EFI_PCI_H= OT_PLUG_INIT protocol. + @param[in] HpcDevicePath The Device Path to the HPC that is being ini= tialized. + @param[in] HpcPciAddress The address of the Hot Plug Controller funct= ion on the PCI bus. + @param[in] Event The event that should be signaled when the H= ot Plug Controller initialization is complete. Set to NULL if the caller wa= nts to wait until the entire initialization process is complete. The event = must be of the type EFI_EVT_SIGNAL. + @param[out] HpcState The state of the Hot Plug Controller hardwar= e. The type EFI_Hpc_STATE is defined in section 3.1. + + @retval EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +InitializeRootHpc ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath, + IN UINT64 PhpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *PhpcState + ); + +/** + Returns the resource padding required by the PCI bus that is controlled = by the specified Hot Plug Controller. + + @param[in] This The pointer to the instance of the EFI_PCI_HO= T_PLUG_INIT protocol. initialized. + @param[in] HpcDevicePath The Device Path to the Hot Plug Controller. + @param[in] HpcPciAddress The address of the Hot Plug Controller functi= on on the PCI bus. + @param[out] HpcState The state of the Hot Plug Controller hardware= . The type EFI_HPC_STATE is defined in section 3.1. + @param[out] Padding This is the amount of resource padding requir= ed by the PCI bus under the control of the specified Hpc. Since the caller = does not know the size of this buffer, this buffer is allocated by the call= ee and freed by the caller. + @param[out] Attribute Describes how padding is accounted for. + + @retval EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +GetResourcePadding ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *PhpcDevicePath, + IN UINT64 PhpcPciAddress, + OUT EFI_HPC_STATE *PhpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Sm= m/TbtSmiHandler.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Tbt= Init/Smm/TbtSmiHandler.h new file mode 100644 index 0000000000..b91b0f14bd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm= iHandler.h @@ -0,0 +1,180 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _TBT_SMI_HANDLER_H_ +#define _TBT_SMI_HANDLER_H_ + +#include +#include +#include + +#ifdef PROGRESS_CODE +#undef PROGRESS_CODE +#endif + +#define MAX_TBT_DEPTH 6 + +#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRID= GE_P2P)) + +#define BAR_ALIGN(v, a) ((((v) - 1) | (a)) + 1) + +#define CMD_BUS_MASTER BIT2 +#define CMD_BM_IO (CMD_BUS_MASTER | BIT0) +#define CMD_BM_MEM (CMD_BUS_MASTER | BIT1) +#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0) + +#define DEF_CACHE_LINE_SIZE 0x20 +#define DEF_RES_IO_PER_DEV 4 +#define DEF_RES_MEM_PER_DEV 32 +#define DEF_RES_PMEM_PER_DEV 32 + +#define DOCK_BUSSES 8 + +#define DISBL_IO_REG1C 0x01F1 +#define DISBL_MEM32_REG20 0x0000FFF0 +#define DISBL_PMEM_REG24 0x0001FFF1 + +#define count(x) (sizeof (x) / sizeof ((x)[0])) + +#define PCIE_CAP_ID_SSID_SSVID 0x0D +#define INVALID_PCI_DEVICE 0xFFFFFFFF +#define PCI_TBT_VESC_REG2 0x510 + +typedef struct _PortInfo { + UINT8 IoBase; + UINT8 IoLimit; + UINT16 MemBase; + UINT16 MemLimit; + UINT64 PMemBase64; + UINT64 PMemLimit64; + UINT8 BusNumLimit; + UINT8 ConfedEP; +} PORT_INFO; + +typedef struct _MEM_REGS { + UINT32 Base; + UINT32 Limit; +} MEM_REGS; + +typedef struct _PMEM_REGS { + UINT64 Base64; + UINT64 Limit64; +} PMEM_REGS; + +typedef struct _IO_REGS { + UINT16 Base; + UINT16 Limit; +} IO_REGS; + +typedef struct _BRDG_RES_CONFIG { + UINT8 Cmd; + UINT8 Cls; + UINT8 IoBase; + UINT8 IoLimit; + UINT16 MemBase; + UINT16 MemLimit; + UINT64 PMemBase64; + UINT64 PMemLimit64; +} BRDG_RES_CONFIG; + +typedef struct _BRDG_CONFIG { + DEV_ID DevId; + UINT8 PBus; + UINT8 SBus; + UINT8 SubBus; + BOOLEAN IsDSBridge; + BRDG_RES_CONFIG Res; +} BRDG_CONFIG; + +enum { + HR_US_PORT, + HR_DS_PORT0, + HR_DS_PORT3, + HR_DS_PORT4, + HR_DS_PORT5, + HR_DS_PORT6, + MAX_CFG_PORTS +}; + +enum { + HR_DS_PORT1 =3D HR_DS_PORT3 +}; + +// +// Alpine Ridge +// +enum { + AR_DS_PORT1 =3D HR_DS_PORT3, + AR_DS_PORT2, + AR_DS_PORT3, + AR_DS_PORT4 +}; + +typedef struct _HR_CONFIG { + UINT16 DeviceId; + UINT8 HRBus; + UINT8 MinDSNumber; + UINT8 MaxDSNumber; + UINT8 BridgeLoops; +} HR_CONFIG; + +STATIC const BRDG_RES_CONFIG NOT_IN_USE_BRIDGE =3D { + CMD_BUS_MASTER, + 0, + DISBL_IO_REG1C & 0xFF, + DISBL_IO_REG1C >> 8, + DISBL_MEM32_REG20 & 0xFFFF, + DISBL_MEM32_REG20 >> 16, + DISBL_PMEM_REG24 & 0xFFFF, + DISBL_PMEM_REG24 >> 16 +}; + +typedef union _BRDG_CIO_MAP_REG { + UINT32 AB_REG; + struct { + UINT32 NumOfDSPorts : 5; + UINT32 CioPortMap : 27; + } Bits; +} BRDG_CIO_MAP_REG; + +// +// Functions +// +VOID +ThunderboltCallback ( + IN UINT8 Type + ); + +VOID +TbtDisablePCIDevicesAndBridges ( + IN UINT8 Type + ); + +VOID +EndOfThunderboltCallback( + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction +); + +VOID +ConfigureTbtAspm( + IN UINT8 Type, + IN UINT16 Aspm +); + +UINT8 +PcieFindCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 CapId + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Bo= ardInitLib.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/= BoardInitLib.h new file mode 100644 index 0000000000..ac13acc27d --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInit= Lib.h @@ -0,0 +1,32 @@ +/** @file + Header file for board Init function for DXE Init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _DXE_BOARD_INIT_LIB_H_ +#define _DXE_BOARD_INIT_LIB_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +BoardConfigInit ( + VOID + ); + +#endif // _DXE_BOARD_INIT_LIB_H_ + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Cp= uPolicyInitDxe.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInit= Dxe/CpuPolicyInitDxe.h new file mode 100644 index 0000000000..5d0e2777d8 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicy= InitDxe.h @@ -0,0 +1,38 @@ +/** @file + Header file for the SiliconPolicyInitDxe Driver. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _CPU_POLICY_INIT_DXE_H_ +#define _CPU_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include + +#include +#include + + +/** + Initialize Intel CPU DXE Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this drive= r. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +CpuPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Go= pPolicyInitDxe.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInit= Dxe/GopPolicyInitDxe.h new file mode 100644 index 0000000000..ff975efae0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicy= InitDxe.h @@ -0,0 +1,41 @@ +/** @file +Header file for the GopPolicyInitDxe Driver. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _GOP_POLICY_INIT_DXE_H_ +#define _GOP_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** +Initialize GOP DXE Policy + +@param[in] ImageHandle Image handle of this driver. + +@retval EFI_SUCCESS Initialization complete. +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +GopPolicyInitDxe( + IN EFI_HANDLE ImageHandle + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Pc= hPolicyInitDxe.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInit= Dxe/PchPolicyInitDxe.h new file mode 100644 index 0000000000..1055fed7c8 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicy= InitDxe.h @@ -0,0 +1,52 @@ +/** @file + Header file for the PchPolicyInitDxe Driver. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PCH_POLICY_INIT_DXE_H_ +#define _PCH_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include + +extern UINT8 mFirmwareConfiguration; + +/** + PCH DXE Policy Driver Entry Point \n + - Introduction \n + Pch DXE drivers behavior can be controlled by platform policy without = modifying reference code directly. + Platform policy Protocol is initialized with default settings in this = funciton. + This policy Protocol has to be initialized prior to PCH initialization= DXE drivers execution. + + - @pre + - Runtime variable service should be ready if policy initialization re= quired. + + - @result + PCH_POLICY_PROTOCOL will be installed successfully and ready for Pch r= eference code use. + + - Porting Recommendations \n + Policy should be initialized basing on platform design or user selecti= on (like BIOS Setup Menu) + + @param[in] ImageHandle - Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +PchPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Po= licyInitDxe.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe= /PolicyInitDxe.h new file mode 100644 index 0000000000..d2aac9823e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.h @@ -0,0 +1,45 @@ +/** @file + Header file for the PolicyInitDxe Driver. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _POLICY_INIT_DXE_H_ +#define _POLICY_INIT_DXE_H_ + + +#include +#include +#include +#include + +#include "SaPolicyInitDxe.h" +#include "PchPolicyInitDxe.h" +#include "SiliconPolicyInitDxe.h" +#include "GopPolicyInitDxe.h" +#include "CpuPolicyInitDxe.h" + +#include +/** + Initialize DXE Platform Policy + + @param[in] ImageHandle - Image handle of this driver. + @param[in] SystemTable - Global system service table. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driv= er. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ + +EFI_STATUS +EFIAPI +PolicyInitDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Sa= PolicyInitDxe.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitD= xe/SaPolicyInitDxe.h new file mode 100644 index 0000000000..0f86711e6a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyI= nitDxe.h @@ -0,0 +1,56 @@ +/** @file + Header file for the SaPolicyInitDxe Driver. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SA_POLICY_INIT_DXE_H_ +#define _SA_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +extern UINT8 mFirmwareConfiguration; + +/** + SA DXE Policy Driver Entry Point \n + - Introduction \n + System Agent DXE drivers behavior can be controlled by platform policy= without modifying reference code directly. + Platform policy Protocol is initialized with default settings in this = funciton. + This policy Protocol has to be initialized prior to System Agent initi= alization DXE drivers execution. + + - @pre + - Runtime variable service should be ready if policy initialization re= quired. + + - @result + SA_POLICY_PROTOCOL will be installed successfully and ready for System= Agent reference code use. + + - Porting Recommendations \n + Policy should be initialized basing on platform design or user selecti= on (like BIOS Setup Menu) + + @param[in] ImageHandle - Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SaPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Si= liconPolicyInitDxe.h b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Policy= InitDxe/SiliconPolicyInitDxe.h new file mode 100644 index 0000000000..a2c5f548fa --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPo= licyInitDxe.h @@ -0,0 +1,37 @@ +/** @file + Header file for the SiliconPolicyInitDxe Driver. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SILICON_POLICY_INIT_DXE_H_ +#define _SILICON_POLICY_INIT_DXE_H_ + +#include +#include +#include +#include +#include + +#include + +/** + Initilize Intel CPU DXE Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this dr= iver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SiliconPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ); + +#endif + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiG= nvsInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGn= vsInit.c new file mode 100644 index 0000000000..1ff129c307 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/AcpiGnvsInit= .c @@ -0,0 +1,96 @@ +/** @file + Acpi Gnvs Init Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/** +@brief + Global NVS initialize. + + @param[in] GlobalNvs - Pointer of Global NVS area + + @retval EFI_SUCCESS - Allocate Global NVS completed. + @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS. +**/ +EFI_STATUS +EFIAPI +AcpiGnvsInit ( + IN OUT VOID **GlobalNvs + ) +{ + UINTN Pages; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + EFI_GLOBAL_NVS_AREA_PROTOCOL *GNVS; + EFI_MP_SERVICES_PROTOCOL *MpService; + UINTN NumberOfCPUs; + UINTN NumberOfEnabledCPUs; + + Pages =3D EFI_SIZE_TO_PAGES (sizeof (EFI_GLOBAL_NVS_AREA)); + Address =3D 0xffffffff; // allocate address below 4G. + + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // + // Locate the MP services protocol + // Find the MP Protocol. This is an MP platform, so MP protocol must be = there. + // + Status =3D gBS->LocateProtocol ( + &gEfiMpServiceProtocolGuid, + NULL, + (VOID **) &MpService + ); + ASSERT_EFI_ERROR (Status); + + // + // Determine the number of processors + // + MpService->GetNumberOfProcessors ( + MpService, + &NumberOfCPUs, + &NumberOfEnabledCPUs + ); + + *GlobalNvs =3D (VOID *) (UINTN) Address; + SetMem (*GlobalNvs, sizeof (EFI_GLOBAL_NVS_AREA), 0); + + // + // GNVS default value init here... + // + GNVS =3D (EFI_GLOBAL_NVS_AREA_PROTOCOL *) &Address; + + GNVS->Area->ThreadCount =3D (UINT8)NumberOfEnabledCPUs; + + // + // Miscellaneous + // + GNVS->Area->PL1LimitCS =3D 0; + GNVS->Area->PL1LimitCSValue =3D 4500; + + return EFI_SUCCESS; +} + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Board= AcpiDxe.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardA= cpiDxe.c new file mode 100644 index 0000000000..cb5f328a39 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/BoardAcpiDxe= .c @@ -0,0 +1,290 @@ +/** @file + ACPI Platform Driver + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_GLOBAL_NVS_AREA_PROTOCOL mG= lobalNvsArea; + +/** +@brief + Global NVS initialize. + + @param[in] GlobalNvs - Pointer of Global NVS area + + @retval EFI_SUCCESS - Allocate Global NVS completed. + @retval EFI_OUT_OF_RESOURCES - Failed to allocate required page for GNVS. +**/ +EFI_STATUS +EFIAPI +AcpiGnvsInit ( + IN OUT VOID **GlobalNvs + ); + +// +// Function implementations +// + +/** + Locate the first instance of a protocol. If the protocol requested is an + FV protocol, then it will return the first FV that contains the ACPI tab= le + storage file. + + @param[in] Protocol The protocol to find. + @param[in] Instance Return pointer to the first instance of th= e protocol. + @param[in] Type TRUE if the desired protocol is a FV proto= col. + + @retval EFI_SUCCESS The function completed successfully. + @retval EFI_NOT_FOUND The protocol could not be located. + @retval EFI_OUT_OF_RESOURCES There are not enough resources to find the= protocol. +**/ +EFI_STATUS +LocateSupportProtocol ( + IN EFI_GUID *Protocol, + IN EFI_GUID *gEfiAcpiMultiTableStorageGuid, + OUT VOID **Instance, + IN BOOLEAN Type + ) +{ + EFI_STATUS Status; + EFI_HANDLE *HandleBuffer; + UINTN NumberOfHandles; + EFI_FV_FILETYPE FileType; + UINT32 FvStatus; + EFI_FV_FILE_ATTRIBUTES Attributes; + UINTN Size; + UINTN Index; + + // + // Locate protocol. + // + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + Protocol, + NULL, + &NumberOfHandles, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + // + // Defined errors at this time are not found and out of resources. + // + return Status; + } + + // + // Looking for FV with ACPI storage file + // + for (Index =3D 0; Index < NumberOfHandles; Index++) { + + // + // Get the protocol on this handle + // This should not fail because of LocateHandleBuffer + // + Status =3D gBS->HandleProtocol ( + HandleBuffer[Index], + Protocol, + Instance + ); + ASSERT_EFI_ERROR (Status); + + if (!Type) { + + // + // Not looking for the FV protocol, so find the first instance of the + // protocol. There should not be any errors because our handle buff= er + // should always contain at least one or LocateHandleBuffer would ha= ve + // returned not found. + // + break; + } + // + // See if it has the ACPI storage file + // + Size =3D 0; + FvStatus =3D 0; + Status =3D ((EFI_FIRMWARE_VOLUME2_PROTOCOL *) (*Instance))->ReadFile ( + *Instance, + gEfiAcpiMult= iTableStorageGuid, + NULL, + &Size, + &FileType, + &Attributes, + &FvStatus + ); + // + // If we found it, then we are done + // + if (Status =3D=3D EFI_SUCCESS) { + break; + } + } + + // + // Our exit status is determined by the success of the previous operatio= ns + // If the protocol was found, Instance already points to it. + // + // + // Free any allocated buffers + // + FreePool (HandleBuffer); + + return Status; +} + +EFI_STATUS +PublishAcpiTablesFromFv ( + IN EFI_GUID *gEfiAcpiMultiTableStorageGuid + ) +{ + EFI_STATUS Status; + EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol; + EFI_ACPI_COMMON_HEADER *CurrentTable; + UINT32 FvStatus; + UINTN Size; + UINTN TableHandle; + INTN Instance; + EFI_ACPI_TABLE_PROTOCOL *AcpiTable; + + Instance =3D 0; + TableHandle =3D 0; + CurrentTable =3D NULL; + FwVol =3D NULL; + + // + // Find the AcpiSupport protocol + // + Status =3D LocateSupportProtocol ( + &gEfiAcpiTableProtocolGuid, + gEfiAcpiMultiTableStorageGuid, + (VOID **) &AcpiTable, + FALSE + ); + ASSERT_EFI_ERROR (Status); + + // + // Locate the firmware volume protocol + // + Status =3D LocateSupportProtocol ( + &gEfiFirmwareVolume2ProtocolGuid, + gEfiAcpiMultiTableStorageGuid, + (VOID **) &FwVol, + TRUE + ); + + // + // Read tables from the storage file. + // + + while (Status =3D=3D EFI_SUCCESS) { + Status =3D FwVol->ReadSection ( + FwVol, + gEfiAcpiMultiTableStorageGuid, + EFI_SECTION_RAW, + Instance, + (VOID **) &CurrentTable, + &Size, + &FvStatus + ); + + if (!EFI_ERROR (Status)) { + // + // Add the table + // + TableHandle =3D 0; + + Status =3D AcpiTable->InstallAcpiTable ( + AcpiTable, + CurrentTable, + CurrentTable->Length, + &TableHandle + ); + + + ASSERT_EFI_ERROR (Status); + + // + // Increment the instance + // + Instance++; + CurrentTable =3D NULL; + } + } + + // + // Finished + // + return EFI_SUCCESS; +} + +/** + ACPI Platform driver installation function. + + @param[in] ImageHandle Handle for this drivers loaded image protocol. + @param[in] SystemTable EFI system table. + + @retval EFI_SUCCESS The driver installed without error. + @retval EFI_ABORTED The driver encountered an error and could not= complete installation of + the ACPI tables. + +**/ +EFI_STATUS +EFIAPI +InstallAcpiBoard ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + AcpiGnvsInit((VOID **) &mGlobalNvsArea.Area); + + // + // This PCD set must be done before PublishAcpiTablesFromFv. + // The PCD data will be used there. + // + PcdSet64S (PcdAcpiGnvsAddress, (UINT64)(UINTN)mGlobalNvsArea.Area); + + // + // Platform ACPI Tables + // + PublishAcpiTablesFromFv (&gEfiCallerIdGuid); + + // + // This protocol publish must be done after PublishAcpiTablesFromFv. + // The NVS data is be updated there. + // + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEfiGlobalNvsAreaProtocolGuid, + &mGlobalNvsArea, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/Pci= HotPlug.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/PciH= otPlug.c new file mode 100644 index 0000000000..2b36475c53 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/PciHotPlug/PciHotPlug= .c @@ -0,0 +1,353 @@ +/** @file + Pci Hotplug Driver : This file will perform specific PCI-EXPRESS + Devics resource configuration. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// Statements that include other files +// +#include "PciHotPlug.h" +#include +#include +#include +#include + +#define PCIE_NUM (20) +#define PEG_NUM (3) +#define PADDING_BUS (1) +#define PADDING_NONPREFETCH_MEM (1) +#define PADDING_PREFETCH_MEM (1) +#define PADDING_IO (1) +#define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM + PADDING_PREFE= TCH_MEM + PADDING_IO) + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION mPcieLocation[PCIE= _NUM + PEG_NUM]; + +GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount =3D 0; + +GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH mHotplugPcieDevice= PathTemplate =3D { + ACPI, + PCI(0xFF, 0xFF), // Dummy Device no & Function no + END +}; + +/** + Entry point for the driver. + + This routine reads the PlatformType GPI on FWH and produces a protocol + to be consumed by the chipset driver to effect those settings. + + @param[in] ImageHandle An image handle. + @param[in] SystemTable A pointer to the system table. + + @retval EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +PciHotPlug ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + PCI_HOT_PLUG_INSTANCE *PciHotPlug; + UINTN Index; + UINTN RpDev; + UINTN RpFunc; + PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath; + UINT32 PcieRootPortHpeData =3D 0; + + DEBUG ((DEBUG_INFO, "PciHotPlug Entry\n")); + + PcieRootPortHpeData =3D PcdGet32 (PcdPchPcieRootPortHpe); + // + // PCH Rootports Hotplug device path creation + // + for (Index =3D 0; Index < PCIE_NUM; Index++) { + if (((PcieRootPortHpeData >> Index) & BIT0) =3D=3D BIT0) { // Check th= e Rootport no's hotplug is set + Status =3D GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the a= ctual device/function no corresponding to the Rootport no provided + ASSERT_EFI_ERROR (Status); + + HotplugPcieDevicePath =3D NULL; + HotplugPcieDevicePath =3D AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE= _PATH)); + ASSERT (HotplugPcieDevicePath !=3D NULL); + if (HotplugPcieDevicePath =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, siz= eof (PCIE_HOT_PLUG_DEVICE_PATH)); + HotplugPcieDevicePath->PciRootPortNode.Device =3D (UINT8) RpDev; // = Update real Device no + HotplugPcieDevicePath->PciRootPortNode.Function =3D (UINT8) RpFunc; = // Update real Function no + + mPcieLocation[mHpcCount].HpcDevicePath =3D (EFI_DEVICE_PATH_PROTOCOL= *)HotplugPcieDevicePath; + mPcieLocation[mHpcCount].HpbDevicePath =3D (EFI_DEVICE_PATH_PROTOCOL= *)HotplugPcieDevicePath; + mHpcCount++; + + DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00, Device = 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount= , RpDev, RpFunc)); + } + } + + + PciHotPlug =3D AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE)); + ASSERT (PciHotPlug !=3D NULL); + if (PciHotPlug =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Initialize driver private data. + // + ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE)); + + PciHotPlug->Signature =3D PCI_HOT_PLUG_DRI= VER_PRIVATE_SIGNATURE; + PciHotPlug->HotPlugInitProtocol.GetRootHpcList =3D GetRootHpcList; + PciHotPlug->HotPlugInitProtocol.InitializeRootHpc =3D InitializeRootHp= c; + PciHotPlug->HotPlugInitProtocol.GetResourcePadding =3D GetResourcePaddi= ng; + + Status =3D gBS->InstallProtocolInterface ( + &PciHotPlug->Handle, + &gEfiPciHotPlugInitProtocolGuid, + EFI_NATIVE_INTERFACE, + &PciHotPlug->HotPlugInitProtocol + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + + +/** + This procedure returns a list of Root Hot Plug controllers that require + initialization during boot process + + @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLU= G_INIT protocol. + @param[out] HpcCount The number of Root HPCs returned. + @param[out] HpcList The list of Root HPCs. HpcCount defines the number= of elements in this list. + + @retval EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +GetRootHpcList ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + OUT UINTN *HpcCount, + OUT EFI_HPC_LOCATION **HpcList + ) +{ + *HpcCount =3D mHpcCount; + *HpcList =3D mPcieLocation; + + return EFI_SUCCESS; +} + + +/** + This procedure Initializes one Root Hot Plug Controller + This process may casue initialization of its subordinate buses + + @param[in] This The pointer to the instance of the EFI_PCI_H= OT_PLUG_INIT protocol. + @param[in] HpcDevicePath The Device Path to the HPC that is being ini= tialized. + @param[in] HpcPciAddress The address of the Hot Plug Controller funct= ion on the PCI bus. + @param[in] Event The event that should be signaled when the H= ot Plug Controller initialization is complete. Set to NULL if the caller wa= nts to wait until the entire initialization process is complete. The event = must be of the type EFI_EVT_SIGNAL. + @param[out] HpcState The state of the Hot Plug Controller hardwar= e. The type EFI_Hpc_STATE is defined in section 3.1. + + @retval EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +InitializeRootHpc ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + IN EFI_EVENT Event, OPTIONAL + OUT EFI_HPC_STATE *HpcState + ) +{ + if (Event) { + gBS->SignalEvent (Event); + } + + *HpcState =3D EFI_HPC_STATE_INITIALIZED; + + return EFI_SUCCESS; +} + + +/** + Returns the resource padding required by the PCI bus that is controlled = by the specified Hot Plug Controller. + + @param[in] This The pointer to the instance of the EFI_PCI_HO= T_PLUG_INIT protocol. initialized. + @param[in] HpcDevicePath The Device Path to the Hot Plug Controller. + @param[in] HpcPciAddress The address of the Hot Plug Controller functi= on on the PCI bus. + @param[out] HpcState The state of the Hot Plug Controller hardware= . The type EFI_HPC_STATE is defined in section 3.1. + @param[out] Padding This is the amount of resource padding requir= ed by the PCI bus under the control of the specified Hpc. Since the caller = does not know the size of this buffer, this buffer is allocated by the call= ee and freed by the caller. + @param[out] Attribute Describes how padding is accounted for. + + @retval EFI_SUCCESS. +**/ +EFI_STATUS +EFIAPI +GetResourcePadding ( + IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This, + IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath, + IN UINT64 HpcPciAddress, + OUT EFI_HPC_STATE *HpcState, + OUT VOID **Padding, + OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes + ) +{ + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource; + EFI_STATUS Status; + UINT8 RsvdExtraBusNum =3D 0; + UINT16 RsvdPcieMegaMem =3D 10; + UINT8 PcieMemAddrRngMax =3D 0; + UINT16 RsvdPciePMegaMem =3D 10; + UINT8 PciePMemAddrRngMax =3D 0; + UINT8 RsvdTbtExtraBusNum =3D 0; + UINT16 RsvdTbtPcieMegaMem =3D 10; + UINT8 TbtPcieMemAddrRngMax =3D 0; + UINT16 RsvdTbtPciePMegaMem =3D 10; + UINT8 TbtPciePMemAddrRngMax =3D 0; + UINT8 RsvdPcieKiloIo =3D 4; + BOOLEAN SetResourceforTbt =3D FALSE; + UINTN RpIndex; + UINTN RpDev; + UINTN RpFunc; + +DEBUG ((DEBUG_INFO, "GetResourcePadding : Start \n")); + + PaddingResource =3D AllocatePool (PADDING_NUM * sizeof (EFI_ACPI_ADDRESS= _SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + ASSERT (PaddingResource !=3D NULL); + if (PaddingResource =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + *Padding =3D (VOID *) PaddingResource; + + RpDev =3D (UINTN) ((HpcPciAddress >> 16) & 0xFF); + RpFunc =3D (UINTN) ((HpcPciAddress >> 8) & 0xFF); + + // Get the actual Rootport no corresponding to the device/function no pr= ovided + if (RpDev =3D=3D SA_PEG_DEV_NUM) { + // PEG + RpIndex =3D PCIE_NUM + RpFunc; + DEBUG ((DEBUG_INFO, "GetResourcePadding : PEG Rootport no %02d Bus 0x0= 0, Device 0x%x, Function 0x%x \n", (RpIndex-PCIE_NUM), RpDev, RpFunc)); + } else { + // PCH + Status =3D GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex); + DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH Rootport no %02d Bus 0x0= 0, Device 0x%x, Function 0x%x \n", RpIndex, RpDev, RpFunc)); + } + + GetRootporttoSetResourcesforTbt(RpIndex, &RsvdTbtExtraBusNum, &RsvdTbtPc= ieMegaMem ,&TbtPcieMemAddrRngMax ,&RsvdTbtPciePMegaMem ,&TbtPciePMemAddrRng= Max, &SetResourceforTbt); + if (SetResourceforTbt) { + RsvdExtraBusNum =3D RsvdTbtExtraBusNum; + RsvdPcieMegaMem =3D RsvdTbtPcieMegaMem; + PcieMemAddrRngMax =3D TbtPcieMemAddrRngMax; + RsvdPciePMegaMem =3D RsvdTbtPciePMegaMem; + PciePMemAddrRngMax =3D TbtPciePMemAddrRngMax; + } + + // + // Padding for bus + // + ZeroMem (PaddingResource, PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_D= ESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR)); + *Attributes =3D EfiPaddingPciBus; + + PaddingResource->Desc =3D 0x8A; + PaddingResource->Len =3D 0x2B; + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_BUS; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->SpecificFlag =3D 0; + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrRangeMax =3D 0; + PaddingResource->AddrLen =3D RsvdExtraBusNum; + + // + // Padding for non-prefetchable memory + // + PaddingResource++; + PaddingResource->Desc =3D 0x8A; + PaddingResource->Len =3D 0x2B; + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag =3D 0x0; + if (SetResourceforTbt) { + PaddingResource->AddrSpaceGranularity =3D 32; + } else { + PaddingResource->AddrSpaceGranularity =3D 32; + } + PaddingResource->SpecificFlag =3D 0; + // + // Pad non-prefetchable + // + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrLen =3D RsvdPcieMegaMem * 0x100000; + if (SetResourceforTbt) { + PaddingResource->AddrRangeMax =3D (1 << PcieMemAddrRngMax) - 1; + } else { + PaddingResource->AddrRangeMax =3D 1; + } + + // + // Padding for prefetchable memory + // + PaddingResource++; + PaddingResource->Desc =3D 0x8A; + PaddingResource->Len =3D 0x2B; + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_MEM; + PaddingResource->GenFlag =3D 0x0; + if (SetResourceforTbt) { + PaddingResource->AddrSpaceGranularity =3D 32; + } else { + PaddingResource->AddrSpaceGranularity =3D 32; + } + PaddingResource->SpecificFlag =3D 06; + // + // Padding for prefetchable memory + // + PaddingResource->AddrRangeMin =3D 0; + if (SetResourceforTbt) { + PaddingResource->AddrLen =3D RsvdPciePMegaMem * 0x100000; + } else { + PaddingResource->AddrLen =3D RsvdPcieMegaMem * 0x100000; + } + // + // Pad 16 MB of MEM + // + if (SetResourceforTbt) { + PaddingResource->AddrRangeMax =3D (1 << PciePMemAddrRngMax) - 1; + } else { + PaddingResource->AddrRangeMax =3D 1; + } + // + // Alignment + // + // Padding for I/O + // + PaddingResource++; + PaddingResource->Desc =3D 0x8A; + PaddingResource->Len =3D 0x2B; + PaddingResource->ResType =3D ACPI_ADDRESS_SPACE_TYPE_IO; + PaddingResource->GenFlag =3D 0x0; + PaddingResource->SpecificFlag =3D 0; + PaddingResource->AddrRangeMin =3D 0; + PaddingResource->AddrLen =3D RsvdPcieKiloIo * 0x400; + // + // Pad 4K of IO + // + PaddingResource->AddrRangeMax =3D 1; + // + // Alignment + // + // Terminate the entries. + // + PaddingResource++; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc =3D ACPI_END= _TAG_DESCRIPTOR; + ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum =3D 0x0; + + *HpcState =3D EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED; + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Dx= e/TbtDxe.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Dx= e/TbtDxe.c new file mode 100644 index 0000000000..c670f23320 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Dxe/TbtDx= e.c @@ -0,0 +1,228 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA_PROTOCOL mT= btNvsAreaProtocol; +GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *g= TbtInfoHob =3D NULL; + +/** + TBT NVS Area Initialize + +**/ + +VOID +TbtNvsAreaInit ( + IN VOID **mTbtNvsAreaPtr + ) +{ + UINTN Pages; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol; + DXE_TBT_POLICY_PROTOCOL *DxeTbtConfig; + + DEBUG ((DEBUG_INFO, "TbtNvsAreaInit Start\n")); + Status =3D gBS->LocateProtocol ( + &gDxeTbtPolicyProtocolGuid, + NULL, + (VOID **) &DxeTbtConfig + ); + ASSERT_EFI_ERROR (Status); + + Pages =3D EFI_SIZE_TO_PAGES (sizeof (TBT_NVS_AREA)); + Address =3D 0xffffffff; // allocate address below 4G. + + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); + ASSERT_EFI_ERROR (Status); + + *mTbtNvsAreaPtr =3D (VOID *) (UINTN) Address; + SetMem (*mTbtNvsAreaPtr, sizeof (TBT_NVS_AREA), 0); + + // + // TBTNvsAreaProtocol default value init here + // + TbtNvsAreaProtocol =3D (TBT_NVS_AREA_PROTOCOL *) &Address; + + // + // Initialize default values + // + TbtNvsAreaProtocol->Area->WAKFinished =3D 0; + TbtNvsAreaProtocol->Area->DiscreteTbtSupport =3D ((gTbtInfoHob-> DT= btControllerConfig.DTbtControllerEn =3D=3D 1 ) ? TRUE : FALSE); + TbtNvsAreaProtocol->Area->TbtAcpiRemovalSupport =3D 0; + TbtNvsAreaProtocol->Area->TbtGpioFilter =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.Gpio5Filter; +// TbtNvsAreaProtocol->Area->TrOsup =3D (UINT8) DxeTbtCo= nfig->TbtCommonConfig.TrA0OsupWa; + TbtNvsAreaProtocol->Area->TbtFrcPwrEn =3D gTbtInfoHob->DTbtC= ommonConfig.Gpio3ForcePwr; + TbtNvsAreaProtocol->Area->TbtAspm =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtAspm; +// TbtNvsAreaProtocol->Area->TbtL1SubStates =3D (UINT8) DxeTbtCo= nfig->TbtCommonConfig.TbtL1SubStates; + TbtNvsAreaProtocol->Area->TbtSetClkReq =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtSetClkReq; + TbtNvsAreaProtocol->Area->TbtLtr =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtLtr; +// TbtNvsAreaProtocol->Area->TbtPtm =3D (UINT8) DxeTbtCo= nfig->TbtCommonConfig.TbtPtm; + TbtNvsAreaProtocol->Area->TbtWakeupSupport =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtWakeupSupport; + TbtNvsAreaProtocol->Area->TbtAcDcSwitch =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.TbtAcDcSwitch; + TbtNvsAreaProtocol->Area->Rtd3TbtSupport =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.Rtd3Tbt; // TBT RTD3 Enable. + TbtNvsAreaProtocol->Area->Rtd3TbtOffDelay =3D (UINT16) DxeTbtCon= fig->TbtCommonConfig.Rtd3TbtOffDelay; // TBT RTD3 Off delay in ms. + TbtNvsAreaProtocol->Area->Rtd3TbtClkReq =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.Rtd3TbtClkReq; // TBT RTD3 ClkReq Mask Enable. + TbtNvsAreaProtocol->Area->Rtd3TbtClkReqDelay =3D (UINT16) DxeTbtCon= fig->TbtCommonConfig.Rtd3TbtClkReqDelay; // TBT RTD3 ClkReq mask delay in m= s. + TbtNvsAreaProtocol->Area->TbtWin10Support =3D (UINT8) DxeTbtConf= ig->TbtCommonConfig.Win10Support; // TBT FW Execution Mode + + // + // DTBT Controller 1 + // + TbtNvsAreaProtocol->Area->DTbtControllerEn0 =3D gTbtInfoHob-> DTbt= ControllerConfig.DTbtControllerEn; + TbtNvsAreaProtocol->Area->RootportSelected0 =3D gTbtInfoHob-> DTbt= ControllerConfig.PcieRpNumber; + TbtNvsAreaProtocol->Area->RootportSelected0Type =3D gTbtInfoHob-> DTbt= ControllerConfig.Type; + TbtNvsAreaProtocol->Area->RootportEnabled0 =3D gTbtInfoHob-> DTbt= ControllerConfig.DTbtControllerEn; + TbtNvsAreaProtocol->Area->TbtFrcPwrGpioNo0 =3D gTbtInfoHob-> DTbt= ControllerConfig.ForcePwrGpio.GpioPad; + TbtNvsAreaProtocol->Area->TbtFrcPwrGpioLevel0 =3D gTbtInfoHob-> DTbt= ControllerConfig.ForcePwrGpio.GpioLevel; + TbtNvsAreaProtocol->Area->TbtCioPlugEventGpioNo0 =3D gTbtInfoHob-> DTbt= ControllerConfig.CioPlugEventGpio.GpioPad; + TbtNvsAreaProtocol->Area->TbtPcieRstGpioNo0 =3D gTbtInfoHob-> DTbt= ControllerConfig.PcieRstGpio.GpioPad; + TbtNvsAreaProtocol->Area->TbtPcieRstGpioLevel0 =3D gTbtInfoHob-> DTbt= ControllerConfig.PcieRstGpio.GpioLevel; + + TbtNvsAreaProtocol->Area->TBtCommonGpioSupport =3D gTbtInfoHob->DTbtC= ommonConfig.DTbtSharedGpioConfiguration; + + DEBUG ((DEBUG_INFO, "TbtNvsAreaInit End\n")); +} + +/** + This function gets registered as a callback to patch TBT ASL code + + @param[in] Event - A pointer to the Event that triggered the callbac= k. + @param[in] Context - A pointer to private data registered with the cal= lback function. + can we put this also in read me +**/ +VOID +EFIAPI +TbtAcpiEndOfDxeCallback ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + UINT32 Address; + UINT16 Length; + UINT32 Signature; + + Status =3D InitializeAslUpdateLib (); + ASSERT_EFI_ERROR (Status); + + Address =3D (UINT32) (UINTN) mTbtNvsAreaProtocol.Area; + Length =3D (UINT16) sizeof (TBT_NVS_AREA); + DEBUG ((DEBUG_INFO, "Patch TBT NvsAreaAddress: TBT NVS Address %x Length= %x\n", Address, Length)); + Status =3D UpdateNameAslCode (SIGNATURE_32 ('T','N','V','B'), &Address,= sizeof (Address)); + ASSERT_EFI_ERROR (Status); + Status =3D UpdateNameAslCode (SIGNATURE_32 ('T','N','V','L'), &Length, = sizeof (Length)); + ASSERT_EFI_ERROR (Status); + + if (gTbtInfoHob !=3D NULL) { + if (gTbtInfoHob-> DTbtControllerConfig.DTbtControllerEn =3D=3D 1) { + if (gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSigna= turePorting =3D=3D TRUE) { + DEBUG ((DEBUG_INFO, "Patch ATBT Method Name\n")); + Signature =3D gTbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.= AcpiGpeSignature; + Status =3D UpdateNameAslCode (SIGNATURE_32 ('A','T','B','T'), &Si= gnature, sizeof (Signature)); + ASSERT_EFI_ERROR (Status); + } + } + } + + return; +} + +/** + Initialize Thunderbolt(TM) SSDT ACPI tables + + @retval EFI_SUCCESS ACPI tables are initialized successfully + @retval EFI_NOT_FOUND ACPI tables not found +**/ + +EFI_STATUS +EFIAPI +TbtDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + // EFI_EVENT EndOfDxeEvent; + + DEBUG ((DEBUG_INFO, "TbtDxeEntryPoint \n")); + + // + // Get TBT INFO HOB + // + gTbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid); + if (gTbtInfoHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + InstallTbtPolicy (ImageHandle); + // + // Update DXE TBT Policy + // + UpdateTbtPolicyCallback (); + + // + // Print DXE TBT Policy + // + TbtPrintDxePolicyConfig (); + + // + // Initialize Tbt Nvs Area + // + TbtNvsAreaInit ((VOID **) &mTbtNvsAreaProtocol.Area); + + + // + // [ACPI] Thunderbolt ACPI table + // + + + Handle =3D NULL; + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gTbtNvsAreaProtocolGuid, + &mTbtNvsAreaProtocol, + NULL + ); + ASSERT_EFI_ERROR (Status); + + // + // Register an end of DXE event for TBT ACPI to do some patch can be put= as description + // + /** + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + TbtAcpiEndOfDxeCallback, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + ASSERT_EFI_ERROR (Status); +**/ + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Pe= i/PeiTbtInit.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtIni= t/Pei/PeiTbtInit.c new file mode 100644 index 0000000000..bdd8de0cfd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Pei/PeiTb= tInit.c @@ -0,0 +1,211 @@ +/** @file + Source code file for TBT Init PEI module + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/* +/** + This function Update and Print PEI TBT Policy after TbtPolicyBoardInitDo= ne + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification = event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this fu= nction. + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ + + +/** + This function pass PEI TBT Policy to Hob at the end of PEI + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification = event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this fu= nction. + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ + + +EFI_STATUS +EFIAPI +PassTbtPolicyToHob ( +VOID + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + TBT_INFO_HOB *TbtInfoHob; + PEI_TBT_POLICY *PeiTbtConfig; + + DEBUG ((DEBUG_INFO, "PassTbtPolicyToHob\n")); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + if (BootMode =3D=3D BOOT_ON_S3_RESUME ) { + return EFI_SUCCESS; + } + + Status =3D PeiServicesLocatePpi ( + &gPeiTbtPolicyPpiGuid, + 0, + NULL, + (VOID **) &PeiTbtConfig + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + + // + // Create HOB for TBT Data + // + Status =3D PeiServicesCreateHob ( + EFI_HOB_TYPE_GUID_EXTENSION, + sizeof (TBT_INFO_HOB), + (VOID **) &TbtInfoHob + ); + DEBUG ((DEBUG_INFO, "TbtInfoHob Created \n")); + ASSERT_EFI_ERROR (Status); + + // + // Initialize the TBT INFO HOB data. + // + TbtInfoHob->EfiHobGuidType.Name =3D gTbtInfoHobGuid; + + // + // Update DTBT Policy + // + TbtInfoHob-> DTbtControllerConfig.DTbtControllerEn =3D PeiTbtConfig-> DT= btControllerConfig.DTbtControllerEn; + TbtInfoHob-> DTbtControllerConfig.Type =3D PeiTbtConfig-> DTbtController= Config.Type; + TbtInfoHob-> DTbtControllerConfig.PcieRpNumber =3D PeiTbtConfig-> DTbtCo= ntrollerConfig.PcieRpNumber; + TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioPad =3D PeiTbtConfig-= > DTbtControllerConfig.ForcePwrGpio.GpioPad; + TbtInfoHob-> DTbtControllerConfig.ForcePwrGpio.GpioLevel =3D PeiTbtConfi= g-> DTbtControllerConfig.ForcePwrGpio.GpioLevel; + TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.GpioPad =3D PeiTbtCon= fig-> DTbtControllerConfig.CioPlugEventGpio.GpioPad; + TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature =3D = PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignature; + TbtInfoHob-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignaturePorti= ng =3D PeiTbtConfig-> DTbtControllerConfig.CioPlugEventGpio.AcpiGpeSignatur= ePorting; + TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioPad =3D PeiTbtConfig->= DTbtControllerConfig.PcieRstGpio.GpioPad; + TbtInfoHob-> DTbtControllerConfig.PcieRstGpio.GpioLevel =3D PeiTbtConfig= -> DTbtControllerConfig.PcieRstGpio.GpioLevel; + + TbtInfoHob->DTbtCommonConfig.TbtBootOn =3D PeiTbtConfig->DTbtCommonConfi= g.TbtBootOn; + TbtInfoHob->DTbtCommonConfig.TbtUsbOn =3D PeiTbtConfig->DTbtCommonConfig= .TbtUsbOn; + TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwr =3D PeiTbtConfig->DTbtCommonC= onfig.Gpio3ForcePwr; + TbtInfoHob->DTbtCommonConfig.Gpio3ForcePwrDly =3D PeiTbtConfig->DTbtComm= onConfig.Gpio3ForcePwrDly; + TbtInfoHob->DTbtCommonConfig.DTbtSharedGpioConfiguration =3D PeiTbtConfi= g->DTbtCommonConfig.DTbtSharedGpioConfiguration; + TbtInfoHob->DTbtCommonConfig.PcieRstSupport =3D PeiTbtConfig->DTbtCommon= Config.PcieRstSupport; + + return EFI_SUCCESS; +} + + +/** + This function handles TbtInit task at the end of PEI + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification = event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this fu= nction. + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ + +EFI_STATUS +EFIAPI +TbtInitEndOfPei ( + VOID + ) +{ + EFI_STATUS Status; + BOOLEAN DTbtExisted; + PEI_TBT_POLICY *PeiTbtConfig; + + DEBUG ((DEBUG_INFO, "TbtInitEndOfPei Entry\n")); + + Status =3D EFI_SUCCESS; + PeiTbtConfig =3D NULL; + DTbtExisted =3D FALSE; + + Status =3D PeiServicesLocatePpi ( + &gPeiTbtPolicyPpiGuid, + 0, + NULL, + (VOID **) &PeiTbtConfig + ); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_ERROR, " gPeiTbtPolicyPpiGuid Not installed!!!\n")); + } + ASSERT_EFI_ERROR (Status); + + if (PeiTbtConfig-> DTbtControllerConfig.DTbtControllerEn =3D=3D 1) { + DTbtExisted =3D TRUE; + } + + if (DTbtExisted =3D=3D TRUE) { + // + // Call Init function + // + Status =3D TbtInit (); + } + + return EFI_SUCCESS; +} + +/** + TBT Init PEI module entry point + + @param[in] FileHandle Not used. + @param[in] PeiServices General purpose services available to e= very PEIM. + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se +**/ +EFI_STATUS +EFIAPI +TbtInitEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "TBT PEI EntryPoint\n")); + + // + // Install PEI TBT Policy + // + Status =3D InstallPeiTbtPolicy (); + ASSERT_EFI_ERROR (Status); + + + UpdatePeiTbtPolicy (); + + TbtPrintPeiPolicyConfig (); + // + // Performing PassTbtPolicyToHob and TbtInitEndOfPei + // + Status =3D PassTbtPolicyToHob (); + + Status =3D TbtInitEndOfPei (); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Sm= m/TbtSmiHandler.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Tbt= Init/Smm/TbtSmiHandler.c new file mode 100644 index 0000000000..a6bdc6ef9f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm= iHandler.c @@ -0,0 +1,1609 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "TbtSmiHandler.h" +#include +#include +#include +#include +#include +#include +#include +#define MEM_PER_SLOT (DEF_RES_MEM_PER_DEV << 4) +#define PMEM_PER_SLOT (DEF_RES_PMEM_PER_DEV << 4) +#define IO_PER_SLOT (DEF_RES_IO_PER_DEV << 2) + +GLOBAL_REMOVE_IF_UNREFERENCED UINTN gDeviceBaseAddress; +// +//US(X:0:0), DS(X+1:3:0),DS(X+1:4:0),DS(X+1:5:0),DS(X+1:6:0) +// +GLOBAL_REMOVE_IF_UNREFERENCED BRDG_CONFIG HrConfigs[MAX_CFG_PORT= S]; + +extern UINT8 gCurrentDiscreteTbtRootPort; +extern UINT8 gCurrentDiscreteTbtRootPortType; + +BOOLEAN isLegacyDevice =3D FALSE; +STATIC UINT8 TbtSegment =3D 0; + +STATIC +VOID +PortInfoInit ( + IN OUT PORT_INFO *PortInfo + ) +{ + PortInfo->BusNumLimit =3D 4; +} + +STATIC +VOID +UnsetVesc ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun + ) +{ + UINT8 Dbus; + UINT32 Data32; + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fu= n, 0); + + // + // Check for abcence of DS bridge + // + if(0xFFFF =3D=3D PciSegmentRead16(gDeviceBaseAddress + PCI_DEVICE_ID_OFF= SET)) { + return; + } + + // + // Unset vesc_reg2[23] bit (to have an option to access below DS) + // + Data32 =3D PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2); + Data32 &=3D 0xFF7FFFFF; + PciSegmentWrite32(gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32); + // + // Go to Device behind DS + // + Dbus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_= REGISTER_OFFSET); + DEBUG((DEBUG_INFO, "Dbus =3D %d\n",Dbus)); + // + // Check if there is something behind this Downstream Port (Up or Ep) + // If there nothing behind Downstream Port Set vesc_reg2[23] bit -> thi= s will flush all future MemWr + // + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Dbus, 0x00, = 0x00, 0); + if(0xFFFF =3D=3D PciSegmentRead16(gDeviceBaseAddress + PCI_DEVICE_ID_OFF= SET)) + { + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fu= n, 0); + Data32 =3D PciSegmentRead32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2); + Data32 |=3D 0x00800000; + PciSegmentWrite32 (gDeviceBaseAddress + PCI_TBT_VESC_REG2, Data32); + } +}// Unset_VESC_REG2 + +STATIC +UINT16 +MemPerSlot ( + IN UINT16 CurrentUsage + ) +{ + if (CurrentUsage =3D=3D 0) { + return 0; + } + + if (CurrentUsage <=3D 16) { + return 16; + } + + if (CurrentUsage <=3D 64) { + return 64; + } + + if (CurrentUsage <=3D 128) { + return 128; + } + + if (CurrentUsage <=3D 256) { + return 256; + } + + if (CurrentUsage <=3D 512) { + return 512; + } + + if (CurrentUsage <=3D 1024) { + return 1024; + } + + return CurrentUsage; +} // MemPerSlot + +STATIC +UINT64 +PMemPerSlot ( + IN UINT64 CurrentUsage + ) +{ + if (CurrentUsage =3D=3D 0) { + return 0; + } + + if (CurrentUsage <=3D 1024ULL) { + return 1024ULL; + } + + if (CurrentUsage <=3D 4096ULL) { + return 4096ULL; + } + + return CurrentUsage; +} // PMemPerSlot + +STATIC +VOID +SetPhyPortResources ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 SubBus, + IN INT8 Depth, + IN PORT_INFO *CurrentPi, + IN OUT PORT_INFO *PortInfo + ) +{ + UINT8 Cmd; + UINT16 DeltaMem; + UINT64 DeltaPMem; + + Cmd =3D CMD_BUS_MASTER; + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0x= 00, 0); + + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIST= ER_OFFSET, SubBus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); + + DeltaMem =3D PortInfo->MemBase - CurrentPi->MemBase; + if (isLegacyDevice) { + if (Depth >=3D 0 && (DeltaMem < MEM_PER_SLOT)) { + PortInfo->MemBase +=3D MEM_PER_SLOT - DeltaMem; + } + } else { + if (DeltaMem < MemPerSlot (DeltaMem)) { + PortInfo->MemBase +=3D MemPerSlot (DeltaMem) - DeltaMem; + } + } + + if (PortInfo->MemBase > CurrentPi->MemBase && (PortInfo->MemBase - 0x10)= <=3D PortInfo->MemLimit) { + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), CurrentPi->MemBase); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryLimit), PortInfo->MemBase - 0x10); + Cmd |=3D CMD_BM_MEM; + } else { + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), DISBL_MEM32_REG20); + PortInfo->MemBase =3D CurrentPi->MemBase; + } + + DeltaPMem =3D PortInfo->PMemBase64 - CurrentPi->PMemBase64; + if (isLegacyDevice) { + if ((Depth >=3D 0) && ((UINTN)DeltaPMem < (UINTN)PMEM_PER_SLOT)) { + PortInfo->PMemBase64 +=3D PMEM_PER_SLOT - DeltaPMem; + } + } else { + if (DeltaPMem < PMemPerSlot (DeltaPMem)) { + PortInfo->PMemBase64 +=3D PMemPerSlot (DeltaPMem) - DeltaPMem; + } + } + + if (PortInfo->PMemBase64 > CurrentPi->PMemBase64 && (PortInfo->PMemBase6= 4 - 0x10) <=3D PortInfo->PMemLimit64) { + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), (UINT16) (CurrentPi->PMemBase64 & 0xFFFF)); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryLimit), (UINT16) ((PortInfo->PMemBase64 - 0x10) & 0xFFFF)= ); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), (UINT32) (CurrentPi->PMemBase64 >> 16)); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), (UINT32) ((PortInfo->PMemBase64 - 0x10) >> 16)); + Cmd |=3D CMD_BM_MEM; + } else { + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), DISBL_PMEM_REG24); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), 0); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), 0); + PortInfo->PMemBase64 =3D CurrentPi->PMemBase64; + } + + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA= CHE_LINE_SIZE); +} // SetPhyPortResources + +STATIC +UINT32 +SaveSetGetRestoreBar ( + IN UINTN Bar + ) +{ + UINT32 BarReq; + UINT32 OrigBar; + + OrigBar =3D PciSegmentRead32(Bar); // Save BAR + PciSegmentWrite32(Bar, 0xFFFFFFFF); // Set BAR + BarReq =3D PciSegmentRead32(Bar); // Get BAR + PciSegmentWrite32(Bar, OrigBar); // Restore BAR + + return BarReq; +} // SaveSetGetRestoreBar + +STATIC +VOID +SetIoBar ( + IN UINTN BAR, + IN UINT32 BarReq, + IN OUT UINT8 *Cmd, + IN OUT IO_REGS *IoReg + ) +{ + UINT16 Alignment; + UINT16 Size; + UINT16 NewBase; + + Alignment =3D ~(BarReq & 0xFFFC); + Size =3D Alignment + 1; + + if (IoReg->Base > IoReg->Limit || !Size) { + return ; + + } + + NewBase =3D BAR_ALIGN (IoReg->Base, Alignment); + if (NewBase > IoReg->Limit || NewBase + Size - 1 > IoReg->Limit) { + return ; + + } + PciSegmentWrite16(BAR, NewBase); + IoReg->Base =3D NewBase + Size; // Advance to new position + *Cmd |=3D CMD_BM_IO; // Set Io Space Enable +} // SetIoBar + +STATIC +VOID +SetMemBar ( + IN UINTN BAR, + IN UINT32 BarReq, + IN OUT UINT8 *Cmd, + IN OUT MEM_REGS *MemReg + ) +{ + UINT32 Alignment; + UINT32 Size; + UINT32 NewBase; + + Alignment =3D ~(BarReq & 0xFFFFFFF0); + Size =3D Alignment + 1; + + if (MemReg->Base > MemReg->Limit || !Size) { + return ; + + } + + NewBase =3D BAR_ALIGN (MemReg->Base, Alignment); + if (NewBase > MemReg->Limit || NewBase + Size - 1 > MemReg->Limit) { + return ; + + } + + PciSegmentWrite32(BAR, NewBase); + MemReg->Base =3D NewBase + Size; // Advance to new position + *Cmd |=3D CMD_BM_MEM; // Set Memory Space Enable +} // SetMemBar + +STATIC +VOID +SetPMem64Bar ( + IN UINTN BAR, + IN BOOLEAN IsMaxBar, + IN UINT32 BarReq, + IN OUT UINT8 *Cmd, + IN OUT PMEM_REGS *MemReg + ) +{ + UINT32 Alignment; + UINT32 Size; + UINT64 NewBase; + + Alignment =3D ~(BarReq & 0xFFFFFFF0); + Size =3D Alignment + 1; + + if (MemReg->Base64 > MemReg->Limit64 || !Size) { + return ; + } + + NewBase =3D BAR_ALIGN (MemReg->Base64, Alignment); + if (NewBase > MemReg->Limit64 || NewBase + Size - 1 > MemReg->Limit64) { + return ; + } + PciSegmentWrite32(BAR, (UINT32)(NewBase & 0xFFFFFFFF)); + if (!IsMaxBar) { + BAR++; + PciSegmentWrite32(BAR, (UINT32)(NewBase >> 32)); + } + MemReg->Base64 =3D NewBase + Size; // Advance to new position + *Cmd |=3D CMD_BM_MEM; // Set Memory Space Enable +} // SetPMem64Bar + +STATIC +VOID +SetDevResources ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 MaxFun, // PCI_MAX_FUNC for devices, 1 for bridge + IN UINT8 MaxBar, // PCI_BAR5 for devices, PCI_BAR1 for br= idge + IN OUT PORT_INFO *PortInfo + ) +{ + UINT8 Fun; + UINT8 Reg; + UINT32 BarReq; + IO_REGS Io; + MEM_REGS Mem; + PMEM_REGS PMem; + UINT8 Cmd; + + Io.Base =3D PortInfo->IoBase << 8; + Io.Limit =3D (PortInfo->IoLimit << 8) | 0xFF; + Mem.Base =3D PortInfo->MemBase << 16; + Mem.Limit =3D (PortInfo->MemLimit << 16) | 0xFFFF; + PMem.Base64 =3D PortInfo->PMemBase64 << 16; + PMem.Limit64 =3D (PortInfo->PMemLimit64 << 16) | 0xFFFF; + + for (Fun =3D 0; Fun < MaxFun; ++Fun) { + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, = Fun, 0); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BUS_MAS= TER); + Cmd =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET); + if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID= _OFFSET)) { + continue; + + } + + for (Reg =3D PCI_BASE_ADDRESSREG_OFFSET; Reg <=3D MaxBar; Reg +=3D 4) { + BarReq =3D SaveSetGetRestoreBar(gDeviceBaseAddress + Reg); // Perfor= m BAR sizing + + if (BarReq & BIT0) { + // + // I/O BAR + // + SetIoBar ( + (gDeviceBaseAddress + Reg), + BarReq, + &Cmd, + &Io + ); + continue; + } + + if (BarReq & BIT3) { + // + // P-Memory BAR + // + SetPMem64Bar ((gDeviceBaseAddress + Reg), MaxBar =3D=3D Reg, BarRe= q, &Cmd, &PMem); + } else { + SetMemBar ((gDeviceBaseAddress + Reg), BarReq, &Cmd, &Mem); + } + + if (BIT2 =3D=3D (BarReq & (BIT2 | BIT1))) { + // + // Base address is 64 bits wide + // + Reg +=3D 4; + if (!(BarReq & BIT3)) { + // + // 64-bit memory bar + // + PciSegmentWrite32 (gDeviceBaseAddress + Reg, 0); + } + } + } + + if (Cmd & BIT1) { + // + // If device uses I/O and MEM mapping use only MEM mepping + // + Cmd &=3D ~BIT0; + } + + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_= CACHE_LINE_SIZE); + } + // + // Update PortInfo if any changes + // + if (Io.Base > ((UINT32) PortInfo->IoBase << 8)) { + PortInfo->IoBase =3D (UINT8) (BAR_ALIGN (Io.Base, 0xFFF) >> 8); + } + + if (Mem.Base > ((UINT32) PortInfo->MemBase << 16)) { + PortInfo->MemBase =3D (UINT16) (BAR_ALIGN (Mem.Base, 0xFFFFF) >> 16); + } + + if (PMem.Base64 > (PortInfo->PMemBase64 << 16)) { + PortInfo->PMemBase64 =3D (BAR_ALIGN (PMem.Base64, 0xFFFFF) >> 16); + } +} // SetDevResources + +STATIC +VOID +InitARHRConfigs( + IN HR_CONFIG *Hr_Config, + IN UINT8 BusNumLimit, + IN OUT BRDG_RES_CONFIG* HrResConf +) +{ + UINT8 i,j; + + // + // DS port for USB device + // + HrConfigs[AR_DS_PORT2].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1; + HrConfigs[AR_DS_PORT2].DevId.Dev =3D 2; + HrConfigs[AR_DS_PORT2].DevId.Fun =3D 0; + HrConfigs[AR_DS_PORT2].PBus =3D HrConfigs[AR_DS_PORT2].DevId.Bus; + HrConfigs[AR_DS_PORT2].SBus =3D HrConfigs[AR_DS_PORT2].PBus + 1; + HrConfigs[AR_DS_PORT2].SubBus =3D HrConfigs[AR_DS_PORT2].PBus + 1; + // + // CIO port + // + HrConfigs[AR_DS_PORT1].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1; + HrConfigs[AR_DS_PORT1].DevId.Dev =3D 1; + HrConfigs[AR_DS_PORT1].DevId.Fun =3D 0; + HrConfigs[AR_DS_PORT1].PBus =3D HrConfigs[AR_DS_PORT1].DevId.Bus; + HrConfigs[AR_DS_PORT1].SBus =3D HrConfigs[HR_DS_PORT0].SubBus + 1; + HrConfigs[AR_DS_PORT1].SubBus =3D BusNumLimit; + + switch(Hr_Config->DeviceId) + { + // + // HR with 1 DS and 1 USB + // + case AR_HR_2C: + case AR_HR_LP: + case AR_HR_C0_2C: + case TR_HR_2C: + Hr_Config->MinDSNumber =3D HrConfigs[AR_DS_PORT1].DevId.Dev; + Hr_Config->MaxDSNumber =3D HrConfigs[AR_DS_PORT2].DevId.Dev; + Hr_Config->BridgeLoops =3D 4; + break; + // + // HR with 2 DS and 1 USB + // + case AR_HR_4C: + case TR_HR_4C: + case AR_HR_C0_4C: + Hr_Config->MinDSNumber =3D 1; + Hr_Config->MaxDSNumber =3D 4; + Hr_Config->BridgeLoops =3D 6; + for(j =3D 2, i =3D Hr_Config->MinDSNumber; j < count(HrConfigs) && i= <=3D Hr_Config->MaxDSNumber; ++j, ++i) + { + HrConfigs[j].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1; + HrConfigs[j].DevId.Dev =3D i; + HrConfigs[j].DevId.Fun =3D 0; + HrConfigs[j].PBus =3D HrConfigs[j].DevId.Bus; + HrConfigs[j].Res.Cls =3D DEF_CACHE_LINE_SIZE; + } + break; + } +}//InitARHRConfigs + + +STATIC +VOID +InitCommonHRConfigs ( + IN HR_CONFIG *Hr_Config, + IN UINT8 BusNumLimit, + IN OUT BRDG_RES_CONFIG *HrResConf + ) +{ + UINT8 i; + + UINT8 j; + for(i =3D 0; i < count(HrConfigs); ++i) { + HrConfigs[i].IsDSBridge =3D TRUE; + } + // + // US(HRBus:0:0) + // + HrConfigs[HR_US_PORT].DevId.Bus =3D Hr_Config->HRBus; + HrConfigs[HR_US_PORT].DevId.Dev =3D 0; + HrConfigs[HR_US_PORT].DevId.Fun =3D 0; + HrConfigs[HR_US_PORT].Res =3D *HrResConf; + HrConfigs[HR_US_PORT].Res.IoBase =3D 0xF1; + HrConfigs[HR_US_PORT].Res.IoLimit =3D 0x01; + HrConfigs[HR_US_PORT].PBus =3D HrConfigs[HR_US_PORT].DevId.Bus; + HrConfigs[HR_US_PORT].SBus =3D HrConfigs[HR_US_PORT].PBus + 1; + HrConfigs[HR_US_PORT].SubBus =3D BusNumLimit; + HrConfigs[HR_US_PORT].IsDSBridge =3D FALSE; + + // + // HIA resides here + // + HrConfigs[HR_DS_PORT0].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus = + 1; + HrConfigs[HR_DS_PORT0].DevId.Dev =3D 0; + HrConfigs[HR_DS_PORT0].DevId.Fun =3D 0; + HrConfigs[HR_DS_PORT0].Res =3D NOT_IN_USE_BRIDGE; + HrConfigs[HR_DS_PORT0].Res.MemBase =3D HrResConf->MemLimit; + HrConfigs[HR_DS_PORT0].Res.MemLimit =3D HrResConf->MemLimit; + HrResConf->MemLimit -=3D 0x10; //This 1 MB chunk will be = used by HIA + HrConfigs[HR_DS_PORT0].Res.Cmd =3D CMD_BM_MEM; + HrConfigs[HR_DS_PORT0].Res.Cls =3D DEF_CACHE_LINE_SIZE; + HrConfigs[HR_DS_PORT0].PBus =3D HrConfigs[HR_DS_PORT0].DevId.Bus; + HrConfigs[HR_DS_PORT0].SBus =3D HrConfigs[HR_DS_PORT0].PBus + 1; + HrConfigs[HR_DS_PORT0].SubBus =3D HrConfigs[HR_DS_PORT0].PBus + 1; + + switch (Hr_Config->DeviceId) { + // + // Alpine Ridge + // + case AR_HR_2C: + case AR_HR_C0_2C: + case AR_HR_LP: + case AR_HR_4C: + case AR_HR_C0_4C: + // + // Titan Ridge + // + case TR_HR_2C: + case TR_HR_4C: + InitARHRConfigs(Hr_Config, BusNumLimit, HrResConf); + break; + + default: + // + // DS(HRBus+2:3-6:0) + // + Hr_Config->MinDSNumber =3D 3; + Hr_Config->MaxDSNumber =3D 6; + Hr_Config->BridgeLoops =3D count (HrConfigs); + + for (j =3D 2, i =3D Hr_Config->MinDSNumber; j < count (HrConfigs) && i= <=3D Hr_Config->MaxDSNumber; ++j, ++i) { + HrConfigs[j].DevId.Bus =3D HrConfigs[HR_US_PORT].DevId.Bus + 1; + HrConfigs[j].DevId.Dev =3D i; + HrConfigs[j].DevId.Fun =3D 0; + HrConfigs[j].PBus =3D HrConfigs[j].DevId.Bus; + HrConfigs[j].Res.Cls =3D DEF_CACHE_LINE_SIZE; + } + } +} // InitCommonHRConfigs + +STATIC +VOID +InitHRDSPort_Disable ( + IN UINT8 id, + IN OUT BRDG_CONFIG *BrdgConf + ) +{ + HrConfigs[id].Res =3D NOT_IN_USE_BRIDGE; + HrConfigs[id].SBus =3D BrdgConf->SBus; + HrConfigs[id].SubBus =3D BrdgConf->SBus; + + BrdgConf->SBus++; +} // InitHRDSPort_Disable + +//AR only + +STATIC +VOID +InitARDSPort_1Port( + IN OUT BRDG_CONFIG* BrdgConf +) +{ + UINT16 MemBase =3D BrdgConf->Res.MemBase & 0xFFF0; + UINT64 PMemBase64 =3D BrdgConf->Res.PMemBase64 & ~0xFULL; + UINT8 BusRange =3D BrdgConf->SubBus - BrdgConf->PBus - 2; + + HrConfigs[AR_DS_PORT1].Res =3D NOT_IN_USE_BRIDGE; + HrConfigs[AR_DS_PORT1].Res.Cls =3D DEF_CACHE_LINE_SIZE; + HrConfigs[AR_DS_PORT1].Res.Cmd =3D CMD_BM_MEM; + HrConfigs[AR_DS_PORT1].Res.MemBase =3D MemBase; + HrConfigs[AR_DS_PORT1].Res.MemLimit =3D BrdgConf->Res.MemLimit - 1; + HrConfigs[AR_DS_PORT1].Res.PMemBase64 =3D PMemBase64; + HrConfigs[AR_DS_PORT1].Res.PMemLimit64 =3D BrdgConf->Res.PMemLimit64; + HrConfigs[AR_DS_PORT1].SBus =3D BrdgConf->SBus; + HrConfigs[AR_DS_PORT1].SubBus =3D BrdgConf->SBus + BusRange; + + BrdgConf->SBus =3D HrConfigs[AR_DS_PORT1].SubBus + 1; + + HrConfigs[AR_DS_PORT2].Res =3D NOT_IN_USE_BRIDGE; + HrConfigs[AR_DS_PORT2].Res.Cls =3D DEF_CACHE_LINE_SIZE; + HrConfigs[AR_DS_PORT2].Res.Cmd =3D CMD_BM_MEM; + HrConfigs[AR_DS_PORT2].Res.MemBase =3D BrdgConf->Res.MemLimit; + HrConfigs[AR_DS_PORT2].Res.MemLimit =3D BrdgConf->Res.MemLimit; + HrConfigs[AR_DS_PORT2].SBus =3D BrdgConf->SBus; + HrConfigs[AR_DS_PORT2].SubBus =3D BrdgConf->SBus; + + BrdgConf->SBus =3D HrConfigs[AR_DS_PORT2].SubBus + 1; +}//InitARDSPort_1Port + +STATIC +VOID +InitARDSPort_2Port( + IN OUT BRDG_CONFIG* BrdgConf +) +{ + UINT16 MemBase =3D BrdgConf->Res.MemBase & 0xFFF0; + UINT64 PMemBase64 =3D BrdgConf->Res.PMemBase64 & ~0xFULL; + UINT8 BusRange =3D BrdgConf->SubBus - BrdgConf->PBus - 3; + + // Busses are split between ports 1 and 4 + BusRange /=3D 2; + + HrConfigs[AR_DS_PORT1].Res =3D NOT_IN_USE_BRIDGE; + HrConfigs[AR_DS_PORT1].Res.Cls =3D DEF_CACHE_LINE_SIZE; + HrConfigs[AR_DS_PORT1].Res.Cmd =3D CMD_BM_MEM; + HrConfigs[AR_DS_PORT1].Res.MemBase =3D MemBase; + HrConfigs[AR_DS_PORT1].Res.MemLimit =3D MemBase + 0x17F0 - 1; + HrConfigs[AR_DS_PORT1].Res.PMemBase64 =3D PMemBase64; + HrConfigs[AR_DS_PORT1].Res.PMemLimit64 =3D PMemBase64 + 0x2000 - 1; + HrConfigs[AR_DS_PORT1].SBus =3D BrdgConf->SBus; + HrConfigs[AR_DS_PORT1].SubBus =3D BrdgConf->SBus + BusRange; + + BrdgConf->SBus =3D HrConfigs[AR_DS_PORT1].SubBus + 1; + + HrConfigs[AR_DS_PORT2].Res =3D NOT_IN_USE_BRIDGE; + HrConfigs[AR_DS_PORT2].Res.Cls =3D DEF_CACHE_LINE_SIZE; + HrConfigs[AR_DS_PORT2].Res.Cmd =3D CMD_BM_MEM; + HrConfigs[AR_DS_PORT2].Res.MemBase =3D MemBase + 0x17F0; + HrConfigs[AR_DS_PORT2].Res.MemLimit =3D MemBase + 0x1800 - 1; + HrConfigs[AR_DS_PORT2].SBus =3D BrdgConf->SBus; + HrConfigs[AR_DS_PORT2].SubBus =3D BrdgConf->SBus; + + BrdgConf->SBus =3D HrConfigs[AR_DS_PORT2].SubBus + 1; + + + HrConfigs[AR_DS_PORT4].Res =3D NOT_IN_USE_BRIDGE; + HrConfigs[AR_DS_PORT4].Res.Cls =3D DEF_CACHE_LINE_SIZE; + HrConfigs[AR_DS_PORT4].Res.Cmd =3D CMD_BM_MEM; + HrConfigs[AR_DS_PORT4].Res.MemBase =3D MemBase + 0x1800; + HrConfigs[AR_DS_PORT4].Res.MemLimit =3D BrdgConf->Res.MemLimit; + HrConfigs[AR_DS_PORT4].Res.PMemBase64 =3D PMemBase64 + 0x2000; + HrConfigs[AR_DS_PORT4].Res.PMemLimit64 =3D BrdgConf->Res.PMemLimit64; + HrConfigs[AR_DS_PORT4].SBus =3D BrdgConf->SBus; + HrConfigs[AR_DS_PORT4].SubBus =3D BrdgConf->SubBus; + + BrdgConf->SBus =3D HrConfigs[AR_DS_PORT4].SubBus + 1; +}//InitARDSPort_2Port + + +STATIC +BOOLEAN +CheckLimits ( + IN BOOLEAN Is2PortDev, + IN BRDG_RES_CONFIG *HrResConf, + IN UINT8 BusRange + ) +{ + UINT16 MemBase; + UINT16 MemLimit; + UINT64 PMemBase64; + UINT64 PMemLimit64; + + MemBase =3D HrResConf->MemBase & 0xFFF0; + MemLimit =3D HrResConf->MemLimit & 0xFFF0; + PMemBase64 =3D HrResConf->PMemBase64 & 0xFFF0; + PMemLimit64 =3D HrResConf->PMemLimit64 & 0xFFF0; + // + // Check memoty alignment + // + if (MemBase & 0x3FF) { + DEBUG((DEBUG_INFO, "M alig\n")); + return FALSE; + } + + if (PMemBase64 & 0xFFF) { + DEBUG((DEBUG_INFO, "PM alig\n")); + return FALSE; + } + + if (Is2PortDev) { + // + // Check mem size + // + if (MemLimit + 0x10 - MemBase < 0x2E00) { + DEBUG((DEBUG_INFO, "M size\n")); + return FALSE; + } + // + // Check P-mem size + // + if (PMemLimit64 + 0x10 - PMemBase64 < 0x4A00) { + DEBUG((DEBUG_INFO, "PM size\n")); + return FALSE; + } + // + // Check bus range + // + if (BusRange < 106) { + DEBUG((DEBUG_INFO, "Bus range\n")); + return FALSE; + } + } else { + // + // Check mem size + // + if (MemLimit + 0x10 - MemBase < 0x1600) { + DEBUG((DEBUG_INFO, "M size\n")); + return FALSE; + } + // + // Check P-mem size + // + if (PMemLimit64 + 0x10 - PMemBase64 < 0x2200) { + DEBUG((DEBUG_INFO, "PM size\n")); + return FALSE; + } + // + // Check bus range + // + if (BusRange < 56) { + DEBUG((DEBUG_INFO, "Bus range\n")); + return FALSE; + } + } + + return TRUE; +} // CheckLimits + +STATIC +BOOLEAN +InitHRResConfigs ( + IN OUT HR_CONFIG *Hr_Config, + IN UINT8 BusNumLimit, + IN OUT BRDG_RES_CONFIG*HrResConf + ) +{ + BRDG_CONFIG BrdgConf =3D { { 0 } }; + + InitCommonHRConfigs (Hr_Config, BusNumLimit, HrResConf); + BrdgConf.PBus =3D Hr_Config->HRBus + 2;// Take into account busses + BrdgConf.SBus =3D Hr_Config->HRBus + 3;// for US and DS of HIA + BrdgConf.SubBus =3D BusNumLimit; + BrdgConf.Res =3D *HrResConf; + while (TRUE) { + switch (Hr_Config->DeviceId) { + case AR_HR_4C: + case TR_HR_4C: + case AR_HR_C0_4C: + // + // 2 Port host + // + if (CheckLimits (TRUE, HrResConf, BusNumLimit - Hr_Config->HRBus)) { + + + InitARDSPort_2Port(&BrdgConf); + DEBUG((DEBUG_INFO, "AR2\n")); + + return TRUE; + } else { + return FALSE; + } + // AR only + case AR_HR_2C: // 1 port host + case AR_HR_C0_2C: + case AR_HR_LP: + case TR_HR_2C: + DEBUG((DEBUG_INFO, "AR1\n")); + InitARDSPort_1Port(&BrdgConf); + return TRUE; + + default: + InitHRDSPort_Disable (HR_DS_PORT3, &BrdgConf); + InitHRDSPort_Disable (HR_DS_PORT4, &BrdgConf); + InitHRDSPort_Disable (HR_DS_PORT5, &BrdgConf); + InitHRDSPort_Disable (HR_DS_PORT6, &BrdgConf); + return FALSE; + } + } +} // InitHRResConfigs + +STATIC +BOOLEAN +InitializeHostRouter ( + OUT HR_CONFIG *Hr_Config, + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction + ) +{ + UINT8 BusNumLimit; + BRDG_RES_CONFIG HrResConf =3D { 0 }; + UINT8 i; + BOOLEAN Ret; + + Ret =3D TRUE; + + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, RpDe= vice, RpFunction, 0); + Hr_Config->HRBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE= _SECONDARY_BUS_REGISTER_OFFSET); + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, Hr_Config->= HRBus, 0x00, 0x00, 0); + Hr_Config->DeviceId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVIC= E_ID_OFFSET); + if (!(IsTbtHostRouter (Hr_Config->DeviceId))) { + return FALSE; + } + TbtSegment =3D (UINT8)RpSegment; + + HrResConf.Cmd =3D CMD_BM_MEM; + HrResConf.Cls =3D DEF_CACHE_LINE_SIZE; + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus, R= pDevice, RpFunction, 0); + HrResConf.IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET_= OF (PCI_TYPE01, Bridge.IoBase)); + HrResConf.IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET_= OF (PCI_TYPE01, Bridge.IoLimit)); + HrResConf.MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.MemoryBase)); + HrResConf.MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.MemoryLimit)); + HrResConf.PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)); + HrResConf.PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)); + HrResConf.PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddress= + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16; + HrResConf.PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddress= + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16; + BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDI= NATE_BUS_REGISTER_OFFSET); + + Ret =3D InitHRResConfigs (Hr_Config, BusNumLimit, &HrResConf); + + for (i =3D 0; i < Hr_Config->BridgeLoops; ++i) { + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + Bus =3D HrConfigs[i].DevId.Bus; + Dev =3D HrConfigs[i].DevId.Dev; + Fun =3D HrConfigs[i].DevId.Fun; + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, F= un, 0); + + PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, HrCo= nfigs[i].Res.Cls); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER= _OFFSET, HrConfigs[i].PBus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST= ER_OFFSET, HrConfigs[i].SBus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI= STER_OFFSET, HrConfigs[i].SubBus); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), HrConfigs[i].Res.MemBase); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryLimit), HrConfigs[i].Res.MemLimit); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), (UINT16) (HrConfigs[i].Res.PMemBase64 & 0xFFFF)); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryLimit), (UINT16) (HrConfigs[i].Res.PMemLimit64 & 0xFFFF)); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), (UINT32) (HrConfigs[i].Res.PMemBase64 >> 16)); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), (UINT32) (HrConfigs[i].Res.PMemLimit64 >> 16)); + PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oBase), HrConfigs[i].Res.IoBase); + PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oLimit), HrConfigs[i].Res.IoLimit); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoBaseUpper16), 0x00000000); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, HrConfigs[i= ].Res.Cmd); + } + if (Hr_Config->DeviceId =3D=3D AR_HR_2C || Hr_Config->DeviceId =3D=3D AR= _HR_4C || Hr_Config->DeviceId =3D=3D AR_HR_LP) { + for (i =3D 0; i < Hr_Config->BridgeLoops; ++i) { + if(HrConfigs[i].IsDSBridge) { + UnsetVesc(HrConfigs[i].DevId.Bus, HrConfigs[i].DevId.Dev, HrConfig= s[i].DevId.Fun); + } + } + } + + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,(Hr_Config->H= RBus + 2), 0x00, 0x00, 0); + PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PC= I_BAR_IDX0 * 4), HrConfigs[HR_DS_PORT0].Res.MemLimit << 16); + PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFSET + (PC= I_BAR_IDX1 * 4), (HrConfigs[HR_DS_PORT0].Res.MemLimit + 0x4) << 16); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA= CHE_LINE_SIZE); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BM_MEM); + return Ret; +} // InitializeHostRouter +STATIC +UINT8 +ConfigureSlot ( + IN UINT8 Bus, + IN UINT8 MAX_DEVICE, + IN INT8 Depth, + IN BOOLEAN ArPcie, + IN OUT PORT_INFO *PortInfo + ) +{ + UINT8 Device; + UINT8 SBus; + UINT8 UsedBusNumbers; + UINT8 RetBusNum; + PORT_INFO CurrentSlot; + + RetBusNum =3D 0; + + for (Device =3D 0; Device < MAX_DEVICE; Device++) { + // + // Continue if device is absent + // + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Devic= e, 0x00, 0); + if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID= _OFFSET)) { + continue; + + } + + if (P2P_BRIDGE !=3D PciSegmentRead16 (gDeviceBaseAddress + (PCI_CLASSC= ODE_OFFSET + 1))) { + SetDevResources ( + Bus, + Device, + PCI_MAX_FUNC, + PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR_IDX5 * 4), + PortInfo + ); + continue; + } + // + // Else Bridge + // + CopyMem (&CurrentSlot, PortInfo, sizeof (PORT_INFO)); + + ++RetBusNum; // UP Bridge + SBus =3D Bus + RetBusNum; // DS Bridge + + if (SBus + 1 >=3D PortInfo->BusNumLimit) { + continue; + + } + + SetDevResources (Bus, Device, 1, PCI_BASE_ADDRESSREG_OFFSET + (PCI_BAR= _IDX1 * 4), PortInfo); + + // + // Init UP Bridge to reach DS Bridge + // + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER= _OFFSET, Bus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST= ER_OFFSET, SBus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI= STER_OFFSET, PortInfo->BusNumLimit); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BM_MEM); + + if(ArPcie) { + UnsetVesc(Bus, Device, 0x00); + } + + UsedBusNumbers =3D ConfigureSlot(SBus, PCI_MAX_DEVICE + 1, -1, FALSE, Po= rtInfo); + RetBusNum +=3D UsedBusNumbers; + + SetPhyPortResources ( + Bus, + Device, + SBus + UsedBusNumbers, + Depth, + &CurrentSlot, + PortInfo + ); + } + // + // for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++) + // + return RetBusNum; +} // ConfigureSlot + +STATIC +VOID +SetCioPortResources ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 SBus, + IN UINT8 SubBus, + IN PORT_INFO *portInfoBeforeChange, + IN OUT PORT_INFO *PortInfo + ) +{ + UINT8 Cmd; + Cmd =3D CMD_BUS_MASTER; + + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, 0x0= 0, 0); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER_O= FFSET, Bus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTER= _OFFSET, SBus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIST= ER_OFFSET, SubBus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); + + if (PortInfo->IoBase <=3D PortInfo->IoLimit) { + PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oBase), PortInfo->IoBase); + PciSegmentWrite8 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.I= oLimit), PortInfo->IoLimit); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoBaseUpper16), 0x00000000); + Cmd |=3D CMD_BM_IO; + } else { + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoBase), DISBL_IO_REG1C); + } + + if (PortInfo->MemBase <=3D PortInfo->MemLimit) { + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), PortInfo->MemBase); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryLimit), PortInfo->MemLimit); + Cmd |=3D CMD_BM_MEM; + } else { + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), DISBL_MEM32_REG20); + } + + if (PortInfo->PMemBase64 <=3D PortInfo->PMemLimit64) { + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), (UINT16) (PortInfo->PMemBase64 & 0xFFFF)); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryLimit), (UINT16) (PortInfo->PMemLimit64 & 0xFFFF)); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), (UINT32) (PortInfo->PMemBase64 >> 16)); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), (UINT32) (PortInfo->PMemLimit64 >> 16)); + Cmd |=3D CMD_BM_MEM; + } else { + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), DISBL_PMEM_REG24); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableBaseUpper32), 0); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableLimitUpper32), 0); + } + + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, Cmd); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_CA= CHE_LINE_SIZE); +} // SetCioPortResources + +STATIC +VOID +SetSlotsAsUnused ( + IN UINT8 Bus, + IN UINT8 MaxSlotNum, + IN UINT8 CioSlot, + IN OUT PORT_INFO *PortInfo + ) +{ + UINT8 Slot; + for (Slot =3D MaxSlotNum; Slot > CioSlot; --Slot) { + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Slot, = 0x00, 0); + if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID= _OFFSET)) { + continue; + } + + PciSegmentWrite8 (gDeviceBaseAddress + PCI_CACHELINE_SIZE_OFFSET, DEF_= CACHE_LINE_SIZE); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_REGISTER= _OFFSET, Bus); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGIST= ER_OFFSET, PortInfo->BusNumLimit); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGI= STER_OFFSET, PortInfo->BusNumLimit); + PciSegmentWrite16 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= IoBase), DISBL_IO_REG1C); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= MemoryBase), DISBL_MEM32_REG20); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, Bridge.= PrefetchableMemoryBase), DISBL_PMEM_REG24); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, CMD_BUS_MAS= TER); + PortInfo->BusNumLimit--; + } +} // SetSlotsAsUnused + +STATIC +UINT16 +FindVendorSpecificHeader( + IN UINT8 Bus +) +{ + PCI_EXP_EXT_HDR *ExtHdr; + UINT32 ExtHdrValue; + UINT16 ExtendedRegister; + + ExtHdr =3D (PCI_EXP_EXT_HDR*) &ExtHdrValue; + ExtendedRegister =3D 0x100; + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x= 00, 0); + while (ExtendedRegister) { + ExtHdrValue =3D PciSegmentRead32 (gDeviceBaseAddress + ExtendedRegiste= r); + if (ExtHdr->CapabilityId =3D=3D 0xFFFF) { + return 0x0000; // No Vendor-Specific Extended Capability header + } + + if (PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID =3D=3D ExtHdr->= CapabilityId) { + return ExtendedRegister; + } + + ExtendedRegister =3D (UINT16) ExtHdr->NextCapabilityOffset; + } + return 0x0000; // No Vendor-Specific Extended Capability header +} + +STATIC +UINT8 +FindSsid_SsvidHeader ( + IN UINT8 Bus + ) +{ + UINT8 CapHeaderId; + UINT8 CapHeaderOffset; + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x= 00, 0); + CapHeaderOffset =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_CAPBILIT= Y_POINTER_OFFSET); + + while (CapHeaderOffset !=3D 0) { + CapHeaderId =3D PciSegmentRead8 (gDeviceBaseAddress + CapHeaderOffset); + + if (CapHeaderId =3D=3D PCIE_CAP_ID_SSID_SSVID) { + return CapHeaderOffset; + } + + CapHeaderOffset =3D PciSegmentRead8 (gDeviceBaseAddress + CapHeaderOff= set + 1); + } + + DEBUG((DEBUG_INFO, "SID0\n")); + return 0; +} // FindSsid_SsvidHeader + +STATIC +BOOLEAN +GetCioSlotByDevId ( + IN UINT8 Bus, + OUT UINT8 *CioSlot, + OUT UINT8 *MaxSlotNum, + OUT BOOLEAN *ArPcie + ) +{ + UINT16 VSECRegister; + BRDG_CIO_MAP_REG BridgMap; + UINT32 BitScanRes; + UINT16 DevId; + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, 0x00, 0= x00, 0); + DevId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_= ID_OFFSET); + + // + // Init out params in case device is not recognised + // + *CioSlot =3D 4; + *MaxSlotNum =3D 7; + *ArPcie =3D FALSE; + + switch (DevId) { + // + // For known device IDs + // + case 0x1578: + *ArPcie =3D TRUE; + } + + switch (DevId) { + // + // For known device IDs + // + case 0x1513: + case 0x151A: + case 0x151B: + case 0x1547: + case 0x1548: + return TRUE; // Just return + case 0x1549: + return FALSE; // Just return + } + + VSECRegister =3D FindVendorSpecificHeader(Bus); + if (!VSECRegister) { + return TRUE; // Just return + } + // + // Go to Bridge/CIO map register + // + VSECRegister +=3D 0x18; + BridgMap.AB_REG =3D PciSegmentRead32(gDeviceBaseAddress + VSECRegister); + // + // Check for range + // + if (BridgMap.Bits.NumOfDSPorts < 1 || BridgMap.Bits.NumOfDSPorts > 27) { + return TRUE; + // + // Not a valid register + // + } + // + // Set OUT params + // + *MaxSlotNum =3D (UINT8) BridgMap.Bits.NumOfDSPorts; + +#ifdef _MSC_VER + if(!_BitScanForward(&BitScanRes, BridgMap.Bits.CioPortMap)) { // No DS b= ridge which is CIO port + return FALSE; + } +#else +#ifdef __GNUC__ + if (BridgMap.Bits.CioPortMap =3D=3D 0) { + return FALSE; + } + BitScanRes =3D __builtin_ctz (BridgMap.Bits.CioPortMap); +#else +#error Unsupported Compiler +#endif +#endif + + *CioSlot =3D (UINT8)BitScanRes; + return TRUE; +} // GetCioSlotByDevId + +#define TBT_LEGACY_SUB_SYS_ID 0x11112222 + +STATIC +BOOLEAN +IsLegacyDevice ( + IN UINT8 Bus + ) +{ + UINT32 Sid; + UINT8 SidRegister; + UINT16 DevId; + + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, 0x00, 0x= 00, 0); + DevId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_= ID_OFFSET); + switch (DevId) { + // + // For known device IDs + // + case 0x1513: + case 0x151A: + case 0x151B: + DEBUG((DEBUG_INFO, "Legacy ")); + DEBUG((DEBUG_INFO, "DevId =3D %d\n",DevId)); + return TRUE; + // + // Legacy device by Device Id + // + } + + SidRegister =3D FindSsid_SsvidHeader(Bus); + + if (!SidRegister) { + return TRUE; // May be absent for legacy devices + } + // + // Go to register + // + SidRegister +=3D 0x4; + Sid =3D PciSegmentRead32(gDeviceBaseAddress + SidRegister); + DEBUG((DEBUG_INFO, "SID")); + DEBUG((DEBUG_INFO, " =3D %d\n", Sid)); + +return TBT_LEGACY_SUB_SYS_ID =3D=3D Sid || 0 =3D=3D Sid; +} // IsLegacyDevice + +STATIC +VOID +UnsetVescEp( + IN UINT8 Bus, + IN UINT8 MaxSlotNum + ) +{ + UINT8 i; + + for (i =3D 0; i <=3D MaxSlotNum; ++i) + { + UnsetVesc(Bus, i, 0); + } +}// Unset_VESC_REG2_EP + +STATIC +BOOLEAN +ConfigureEP ( + IN INT8 Depth, + IN OUT UINT8 *Bus, + IN OUT PORT_INFO *PortInfo + ) +{ + UINT8 SBus; + UINT8 CioSlot; + UINT8 MaxSlotNum; + BOOLEAN ArPcie; + UINT8 MaxPHYSlots; + UINT8 UsedBusNumbers; + UINT8 cmd; + BOOLEAN CioSlotPresent; + BOOLEAN Continue; + PORT_INFO PortInfoOrg; + UINT8 CioBus; + + CioSlot =3D 4; + MaxSlotNum =3D 7; + CopyMem (&PortInfoOrg, PortInfo, sizeof (PORT_INFO)); + + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, *Bus, 0x00, = 0x00, 0); + cmd =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_COMMAND_= OFFSET); + // AR ONLY + // Endpoint on CIO slot, but not a bridge device + if (P2P_BRIDGE !=3D PciSegmentRead16 (gDeviceBaseAddress + (PCI_CLASSCOD= E_OFFSET + 1))) { + DEBUG((DEBUG_INFO, "UEP\n")); + // Check whether EP already configured by examining CMD register + if(cmd & CMD_BUS_MASTER) // Yes, no need to touch this EP + { + DEBUG((DEBUG_INFO, "BMF\n")); + return FALSE; + } + // Configure it as regular PCIe device + ConfigureSlot(*Bus, PCI_MAX_DEVICE + 1, -1, FALSE, PortInfo); + + return FALSE; + } + + // + // Based on Device ID assign Cio slot and max number of PHY slots to scan + // + CioSlotPresent =3D GetCioSlotByDevId(*Bus, &CioSlot, &MaxSlotNum, &ArP= cie); + MaxPHYSlots =3D MaxSlotNum; + // + // Check whether EP already configured by examining CMD register + // + + if (cmd & CMD_BUS_MASTER) { + // + // Yes no need to touch this EP, just move to next one in chain + // + CioBus =3D *Bus + 1; + if(ArPcie){ + UnsetVescEp(CioBus, MaxSlotNum); + } + if (!CioSlotPresent) { + // + // Cio slot is not present in EP, just return FALSE + // + DEBUG((DEBUG_INFO, "BMF\n")); + return FALSE; + } + // + // Take all resources from Cio slot and return + // + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,CioBus, Cio= Slot, 0x00, 0); + PortInfo->BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_= BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET); + PortInfo->IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFS= ET_OF (PCI_TYPE01, Bridge.IoBase)); + PortInfo->IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFS= ET_OF (PCI_TYPE01, Bridge.IoLimit)); + PortInfo->MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFF= SET_OF (PCI_TYPE01, Bridge.MemoryBase)); + PortInfo->MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFF= SET_OF (PCI_TYPE01, Bridge.MemoryLimit)); + PortInfo->PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFF= SET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0; + PortInfo->PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFF= SET_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0; + PortInfo->PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddr= ess + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16; + PortInfo->PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddr= ess + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16; + PortInfo->PMemLimit64 |=3D 0xF; + // + // Jump to next EP + // + *Bus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BU= S_REGISTER_OFFSET); + // + // Should we continue? + // + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus, 0x00,= 0x00, 0); + Continue =3D 0xFFFF !=3D PciSegmentRead16 (gDeviceBaseAddress= + PCI_DEVICE_ID_OFFSET); + return Continue; + } + // + // Set is legacy dvice + // + isLegacyDevice =3D IsLegacyDevice (*Bus); + + SetCioPortResources ( + *Bus, + 0, // Assign all available resources to US port of EP + *Bus + 1, + PortInfo->BusNumLimit, + 0, + PortInfo + ); + + SBus =3D *Bus + 1;// Jump to DS port + + if (CioSlotPresent) { + MaxPHYSlots =3D CioSlot; + } + + UsedBusNumbers =3D ConfigureSlot(SBus, MaxPHYSlots, Depth, ArPcie, PortI= nfo); + if (!CioSlotPresent) { + return FALSE; + // + // Stop resource assignment on this chain + // + } + // + // Set rest of slots us unused + // + SetSlotsAsUnused (SBus, MaxSlotNum, CioSlot, PortInfo); + + SetCioPortResources ( + SBus, + CioSlot, + SBus + UsedBusNumbers + 1, + PortInfo->BusNumLimit, + &PortInfoOrg, + PortInfo + ); + *Bus =3D SBus + UsedBusNumbers + 1;// Go to next EP + if(ArPcie) { + UnsetVesc(SBus, CioSlot, 0x00); + } + if (*Bus > PortInfo->BusNumLimit - 2) { + // + // In case of bus numbers are exhausted stop enumeration + // + return FALSE; + } + // + // Check whether we should continue on this chain + // + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,*Bus, 0x00, 0= x00, 0); + Continue =3D 0xFFFF !=3D PciSegmentRead16 (gDeviceBaseAddress += PCI_DEVICE_ID_OFFSET); + return Continue; +} // ConfigureEP + +STATIC +VOID +GetPortResources ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN OUT PORT_INFO *PortInfo + ) +{ + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun= , 0); + PortInfo->BusNumLimit =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BR= IDGE_SUBORDINATE_BUS_REGISTER_OFFSET); + PortInfo->IoBase =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.IoBase)) & 0xF0; + PortInfo->IoLimit =3D PciSegmentRead8 (gDeviceBaseAddress + OFFSET= _OF (PCI_TYPE01, Bridge.IoLimit)) & 0xF0; + PortInfo->MemBase =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE= T_OF (PCI_TYPE01, Bridge.MemoryBase)) & 0xFFF0; + PortInfo->MemLimit =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE= T_OF (PCI_TYPE01, Bridge.MemoryLimit)) & 0xFFF0; + PortInfo->PMemBase64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE= T_OF (PCI_TYPE01, Bridge.PrefetchableMemoryBase)) & 0xFFF0; + PortInfo->PMemLimit64 =3D PciSegmentRead16 (gDeviceBaseAddress + OFFSE= T_OF (PCI_TYPE01, Bridge.PrefetchableMemoryLimit)) & 0xFFF0; + PortInfo->PMemBase64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddres= s + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableBaseUpper32))) << 16; + PortInfo->PMemLimit64 |=3D (UINT64)(PciSegmentRead32 (gDeviceBaseAddres= s + OFFSET_OF (PCI_TYPE01, Bridge.PrefetchableLimitUpper32))) << 16; + PortInfo->IoLimit |=3D 0xF; + PortInfo->MemLimit |=3D 0xF; + PortInfo->PMemLimit64 |=3D 0xF; +} // GetPortResources + +STATIC +VOID +ConfigurePort ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN OUT PORT_INFO *PortInfo + ) +{ + INT8 i; + UINT8 USBusNum; + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun= , 0); + USBusNum =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE_S= ECONDARY_BUS_REGISTER_OFFSET); + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, USBusNum, 0x= 00, 0x00, 0); + if (0xFFFF =3D=3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVICE_ID_O= FFSET)) { + // + // Nothing to do if TBT device is not connected + // + return ; + } + + GetPortResources(Bus, Dev, Fun, PortInfo);// Take reserved resources fro= m DS port + // + // Assign resources to EPs + // + for (i =3D 0; i < MAX_TBT_DEPTH; ++i) { + PortInfo->ConfedEP++; + if (!ConfigureEP (i, &USBusNum, PortInfo)) { + return ; + } + } +} // ConfigurePort + +VOID +ThunderboltCallback ( + IN UINT8 Type + ) +{ + PORT_INFO PortInfoOrg =3D { 0 }; + HR_CONFIG HrConfig =3D { 0 }; + UINT8 i; + UINTN Segment =3D 0; + UINTN Bus =3D 0; + UINTN Device; + UINTN Function; + + DEBUG((DEBUG_INFO, "ThunderboltCallback.Entry\n")); + + DEBUG((DEBUG_INFO, "PortInfo Initialization\n")); + PortInfoInit (&PortInfoOrg); + if(Type =3D=3D DTBT_CONTROLLER) { + if (gCurrentDiscreteTbtRootPort =3D=3D 0) { + DEBUG((DEBUG_ERROR, "Invalid RP Input\n")); + return; + } + GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType, gCurrentDiscreteTbtRo= otPort - 1, &Device, &Function); + DEBUG((DEBUG_INFO, "InitializeHostRouter. \n")); + if (!InitializeHostRouter (&HrConfig, Segment, Bus, Device, Function))= { + return ; + } + // + // Configure DS ports + // + for (i =3D HrConfig.MinDSNumber; i <=3D HrConfig.MaxDSNumber; ++i) { + DEBUG((DEBUG_INFO, "ConfigurePort. \n")); + ConfigurePort (HrConfig.HRBus + 1, i,0, &PortInfoOrg); + } + + DEBUG((DEBUG_INFO, "EndOfThunderboltCallback.\n")); + EndOfThunderboltCallback (Segment, Bus, Device, Function); + + } + DEBUG((DEBUG_INFO, "ThunderboltCallback.Exit\n")); +} // ThunderboltCallback + +VOID +DisablePCIDevicesAndBridges ( + IN UINT8 MinBus, + IN UINT8 MaxBus + ) +{ + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 RegVal; + // + // Disable PCI device First, and then Disable PCI Bridge + // + for (Bus =3D MaxBus; Bus > MinBus; --Bus) { + for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, De= v, Fun, 0); + if (INVALID_PCI_DEVICE =3D=3D PciSegmentRead32 (gDeviceBaseAddress= + PCI_VENDOR_ID_OFFSET)) { + if (Fun =3D=3D 0) { + break; + + } + + continue; + } + + RegVal =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_HEADER_TYPE_O= FFSET); + if (HEADER_TYPE_DEVICE =3D=3D (RegVal & 1)) { + // + // ******** Disable PCI Device ******** + // BIT0 I/O Space Enabled BIT1 Memory Space Enabled + // BIT2 Bus Master Enabled BIT4 Memory Write and Invalidatio= n Enable + // + PciSegmentAnd8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, (UINT8)= ~(BIT0 | BIT1 | BIT2 | BIT4)); + PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX0 * 4), 0); + PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX1 * 4), 0); + PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX2 * 4), 0); + PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX3 * 4), 0); + PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX4 * 4), 0); + PciSegmentWrite32 (gDeviceBaseAddress + PCI_BASE_ADDRESSREG_OFFS= ET + (PCI_BAR_IDX5 * 4), 0); + } + } + } + } + // + // now no more PCI dev on another side of PCI Bridge can safty disable P= CI Bridge + // + for (Bus =3D MaxBus; Bus > MinBus; --Bus) { + for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, De= v, Fun, 0); + if (INVALID_PCI_DEVICE =3D=3D PciSegmentRead32 (gDeviceBaseAddress= + PCI_VENDOR_ID_OFFSET)) { + if (Fun =3D=3D 0) { + break; + } + + continue; + } + + RegVal =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_HEADER_TYPE_O= FFSET); + if (HEADER_TYPE_PCI_TO_PCI_BRIDGE =3D=3D (RegVal & BIT0)) { + PciSegmentAnd8 (gDeviceBaseAddress + PCI_COMMAND_OFFSET, (UINT8)= ~(BIT0 | BIT1 | BIT2 | BIT4)); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_PRIMARY_BUS_RE= GISTER_OFFSET, 0); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BU= S_REGISTER_OFFSET, 0); + PciSegmentWrite8 (gDeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_= REGISTER_OFFSET, 0); + PciSegmentWrite32 (gDeviceBaseAddress + OFFSET_OF (PCI_TYPE01, B= ridge.PrefetchableBaseUpper32), 0); + } + } // for ( Fun .. ) + } // for ( Dev ... ) + } // for ( Bus ... ) +} // DisablePCIDevicesAndBridges + +VOID +TbtDisablePCIDevicesAndBridges ( + IN UINT8 Type + ) +{ + UINTN Segment =3D 0; + UINTN Bus =3D 0; + UINTN Device; + UINTN Function; + UINT8 MinBus; + UINT8 MaxBus; + UINT16 DeviceId; + + MinBus =3D 1; + if(Type =3D=3D DTBT_CONTROLLER) { + // + // for(Dev =3D 0; Dev < 8; ++Dev) + // { + // PciOr8(PCI_LIB_ADDRESS(2, Dev, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFSE= T), 0x40); + // gBS->Stall(2000); // 2msec + // PciAnd8(PCI_LIB_ADDRESS(2, Dev, 0, PCI_BRIDGE_CONTROL_REGISTER_OFFS= ET), 0xBF); + // } + // gBS->Stall(200 * 1000); // 200 msec + // + if (gCurrentDiscreteTbtRootPort =3D=3D 0) { + DEBUG((DEBUG_ERROR, "Invalid RP Input\n")); + return; + } + GetDTbtRpDevFun(gCurrentDiscreteTbtRootPortType, gCurrentDiscreteTbtRo= otPort - 1, &Device, &Function); + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, = Function, 0); + MinBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE= _SECONDARY_BUS_REGISTER_OFFSET); + MaxBus =3D PciSegmentRead8 (gDeviceBaseAddress + PCI_BRIDGE= _SUBORDINATE_BUS_REGISTER_OFFSET); + gDeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (Segment, MinBus, 0x00,= 0x00, 0); + DeviceId =3D PciSegmentRead16 (gDeviceBaseAddress + PCI_DEVIC= E_ID_OFFSET); + if (!(IsTbtHostRouter (DeviceId))) { + return; + } + TbtSegment =3D (UINT8)Segment; + MinBus++; + // + // @todo : Move this out when we dont have Loop for ITBT + // + DisablePCIDevicesAndBridges(MinBus, MaxBus); + + } +} // DisablePCIDevicesAndBridges + + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Sm= m/TbtSmm.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Sm= m/TbtSmm.c new file mode 100644 index 0000000000..721438c718 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSm= m.c @@ -0,0 +1,1765 @@ +/** @file + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// Module specific Includes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "TbtSmiHandler.h" +#include +#include +#include +#include +#define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CL= ASS_BRIDGE_P2P)) + +#define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0) + +#define DISBL_IO_REG1C 0x01F1 +#define DISBL_MEM32_REG20 0x0000FFF0 +#define DISBL_PMEM_REG24 0x0001FFF1 + +#define DOCK_BUSSES 8 + +#define PCI_CAPABILITY_ID_PCIEXP 0x10 +#define PCI_CAPBILITY_POINTER_OFFSET 0x34 + +#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Snoop Latency can we put like this ? +#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Non-Snoop Latency can we put like this ? + + +GLOBAL_REMOVE_IF_UNREFERENCED TBT_NVS_AREA *mTbtNvsAreaPtr; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscrete= TbtRootPort; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gCurrentDiscrete= TbtRootPortType; +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxSnoopLa= tency; +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 TbtLtrMaxNoSnoop= Latency; +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 gDTbtPcieRstSupp= ort; +GLOBAL_REMOVE_IF_UNREFERENCED TBT_INFO_HOB *gTbtInfoHob =3D= NULL; +STATIC UINTN mPciExpressBaseA= ddress; +STATIC UINT8 TbtSegment =3D 0; +VOID +GpioWrite ( + IN UINT32 GpioNumber, + IN BOOLEAN Value + ) +{ + GpioSetOutputValue (GpioNumber, (UINT32)Value); +} + +/** + Search and return the offset of desired Pci Express Capability ID + CAPID list: + 0x0001 =3D Advanced Error Reporting Capability + 0x0002 =3D Virtual Channel Capability + 0x0003 =3D Device Serial Number Capability + 0x0004 =3D Power Budgeting Capability + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId Extended CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT16 +PcieFindExtendedCapId ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT16 CapId + ) +{ + UINT16 CapHeaderOffset; + UINT16 CapHeaderId; + UINT64 DeviceBase; + + DeviceBase =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Functio= n, 0); + + /// + /// Start to search at Offset 0x100 + /// Get Capability Header, A pointer value of 00h is used to indicate th= e last capability in the list. + /// + CapHeaderId =3D 0; + CapHeaderOffset =3D 0x100; + while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D 0xFFFF) { + CapHeaderId =3D PciSegmentRead16 (DeviceBase + CapHeaderOffset); + if (CapHeaderId =3D=3D CapId) { + return CapHeaderOffset; + } + /// + /// Each capability must be DWORD aligned. + /// The bottom two bits of all pointers are reserved and must be imple= mented as 00b + /// although software must mask them to allow for future uses of these= bits. + /// + CapHeaderOffset =3D (PciSegmentRead16 (DeviceBase + CapHeaderOffset + = 2) >> 4) & ((UINT16) ~(BIT0 | BIT1)); + } + + return 0; +} + +/** + Find the Offset to a given Capabilities ID + CAPID list: + 0x01 =3D PCI Power Management Interface + 0x04 =3D Slot Identification + 0x05 =3D MSI Capability + 0x10 =3D PCI Express Capability + + @param[in] Bus Pci Bus Number + @param[in] Device Pci Device Number + @param[in] Function Pci Function Number + @param[in] CapId CAPID to search for + + @retval 0 CAPID not found + @retval Other CAPID found, Offset of desired CAPID +**/ +UINT8 +PcieFindCapId ( + IN UINT8 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 CapId + ) +{ + UINT8 CapHeaderOffset; + UINT8 CapHeaderId; + UINT64 DeviceBase; + + DeviceBase =3D PCI_SEGMENT_LIB_ADDRESS (Segment, Bus, Device, Function, = 0); + + if ((PciSegmentRead8 (DeviceBase + PCI_PRIMARY_STATUS_OFFSET) & EFI_PCI_= STATUS_CAPABILITY) =3D=3D 0x00) { + /// + /// Function has no capability pointer + /// + return 0; + } + + /// + /// Check the header layout to determine the Offset of Capabilities Poin= ter Register + /// + if ((PciSegmentRead8 (DeviceBase + PCI_HEADER_TYPE_OFFSET) & HEADER_LAYO= UT_CODE) =3D=3D (HEADER_TYPE_CARDBUS_BRIDGE)) { + /// + /// If CardBus bridge, start at Offset 0x14 + /// + CapHeaderOffset =3D 0x14; + } else { + /// + /// Otherwise, start at Offset 0x34 + /// + CapHeaderOffset =3D 0x34; + } + /// + /// Get Capability Header, A pointer value of 00h is used to indicate th= e last capability in the list. + /// + CapHeaderId =3D 0; + CapHeaderOffset =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset) & ((U= INT8) ~(BIT0 | BIT1)); + while (CapHeaderOffset !=3D 0 && CapHeaderId !=3D 0xFF) { + CapHeaderId =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset); + if (CapHeaderId =3D=3D CapId) { + return CapHeaderOffset; + } + /// + /// Each capability must be DWORD aligned. + /// The bottom two bits of all pointers (including the initial pointer= at 34h) are reserved + /// and must be implemented as 00b although software must mask them to= allow for future uses of these bits. + /// + CapHeaderOffset =3D PciSegmentRead8 (DeviceBase + CapHeaderOffset + 1)= & ((UINT8) ~(BIT0 | BIT1)); + } + + return 0; +} +/** + This function configures the L1 Substates. + It can be used for Rootport and endpoint devices. + + @param[in] DownstreamPort Indicates if the device about to= be programmed is a downstream port + @param[in] DeviceBase Device PCI configuration base ad= dress + @param[in] L1SubstateExtCapOffset Pointer to L1 Substate Capabilit= y Structure + @param[in] PortL1SubstateCapSupport L1 Substate capability setting + @param[in] PortCommonModeRestoreTime Common Mode Restore Time + @param[in] PortTpowerOnValue Tpower_on Power On Wait Time + @param[in] PortTpowerOnScale Tpower-on Scale + + @retval none +**/ +VOID +ConfigureL1s ( + IN UINTN DeviceBase, + IN UINT16 L1SubstateExtCapOffset, + IN UINT32 PortL1SubstateCapSupport, + IN UINT32 PortCommonModeRestoreTime, + IN UINT32 PortTpowerOnValue, + IN UINT32 PortTpowerOnScale, + IN UINT16 MaxLevel + ) +{ + + PciSegmentAndThenOr32 ( + DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, + (UINT32) ~(0xFF00), + (UINT32) PortCommonModeRestoreTime << 8 + ); + + PciSegmentAnd32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_= OFFSET, 0xFFFFFF04); + + PciSegmentOr32(DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL2_O= FFSET,(UINT32) ((PortTpowerOnValue << N_PCIE_EX_L1SCTL2_POWT) | PortTpowerO= nScale)); + + PciSegmentAndThenOr32 ( + DeviceBase + L1SubstateExtCapOffset + R_PCIE_EX_L1SCTL1_OFFSET, + (UINT32) ~(0xE3FF0000), + (UINT32) (BIT30 | BIT23 | BIT21) + ); + +} + +VOID +RootportL1sSupport ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 RootL1SubstateExtCapOffset, + IN UINT16 MaxL1Level + ) +{ + UINTN ComponentABaseAddress; + UINTN ComponentBBaseAddress; + UINT8 SecBus; + UINT32 PortL1SubstateCapSupport; + UINT32 PortCommonModeRestoreTime; + UINT32 PortTpowerOnValue; + UINT32 PortTpowerOnScale; + UINT16 ComponentBL1SubstateExtCapOffset; + UINT32 ComponentBL1Substates; + UINT32 ComponentBCommonModeRestoreTime; + UINT32 ComponentBTpowerOnValue; + UINT32 ComponentBTpowerOnScale; + UINT32 Data32; + + PortL1SubstateCapSupport =3D 0; + PortCommonModeRestoreTime =3D 0; + PortTpowerOnValue =3D 0; + PortTpowerOnScale =3D 0; + Data32 =3D 0; + + ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev= , Fun, 0); + if (RootL1SubstateExtCapOffset !=3D 0) { + Data32 =3D PciSegmentRead32 (ComponentABaseAddress + RootL1SubstateExt= CapOffset + R_PCIE_EX_L1SCAP_OFFSET); + PortL1SubstateCapSupport =3D (Data32) & 0x0F; + PortCommonModeRestoreTime =3D (Data32 >> 8) & 0xFF; + PortTpowerOnScale =3D (Data32 >> 16) & 0x3; + PortTpowerOnValue =3D (Data32 >> 19) & 0x1F; + } else { + MaxL1Level =3D 0; // If L1 Substates from Root Port sid= e is disable, then Disable from Device side also. + } + + SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B= RIDGE_SECONDARY_BUS_REGISTER_OFFSET); + ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0= , 0, 0); + + if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) =3D= =3D 0xFFFF) { + ComponentBL1SubstateExtCapOffset =3D PcieFindExtendedCapId ( + SecBus, + 0, + 0, + V_PCIE_EX_L1S_CID + ); + if (ComponentBL1SubstateExtCapOffset !=3D 0) { + ComponentBL1Substates =3D PciSegmentRead32 (ComponentBBaseAddress + = ComponentBL1SubstateExtCapOffset + R_PCIE_EX_L1SCAP_OFFSET); + ComponentBCommonModeRestoreTime =3D (ComponentBL1Substates >> 8) & 0= xFF; + ComponentBTpowerOnScale =3D (ComponentBL1Substates >> 16) & = 0x3; + ComponentBTpowerOnValue =3D (ComponentBL1Substates >> 19) & = 0x1F; + + if (MaxL1Level =3D=3D 3) { + if (Data32 >=3D ComponentBL1Substates) { + if (~(Data32 | BIT2)) { + MaxL1Level =3D 1; + } + } + else { + if (~(ComponentBL1Substates | BIT2)) { + MaxL1Level =3D 1; + } + } + } + + if (MaxL1Level =3D=3D 3) { + ConfigureL1s ( + ComponentABaseAddress, + RootL1SubstateExtCapOffset, + PortL1SubstateCapSupport, + ComponentBCommonModeRestoreTime, + ComponentBTpowerOnValue, + ComponentBTpowerOnScale, + MaxL1Level + ); + + ConfigureL1s ( + ComponentBBaseAddress, + ComponentBL1SubstateExtCapOffset, + ComponentBL1Substates, + PortCommonModeRestoreTime, + PortTpowerOnValue, + PortTpowerOnScale, + MaxL1Level + ); + } + + if (MaxL1Level =3D=3D 1) { + PciSegmentOr32 ( + ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX_L= 1SCTL1_OFFSET, + (UINT32) (BIT3 | BIT1) + ); + + PciSegmentOr32 ( + ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_PCI= E_EX_L1SCTL1_OFFSET, + (UINT32) (BIT3 | BIT1) + ); + } + else { + if (RootL1SubstateExtCapOffset !=3D 0) { + PciSegmentOr32 ( + ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX= _L1SCTL1_OFFSET, + (UINT32) (BIT3 | BIT1) + ); + + PciSegmentOr32 ( + ComponentABaseAddress + RootL1SubstateExtCapOffset + R_PCIE_EX= _L1SCTL1_OFFSET, + (UINT32) (BIT2 | BIT0) + ); + } + if (ComponentBL1SubstateExtCapOffset !=3D 0) { + PciSegmentOr32 ( + ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_P= CIE_EX_L1SCTL1_OFFSET, + (UINT32) (BIT3 | BIT1) + ); + + PciSegmentOr32 ( + ComponentBBaseAddress + ComponentBL1SubstateExtCapOffset + R_P= CIE_EX_L1SCTL1_OFFSET, + (UINT32) (BIT2 | BIT0) + ); + } + } + } + } +} + +VOID +MultiFunctionDeviceAspm ( + IN UINT8 Bus, + IN UINT8 Dev + ) +{ + UINT16 LowerAspm; + UINT16 AspmVal; + UINT8 Fun; + UINT64 DeviceBaseAddress; + UINT8 CapHeaderOffset; + + LowerAspm =3D 3; // L0s and L1 Supported + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + // + // Check for Device availability + // + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, F= un, 0); + if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=3D= 0xFFFF) { + // Device not present + continue; + } + + CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); + + AspmVal =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0= x00C) >> 10) & 3; + if (LowerAspm > AspmVal) { + LowerAspm =3D AspmVal; + } + } //Fun + + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + // + // Check for Device availability + // + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, F= un, 0); + if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D=3D= 0xFFFF) { + // + // Device not present + // + continue; + } + + CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); + + PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xF= FFC, LowerAspm); + } //Fun +} + +UINT16 +LimitAspmLevel ( + IN UINT16 SelectedAspm, + IN UINT16 MaxAspmLevel + ) +{ + SelectedAspm =3D SelectedAspm & MaxAspmLevel; + + return SelectedAspm; +} + +UINT16 +FindOptimalAspm ( + IN UINT16 ComponentAaspm, + IN UINT16 ComponentBaspm + ) +{ + UINT16 SelectedAspm; + + SelectedAspm =3D ComponentAaspm & ComponentBaspm; + + return SelectedAspm; +} + +UINT16 +FindComponentBaspm ( + IN UINT8 Bus, + IN UINT8 MaxBus + ) +{ + UINT8 BusNo; + UINT8 DevNo; + UINT8 FunNo; + UINT64 DevBaseAddress; + UINT8 RegVal; + UINT8 SecBusNo; + UINT16 SelectedAspm; // No ASPM Support + UINT8 CapHeaderOffset_B; + BOOLEAN AspmFound; + + SelectedAspm =3D 0; + AspmFound =3D FALSE; + + for (BusNo =3D MaxBus; (BusNo !=3D 0xFF) && (!AspmFound); --BusNo) { + for (DevNo =3D 0; (DevNo <=3D PCI_MAX_DEVICE) && (!AspmFound); ++DevNo= ) { + for (FunNo =3D 0; (FunNo <=3D PCI_MAX_FUNC) && (!AspmFound); ++FunNo= ) { + // + // Check for Device availability + // + DevBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, BusNo, Dev= No, FunNo, 0); + if (PciSegmentRead16 (DevBaseAddress + PCI_DEVICE_ID_OFFSET) =3D= =3D 0xFFFF) { + // + // Device not present + // + continue; + } + + RegVal =3D PciSegmentRead8 (DevBaseAddress + PCI_HEADER_TYPE_OFFSE= T); + if ((RegVal & (BIT0 + BIT1 + BIT2 + BIT3 + BIT4 + BIT5 + BIT6)) != =3D 0x01) { + // + // Not a PCI-to-PCI bridges device + // + continue; + } + + SecBusNo =3D PciSegmentRead8 (DevBaseAddress + PCI_BRIDGE_SECONDAR= Y_BUS_REGISTER_OFFSET); + + if (SecBusNo =3D=3D Bus) { + // + // This is the Rootbridge for the given 'Bus' device + // + CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, BusNo, DevNo, F= unNo, 0x10); + SelectedAspm =3D (PciSegmentRead16 (DevBaseAddress + CapHea= derOffset_B + 0x00C) >> 10) & 3; + AspmFound =3D TRUE; + } + } //FunNo + } //DevNo + } //BusNo + + return (SelectedAspm); +} + +VOID +NoAspmSupport ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT8 CapHeaderOffset + ) +{ + UINT64 DeviceBaseAddress; + + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun= , 0); + PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF= C, 0x00); +} + +VOID +EndpointAspmSupport ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT8 CapHeaderOffset, + IN UINT8 MaxBus, + IN UINT16 MaxAspmLevel + ) +{ + UINT64 DeviceBaseAddress; + UINT16 ComponentAaspm; + UINT16 ComponentBaspm; + UINT16 SelectedAspm; + + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun= , 0); + ComponentAaspm =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOf= fset + 0x00C) >> 10) & 3; + ComponentBaspm =3D FindComponentBaspm (Bus, MaxBus); + SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm); + SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel); + PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF= C, SelectedAspm); +} + +VOID +UpstreamAspmSupport ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT8 CapHeaderOffset, + IN UINT8 MaxBus, + IN UINT16 MaxAspmLevel + ) +{ + UINT64 DeviceBaseAddress; + UINT16 ComponentAaspm; + UINT16 ComponentBaspm; + UINT16 SelectedAspm; + + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun= , 0); + ComponentAaspm =3D (PciSegmentRead16 (DeviceBaseAddress + CapHeaderOf= fset + 0x00C) >> 10) & 3; + ComponentBaspm =3D FindComponentBaspm (Bus, MaxBus); + SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm); + SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel); + PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10, 0xFFF= C, SelectedAspm); +} + +VOID +DownstreamAspmSupport ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT8 CapHeaderOffset, + IN UINT16 MaxAspmLevel + ) +{ + UINT64 ComponentABaseAddress; + UINT64 ComponentBBaseAddress; + UINT16 ComponentAaspm; + UINT16 ComponentBaspm; + UINT16 SelectedAspm; + UINT8 SecBus; + UINT8 CapHeaderOffset_B; + + ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,= Fun, 0); + ComponentAaspm =3D (PciSegmentRead16 (ComponentABaseAddress + Cap= HeaderOffset + 0x00C) >> 10) & 3; + + SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B= RIDGE_SECONDARY_BUS_REGISTER_OFFSET); + ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0= , 0, 0); + ComponentBaspm =3D 0; // No ASPM Support + if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) !=3D= 0xFFFF) { + CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); + ComponentBaspm =3D (PciSegmentRead16 (ComponentBBaseAddress + CapHe= aderOffset_B + 0x00C) >> 10) & 3; + } + + SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm); + SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel); + PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0= xFFFC, SelectedAspm); +} + +VOID +RootportAspmSupport ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT8 CapHeaderOffset, + IN UINT16 MaxAspmLevel + ) +{ + UINT64 ComponentABaseAddress; + UINT64 ComponentBBaseAddress; + UINT16 ComponentAaspm; + UINT16 ComponentBaspm; + UINT16 SelectedAspm; + UINT8 SecBus; + UINT8 CapHeaderOffset_B; + + ComponentABaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,= Fun, 0); + ComponentAaspm =3D (PciSegmentRead16 (ComponentABaseAddress + Cap= HeaderOffset + 0x00C) >> 10) & 3; + + SecBus =3D PciSegmentRead8 (ComponentABaseAddress + PCI_B= RIDGE_SECONDARY_BUS_REGISTER_OFFSET); + ComponentBBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, SecBus, 0= , 0, 0); + ComponentBaspm =3D 0; // No ASPM Support + if (PciSegmentRead16 (ComponentBBaseAddress + PCI_DEVICE_ID_OFFSET) !=3D= 0xFFFF) { + CapHeaderOffset_B =3D PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); + ComponentBaspm =3D (PciSegmentRead16 (ComponentBBaseAddress + CapHe= aderOffset_B + 0x00C) >> 10) & 3; + } + + SelectedAspm =3D FindOptimalAspm (ComponentAaspm, ComponentBaspm); + SelectedAspm =3D LimitAspmLevel (SelectedAspm, MaxAspmLevel); + PciSegmentAndThenOr16 (ComponentABaseAddress + CapHeaderOffset + 0x10, 0= xFFFC, SelectedAspm); +} + +VOID +ThunderboltEnableAspmWithoutLtr ( + IN UINT16 MaxAspmLevel, + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction + ) +{ + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 RootBus; + UINT8 RootDev; + UINT8 RootFun; + UINT8 MinBus; + UINT8 MaxBus; + UINT16 DeviceId; + UINT64 DeviceBaseAddress; + UINT8 RegVal; + UINT8 CapHeaderOffset; + UINT16 DevicePortType; + + MinBus =3D 0; + MaxBus =3D 0; + + MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); + MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); + if (!(IsTbtHostRouter (DeviceId))) { + return; + } + + TbtSegment =3D (UINT8)RpSegment; + + RootBus =3D (UINT8)RpBus; + RootDev =3D (UINT8)RpDevice; + RootFun =3D (UINT8)RpFunction; + + // + // Enumerate all the bridges and devices which are available on TBT hos= t controller + // + for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { + for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { + // + // Check for Device availability + // + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev,= 0, 0); + if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) =3D= =3D 0xFFFF) { + // + // Device not present + // + continue; + } + + RegVal =3D PciSegmentRead8 (DeviceBaseAddress + PCI_HEADER_TYPE_OFFS= ET); + if ((RegVal & BIT7) =3D=3D 0) { + // + // Not a multi-function device + // + continue; + } + + MultiFunctionDeviceAspm(Bus, Dev); + } //Dev + } //Bus + + + for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { + for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + // + // Check for Device availability + // + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); + if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { + // + // Device not present + // + continue; + } + + CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10= ); + DevicePortType =3D (PciSegmentRead16 (DeviceBaseAddress + CapHead= erOffset + 0x002) >> 4) & 0xF; + if(PciSegmentRead8 (DeviceBaseAddress + PCI_CLASSCODE_OFFSET) =3D= =3D PCI_CLASS_SERIAL) { + MaxAspmLevel =3D (UINT16) 0x1; + } + + switch (DevicePortType) { + case 0: + // + // PCI Express Endpoint + // + EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); + break; + + case 1: + // + // Legacy PCI Express Endpoint + // + EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); + break; + + case 4: + // + // Root Port of PCI Express Root Complex + // + RootportAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLeve= l); + break; + + case 5: + // + // Upstream Port of PCI Express Switch + // + UpstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); + break; + + case 6: + // + // Downstream Port of PCI Express Switch + // + DownstreamAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxAspmLe= vel); + break; + + case 7: + // + // PCI Express to PCI/PCI-X Bridge + // + NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset); + break; + + case 8: + // + // PCI/PCI-X to PCI Express Bridge + // + NoAspmSupport (Bus, Dev, Fun, CapHeaderOffset); + break; + + case 9: + // + // Root Complex Integrated Endpoint + // + EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); + break; + + case 10: + // + // Root Complex Event Collector + // + EndpointAspmSupport (Bus, Dev, Fun, CapHeaderOffset, MaxBus, Max= AspmLevel); + break; + + default: + break; + } + // + // switch(DevicePortType) + // + } + // + // Fun + // + } + // + // Dev + // + } + // + // Bus + // + CapHeaderOffset =3D PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun= , 0x10); + RootportAspmSupport (RootBus, RootDev, RootFun, CapHeaderOffset, MaxAspm= Level); +} + + + +VOID +ThunderboltEnableL1Sub ( + IN UINT16 MaxL1Level, + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction + ) +{ + UINT16 CapHeaderOffsetExtd; + + RpBus =3D 0; + + CapHeaderOffsetExtd =3D PcieFindExtendedCapId ((UINT8) RpBus, (UINT8) Rp= Device, (UINT8) RpFunction, V_PCIE_EX_L1S_CID); + RootportL1sSupport ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction,= CapHeaderOffsetExtd, MaxL1Level); +} + +VOID +ThunderboltDisableAspmWithoutLtr ( + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction + ) +{ + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 RootBus; + UINT8 RootDev; + UINT8 RootFun; + UINT8 MinBus; + UINT8 MaxBus; + UINT16 DeviceId; + UINT64 DeviceBaseAddress; + UINT8 CapHeaderOffset; + + MinBus =3D 0; + MaxBus =3D 0; + + MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); + MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); + if (!(IsTbtHostRouter (DeviceId))) { + return; + } + + TbtSegment =3D (UINT8)RpSegment; + RootBus =3D (UINT8)RpBus; + RootDev =3D (UINT8)RpDevice; + RootFun =3D (UINT8)RpFunction; + + // + // Enumerate all the bridges and devices which are available on TBT hos= t controller + // + for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { + for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + // + // Check for Device availability + // + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); + if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { + // + // Device not present + // + continue; + } + + CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10= ); + PciSegmentAndThenOr16 (DeviceBaseAddress + CapHeaderOffset + 0x10,= 0xFFFC, 0x00); + } //Fun + } //Dev + } //Bus + + CapHeaderOffset =3D PcieFindCapId (TbtSegment, RootBus, RootDev, RootFun= , 0x10); + NoAspmSupport(RootBus, RootDev, RootFun, CapHeaderOffset); +} + +VOID +TbtProgramClkReq ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 ClkReqSetup + ) +{ + UINT64 DeviceBaseAddress; + UINT8 CapHeaderOffset; + UINT16 Data16; + + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, = Function, 0); + CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Device, Function, = 0x10); + + // + // Check if CLKREQ# is supported + // + if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x0C) & BIT= 18) !=3D 0) { + Data16 =3D PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x0= 10); + + if (ClkReqSetup) { + Data16 =3D Data16 | BIT8; // Enable Clock Power Management + } else { + Data16 =3D Data16 & (UINT16)(~BIT8); // Disable Clock Power Managem= ent + } + + PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x010, Data16= ); + } +} +VOID +TbtProgramPtm( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 PtmSetup, + IN BOOLEAN IsRoot +) +{ + UINT64 DeviceBaseAddress; + UINT16 CapHeaderOffset; + UINT16 PtmControlRegister; + UINT16 PtmCapabilityRegister; + + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS(TbtSegment, Bus, Device, = Function, 0); + CapHeaderOffset =3D PcieFindExtendedCapId(Bus, Device, Function, 0x001F= /*V_PCIE_EX_PTM_CID*/); + if(CapHeaderOffset !=3D 0) { + PtmCapabilityRegister =3D PciSegmentRead16(DeviceBaseAddress + CapHe= aderOffset + 0x04); + // + // Check if PTM Requester/ Responder capability for the EP/Down strea= m etc + // + if ((PtmCapabilityRegister & (BIT1 | BIT0)) !=3D 0) { + PtmControlRegister =3D PciSegmentRead16(DeviceBaseAddress + CapHea= derOffset + 0x08); + + if (PtmSetup) { + PtmControlRegister =3D PtmControlRegister | BIT0; // Enable PTM + if(IsRoot) { + PtmControlRegister =3D PtmControlRegister | BIT1; // Enable P= TM + } + PtmControlRegister =3D PtmControlRegister | (PtmCapabilityRegis= ter & 0xFF00); // Programm Local Clock Granularity + } else { + PtmControlRegister =3D PtmControlRegister & (UINT16)(~(BIT0 | B= IT1)); // Disable Clock Power Management + } + + PciSegmentWrite16(DeviceBaseAddress + CapHeaderOffset + 0x08, PtmC= ontrolRegister); + } + } +} + +VOID +ConfigureTbtPm ( + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction, + IN UINT8 Configuration // 1- Clk Request , 2- PTM , + ) +{ + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 MinBus; + UINT8 MaxBus; + UINT16 DeviceId; + UINT64 DeviceBaseAddress; + + MinBus =3D 0; + MaxBus =3D 0; + + if ((Configuration !=3D 1) && (Configuration !=3D 2)) { + return; + } + MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); + MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); + if (!(IsTbtHostRouter (DeviceId))) { + return; + } + + TbtSegment =3D (UINT8)RpSegment; + // + // Enumerate all the bridges and devices which are available on TBT hos= t controller + // + for (Bus =3D MaxBus; Bus >=3D MinBus; --Bus) { + for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + // + // Check for Device availability + // + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); + if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { + if (Fun =3D=3D 0) { + // + // IF Fun is zero, stop enumerating other functions of the par= ticular bridge + // + break; + } + // + // otherwise, just skip checking for CLKREQ support + // + continue; + } + switch (Configuration) { + case 1: + TbtProgramClkReq (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtSe= tClkReq); + break; + case 2: + TbtProgramPtm (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtPtm, = FALSE); + TbtProgramPtm((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunct= ion, (UINT8) mTbtNvsAreaPtr->TbtPtm, TRUE); + break; + default: + break; + } + } //Fun + } // Dev + } // Bus +} + +/** + 1) Check LTR support in device capabilities 2 register (bit 11). + 2) If supported enable LTR in device control 2 register (bit 10). + +**/ +VOID +TbtProgramLtr ( + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function, + IN UINT8 LtrSetup + ) +{ + UINT64 DeviceBaseAddress; + UINT8 CapHeaderOffset; + UINT16 Data16; + + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, = Function, 0); + CapHeaderOffset =3D PcieFindCapId (TbtSegment, Bus, Device, Function, = 0x10); + + // + // Check if LTR# is supported + // + if ((PciSegmentRead32 (DeviceBaseAddress + CapHeaderOffset + 0x24) & BIT= 11) !=3D 0) { + Data16 =3D PciSegmentRead16 (DeviceBaseAddress + CapHeaderOffset + 0x0= 28); + + if (LtrSetup) { + Data16 =3D Data16 | BIT10; // LTR Mechanism Enable + } else { + Data16 =3D Data16 & (UINT16)(~BIT10); // LTR Mechanism Disable + } + + PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffset + 0x028, Data16= ); + } +} + +VOID +ConfigureLtr ( + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction + ) +{ + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 MinBus; + UINT8 MaxBus; + UINT16 DeviceId; + UINT64 DeviceBaseAddress; + + MinBus =3D 0; + MaxBus =3D 0; + + MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); + MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); + if (!(IsTbtHostRouter (DeviceId))) { + return; + } + + TbtSegment =3D (UINT8)RpSegment; + // + // Enumerate all the bridges and devices which are available on TBT hos= t controller + // + for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { + for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + // + // Check for Device availability + // + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); + if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { + if (Fun =3D=3D 0) { + // + // IF Fun is zero, stop enumerating other functions of the par= ticular bridge + // + break; + } + // + // otherwise, just skip checking for LTR support + // + continue; + } + + TbtProgramLtr (Bus, Dev, Fun, (UINT8) mTbtNvsAreaPtr->TbtLtr); + + } //Fun + } // Dev + } // Bus + TbtProgramLtr ((UINT8) RpBus, (UINT8) RpDevice, (UINT8) RpFunction, (UIN= T8) mTbtNvsAreaPtr->TbtLtr); +} + +/* + US ports and endpoints which declare support must also have the LTR capa= bility structure (cap ID 18h). + In this structure you need to enter the max snoop latency and max non-sn= oop latency in accordance with the format specified in the PCIe spec. + The latency value itself is platform specific so you'll need to get it f= rom the platform architect or whatever. +*/ +VOID +ThunderboltGetLatencyLtr ( + VOID + ) +{ + PCH_SERIES PchSeries; + + PchSeries =3D GetPchSeries (); + + if(gCurrentDiscreteTbtRootPortType =3D=3D DTBT_TYPE_PEG) { + // PEG selector + TbtLtrMaxSnoopLatency =3D LTR_MAX_SNOOP_LATENCY_VALUE; + TbtLtrMaxNoSnoopLatency =3D LTR_MAX_NON_SNOOP_LATENCY_VALUE; + } else if (gCurrentDiscreteTbtRootPortType =3D=3D DTBT_TYPE_PCH) { + // PCH selector + + if (PchSeries =3D=3D PchLp) { + TbtLtrMaxSnoopLatency =3D 0x1003; + TbtLtrMaxNoSnoopLatency =3D 0x1003; + } + if (PchSeries =3D=3D PchH) { + TbtLtrMaxSnoopLatency =3D 0x0846; + TbtLtrMaxNoSnoopLatency =3D 0x0846; + } + } +} + +VOID +SetLatencyLtr ( + IN UINT8 Bus, + IN UINT8 Dev, + IN UINT8 Fun, + IN UINT16 CapHeaderOffsetExtd, + IN UINT16 LtrMaxSnoopLatency, + IN UINT16 LtrMaxNoSnoopLatency + ) +{ + UINT64 DeviceBaseAddress; + if(CapHeaderOffsetExtd =3D=3D 0) { + return; + } + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun= , 0); + PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x004, LtrM= axSnoopLatency); + PciSegmentWrite16 (DeviceBaseAddress + CapHeaderOffsetExtd + 0x006, LtrM= axNoSnoopLatency); +} + +VOID +ThunderboltSetLatencyLtr ( + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction + ) +{ + UINT8 Bus; + UINT8 Dev; + UINT8 Fun; + UINT8 MinBus; + UINT8 MaxBus; + UINT16 DeviceId; + UINT64 DeviceBaseAddress; + UINT8 CapHeaderOffsetStd; + UINT16 CapHeaderOffsetExtd; + UINT16 DevicePortType; + + MinBus =3D 0; + MaxBus =3D 0; + + MinBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); + MaxBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, RpBus= , RpDevice, RpFunction, PCI_BRIDGE_SUBORDINATE_BUS_REGISTER_OFFSET)); + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (RpSegment, MinB= us, 0x00, 0x00, PCI_DEVICE_ID_OFFSET)); + if (!(IsTbtHostRouter (DeviceId))) { + return; + } + + TbtSegment =3D (UINT8)RpSegment; + + for (Bus =3D MinBus; Bus <=3D MaxBus; ++Bus) { + for (Dev =3D 0; Dev <=3D PCI_MAX_DEVICE; ++Dev) { + for (Fun =3D 0; Fun <=3D PCI_MAX_FUNC; ++Fun) { + // + // Check for Device availability + // + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, De= v, Fun, 0); + if (PciSegmentRead16 (DeviceBaseAddress + PCI_DEVICE_ID_OFFSET) = =3D=3D 0xFFFF) { + // + // Device not present + // + continue; + } + + CapHeaderOffsetStd =3D PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0= x10); + DevicePortType =3D (PciSegmentRead16 (DeviceBaseAddress + CapHead= erOffsetStd + 0x002) >> 4) & 0xF; + + CapHeaderOffsetExtd =3D PcieFindExtendedCapId (Bus, Dev, Fun, 0x00= 18); + + switch (DevicePortType) { + case 0: + // + // PCI Express Endpoint + // + SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo= pLatency, TbtLtrMaxNoSnoopLatency); + break; + + case 1: + // + // Legacy PCI Express Endpoint + // + SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo= pLatency, TbtLtrMaxNoSnoopLatency); + break; + + case 4: + // + // Root Port of PCI Express Root Complex + // + // Do-nothing + break; + + case 5: + // + // Upstream Port of PCI Express Switch + // + SetLatencyLtr (Bus, Dev, Fun, CapHeaderOffsetExtd, TbtLtrMaxSnoo= pLatency, TbtLtrMaxNoSnoopLatency); + break; + + case 6: + // + // Downstream Port of PCI Express Switch + // + // Do-nothing + break; + + case 7: + // + // PCI Express to PCI/PCI-X Bridge + // + // Do-nothing + break; + + case 8: + // + // PCI/PCI-X to PCI Express Bridge + // + // Do-nothing + break; + + case 9: + // + // Root Complex Integrated Endpoint + // + // Do-nothing + break; + + case 10: + // + // Root Complex Event Collector + // + // Do-nothing + break; + + default: + break; + } + // + // switch(DevicePortType) + // + } + // + // Fun + // + } + // + // Dev + // + } + // + // Bus + // +} + +static +VOID +Stall ( + UINTN Usec + ) +{ + UINTN Index; + UINT32 Data32; + UINT32 PrevData; + UINTN Counter; + + Counter =3D (UINTN) ((Usec * 10) / 3); + // + // Call WaitForTick for Counter + 1 ticks to try to guarantee Counter ti= ck + // periods, thus attempting to ensure Microseconds of stall time. + // + if (Counter !=3D 0) { + + PrevData =3D IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_= TMR); + for (Index =3D 0; Index < Counter;) { + Data32 =3D IoRead32 (PcdGet16 (PcdAcpiBaseAddress) + R_PCH_ACPI_PM1_= TMR); + if (Data32 < PrevData) { + // + // Reset if there is a overlap + // + PrevData =3D Data32; + continue; + } + + Index +=3D (Data32 - PrevData); + PrevData =3D Data32; + } + } + + return ; +} +/** + Called during Sx entry, initates TbtSetPcie2TbtCommand HandShake to set = GO2SX_NO_WAKE + for Tbt devices if WakeupSupport is not present. + + @param[in] DispatchHandle - The unique handle assigned to this h= andler by SmiHandlerRegister(). + @param[in] DispatchContext - Points to an optional handler contex= t which was specified when the + handler was registered. + @param[in, out] CommBuffer - A pointer to a collection of data in= memory that will + be conveyed from a non-SMM environme= nt into an SMM environment. + @param[in, out] CommBufferSize - The size of the CommBuffer. + + @retval EFI_SUCCESS - The interrupt was handled successful= ly. +**/ +EFI_STATUS +EFIAPI +SxDTbtEntryCallback ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer OPTIONAL, + IN UINTN *CommBufferSize OPTIONAL + ) +{ + UINT16 DeviceId; + UINT8 CableConnected; + UINT8 RootportSelected; + UINT8 HoustRouteBus; + volatile UINT32 *PowerState; + UINT32 PowerStatePrev; + BOOLEAN SecSubBusAssigned; + UINT64 DeviceBaseAddress; + UINT8 CapHeaderOffset; + UINTN RpDev; + UINTN RpFunc; + EFI_STATUS Status; + UINT32 Timeout; + UINT32 RegisterValue; + UINT64 Tbt2Pcie; + UINTN Index; + UINT32 TbtCioPlugEventGpioNo; + UINT32 TbtFrcPwrGpioNo; + UINT8 TbtFrcPwrGpioLevel; + UINT32 TbtPcieRstGpioNo; + UINT8 TbtPcieRstGpioLevel; + EFI_SMM_SX_REGISTER_CONTEXT *EntryDispatchContext; + + CableConnected =3D 0; + HoustRouteBus =3D 3; + SecSubBusAssigned =3D FALSE; + Timeout =3D 600; + RootportSelected =3D 0; + TbtCioPlugEventGpioNo =3D 0; + TbtFrcPwrGpioNo =3D 0; + TbtFrcPwrGpioLevel =3D 0; + TbtPcieRstGpioNo =3D 0; + TbtPcieRstGpioLevel =3D 0; + Index =3D 0; + + EntryDispatchContext =3D (EFI_SMM_SX_REGISTER_CONTEXT*) DispatchContext; + +// CableConnected =3D GetTbtHostRouterStatus (); + //SaveTbtHostRouterStatus (CableConnected & 0xF0); + // + // Get the Power State and Save + // + if (((mTbtNvsAreaPtr->DTbtControllerEn0 =3D=3D 0) && (Index =3D=3D 0))) = { + + RootportSelected =3D mTbtNvsAreaPtr->RootportSelected0; + TbtCioPlugEventGpioNo =3D mTbtNvsAreaPtr->TbtCioPlugEventGpioNo0; + TbtFrcPwrGpioNo =3D mTbtNvsAreaPtr->TbtFrcPwrGpioNo0; + TbtFrcPwrGpioLevel =3D mTbtNvsAreaPtr->TbtFrcPwrGpioLevel0; + TbtPcieRstGpioNo =3D mTbtNvsAreaPtr->TbtPcieRstGpioNo0; + TbtPcieRstGpioLevel =3D mTbtNvsAreaPtr->TbtPcieRstGpioLevel0; + } + + Status =3D GetDTbtRpDevFun (gCurrentDiscreteTbtRootPortType, RootportSel= ected - 1, &RpDev, &RpFunc); + ASSERT_EFI_ERROR (Status); + CapHeaderOffset =3D PcieFindCapId (TbtSegment, 0x00, (UINT8)RpDev, (UINT= 8)RpFunc, 0x01); + DeviceBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (TbtSegment, 0x00, (UINT32= )RpDev, (UINT32)RpFunc, 0); + PowerState =3D &*((volatile UINT32 *) (mPciExpressBaseAddress + D= eviceBaseAddress + CapHeaderOffset + 4)); //PMCSR + PowerStatePrev =3D *PowerState; + *PowerState &=3D 0xFFFFFFFC; + + HoustRouteBus =3D PciSegmentRead8 (DeviceBaseAddress + PCI_BRIDGE_SECOND= ARY_BUS_REGISTER_OFFSET); + // + // Check the Subordinate bus .If it is Zero ,assign temporary bus to + // find the device presence . + // + if (HoustRouteBus =3D=3D 0) { + PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTE= R_OFFSET, 0xF0); + PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIS= TER_OFFSET, 0xF0); + HoustRouteBus =3D 0xF0; + SecSubBusAssigned =3D TRUE; + } + // + // Clear Interrupt capability of TBT CIO Plug Event Pin to make sure no = SCI is getting generated, + // This GPIO will be reprogrammed while resuming as part of Platform GPI= O Programming. + // + GpioSetPadInterruptConfig (TbtCioPlugEventGpioNo, GpioIntDis); + // + // Read the TBT Host router DeviceID + // + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Hous= tRouteBus, 0, 0, PCI_DEVICE_ID_OFFSET)); + + // + // Check For HostRouter Presence + // + if (IsTbtHostRouter (DeviceId)) { + // CableConnected =3D GetTbtHostRouterStatus (); + if (!((CableConnected & (DTBT_SAVE_STATE_OFFSET << Index)) =3D=3D (DTB= T_SAVE_STATE_OFFSET << Index))) { + CableConnected =3D CableConnected | (DTBT_SAVE_STATE_OFFSET << Index= ); + // SaveTbtHostRouterStatus (CableConnected); + } + } + + // + // Check value of Tbt2Pcie reg, if Tbt is not present, bios needs to app= ly force power prior to sending mailbox command + // + GET_TBT2PCIE_REGISTER_ADDRESS(TbtSegment, HoustRouteBus, 0x00, 0x00, Tbt= 2Pcie) + RegisterValue =3D PciSegmentRead32 (Tbt2Pcie); + if (0xFFFFFFFF =3D=3D RegisterValue) { + + GpioWrite (TbtFrcPwrGpioNo,TbtFrcPwrGpioLevel); + + while (Timeout -- > 0) { + RegisterValue =3D PciSegmentRead32 (Tbt2Pcie); + if (0xFFFFFFFF !=3D RegisterValue) { + break; + } + Stall(1* (UINTN)1000); + } + // + // Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox = command for AIC. + // However BIOS shall not execute go2sx mailbox command on S5/reboot c= ycle. + // + + if( (EntryDispatchContext->Type =3D=3D SxS3) || (EntryDispatchContext-= >Type =3D=3D SxS4)) + { + if(!mTbtNvsAreaPtr->TbtWakeupSupport) { + //Wake Disabled, GO2SX_NO_WAKE Command + TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0= , TBT_5S_TIMEOUT); + } else { + //Wake Enabled, GO2SX Command + TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S= _TIMEOUT); + } + } + if (mTbtNvsAreaPtr->TbtFrcPwrEn =3D=3D 0) { + GpioWrite (TbtFrcPwrGpioNo,!(TbtFrcPwrGpioLevel)); + } + } else { + // + // Before entering Sx state BIOS should execute GO2SX/NO_WAKE mailbox = command for AIC. + // However BIOS shall not execute go2sx mailbox command on S5/reboot c= ycle. + // + if( (EntryDispatchContext->Type =3D=3D SxS3) || (EntryDispatchContext-= >Type =3D=3D SxS4)) + { + if(!mTbtNvsAreaPtr->TbtWakeupSupport) { + //Wake Disabled, GO2SX_NO_WAKE Command + TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX_NO_WAKE, HoustRouteBus, 0, 0= , TBT_5S_TIMEOUT); + } else { + //Wake Enabled, GO2SX Command + TbtSetPcie2TbtCommand (PCIE2TBT_GO2SX, HoustRouteBus, 0, 0, TBT_5S= _TIMEOUT); + } + } + } + *PowerState =3D PowerStatePrev; + // + // Restore the bus number in case we assigned temporarily + // + if (SecSubBusAssigned) { + PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SECONDARY_BUS_REGISTE= R_OFFSET, 0x00); + PciSegmentWrite8 (DeviceBaseAddress + PCI_BRIDGE_SUBORDINATE_BUS_REGIS= TER_OFFSET, 0x00); + } + if (gDTbtPcieRstSupport) { + GpioWrite (TbtPcieRstGpioNo,TbtPcieRstGpioLevel); + } + return EFI_SUCCESS; +} + +VOID +ThunderboltSwSmiCallback ( + IN UINT8 Type + ) +{ + UINT8 ThunderboltSmiFunction; + + DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Entry\n")); + ThunderboltSmiFunction =3D mTbtNvsAreaPtr->ThunderboltSmiFunction; + DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback. ThunderboltSmiFunction=3D= %d\n", ThunderboltSmiFunction)); + if (Type =3D=3D DTBT_CONTROLLER) { + gCurrentDiscreteTbtRootPort =3D mTbtNvsAreaPtr->CurrentDiscreteTbt= RootPort; + gCurrentDiscreteTbtRootPortType =3D mTbtNvsAreaPtr->CurrentDiscreteTbt= RootPortType; + } + + switch (ThunderboltSmiFunction) { + case 21: + ThunderboltCallback (Type); + break; + + case 22: + TbtDisablePCIDevicesAndBridges (Type); + break; + + case 23: + ConfigureTbtAspm (Type, (UINT16) 0x02); + break; + + case 24: + ConfigureTbtAspm (Type, (UINT16) 0x01); + break; + + default: + break; + } + DEBUG ((DEBUG_INFO, "ThunderboltSwSmiCallback Exit.\n")); +} +STATIC +EFI_STATUS +EFIAPI +DiscreteThunderboltSwSmiCallback ( + IN EFI_HANDLE DispatchHandle, + IN CONST VOID *DispatchContext, + IN OUT VOID *CommBuffer OPTIONAL, + IN UINTN *CommBufferSize OPTIONAL + ) +{ + ThunderboltSwSmiCallback(DTBT_CONTROLLER); + return EFI_SUCCESS; +} +EFI_STATUS +TbtRegisterHandlers ( + IN BOOLEAN Type + ) +{ + EFI_STATUS Status; + UINTN SmiInputValue; + EFI_SMM_HANDLER_ENTRY_POINT2 SxHandler; + EFI_SMM_HANDLER_ENTRY_POINT2 SwHandler; + EFI_SMM_SX_DISPATCH2_PROTOCOL *SxDispatchProtocol; + EFI_SMM_SW_DISPATCH2_PROTOCOL *SwDispatch; + EFI_SMM_SX_REGISTER_CONTEXT EntryDispatchContext; + EFI_SMM_SW_REGISTER_CONTEXT SwContext; + EFI_HANDLE SwDispatchHandle; + EFI_HANDLE S3DispatchHandle; + EFI_HANDLE S4DispatchHandle; + EFI_HANDLE S5DispatchHandle; + + Status =3D EFI_UNSUPPORTED; + + if(Type =3D=3D DTBT_CONTROLLER) { + SxHandler =3D SxDTbtEntryCallback; + SwHandler =3D DiscreteThunderboltSwSmiCallback; + SmiInputValue =3D PcdGet8 (PcdSwSmiDTbtEnumerate); + gDTbtPcieRstSupport =3D gTbtInfoHob->DTbtCommonConfig.PcieRstSupport; + Status =3D EFI_SUCCESS; + } + if (EFI_ERROR (Status)) { + return Status; + } + + SwDispatchHandle =3D NULL; + S3DispatchHandle =3D NULL; + S4DispatchHandle =3D NULL; + S5DispatchHandle =3D NULL; + + Status =3D gSmst->SmmLocateProtocol ( + &gEfiSmmSxDispatch2ProtocolGuid, + NULL, + (VOID **) &SxDispatchProtocol + ); + ASSERT_EFI_ERROR (Status); + // + // Register S3 entry phase call back function + // + EntryDispatchContext.Type =3D SxS3; + EntryDispatchContext.Phase =3D SxEntry; + Status =3D SxDispatchProtocol->Register ( + SxDispatchProtocol, + SxHandler, + &EntryDispatchContext, + &S3DispatchHandle + ); + ASSERT_EFI_ERROR (Status); + // + // Register S4 entry phase call back function + // + EntryDispatchContext.Type =3D SxS4; + EntryDispatchContext.Phase =3D SxEntry; + Status =3D SxDispatchProtocol->Register ( + SxDispatchProtocol, + SxHandler, + &EntryDispatchContext, + &S4DispatchHandle + ); + ASSERT_EFI_ERROR (Status); + // + // Register S5 entry phase call back function + // + EntryDispatchContext.Type =3D SxS5; + EntryDispatchContext.Phase =3D SxEntry; + Status =3D SxDispatchProtocol->Register ( + SxDispatchProtocol, + SxHandler, + &EntryDispatchContext, + &S5DispatchHandle + ); + ASSERT_EFI_ERROR (Status); + // + // Locate the SMM SW dispatch protocol + // + Status =3D gSmst->SmmLocateProtocol ( + &gEfiSmmSwDispatch2ProtocolGuid, + NULL, + (VOID **) &SwDispatch + ); + + ASSERT_EFI_ERROR (Status); + // + // Register SWSMI handler + // + SwContext.SwSmiInputValue =3D SmiInputValue; + Status =3D SwDispatch->Register ( + SwDispatch, + SwHandler, + &SwContext, + &SwDispatchHandle + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} +EFI_STATUS +InSmmFunction ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D EFI_SUCCESS; + + Status =3D TbtRegisterHandlers(DTBT_CONTROLLER); + return Status; +} + +EFI_STATUS +EFIAPI +TbtSmmEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + TBT_NVS_AREA_PROTOCOL *TbtNvsAreaProtocol; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "TbtSmmEntryPoint\n")); + + mPciExpressBaseAddress =3D PcdGet64 (PcdPciExpressBaseAddress); + // + // Locate Tbt shared data area + // + Status =3D gBS->LocateProtocol (&gTbtNvsAreaProtocolGuid, NULL, (VOID **= ) &TbtNvsAreaProtocol); + ASSERT_EFI_ERROR (Status); + mTbtNvsAreaPtr =3D TbtNvsAreaProtocol->Area; + + // + // Get TBT INFO HOB + // + gTbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid); + if (gTbtInfoHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + + return InSmmFunction (ImageHandle, SystemTable); +} + +VOID +EndOfThunderboltCallback ( + IN UINTN RpSegment, + IN UINTN RpBus, + IN UINTN RpDevice, + IN UINTN RpFunction + ) +{ + if(mTbtNvsAreaPtr->TbtL1SubStates !=3D 0) { + ThunderboltEnableL1Sub (mTbtNvsAreaPtr->TbtL1SubStates, RpSegment, RpB= us, RpDevice, RpFunction); + } + ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 1); + if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case + ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFuncti= on); + } else { //Aspm enable case + ThunderboltEnableAspmWithoutLtr ((UINT16)mTbtNvsAreaPtr->TbtAspm, RpSe= gment, RpBus, RpDevice, RpFunction); + } + + if (mTbtNvsAreaPtr->TbtLtr) { + ThunderboltGetLatencyLtr (); + ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction); + } + ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction); + ConfigureTbtPm(RpSegment, RpBus, RpDevice, RpFunction, 2); +} // EndOfThunderboltCallback + +VOID +ConfigureTbtAspm ( + IN UINT8 Type, + IN UINT16 Aspm + ) +{ + UINTN RpSegment =3D 0; + UINTN RpBus =3D 0; + UINTN RpDevice; + UINTN RpFunction; + + if(Type =3D=3D DTBT_CONTROLLER) { + if (gCurrentDiscreteTbtRootPort =3D=3D 0) { + return; + } + GetDTbtRpDevFun(DTBT_CONTROLLER, gCurrentDiscreteTbtRootPort - 1, &RpD= evice, &RpFunction); + + ConfigureTbtPm (RpSegment, RpBus, RpDevice, RpFunction, 1); + if (!mTbtNvsAreaPtr->TbtAspm) { //Aspm disable case + ThunderboltDisableAspmWithoutLtr (RpSegment, RpBus, RpDevice, RpFunc= tion); + } else { //Aspm enable case + ThunderboltEnableAspmWithoutLtr ((UINT16) Aspm, RpSegment, RpBus, Rp= Device, RpFunction); + } + + if (mTbtNvsAreaPtr->TbtLtr) { + ThunderboltGetLatencyLtr (); + ThunderboltSetLatencyLtr (RpSegment, RpBus, RpDevice, RpFunction); + } + ConfigureLtr (RpSegment, RpBus, RpDevice, RpFunction); + } // EndOfThunderboltCallback +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/Ac= piTimerLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/= AcpiTimerLib.c new file mode 100644 index 0000000000..ec06eee73f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Library/AcpiTimerLib/AcpiTimer= Lib.c @@ -0,0 +1,394 @@ +/** @file + ACPI Timer implements one instance of Timer Library. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +// +// OVERRIDE: OverrideBegin +// +#include +// +// OVERRIDE: OverrideEnd +// + + +/** + Internal function to retrieves the 64-bit frequency in Hz. + + Internal function to retrieves the 64-bit frequency in Hz. + + @return The frequency in Hz. + +**/ +UINT64 +InternalGetPerformanceCounterFrequency ( + VOID + ); + +/** + The constructor function enables ACPI IO space. + + If ACPI I/O space not enabled, this function will enable it. + It will always return RETURN_SUCCESS. + + @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS. + +**/ +RETURN_STATUS +EFIAPI +AcpiTimerLibConstructor ( + VOID + ) +{ + UINTN Bus; + UINTN Device; + UINTN Function; + UINTN EnableRegister; + UINT8 EnableMask; + + // + // ASSERT for the invalid PCD values. They must be configured to the rea= l value. + // + ASSERT (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) !=3D 0xFFFF); + ASSERT (PcdGet16 (PcdAcpiIoPortBaseAddress) !=3D 0xFFFF); + + // + // If the register offset to the BAR for the ACPI I/O Port Base Address = is 0x0000, then + // no PCI register programming is required to enable access to the the A= CPI registers + // specified by PcdAcpiIoPortBaseAddress + // + if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) =3D=3D 0x0000) { + return RETURN_SUCCESS; + } + + // + // ASSERT for the invalid PCD values. They must be configured to the rea= l value. + // + ASSERT (PcdGet8 (PcdAcpiIoPciDeviceNumber) !=3D 0xFF); + ASSERT (PcdGet8 (PcdAcpiIoPciFunctionNumber) !=3D 0xFF); + ASSERT (PcdGet16 (PcdAcpiIoPciEnableRegisterOffset) !=3D 0xFFFF); + + // + // Retrieve the PCD values for the PCI configuration space required to p= rogram the ACPI I/O Port Base Address + // + Bus =3D PcdGet8 (PcdAcpiIoPciBusNumber); + Device =3D PcdGet8 (PcdAcpiIoPciDeviceNumber); + Function =3D PcdGet8 (PcdAcpiIoPciFunctionNumber); + EnableRegister =3D PcdGet16 (PcdAcpiIoPciEnableRegisterOffset); + EnableMask =3D PcdGet8 (PcdAcpiIoBarEnableMask); + + // + // If ACPI I/O space is not enabled yet, program ACPI I/O base address a= nd enable it. + // + if ((PciRead8 (PCI_LIB_ADDRESS (Bus, Device, Function, EnableRegister)) = & EnableMask) !=3D EnableMask) { + PciWrite16 ( + PCI_LIB_ADDRESS (Bus, Device, Function, PcdGet16 (PcdAcpiIoPciBarReg= isterOffset)), + PcdGet16 (PcdAcpiIoPortBaseAddress) + ); + PciOr8 ( + PCI_LIB_ADDRESS (Bus, Device, Function, EnableRegister), + EnableMask + ); + } + + return RETURN_SUCCESS; +} + +/** + Internal function to retrieve the ACPI I/O Port Base Address. + + Internal function to retrieve the ACPI I/O Port Base Address. + + @return The 16-bit ACPI I/O Port Base Address. + +**/ +UINT16 +InternalAcpiGetAcpiTimerIoPort ( + VOID + ) +{ + UINT16 Port; + + Port =3D PcdGet16 (PcdAcpiIoPortBaseAddress); + + // + // If the register offset to the BAR for the ACPI I/O Port Base Address = is not 0x0000, then + // read the PCI register for the ACPI BAR value in case the BAR has been= programmed to a + // value other than PcdAcpiIoPortBaseAddress + // + if (PcdGet16 (PcdAcpiIoPciBarRegisterOffset) !=3D 0x0000) { + Port =3D PciRead16 (PCI_LIB_ADDRESS ( + PcdGet8 (PcdAcpiIoPciBusNumber), + PcdGet8 (PcdAcpiIoPciDeviceNumber), + PcdGet8 (PcdAcpiIoPciFunctionNumber), + PcdGet16 (PcdAcpiIoPciBarRegisterOffset) + )); + } + + return (Port & PcdGet16 (PcdAcpiIoPortBaseAddressMask)) + PcdGet16 (PcdA= cpiPm1TmrOffset); +} + +/** + Stalls the CPU for at least the given number of ticks. + + Stalls the CPU for at least the given number of ticks. It's invoked by + MicroSecondDelay() and NanoSecondDelay(). + + @param Delay A period of time to delay in ticks. + +**/ +VOID +InternalAcpiDelay ( + IN UINT32 Delay + ) +{ + UINT16 Port; + UINT32 Ticks; + UINT32 Times; + + Port =3D InternalAcpiGetAcpiTimerIoPort (); + Times =3D Delay >> 22; + Delay &=3D BIT22 - 1; + do { + // + // The target timer count is calculated here + // + Ticks =3D IoBitFieldRead32 (Port, 0, 23) + Delay; + Delay =3D BIT22; + // + // Wait until time out + // Delay >=3D 2^23 could not be handled by this function + // Timer wrap-arounds are handled correctly by this function + // + while (((Ticks - IoBitFieldRead32 (Port, 0, 23)) & BIT23) =3D=3D 0) { + CpuPause (); + } + } while (Times-- > 0); +} + +/** + Stalls the CPU for at least the given number of microseconds. + + Stalls the CPU for the number of microseconds specified by MicroSeconds. + + @param MicroSeconds The minimum number of microseconds to delay. + + @return MicroSeconds + +**/ +UINTN +EFIAPI +MicroSecondDelay ( + IN UINTN MicroSeconds + ) +{ + InternalAcpiDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + MicroSeconds, + ACPI_TIMER_FREQUENCY + ), + 1000000u + ) + ); + return MicroSeconds; +} + +/** + Stalls the CPU for at least the given number of nanoseconds. + + Stalls the CPU for the number of nanoseconds specified by NanoSeconds. + + @param NanoSeconds The minimum number of nanoseconds to delay. + + @return NanoSeconds + +**/ +UINTN +EFIAPI +NanoSecondDelay ( + IN UINTN NanoSeconds + ) +{ + InternalAcpiDelay ( + (UINT32)DivU64x32 ( + MultU64x32 ( + NanoSeconds, + ACPI_TIMER_FREQUENCY + ), + 1000000000u + ) + ); + return NanoSeconds; +} + +/** + Retrieves the current value of a 64-bit free running performance counter. + + Retrieves the current value of a 64-bit free running performance counter= . The + counter can either count up by 1 or count down by 1. If the physical + performance counter counts by a larger increment, then the counter values + must be translated. The properties of the counter can be retrieved from + GetPerformanceCounterProperties(). + + @return The current value of the free running performance counter. + +**/ +UINT64 +EFIAPI +GetPerformanceCounter ( + VOID + ) +{ + return AsmReadTsc (); +} + +/** + Retrieves the 64-bit frequency in Hz and the range of performance counter + values. + + If StartValue is not NULL, then the value that the performance counter s= tarts + with immediately after is it rolls over is returned in StartValue. If + EndValue is not NULL, then the value that the performance counter end wi= th + immediately before it rolls over is returned in EndValue. The 64-bit + frequency of the performance counter in Hz is always returned. If StartV= alue + is less than EndValue, then the performance counter counts up. If StartV= alue + is greater than EndValue, then the performance counter counts down. For + example, a 64-bit free running counter that counts up would have a Start= Value + of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter + that counts down would have a StartValue of 0xFFFFFF and an EndValue of = 0. + + @param StartValue The value the performance counter starts with when it + rolls over. + @param EndValue The value that the performance counter ends with bef= ore + it rolls over. + + @return The frequency in Hz. + +**/ +UINT64 +EFIAPI +GetPerformanceCounterProperties ( + OUT UINT64 *StartValue, OPTIONAL + OUT UINT64 *EndValue OPTIONAL + ) +{ + if (StartValue !=3D NULL) { + *StartValue =3D 0; + } + + if (EndValue !=3D NULL) { + *EndValue =3D 0xffffffffffffffffULL; + } + return InternalGetPerformanceCounterFrequency (); +} + +/** + Converts elapsed ticks of performance counter to time in nanoseconds. + + This function converts the elapsed ticks of running performance counter = to + time value in unit of nanoseconds. + + @param Ticks The number of elapsed ticks of running performance cou= nter. + + @return The elapsed time in nanoseconds. + +**/ +UINT64 +EFIAPI +GetTimeInNanoSecond ( + IN UINT64 Ticks + ) +{ + UINT64 Frequency; + UINT64 NanoSeconds; + UINT64 Remainder; + INTN Shift; + Frequency =3D GetPerformanceCounterProperties (NULL, NULL); + + // + // Ticks + // Time =3D --------- x 1,000,000,000 + // Frequency + // + NanoSeconds =3D MultU64x32 (DivU64x64Remainder (Ticks, Frequency, &Remai= nder), 1000000000u); + + // + // Ensure (Remainder * 1,000,000,000) will not overflow 64-bit. + // Since 2^29 < 1,000,000,000 =3D 0x3B9ACA00 < 2^30, Remainder should < = 2^(64-30) =3D 2^34, + // i.e. highest bit set in Remainder should <=3D 33. + // + Shift =3D MAX (0, HighBitSet64 (Remainder) - 33); + Remainder =3D RShiftU64 (Remainder, (UINTN) Shift); + Frequency =3D RShiftU64 (Frequency, (UINTN) Shift); + NanoSeconds +=3D DivU64x64Remainder (MultU64x32 (Remainder, 1000000000u)= , Frequency, NULL); + + return NanoSeconds; +} + +// +// OVERRIDE: OverrideBegin +// +/** + Calculate TSC frequency. + + The TSC counting frequency is determined by using CPUID leaf 0x15 that i= s the preferred + method for Skylake and beyond. Frequency in MHz =3D Core XTAL frequency= * EBX/EAX. + In newer flavors of the CPU, core xtal frequency is returned in ECX (or = 0 if not + supported). If ECX is 0, 24MHz is assumed. + @return The number of TSC counts per second. + +**/ +UINT64 +InternalCalculateTscFrequency ( + VOID + ) +{ + UINT64 TscFrequency; + UINT64 CoreXtalFrequency; + UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; + + // + // Use CPUID leaf 0x15. + // TSC frequency =3D (Core Xtal Frequency) * EBX/EAX. EBX returns 0 if = not + // supported. ECX, if non zero, provides Core Xtal Frequency in hertz + // (SDM Dec 2016). + // + AsmCpuid (CPUID_TIME_STAMP_COUNTER, &RegEax, &RegEbx, &RegEcx, NULL); + ASSERT (RegEbx !=3D 0); + + // + // If core xtal frequency (ECX) returns 0, it is safe to use 24MHz for p= ost + // Skylake client CPU's. + // + if (RegEcx =3D=3D 0) { + CoreXtalFrequency =3D 24000000ul; + } else { + CoreXtalFrequency =3D (UINT64)RegEcx; + } + + // + // Calculate frequency. For integer division, round up/down result + // correctly by adding denominator/2 to the numerator prior to division. + // + TscFrequency =3D DivU64x32 (MultU64x32 (CoreXtalFrequency, RegEbx) + (UI= NT64)(RegEax >> 1), RegEax); + + return TscFrequency; +} +// +// OVERRIDE: OverrideEnd +// + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Bo= ardInitLib.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/= BoardInitLib.c new file mode 100644 index 0000000000..2bba58eed3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInit= Lib.c @@ -0,0 +1,612 @@ +/** @file + Source code for the board configuration init function in DXE init phase. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "BoardInitLib.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +// +// Null function for nothing GOP VBT update. +// +VOID +GopVbtSpecificUpdateNull( + IN CHILD_STRUCT **ChildStructPtr +); + +// +// for CFL U DDR4 +// +VOID +CflUDdr4GopVbtSpecificUpdate( + IN CHILD_STRUCT **ChildStructPtr +); + +/** + Updates DIMM slots status for Desktop,server and workstation boards + +**/ +VOID +UpdateDimmPopulationConfig( + VOID + ) +{ + MEMORY_INFO_DATA_HOB *MemInfo; + UINT8 Slot0; + UINT8 Slot1; + UINT8 Slot2; + UINT8 Slot3; + CONTROLLER_INFO *ControllerInfo; + EFI_HOB_GUID_TYPE *GuidHob; + + GuidHob =3D NULL; + MemInfo =3D NULL; + + GuidHob =3D GetFirstGuidHob (&gSiMemoryInfoDataGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob !=3D NULL) { + MemInfo =3D (MEMORY_INFO_DATA_HOB *) GET_GUID_HOB_DATA (GuidHob); + } + if (MemInfo !=3D NULL) { + if (PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorDesktop || + PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorUpServer || + PcdGet8 (PcdPlatformFlavor) =3D=3D FlavorWorkstation) { + ControllerInfo =3D &MemInfo->Controller[0]; + Slot0 =3D ControllerInfo->ChannelInfo[0].DimmInfo[0].Status; + Slot1 =3D ControllerInfo->ChannelInfo[0].DimmInfo[1].Status; + Slot2 =3D ControllerInfo->ChannelInfo[1].DimmInfo[0].Status; + Slot3 =3D ControllerInfo->ChannelInfo[1].DimmInfo[1].Status; + + // + // Channel 0 Channel 1 + // Slot0 Slot1 Slot0 Slot1 - Population AIO= board + // 0 0 0 0 - Invalid - In= valid + // 0 0 0 1 - Valid - In= valid + // 0 0 1 0 - Invalid - Va= lid + // 0 0 1 1 - Valid - Va= lid + // 0 1 0 0 - Valid - In= valid + // 0 1 0 1 - Valid - In= valid + // 0 1 1 0 - Invalid - In= valid + // 0 1 1 1 - Valid - In= valid + // 1 0 0 0 - Invalid - Va= lid + // 1 0 0 1 - Invalid - In= valid + // 1 0 1 0 - Invalid - Va= lid + // 1 0 1 1 - Invalid - Va= lid + // 1 1 0 0 - Valid - Va= lid + // 1 1 0 1 - Valid - In= valid + // 1 1 1 0 - Invalid - Va= lid + // 1 1 1 1 - Valid - Va= lid + // + + if ((Slot0 && (Slot1 =3D=3D 0)) || (Slot2 && (Slot3 =3D=3D 0))) { + PcdSetBoolS (PcdDimmPopulationError, TRUE); + } + } + } +} + +/** + Init Misc Platform Board Config Block. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +BoardMiscInit ( + IN UINT16 BoardId + ) +{ +// PcdSet64S (PcdFuncBoardHookPlatformSetupOverride, (UINT64) (UINTN) Boa= rdHookPlatformSetup); + + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS (PcdPssReadSN, TRUE); + PcdSet8S (PcdPssI2cSlaveAddress, 0x6E); + PcdSet8S (PcdPssI2cBusNumber, 0x04); + break; + default: + PcdSetBoolS (PcdPssReadSN, FALSE); + PcdSet8S (PcdPssI2cSlaveAddress, 0x6E); + PcdSet8S (PcdPssI2cBusNumber, 0x04); + break; + } + + + return EFI_SUCCESS; +} + +/** + Init Platform Board Config Block for ACPI platform. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +InitAcpiPlatformPcd ( + IN UINT16 BoardId + ) +{ + TBT_INFO_HOB *TbtInfoHob =3D NULL; + + TbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid); + + // + // Update OEM table ID + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + if ((TbtInfoHob !=3D NULL) && (TbtInfoHob->DTbtControllerConfig[0].D= TbtControllerEn =3D=3D 1)) { + PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_',= 'w', 'h', 'l', 't', '4')); + } else { + PcdSet64S (PcdXhciAcpiTableSignature, SIGNATURE_64 ('x', 'h', '_',= 'w', 'h', 'l', 'd', '4')); + } + break; + default: + PcdSet64S (PcdXhciAcpiTableSignature, 0); + break; + } + + // + // Modify Preferred_PM_Profile field based on Board SKU's. Default is se= t to Mobile + // + PcdSet8S (PcdPreferredPmProfile, EFI_ACPI_2_0_PM_PROFILE_MOBILE); + + // + // Assign FingerPrint, Gnss, TouchPanel, Audio related GPIO. + // + switch(BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdFingerPrintSleepGpio, GPIO_CNL_LP_GPP_B17); + PcdSet32S (PcdFingerPrintIrqGpio, GPIO_CNL_LP_GPP_B16); + // + // Configure WWAN Reset pin + // + PcdSet32S (PcdGnssResetGpio, GPIO_CNL_LP_GPP_F1); + PcdSet32S (PcdTouchpanelIrqGpio, GPIO_CNL_LP_GPP_D10); + PcdSet32S (PcdTouchpadIrqGpio, GPIO_CNL_LP_GPP_B3); + PcdSet32S (PcdHdaI2sCodecIrqGpio, GPIO_CNL_LP_GPP_C8); + break; + default: + break; + } + + // + // Configure GPIOs for discrete USB BT module + // + switch(BoardId) { + + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdBtIrqGpio, GPIO_CNL_LP_GPP_B2); + PcdSet32S (PcdBtRfKillGpio, GPIO_CNL_LP_GPP_B4); + break; + default: + break; + } + + // + // Board Specific Init + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS(PcdWhlErbRtd3TableEnable, TRUE); + PcdSet8S (PcdHdaI2sCodecI2cBusNumber, 0); // I2S Audio Codec conntec= ted to I2C0 + PcdSet8S (PcdBleUsbPortNumber, 9); + break; + default: + break; + } + + return EFI_SUCCESS; +} + +/** + Init Common Platform Board Config Block. + + @param[in] BoardId An unsigned integer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +InitCommonPlatformPcd ( + IN UINT16 BoardId + ) +{ + PCD64_BLOB Data64; + TBT_INFO_HOB *TbtInfoHob =3D NULL; + + TbtInfoHob =3D (TBT_INFO_HOB *) GetFirstGuidHob (&gTbtInfoHobGuid); + + + // + // Enable EC SMI# for SMI + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdEcSmiGpio, GPIO_CNL_LP_GPP_E3); + PcdSet32S (PcdEcLowPowerExitGpio, GPIO_CNL_LP_GPP_B23); + break; + }; + + // + // HID I2C Interrupt GPIO. + // + switch (BoardId) { + default: + // on all supported boards interrupt input is on same GPIO pad. How = convenient. + PcdSet32S (PcdHidI2cIntPad, GPIO_CNL_LP_GPP_D10); + break; + } + + // + // PS2 KB Specific Init for Sds Serial platform. + // + if (BoardId =3D=3D BoardIdWhiskeyLakeRvp) { + PcdSetBoolS (PcdDetectPs2KbOnCmdAck, TRUE); + } else { + PcdSetBoolS (PcdDetectPs2KbOnCmdAck, FALSE); + } + + switch (BoardId) { + default: + PcdSetBoolS (PcdSpdAddressOverride, FALSE); + break; + } + + // + // DDISelection + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S (PcdDDISelection, 1); + break; + default: + PcdSet8S (PcdDDISelection, 0); + break; + } + + // + // GFX Detect + // + switch (BoardId) { + default: + // Not all the boards support GFX_CRB_DET. This is not an error. + Data64.BoardGpioConfig.Type =3D BoardGpioTypeNotSupported; + break; + } + + PcdSet64S (PcdGfxCrbDetectGpio, Data64.Blob); + + // + // USB Type-C + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS(PcdUsbTypeCSupport, TRUE); + // Discete Ports + PcdSet8S(PcdTypeCPortsSupported, 2); + // TBT Port 1 mapping and properties [TBT AIC] + PcdSet8S(PcdUsbTypeCPort1, 1); + PcdSet8S(PcdUsbTypeCPort1Pch, 5); + // TBT Port 2 mapping and properties [TBT AIC] + PcdSet8S(PcdUsbTypeCPort2, 2); + PcdSet8S(PcdUsbTypeCPort2Pch, 7); + break; + default: + PcdSetBoolS (PcdUsbTypeCSupport, FALSE); + break; + } + + // + // Battery Present + // + switch (BoardId) { + default: + PcdSet8S (PcdBatteryPresent, BOARD_REAL_BATTERY_SUPPORTED | BOARD_VIRT= UAL_BATTERY_SUPPORTED); + break; + } + + // + // TS-on-DIMM temperature + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS (PcdTsOnDimmTemperature, TRUE); + break; + default: + PcdSetBoolS (PcdTsOnDimmTemperature, FALSE); + break; + } + // + // Real Battery 1 Control & Real Battery 2 Control + // + PcdSet8S (PcdRealBattery1Control, 1); + PcdSet8S (PcdRealBattery2Control, 2); + + // + // Mipi Camera Sensor + // + PcdSetBoolS (PcdMipiCamSensor, FALSE); + // + // Mipi Camera Sensor Link Used + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S (PcdMipiCam0LinkUsed, 3); + PcdSet8S (PcdMipiCam1LinkUsed, 6); + PcdSet8S (PcdMipiCam2LinkUsed, 9); + PcdSet8S (PcdMipiCam3LinkUsed, 7); + break; + default: + break; + } + + // + // H8S2113 SIO + // + switch(BoardId) { + default: + PcdSetBoolS (PcdH8S2113SIO, FALSE); + break; + } + + + // + // NCT6776F COM, SIO & HWMON + // + PcdSetBoolS (PcdNCT6776FCOM, FALSE); + PcdSetBoolS (PcdNCT6776FSIO, FALSE); + PcdSetBoolS (PcdNCT6776FHWMON, FALSE); + + // + // SMC Runtime Sci Pin + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdSmcRuntimeSciPin, (UINT32) GPIO_CNL_LP_GPP_E16); + break; + default: + PcdSet32S (PcdSmcRuntimeSciPin, 0x00); + break; + } + + // + // Convertable Dock Support + // + switch (BoardId) { + default: + PcdSetBoolS (PcdConvertableDockSupport, FALSE); + break; + } + + // + // Ec Hotkey F3, F4, F5, F6, F7 and F8 Support + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet8S (PcdEcHotKeyF3Support, 1); + PcdSet8S (PcdEcHotKeyF4Support, 1); + PcdSet8S (PcdEcHotKeyF5Support, 1); + PcdSet8S (PcdEcHotKeyF6Support, 1); + PcdSet8S (PcdEcHotKeyF7Support, 1); + PcdSet8S (PcdEcHotKeyF8Support, 1); + break; + default: + PcdSet8S (PcdEcHotKeyF3Support, 0); + PcdSet8S (PcdEcHotKeyF4Support, 0); + PcdSet8S (PcdEcHotKeyF5Support, 0); + PcdSet8S (PcdEcHotKeyF6Support, 0); + PcdSet8S (PcdEcHotKeyF7Support, 0); + PcdSet8S (PcdEcHotKeyF8Support, 0); + break; + } + + // + // Virtual Button Volume Up & Done Support + // Virtual Button Home Button Support + // Virtual Button Rotation Lock Support + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, TRUE); + PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, TRUE); + PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, FALSE); + PcdSetBoolS (PcdVirtualButtonRotationLockSupport, FALSE); + break; + default: + PcdSetBoolS (PcdVirtualButtonVolumeUpSupport, FALSE); + PcdSetBoolS (PcdVirtualButtonVolumeDownSupport, FALSE); + PcdSetBoolS (PcdVirtualButtonHomeButtonSupport, FALSE); + PcdSetBoolS (PcdVirtualButtonRotationLockSupport, FALSE); + break; + } + + // + // Slate Mode Switch Support + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS (PcdSlateModeSwitchSupport, TRUE); + break; + default: + PcdSetBoolS (PcdSlateModeSwitchSupport, FALSE); + break; + } + + // + // Ac Dc Auto Switch Support + // + switch (BoardId) { + default: + PcdSetBoolS (PcdAcDcAutoSwitchSupport, TRUE); + break; + } + + // + // Pm Power Button Gpio Pin + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSet32S (PcdPmPowerButtonGpioPin, (UINT32) GPIO_CNL_LP_GPD3); + break; + default: + PcdSet32S (PcdPmPowerButtonGpioPin, 0x00); + break; + } + + // + // Acpi Enable All Button Support + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS (PcdAcpiEnableAllButtonSupport, TRUE); + break; + default: + PcdSetBoolS (PcdAcpiEnableAllButtonSupport, FALSE); + break; + } + + // + // Acpi Hid Driver Button Support + // + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + PcdSetBoolS (PcdAcpiHidDriverButtonSupport, TRUE); + break; + default: + PcdSetBoolS (PcdAcpiHidDriverButtonSupport, FALSE); + break; + } + + // + // USB Type C EC less + // + switch (BoardId) { + default: + PcdSetBoolS (PcdUsbTypeCEcLess, FALSE); + break; + } + + return EFI_SUCCESS; +} + +/** + Check if given rootport has device connected and enable wake capability + + @param[in] RpNum An unsigned integer represent the root port = number. + + @retval TRUE if endpoint was connected + @retval FALSE if no endpoint was detected +**/ +BOOLEAN +IsPcieEndPointPresent ( + IN UINT8 RpNum + ) +{ + EFI_STATUS Status; + UINTN RpDev; + UINTN RpFun; + UINT64 RpBaseAddress; + + Status =3D GetPchPcieRpDevFun (RpNum, &RpDev, &RpFun); + if (!EFI_ERROR (Status)) { + // + // check if device is present + // + RpBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS ( + DEFAULT_PCI_SEGMENT_NUMBER_PCH, + DEFAULT_PCI_BUS_NUMBER_PCH, + RpDev, + RpFun, + 0 + ); + + if ((PciSegmentRead16 (RpBaseAddress) !=3D 0xFFFF) && + (PciSegmentRead16 (RpBaseAddress + R_PCH_PCIE_CFG_SLSTS) & B_PCIE_= SLSTS_PDS)) { + return TRUE; + } + } + + return FALSE; + +} + +/** + Enable Tier2 GPIO Sci wake capability. + + @param[in] BoardId An unsigned integrer represent the board id. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +Tier2GpioWakeSupport ( + IN UINT16 BoardId + ) +{ + BOOLEAN Tier2GpioWakeEnable; + + Tier2GpioWakeEnable =3D FALSE; + switch (BoardId) { + case BoardIdWhiskeyLakeRvp: + // + // Root port #14: M.2 WLAN + // + if (IsPcieEndPointPresent (13)) { + Tier2GpioWakeEnable =3D TRUE; + } + break; + default: + break; + } + PcdSetBoolS (PcdGpioTier2WakeEnable, Tier2GpioWakeEnable); + + return EFI_SUCCESS; +} + +/** + Board configuration init function for DXE phase. + + @param Content pointer to the buffer contain init information for boar= d init. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +BoardConfigInit ( + VOID + ) +{ + EFI_STATUS Status; + UINT16 BoardId; + + BoardId =3D BoardIdWhiskeyLakeRvp; + + Status =3D InitAcpiPlatformPcd (BoardId); + ASSERT_EFI_ERROR(Status); + + Status =3D InitCommonPlatformPcd (BoardId); + ASSERT_EFI_ERROR(Status); + + Status =3D BoardMiscInit (BoardId); + ASSERT_EFI_ERROR(Status); + + Status =3D Tier2GpioWakeSupport (BoardId); + ASSERT_EFI_ERROR(Status); + + return EFI_SUCCESS; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Cp= uPolicyInitDxe.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInit= Dxe/CpuPolicyInitDxe.c new file mode 100644 index 0000000000..eb7c3bbea0 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/CpuPolicy= InitDxe.c @@ -0,0 +1,46 @@ +/** @file + This file is SampleCode for Intel Silicon DXE Platform Policy initialzat= ion. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +DXE_CPU_POLICY_PROTOCOL mCpuPolicyData; + +/** + Initialize Intel CPU DXE Platform Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +CpuPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + + ZeroMem(&mCpuPolicyData, sizeof (DXE_CPU_POLICY_PROTOCOL)); + mCpuPolicyData.Revision =3D DXE_CPU_POLICY_PROTO= COL_REVISION; + + UpdateDxeSiCpuPolicy(&mCpuPolicyData); + + // + // Install CpuInstallPolicyProtocol. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D CpuInstallPolicyProtocol(ImageHandle, &mCpuPolicyData); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Go= pPolicyInitDxe.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInit= Dxe/GopPolicyInitDxe.c new file mode 100644 index 0000000000..66aab2d198 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/GopPolicy= InitDxe.c @@ -0,0 +1,174 @@ +/** @file + This file initialises and Installs GopPolicy Protocol. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "GopPolicyInitDxe.h" +#include + +GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy; +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize =3D 0; +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress =3D 0; + +// +// Function implementations +// + +/** + + @param[out] CurrentLidStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ + +EFI_STATUS +EFIAPI +GetPlatformLidStatus ( + OUT LID_STATUS *CurrentLidStatus + ) +{ + return EFI_UNSUPPORTED; +} + +/** + + @param[out] CurrentDockStatus + + @retval EFI_SUCCESS + @retval EFI_UNSUPPORTED +**/ +EFI_STATUS +EFIAPI +GetPlatformDockStatus ( + OUT DOCK_STATUS CurrentDockStatus + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + + @param[out] VbtAddress + @param[out] VbtSize + + @retval EFI_SUCCESS + @retval EFI_NOT_FOUND +**/ +EFI_STATUS +EFIAPI +GetVbtData ( + OUT EFI_PHYSICAL_ADDRESS *VbtAddress, + OUT UINT32 *VbtSize + ) +{ + EFI_STATUS Status; + UINTN FvProtocolCount; + EFI_HANDLE *FvHandles; + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv; + UINTN Index; + UINT32 AuthenticationStatus; + UINT8 *Buffer; + UINTN VbtBufferSize; + + Status =3D EFI_NOT_FOUND; + if ( mVbtAddress =3D=3D 0) { + Fv =3D NULL; + Buffer =3D 0; + FvHandles =3D NULL; + Status =3D gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiFirmwareVolume2ProtocolGuid, + NULL, + &FvProtocolCount, + &FvHandles + ); + if (!EFI_ERROR (Status)) { + for (Index =3D 0; Index < FvProtocolCount; Index++) { + Status =3D gBS->HandleProtocol ( + FvHandles[Index], + &gEfiFirmwareVolume2ProtocolGuid, + (VOID **) &Fv + ); + VbtBufferSize =3D 0; + Status =3D Fv->ReadSection ( + Fv, + PcdGetPtr(PcdIntelGraphicsVbtFileGuid), + EFI_SECTION_RAW, + 0, + (VOID **) &Buffer, + &VbtBufferSize, + &AuthenticationStatus + ); + if (!EFI_ERROR (Status)) { + *VbtAddress =3D (EFI_PHYSICAL_ADDRESS)Buffer; + *VbtSize =3D (UINT32)VbtBufferSize; + mVbtAddress =3D *VbtAddress; + mVbtSize =3D *VbtSize; + Status =3D EFI_SUCCESS; + break; + } + } + } else { + Status =3D EFI_NOT_FOUND; + } + + if (FvHandles !=3D NULL) { + FreePool (FvHandles); + FvHandles =3D NULL; + } + } else { + *VbtAddress =3D mVbtAddress; + *VbtSize =3D mVbtSize; + Status =3D EFI_SUCCESS; + } + + return Status; +} + +/** +Initialize GOP DXE Policy + +@param[in] ImageHandle Image handle of this driver. + +@retval EFI_SUCCESS Initialization complete. +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver. +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ + +EFI_STATUS +EFIAPI +GopPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + + // + // Initialize the EFI Driver Library + // + SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0); + + mGOPPolicy.Revision =3D GOP_POLICY_PROTOCOL_REVISION_03; + mGOPPolicy.GetPlatformLidStatus =3D GetPlatformLidStatus; + mGOPPolicy.GetVbtData =3D GetVbtData; + mGOPPolicy.GetPlatformDockStatus =3D GetPlatformDockStatus; + + // + // Install protocol to allow access to this Policy. + // + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gGopPolicyProtocolGuid, + &mGOPPolicy, + NULL + ); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Pc= hPolicyInitDxe.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInit= Dxe/PchPolicyInitDxe.c new file mode 100644 index 0000000000..2a1604fa13 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PchPolicy= InitDxe.c @@ -0,0 +1,55 @@ +/** @file + This file is SampleCode for PCH DXE Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PchPolicyInitDxe.h" + +// +// Function implementations +// + +/** + Initialize PCH DXE Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +PchPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + PCH_POLICY_PROTOCOL *PchPolicy; + + // + // Call CreatePchDxeConfigBlocks to create & initialize platform policy = structure + // and get all Intel default policy settings. + // + Status =3D CreatePchDxeConfigBlocks (&PchPolicy); + DEBUG((DEBUG_INFO, "PchPolicy->TableHeader.NumberOfBlocks =3D 0x%x\n", P= chPolicy->TableHeader.NumberOfBlocks)); + ASSERT_EFI_ERROR (Status); + + if (mFirmwareConfiguration !=3D FwConfigDefault) { + UpdateDxePchPolicy (PchPolicy); + } + + // + // Install PchInstallPolicyProtocol. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D PchInstallPolicyProtocol (ImageHandle, PchPolicy); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Po= licyInitDxe.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe= /PolicyInitDxe.c new file mode 100644 index 0000000000..ccaa57ce16 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/PolicyIni= tDxe.c @@ -0,0 +1,88 @@ +/** @file + This file is a wrapper for Platform Policy driver. Get Setup + Value to initialize Intel DXE Platform Policy. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PolicyInitDxe.h" +#include +#include "BoardInitLib.h" + +GLOBAL_REMOVE_IF_UNREFERENCED UINT8 mFirmwareConfiguration =3D = 0; + +/** + Initialize DXE Platform Policy + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Global system service table. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +PolicyInitDxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + Status =3D BoardConfigInit(); + + mFirmwareConfiguration =3D FwConfigProduction; + // + // SystemAgent Dxe Platform Policy Initialization + // + Status =3D SaPolicyInitDxe (ImageHandle); + DEBUG ((DEBUG_INFO, "SystemAgent Dxe Platform Policy Initialization done= \n")); + ASSERT_EFI_ERROR (Status); + + // + // PCH Dxe Platform Policy Initialization + // + Status =3D PchPolicyInitDxe (ImageHandle); + DEBUG ((DEBUG_INFO, "PCH Dxe Platform Policy Initialization done\n")); + ASSERT_EFI_ERROR (Status); + + // + // Silicon Dxe Platform Policy Initialization + // + Status =3D SiliconPolicyInitDxe (ImageHandle); + DEBUG ((DEBUG_INFO, "Silicon Dxe Platform Policy Initialization done\n")= ); + ASSERT_EFI_ERROR (Status); + + // + // CPU DXE Platform Policy Initialization + // + Status =3D CpuPolicyInitDxe (ImageHandle); + DEBUG ((DEBUG_INFO, "Cpu Dxe Platform Policy Initialization done\n")); + ASSERT_EFI_ERROR (Status); + + + if (PcdGetBool(PcdIntelGopEnable)) { + // + // GOP Dxe Policy Initialization + // + Status =3D GopPolicyInitDxe(ImageHandle); + DEBUG((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); + ASSERT_EFI_ERROR(Status); + } + if (PcdGetBool(PcdTbtEnable)) { + // + // Update TBT Policy + // + Status =3D InstallTbtPolicy (ImageHandle); + DEBUG ((DEBUG_INFO, "Install Tbt Policy done\n")); + ASSERT_EFI_ERROR (Status); + } + + return Status; + +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Sa= PolicyInitDxe.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitD= xe/SaPolicyInitDxe.c new file mode 100644 index 0000000000..c0095c09c3 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/SaPolicyI= nitDxe.c @@ -0,0 +1,60 @@ +/** @file + This file is SampleCode for SA DXE Policy initialization. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SaPolicyInitDxe.h" + + +// +// Function implementations +// + +/** + Initialize SA DXE Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this drive= r. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SaPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + SA_POLICY_PROTOCOL *SaPolicy; + + // + // Call CreateSaDxeConfigBlocks to create & initialize platform policy s= tructure + // and get all Intel default policy settings. + // + Status =3D CreateSaDxeConfigBlocks(&SaPolicy); + DEBUG((DEBUG_INFO, "SaPolicy->TableHeader.NumberOfBlocks =3D 0x%x\n ", S= aPolicy->TableHeader.NumberOfBlocks)); + ASSERT_EFI_ERROR(Status); + + UpdateDxeSaPolicyBoardConfig (SaPolicy); + + if (mFirmwareConfiguration !=3D FwConfigDefault) { + + UpdateDxeSaPolicy (SaPolicy); + } + + // + // Install SaInstallPolicyProtocol. + // While installed, RC assumes the Policy is ready and finalized. So ple= ase + // update and override any setting before calling this function. + // + Status =3D SaInstallPolicyProtocol (ImageHandle, SaPolicy); + ASSERT_EFI_ERROR (Status); + + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/Si= liconPolicyInitDxe.c b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Policy= InitDxe/SiliconPolicyInitDxe.c new file mode 100644 index 0000000000..15adca5cdd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/SiliconPo= licyInitDxe.c @@ -0,0 +1,46 @@ +/** @file + This file is SampleCode for Intel Silicon DXE Platform Policy initialzat= ion. + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include + +DXE_SI_POLICY_PROTOCOL mSiPolicyData =3D { 0 }; + +/** + Initilize Intel Cpu DXE Platform Policy + + @param[in] ImageHandle Image handle of this driver. + + @retval EFI_SUCCESS Initialization complete. + @exception EFI_UNSUPPORTED The chipset is unsupported by this driver. + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver. + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally. +**/ +EFI_STATUS +EFIAPI +SiliconPolicyInitDxe ( + IN EFI_HANDLE ImageHandle + ) +{ + EFI_STATUS Status; + + mSiPolicyData.Revision =3D DXE_SI_POLICY_PROTOCO= L_REVISION; + + /// + /// Install the DXE_SI_POLICY_PROTOCOL interface + /// + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &ImageHandle, + &gDxeSiPolicyProtocolGuid, + &mSiPolicyData, + NULL + ); + ASSERT_EFI_ERROR (Status); + return Status; +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/= AMLUPD.asl b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/= AMLUPD.asl new file mode 100644 index 0000000000..7e44f5585a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/AMLUPD.= asl @@ -0,0 +1,20 @@ +/** @file + ACPI DSDT table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +//////////////////////////////////////////////////////////////////////////= ///////// +//Values are set like this to have ASL compiler reserve enough space for o= bjects +//////////////////////////////////////////////////////////////////////////= ///////// +// +// Available Sleep states +// +Name(SS1,0) +Name(SS2,0) +Name(SS3,1) +Name(SS4,1) + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/= DSDT.ASL b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DS= DT.ASL new file mode 100644 index 0000000000..dd85f07bd2 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/DSDT.ASL @@ -0,0 +1,37 @@ +/** @file + ACPI DSDT table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PlatformBoardId.h" + +DefinitionBlock ( + "DSDT.aml", + "DSDT", + 0x02, // DSDT revision. + // A Revision field value greater than or equal to 2 signifies tha= t integers + // declared within the Definition Block are to be evaluated as 64-= bit values + "INTEL", // OEM ID (6 byte string) + "WHL ",// OEM table ID (8 byte string) + 0x0 // OEM version of DSDT table (4 byte Integer) +) + +// BEGIN OF ASL SCOPE +{ + // Miscellaneous services enabled in Project + Include ("AMLUPD.asl") + Include ("PciTree.asl") + Include ("Platform.asl") + + Name(\_S0, Package(4){0x0,0x0,0,0}) // mandatory System state + if(SS1) { Name(\_S1, Package(4){0x1,0x0,0,0})} + if(SS3) { Name(\_S3, Package(4){0x5,0x0,0,0})} + if(SS4) { Name(\_S4, Package(4){0x6,0x0,0,0})} + Name(\_S5, Package(4){0x7,0x0,0,0}) // mandatory System state + +}// End of ASL File + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/= HostBus.asl b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt= /HostBus.asl new file mode 100644 index 0000000000..aa302b6e3b --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/HostBus= .asl @@ -0,0 +1,516 @@ +/** @file + This file contains the SystemAgent PCI Configuration space + definition. + It defines various System Agent PCI Configuration Space registers + which will be used to dynamically produce all resources in the Host Bus. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// Define various System Agent (SA) PCI Configuration Space +// registers which will be used to dynamically produce all +// resources in the Host Bus _CRS. +// +OperationRegion (HBUS, PCI_Config, 0x00, 0x100) +Field (HBUS, DWordAcc, NoLock, Preserve) +{ + Offset(0x40), // EPBAR (0:0:0:40) + EPEN, 1, // Enable + , 11, + EPBR, 20, // EPBAR [31:12] + + Offset(0x48), // MCHBAR (0:0:0:48) + MHEN, 1, // Enable + , 14, + MHBR, 17, // MCHBAR [31:15] + + Offset(0x50), // GGC (0:0:0:50) + GCLK, 1, // GGCLCK + + Offset(0x54), // DEVEN (0:0:0:54) + D0EN, 1, // DEV0 Enable + D1F2, 1, // DEV1 FUN2 Enable + D1F1, 1, // DEV1 FUN1 Enable + D1F0, 1, // DEV1 FUN0 Enable + + Offset(0x60), // PCIEXBAR (0:0:0:60) + PXEN, 1, // Enable + PXSZ, 2, // PCI Express Size + , 23, + PXBR, 6, // PCI Express BAR [31:26] + + Offset(0x68), // DMIBAR (0:0:0:68) + DIEN, 1, // Enable + , 11, + DIBR, 20, // DMIBAR [31:12] + + Offset(0x70), // MESEG_BASE (0:0:0:70) + , 20, + MEBR, 12, // MESEG_BASE [31:20] + + Offset(0x80), // PAM0 Register (0:0:0:80) + PMLK, 1, // PAM Lock bit. + , 3, + PM0H, 2, // PAM 0, High Nibble + , 2, + + Offset(0x81), // PAM1 Register (0:0:0:81) + PM1L, 2, // PAM1, Low Nibble + , 2, + PM1H, 2, // PAM1, High Nibble + , 2, + + Offset(0x82), // PAM2 Register (0:0:0:82) + PM2L, 2, // PAM2, Low Nibble + , 2, + PM2H, 2, // PAM2, High Nibble + , 2, + + Offset(0x83), // PAM3 Register (0:0:0:83) + PM3L, 2, // PAM3, Low Nibble + , 2, + PM3H, 2, // PAM3, High Nibble + , 2, + + Offset(0x84), // PAM4 Register (0:0:0:84) + PM4L, 2, // PAM4, Low Nibble + , 2, + PM4H, 2, // PAM4, High Nibble + , 2, + + Offset(0x85), // PAM5 Register (0:0:0:85) + PM5L, 2, // PAM5, Low Nibble + , 2, + PM5H, 2, // PAM5, High Nibble + , 2, + + Offset(0x86), // PAM6 Register (0:0:0:86) + PM6L, 2, // PAM6, Low Nibble + , 2, + PM6H, 2, // PAM6, High Nibble + , 2, + + Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8) + , 20, + TUUD, 19, // TOUUD [38:20] + + Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC) + , 20, + TLUD, 12, // TOLUD [31:20] + + Offset(0xC8), // ERRSTS register (0:0:0:C8) + , 7, + HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR +} + +// +// Define a buffer that will store all the bus, memory, and IO information +// relating to the Host Bus. This buffer will be dynamically altered in +// the _CRS and passed back to the OS. +// +Name(BUF0,ResourceTemplate() +{ + // + // Bus Number Allocation: Bus 0 to 0xFF + // + WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00, + 0x0000,0x00FF,0x00,0x0100,,,PB00) + + // + // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 ) + // + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00) + + // + // PCI Configuration Registers ( 0x0CF8 - 0x0CFF ) + // + Io(Decode16,0x0CF8,0x0CF8,1,0x08) + + // + // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF ) + // + DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange, + 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01) + + // + // Video Buffer Area ( 0xA0000 - 0xBFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000) + + // + // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000) + + // + // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400) + + // + // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800) + + // + // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00) + + // + // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000) + + // + // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400) + + // + // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800) + + // + // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00) + + // + // BIOS Extension Area ( 0xE0000 - 0xE3FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000) + + // + // BIOS Extension Area ( 0xE4000 - 0xE7FFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400) + + // + // BIOS Extension Area ( 0xE8000 - 0xEBFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800) + + // + // BIOS Extension Area ( 0xEC000 - 0xEFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00) + + // + // BIOS Area ( 0xF0000 - 0xFFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, + ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000) + +// // +// // Memory Hole Region ( 0xF00000 - 0xFFFFFF ) +// // +// DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable, +// ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE) + + // + // PCI Memory Region ( TOLUD - 0xDFFFFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, + ReadWrite,0x00,0x00000000,0xDFFFFFFF,0x00,0xE0000000,,,PM01) + + // + // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) ) + // (This is dummy range for OS compatibility, will patch it in _CRS) + // + QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, + ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02) + + // + // PCH reserved resources ( 0xFC800000 - 0xFE7FFFFF ) + // + DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable, + ReadWrite,0x00,0xFC800000,0xFE7FFFFF,0x00,0x2000000,,,PM03) +}) + +Name(EP_B, 0) // to store EP BAR +Name(MH_B, 0) // to store MCH BAR +Name(PC_B, 0) // to store PCIe BAR +Name(PC_L, 0) // to store PCIe BAR Length +Name(DM_B, 0) // to store DMI BAR + +// +// Get EP BAR +// +Method(GEPB,0,Serialized) +{ + if(LEqual(EP_B,0)) + { + ShiftLeft(\_SB.PCI0.EPBR,12,EP_B) + } + Return(EP_B) +} + +// +// Get MCH BAR +// +Method(GMHB,0,Serialized) +{ + if(LEqual(MH_B,0)) + { + ShiftLeft(\_SB.PCI0.MHBR,15,MH_B) + } + Return(MH_B) +} + +// +// Get PCIe BAR +// +Method(GPCB,0,Serialized) +{ + if(LEqual(PC_B,0)) + { + ShiftLeft(\_SB.PCI0.PXBR,26,PC_B) + } + Return(PC_B) +} + +// +// Get PCIe Length +// +Method(GPCL,0,Serialized) +{ + if(LEqual(PC_L,0)) { + ShiftRight(0x10000000, \_SB.PCI0.PXSZ,PC_L) + } + Return(PC_L) +} + +// +// Get DMI BAR +// +Method(GDMB,0,Serialized) +{ + if(LEqual(DM_B,0)) + { + ShiftLeft(\_SB.PCI0.DIBR,12,DM_B) + } + Return(DM_B) +} + + +Method(_CRS,0,Serialized) +{ + // + // Fix up Max Bus Number and Length + // + Store(\_SB.PCI0.GPCL(),Local0) + CreateWordField(BUF0, ^PB00._MAX, PBMX) + Store(Subtract(ShiftRight(Local0,20),2), PBMX) + CreateWordField(BUF0, ^PB00._LEN, PBLN) + Store(Subtract(ShiftRight(Local0,20),1), PBLN) + // + // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF. + // + If(PM1L) // \_SB.PCI0 + { + // PAMx !=3D 0. Set length =3D 0. + + CreateDwordField(BUF0, ^C000._LEN,C0LN) + Store(Zero,C0LN) + } + + If(LEqual(PM1L,1)) + { + CreateBitField(BUF0, ^C000._RW,C0RW) + Store(Zero,C0RW) + } + + If(PM1H) + { + CreateDwordField(BUF0, ^C400._LEN,C4LN) + Store(Zero,C4LN) + } + + If(LEqual(PM1H,1)) + { + CreateBitField(BUF0, ^C400._RW,C4RW) + Store(Zero,C4RW) + } + + If(PM2L) + { + CreateDwordField(BUF0, ^C800._LEN,C8LN) + Store(Zero,C8LN) + } + + If(LEqual(PM2L,1)) + { + CreateBitField(BUF0, ^C800._RW,C8RW) + Store(Zero,C8RW) + } + + If(PM2H) + { + CreateDwordField(BUF0, ^CC00._LEN,CCLN) + Store(Zero,CCLN) + } + + If(LEqual(PM2H,1)) + { + CreateBitField(BUF0, ^CC00._RW,CCRW) + Store(Zero,CCRW) + } + + If(PM3L) + { + CreateDwordField(BUF0, ^D000._LEN,D0LN) + Store(Zero,D0LN) + } + + If(LEqual(PM3L,1)) + { + CreateBitField(BUF0, ^D000._RW,D0RW) + Store(Zero,D0RW) + } + + If(PM3H) + { + CreateDwordField(BUF0, ^D400._LEN,D4LN) + Store(Zero,D4LN) + } + + If(LEqual(PM3H,1)) + { + CreateBitField(BUF0, ^D400._RW,D4RW) + Store(Zero,D4RW) + } + + If(PM4L) + { + CreateDwordField(BUF0, ^D800._LEN,D8LN) + Store(Zero,D8LN) + } + + If(LEqual(PM4L,1)) + { + CreateBitField(BUF0, ^D800._RW,D8RW) + Store(Zero,D8RW) + } + + If(PM4H) + { + CreateDwordField(BUF0, ^DC00._LEN,DCLN) + Store(Zero,DCLN) + } + + If(LEqual(PM4H,1)) + { + CreateBitField(BUF0, ^DC00._RW,DCRW) + Store(Zero,DCRW) + } + + If(PM5L) + { + CreateDwordField(BUF0, ^E000._LEN,E0LN) + Store(Zero,E0LN) + } + + If(LEqual(PM5L,1)) + { + CreateBitField(BUF0, ^E000._RW,E0RW) + Store(Zero,E0RW) + } + + If(PM5H) + { + CreateDwordField(BUF0, ^E400._LEN,E4LN) + Store(Zero,E4LN) + } + + If(LEqual(PM5H,1)) + { + CreateBitField(BUF0, ^E400._RW,E4RW) + Store(Zero,E4RW) + } + + If(PM6L) + { + CreateDwordField(BUF0, ^E800._LEN,E8LN) + Store(Zero,E8LN) + } + + If(LEqual(PM6L,1)) + { + CreateBitField(BUF0, ^E800._RW,E8RW) + Store(Zero,E8RW) + } + + If(PM6H) + { + CreateDwordField(BUF0, ^EC00._LEN,ECLN) + Store(Zero,ECLN) + } + + If(LEqual(PM6H,1)) + { + CreateBitField(BUF0, ^EC00._RW,ECRW) + Store(Zero,ECRW) + } + + If(PM0H) + { + CreateDwordField(BUF0, ^F000._LEN,F0LN) + Store(Zero,F0LN) + } + + If(LEqual(PM0H,1)) + { + CreateBitField(BUF0, ^F000._RW,F0RW) + Store(Zero,F0RW) + } + + // + // Create pointers to Memory Sizing values. + // + CreateDwordField(BUF0, ^PM01._MIN,M1MN) + CreateDwordField(BUF0, ^PM01._MAX,M1MX) + CreateDwordField(BUF0, ^PM01._LEN,M1LN) + + // + // Set Memory Size Values. TLUD represents bits 31:20 of phyical + // TOM, so shift these bits into the correct position and fix up + // the Memory Region available to PCI. + // + Store (0x50800000, M1LN) + Store (0x8F800000, M1MN) + Subtract (Add (M1MN, M1LN), 1, M1MX) + + // + // Create pointers to Memory Sizing values. + // Patch PM02 range basing on memory size and OS type + // + CreateQwordField(BUF0, ^PM02._LEN,MSLN) + // + // Set resource length to 0 + // + Store (0, MSLN) + + D8XH (0, 0xC5) + D8XH (1, 0xAA) + + Return(BUF0) +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/= PciTree.asl b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt= /PciTree.asl new file mode 100644 index 0000000000..ff3b0dbe08 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciTree= .asl @@ -0,0 +1,309 @@ +/** @file + ACPI DSDT table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +Scope(\_SB) { + Name(PD00, Package(){ +// If the setting changed in PCH PxRcConfig policy, platform should also u= pdate static assignment here. +// PCI Bridge +// D31: cAVS, SMBus, GbE, Nothpeak + Package(){0x001FFFFF, 0, 0, 11 }, + Package(){0x001FFFFF, 1, 0, 10 }, + Package(){0x001FFFFF, 2, 0, 11 }, + Package(){0x001FFFFF, 3, 0, 11 }, +// D30: SerialIo and SCS - can't use PIC +// D29: PCI Express Port 9-16 + Package(){0x001DFFFF, 0, 0, 11 }, + Package(){0x001DFFFF, 1, 0, 10 }, + Package(){0x001DFFFF, 2, 0, 11 }, + Package(){0x001DFFFF, 3, 0, 11 }, +// D28: PCI Express Port 1-8 + Package(){0x001CFFFF, 0, 0, 11 }, + Package(){0x001CFFFF, 1, 0, 10 }, + Package(){0x001CFFFF, 2, 0, 11 }, + Package(){0x001CFFFF, 3, 0, 11 }, +// D27: PCI Express Port 17-20 + Package(){0x001BFFFF, 0, 0, 11 }, + Package(){0x001BFFFF, 1, 0, 10 }, + Package(){0x001BFFFF, 2, 0, 11 }, + Package(){0x001BFFFF, 3, 0, 11 }, +// D25: SerialIo - can't use PIC +// D23: SATA controller + Package(){0x0017FFFF, 0, 0, 11 }, +// D22: CSME (HECI, IDE-R, Keyboard and Text redirection + Package(){0x0016FFFF, 0, 0, 11 }, + Package(){0x0016FFFF, 1, 0, 10 }, + Package(){0x0016FFFF, 2, 0, 11 }, + Package(){0x0016FFFF, 3, 0, 11 }, +// D21: SerialIo - can't use PIC +// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller +// D20: xHCI, OTG, CNVi WiFi, SDcard + Package(){0x0014FFFF, 0, 0, 11 }, + Package(){0x0014FFFF, 1, 0, 10 }, + Package(){0x0014FFFF, 2, 0, 11 }, + Package(){0x0014FFFF, 3, 0, 11 }, +// D19: Integrated Sensor Hub - can't use PIC +// D18: Thermal, UFS, SerialIo SPI2 - can't use PIC + Package(){0x0012FFFF, 0, 0, 11 }, + Package(){0x0012FFFF, 1, 0, 10 }, + Package(){0x0012FFFF, 2, 0, 11 }, + Package(){0x0012FFFF, 3, 0, 11 }, + +// Host Bridge +// P.E.G. Root Port D1F0 + Package(){0x0001FFFF, 0, 0, 11 }, + Package(){0x0001FFFF, 1, 0, 10 }, + Package(){0x0001FFFF, 2, 0, 11 }, + Package(){0x0001FFFF, 3, 0, 11 }, +// P.E.G. Root Port D1F1 +// P.E.G. Root Port D1F2 +// SA IGFX Device + Package(){0x0002FFFF, 0, 0, 11 }, +// SA Thermal Device + Package(){0x0004FFFF, 0, 0, 11 }, +// SA IPU Device + Package(){0x0005FFFF, 0, 0, 11 }, +// SA GNA Device + Package(){0x0008FFFF, 0, 0, 11 }, + }) + Name(AR00, Package(){ +// PCI Bridge +// D31: cAVS, SMBus, GbE, Nothpeak + Package(){0x001FFFFF, 0, 0, 16 }, + Package(){0x001FFFFF, 1, 0, 17 }, + Package(){0x001FFFFF, 2, 0, 18 }, + Package(){0x001FFFFF, 3, 0, 19 }, +// D30: SerialIo and SCS + Package(){0x001EFFFF, 0, 0, 20 }, + Package(){0x001EFFFF, 1, 0, 21 }, + Package(){0x001EFFFF, 2, 0, 22 }, + Package(){0x001EFFFF, 3, 0, 23 }, +// D29: PCI Express Port 9-16 + Package(){0x001DFFFF, 0, 0, 16 }, + Package(){0x001DFFFF, 1, 0, 17 }, + Package(){0x001DFFFF, 2, 0, 18 }, + Package(){0x001DFFFF, 3, 0, 19 }, +// D28: PCI Express Port 1-8 + Package(){0x001CFFFF, 0, 0, 16 }, + Package(){0x001CFFFF, 1, 0, 17 }, + Package(){0x001CFFFF, 2, 0, 18 }, + Package(){0x001CFFFF, 3, 0, 19 }, +// D27: PCI Express Port 17-20 + Package(){0x001BFFFF, 0, 0, 16 }, + Package(){0x001BFFFF, 1, 0, 17 }, + Package(){0x001BFFFF, 2, 0, 18 }, + Package(){0x001BFFFF, 3, 0, 19 }, +// D26: eMMC + Package(){0x001AFFFF, 0, 0, 16 }, + Package(){0x001AFFFF, 1, 0, 17 }, + Package(){0x001AFFFF, 2, 0, 18 }, + Package(){0x001AFFFF, 3, 0, 19 }, +// D25: SerialIo + Package(){0x0019FFFF, 0, 0, 32 }, + Package(){0x0019FFFF, 1, 0, 33 }, + Package(){0x0019FFFF, 2, 0, 34 }, +// D23: SATA controller + Package(){0x0017FFFF, 0, 0, 16 }, +// D22: CSME (HECI, IDE-R, Keyboard and Text redirection + Package(){0x0016FFFF, 0, 0, 16 }, + Package(){0x0016FFFF, 1, 0, 17 }, + Package(){0x0016FFFF, 2, 0, 18 }, + Package(){0x0016FFFF, 3, 0, 19 }, +// D21: SerialIo + Package(){0x0015FFFF, 0, 0, 16 }, + Package(){0x0015FFFF, 1, 0, 17 }, + Package(){0x0015FFFF, 2, 0, 18 }, + Package(){0x0015FFFF, 3, 0, 19 }, +// D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller +// D20: xHCI, OTG, CNVi WiFi, SDcard + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, +// D19: Integrated Sensor Hub + Package(){0x0013FFFF, 0, 0, 20 }, +// D18: Thermal, UFS, SerialIo SPI 2 + Package(){0x0012FFFF, 0, 0, 16 }, + Package(){0x0012FFFF, 1, 0, 24 }, + Package(){0x0012FFFF, 2, 0, 18 }, + Package(){0x0012FFFF, 3, 0, 19 }, + +// Host Bridge +// P.E.G. Root Port D1F0 + Package(){0x0001FFFF, 0, 0, 16 }, + Package(){0x0001FFFF, 1, 0, 17 }, + Package(){0x0001FFFF, 2, 0, 18 }, + Package(){0x0001FFFF, 3, 0, 19 }, +// P.E.G. Root Port D1F1 +// P.E.G. Root Port D1F2 +// SA IGFX Device + Package(){0x0002FFFF, 0, 0, 16 }, +// SA Thermal Device + Package(){0x0004FFFF, 0, 0, 16 }, +// SA IPU Device + Package(){0x0005FFFF, 0, 0, 16 }, +// SA GNA Device + Package(){0x0008FFFF, 0, 0, 16 }, + }) + Name(PD04, Package(){ + Package(){0x0000FFFF, 0, 0, 11 }, + Package(){0x0000FFFF, 1, 0, 10 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 11 }, + }) + Name(AR04, Package(){ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + Name(PD05, Package(){ + Package(){0x0000FFFF, 0, 0, 10 }, + Package(){0x0000FFFF, 1, 0, 11 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 11 }, + }) + Name(AR05, Package(){ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + Name(PD06, Package(){ + Package(){0x0000FFFF, 0, 0, 11 }, + Package(){0x0000FFFF, 1, 0, 11 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 10 }, + }) + Name(AR06, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + Name(PD07, Package(){ + Package(){0x0000FFFF, 0, 0, 11 }, + Package(){0x0000FFFF, 1, 0, 11 }, + Package(){0x0000FFFF, 2, 0, 10 }, + Package(){0x0000FFFF, 3, 0, 11 }, + }) + Name(AR07, Package(){ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + Name(PD08, Package(){ + Package(){0x0000FFFF, 0, 0, 11 }, + Package(){0x0000FFFF, 1, 0, 10 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 11 }, + }) + Name(AR08, Package(){ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + Name(PD09, Package(){ + Package(){0x0000FFFF, 0, 0, 10 }, + Package(){0x0000FFFF, 1, 0, 11 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 11 }, + }) + Name(AR09, Package(){ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + Name(PD0E, Package(){ + Package(){0x0000FFFF, 0, 0, 11 }, + Package(){0x0000FFFF, 1, 0, 11 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 10 }, + }) + Name(AR0E, Package(){ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + Name(PD0F, Package(){ + Package(){0x0000FFFF, 0, 0, 11 }, + Package(){0x0000FFFF, 1, 0, 11 }, + Package(){0x0000FFFF, 2, 0, 10 }, + Package(){0x0000FFFF, 3, 0, 11 }, + }) + Name(AR0F, Package(){ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + Name(PD02, Package(){ + Package(){0x0000FFFF, 0, 0, 11 }, + Package(){0x0000FFFF, 1, 0, 10 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 11 }, + }) + Name(AR02, Package(){ +// P.E.G. Port Slot x16 + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + Name(PD0A, Package(){ +// P.E.G. Port Slot x8 + Package(){0x0000FFFF, 0, 0, 10 }, + Package(){0x0000FFFF, 1, 0, 11 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 11 }, + }) + Name(AR0A, Package(){ +// P.E.G. Port Slot x8 + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + Name(PD0B, Package(){ +// P.E.G. Port Slot x4 + Package(){0x0000FFFF, 0, 0, 11 }, + Package(){0x0000FFFF, 1, 0, 11 }, + Package(){0x0000FFFF, 2, 0, 11 }, + Package(){0x0000FFFF, 3, 0, 10 }, + }) + Name(AR0B, Package(){ +// P.E.G. Port Slot x4 + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + +//------------------------------------------------------------------------= --- +// Begin PCI tree object scope +//------------------------------------------------------------------------= --- + Device(PCI0) { // PCI Bridge "Host Bridge" + Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 hos= t hierarchy + Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't und= erstand the new HID + Name(_SEG, 0) + Name(_ADR, 0x00000000) + Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for = Peer PCI busses. Name can be overriden with control method placed directly = under Device scope + Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root= PCI Bus + Name(_UID, 0x0000) // Unique Bus ID, optional + Method(_PRT,0) { + If(PICM) {Return(AR00)} // APIC mode + Return (PD00) // PIC Mode + } // end _PRT + + Include("HostBus.asl") + } // end PCI0 Bridge "Host Bridge" +} // end _SB scope + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/= Platform.asl b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsd= t/Platform.asl new file mode 100644 index 0000000000..951c01455f --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Platfor= m.asl @@ -0,0 +1,76 @@ +/** @file + ACPI DSDT table + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// Define Port 80 as an ACPI Operating Region to use for debugging. Please +// note that the Intel CRBs have the ability to ouput a Word to +// Port 80h for debugging purposes, so the model implemented here may not = be +// able to be used on OEM Designs. + +OperationRegion(PRT0,SystemIO,0x80,2) +Field(PRT0,WordAcc,Lock,Preserve) +{ + P80B, 16 +} + +// Port 80h Update: +// Update 2 bytes of Port 80h. +// +// Arguments: +// Arg0: 0 =3D Write Port 80h +// 1 =3D Write Port 81h +// Arg1: 8-bit Value to write +// +// Return Value: +// None + +Name(P80T, 0) // temp buffer for P80 + +Method(D8XH,2,Serialized) +{ + If(LEqual(Arg0,0)) // Write Port 80h + { + Store(Or(And(P80T,0xFF00),Arg1),P80T) + } + If(LEqual(Arg0,1)) // Write Port 81h + { + Store(Or(And(P80T,0x00FF),ShiftLeft(Arg1,8)),P80T) + } + Store(P80T,P80B) +} + +// +// Define SW SMI port as an ACPI Operating Region to use for generate SW S= MI. +// +OperationRegion(SPRT,SystemIO, 0xB2,2) +Field (SPRT, ByteAcc, Lock, Preserve) { + SSMP, 8 +} + +// The _PIC Control Method is optional for ACPI design. It allows the +// OS to inform the ASL code which interrupt controller is being used, +// the 8259 or APIC. The reference code in this document will address +// PCI IRQ Routing and resource allocation for both cases. +// +// The values passed into _PIC are: +// 0 =3D 8259 +// 1 =3D IOAPIC + +Method(\_PIC,1) +{ + Store(Arg0,PICM) +} + +Scope (\) +{ + // + // Global Name, returns current Interrupt controller mode; + // updated from _PIC control method + // + Name(PICM, 0) +} + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/AcpiTables= /Rtd3PcieTbt.asl b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/Acpi= Tables/Rtd3PcieTbt.asl new file mode 100644 index 0000000000..38d60d6dbd --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/AcpiTables/Rtd3Pc= ieTbt.asl @@ -0,0 +1,405 @@ +/** @file + ACPI RTD3 SSDT table for SPT PCIe + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#define PID_ICC 0xDC +#define R_PCH_PCR_ICC_MSKCKRQ 0x100C = ///< Mask Control CLKREQ + +External(PCRA,MethodObj) +External(PCRO,MethodObj) +External(\MMRP, MethodObj) +External(\MMTB, MethodObj) +External(\TRDO, IntObj) +External(\TRD3, IntObj) +External(\TBPE, IntObj) +External(\TOFF, IntObj) +External(\TBSE, IntObj) +External(\TBOD, IntObj) +External(\TBRP, IntObj) +External(\TBHR, IntObj) +External(\RTBC, IntObj) +External(\TBCD, IntObj) + +Name(G2SD, 0) // Go2Sx done, set by GO2S, cleaned by _ON + +Name(WKEN, 0) + + Method(_S0W, 0) + { + /// This method returns the lowest D-state supported by PCIe root port d= uring S0 state + + ///- PMEs can be generated from D3hot for ULT + Return(4) + + /** @defgroup pcie_s0W PCIE _S0W **/ + } // End _S0W + + Method (_DSD, 0) { + Return ( + Package () { + ToUUID("6211E2C0-58A3-4AF3-90E1-927A4E0C55A4"), + Package () { + Package (2) {"HotPlugSupportInD3", 1}, + } + } + ) // End of Return () + } + + Method(_DSW, 3) + { + /// This method is used to enable/disable wake from PCIe (WKEN) + If (LGreaterEqual(Arg1, 1)) { /// If entering Sx, need to disable WA= KE# from generating runtime PME + /// Also set 2 to TOFF. + Store(0, WKEN) + Store (2, TOFF) + } Else { /// If Staying in S0 + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake + { ///- Set PME + Store(1, WKEN) + Store (1, TOFF) + } Else { ///- Disable runtime PME, either because staying in D0 or= disabling wake + Store(0, WKEN) + Store(0, TOFF) + } + } + + /** @defgroup pcie_dsw PCIE _DSW **/ + } // End _DSW + + + PowerResource(PXP, 0, 0) + { + /// Define the PowerResource for PCIe slot + /// Method: _STA(), _ON(), _OFF() + /** @defgroup pcie_pxp PCIE Power Resource **/ + + Method(_STA, 0) + { + Return(PSTA()) + } /** @defgroup pcie_sta PCIE _STA method **/ + + Method(_ON) /// Turn on core power to PCIe Slot + { + Store(1, TRDO) + PON() + Store(0, TRDO) + } /** @defgroup pcie_on PCIE _ON method **/ + + Method(_OFF) /// Turn off core power to PCIe Slot + { + Store(1, TRD3) + POFF() + Store(0, TRD3) + } // End of Method_OFF + } // End PXP + + Method(PSTA, 0) + { + /// Returns the status of PCIe slot core power + // detect power pin status + if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { + if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode + if(LEqual(\_SB.GGOV(DeRefOf(Index(PWRG, 2))),DeRefOf(Index(PWRG,= 3)))){ + Return (1) + } Else { + Return (0) + } + } // GPIO mode + if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode + if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(PWRG, 1)),DeRefOf(In= dex(PWRG, 2))),DeRefOf(Index(PWRG, 3)))){ + Return (1) + } Else { + Return (0) + } + } // IOEX mode + } + // detect reset pin status + if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { + if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode + if(LEqual(\_SB.GGOV(DeRefOf(Index(RSTG, 2))),DeRefOf(Index(RSTG,= 3)))){ + Return (1) + } Else { + Return (0) + } + } // GPIO mode + if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode + if(LEqual(\_SB.PCI0.GEXP.GEPS(DeRefOf(Index(RSTG, 1)),DeRefOf(In= dex(RSTG, 2))),DeRefOf(Index(RSTG, 3)))){ + Return (1) + } Else { + Return (0) + } + } // IOEX mode + } + Return (0) + } /** @defgroup pcie_sta PCIE _STA method **/ + + Method (SXEX, 0, Serialized) { + + Store(\MMTB(TBSE), Local7) + OperationRegion(TBDI, SystemMemory, Local7, 0x550)// TBT HR PCICFG M= MIO + Field(TBDI,DWordAcc, NoLock, Preserve) { + DIVI, 32, + CMDR, 32, + Offset(0x548), + TB2P, 32, + P2TB, 32 + } + + Store(100, Local1) + Store(0x09, P2TB) // Write SX_EXIT_TBT_CONNECTED to PCIe2TBT + While (LGreater(Local1, 0)) { + + Store(Subtract(Local1, 1), Local1) + Store(TB2P, Local2) + If (LEqual(Local2, 0xFFFFFFFF)) { // Device gone + Return() + } + If (And(Local2, 1)) { // Done + break + } + Sleep(5) + } + Store(0x0, P2TB) // Write 0 to PCIe2TBT + + // Fast Link bring-up flow + Store(500, Local1) + While (LGreater(Local1, 0)) { + Store(Subtract(Local1, 1), Local1) + Store(TB2P, Local2) + If (LEqual(Local2, 0xFFFFFFFF)) {// Device gone + Return() + } + If (LNotEqual(DIVI, 0xFFFFFFFF)) { + break + } + Sleep(10) + } + } // End of Method(SXEX, 0, Serialized) + + Method(PON) /// Turn on core power to PCIe Slot + { + + Store(\MMRP(\TBSE), Local7) + OperationRegion(L23P,SystemMemory,Local7,0xE4) + Field(L23P,WordAcc, NoLock, Preserve) + { + Offset(0xA4),// PMCSR + PSD0, 2, // PowerState + Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable + , 2, + L2TE, 1, // 2, L23_Rdy Entry Request (L23ER) + L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) + } + + Store(\MMTB(\TBSE), Local6) + OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG M= MIO + Field(TBDI,DWordAcc, NoLock, Preserve) { + DIVI, 32, + CMDR, 32, + Offset(0xA4), + TBPS, 2, // PowerState of TBT + Offset(0x548), + TB2P, 32, + P2TB, 32 + } + + Store(0, TOFF) + // Check RTD3 power enable, if already ON, no need to execute sx_exit + If (TBPE) { + Return() + } + + Store(0,G2SD) + If (\RTBC) { + /// de-assert CLK_REQ MSK + if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enab= led + PCRA(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,Not(DeRefOf(Index(SCLK, 1))))= // And ~SCLK to clear bit + } + Sleep(\TBCD) + } + + /// Turn ON Power for PCIe Slot + if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled + if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode + \_SB.SGOV(DeRefOf(Index(PWRG, 2)),DeRefOf(Index(PWRG, 3))) + Store(1, TBPE) + Sleep(PEP0) /// Sleep for programmable delay + } + if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode + \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, = 2)),DeRefOf(Index(PWRG, 3))) + Store(1, TBPE) + Sleep(PEP0) /// Sleep for programmable delay + } + } + + /// De-Assert Reset Pin + if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled + if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode + \_SB.SGOV(DeRefOf(Index(RSTG, 2)),DeRefOf(Index(RSTG, 3))) + } + if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode + \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, = 2)),DeRefOf(Index(RSTG, 3))) + } + } + + /// Clear DLSULPPGE, then set L23_Rdy to Detect Transition (L23R2DT) + Store(0, DPGE) + Store(1, L2TR) + Sleep(16) + Store(0, Local0) + /// Wait up to 12 ms for transition to Detect + While(L2TR) { + If(Lgreater(Local0, 4)) // Debug - Wait for 5 ms + { + Break + } + Sleep(16) + Increment(Local0) + } + /// Once in Detect, wait up to 124 ms for Link Active (typically hap= pens in under 70ms) + /// Worst case per PCIe spec from Detect to Link Active is: + /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config = (24+2+2+2+2) + Store(1, DPGE) + Store(0, Local0) + While(LEqual(LASX,0)) { + If(Lgreater(Local0, 8)) + { + Break + } + Sleep(16) + Increment(Local0) + } + Store(0, LEDM) /// Set PCIEDBG.DMIL1EDM (324[3]) =3D 0 + + // TBT special sleep. + Store(PSD0, Local1) + Store(0, PSD0)// D0 + Store(20, Local2) // Poll for TBT, up to 200 ms + + While (LGreater(Local2, 0)) { + Store(Subtract(Local2, 1), Local2) + Store(TB2P, Local3) + If (LNotEqual(Local3, 0xFFFFFFFF)) { // Done + break + } + Sleep(10) + } + + If (LLessEqual(Local2, 0)) { + } + SXEX() + Store(Local1, PSD0) // Back to Local1 + } /** @defgroup pcie_on PCIE _ON method **/ + + Method(POFF) { /// Turn off core power to PCIe Slot + If (LEqual(TOFF, 0)) { + Return() + } + Store(\MMRP(\TBSE), Local7) + OperationRegion(L23P, SystemMemory, Local7, 0xE4) + Field(L23P,WordAcc, NoLock, Preserve) + { + Offset(0xA4),// PMCSR + PSD0, 2, // PowerState + Offset(0xE2),// 0xE2, RPPGEN - Root Port Power Gating Enable + , 2, + L2TE, 1, // 2, L23_Rdy Entry Request (L23ER) + L2TR, 1, // 3, L23_Rdy to Detect Transition (L23R2DT) + } + + Store(\MMTB(TBSE), Local6) + OperationRegion(TBDI, SystemMemory, Local6, 0x550)// TBT HR PCICFG M= MIO + Field(TBDI,DWordAcc, NoLock, Preserve) { + DIVI, 32, + CMDR, 32, + Offset(0xA4), + TBPS, 2, // PowerState of TBT + Offset(0x548), + TB2P, 32, + P2TB, 32 + } + + Store(PSD0, Local1) + Store(0, PSD0)// D0 + + Store(P2TB, Local3) + + If (Lgreater(TOFF, 1)) { + Sleep(10) + Store(Local1, PSD0) // Back to Local1 + Return() + } + Store(0, TOFF) + + Store(Local1, PSD0) // Back to Local1 + + /// Set L23_Rdy Entry Request (L23ER) + Store(1, L2TE) + Sleep(16) + Store(0, Local0) + While(L2TE) { + If(Lgreater(Local0, 4)) /// Debug - Wait for 5 ms + { + Break + } + Sleep(16) + Increment(Local0) + } + Store(1, LEDM) /// PCIEDBG.DMIL1EDM (324[3]) =3D 1 + + /// Assert Reset Pin + if(LNotEqual(DeRefOf(Index(RSTG, 0)),0)) { // if reset pin enabled + if(LEqual(DeRefOf(Index(RSTG, 0)),1)) { // GPIO mode + \_SB.SGOV(DeRefOf(Index(RSTG, 2)),Xor(DeRefOf(Index(RSTG, 3)),1)) + } + if(LEqual(DeRefOf(Index(RSTG, 0)),2)) { // IOEX mode + \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(RSTG, 1)),DeRefOf(Index(RSTG, = 2)),Xor(DeRefOf(Index(RSTG, 3)),1)) + } + } + If (\RTBC) { + /// assert CLK_REQ MSK + if(LNotEqual(DeRefOf(Index(SCLK, 0)),0)) { // if power gating enab= led + PCRO(PID_ICC,R_PCH_PCR_ICC_MSKCKRQ,DeRefOf(Index(SCLK, 1))) /= / Or SCLK to set bit + Sleep(16) + } + } + + /// Power OFF for TBT + if(LNotEqual(DeRefOf(Index(PWRG, 0)),0)) { // if power gating enabled + if(LEqual(DeRefOf(Index(PWRG, 0)),1)) { // GPIO mode + \_SB.SGOV(DeRefOf(Index(PWRG, 2)),Xor(DeRefOf(Index(PWRG, 3)),1)) + } + if(LEqual(DeRefOf(Index(PWRG, 0)),2)) { // IOEX mode + \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(PWRG, 1)),DeRefOf(Index(PWRG, = 2)),Xor(DeRefOf(Index(PWRG, 3)),1)) + } + } + + Store(0, TBPE) + + Store(1, LDIS) /// Set Link Disable + Store(0, LDIS) /// Toggle link disable + + /// enable WAKE + If (WKEN) { + If (LNotEqual(DeRefOf(Index(WAKG, 0)),0)) { // if power gating ena= bled + If (LEqual(DeRefOf(Index(WAKG, 0)),1)) { // GPIO mode + \_SB.SGOV(DeRefOf(Index(WAKG, 2)),DeRefOf(Index(WAKG, 3))) + \_SB.SHPO(DeRefOf(Index(WAKG, 2)), 0) // set gpio ownership to= ACPI(0=3DACPI mode, 1=3DGPIO mode) + } + If (LEqual(DeRefOf(Index(WAKG, 0)),2)) { // IOEX mode + \_SB.PCI0.GEXP.SGEP(DeRefOf(Index(WAKG, 1)),DeRefOf(Index(WAKG= , 2)),DeRefOf(Index(WAKG, 3))) + } + } + } + Sleep(\TBOD) + /** @defgroup pcie_off PCIE _OFF method **/ + } // End of Method_OFF + + Name(_PR0, Package(){PXP}) + Name(_PR3, Package(){PXP}) + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/AcpiTables= /Tbt.asl b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/AcpiTables/T= bt.asl new file mode 100644 index 0000000000..66584c21c5 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/AcpiTables/Tbt.asl @@ -0,0 +1,1877 @@ +/** @file + Thunderbolt ACPI methods + + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#define DTBT_CONTROLLER 0x00 +#define DTBT_TYPE_PCH 0x01 +#define DTBT_TYPE_PEG 0x02 +#define DTBT_SMI_HANDLER_NUMBER 0xF7 +#define TBT_SMI_ENUMERATION_FUNCTION 21 +#define TBT_SMI_RESET_SWITCH_FUNCTION 22 +#define TBT_SMI_DISABLE_MSI_FUNCTION 23 +#ifndef BIT29 +#define BIT29 0x20000000 +#endif + +Name(LDLY, 300) //300 ms +Name (TNVB, 0xFFFF0000) // TBT NVS Base address +Name (TNVL, 0xAA55) // TBT NVS Length +Include ("Acpi/TbtNvs.asl") + +External(\_SB.PCI0.RP02.L23D, MethodObj) +External(\_SB.PCI0.RP03.L23D, MethodObj) +External(\_SB.PCI0.RP04.L23D, MethodObj) +External(\_SB.PCI0.RP05.L23D, MethodObj) +External(\_SB.PCI0.RP06.L23D, MethodObj) +External(\_SB.PCI0.RP07.L23D, MethodObj) +External(\_SB.PCI0.RP08.L23D, MethodObj) +External(\_SB.PCI0.RP09.L23D, MethodObj) +External(\_SB.PCI0.RP10.L23D, MethodObj) +External(\_SB.PCI0.RP11.L23D, MethodObj) +External(\_SB.PCI0.RP12.L23D, MethodObj) +External(\_SB.PCI0.RP13.L23D, MethodObj) +External(\_SB.PCI0.RP14.L23D, MethodObj) +External(\_SB.PCI0.RP15.L23D, MethodObj) +External(\_SB.PCI0.RP16.L23D, MethodObj) +External(\_SB.PCI0.RP17.L23D, MethodObj) +External(\_SB.PCI0.RP18.L23D, MethodObj) +External(\_SB.PCI0.RP19.L23D, MethodObj) +External(\_SB.PCI0.RP20.L23D, MethodObj) +External(\_SB.PCI0.RP21.L23D, MethodObj) +External(\_SB.PCI0.RP22.L23D, MethodObj) +External(\_SB.PCI0.RP23.L23D, MethodObj) +External(\_SB.PCI0.RP24.L23D, MethodObj) + +External(\_SB.PCI0.RP01.DL23, MethodObj) +External(\_SB.PCI0.RP02.DL23, MethodObj) +External(\_SB.PCI0.RP03.DL23, MethodObj) +External(\_SB.PCI0.RP04.DL23, MethodObj) +External(\_SB.PCI0.RP05.DL23, MethodObj) +External(\_SB.PCI0.RP06.DL23, MethodObj) +External(\_SB.PCI0.RP07.DL23, MethodObj) +External(\_SB.PCI0.RP08.DL23, MethodObj) +External(\_SB.PCI0.RP09.DL23, MethodObj) +External(\_SB.PCI0.RP10.DL23, MethodObj) +External(\_SB.PCI0.RP11.DL23, MethodObj) +External(\_SB.PCI0.RP12.DL23, MethodObj) +External(\_SB.PCI0.RP13.DL23, MethodObj) +External(\_SB.PCI0.RP14.DL23, MethodObj) +External(\_SB.PCI0.RP15.DL23, MethodObj) +External(\_SB.PCI0.RP16.DL23, MethodObj) +External(\_SB.PCI0.RP17.DL23, MethodObj) +External(\_SB.PCI0.RP18.DL23, MethodObj) +External(\_SB.PCI0.RP19.DL23, MethodObj) +External(\_SB.PCI0.RP20.DL23, MethodObj) +External(\_SB.PCI0.RP21.DL23, MethodObj) +External(\_SB.PCI0.RP22.DL23, MethodObj) +External(\_SB.PCI0.RP23.DL23, MethodObj) +External(\_SB.PCI0.RP24.DL23, MethodObj) + +External(\_SB.PCI0.RTEN, MethodObj) +External(\_SB.PCI0.RTDS, MethodObj) +External(\_SB.PCI0.RP01.PON, MethodObj) +External(\_SB.PCI0.RP02.PON, MethodObj) +External(\_SB.PCI0.RP03.PON, MethodObj) +External(\_SB.PCI0.RP04.PON, MethodObj) +External(\_SB.PCI0.RP05.PON, MethodObj) +External(\_SB.PCI0.RP06.PON, MethodObj) +External(\_SB.PCI0.RP07.PON, MethodObj) +External(\_SB.PCI0.RP08.PON, MethodObj) +External(\_SB.PCI0.RP09.PON, MethodObj) +External(\_SB.PCI0.RP10.PON, MethodObj) +External(\_SB.PCI0.RP11.PON, MethodObj) +External(\_SB.PCI0.RP12.PON, MethodObj) +External(\_SB.PCI0.RP13.PON, MethodObj) +External(\_SB.PCI0.RP14.PON, MethodObj) +External(\_SB.PCI0.RP15.PON, MethodObj) +External(\_SB.PCI0.RP16.PON, MethodObj) +External(\_SB.PCI0.RP17.PON, MethodObj) +External(\_SB.PCI0.RP18.PON, MethodObj) +External(\_SB.PCI0.RP19.PON, MethodObj) +External(\_SB.PCI0.RP20.PON, MethodObj) +External(\_SB.PCI0.RP21.PON, MethodObj) +External(\_SB.PCI0.RP22.PON, MethodObj) +External(\_SB.PCI0.RP23.PON, MethodObj) +External(\_SB.PCI0.RP24.PON, MethodObj) +External(\_SB.PCI0.PEG0.PG00._ON, MethodObj) +External(\_SB.PCI0.PEG1.PG01._ON, MethodObj) +External(\_SB.PCI0.PEG2.PG02._ON, MethodObj) + +Name(TRDO, 0) // 1 during TBT RTD3 _ON +Name(TRD3, 0) // 1 during TBT RTD3 _OFF +Name(TBPE, 0) // Reflects RTD3_PWR_EN value +Name(TOFF, 0) // param to TBT _OFF method + + Method (TBON, 0, Serialized) { + // TBT On process before entering Sx state. + Store(1, TRDO) + Switch (ToInteger(\RPS0)) { // TBT Root port Selector + Case (1) { + If (CondRefOf(\_SB.PCI0.RP01.PON)) { + \_SB.PCI0.RP01.PON() + } + } + Case (2) { + If (CondRefOf(\_SB.PCI0.RP02.PON)) { + \_SB.PCI0.RP02.PON() + } + } + Case (3) { + If (CondRefOf(\_SB.PCI0.RP03.PON)) { + \_SB.PCI0.RP03.PON() + } + } + Case (4) { + If (CondRefOf(\_SB.PCI0.RP04.PON)) { + \_SB.PCI0.RP04.PON() + } + } + Case (5) { + If (CondRefOf(\_SB.PCI0.RP05.PON)) { + \_SB.PCI0.RP05.PON() + } + } + Case (6) { + If (CondRefOf(\_SB.PCI0.RP06.PON)) { + \_SB.PCI0.RP06.PON() + } + } + Case (7) { + If (CondRefOf(\_SB.PCI0.RP07.PON)) { + \_SB.PCI0.RP07.PON() + } + } + Case (8) { + If (CondRefOf(\_SB.PCI0.RP08.PON)) { + \_SB.PCI0.RP08.PON() + } + } + Case (9) { + If (CondRefOf(\_SB.PCI0.RP09.PON)) { + \_SB.PCI0.RP09.PON() + } + } + Case (10) { + If (CondRefOf(\_SB.PCI0.RP10.PON)) { + \_SB.PCI0.RP10.PON() + } + } + Case (11) { + If (CondRefOf(\_SB.PCI0.RP11.PON)) { + \_SB.PCI0.RP11.PON() + } + } + Case (12) { + If (CondRefOf(\_SB.PCI0.RP12.PON)) { + \_SB.PCI0.RP12.PON() + } + } + Case (13) { + If (CondRefOf(\_SB.PCI0.RP13.PON)) { + \_SB.PCI0.RP13.PON() + } + } + Case (14) { + If (CondRefOf(\_SB.PCI0.RP14.PON)) { + \_SB.PCI0.RP14.PON() + } + } + Case (15) { + If (CondRefOf(\_SB.PCI0.RP15.PON)) { + \_SB.PCI0.RP15.PON() + } + } + Case (16) { + If (CondRefOf(\_SB.PCI0.RP16.PON)) { + \_SB.PCI0.RP16.PON() + } + } + Case (17) { + If (CondRefOf(\_SB.PCI0.RP17.PON)) { + \_SB.PCI0.RP17.PON() + } + } + Case (18) { + If (CondRefOf(\_SB.PCI0.RP18.PON)) { + \_SB.PCI0.RP18.PON() + } + } + Case (19) { + If (CondRefOf(\_SB.PCI0.RP19.PON)) { + \_SB.PCI0.RP19.PON() + } + } + Case (20) { + If (CondRefOf(\_SB.PCI0.RP20.PON)) { + \_SB.PCI0.RP20.PON() + } + } + Case (21) { + If (CondRefOf(\_SB.PCI0.RP21.PON)) { + \_SB.PCI0.RP21.PON() + } + } + Case (22) { + If (CondRefOf(\_SB.PCI0.RP22.PON)) { + \_SB.PCI0.RP22.PON() + } + } + Case (23) { + If (CondRefOf(\_SB.PCI0.RP23.PON)) { + \_SB.PCI0.RP23.PON() + } + } + Case (24) { + If (CondRefOf(\_SB.PCI0.RP24.PON)) { + \_SB.PCI0.RP24.PON() + } + } + }//Switch(ToInteger(RPS0)) // TBT Selector + Store(0, TRDO) + } // End of TBON + // + // Name: TBTD + // Description: Function to return the TBT RP# device no + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // Return: TBT RP# device no + // + Method(TBTD,2) + { + ADBG("TBTD") + If (LEqual(Arg1, DTBT_TYPE_PCH)) { + Switch(ToInteger(Arg0)) + { + Case (Package () {1, 2, 3, 4, 5, 6, 7, 8}) + { + Store(0x1C, Local0) //Device28-Function0...Function7 =3D 11100.0= 00...111 + } + Case (Package () {9, 10, 11, 12, 13, 14, 15, 16}) + { + Store(0x1D, Local0) //Device29-Function0...Function7 =3D 11101.0= 00...111 + } + Case (Package () {17, 18, 19, 20, 21, 22, 23, 24}) + { + Store(0x1B, Local0) //Device27-Function0...Function3 =3D 11011.0= 00...011 + } + } + } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { + Switch(ToInteger(Arg0)) + { + Case (Package () {1, 2, 3}) + { + Store(0x1, Local0) //Device1-Function0...Function2 =3D 00001.000= ...010 + } + } + } Else { + Store(0xFF, Local0) + } + + ADBG("Device no") + ADBG(Local0) + + Return(Local0) + } // End of Method(TBTD,1) + + // + // Name: TBTF + // Description: Function to return the TBT RP# function no + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // Return: TBT RP# function no + // + Method(TBTF,2) + { + ADBG("TBTF") + If (LEqual(Arg1, DTBT_TYPE_PCH)) { + Switch(ToInteger(Arg0)) + { + Case (1) + { + Store(And(\RPA1,0xF), Local0) //Device28-Function0 =3D 11100.000 + } + Case (2) + { + Store(And(\RPA2,0xF), Local0) //Device28-Function1 =3D 11100.001 + } + Case (3) + { + Store(And(\RPA3,0xF), Local0) //Device28-Function2 =3D 11100.010 + } + Case (4) + { + Store(And(\RPA4,0xF), Local0) //Device28-Function3 =3D 11100.011 + } + Case (5) + { + Store(And(\RPA5,0xF), Local0) //Device28-Function4 =3D 11100.100 + } + Case (6) + { + Store(And(\RPA6,0xF), Local0) //Device28-Function5 =3D 11100.101 + } + Case (7) + { + Store(And(\RPA7,0xF), Local0) //Device28-Function6 =3D 11100.110 + } + Case (8) + { + Store(And(\RPA8,0xF), Local0) //Device28-Function7 =3D 11100.111 + } + Case (9) + { + Store(And(\RPA9,0xF), Local0) //Device29-Function0 =3D 11101.000 + } + Case (10) + { + Store(And(\RPAA,0xF), Local0) //Device29-Function1 =3D 11101.001 + } + Case (11) + { + Store(And(\RPAB,0xF), Local0) //Device29-Function2 =3D 11101.010 + } + Case (12) + { + Store(And(\RPAC,0xF), Local0) //Device29-Function3 =3D 11101.011 + } + Case (13) + { + Store(And(\RPAD,0xF), Local0) //Device29-Function4 =3D 11101.100 + } + Case (14) + { + Store(And(\RPAE,0xF), Local0) //Device29-Function5 =3D 11101.101 + } + Case (15) + { + Store(And(\RPAF,0xF), Local0) //Device29-Function6 =3D 11101.110 + } + Case (16) + { + Store(And(\RPAG,0xF), Local0) //Device29-Function7 =3D 11101.111 + } + Case (17) + { + Store(And(\RPAH,0xF), Local0) //Device27-Function0 =3D 11011.000 + } + Case (18) + { + Store(And(\RPAI,0xF), Local0) //Device27-Function1 =3D 11011.001 + } + Case (19) + { + Store(And(\RPAJ,0xF), Local0) //Device27-Function2 =3D 11011.010 + } + Case (20) + { + Store(And(\RPAK,0xF), Local0) //Device27-Function3 =3D 11011.011 + } + Case (21) + { + Store(And(\RPAL,0xF), Local0) //Device27-Function4 =3D 11011.100 + } + Case (22) + { + Store(And(\RPAM,0xF), Local0) //Device27-Function5 =3D 11011.101 + } + Case (23) + { + Store(And(\RPAN,0xF), Local0) //Device27-Function6 =3D 11011.110 + } + Case (24) + { + Store(And(\RPAO,0xF), Local0) //Device27-Function7 =3D 11011.111 + } + } + } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { + Switch(ToInteger(Arg0)) + { + Case (1) + { + Store(0x0, Local0) //Device1-Function0 =3D 00001.000 + } + Case (2) + { + Store(0x1, Local0) //Device1-Function1 =3D 00001.001 + } + Case (3) + { + Store(0x2, Local0) //Device1-Function2 =3D 00001.010 + } + } + } Else { + Store(0xFF, Local0) + } + + ADBG("Function no") + ADBG(Local0) + + Return(Local0) + } // End of Method(TBTF,1) + + // + // Name: MMRP + // Description: Function to return the Pci base address of TBT rootport + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // + + Method(MMRP, 2, Serialized) + { + Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address + Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no + Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no + + Return(Local0) + } // End of Method(MMRP) + + // + // Name: MMRP + // Description: Function to return the Pci base address of TBT Up stream= port + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // + Method(MMTB, 2, Serialized) + { + ADBG("MMTB") + + Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address + + Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no + Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no + + OperationRegion (MMMM, SystemMemory, Local0, 0x1A) + Field (MMMM, AnyAcc, NoLock, Preserve) + { + Offset(0x19), + SBUS, 8 + } + Store(SBUS, Local2) + Store(\_SB.PCI0.GPCB(), Local0) + Multiply(Local2, 0x100000, Local2) + Add(Local2, Local0, Local0) // TBT HR US port + + ADBG("TBT-US-ADR") + ADBG(Local0) + + Return(Local0) + } // End of Method(MMTB, 1, Serialized) + // + // Name: FFTB + // Description: Function to Check for FFFF in TBT PCIe + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // Return: 1 if TBT PCIe space has value FFFF, 0 if not + // + Method(FFTB, 2, Serialized) + { + ADBG("FFTB") + + Add(MMTB(Arg0, Arg1), 0x548, Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x08) + Field(PXVD,DWordAcc, NoLock, Preserve) + { + TB2P, 32, + P2TB, 32 + } + + Store(TB2P, Local1) + + If(LEqual(Local1, 0xFFFFFFFF)) + { + ADBG("FFTb 1") + Return (1) + } + Else + { + ADBG("FFTb 0") + Return (0) + } + } // End of Method(FFTB) + +Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory buffer, = fixed up during POST + +Scope(\_GPE) +{ + // + // + //OS up Mail Box command execution to host router upstream port each time + //exiting from Sx State .Avoids intermediate + //PCIe Scan by OS during resorce allocation + // Arg0 : PCIe Base address + // Arg1 : Controller Type 0x00 : DTBT + //Developer notes: Called twice + // 1. During OS INIT (booting to OS from S3-S5/Reboot) + // 2. Up on Hot plug + // + Method(OSUP, 2, Serialized) + { + ADBG("OSUP") + + Add(Arg0, 0x540, Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x10) + Field(PXVD,DWordAcc, NoLock, Preserve) + { + IT2P, 32, + IP2T, 32, + DT2P, 32, + DP2T, 32 + } + + Store(100, Local1) + Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT + + While(LGreater(Local1, 0)) + { + Store(Subtract(Local1, 1), Local1) + Store(DT2P, Local2) + + If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1, DTBT_CONTROLLER)))//= Device gone + { + ADBG("Dev gone") + Return(2) + } + If(And(Local2, 1)) // Done + { + ADBG("Cmd acknowledged") + break + } + Sleep(50) + } + If(LEqual(TRWA,1)) + { + Store(0xC, DP2T) // Write OSUP to PCIe2TBT + } + Else + { + Store(0x0, DP2T) // Write 0 to PCIe2TBT + } + + //Store(0x00, P2TB) // Write 0 to PCIe2TBT + + ADBG("End-of-OSUP") + + Return(1) + } // End of Method(OSUP, 1, Serialized) + + // + // Check for FFFF in TBT + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // + + Method(TBFF, 2, Serialized) + { + ADBG("TBFF") + + Store(MMTB(Arg0, Arg1), Local0) + OperationRegion (PXVD, SystemMemory, Local0, 0x8) + Field (PXVD, DWordAcc, NoLock, Preserve) { + VEDI, 32, // Vendor/Device ID + CMDR, 32 // CMD register + } + + Store(VEDI, Local1) + + If (LEqual(Local1, 0xFFFFFFFF)) { + If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode? + If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone + Return (2)// Notify only + } + Return (1)// Exit w/o notify + } Else { + Return (OSUP(Local0, DTBT_CONTROLLER)) + } + } Else + { + ADBG("Dev Present") + Return (0) + } + } // End of Method(TBFF, 1, Serialized) + + // + // Secondary bus of TBT RP + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // + + Method(TSUB, 2, Serialized) + { + ADBG("TSUB") + + Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address + + Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no + Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no + + ADBG("ADR") + ADBG(Local0) + + OperationRegion (MMMM, SystemMemory, Local0, 0x1A) + Field (MMMM, AnyAcc, NoLock, Preserve) + { + Offset(0x19), + SBUS, 8 + } + + ADBG("Sec Bus") + ADBG(SBUS) + + Return(SBUS) + } // End of Method(TSUB, 0, Serialized) + + // + // Pmem of TBT RP + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // + + Method(TSUP, 2, Serialized) + { + ADBG("TSUB") + + Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address + + Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no + Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no + + ADBG("ADR:") + ADBG(Local0) + + OperationRegion (MMMM, SystemMemory, Local0, 0x30) + Field (MMMM, AnyAcc, NoLock, Preserve) + { + CMDS, 32, + Offset(0x19), + SBUS, 8, + SBU5, 8, + Offset(0x1C), + SEIO, 32, + MMBL, 32, + PMBL, 32, + + } + + ADBG("Pmem of TBT RP:") + ADBG(PMBL) + + Return(PMBL) + } // End of Method(TSUP, 0, Serialized) + + // + // Wait for secondary bus in TBT RP + // Input: Arg0 -> Tbt Root Port value from Tbt NVS + // Input: Arg1 -> Tbt port type value from Tbt NVS + // + + Method(WSUB, 2, Serialized) + { + ADBG(Concatenate("WSUB=3D", ToHexString(Arg0))) + ADBG(ToHexString(Timer)) + + Store(0, Local0) + Store(0, Local1) + While(1) + { + Store(TSUP(Arg0, Arg1), Local1) + If(LGreater(Local1, 0x1FFF1)) + { + ADBG("WSUB-Finished") + Break + } + Else + { + Add(Local0, 1, Local0) + If(LGreater(Local0, 1000)) + { + Sleep(1000) + ADBG("WSUB-Deadlock") + } + Else + { + Sleep(16) + } + } + } + ADBG(Concatenate("WSUb=3D", ToHexString(Local1))) + } // End of Method(WSUB) + + // Wait for _WAK finished + Method(WWAK) + { + ADBG("WWAK") + + Wait(WFEV, 0xFFFF) + Signal(WFEV) // Set it, to enter on next HP + } // End of Method(WWAK) + + Method(NTFY, 2, Serialized) + { + ADBG("NTFY") + + If(LEqual(NOHP,1)) + { + If (LEqual(Arg1, DTBT_TYPE_PCH)) { + Switch(ToInteger(Arg0)) // TBT Selector + { + Case (1) + { + ADBG("Notify RP01") + Notify(\_SB.PCI0.RP01,0) + } + Case (2) + { + ADBG("Notify RP02") + Notify(\_SB.PCI0.RP02,0) + } + Case (3) + { + ADBG("Notify RP03") + Notify(\_SB.PCI0.RP03,0) + } + Case (4) + { + ADBG("Notify RP04") + Notify(\_SB.PCI0.RP04,0) + } + Case (5) + { + ADBG("Notify RP05") + Notify(\_SB.PCI0.RP05,0) + } + Case (6) + { + ADBG("Notify RP06") + Notify(\_SB.PCI0.RP06,0) + } + Case (7) + { + ADBG("Notify RP07") + Notify(\_SB.PCI0.RP07,0) + } + Case (8) + { + ADBG("Notify RP08") + Notify(\_SB.PCI0.RP08,0) + } + Case (9) + { + ADBG("Notify RP09") + Notify(\_SB.PCI0.RP09,0) + } + Case (10) + { + ADBG("Notify RP10") + Notify(\_SB.PCI0.RP10,0) + } + Case (11) + { + ADBG("Notify RP11") + Notify(\_SB.PCI0.RP11,0) + } + Case (12) + { + ADBG("Notify RP12") + Notify(\_SB.PCI0.RP12,0) + } + Case (13) + { + ADBG("Notify RP13") + Notify(\_SB.PCI0.RP13,0) + } + Case (14) + { + ADBG("Notify RP14") + Notify(\_SB.PCI0.RP14,0) + } + Case (15) + { + ADBG("Notify RP15") + Notify(\_SB.PCI0.RP15,0) + } + Case (16) + { + ADBG("Notify RP16") + Notify(\_SB.PCI0.RP16,0) + } + Case (17) + { + ADBG("Notify RP17") + Notify(\_SB.PCI0.RP17,0) + } + Case (18) + { + ADBG("Notify RP18") + Notify(\_SB.PCI0.RP18,0) + } + Case (19) + { + ADBG("Notify RP19") + Notify(\_SB.PCI0.RP19,0) + } + Case (20) + { + ADBG("Notify RP20") + Notify(\_SB.PCI0.RP20,0) + } + Case (21) + { + ADBG("Notify RP21") + Notify(\_SB.PCI0.RP21,0) + } + Case (22) + { + ADBG("Notify RP22") + Notify(\_SB.PCI0.RP22,0) + } + Case (23) + { + ADBG("Notify RP23") + Notify(\_SB.PCI0.RP23,0) + } + Case (24) + { + ADBG("Notify RP24") + Notify(\_SB.PCI0.RP24,0) + } + }//Switch(ToInteger(TBSS)) // TBT Selector + } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) { + Switch(ToInteger(Arg0)) + { + Case (1) + { + ADBG("Notify PEG0") + Notify(\_SB.PCI0.PEG0,0) + } + Case (2) + { + ADBG("Notify PEG1") + Notify(\_SB.PCI0.PEG1,0) + } + Case (3) + { + ADBG("Notify PEG2") + Notify(\_SB.PCI0.PEG2,0) + } + } + }//Switch(ToInteger(TBSS)) // TBT Selector + }//If(NOHP()) + P8XH(0,0xC2) + P8XH(1,0xC2) + }// End of Method(NTFY) + +// +// TBT BIOS, GPIO 5 filtering, +// Hot plug of 12V USB devices, into TBT host router, cause electrical no= ise on PCH GPIOs, +// This noise cause false hot-plug events, and negatively influence BIOS = assisted hot-plug. +// WHL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS= ) on any GPIO pad. Native functions have to implement their own digital gli= tch-filter logic +// if needed. As HW filter was not implemented on WHL PCH, because of tha= t SW workaround should be implemented in BIOS. +// Register 0x544(Bios mailbox) bit 0 definition: +// if BIOS reads bit as 1, BIOS will clear the bit and continue normal fl= ow, if bit is 0 BIOS will exit from method +// + + Method(GNIS,2, Serialized) + { + + ADBG("GNIS") + If(LEqual(GP5F, 0)) + { + ADBG("GNIS_Dis=3D0") + Return(0) + } + // + // BIOS mailbox command for GPIO filter + // + Add(MMTB(Arg0, Arg1), 0x544, Local0) + OperationRegion(PXVD,SystemMemory,Local0,0x08) + + Field(PXVD,DWordAcc, NoLock, Preserve) + { + HPFI, 1, + Offset(0x4), + TB2P, 32 + } + Store(TB2P, Local1) + ADBG(Concatenate("TB2P=3D", ToHexString(Local1))) + If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect? + { + ADBG("GNIS=3D0") + Return(0) + } + Store(HPFI, Local2) + ADBG(Concatenate("HPFI=3D", ToHexString(Local2))) + If(LEqual(Local2, 0x01)) + { + Store(0x00, HPFI) + ADBG("GNIS=3D0") + Return(0) + } + // Any other values treated as a GPIO noise + ADBG("GNIS=3D1") + Return(1) + } + + Method(CHKP,2, Serialized) + { + Add(MMTB(Arg0, Arg1), 0x544, Local0) + OperationRegion(PXVE,SystemMemory,Local0,0x08) + + Field(PXVE,DWordAcc, NoLock, Preserve) + { + HPFI, 1, + Offset(0x4), + TB2P, 32 + } + Store(TB2P, Local1) + And(Local1,BIT29,Local1) + ADBG(Concatenate("Local1=3D", ToHexString(Local1))) + //ADBG(Concatenate("BIT29=3D", ToHexString(LAnd(Local1,BIT29)))) + If(LEqual(Local1, BIT29)) + { + Return(1) + } + Else + { + Return(0) + } + } + + // + // Method to Handle enumerate PCIe structure through + // SMI for Thunderbolt(TM) devices + // + Method(XTBT,2, Serialized) + { + ADBG("XTBT") + ADBG("RP :") + ADBG(Arg0) + Store(Arg0, DTCP) // Root port to enumerate + Store(Arg1, DTPT) // Root port Type + If(LEqual(Arg0, RPS0)) { + Store (1, Local0) + } ElseIf (LEqual(Arg0, RPS1)) { + Store (2, Local0) + } Else { + Store (0, Local0) + Return () + } + + If (TRDO) { + ADBG("Durng TBT_ON") + Return () + } + + If (TRD3) { + ADBG("During TBT_OFF") + Return () + } + WWAK() + WSUB(Arg0, Arg1) + If(GNIS(Arg0, Arg1)) + { + Return() + } + + OperationRegion(SPRT,SystemIO, 0xB2,2) + Field (SPRT, ByteAcc, Lock, Preserve) + { + SSMP, 8 + } + + ADBG("TBT-HP-Handler") + + Acquire(OSUM, 0xFFFF) + Store(TBFF(Arg0, Arg1), Local1) + If(LEqual(Local1, 1))// Only HR + { + Sleep(16) + Release(OSUM) + ADBG("OS_Up_Received") + Return () + } + If(LEqual(Local1, 2)) // Disconnect + { + NTFY(Arg0, Arg1) + Sleep(16) + Release(OSUM) + ADBG("Disconnect") + Return () + } + + // HR and EP + If(LEqual(SOHP, 1)) + { + // Trigger SMI to enumerate PCIe Structure + ADBG("TBT SW SMI") + Store(21, TBSF) + Store(0xF7, SSMP) + } + NTFY(Arg0, Arg1) + Sleep(16) + Release(OSUM) + + ADBG("End-of-XTBT") + } // End of Method(XTBT) + + // + // Calling Method to Handle enumerate PCIe structure through + // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs + // Used in Two ways , + // If CIO GPIO(1 Tier) is Different for the Controllers, this will be us= ed as 1 Tier GPIO Handler for 1st controller + // If CIO GPIO(1 Tier) is Same for all the controllers, this will be use= d as 1 Tier GPIO Handler for All the controllers + // + Method(ATBT) + { + ADBG("ATBT") + // + // Calling Method to Handle enumerate PCIe structure through + // + If(LEqual(CGST,0)) { // If GPIO is Different for each controller + If(LEqual(RPN0,1)) + { + XTBT(RPS0, RPT0) + } + } Else { + If(LEqual(RPN0,1)) + { + XTBT(RPS0, RPT0) + } + ElseIf(LEqual(RPN1,1)) + { + XTBT(RPS1, RPT1) + } + } + ADBG("End-of-ATBT") + } // End of Method(ATBT) + + Method(BTBT) + { + ADBG("BTBT") + // + // Calling Method to Handle enumerate PCIe structure through + // + If(LEqual(CGST,0)) { // If GPIO is Different for each controller + If(LEqual(RPN1,1)) + { + XTBT(RPS1, RPT1) + } + } + ADBG("End-of-BTBT") + } // End of Method(BTBT) + // + // Method to call OSPU Mail box command + // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT + // Arg1 : TBT RP Selector / DMA + // Arg2 : TBT Type (PCH or PEG) + // + Method(TINI, 3, Serialized) + { + ADBG("TINI") + If(Lequal (Arg0, DTBT_CONTROLLER)) + { + //ADBG("DTBT") + Store(MMRP(Arg1, Arg2), Local0) + OperationRegion(RP_X,SystemMemory,Local0,0x20) + Field(RP_X,DWordAcc, NoLock, Preserve) + { + REG0, 32, + REG1, 32, + REG2, 32, + REG3, 32, + REG4, 32, + REG5, 32, + REG6, 32, + REG7, 32 + } + Store(REG6, Local1) + Store(0x00F0F000, REG6) + Store(MMTB(Arg1, Arg2), Local2) + OSUP(Local2, DTBT_CONTROLLER) + Store(Local1, REG6) + } + ADBG("End-of-TINI") + } + +} // End of Scope (\_GPE) + +Scope (\_SB) +{ + // + // The code needs to be executed for TBT Hotplug Handler event (2-tier G= PI GPE event architecture) is presented here + // + Method(THDR, 3, Serialized) + { + ADBG("THDR") + \_SB.CAGS(Arg0) + \_GPE.XTBT(Arg1, Arg2) + } // End of Method(THDR, 3, Serialized) +} // End of Scope(\_SB) + +Scope (\_SB) +{ + // + // Name: CGWR [Combined GPIO Write] + // Description: Function to write into GPIO + // Input: Arg0 -> GpioPad / Expander pin + // Arg1 -> Value + // Return: Nothing + // + Method(CGWR, 2, Serialized) + { + // PCH + If (CondRefOf(\_SB.SGOV)) + { + \_SB.SGOV(Arg0, Arg1) + } + } // End of Method(CGWR, 4, Serialized) + + // + // Name: CGRD [Combined GPIO Read] + // Description: Function to read from GPIO + // Input: Arg0 -> GpioPad / Expander pin + // Arg1 -> 0: GPO [GPIO TX State] + // 1: GPI [GPIO RX State] + // Return: Value + // + Method(CGRD, 2, Serialized) + { + Store(1, Local0) + // PCH + If (LEqual(Arg1, 0)) + { + // GPIO TX State + If (CondRefOf(\_SB.GGOV)) + { + Store(\_SB.GGOV(Arg0), Local0) + } + } + ElseIf (LEqual(Arg1, 1)) + { + // GPIO RX State + If (CondRefOf(\_SB.GGIV)) + { + Store(\_SB.GGIV(Arg0), Local0) + } + } + Return(Local0) + } // End of Method(CGRD, 4, Serialized) + // + // Name: WRGP [GPIO Write] + // Description: Function to write into GPIO + // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo + // Arg1 -> Value + // Return: Nothing + // + Method(WRGP, 2, Serialized) + { + Store(Arg0, Local0) + Store(Arg0, Local1) + And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00) + ShiftRight(Local1, 32, Local1) // High 32 bits (63:32) + If (LEqual(And(Local0, 0xFF), 1)) + { + // PCH + \_SB.CGWR(Local1, Arg1) + } + } // End of Method(WRGP, 2, Serialized) + + // + // Name: RDGP [GPIO Read] + // Description: Function to write into GPIO + // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo + // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State indic= ator} + // Return: Value + // + Method(RDGP, 2, Serialized) + { + Store(1, Local7) + Store(Arg0, Local0) + Store(Arg0, Local1) + And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00) + ShiftRight(Local1, 32, Local1) // High 32 bits (63:32) + If (LEqual(And(Local0, 0xFF), 1)) + { + // PCH + Store(\_SB.CGRD(Local1, Arg1), Local7) + } + Return(Local7) + } // End of Method(RDGP, 2, Serialized) + +} // End of Scope(\_SB) + +Scope(\_SB) +{ + // Asserts/De-asserts TBT force power + Method(TBFP, 2) + { + If(Arg0) + { + // Implementation dependent way to assert TBT force power + If(LEqual(Arg1, 1)) { + CGWR(FPG0, FP0L) + } + Else { + CGWR(FPG1, FP1L) + } + } + Else + { + // Implementation dependent way to de-assert TBT force power + If(LEqual(Arg1, 1)) { + CGWR(FPG0, LNot(FP0L)) + } + Else { + CGWR(FPG1, LNot(FP1L)) + } + } + } + + // WMI ACPI device to control TBT force power + Device(WMTF) + { + // pnp0c14 is pnp id assigned to WMI mapper + Name(_HID, "PNP0C14") + Name(_UID, "TBFP") + + Name(_WDG, Buffer() { + // {86CCFD48-205E-4A77-9C48-2021CBEDE341} + 0x48, 0xFD, 0xCC, 0x86, + 0x5E, 0x20, + 0x77, 0x4A, + 0x9C, 0x48, + 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41, + 84, 70, // Object Id (TF) + 1, // Instance Count + 0x02 // Flags (WMIACPI_REGFLAG_METHOD) + }) + + // Set TBT force power + // Arg2 is force power value + Method(WMTF, 3) + { + CreateByteField(Arg2,0,FP) + + If(FP) + { + TBFP(1, 1) + } + Else + { + TBFP(0, 1) + } + } + } +} // End of Scope(\_SB) + + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1)))) +{ + Scope(\_SB.PCI0.RP01) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP01) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2)))) +{ + Scope(\_SB.PCI0.RP02) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP02) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3)))) +{ + Scope(\_SB.PCI0.RP03) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP03) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4)))) +{ + Scope(\_SB.PCI0.RP04) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP04) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5)))) +{ + Scope(\_SB.PCI0.RP05) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP05) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6)))) +{ + Scope(\_SB.PCI0.RP06) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP06) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7)))) +{ + Scope(\_SB.PCI0.RP07) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP07) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8)))) +{ + Scope(\_SB.PCI0.RP08) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP08) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9)))) +{ + Scope(\_SB.PCI0.RP09) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP09) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10)))) +{ + Scope(\_SB.PCI0.RP10) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP10) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11)))) +{ + Scope(\_SB.PCI0.RP11) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP11) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12)))) +{ + Scope(\_SB.PCI0.RP12) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP12) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13)))) +{ + Scope(\_SB.PCI0.RP13) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP13) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14)))) +{ + Scope(\_SB.PCI0.RP14) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP14) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15)))) +{ + Scope(\_SB.PCI0.RP15) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP15) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16)))) +{ + Scope(\_SB.PCI0.RP16) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP16) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17)))) +{ + Scope(\_SB.PCI0.RP17) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP17) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18)))) +{ + Scope(\_SB.PCI0.RP18) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP18) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19)))) +{ + Scope(\_SB.PCI0.RP19) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP19) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20)))) +{ + Scope(\_SB.PCI0.RP20) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.RP20) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21)))) +{ + Scope(\_SB.PCI0.PEG0) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.PEG0) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22)))) +{ + Scope(\_SB.PCI0.PEG1) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.PEG1) +} + +If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23)))) +{ + Scope(\_SB.PCI0.PEG2) + { + Device(HRUS)// Host router Upstream port + { + Name(_ADR, 0x00000000) + + Method(_RMV) + { + Return(TARS) + } // end _RMV + } + }//End of Scope(\_SB.PCI0.PEG2) +} + +Scope(\_SB) +{ + // + // Name: PERB + // Description: Function to read a Byte from PCIE-MMIO + // Input: Arg0 -> PCIE base address + // Arg1 -> Bus + // Arg2 -> Device + // Arg3 -> Function + // Arg4 -> Register offset + // Return: Byte data read from PCIE-MMIO + // + Method(PERB,5,Serialized) + { + ADBG("PERB") + + Store(Arg0, Local7) + Or(Local7, ShiftLeft(Arg1, 20), Local7) + Or(Local7, ShiftLeft(Arg2, 15), Local7) + Or(Local7, ShiftLeft(Arg3, 12), Local7) + Or(Local7, Arg4, Local7) + + OperationRegion(PCI0, SystemMemory, Local7, 1) + Field(PCI0, ByteAcc,NoLock,Preserve) + { + TEMP, 8 + } + + Return(TEMP) + } // End of Method(PERB,5,Serialized) + + // + // Name: PEWB + // Description: Function to write a Byte into PCIE-MMIO + // Input: Arg0 -> PCIE base address + // Arg1 -> Bus + // Arg2 -> Device + // Arg3 -> Function + // Arg4 -> Register offset + // Arg5 -> Data + // Return: Nothing + // + Method(PEWB,6,Serialized) + { + ADBG("PEWB") + + Store(Arg0, Local7) + Or(Local7, ShiftLeft(Arg1, 20), Local7) + Or(Local7, ShiftLeft(Arg2, 15), Local7) + Or(Local7, ShiftLeft(Arg3, 12), Local7) + Or(Local7, Arg4, Local7) + + OperationRegion(PCI0, SystemMemory, Local7, 1) + Field(PCI0, ByteAcc,NoLock,Preserve) + { + TEMP, 8 + } + + Store(Arg5,TEMP) + } // End of Method(PEWB,6,Serialized) + + // + // Name: PERW + // Description: Function to read a Word from PCIE-MMIO + // Input: Arg0 -> PCIE base address + // Arg1 -> Bus + // Arg2 -> Device + // Arg3 -> Function + // Arg4 -> Register offset + // Return: Word data read from PCIE-MMIO + // + Method(PERW,5,Serialized) + { + ADBG("PERW") + + Store(Arg0, Local7) + Or(Local7, ShiftLeft(Arg1, 20), Local7) + Or(Local7, ShiftLeft(Arg2, 15), Local7) + Or(Local7, ShiftLeft(Arg3, 12), Local7) + Or(Local7, Arg4, Local7) + + OperationRegion(PCI0, SystemMemory, Local7, 2) + Field(PCI0, ByteAcc,NoLock,Preserve) + { + TEMP, 16 + } + + Return(TEMP) + } // End of Method(PERW,5,Serialized) + + // + // Name: PEWW + // Description: Function to write a Word into PCIE-MMIO + // Input: Arg0 -> PCIE base address + // Arg1 -> Bus + // Arg2 -> Device + // Arg3 -> Function + // Arg4 -> Register offset + // Arg5 -> Data + // Return: Nothing + // + Method(PEWW,6,Serialized) + { + ADBG("PEWW") + + Store(Arg0, Local7) + Or(Local7, ShiftLeft(Arg1, 20), Local7) + Or(Local7, ShiftLeft(Arg2, 15), Local7) + Or(Local7, ShiftLeft(Arg3, 12), Local7) + Or(Local7, Arg4, Local7) + + OperationRegion(PCI0, SystemMemory, Local7, 2) + Field(PCI0, ByteAcc,NoLock,Preserve) + { + TEMP, 16 + } + + Store(Arg5,TEMP) + } // End of Method(PEWW,6,Serialized) + + // + // Name: PERD + // Description: Function to read a Dword from PCIE-MMIO + // Input: Arg0 -> PCIE base address + // Arg1 -> Bus + // Arg2 -> Device + // Arg3 -> Function + // Arg4 -> Register offset + // Return: Dword data read from PCIE-MMIO + // + Method(PERD,5,Serialized) + { + ADBG("PERD") + + Store(Arg0, Local7) + Or(Local7, ShiftLeft(Arg1, 20), Local7) + Or(Local7, ShiftLeft(Arg2, 15), Local7) + Or(Local7, ShiftLeft(Arg3, 12), Local7) + Or(Local7, Arg4, Local7) + + OperationRegion(PCI0, SystemMemory, Local7, 4) + Field(PCI0, ByteAcc,NoLock,Preserve) + { + TEMP, 32 + } + + Return(TEMP) + } // End of Method(PERD,5,Serialized) + + // + // Name: PEWD + // Description: Function to write a Dword into PCIE-MMIO + // Input: Arg0 -> PCIE base address + // Arg1 -> Bus + // Arg2 -> Device + // Arg3 -> Function + // Arg4 -> Register offset + // Arg5 -> Data + // Return: Nothing + // + Method(PEWD,6,Serialized) + { + ADBG("PEWD") + + Store(Arg0, Local7) + Or(Local7, ShiftLeft(Arg1, 20), Local7) + Or(Local7, ShiftLeft(Arg2, 15), Local7) + Or(Local7, ShiftLeft(Arg3, 12), Local7) + Or(Local7, Arg4, Local7) + + OperationRegion(PCI0, SystemMemory, Local7, 4) + Field(PCI0, ByteAcc,NoLock,Preserve) + { + TEMP, 32 + } + + Store(Arg5,TEMP) + } // End of Method(PEWD,6,Serialized) + + // + // Name: STDC + // Description: Function to get Standard Capability Register Offset + // Input: Arg0 -> PCIE base address + // Arg1 -> Bus + // Arg2 -> Device + // Arg3 -> Function + // Arg4 -> Capability ID + // Return: Capability Register Offset data + // + Method(STDC,5,Serialized) + { + ADBG("STDC") + + //Check for Referenced device is present or not + Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID regist= er + If(LEqual(Local7, 0xFFFF)) + { + ADBG("Referenced device is not present") + Return(0) + } + + Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status re= gister + If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List + { + //No Capabilities linked list is available + ADBG("No Capabilities linked list is available") + Return(0) + } + + //Local1 is for storing CapabilityID + //Local2 is for storing CapabilityPtr + Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr + + While(1) + { + And(Local2, 0xFC, Local2) //Each capability must be DWORD aligned + + If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate= the last capability in the list + { + ADBG("Capability ID is not found") + Return(0) + } + + Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID + + If(LEqual(Arg4, Local1)) //CapabilityID match + { + ADBG("Capability ID is found") + ADBG("Capability Offset : ") + ADBG(Local2) + Return(Local2) + } + Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2) //Capa= bilityPtr + Return(0) + } + } // End of Method(STDC,5,Serialized) + +} // End Scope(\_SB) + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45913): https://edk2.groups.io/g/devel/message/45913 Mute This Topic: https://groups.io/mt/32918207/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45914+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45914+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001034; cv=none; d=zoho.com; s=zohoarc; b=XYcQvtTUJl8EUXajspQLg+Y1RekQMLKkweKj7xseVR5mA0SciP33i6Y86N14nF36d2OQYMkqYcqEdlQ/bkkcjVBAZ3RfICqjxhB+3XxdMgwWIfEYaA/2jc74eH87qN2tt74NGT3WprJgRaKLFaiwWYhsXgbb3KOEqBlhTUyGrak= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001034; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=IwNgnvJnK5Jcr9oEucYvUd5sFA6TlBCKDaBL5pTuROY=; b=ffQgPoCwyKxj5Sz7ujvYHW+TDZyTDHvbzgpsEuq7ILbNjxqH5Tw1wyo60ZqJ9hVD3Jh7VhnE0el0LpwkNYPCK4PLYVJ1CtOOb4Jktsfl4vBAxHqUgHeTTv57ABxwxllp38CS1LunwLhtTLku35ywHcvewpoHiu67YZVaFOP2az0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45914+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001034871336.3710298758391; Fri, 16 Aug 2019 17:17:14 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:13 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:17:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319382" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:17:01 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 36/37] WhiskeylakeOpenBoardPkg/WhiskeylakeURvp: Add DSC and build files Date: Fri, 16 Aug 2019 17:16:02 -0700 Message-Id: <20190817001603.30632-37-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001034; bh=QCAQAtidRWALZi2AGXwxk+nnrXlVjjYdEHQp7bkKscM=; h=Cc:Date:From:Reply-To:Subject:To; b=fDKdfsgsFDoFzOnILQ/GyykvOLfafyTqWIvpugvn0GOpStYZ3/NxENfSC7UnfAELFAW 82XEOWgV93KJGZ0+AEKXKPpjsLCais6i2FL71kseEItuhSxY8tEvlEU4c1ikUTNObZbG4 8uT+eKVywaUM5GsoI0EI9yGl2aZfCdEH6YE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 Adds the DSC and build files necessary to build the WhiskeylakeURvp board instance. Key files =3D=3D=3D=3D=3D=3D=3D=3D=3D * build_config.cfg - Board-specific build configuration file. * OpenBoardPkg.dsc - The WhiskeylakeURvp board description file. * OpenBoardPkgConfig.dsc - Used for feature-related PCD customization. * OpenBoardPkgPcd.dsc - Used for other PCD customization. * OpenBoardPkg.fdf - The WhiskeylakeURvp board flash file. * FlashMapInclude.fdf - The WhiskeylakeURvp board flash map. * OpenBoardPkgBuildOption.dsc - Sets build options Based on PCD values. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc = | 385 +++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgBuildOp= tion.dsc | 154 +++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgConfig.= dsc | 128 ++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPcd.dsc= | 245 +++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/FlashMa= pInclude.fdf | 49 ++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.fdf = | 706 ++++++++++++++++++++ Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg = | 33 + 7 files changed, 1700 insertions(+) diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.dsc new file mode 100644 index 0000000000..eea809140c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.d= sc @@ -0,0 +1,385 @@ +## @file +# Platform description. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + # + # Set platform specific package/folder name, same as passed from PREBUIL= D script. + # PLATFORM_PACKAGE would be the same as PLATFORM_NAME as well as package= build folder + # DEFINE only takes effect at R9 DSC and FDF. + # + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg + DEFINE PLATFORM_SI_PACKAGE =3D CoffeelakeSiliconPkg + DEFINE PLATFORM_SI_BIN_PACKAGE =3D CoffeelakeSiliconBinPkg + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D CoffeeLakeFspBinPkg + DEFINE PLATFORM_BOARD_PACKAGE =3D WhiskeylakeOpenBoardPkg + DEFINE BOARD =3D WhiskeylakeURvp + DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE)/$(BO= ARD) + + # + # Platform On/Off features are defined here + # + !include OpenBoardPkgConfig.dsc + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + PLATFORM_NAME =3D $(PLATFORM_PACKAGE) + PLATFORM_GUID =3D 84D0F5BD-0EF3-4CC0-9B09-F2D0F2AA= 5C5E + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/$(PROJECT) + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D ALL + + + FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf + + FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0 + DEFINE TOP_MEMORY_ADDRESS =3D 0x0 + + # + # Default value for OpenBoardPkg.fdf use + # + DEFINE BIOS_SIZE_OPTION =3D SIZE_70 + +##########################################################################= ###### +# +# SKU Identification section - list of all SKU IDs supported by this +# Platform. +# +##########################################################################= ###### +[SkuIds] + 0|DEFAULT # The entry: 0|DEFAULT is reserved and always req= uired. + 0x60|WhiskeylakeURvp + +##########################################################################= ###### +# +# Library Class section - list of all Library Classes needed by this Platf= orm. +# +##########################################################################= ###### + + !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc + !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc + !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc + +[LibraryClasses.common] + + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf + + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf + I2cAccessLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiI2cAccessLib/PeiI2cAcc= essLib.inf + GpioExpanderLib|$(PLATFORM_BOARD_PACKAGE)/Library/BaseGpioExpanderLib/Ba= seGpioExpanderLib.inf + + PlatformHookLib|$(PROJECT)/Library/BasePlatformHookLib/BasePlatformHookL= ib.inf + + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf + PlatformSecLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/SecFspWrappe= rPlatformSecLib/SecFspWrapperPlatformSecLib.inf + + FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf + FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf + + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf + + ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseCon= figBlockLib.inf + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf + + # Tbt + !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + TbtCommonLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiDxeSmmT= btCommonLib/TbtCommonLib.inf + !endif + DxeTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/DxeTbtPol= icyLib/DxeTbtPolicyLib.inf + # + # Silicon Init Package + # + !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc + PchHsioLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchHsioLib/PeiDxe= SmmPchHsioLib.inf + MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPci= Lib.inf + PchPmcLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchPmcLib/PeiDxeSm= mPchPmcLib.inf + + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf + +[LibraryClasses.IA32] + # + # PEI phase common + # + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf + !if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/P= eiTestPointCheckLib.inf + !endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf + HdaVerbTableLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiHdaVerbTableLib/Pei= HdaVerbTableLib.inf + + # Tbt + !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + PeiTbtPolicyLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/PeiTbtP= olicyLib/PeiTbtPolicyLib.inf + PeiDTbtInitLib|$(PLATFORM_BOARD_PACKAGE)/Features/Tbt/Library/Private/= PeiDTbtInitLib/PeiDTbtInitLib.inf + !endif + + # + # Silicon Init Package + # + !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc + PeiPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyIni= tLib/PeiPolicyInitLib.inf + PeiPolicyBoardConfigLib|$(PROJECT)/Library/PeiPolicyBoardConfigLib/Pei= PolicyBoardConfigLib.inf + PeiPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiPolicyU= pdateLib/PeiPolicyUpdateLib.inf + PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHo= oklib.inf + !if $(TARGET) =3D=3D DEBUG + GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLib/BaseG= pioCheckConflictLib.inf + !else + GpioCheckConflictLib|$(PROJECT)/Library/BaseGpioCheckConflictLibNull/B= aseGpioCheckConflictLibNull.inf + !endif + +[LibraryClasses.IA32.SEC] + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf + SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf + TimerLib|$(PLATFORM_BOARD_PACKAGE)/Library/AcpiTimerLib/BaseAcpiTimerLib= .inf + +[LibraryClasses.X64] + # + # DXE phase common + # + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf + !if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/D= xeTestPointCheckLib.inf + !endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/DxeMultiBoardInitSupportLib.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/DxeMultiBoardAcpiSupportLib.inf + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf + + DxePolicyBoardConfigLib|$(PROJECT)/Library/DxePolicyBoardConfigLib/DxePo= licyBoardConfigLib.inf + DxePolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxePolicyUpd= ateLib/DxePolicyUpdateLib.inf + # + # Silicon Init Package + # + !include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + +[LibraryClasses.X64.DXE_SMM_DRIVER] + SpiFlashCommonLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/SmmSpiFlashCommonLi= b/SmmSpiFlashCommonLib.inf + !if $(TARGET) =3D=3D DEBUG + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/S= mmTestPointCheckLib.inf + !endif + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf + BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/SmmMultiBoardAcpiSupportLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + +[LibraryClasses.X64.DXE_RUNTIME_DRIVER] + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf + !include OpenBoardPkgPcd.dsc + +[Components.IA32] + # + # Common + # + !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc + + # + # FSP wrapper SEC Core + # + UefiCpuPkg/SecCore/SecCore.inf { + + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf + } + + # + # Silicon + # + !include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc + + # + # Platform + # + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib= .inf + !else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf + !endif + NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf + } + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf { + + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPo= licyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + } + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPostMemLi= b.inf + !else + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.i= nf + !endif + } + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +#to do $(PLATFORM_PACKAGE)/FspWrapper/FspWrapperPeim/FspWrapperPeim.inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf { + + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPo= licyUpdateLibNull/SiliconPolicyUpdateLibNull.inf + } + + # + # Security + # + + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf + !endif + + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf + + # Tbt + !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf + !endif + +[Components.X64] + + # + # Common + # + !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc + + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf + + UefiCpuPkg/CpuDxe/CpuDxe.inf + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + # + # Shell + # + ShellPkg/Application/Shell/Shell.inf { + + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE + + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Com= mandsLib.inf + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1C= ommandsLib.inf + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comma= ndsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1C= ommandsLib.inf + NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2C= ommandsLib.inf + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommand= Lib.inf + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandlePars= ingLib.inf + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfg= CommandLib.inf + ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib= .inf + ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf + } + + # + # Silicon + # + !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc + + # Tbt + !if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf + $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf + $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf + !endif + + # + # Platform + # + $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf{ + + NULL|$(PROJECT)/Library/BaseFuncLib/BaseFuncLib.inf + } + + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf { + + SiliconPolicyInitLib|MinPlatformPkg/PlatformInit/Library/SiliconPoli= cyInitLibNull/SiliconPolicyInitLibNull.inf + SiliconPolicyUpdateLib|MinPlatformPkg/PlatformInit/Library/SiliconPolic= yUpdateLibNull/SiliconPolicyUpdateLibNull.inf + } + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf + + # + # OS Boot + # + !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf + $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf { + + !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE + BoardAcpiEnableLib|$(PROJECT)/Library/BoardAcpiLib/SmmBoardAcpiEna= bleLib.inf + !else + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.i= nf + !endif + } + + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf + + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046 + + !if $(TARGET) =3D=3D DEBUG + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialP= ort.inf + !endif + } + + !endif + + # + # Security + # + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf + + !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf + !endif + + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf + + # + # Other + # + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf + + !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc + !include OpenBoardPkgBuildOption.dsc + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgBuildOption.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeUR= vp/OpenBoardPkgBuildOption.dsc new file mode 100644 index 0000000000..be1d47c719 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgBu= ildOption.dsc @@ -0,0 +1,154 @@ +## @file +# platform build option configuration file. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[BuildOptions] +# Define Build Options both for EDK and EDKII drivers. + + + DEFINE DSC_S3_BUILD_OPTIONS =3D + + DEFINE DSC_CSM_BUILD_OPTIONS =3D + +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE + DEFINE DSC_ACPI_BUILD_OPTIONS =3D -DACPI_SUPPORT=3D1 +!else + DEFINE DSC_ACPI_BUILD_OPTIONS =3D +!endif + + DEFINE BIOS_GUARD_BUILD_OPTIONS =3D + + DEFINE OVERCLOCKING_BUILD_OPTION =3D + + DEFINE FSP_BINARY_BUILD_OPTIONS =3D + + DEFINE FSP_WRAPPER_BUILD_OPTIONS =3D -DFSP_WRAPPER_FLAG + + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =3D + + DEFINE RESTRICTED_OPTION =3D + + + DEFINE SV_BUILD_OPTIONS =3D + + DEFINE TEST_MENU_BUILD_OPTION =3D + +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL- +!else + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D +!endif + + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =3D + + + DEFINE TPM_BUILD_OPTION =3D + + DEFINE TPM2_BUILD_OPTION =3D + + DEFINE DSC_TBT_BUILD_OPTIONS =3D + + DEFINE DSC_DCTT_BUILD_OPTIONS =3D + + DEFINE EMB_BUILD_OPTIONS =3D + + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =3D -DMEM_DOWN_FLAG=3D1 + + DEFINE DSC_KBCEMUL_BUILD_OPTIONS =3D + + DEFINE BOOT_GUARD_BUILD_OPTIONS =3D + + DEFINE SECURE_BOOT_BUILD_OPTIONS =3D + + DEFINE USBTYPEC_BUILD_OPTION =3D + + DEFINE CAPSULE_BUILD_OPTIONS =3D + + DEFINE PERFORMANCE_BUILD_OPTION =3D + + DEFINE DEBUGUSEUSB_BUILD_OPTION =3D + + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =3D -DDISABLE_NEW_= DEPRECATED_INTERFACES=3D1 + + DEFINE SINITBIN_BUILD_OPTION =3D + + DEFINE MINTREE_FLAG_BUILD_OPTION =3D -DMINTREE_FLAG=3D1 + + DEFINE CPUTYPE_BUILD_OPTION =3D -DCPU_CFL=3D1 + +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTI= ONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_= OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGU= SEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_T= EMPRAM_INIT_AND_EXIT_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_B= UILD_OPTIONS) $(DSC_CSM_BUILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_= BUILD_OPTION) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYP= EC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION) +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(CPUTYPE_BUILD_OPTION) +[BuildOptions.Common.EDKII] + +# +# For IA32 Global Build Flag +# + *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI + *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_IA32_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + +# +# For IA32 Specific Build Flag +# +GCC: *_*_IA32_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI +MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) +MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) + +# +# For X64 Global Build Flag +# + *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 + *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + *_*_X64_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + + +# +# For X64 Specific Build Flag +# +GCC: *_*_X64_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 +MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) +MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) +MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) + + +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_C= ORE] + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support Memory= Attribute table +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER] + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX pro= tection +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE,= BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPL= ICATION] + #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096 + #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgConfig.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Op= enBoardPkgConfig.dsc new file mode 100644 index 0000000000..c68fecf50e --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgCo= nfig.dsc @@ -0,0 +1,128 @@ +## @file +# Platform configuration file. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[PcdsFixedAtBuild] + # + # Please select BootStage here. + # Stage 1 - enable debug (system deadloop after debug init) + # Stage 2 - mem init (system deadloop after mem init) + # Stage 3 - boot to shell only + # Stage 4 - boot to OS + # Stage 5 - boot to OS with security boot enabled + # + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4 + +[PcdsFeatureFlag] + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE +!endif + + gBoardModuleTokenSpaceGuid.PcdTbtEnable|FALSE + # + # More fine granularity control below: + # + + gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport|TRUE + +# +# TRUE is ENABLE. FALSE is DISABLE. +# +# +# BIOS build switches configuration +# + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + +# CPU + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE + +# SA + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSgEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSaOcEnable|TRUE + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE + +# ME + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPttEnable|TRUE + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE + + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCsmEnable|FALSE + gSiPkgTokenSpaceGuid.PcdTraceHubEnable|TRUE + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE + gSiPkgTokenSpaceGuid.PcdUseHpetTimer|TRUE # TRUE -= HPET / FALSE - 8254 timer is used. + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE + + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE + gSiPkgTokenSpaceGuid.PcdCflCpuEnable|TRUE + gSiPkgTokenSpaceGuid.PcdIpuEnable|TRUE + gSiPkgTokenSpaceGuid.PcdGnaEnable|TRUE + +# +# Override some PCDs for specific build requirements. +# + # + # Disable USB debug message when Source Level Debug is enabled + # because they cannot be enabled at the same time. + # + + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE + + !if $(TARGET) =3D=3D DEBUG + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !else + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE + !endif + + !if $(TARGET) =3D=3D DEBUG + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE + !else + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE + !endif + + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkgPcd.dsc b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenB= oardPkgPcd.dsc new file mode 100644 index 0000000000..96d65133ae --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkgPc= d.dsc @@ -0,0 +1,245 @@ +## @file +# Platform description. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Pcd Section - list of all EDK II PCD Entries defined by this Platform +# +##########################################################################= ###### +[PcdsFeatureFlag.common] + #gEfiMdeModulePkgTokenSpaceGuid.PcdFrameworkCompatibilitySupport|TRUE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE +!if $(TARGET) =3D=3D RELEASE + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE +!else + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE + + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE + + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE + + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE + +[PcdsFixedAtBuild.common] + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140 +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1 +!endif + + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 + + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 + + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000 +!if $(TARGET) =3D=3D RELEASE + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0 + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3 +!else + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS) + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01 + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000 + gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE + +# +# 8MB Default +# +gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 + +# +# 16MB TSEG in Debug build only. +# +!if $(TARGET) =3D=3D DEBUG + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000 +!endif + + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08 + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC + + !if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x402 + !else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x188B + !endif + + + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x4b + !if $(TARGET) =3D=3D RELEASE + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x70 + !else + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xE0 + !endif + + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEAC000 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFDC0000 + + ## Specifies the size of the microcode Region. + # @Prompt Microcode Region size. + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 + + ## Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + + ## Specifies the AP wait loop state during POST phase. + # The value is defined as below. + # 1: Place AP in the Hlt-Loop state. + # 2: Place AP in the Mwait-Loop state. + # 3: Place AP in the Run-Loop state. + # @Prompt The AP wait loop state. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 + + + # + # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags + # + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will = validate that input and output buffers lie entirely within the expected fix= ed memory regions. + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will= validate that input and output pointers embedded within the fixed communic= ation buffer only refer to address ranges \ + # that lie entirely within the expected fixed memory regions. + # BIT2: Firmware setting this bit is an indication that it will not allo= w reconfiguration of system resources via non-architectural mechanisms. + # BIT3-31: Reserved + # + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07 + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} +!endif + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6 + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00} +!endif + +[PcdsFixedAtBuild.IA32] + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 + +[PcdsFixedAtBuild.X64] + # Default platform supported RFC 4646 languages: (American) English + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US" + + +[PcdsPatchableInModule.common] + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0208 + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046 + +!if $(TARGET) =3D=3D DEBUG + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1 +!endif + +[PcdsDynamicHii.X64.DEFAULT] + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout" + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport" + +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout" +!endif + +[PcdsDynamicDefault] + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0xFFD50000 + # Platform will pre-allocate UPD buffer and pass it to FspWrapper + # Those dummy address will be patched before FspWrapper executing + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0 + + ## Specifies max supported number of Logical Processors. + # @Prompt Configure max supported number of Logical Processors + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16 + +[PcdsDynamicDefault.common.DEFAULT] + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE + # + # Set video to native resolution as Windows 8 WHCK requirement. + # + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0x0 + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0x0 + + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0 + + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00 + +[PcdsDynamicDefault.common.DEFAULT] + + # Tbt + gBoardModuleTokenSpaceGuid.PcdDTbtGpioLevel | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtForcepowerGpioPad | 13 + gBoardModuleTokenSpaceGuid.PcdDTbtCioPlugEventGpioPad | 0x02010011 + gBoardModuleTokenSpaceGuid.PcdDTbtWakeupSupport | 0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtHotSMI | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtHotNotify | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtSetClkReq| 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtAspm | 0x0 + gBoardModuleTokenSpaceGuid.PcdDTbtAcDcSwitch | 0x0 + + gBoardModuleTokenSpaceGuid.PcdRtd3Tbt | 0x1 + gBoardModuleTokenSpaceGuid.PcdRtd3TbtClkReq | 0x1 + gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 + gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0 + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include= /Fdf/FlashMapInclude.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/Whiskeyla= keURvp/Include/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000..9209b9e88a --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/Fl= ashMapInclude.fdf @@ -0,0 +1,49 @@ +## @file +# FDF file of Platform. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# +# 8 M BIOS - for FSP wrapper +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# +DEFINE FLASH_BASE =3D 0x= FF800000 # +DEFINE FLASH_SIZE =3D 0x= 00800000 # +DEFINE FLASH_BLOCK_SIZE =3D 0x= 00010000 # +DEFINE FLASH_NUM_BLOCKS =3D 0x= 00000080 # +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D# + +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D 0x= 00000000 # Flash addr (0xFF800000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D 0x= 00040000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D 0x= 00000000 # Flash addr (0xFF800000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D 0x= 0001E000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D 0x= 0001E000 # Flash addr (0xFF81E000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D 0x= 00002000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D 0x= 00020000 # Flash addr (0xFF820000) +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D 0x= 00020000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x= 00040000 # Flash addr (0xFF840000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D 0x= 00060000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D 0x= 000A0000 # Flash addr (0xFF8A0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x= 00070000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D 0x= 00110000 # Flash addr (0xFF910000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x= 00090000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D 0x= 001A0000 # Flash addr (0xFF9A0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x= 00190000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D 0x= 00330000 # Flash addr (0xFFB30000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x= 00170000 # +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D 0x= 004A0000 # Flash addr (0xFFCA0000) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D 0x= 000B0000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D 0x= 00550000 # Flash addr (0xFFD50000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x= 00070000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 005C0000 # Flash addr (0xFFDC0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 000EC000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 006AC000 # Flash addr (0xFFEAC000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00014000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006C0000 # Flash addr (0xFFEC0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00140000 # + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoa= rdPkg.fdf b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoar= dPkg.fdf new file mode 100644 index 0000000000..611078e4b4 --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.f= df @@ -0,0 +1,706 @@ +## @file +# FDF file of Platform. +# +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +[Defines] + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf + +##########################################################################= ###### +# +# FD Section +# The [FD] Section is made up of the definition statements and a +# description of what goes into the Flash Device Image. Each FD section +# defines one flash "device" image. A flash device image may be one of +# the following: Removable media bootable image (like a boot floppy +# image,) an Option ROM image (that would be "flashed" into an add-in +# card,) a System "Flash" image (that would be burned into a system's +# flash) or an Update ("Capsule") image that will be used to update and +# existing system flash. +# +##########################################################################= ###### +[FD.WhiskeylakeURvp] +# +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, c= annot be +# assigned with PCD values. Instead, it uses the definitions for its varie= ty, which +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS. +# +BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddr= ess #The base address of the FLASH Device. +Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size in bytes of the FLASH Device +ErasePolarity =3D 1 +BlockSize =3D $(FLASH_BLOCK_SIZE) +NumBlocks =3D $(FLASH_NUM_BLOCKS) + +DEFINE SIPKG_DXE_SMM_BIN =3D INF +DEFINE SIPKG_PEI_BIN =3D INF + +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macr= o expression is not supported. +# So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to = get the real CodeCache base address. +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvPreMemoryOffset) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui= d.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffse= t) +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize) +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60 +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60 +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiP= kgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashM= icrocodeFvOffset) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= SiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x60 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok= enSpaceGuid.PcdBiosAreaBaseAddress +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok= enSpaceGuid.PcdBiosSize +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok= enSpaceGuid.PcdBiosAreaBaseAddress +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok= enSpaceGuid.PcdBiosSize +##########################################################################= ###### +# +# Following are lists of FD Region layout which correspond to the location= s of different +# images within the flash device. +# +# Regions must be defined in ascending order and may not overlap. +# +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by +# the pipe "|" character, followed by the size of the region, also in hex = with the leading +# "0x" characters. Like: +# Offset|Size +# PcdOffsetCName|PcdSizeCName +# RegionType +# Fv Size can be adjusted +# +##########################################################################= ###### +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModul= ePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +#NV_VARIABLE_STORE +DATA =3D { + ## This is the EFI_FIRMWARE_VOLUME_HEADER + # ZeroVector [] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # FileSystemGuid + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C, + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50, + # FvLength: 0x40000 + 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, + #Signature "_FVH" #Attributes + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00, + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision + # + # Be careful on CheckSum field. + # + 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02, + #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block + 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, + #Blockmap[1]: End + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + ## This is the VARIABLE_STORE_HEADER +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, 0x= 439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }} + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43, + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92, +!else + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x98,= 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }} + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41, + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d, +!endif + #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x1DFB8 + # This can speed up the Variable Dispatch a bit. + 0xB8, 0xDF, 0x01, 0x00, + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32 + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +#NV_FTW_WORKING +DATA =3D { + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }} + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49, + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95, + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF, + # WriteQueueSize: UINT64 + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +} + +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModul= ePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +#NV_FTW_SPARE + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvAdvancedSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvAdvancedSize +FV =3D FvAdvanced + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvSecuritySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvSecuritySize +FV =3D FvSecurity + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvOsBootSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize +FV =3D FvOsBoot + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvUefiBootSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvUefiBootSize +FV =3D FvUefiBoot + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvPostMemorySize +FV =3D FvPostMemory + +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvSize +#Microcode +FV =3D FvMicrocode + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspSSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspSSize +# FSP_S Section +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspMSize +# FSP_M Section +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspTSize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspTSize +# FSP_T Section +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd + +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTok= enSpaceGuid.PcdFlashFvPreMemorySize +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgToken= SpaceGuid.PcdFlashFvPreMemorySize +FV =3D FvPreMemory + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### +[FV.FvMicrocode] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D FALSE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D FALSE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE + +FILE RAW =3D 197DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.bin +} + +[FV.FvPreMemory] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D + +INF UefiCpuPkg/SecCore/SecCore.inf +INF MdeModulePkg/Core/Pei/PeiMain.inf +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf + +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM= em.inf + +[FV.FvPostMemoryUncompact] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf + +# Init Board Config PCD +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i= nf +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPost= Mem.inf + +FILE RAW =3D C9505BC0-AA3D-4056-9995-870C8DE8594E { + $(PLATFORM_SI_BIN_PACKAGE)/ChipsetInit/CnlPchLpChipsetInitTable_Dx.bin + } +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE +FILE FREEFORM =3DPCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFil= eGuid) { + SECTION RAW =3D $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin + SECTION UI =3D "Vbt" +} +FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D { + SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp +} +!endif # PcdPeiDisplayEnable + + +[FV.FvPostMemory] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 9DFE49DB-8EF0-4D9C-B273-0036144DE917 + +FILE FV_IMAGE =3D 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE { + SECTION FV_IMAGE =3D FvPostMemoryUncompact + } +} + +[FV.FvUefiBootUncompact] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5 + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf +INF $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf + +INF UefiCpuPkg/CpuDxe/CpuDxe.inf +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf + +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf +INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + +INF ShellPkg/Application/Shell/Shell.inf + +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf +INF $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf +INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf + +INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf + + +[FV.FvUefiBoot] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 0496D33D-EA79-495C-B65D-ABF607184E3B + +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvUefiBootUncompact + } + } + +[FV.FvOsBootUncompact] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf + +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf + +INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/Boar= dAcpiDxe/BoardAcpiDxe.inf +INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + +!endif + +[FV.FvLateSilicon] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitD= xe.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmA= ccess.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSm= iDispatcher.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmC= ontrol.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf + +INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab= les/SaAcpiTables.inf +INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab= les/SaSsdt/SaSsdt.inf + +!endif + +[FV.FvOsBoot] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 13BF8810-75FD-4B1A-91E6-E16C4201F80A + +FILE FV_IMAGE =3D B9020753-84A8-4BB6-947C-CE7D41F5CE39 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvOsBootUncompact + } + } + +FILE FV_IMAGE =3D D4632741-510C-44E3-BE21-C3D6D7881485 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvLateSilicon + } + } + +[FV.FvSecurityPreMemory] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 #FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf + +INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoS= amplePei.inf + +INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + +[FV.FvSecurityPostMemory] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 #FV alignment and FV attributes setting. +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 4199E560-54AE-45E5-91A4-F7BC3804E14A + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf + +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf +!endif + +[FV.FvSecurityLate] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D F753FE9A-EEFD-485B-840B-E032D538102C + +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf +INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf + +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE +INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf +!endif +!endif + +[FV.FvSecurity] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF + +FILE FV_IMAGE =3D 757CC075-1428-423D-A73C-22639706C119 { + SECTION FV_IMAGE =3D FvSecurityPreMemory + } + +FILE FV_IMAGE =3D 80BB8482-44D5-4BEC-82B5-8D87A933830B { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvSecurityPostMemory + } + } + +FILE FV_IMAGE =3D C83522D9-80A1-4D95-8C25-3F1370497406 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvSecurityLate + } + } + +[FV.FvAdvancedPreMem] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 6053D78A-457E-4490-A237-31D0FBE2F305 + +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf +!endif + +[FV.FvAdvancedPostMem] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D BE3DF86F-E464-44A3-83F7-0D27E6B88C27 + +[FV.FvAdvancedLate] +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D + +!if gBoardModuleTokenSpaceGuid.PcdTbtEnable =3D=3D TRUE +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf +INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf +INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf +!endif + +[FV.FvAdvanced] +BlockSize =3D $(FLASH_BLOCK_SIZE) +FvAlignment =3D 16 +ERASE_POLARITY =3D 1 +MEMORY_MAPPED =3D TRUE +STICKY_WRITE =3D TRUE +LOCK_CAP =3D TRUE +LOCK_STATUS =3D TRUE +WRITE_DISABLED_CAP =3D TRUE +WRITE_ENABLED_CAP =3D TRUE +WRITE_STATUS =3D TRUE +WRITE_LOCK_CAP =3D TRUE +WRITE_LOCK_STATUS =3D TRUE +READ_DISABLED_CAP =3D TRUE +READ_ENABLED_CAP =3D TRUE +READ_STATUS =3D TRUE +READ_LOCK_CAP =3D TRUE +READ_LOCK_STATUS =3D TRUE +FvNameGuid =3D B23E7388-9953-45C7-9201-0473DDE5487A + +FILE FV_IMAGE =3D 35E7406A-5842-4F2B-BC62-19022C12AF74 { + SECTION FV_IMAGE =3D FvAdvancedPreMem + } + +FILE FV_IMAGE =3D F5DCB34F-27EA-48AC-9406-C894F6D587CA { + SECTION FV_IMAGE =3D FvAdvancedPostMem + } + +FILE FV_IMAGE =3D 5248467B-B87B-4E74-AC02-398AF4BCB712 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE { + SECTION FV_IMAGE =3D FvAdvancedLate + } + } + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf + + diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_c= onfig.cfg b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_co= nfig.cfg new file mode 100644 index 0000000000..1b0619bc1c --- /dev/null +++ b/Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.c= fg @@ -0,0 +1,33 @@ +# @ build_config.cfg +# This is the WhiskeylakeURvp board specific build settings +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN =3D +EDK_SETUP_OPTION =3D +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D WhiskeylakeOpenBoardPkg +PROJECT =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp +BOARD =3D WhiskeylakeURvp +FLASH_MAP_FDF =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Fdf/Flas= hMapInclude.fdf +PROJECT_DSC =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg.dsc +BOARD_PKG_PCD_DSC =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/OpenBoardPkg= Pcd.dsc +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D TRUE +FSP_BIN_PKG =3D CoffeeLakeFspBinPkg +FSP_PKG_NAME =3D CoffeelakeSiliconPkg +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45914): https://edk2.groups.io/g/devel/message/45914 Mute This Topic: https://groups.io/mt/32918208/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 10:10:17 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45912+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45912+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1566001034; cv=none; d=zoho.com; s=zohoarc; b=MTiDyhoeqwL8lLo/SzcU5WuElZe61ChPY4RK+3hH3dRIW6RPQK4Bu0/3Yxop3FtsoO0R2w1zAY3nTNWE9cpvqYh8cyBIpONx2X3d/NeOcxi+AtC9GY/w15fbQd4KgxVX/A4Zp4x78+fnzy0EWreEGhu0NJZ9ouxtPrt9e0q0log= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1566001034; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=9/BScffpO9YqRxyRgn5p9P//5xpugcSuBKiEiCUZUn0=; b=KTqAu5jOZ0WhKCmfo9TGY0mk6yiyk7Nd7tZ+ZFgINhKkgrCBJYUBjjj2ywSJDFY/d9rwRe0nXL1R2M185C76PJB2/+BHsw7rWWvDI/qhOcGsou527bwCjjr6W3psfvpjaV34AdF8m0dukhr7IoVkqB5x+2co/umFHXKaPlubtAk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45912+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1566001034229787.6995780242372; Fri, 16 Aug 2019 17:17:14 -0700 (PDT) Return-Path: X-Received: from mga07.intel.com (mga07.intel.com []) by groups.io with SMTP; Fri, 16 Aug 2019 17:17:13 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Aug 2019 17:17:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,395,1559545200"; d="scan'208";a="182319384" X-Received: from makuback-desk1.amr.corp.intel.com ([10.7.159.162]) by orsmga006.jf.intel.com with ESMTP; 16 Aug 2019 17:17:01 -0700 From: "Kubacki, Michael A" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Liming Gao , Nate DeSimone , Michael D Kinney , Ankit Sinha Subject: [edk2-devel] [edk2-platforms][PATCH V1 37/37] Add WhiskeylakeOpenBoardPkg to global build config and documentation Date: Fri, 16 Aug 2019 17:16:03 -0700 Message-Id: <20190817001603.30632-38-michael.a.kubacki@intel.com> In-Reply-To: <20190817001603.30632-1-michael.a.kubacki@intel.com> References: <20190817001603.30632-1-michael.a.kubacki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.a.kubacki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1566001033; bh=gCkMNzIwi7BYDyM5wa+nPSTjEdPIxSLIsbF8RlF4REY=; h=Cc:Date:From:Reply-To:Subject:To; b=JMWV9o1Twg/HbelAkfWKtMxE5v08qk7o5ATHy95ncz0qxHgx78kc3YUov4q77Z8kG3v U/exSy9okUnkkvDo6xajmW1jNBARttLGE6D+KB61J8PkM6cB1gDLQtg5D4aFp05LmzjXn VODHCCDLAOvTIjYVu2NLdxdSlq6jICMD6Is= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D2083 * Adds the WhiskeylakeURvp board as a build option in build.cfg so it it is listed as a valid build target. * Updates relevant Readme.md files to include instructions for WhiskeylakeOpenBoardPkg. * Adds the maintainers for WhiskeylakeOpenBoardPkg to maintainers.txt. Cc: Sai Chaganty Cc: Chasel Chiu Cc: Liming Gao Cc: Nate DeSimone Cc: Michael D Kinney Cc: Ankit Sinha Signed-off-by: Michael Kubacki Reviewed-by: Ankit Sinha --- Maintainers.txt | 5 +++ Platform/Intel/Readme.md | 44 +++++++++++++------- Platform/Intel/build.cfg | 4 +- Readme.md | 1 + 4 files changed, 38 insertions(+), 16 deletions(-) diff --git a/Maintainers.txt b/Maintainers.txt index bc8cbd6458..b16432bf87 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -98,6 +98,11 @@ M: Shifei A Lu M: Xiaohu Zhou M: Isaac W Oram =20 +Platform/Intel/WhiskeylakeOpenBoardPkg +M: Chasel Chiu +M: Michael Kubacki +M: Nate DeSimone + Platform/Intel/Tools M: Bob Feng M: Liming Gao diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md index 00f42985a2..aaf6ef4d3e 100644 --- a/Platform/Intel/Readme.md +++ b/Platform/Intel/Readme.md @@ -53,9 +53,10 @@ A UEFI firmware implementation using MinPlatformPkg is c= onstructed using the fol =20 =20 ## Board Support +* The `ClevoOpenBoardPkg` contains board implementations for Clevo systems. * The `KabylakeOpenBoardPkg` contains board implementations for Kaby Lake = systems. * The `PurleyOpenBoardPkg` contains board implementations for Purley syste= ms. -* The `ClevoOpenBoardPkg` contains board implementations for Clevo systems. +* The `WhiskeylakeOpenBoardPkg` contains board implementations for Whiskey= Lake systems. =20 ## Board Package Organization The board package follows the standard EDK II package structure with the f= ollowing additional elements and guidelines: @@ -189,7 +190,12 @@ return back to the minimum platform caller. | | | |---build_config.cfg: BoardMtO= lympus specific | | | | build se= ttings, environment variables. | | | |---build_board.py: Optional b= oard-specific pre-build, - | | | | build, pos= t-build and clean functions. + | | | build, pos= t-build and clean functions. + | | | + | | |------WhiskeylakeOpenBoardPkg + | | | |------WhiskeylakeURvp + | | | |---build_config.cfg: Whiskeyl= akeURvp specific build + | | | settings= environment variables. |------FSP =20 @@ -222,19 +228,6 @@ Users can also flash the UEFI firmware image to the hi= ghest area of the flash re =20 ### **Known limitations** =20 -**KabylakeOpenBoardPkg** -1. This firmware project has only been tested on the Intel KabylakeRvp3 bo= ard. -2. This firmware project has only been tested booting to Microsoft Windows= 10 x64 with AHCI mode and Integrated Graphic - Device. -3. The Windows build was tested on Windows 10 with Microsoft Visual Studio= 2015. -4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0. -5. The build was tested with NASM version 2.11.08. - -**PurleyOpenBoardPkg** -1. This firmware project has only been tested on the Microsoft MtOlympus b= oard. -2. This firmware project has only been tested booting to Microsoft Windows= Server 2016 with NVME on M.2 slot. -3. This firmware project build has only been tested using the Microsoft Vi= sual Studio 2015 compiler. - **ClevoOpenBoardPkg** 1. Currently, support is only being added for the N1xxWU series of boards. 2. The Windows build was tested on Windows 10 with Microsoft Visual Studio= 2015 compiler. @@ -244,6 +237,27 @@ Users can also flash the UEFI firmware image to the hi= ghest area of the flash re 6. The firmware project applies to all Clevo supported board configuration= s but is only being tested on System 76 Galago Pro devices. =20 +**KabylakeOpenBoardPkg** +1. This firmware project has only been tested on the Intel KabylakeRvp3 bo= ard. +2. This firmware project has only been tested booting to Microsoft Windows= 10 x64 with AHCI mode and Integrated Graphic + Device. +3. The Windows build was tested on Windows 10 with Microsoft Visual Studio= 2015. +4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0. +5. The build was tested with NASM version 2.11.08. + +**PurleyOpenBoardPkg** +1. This firmware project has only been tested on the Microsoft MtOlympus b= oard. +2. This firmware project has only been tested booting to Microsoft Windows= Server 2016 with NVME on M.2 slot. +3. This firmware project build has only been tested using the Microsoft Vi= sual Studio 2015 compiler. + +**WhiskeylakeOpenBoardPkg** +1. This firmware project has only been tested on the Intel WhiskeylakeURvp= board. +2. This firmware project has only been tested booting to Microsoft Windows= 10 x64 with AHCI mode and Integrated Graphic + Device. +3. The Windows build was tested on Windows 10 with Microsoft Visual Studio= 2015. +4. The Linux build was tested on Ubuntu 16.04.5 LTS with GCC version 5.4.0. +5. The build was tested with NASM version 2.11.08. + ### **Planned Activities** * Replace the batch build scripts with cross-platform Python build scripts. * Publish a Minimum Platform specification to describe the architecture an= d interfaces in more detail. diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg index fc6e4fe824..b6d32ada49 100644 --- a/Platform/Intel/build.cfg +++ b/Platform/Intel/build.cfg @@ -51,6 +51,8 @@ NUMBER_OF_PROCESSORS =3D 0 =20 [PLATFORMS] # board_name =3D path_to_board_build_config.cfg +BoardMtOlympus =3D PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg KabylakeRvp3 =3D KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg N1xxWU =3D ClevoOpenBoardPkg/N1xxWU/build_config.cfg -BoardMtOlympus =3D PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg +WhiskeylakeURvp =3D WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.c= fg + diff --git a/Readme.md b/Readme.md index 1befd0b544..e4f211eee6 100644 --- a/Readme.md +++ b/Readme.md @@ -228,6 +228,7 @@ they will be documented with the platform. * [Clevo](Platform/Intel/ClevoOpenBoardPkg) * [Kaby Lake](Platform/Intel/KabylakeOpenBoardPkg) * [Purley](Platform/Intel/PurleyOpenBoardPkg) +* [Whiskey Lake](Platform/Intel/WhiskeylakeOpenBoardPkg) =20 For more information, see the [EDK II Minimum Platform Specification](https://edk2-docs.gitbooks.io/edk-= ii-minimum-platform-specification). --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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