From nobody Thu May 2 18:06:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45774+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45774+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565927855; cv=none; d=zoho.com; s=zohoarc; b=KIn116lESAqIeSnolSC/E2eBJDiwkz9sRMN+b1QJ64LXKCB5pqWXGXNTCs4HxGhqCkwMeY5HgGvR7IKNRcLuimOM/vehqhm7ZODlL4VGqv3zOnpWWtlfG+jZkR0v92q8AS/7v4RLzLiyS74pYi/jXpt9CEiVpaKEa+ZH5tCA9ds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565927855; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=LFEPBa4ZZwMkKDdi6tsKfc2PnEDW5bPKws6VKMGeslg=; b=EXa+NShsra5ot86v+tqe8THwmMnqp4QPZ0ojjgQfNAhCxd5hK6JXY8nCtPLwpTgPUv+nkHnnmX7jxfaARF1Tb8Ni2xOo9D72//v5dvNWV/fK5uy1OkG6PU3o+1fBynimWkTENqiUfQePdblRCyqyvd7n4GbTp8gUVBkNpxZa6YU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45774+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565927855160346.19589288807026; Thu, 15 Aug 2019 20:57:35 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 15 Aug 2019 20:57:34 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 20:57:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="376590667" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga005.fm.intel.com with ESMTP; 15 Aug 2019 20:57:32 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek , Star Zeng Subject: [edk2-devel] [Patch v4 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros. Date: Fri, 16 Aug 2019 11:57:25 +0800 Message-Id: <20190816035730.3252-2-eric.dong@intel.com> In-Reply-To: <20190816035730.3252-1-eric.dong@intel.com> References: <20190816035730.3252-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565927854; bh=ftYlOu8few5U3aGjTNwzsDJXvMZ5ldsYv5bhmOLKp8Y=; h=Cc:Date:From:Reply-To:Subject:To; b=saglu5pXhwPdId903xkHVjh/aZEtC3Bl1X8orp+AC6Hjt6Wk/pZvVW/CqG61rE9I0cq SvWVjo9WN09aqE/EPbrJFpcg99OHFMFJi6IkcgLpQgHaemhcZByVUHQ5hrA+lxMOP4Ksj bKN+o1KhKMR9H9HOaGtfBw4rH0DCfEx1L6c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Add below new micros which test the current value before write the new value. Only write new value when current value not same as new value. CPU_REGISTER_TABLE_TEST_THEN_WRITE32 CPU_REGISTER_TABLE_TEST_THEN_WRITE64 CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD Also add below API: CpuRegisterTableTestThenWrite Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng Acked-by: Laszlo Ersek Reviewed-by: Ray Ni --- UefiCpuPkg/Include/AcpiCpuData.h | 3 +- .../Include/Library/RegisterCpuFeaturesLib.h | 91 +++++++++++++++++++ .../RegisterCpuFeaturesLib.c | 44 ++++++++- 3 files changed, 134 insertions(+), 4 deletions(-) diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuD= ata.h index b963a2f592..77da5d4455 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -78,7 +78,8 @@ typedef struct { UINT32 Index; // offset 4 - 7 UINT8 ValidBitStart; // offset 8 UINT8 ValidBitLength; // offset 9 - UINT16 Reserved; // offset 10 - 11 + BOOLEAN TestThenWrite; // offset 10 + UINT8 Reserved1; // offset 11 UINT32 HighIndex; // offset 12-15, only valid for Me= moryMapped UINT64 Value; // offset 16-23 } CPU_REGISTER_TABLE_ENTRY; diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index e420e7f075..5bd464b32e 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -348,6 +348,32 @@ CpuRegisterTableWrite ( IN UINT64 Value ); =20 +/** + Adds an entry in specified register table. + + This function adds an entry in specified register table, with given regi= ster type, + register index, bit section and value. + + Driver will test the current value before setting new value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] ValueMask Mask of bits in register to write + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +VOID +EFIAPI +CpuRegisterTableTestThenWrite ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value + ); + /** Adds an entry in specified Pre-SMM register table. =20 @@ -390,6 +416,26 @@ PreSmmCpuRegisterTableWrite ( CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT3= 2, Value); \ } while(FALSE); =20 +/** + Adds a 32-bit register write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, and value. + + Driver will test the current value before setting new value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE32(ProcessorNumber, RegisterType= , Index, Value) \ + do { = \ + CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, M= AX_UINT32, Value); \ + } while(FALSE); + /** Adds a 64-bit register write entry in specified register table. =20 @@ -408,6 +454,26 @@ PreSmmCpuRegisterTableWrite ( CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT6= 4, Value); \ } while(FALSE); =20 +/** + Adds a 64-bit register write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, and value. + + Driver will test the current value before setting new value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE64(ProcessorNumber, RegisterType= , Index, Value) \ + do { = \ + CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, M= AX_UINT64, Value); \ + } while(FALSE); + /** Adds a bit field write entry in specified register table. =20 @@ -431,6 +497,31 @@ PreSmmCpuRegisterTableWrite ( CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMas= k, Value); \ } while(FALSE); =20 +/** + Adds a bit field write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, bit field section, and value. + + Driver will test the current value before setting new value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program. + @param[in] Index Index of the register to program. + @param[in] Type The data type name of a register structure. + @param[in] Field The bit fiel name in register structure to = write. + @param[in] Value Value to write to the bit field. + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD(ProcessorNumber, Register= Type, Index, Type, Field, Value) \ + do { = \ + UINT64 ValueMask; = \ + ValueMask =3D MAX_UINT64; = \ + ((Type *)(&ValueMask))->Field =3D 0; = \ + CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, ~= ValueMask, Value); \ + } while(FALSE); + /** Adds a 32-bit register write entry in specified register table. =20 diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesL= ib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index 67885bf69b..58910b8891 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -1025,6 +1025,8 @@ EnlargeRegisterTable ( @param[in] ValidBitStart Start of the bit section @param[in] ValidBitLength Length of the bit section @param[in] Value Value to write + @param[in] TestThenWrite Whether need to test current Value before w= riting. + **/ VOID CpuRegisterTableWriteWorker ( @@ -1034,7 +1036,8 @@ CpuRegisterTableWriteWorker ( IN UINT64 Index, IN UINT8 ValidBitStart, IN UINT8 ValidBitLength, - IN UINT64 Value + IN UINT64 Value, + IN BOOLEAN TestThenWrite ) { CPU_FEATURES_DATA *CpuFeaturesData; @@ -1070,6 +1073,7 @@ CpuRegisterTableWriteWorker ( RegisterTableEntry[RegisterTable->TableLength].ValidBitStart =3D ValidB= itStart; RegisterTableEntry[RegisterTable->TableLength].ValidBitLength =3D ValidB= itLength; RegisterTableEntry[RegisterTable->TableLength].Value =3D Value; + RegisterTableEntry[RegisterTable->TableLength].TestThenWrite =3D TestTh= enWrite; =20 RegisterTable->TableLength++; } @@ -1105,7 +1109,41 @@ CpuRegisterTableWrite ( Start =3D (UINT8)LowBitSet64 (ValueMask); End =3D (UINT8)HighBitSet64 (ValueMask); Length =3D End - Start + 1; - CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value); + CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value, FALSE); +} + +/** + Adds an entry in specified register table. + + This function adds an entry in specified register table, with given regi= ster type, + register index, bit section and value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] ValueMask Mask of bits in register to write + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +VOID +EFIAPI +CpuRegisterTableTestThenWrite ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value + ) +{ + UINT8 Start; + UINT8 End; + UINT8 Length; + + Start =3D (UINT8)LowBitSet64 (ValueMask); + End =3D (UINT8)HighBitSet64 (ValueMask); + Length =3D End - Start + 1; + CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value, TRUE); } =20 /** @@ -1139,7 +1177,7 @@ PreSmmCpuRegisterTableWrite ( Start =3D (UINT8)LowBitSet64 (ValueMask); End =3D (UINT8)HighBitSet64 (ValueMask); Length =3D End - Start + 1; - CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index,= Start, Length, Value); + CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index,= Start, Length, Value, FALSE); } =20 /** --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45774): https://edk2.groups.io/g/devel/message/45774 Mute This Topic: https://groups.io/mt/32894958/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 18:06:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45775+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45775+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565927857; cv=none; d=zoho.com; s=zohoarc; b=MeN4vr5opzM/VuegkAke02HAh4zpLHQSWzBvE/Zxw2HAcBo+HhU+uG5dEZBnveAGWvPvxIUCIA+olpAYWjctHX9QhA7gaF0U5KCvA+3MCTOrm57PcEIlxhNMtYzFRAjCIg0HayxTuFmk1BUTPtJXEdvmLWMr8Gy6seRld1FelpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565927857; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=ZloY+Csb9Ny0Iam+nFK8wV52yyW6UfjJZYrv2wWi0jE=; b=WHIYNsNOglv71eF1W8SDIt8mzQ4K6ds+Aj+IR6NQP8PYrYNmJHoMZtwGgNS48XaeSMN3rw2+dCkje1l6WXeJGlKJX0N+2OB3FZXgswwxKh6kNXD1L+hyVn25wDdS2gaGmeeS6arhQX07nds0k5S1QIr3qCtr+icq2oS0krmAIT4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45775+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565927857273176.51945996589927; Thu, 15 Aug 2019 20:57:37 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 15 Aug 2019 20:57:36 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 20:57:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="376590672" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga005.fm.intel.com with ESMTP; 15 Aug 2019 20:57:33 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v4 2/6] UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action. Date: Fri, 16 Aug 2019 11:57:26 +0800 Message-Id: <20190816035730.3252-3-eric.dong@intel.com> In-Reply-To: <20190816035730.3252-1-eric.dong@intel.com> References: <20190816035730.3252-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565927856; bh=SFsRXF2FDVQv44ySVmZF18bxPvWt3j8t20eHu2hXGpc=; h=Cc:Date:From:Reply-To:Subject:To; b=aY6yQMbzzeMCb98FI9K0dmEIc9bPwEr/4j9a7ovNpL0a364UuqENEZzT1QwlVSxcr4K +eZiSdVPSihqM7SgbYNR3BUb7AD0xCbwqISpIOeMudz6nEGkSh6ca4gqG/VGjvPZVBgtG PPeD7ZIhxJeF23o6efxT8oFeR/nFEbWHnXc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Eric Dong Cc: Ray Ni Reviewed-by: Laszlo Ersek Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 104 ++++++++++++++++++------------ 1 file changed, 62 insertions(+), 42 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index d8c6b19ead..627a3b87ac 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -159,6 +159,58 @@ S3WaitForSemaphore ( ) !=3D Value); } =20 +/** + Read / write CR value. + + @param[in] CrIndex The CR index which need to read/write. + @param[in] Read Read or write. TRUE is read. + @param[in,out] CrValue CR value. + + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. +**/ +UINTN +ReadWriteCr ( + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue + ) +{ + switch (CrIndex) { + case 0: + if (Read) { + *CrValue =3D AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + break; + case 2: + if (Read) { + *CrValue =3D AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + break; + case 3: + if (Read) { + *CrValue =3D AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + break; + case 4: + if (Read) { + *CrValue =3D AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + break; + default: + return EFI_UNSUPPORTED;; + } + + return EFI_SUCCESS; +} + /** Initialize the CPU registers from a register table. =20 @@ -188,6 +240,7 @@ ProgramProcessorRegister ( UINTN ProcessorIndex; UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; + EFI_STATUS Status; =20 // // Traverse Register Table of this logical processor @@ -206,50 +259,17 @@ ProgramProcessorRegister ( // The specified register is Control Register // case ControlRegister: - switch (RegisterTableEntry->Index) { - case 0: - Value =3D AsmReadCr0 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr0 (Value); - break; - case 2: - Value =3D AsmReadCr2 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr2 (Value); - break; - case 3: - Value =3D AsmReadCr3 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr3 (Value); - break; - case 4: - Value =3D AsmReadCr4 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr4 (Value); - break; - default: + Status =3D ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { break; } + Value =3D (UINTN) BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableE= ntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; // // The specified register is Model Specific Register --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45775): https://edk2.groups.io/g/devel/message/45775 Mute This Topic: https://groups.io/mt/32894959/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 18:06:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45776+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45776+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565927858; cv=none; d=zoho.com; s=zohoarc; b=DQczIUL6cZ38Dq+cYQ0dA8ORb3MLDwGoh8aNfUiQwvLpOVq0RDS9kEpXIW22rBSDf+MQaLMoeNDiK+QVar76W0IerHUPphrRv3dW0PBNB02IiraGdGkWe8zCceGLpJcY79jLQJJ3+5C9RiKQLBfdFiZCXMraV7ihpNz1bSRI/Kg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565927858; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=yCekOT+xwM1HNN2wzFS//c4Y7ZHzKbBKE6NIvmAG/A0=; b=aArIa0/DuXPX1OkhKAZeJh3Pqfr77M9XxUwgNzXyVEdcdEhsbHAuKDH8p1P0lc7Nv3aMF6dm9qS5F+F8kVZg0BJiQhuwDmTGwti3oZAhL3yhB0PlZZqlT0bBhBt0ASHYYpN91UqFY9h4H4QgIepytcTQY0VFxNwBjg2m9q2/kdA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45776+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565927858500760.7488632413467; Thu, 15 Aug 2019 20:57:38 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 15 Aug 2019 20:57:36 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 20:57:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="376590687" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga005.fm.intel.com with ESMTP; 15 Aug 2019 20:57:35 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v4 3/6] UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic. Date: Fri, 16 Aug 2019 11:57:27 +0800 Message-Id: <20190816035730.3252-4-eric.dong@intel.com> In-Reply-To: <20190816035730.3252-1-eric.dong@intel.com> References: <20190816035730.3252-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565927858; bh=hx3mww+d3YeUkSbV4SP3Uv2k7r+XWuEvufBgr7eGVnA=; h=Cc:Date:From:Reply-To:Subject:To; b=WYJ+rgS6ATw2NFK5ybHQ6NPuZDBdGYO/fTeqwYXZVDVVpnIL/5YE5WHnkwZIzIg1qKa UVsDrtx9j6uFDJJTMxIB3F93MjJWcVY5YIwKFphInuIXO3m5tQzddUhPYQKnGIuILtotu G+uyNELv5lsEQOBFwTAjIvmyjZ6M1MEdOpU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Reviewed-by: Laszlo Ersek Reviewed-by: Ray Ni --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 627a3b87ac..ba5cc0194c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -241,6 +241,7 @@ ProgramProcessorRegister ( UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; EFI_STATUS Status; + UINT64 CurrentValue; =20 // // Traverse Register Table of this logical processor @@ -263,6 +264,16 @@ ProgramProcessorRegister ( if (EFI_ERROR (Status)) { break; } + if (RegisterTableEntry->TestThenWrite) { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + break; + } + } Value =3D (UINTN) BitFieldWrite64 ( Value, RegisterTableEntry->ValidBitStart, @@ -275,6 +286,24 @@ ProgramProcessorRegister ( // The specified register is Model Specific Register // case Msr: + if (RegisterTableEntry->TestThenWrite) { + Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >=3D 64) { + if (Value =3D=3D RegisterTableEntry->Value) { + break; + } + } else { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + break; + } + } + } + // // If this function is called to restore register setting after INIT= signal, // there is no need to restore MSRs in register table. --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45776): https://edk2.groups.io/g/devel/message/45776 Mute This Topic: https://groups.io/mt/32894960/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 18:06:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45777+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45777+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565927858; cv=none; d=zoho.com; s=zohoarc; b=HyRYsMmkBXjkyie7lJK5szz2FUwJTMLhIEdSiLn5Z/l5lvEGz6CULWZVRqmCaQVow6hsuAwuBXVTcnB7RHVYcQNdWAq3K7JOZzZgYVYMzL3RmcdzzRvPCXI+A1tIrtDXKV6+a9Trwr1Oor5q/rFYOwaar3UjM/P2e4LMmG/PriE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565927858; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=PerdeuOzz8UAojqfS2MRoLtXZxjEKvMSRnnUlzBwhL8=; b=TIZs/RqakpWU62FAsoHH4Zqs10NoJwZbrLGWt2YlW7TfviMcWpU1kqQ0rPcf3nIf9Zmgs9HazWLto7y5BNUFzQ3/tpVrJX3Q5HdS3YOzkX9TixLOz6maDlfK0FeYPvmuOimqY+QeZAtEmpy+U0EDFkDlDokLR8YD4RPuhwHtCWA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45777+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565927858736539.2502227446104; Thu, 15 Aug 2019 20:57:38 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 15 Aug 2019 20:57:37 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 20:57:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="376590697" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga005.fm.intel.com with ESMTP; 15 Aug 2019 20:57:36 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v4 4/6] UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action. Date: Fri, 16 Aug 2019 11:57:28 +0800 Message-Id: <20190816035730.3252-5-eric.dong@intel.com> In-Reply-To: <20190816035730.3252-1-eric.dong@intel.com> References: <20190816035730.3252-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565927858; bh=sDtOaY4DMbq44KEJ/mO3Y5QZSZW1egZShOhgaUdz2II=; h=Cc:Date:From:Reply-To:Subject:To; b=XRzjslwgdOJTV0kt7uDFyJIH2wyK105cRZqDMVFKCPR75XRJGwiZU+yvSPvjHHqj43a aNY191FL7t80PODim1/0Cjzwewa2O/WjeiPdfXdWn0Y8SIYCDhjaFPQ8fbkClDW3+tIzc Yj4g91XfAJwLwO4Bhl8hsKJlPPFz8CApwq4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Eric Dong Cc: Ray Ni Acked-by: Laszlo Ersek Reviewed-by: Ray Ni --- .../CpuFeaturesInitialize.c | 110 ++++++++++-------- 1 file changed, 63 insertions(+), 47 deletions(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index fb0535edd6..63bc50a55f 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -744,6 +744,58 @@ LibWaitForSemaphore ( ) !=3D Value); } =20 +/** + Read / write CR value. + + @param[in] CrIndex The CR index which need to read/write. + @param[in] Read Read or write. TRUE is read. + @param[in,out] CrValue CR value. + + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. +**/ +UINTN +ReadWriteCr ( + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue + ) +{ + switch (CrIndex) { + case 0: + if (Read) { + *CrValue =3D AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + break; + case 2: + if (Read) { + *CrValue =3D AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + break; + case 3: + if (Read) { + *CrValue =3D AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + break; + case 4: + if (Read) { + *CrValue =3D AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + break; + default: + return EFI_UNSUPPORTED;; + } + + return EFI_SUCCESS; +} + /** Initialize the CPU registers from a register table. =20 @@ -773,6 +825,7 @@ ProgramProcessorRegister ( UINTN ProcessorIndex; UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; + EFI_STATUS Status; =20 // // Traverse Register Table of this logical processor @@ -791,55 +844,18 @@ ProgramProcessorRegister ( // The specified register is Control Register // case ControlRegister: - switch (RegisterTableEntry->Index) { - case 0: - Value =3D AsmReadCr0 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr0 (Value); - break; - case 2: - Value =3D AsmReadCr2 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr2 (Value); - break; - case 3: - Value =3D AsmReadCr3 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr3 (Value); - break; - case 4: - Value =3D AsmReadCr4 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr4 (Value); - break; - case 8: - // - // Do we need to support CR8? - // - break; - default: + Status =3D ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { break; } + + Value =3D (UINTN) BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableE= ntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; // // The specified register is Model Specific Register --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45777): https://edk2.groups.io/g/devel/message/45777 Mute This Topic: https://groups.io/mt/32894961/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 18:06:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45778+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45778+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565927859; cv=none; d=zoho.com; s=zohoarc; b=OxhRiFveR1w5DUxYvRimePDO5ljarxCJb86wXnCmKEaL9ISFgm4SC/pD8fzbdOQKUrqDM5lu/Qn3IGRfYELLDfCUd0RsR46VfL0sz8zZQA4KuT2C7bOcrn2nBSnVMa/wScIKociKgzuUK3ZH6K4dYGRT9ibm0BoRyiCwL6sn4xc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565927859; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=HPM6b3ZpVw8XWHw+yeBSddp56XaA7hpDURQMiL+IL4o=; b=YyGR4MAEemZJgYZJn6qQblqrEoIDS4XI/2AtZwyq8Xw33xgE3EQbissfFQ1GoeRooKJPYZeb567NUOlLnto3JdFC/KqXyz+of6DgIClqWlU1YzfbQHUxNdnkYLInEPY7oC4Qnb0RQL5aCXNFEH0sBp4043zXx+VdX7rxiqu3IVw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45778+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565927859580682.1260123600356; Thu, 15 Aug 2019 20:57:39 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by groups.io with SMTP; Thu, 15 Aug 2019 20:57:38 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 20:57:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="376590705" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga005.fm.intel.com with ESMTP; 15 Aug 2019 20:57:37 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v4 5/6] UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic. Date: Fri, 16 Aug 2019 11:57:29 +0800 Message-Id: <20190816035730.3252-6-eric.dong@intel.com> In-Reply-To: <20190816035730.3252-1-eric.dong@intel.com> References: <20190816035730.3252-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565927859; bh=UlEpEEbVr6QICR7athNaGcJIOnuqg8hUbKxF/SpuBdU=; h=Cc:Date:From:Reply-To:Subject:To; b=fINDhPQMjPiHn7RuRV6fUcalXkYxmgM9t0dzx0ihXOg/d/lYDodH3hJItXzNy7Prf4b fd4S+M06ftLQK+AGEDNKFkrBpRTKNkdGSmQ8yXIvgFZYoz5d01EhajJQaNwklmr/A47mq eWMEHFHQd1UWrEmjhOr4+BlzG9RZDelrwc0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Acked-by: Laszlo Ersek Reviewed-by: Ray Ni --- .../CpuFeaturesInitialize.c | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index 63bc50a55f..0a4fcff033 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -826,6 +826,7 @@ ProgramProcessorRegister ( UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; EFI_STATUS Status; + UINT64 CurrentValue; =20 // // Traverse Register Table of this logical processor @@ -848,7 +849,16 @@ ProgramProcessorRegister ( if (EFI_ERROR (Status)) { break; } - + if (RegisterTableEntry->TestThenWrite) { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + break; + } + } Value =3D (UINTN) BitFieldWrite64 ( Value, RegisterTableEntry->ValidBitStart, @@ -857,10 +867,29 @@ ProgramProcessorRegister ( ); ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; + // // The specified register is Model Specific Register // case Msr: + if (RegisterTableEntry->TestThenWrite) { + Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >=3D 64) { + if (Value =3D=3D RegisterTableEntry->Value) { + break; + } + } else { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + break; + } + } + } + if (RegisterTableEntry->ValidBitLength >=3D 64) { // // If length is not less than 64 bits, then directly write without= reading --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45778): https://edk2.groups.io/g/devel/message/45778 Mute This Topic: https://groups.io/mt/32894962/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu May 2 18:06:20 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45779+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45779+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565927861; cv=none; d=zoho.com; s=zohoarc; b=nmH7hZtZKxojMQzHmw2L5/GucgPCxR/oUbivkbe+KGMQKW1FXJ22Y9lWPJ2tcpSyexM/E6jRtyUyL6Wgwaq0//QkcL8yqTkYj9neWdUv4UZluIoM/qd5/s4C6T1UZlN36sXsqU3JHF5cGKGl9WHHlS0wMtUTBzspgDvVwEstdIw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565927861; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=6wVJs0MFxIsrInDAPLUN/V1TdaZG8lQo9665LvYwBQs=; b=hihdmO8xO+zU9/UBnNOux+JV3a0VD1+AskzlRMdu4CpApl6pe4XRYwM1qPQYYiX93/ytf6WdlC/jhLZN/kperAYKJQNA0bMZHFUCcC7jinu9quZX+bwlVWeTiYnrGSpnMllCzPvcvhkkzS4KsFfu4hyRD5Fvn5M+hjqD53tku54= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45779+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565927861125704.9989463553932; Thu, 15 Aug 2019 20:57:41 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 15 Aug 2019 20:57:39 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Aug 2019 20:57:39 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,391,1559545200"; d="scan'208";a="376590714" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga005.fm.intel.com with ESMTP; 15 Aug 2019 20:57:38 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v4 6/6] UefiCpuPkg/CpuCommonFeaturesLib: Use new macros. Date: Fri, 16 Aug 2019 11:57:30 +0800 Message-Id: <20190816035730.3252-7-eric.dong@intel.com> In-Reply-To: <20190816035730.3252-1-eric.dong@intel.com> References: <20190816035730.3252-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565927860; bh=b/JvNFTNysVzTjCxt/XSB5M83WXa4fJj5mTvabBJ/QQ=; h=Cc:Date:From:Reply-To:Subject:To; b=U0B6M7YFFbgLeYL75UlesoZLnCVfienGNzyFgKGHznUkP818K4VATq28EXvdRbpDH26 JT5pGsRHwb67TagIebXOkgpOIzSSNUmsDF2RkYzfQWerONL+R18T65sTEpmVZa9FgkEv6 eX9B4kxjY3y+wuqcW9jSYvpHqgnPkzmDAl0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Below code is current implementation: if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_FEATURE_CONTROL, MSR_IA32_FEATURE_CONTROL_REGISTER, Bits.Lock, 1 ); } 1. In first normal boot, the Bits.Lock is 0, 1 will be added into the register table and then will set to the MSR. 2. Trig warm reboot, MSR value preserves. After normal boot phase, the Bits.Lock is 1, so it will not be added into the register table during the warm reboot phase. 3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is not added in register table, so it's still 0 after resume. This is not an expect behavior. The expect value is the value should always 1 after booting or resuming from S3. The root cause for this issue is 1. driver bases on current value to insert the "set value action" to the register table. 2. Some MSRs may reserve their value during warm reboot. The solution for this issue is using new added macros for the MSRs which preserve value during warm reboot. Signed-off-by: Eric Dong Cc: Ray Ni Acked-by: Laszlo Ersek Reviewed-by: Ray Ni --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 -- .../CpuCommonFeaturesLib.c | 8 +- .../CpuCommonFeaturesLib/FeatureControl.c | 141 ++++++------------ .../CpuCommonFeaturesLib/MachineCheck.c | 23 ++- 4 files changed, 58 insertions(+), 129 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 25d0174727..b2390e6c39 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -848,21 +848,6 @@ X2ApicInitialize ( IN BOOLEAN State ); =20 -/** - Prepares for the data used by CPU feature detection and initialization. - - @param[in] NumberOfProcessors The number of CPUs in the platform. - - @return Pointer to a buffer of CPU related configuration data. - - @note This service could be called by BSP only. -**/ -VOID * -EFIAPI -FeatureControlGetConfigData ( - IN UINTN NumberOfProcessors - ); - /** Prepares for the data used by CPU feature detection and initialization. =20 diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index fd43b8d662..f0dd3a3b43 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -91,7 +91,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) { Status =3D RegisterCpuFeature ( "Lock Feature Control Register", - FeatureControlGetConfigData, + NULL, LockFeatureControlRegisterSupport, LockFeatureControlRegisterInitialize, CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER, @@ -102,7 +102,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) { Status =3D RegisterCpuFeature ( "SMX", - FeatureControlGetConfigData, + NULL, SmxSupport, SmxInitialize, CPU_FEATURE_SMX, @@ -114,7 +114,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) { Status =3D RegisterCpuFeature ( "VMX", - FeatureControlGetConfigData, + NULL, VmxSupport, VmxInitialize, CPU_FEATURE_VMX, @@ -214,7 +214,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { Status =3D RegisterCpuFeature ( "LMCE", - FeatureControlGetConfigData, + NULL, LmceSupport, LmceInitialize, CPU_FEATURE_LMCE, diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/Uef= iCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c index 3712ef1e5c..6679df8ba4 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c @@ -8,28 +8,6 @@ =20 #include "CpuCommonFeatures.h" =20 -/** - Prepares for the data used by CPU feature detection and initialization. - - @param[in] NumberOfProcessors The number of CPUs in the platform. - - @return Pointer to a buffer of CPU related configuration data. - - @note This service could be called by BSP only. -**/ -VOID * -EFIAPI -FeatureControlGetConfigData ( - IN UINTN NumberOfProcessors - ) -{ - VOID *ConfigData; - - ConfigData =3D AllocateZeroPool (sizeof (MSR_IA32_FEATURE_CONTROL_REGIST= ER) * NumberOfProcessors); - ASSERT (ConfigData !=3D NULL); - return ConfigData; -} - /** Detects if VMX feature supported on current processor. =20 @@ -54,11 +32,6 @@ VmxSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return (CpuInfo->CpuIdVersionInfoEcx.Bits.VMX =3D=3D 1); } =20 @@ -88,8 +61,6 @@ VmxInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of EnableVmxOutsideSmx bit in the MSR_IA32_FEATURE_CONTROL = is core for // below processor type, only program MSR_IA32_FEATURE_CONTROL for threa= d 0 in each @@ -103,18 +74,15 @@ VmxInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.EnableVmxOutsideSmx, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.EnableVmxOutsideSmx, + (State) ? 1 : 0 + ); + return RETURN_SUCCESS; } =20 @@ -142,11 +110,6 @@ LockFeatureControlRegisterSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return TRUE; } =20 @@ -176,8 +139,6 @@ LockFeatureControlRegisterInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for // below processor type, only program MSR_IA32_FEATURE_CONTROL for threa= d 0 in each @@ -191,18 +152,15 @@ LockFeatureControlRegisterInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.Lock, - 1 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.Lock, + 1 + ); + return RETURN_SUCCESS; } =20 @@ -230,11 +188,6 @@ SmxSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return (CpuInfo->CpuIdVersionInfoEcx.Bits.SMX =3D=3D 1); } =20 @@ -265,7 +218,6 @@ SmxInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; RETURN_STATUS Status; =20 // @@ -288,35 +240,32 @@ SmxInitialize ( Status =3D RETURN_UNSUPPORTED; } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.SenterLocalFunctionEnables, - (State) ? 0x7F : 0 - ); - - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.SenterGlobalEnable, - (State) ? 1 : 0 - ); - - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.EnableVmxInsideSmx, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.SenterLocalFunctionEnables, + (State) ? 0x7F : 0 + ); + + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.SenterGlobalEnable, + (State) ? 1 : 0 + ); + + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.EnableVmxInsideSmx, + (State) ? 1 : 0 + ); + return Status; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiC= puPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 2528e0044e..01fd6bb54d 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -319,8 +319,6 @@ LmceInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of LcmeOn bit in the MSR_IA32_MISC_ENABLE is core for below= processor type, only program // MSR_IA32_MISC_ENABLE for thread 0 in each core. @@ -333,17 +331,14 @@ LmceInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.LmceOn, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.LmceOn, + (State) ? 1 : 0 + ); + return RETURN_SUCCESS; } --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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