From nobody Tue May 7 07:17:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45657+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45657+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565837442; cv=none; d=zoho.com; s=zohoarc; b=eNasSke1gdWPiXXkA4YrscRYlaMZ+hohu3jDHpptkRmgizv2tWi0rQrKDO2G1VZ1iLmOGocNC9uE/OdhF5YF8689vDDsIGUktQpVu+Cs5j90tdofcWikd/8EYNYnFYw684/PfYLL9mmmP/Tnl3kpSy5pmuUHU8hzZbacrD7+ZbU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837442; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=ydXMcPknNjav19yqlzbKOjODoduR+BfXryxjDYjKOHY=; b=YdFFziVajRZxSDAOFD2GF8spLGQqE3wI5Lm0UXzsG7SZgeDcCtEDIMYSYjBfQ4lihQQpjvgB91+ZssynXI5g6u4ZujEnoPwAEjUFkg2HW4VfurVB1BI5++KW+sjY9vDGzKcr2qDbJFmOo0jSSRdVZO5mHMX+z0lKERtn4q8+9DM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45657+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837442822609.1539466785711; Wed, 14 Aug 2019 19:50:42 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Wed, 14 Aug 2019 19:50:41 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2019 19:50:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,387,1559545200"; d="scan'208";a="176753289" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga008.fm.intel.com with ESMTP; 14 Aug 2019 19:50:39 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek , Star Zeng Subject: [edk2-devel] [Patch v3 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros. Date: Thu, 15 Aug 2019 10:50:31 +0800 Message-Id: <20190815025036.6780-2-eric.dong@intel.com> In-Reply-To: <20190815025036.6780-1-eric.dong@intel.com> References: <20190815025036.6780-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837441; bh=N/Q29EqptrBBKRJe6k07tLtBPlNjGNr1KGzLIrbFWhg=; h=Cc:Date:From:Reply-To:Subject:To; b=eX4bS903jZBsDWPAorDhqKKkWa3H6CfqNFd9CAFdqmctC7D7FQHePQkLft7opvdMyhV 2aDZyMnVu0ScregoE1rDdCzqZcFfd0fM634h4pT0GhvXz3xOmxOoNNnBFFTn2rPEJnuf8 DyIqa1ZN5nlDqaiR8eeTldi85XA3xXFY/4A= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Add below new micros which test the current value before write the new value. Only write new value when current value not same as new value. CPU_REGISTER_TABLE_TEST_THEN_WRITE32 CPU_REGISTER_TABLE_TEST_THEN_WRITE64 CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD Also add below API: CpuRegisterTableTestThenWrite Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Star Zeng --- UefiCpuPkg/Include/AcpiCpuData.h | 1 + .../Include/Library/RegisterCpuFeaturesLib.h | 91 +++++++++++++++++++ .../RegisterCpuFeaturesLib.c | 45 ++++++++- 3 files changed, 134 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuD= ata.h index b963a2f592..472a1a8070 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -81,6 +81,7 @@ typedef struct { UINT16 Reserved; // offset 10 - 11 UINT32 HighIndex; // offset 12-15, only valid for Me= moryMapped UINT64 Value; // offset 16-23 + UINT8 TestThenWrite; // 0ffset 24 } CPU_REGISTER_TABLE_ENTRY; =20 // diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index e420e7f075..5bd464b32e 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -348,6 +348,32 @@ CpuRegisterTableWrite ( IN UINT64 Value ); =20 +/** + Adds an entry in specified register table. + + This function adds an entry in specified register table, with given regi= ster type, + register index, bit section and value. + + Driver will test the current value before setting new value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] ValueMask Mask of bits in register to write + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +VOID +EFIAPI +CpuRegisterTableTestThenWrite ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value + ); + /** Adds an entry in specified Pre-SMM register table. =20 @@ -390,6 +416,26 @@ PreSmmCpuRegisterTableWrite ( CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT3= 2, Value); \ } while(FALSE); =20 +/** + Adds a 32-bit register write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, and value. + + Driver will test the current value before setting new value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE32(ProcessorNumber, RegisterType= , Index, Value) \ + do { = \ + CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, M= AX_UINT32, Value); \ + } while(FALSE); + /** Adds a 64-bit register write entry in specified register table. =20 @@ -408,6 +454,26 @@ PreSmmCpuRegisterTableWrite ( CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT6= 4, Value); \ } while(FALSE); =20 +/** + Adds a 64-bit register write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, and value. + + Driver will test the current value before setting new value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE64(ProcessorNumber, RegisterType= , Index, Value) \ + do { = \ + CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, M= AX_UINT64, Value); \ + } while(FALSE); + /** Adds a bit field write entry in specified register table. =20 @@ -431,6 +497,31 @@ PreSmmCpuRegisterTableWrite ( CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMas= k, Value); \ } while(FALSE); =20 +/** + Adds a bit field write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, bit field section, and value. + + Driver will test the current value before setting new value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program. + @param[in] Index Index of the register to program. + @param[in] Type The data type name of a register structure. + @param[in] Field The bit fiel name in register structure to = write. + @param[in] Value Value to write to the bit field. + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD(ProcessorNumber, Register= Type, Index, Type, Field, Value) \ + do { = \ + UINT64 ValueMask; = \ + ValueMask =3D MAX_UINT64; = \ + ((Type *)(&ValueMask))->Field =3D 0; = \ + CpuRegisterTableTestThenWrite (ProcessorNumber, RegisterType, Index, ~= ValueMask, Value); \ + } while(FALSE); + /** Adds a 32-bit register write entry in specified register table. =20 diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesL= ib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index 67885bf69b..e9769882b9 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -1025,6 +1025,8 @@ EnlargeRegisterTable ( @param[in] ValidBitStart Start of the bit section @param[in] ValidBitLength Length of the bit section @param[in] Value Value to write + @param[in] TestThenWrite Whether need to test current Value before w= riting. + **/ VOID CpuRegisterTableWriteWorker ( @@ -1034,7 +1036,8 @@ CpuRegisterTableWriteWorker ( IN UINT64 Index, IN UINT8 ValidBitStart, IN UINT8 ValidBitLength, - IN UINT64 Value + IN UINT64 Value, + IN UINT8 TestThenWrite ) { CPU_FEATURES_DATA *CpuFeaturesData; @@ -1070,6 +1073,7 @@ CpuRegisterTableWriteWorker ( RegisterTableEntry[RegisterTable->TableLength].ValidBitStart =3D ValidB= itStart; RegisterTableEntry[RegisterTable->TableLength].ValidBitLength =3D ValidB= itLength; RegisterTableEntry[RegisterTable->TableLength].Value =3D Value; + RegisterTableEntry[RegisterTable->TableLength].TestThenWrite =3D TestTh= enWrite; =20 RegisterTable->TableLength++; } @@ -1105,7 +1109,42 @@ CpuRegisterTableWrite ( Start =3D (UINT8)LowBitSet64 (ValueMask); End =3D (UINT8)HighBitSet64 (ValueMask); Length =3D End - Start + 1; - CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value); + CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value, FALSE); +} + +/** + Adds an entry in specified register table. + + This function adds an entry in specified register table, with given regi= ster type, + register index, bit section and value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] ValueMask Mask of bits in register to write + @param[in] Value Value to write + @param[in] TestThenWrite Whether need to test current Value before w= riting. + + @note This service could be called by BSP only. +**/ +VOID +EFIAPI +CpuRegisterTableTestThenWrite ( + IN UINTN ProcessorNumber, + IN REGISTER_TYPE RegisterType, + IN UINT64 Index, + IN UINT64 ValueMask, + IN UINT64 Value + ) +{ + UINT8 Start; + UINT8 End; + UINT8 Length; + + Start =3D (UINT8)LowBitSet64 (ValueMask); + End =3D (UINT8)HighBitSet64 (ValueMask); + Length =3D End - Start + 1; + CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value, TRUE); } =20 /** @@ -1139,7 +1178,7 @@ PreSmmCpuRegisterTableWrite ( Start =3D (UINT8)LowBitSet64 (ValueMask); End =3D (UINT8)HighBitSet64 (ValueMask); Length =3D End - Start + 1; - CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index,= Start, Length, Value); + CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index,= Start, Length, Value, FALSE); } =20 /** --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45657): https://edk2.groups.io/g/devel/message/45657 Mute This Topic: https://groups.io/mt/32882705/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 07:17:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45658+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45658+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565837444; cv=none; d=zoho.com; s=zohoarc; b=gN2dKcd+Oal/nKbGktOkqvDPeQAZ6tieg3iTqu15Hkg5VRHz5uKTg5WFtd4gzlcyJQC1D+GCqn+IshBl5HqZxNS+KN/Jn8sQQau11KL89l4HWcwTwYw5AGEhlrCiXrhq/yJexgRwIEt7CIQxqBzYVpvitRwIfZFjg1xt7OrodIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837444; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=D8YKdTmFiKtpnNxduOB2/Y/FnL9v1km3Q3EGfr8DCLc=; b=B9wm2sVStw3bCpvNCqr9en/vGjGhYBaNpBbMRdU4JY2nHB++wwPnEX/TsNsWtWHMSGKjg4QLN60zFDVwp/vvh8n58heg3KCNkuHU/27o7m9y6ogSFILxJv1wUzlKwPQrdYdJ/lqGNwctD9xMkbb2BYAB/SHjVfTOD2h5DWOuT70= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45658+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837444226968.6283708915329; Wed, 14 Aug 2019 19:50:44 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Wed, 14 Aug 2019 19:50:42 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2019 19:50:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,387,1559545200"; d="scan'208";a="176753297" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga008.fm.intel.com with ESMTP; 14 Aug 2019 19:50:41 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v3 2/6] UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action. Date: Thu, 15 Aug 2019 10:50:32 +0800 Message-Id: <20190815025036.6780-3-eric.dong@intel.com> In-Reply-To: <20190815025036.6780-1-eric.dong@intel.com> References: <20190815025036.6780-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837442; bh=MbPRD6Wmzzh0C9Y5bHxZcmmnTqZrShG16C8lhfvsiHQ=; h=Cc:Date:From:Reply-To:Subject:To; b=OsLVMVmWgDLTjUydfMxVkJWaVfSMeMuXUuKv63ZSMa0QZLI5fT3HP+2TShMkchAKmrw QW8XGsa9/S+PhcggWjuOaJoM3hqRqkVRAJiqO9f2K+EBnGg1r5ikgtJL9qpIqyclaF5Ki sahe3U0amX4L0stDavqpAafA3Y8e7pSfNjs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Eric Dong Cc: Ray Ni Reviewed-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 104 ++++++++++++++++++------------ 1 file changed, 62 insertions(+), 42 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index d8c6b19ead..627a3b87ac 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -159,6 +159,58 @@ S3WaitForSemaphore ( ) !=3D Value); } =20 +/** + Read / write CR value. + + @param[in] CrIndex The CR index which need to read/write. + @param[in] Read Read or write. TRUE is read. + @param[in,out] CrValue CR value. + + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. +**/ +UINTN +ReadWriteCr ( + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue + ) +{ + switch (CrIndex) { + case 0: + if (Read) { + *CrValue =3D AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + break; + case 2: + if (Read) { + *CrValue =3D AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + break; + case 3: + if (Read) { + *CrValue =3D AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + break; + case 4: + if (Read) { + *CrValue =3D AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + break; + default: + return EFI_UNSUPPORTED;; + } + + return EFI_SUCCESS; +} + /** Initialize the CPU registers from a register table. =20 @@ -188,6 +240,7 @@ ProgramProcessorRegister ( UINTN ProcessorIndex; UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; + EFI_STATUS Status; =20 // // Traverse Register Table of this logical processor @@ -206,50 +259,17 @@ ProgramProcessorRegister ( // The specified register is Control Register // case ControlRegister: - switch (RegisterTableEntry->Index) { - case 0: - Value =3D AsmReadCr0 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr0 (Value); - break; - case 2: - Value =3D AsmReadCr2 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr2 (Value); - break; - case 3: - Value =3D AsmReadCr3 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr3 (Value); - break; - case 4: - Value =3D AsmReadCr4 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr4 (Value); - break; - default: + Status =3D ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { break; } + Value =3D (UINTN) BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableE= ntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; // // The specified register is Model Specific Register --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45658): https://edk2.groups.io/g/devel/message/45658 Mute This Topic: https://groups.io/mt/32882706/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 07:17:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45659+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45659+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565837445; cv=none; d=zoho.com; s=zohoarc; b=UC+18UTBlbCNtCUkWOFNwkskmf8WL3vGKcbPm8PAGY9JLzJsn6dBUU19EP5WVk4mhmcJ2novksyVjsSmywfrX7nMdtqBSx7vsmwiF8yltIqULRViWZ9FaHhOXldj2JXL+bYS82XB4GTB7go0VlEp64VkPK2OuxbQTXgwoVoQ+14= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837445; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=SuyDsurmZtG/zAuFtqZH0xzarb6wQY5if+mLV7OuNeM=; b=Cv/4jf70UPSLeCo1W15inu/r3QOT25TiRt48w6bJyuGes3TrwbHtPuDF86NeA1BBlRuBnp6XxjKskEk3npaaybenYwlQEFOF/69NmphVPj6q4fP05ZNH6dWqBwvjnxcLASg75kdVDs5qWr1DxEmTZFbcQBiQUSLs6kylwFL6XSE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45659+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156583744514861.43154345241419; Wed, 14 Aug 2019 19:50:45 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Wed, 14 Aug 2019 19:50:43 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2019 19:50:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,387,1559545200"; d="scan'208";a="176753309" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga008.fm.intel.com with ESMTP; 14 Aug 2019 19:50:42 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v3 3/6] UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic. Date: Thu, 15 Aug 2019 10:50:33 +0800 Message-Id: <20190815025036.6780-4-eric.dong@intel.com> In-Reply-To: <20190815025036.6780-1-eric.dong@intel.com> References: <20190815025036.6780-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837444; bh=niMQz/KyMpQeqmQQCAYnb7NpdwxbntYwK4Vu3SztyGE=; h=Cc:Date:From:Reply-To:Subject:To; b=rn53SR10yxN/DPA5p4S5OP28u/C8P0NyOVU271lCqTXYX1LFpFdAbr33dYuR46gnm5J +oVRQthYduTmG3WHe69i5P+A1vnQBTQ3wClks10iBFqD3rxkhjmpfqJTeNcYvsB0t1qpH dbicdYHR6pphcUi6cK8/f7V8/PghHczF6Jo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Reviewed-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index 627a3b87ac..ba5cc0194c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -241,6 +241,7 @@ ProgramProcessorRegister ( UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; EFI_STATUS Status; + UINT64 CurrentValue; =20 // // Traverse Register Table of this logical processor @@ -263,6 +264,16 @@ ProgramProcessorRegister ( if (EFI_ERROR (Status)) { break; } + if (RegisterTableEntry->TestThenWrite) { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + break; + } + } Value =3D (UINTN) BitFieldWrite64 ( Value, RegisterTableEntry->ValidBitStart, @@ -275,6 +286,24 @@ ProgramProcessorRegister ( // The specified register is Model Specific Register // case Msr: + if (RegisterTableEntry->TestThenWrite) { + Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >=3D 64) { + if (Value =3D=3D RegisterTableEntry->Value) { + break; + } + } else { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + break; + } + } + } + // // If this function is called to restore register setting after INIT= signal, // there is no need to restore MSRs in register table. --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45659): https://edk2.groups.io/g/devel/message/45659 Mute This Topic: https://groups.io/mt/32882707/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 07:17:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45660+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45660+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565837447; cv=none; d=zoho.com; s=zohoarc; b=Oe8GY1Ff41xX2HuN/qy4Fq1KbL0oRXsnFDOOjzJ4rL4WZCOLdok1SDLKjSsvzcjp+mwZVtcr6gd5OtRtvxejsYyyZcXuawuNX457DLa+Jtyc3+k2sDC1TgKlPEvsUaTPZ+jap8y4x/9GeBFrW/9S8VI2aNAb0i5ScW5fOlLv9LE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837447; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=ODDAvInEOzgGeJgY8wX7z9bXVltqjIWdhAQB/ynF1cE=; b=ab7ONdGh7QD5z6pmh0uC6fQC/GjYjePsBojG9L9BlY6T0wVedIgCmVJHtkM7MGV3IEFa1aHEbFQDdXcLe6+xTPQTkY30ObQxT9dVtHf0YQvll7cG34YZ5aqGM+WhBfgVoI9WqXoF+i+/g+XNhivC8826n9dLrbBv1XRaTGWC+3o= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45660+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837447005549.3756093374982; Wed, 14 Aug 2019 19:50:47 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Wed, 14 Aug 2019 19:50:45 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2019 19:50:45 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,387,1559545200"; d="scan'208";a="176753317" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga008.fm.intel.com with ESMTP; 14 Aug 2019 19:50:43 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v3 4/6] UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action. Date: Thu, 15 Aug 2019 10:50:34 +0800 Message-Id: <20190815025036.6780-5-eric.dong@intel.com> In-Reply-To: <20190815025036.6780-1-eric.dong@intel.com> References: <20190815025036.6780-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837445; bh=CmxKkKKzdDdNylJ/k9l8S3nQabeN5k/nMHQiiEcv8vk=; h=Cc:Date:From:Reply-To:Subject:To; b=D3ZBBitaoW14YWEsC+SVCY9D7+w7KNNBmvVnx9Beo6B1FjK484WuFUyA8Psr8nF9e4V WzonfjN5kZTh2CgtDyCN3Na1f9AnsuuYK9R/rXBP4Fgrlxbk4rnVKN1K/EqA8I+i4S1d1 1QJg6uiQkBUrX50RMkBflK6VxqEUNIOsp60= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Eric Dong Cc: Ray Ni Acked-by: Laszlo Ersek --- .../CpuFeaturesInitialize.c | 110 ++++++++++-------- 1 file changed, 63 insertions(+), 47 deletions(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index fb0535edd6..63bc50a55f 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -744,6 +744,58 @@ LibWaitForSemaphore ( ) !=3D Value); } =20 +/** + Read / write CR value. + + @param[in] CrIndex The CR index which need to read/write. + @param[in] Read Read or write. TRUE is read. + @param[in,out] CrValue CR value. + + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. +**/ +UINTN +ReadWriteCr ( + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue + ) +{ + switch (CrIndex) { + case 0: + if (Read) { + *CrValue =3D AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + break; + case 2: + if (Read) { + *CrValue =3D AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + break; + case 3: + if (Read) { + *CrValue =3D AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + break; + case 4: + if (Read) { + *CrValue =3D AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + break; + default: + return EFI_UNSUPPORTED;; + } + + return EFI_SUCCESS; +} + /** Initialize the CPU registers from a register table. =20 @@ -773,6 +825,7 @@ ProgramProcessorRegister ( UINTN ProcessorIndex; UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; + EFI_STATUS Status; =20 // // Traverse Register Table of this logical processor @@ -791,55 +844,18 @@ ProgramProcessorRegister ( // The specified register is Control Register // case ControlRegister: - switch (RegisterTableEntry->Index) { - case 0: - Value =3D AsmReadCr0 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr0 (Value); - break; - case 2: - Value =3D AsmReadCr2 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr2 (Value); - break; - case 3: - Value =3D AsmReadCr3 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr3 (Value); - break; - case 4: - Value =3D AsmReadCr4 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr4 (Value); - break; - case 8: - // - // Do we need to support CR8? - // - break; - default: + Status =3D ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { break; } + + Value =3D (UINTN) BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableE= ntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; // // The specified register is Model Specific Register --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45660): https://edk2.groups.io/g/devel/message/45660 Mute This Topic: https://groups.io/mt/32882708/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 07:17:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45661+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45661+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565837448; cv=none; d=zoho.com; s=zohoarc; b=TWaXdOlvHo+QPo/hk6yOPX+p2fDG+x/7cFhoOqtlGiR45dhJbPxY8q68r93vWbp5CECWGkbOh3bNJNDtEFk6zC2EiRzq5uxuYy6P1ugltFNe69ELRc+rxPRr9TxEwQny+V7ShUBaSTsnHo0Qt9ErqBh/aWCF2ZSz0f8a2hXebaA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837448; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=Uu8xfTQ+cFoz/kMbIZASm4W1ftMrbWXOVieI2YKGP2E=; b=HoVoXT4AVnCOnjN5aTMRYfeUadzo67D+G1G+i3UFk4NXLtSGv3cUvJldoktiYZGhnkn8b5V4yAT+jS41urpI1SJhfMvkFLMqg32ZtXalEA8iuQVkbMZecMhKsq/R+OTVwTVLGAyyLLKLo98Gl5YUhqdTc0q4gU6LqCVIraU5zK8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45661+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837448321481.4548076656856; Wed, 14 Aug 2019 19:50:48 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Wed, 14 Aug 2019 19:50:46 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2019 19:50:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,387,1559545200"; d="scan'208";a="176753334" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga008.fm.intel.com with ESMTP; 14 Aug 2019 19:50:45 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v3 5/6] UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic. Date: Thu, 15 Aug 2019 10:50:35 +0800 Message-Id: <20190815025036.6780-6-eric.dong@intel.com> In-Reply-To: <20190815025036.6780-1-eric.dong@intel.com> References: <20190815025036.6780-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837447; bh=VMeCvIpAS8r2zH2HJSDm2H/7924GVbTu9xh01DjDBio=; h=Cc:Date:From:Reply-To:Subject:To; b=wrkM4YfH/YjeC3UqY41i+0LShGI1LWgF+Ka8F5AFaRf9Tk/tnllr39XKxXxpavy7IWD 9eVEndpiqQXKitAx4iXEz+fbK/9HVfoMGuzMslXHUC01LpeOq/MXz2fyCHYYFLWROjKQi 6o0yo0klo0l1TdaMfsBVw7bOQdCuKr0CLAk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Acked-by: Laszlo Ersek --- .../CpuFeaturesInitialize.c | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index 63bc50a55f..0a4fcff033 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -826,6 +826,7 @@ ProgramProcessorRegister ( UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; EFI_STATUS Status; + UINT64 CurrentValue; =20 // // Traverse Register Table of this logical processor @@ -848,7 +849,16 @@ ProgramProcessorRegister ( if (EFI_ERROR (Status)) { break; } - + if (RegisterTableEntry->TestThenWrite) { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + break; + } + } Value =3D (UINTN) BitFieldWrite64 ( Value, RegisterTableEntry->ValidBitStart, @@ -857,10 +867,29 @@ ProgramProcessorRegister ( ); ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; + // // The specified register is Model Specific Register // case Msr: + if (RegisterTableEntry->TestThenWrite) { + Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >=3D 64) { + if (Value =3D=3D RegisterTableEntry->Value) { + break; + } + } else { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + break; + } + } + } + if (RegisterTableEntry->ValidBitLength >=3D 64) { // // If length is not less than 64 bits, then directly write without= reading --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45661): https://edk2.groups.io/g/devel/message/45661 Mute This Topic: https://groups.io/mt/32882709/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 07:17:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45662+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45662+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565837449; cv=none; d=zoho.com; s=zohoarc; b=dtkQxUA99uXicFbcB9IaCxcasu5OHTJ1Lgr9wBBxTjaG9U2c+43MnA1mSdFQyMVBurP2kaFtJGVttSYIuwf0JQsQPtiIeYqzjYd/vUjvSMj1L5SCk9qn6ALF9GghOfB/j9mqEM42cOu5bNo+gVv5JkQ4oyNucsXiLjiO27MWMv4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565837449; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=NqZmtiZDNk6tm1OFNJn8jkifLrMpMMp8L+m09LB+COc=; b=i6ITgw2Ohqnm1a8sMwcB5oR5NPBPQAq05ONYn/P/X4A5c13QDCQIJs0NfhUim0pEHE57f1XhaHywq20tyrMaOdaGB55aBL+QNdEMt8Ax8c81S5wakaiSSb0o+T4JpmkFSK9Ugic2Z7cegp+cBXizy49Znf91oBXPzLz01Eo4V8s= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45662+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565837449781554.9690892748685; Wed, 14 Aug 2019 19:50:49 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Wed, 14 Aug 2019 19:50:48 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Aug 2019 19:50:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,387,1559545200"; d="scan'208";a="176753357" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by fmsmga008.fm.intel.com with ESMTP; 14 Aug 2019 19:50:46 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v3 6/6] UefiCpuPkg/CpuCommonFeaturesLib: Use new macros. Date: Thu, 15 Aug 2019 10:50:36 +0800 Message-Id: <20190815025036.6780-7-eric.dong@intel.com> In-Reply-To: <20190815025036.6780-1-eric.dong@intel.com> References: <20190815025036.6780-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565837448; bh=EmVKgnw+68Q7Gwvp+ZKh9fLkEwGFxo0c9jxGwQlh1a4=; h=Cc:Date:From:Reply-To:Subject:To; b=SPpg3Xqur4LYszb+I5M3fvJtZqqbYdjQYe3TO3MZ014Kj2pzmhzXjEM5XxVvo032y66 ApfoDSgbAJB92nn+J8RHFAhSk89feOHMyEnHWFQTQfsX7Tbiw5ag6+5TwRpp9bk+r2D0s 8QfBggqTJZo0xNy8opTRVuHLgjRDj+LZjt8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Below code is current implementation: if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_FEATURE_CONTROL, MSR_IA32_FEATURE_CONTROL_REGISTER, Bits.Lock, 1 ); } 1. In first normal boot, the Bits.Lock is 0, 1 will be added into the register table and then will set to the MSR. 2. Trig warm reboot, MSR value preserves. After normal boot phase, the Bits.Lock is 1, so it will not be added into the register table during the warm reboot phase. 3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is not added in register table, so it's still 0 after resume. This is not an expect behavior. The expect value is the value should always 1 after booting or resuming from S3. The root cause for this issue is 1. driver bases on current value to insert the "set value action" to the register table. 2. Some MSRs may reserve their value during warm reboot. The solution for this issue is using new added macros for the MSRs which preserve value during warm reboot. Signed-off-by: Eric Dong Cc: Ray Ni Acked-by: Laszlo Ersek --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 -- .../CpuCommonFeaturesLib.c | 8 +- .../CpuCommonFeaturesLib/FeatureControl.c | 141 ++++++------------ .../CpuCommonFeaturesLib/MachineCheck.c | 23 ++- 4 files changed, 58 insertions(+), 129 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 25d0174727..b2390e6c39 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -848,21 +848,6 @@ X2ApicInitialize ( IN BOOLEAN State ); =20 -/** - Prepares for the data used by CPU feature detection and initialization. - - @param[in] NumberOfProcessors The number of CPUs in the platform. - - @return Pointer to a buffer of CPU related configuration data. - - @note This service could be called by BSP only. -**/ -VOID * -EFIAPI -FeatureControlGetConfigData ( - IN UINTN NumberOfProcessors - ); - /** Prepares for the data used by CPU feature detection and initialization. =20 diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index fd43b8d662..f0dd3a3b43 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -91,7 +91,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) { Status =3D RegisterCpuFeature ( "Lock Feature Control Register", - FeatureControlGetConfigData, + NULL, LockFeatureControlRegisterSupport, LockFeatureControlRegisterInitialize, CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER, @@ -102,7 +102,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) { Status =3D RegisterCpuFeature ( "SMX", - FeatureControlGetConfigData, + NULL, SmxSupport, SmxInitialize, CPU_FEATURE_SMX, @@ -114,7 +114,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) { Status =3D RegisterCpuFeature ( "VMX", - FeatureControlGetConfigData, + NULL, VmxSupport, VmxInitialize, CPU_FEATURE_VMX, @@ -214,7 +214,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { Status =3D RegisterCpuFeature ( "LMCE", - FeatureControlGetConfigData, + NULL, LmceSupport, LmceInitialize, CPU_FEATURE_LMCE, diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/Uef= iCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c index 3712ef1e5c..6679df8ba4 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c @@ -8,28 +8,6 @@ =20 #include "CpuCommonFeatures.h" =20 -/** - Prepares for the data used by CPU feature detection and initialization. - - @param[in] NumberOfProcessors The number of CPUs in the platform. - - @return Pointer to a buffer of CPU related configuration data. - - @note This service could be called by BSP only. -**/ -VOID * -EFIAPI -FeatureControlGetConfigData ( - IN UINTN NumberOfProcessors - ) -{ - VOID *ConfigData; - - ConfigData =3D AllocateZeroPool (sizeof (MSR_IA32_FEATURE_CONTROL_REGIST= ER) * NumberOfProcessors); - ASSERT (ConfigData !=3D NULL); - return ConfigData; -} - /** Detects if VMX feature supported on current processor. =20 @@ -54,11 +32,6 @@ VmxSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return (CpuInfo->CpuIdVersionInfoEcx.Bits.VMX =3D=3D 1); } =20 @@ -88,8 +61,6 @@ VmxInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of EnableVmxOutsideSmx bit in the MSR_IA32_FEATURE_CONTROL = is core for // below processor type, only program MSR_IA32_FEATURE_CONTROL for threa= d 0 in each @@ -103,18 +74,15 @@ VmxInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.EnableVmxOutsideSmx, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.EnableVmxOutsideSmx, + (State) ? 1 : 0 + ); + return RETURN_SUCCESS; } =20 @@ -142,11 +110,6 @@ LockFeatureControlRegisterSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return TRUE; } =20 @@ -176,8 +139,6 @@ LockFeatureControlRegisterInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for // below processor type, only program MSR_IA32_FEATURE_CONTROL for threa= d 0 in each @@ -191,18 +152,15 @@ LockFeatureControlRegisterInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.Lock, - 1 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.Lock, + 1 + ); + return RETURN_SUCCESS; } =20 @@ -230,11 +188,6 @@ SmxSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return (CpuInfo->CpuIdVersionInfoEcx.Bits.SMX =3D=3D 1); } =20 @@ -265,7 +218,6 @@ SmxInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; RETURN_STATUS Status; =20 // @@ -288,35 +240,32 @@ SmxInitialize ( Status =3D RETURN_UNSUPPORTED; } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.SenterLocalFunctionEnables, - (State) ? 0x7F : 0 - ); - - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.SenterGlobalEnable, - (State) ? 1 : 0 - ); - - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.EnableVmxInsideSmx, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.SenterLocalFunctionEnables, + (State) ? 0x7F : 0 + ); + + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.SenterGlobalEnable, + (State) ? 1 : 0 + ); + + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.EnableVmxInsideSmx, + (State) ? 1 : 0 + ); + return Status; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiC= puPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 2528e0044e..01fd6bb54d 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -319,8 +319,6 @@ LmceInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of LcmeOn bit in the MSR_IA32_MISC_ENABLE is core for below= processor type, only program // MSR_IA32_MISC_ENABLE for thread 0 in each core. @@ -333,17 +331,14 @@ LmceInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.LmceOn, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.LmceOn, + (State) ? 1 : 0 + ); + return RETURN_SUCCESS; } --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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