From nobody Wed Apr 24 07:12:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45425+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45425+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565605917; cv=none; d=zoho.com; s=zohoarc; b=Tf4brpXuoRvfRf5VuQf9Yl0FKZXZbDCeKv7X644YtrB6ERbnhaB7CXjjHhdPJoJ8Nv19OSGioscl4/w3318UeUeyqLM8PrlSU6VYvi9fY8DOPmV8zjkRDqrM81U30iacWThXrlSaozCdGkFcmuM2unx5TcCNgMQIRMxIqS3J6pE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565605917; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=FRd4IUUkrQlEo0JQUJLOqJHWfyv1aKDd/ADe5ztciNA=; b=CJuQ+8IsD6IPopmBcXTsHdTTFl5/5b+lePil25h+Ib5aHhYychnX03oK4KhSv14eFUly9lnqfsELj33WeF/PjnRbAVhIjTntx9WpKMrsoPNO4txFalievR/0IODm88lYHmJlRIPCeYtwXLFq07i420Eg9Vto3x6pWsG2quLPjQo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45425+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156560591708149.116419502031135; Mon, 12 Aug 2019 03:31:57 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Mon, 12 Aug 2019 03:31:56 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Aug 2019 03:31:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,377,1559545200"; d="scan'208";a="169999869" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga008.jf.intel.com with ESMTP; 12 Aug 2019 03:31:54 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v2 1/6] UefiCpuPkg/RegisterCpuFeaturesLib: Add "Test Then Write" Macros. Date: Mon, 12 Aug 2019 18:31:47 +0800 Message-Id: <20190812103152.35164-2-eric.dong@intel.com> In-Reply-To: <20190812103152.35164-1-eric.dong@intel.com> References: <20190812103152.35164-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565605916; bh=hKjJlNMSQ4PCM/l/G8UuadrkBj1uvw8eytrZuyWvAs8=; h=Cc:Date:From:Reply-To:Subject:To; b=GNfxLE/N4DZdf2FwRIKpVV8rFnaPYv4mnUiWCX7Si7qpTNfZNs6I3wZAPAD+JbZeb0R LZXHp/8Lc6LHWT7K5zMUdRlGGTrQGiMPu/lSewSqH42dtXX/g7+nMJLyTTOrZUw9Y6isl 5UF5+MvKNqD+s9m0Qf2/2wQ5DRy9Rp1v6us= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Add below new micros which test the current value before write the new value. Only write new value when current value not same as new value. CPU_REGISTER_TABLE_TEST_THEN_WRITE32 CPU_REGISTER_TABLE_TEST_THEN_WRITE64 CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Acked-by: Laszlo Ersek --- UefiCpuPkg/Include/AcpiCpuData.h | 1 + .../Include/Library/RegisterCpuFeaturesLib.h | 77 +++++++++++++++++-- .../RegisterCpuFeaturesLib.c | 14 +++- 3 files changed, 80 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuD= ata.h index b963a2f592..472a1a8070 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -81,6 +81,7 @@ typedef struct { UINT16 Reserved; // offset 10 - 11 UINT32 HighIndex; // offset 12-15, only valid for Me= moryMapped UINT64 Value; // offset 16-23 + UINT8 TestThenWrite; // 0ffset 24 } CPU_REGISTER_TABLE_ENTRY; =20 // diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index e420e7f075..7e613d883e 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -335,6 +335,7 @@ SwitchBspAfterFeaturesInitialize ( @param[in] Index Index of the register to program @param[in] ValueMask Mask of bits in register to write @param[in] Value Value to write + @param[in] TestThenWrite Whether need to test current Value before w= riting. =20 @note This service could be called by BSP only. **/ @@ -345,7 +346,8 @@ CpuRegisterTableWrite ( IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT64 ValueMask, - IN UINT64 Value + IN UINT64 Value, + IN UINT8 TestThenWrite ); =20 /** @@ -385,9 +387,45 @@ PreSmmCpuRegisterTableWrite ( =20 @note This service could be called by BSP only. **/ -#define CPU_REGISTER_TABLE_WRITE32(ProcessorNumber, RegisterType, Index, V= alue) \ - do { = \ - CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT3= 2, Value); \ +#define CPU_REGISTER_TABLE_WRITE32(ProcessorNumber, RegisterType, Index, V= alue) \ + do { = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT3= 2, Value, FALSE); \ + } while(FALSE); + +/** + Adds a 32-bit register write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, and value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE32(ProcessorNumber, RegisterType= , Index, Value) \ + do { = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT3= 2, Value, TRUE); \ + } while(FALSE); + +/** + Adds a 64-bit register write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, and value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_WRITE64(ProcessorNumber, RegisterType, Index, V= alue) \ + do { = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT6= 4, Value, FALSE); \ } while(FALSE); =20 /** @@ -403,9 +441,9 @@ PreSmmCpuRegisterTableWrite ( =20 @note This service could be called by BSP only. **/ -#define CPU_REGISTER_TABLE_WRITE64(ProcessorNumber, RegisterType, Index, V= alue) \ - do { = \ - CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT6= 4, Value); \ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE64(ProcessorNumber, RegisterType= , Index, Value) \ + do { = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT6= 4, Value, TRUE); \ } while(FALSE); =20 /** @@ -428,7 +466,30 @@ PreSmmCpuRegisterTableWrite ( UINT64 ValueMask; = \ ValueMask =3D MAX_UINT64; = \ ((Type *)(&ValueMask))->Field =3D 0; = \ - CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMas= k, Value); \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMas= k, Value, FALSE); \ + } while(FALSE); + +/** + Adds a bit field write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, bit field section, and value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program. + @param[in] Index Index of the register to program. + @param[in] Type The data type name of a register structure. + @param[in] Field The bit fiel name in register structure to = write. + @param[in] Value Value to write to the bit field. + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD(ProcessorNumber, Register= Type, Index, Type, Field, Value) \ + do { = \ + UINT64 ValueMask; = \ + ValueMask =3D MAX_UINT64; = \ + ((Type *)(&ValueMask))->Field =3D 0; = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMas= k, Value, TRUE); \ } while(FALSE); =20 /** diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesL= ib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index 67885bf69b..5d65b897ee 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -1025,6 +1025,8 @@ EnlargeRegisterTable ( @param[in] ValidBitStart Start of the bit section @param[in] ValidBitLength Length of the bit section @param[in] Value Value to write + @param[in] TestThenWrite Whether need to test current Value before w= riting. + **/ VOID CpuRegisterTableWriteWorker ( @@ -1034,7 +1036,8 @@ CpuRegisterTableWriteWorker ( IN UINT64 Index, IN UINT8 ValidBitStart, IN UINT8 ValidBitLength, - IN UINT64 Value + IN UINT64 Value, + IN UINT8 TestThenWrite ) { CPU_FEATURES_DATA *CpuFeaturesData; @@ -1070,6 +1073,7 @@ CpuRegisterTableWriteWorker ( RegisterTableEntry[RegisterTable->TableLength].ValidBitStart =3D ValidB= itStart; RegisterTableEntry[RegisterTable->TableLength].ValidBitLength =3D ValidB= itLength; RegisterTableEntry[RegisterTable->TableLength].Value =3D Value; + RegisterTableEntry[RegisterTable->TableLength].TestThenWrite =3D TestTh= enWrite; =20 RegisterTable->TableLength++; } @@ -1085,6 +1089,7 @@ CpuRegisterTableWriteWorker ( @param[in] Index Index of the register to program @param[in] ValueMask Mask of bits in register to write @param[in] Value Value to write + @param[in] TestThenWrite Whether need to test current Value before w= riting. =20 @note This service could be called by BSP only. **/ @@ -1095,7 +1100,8 @@ CpuRegisterTableWrite ( IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT64 ValueMask, - IN UINT64 Value + IN UINT64 Value, + IN UINT8 TestThenWrite ) { UINT8 Start; @@ -1105,7 +1111,7 @@ CpuRegisterTableWrite ( Start =3D (UINT8)LowBitSet64 (ValueMask); End =3D (UINT8)HighBitSet64 (ValueMask); Length =3D End - Start + 1; - CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value); + CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value, TestThenWrite); } =20 /** @@ -1139,7 +1145,7 @@ PreSmmCpuRegisterTableWrite ( Start =3D (UINT8)LowBitSet64 (ValueMask); End =3D (UINT8)HighBitSet64 (ValueMask); Length =3D End - Start + 1; - CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index,= Start, Length, Value); + CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index,= Start, Length, Value, FALSE); } =20 /** --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45425): https://edk2.groups.io/g/devel/message/45425 Mute This Topic: https://groups.io/mt/32839205/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed Apr 24 07:12:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45426+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45426+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565605918; cv=none; d=zoho.com; s=zohoarc; b=JM+IGeO7ARBCnftdRLUm/l3x7TABNSMdWU+cG+pyOJpq1cgH81yTKsow6JNh0PEhNNsE8Qqn6YjZ09I7YWNb3GNQ5US9LYjkHXAG+qKgjhv6dPjYGgv+oYj5du7Vd5ma2aYkW5jBfg7jmGMP/TUecT/YxcNucTTvsx0AMjJXME0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565605918; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=qSfNU8FRgcr6VxW6Uc2iY1KQe83r7D4xzD2q0+yIfkg=; b=Vus/8wb4flGNVaVvwNadhcKhsTwLLAjRLYT3FtUI3g80neOsuOJKBZRrfiYNPm/i7Mu7keZG4qjQseAS/+VvIS9CQb2JRSvzTIOXQcA8MPZBEyNFHwr9zbbWPRfvwU3XoiDxbxH0I8WeZdNNyhg5V9rfQdMHeMVIViy4BSMQX3Q= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45426+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565605918270156.46350801864423; Mon, 12 Aug 2019 03:31:58 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Mon, 12 Aug 2019 03:31:57 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Aug 2019 03:31:57 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,377,1559545200"; d="scan'208";a="169999885" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga008.jf.intel.com with ESMTP; 12 Aug 2019 03:31:56 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v2 2/6] UefiCpuPkg/PiSmmCpuDxeSmm: Combine CR read/write action in one function. Date: Mon, 12 Aug 2019 18:31:48 +0800 Message-Id: <20190812103152.35164-3-eric.dong@intel.com> In-Reply-To: <20190812103152.35164-1-eric.dong@intel.com> References: <20190812103152.35164-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565605917; bh=520tRMheZyP9NXETknwwQVQsD8LhiaTQ3wVAEOcxbPU=; h=Cc:Date:From:Reply-To:Subject:To; b=Lj/bg89/6ZyPDTTcJnrD08Vm0W0EXVaSGUfSQRqzff2adwHNKNuXnj0Kda80zYOnfoi kV0EVwpqW8mklOjQ63uWUNlvf2vwav43lGR+W2RSB8Io5t9FzKr9MYWHLaah4wjuF3xS9 8i8SB4vjJl3iLManwnHOWLB2zP1V74wxPeg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 106 ++++++++++++++++++------------ 1 file changed, 63 insertions(+), 43 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index d8c6b19ead..b20992d5ab 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -159,6 +159,58 @@ S3WaitForSemaphore ( ) !=3D Value); } =20 +/** + Read / write CR value. + + @param[in] CrIndex The CR index which need to read/write. + @param[in] Read Read or write. TRUE is read. + @param[in,out] CrValue CR value. + + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. +**/ +UINTN +ReadWriteCr ( + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue + ) +{ + switch (CrIndex) { + case 0: + if (Read) { + *CrValue =3D AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + break; + case 2: + if (Read) { + *CrValue =3D AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + break; + case 3: + if (Read) { + *CrValue =3D AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + break; + case 4: + if (Read) { + *CrValue =3D AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + break; + default: + return EFI_UNSUPPORTED;; + } + + return EFI_SUCCESS; +} + /** Initialize the CPU registers from a register table. =20 @@ -188,6 +240,7 @@ ProgramProcessorRegister ( UINTN ProcessorIndex; UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; + EFI_STATUS Status; =20 // // Traverse Register Table of this logical processor @@ -206,50 +259,17 @@ ProgramProcessorRegister ( // The specified register is Control Register // case ControlRegister: - switch (RegisterTableEntry->Index) { - case 0: - Value =3D AsmReadCr0 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr0 (Value); - break; - case 2: - Value =3D AsmReadCr2 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr2 (Value); - break; - case 3: - Value =3D AsmReadCr3 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr3 (Value); - break; - case 4: - Value =3D AsmReadCr4 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr4 (Value); - break; - default: - break; + Status =3D ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { + continue; } + Value =3D (UINTN) BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableE= ntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; // // The specified register is Model Specific Register --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45426): https://edk2.groups.io/g/devel/message/45426 Mute This Topic: https://groups.io/mt/32839206/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed Apr 24 07:12:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45427+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45427+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565605919; cv=none; d=zoho.com; s=zohoarc; b=S/smGQWSgSZzAKG/jQ9bkJLosAlPaOx7+zMVbrO36qYEZU433VLVjFmzn94QVsyezG7+46VzV0Vlp2wOqW4wrpe+Qrzw84dRPxIMuL3em/9fxP077+nzBxi6WnNpOoGmLQZoOxxJVc94Wiqd/0qgDr1jWsHuxfP9UmeYsLIVCsk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565605919; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=AITRTAVNfYOB/LCwTCl304byz/gDVr2+V/266ilLihQ=; b=OxdSSiUPkqX0sOTh9isU0DvdDIxnzP6hHpTBo5gHyah6ZdDA1KhqudCdjR7CKacyrwGk5NGaFJfUuQ/4C4cCoTRL4oT5d4Fzni7LEWavGFa0SaMcg/We87/7diCLQvtehuCm980FLXtKFFTF0H19AjFpLpqXTqaONJh0dHG2iwA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45427+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565605919488878.6166132932891; Mon, 12 Aug 2019 03:31:59 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Mon, 12 Aug 2019 03:31:58 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Aug 2019 03:31:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,377,1559545200"; d="scan'208";a="169999891" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga008.jf.intel.com with ESMTP; 12 Aug 2019 03:31:57 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v2 3/6] UefiCpuPkg/PiSmmCpuDxeSmm: Supports test then write new value logic. Date: Mon, 12 Aug 2019 18:31:49 +0800 Message-Id: <20190812103152.35164-4-eric.dong@intel.com> In-Reply-To: <20190812103152.35164-1-eric.dong@intel.com> References: <20190812103152.35164-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565605919; bh=/bWXacC9PGrhq2B9iu8FFU7gHFIqvPiXIGihboPTqCE=; h=Cc:Date:From:Reply-To:Subject:To; b=nIwpQ7NXIe570tzHRc4BONjBIHpCG4q4pmiRKJBYmcReaS1cukMXCqoiNgYD/++cQsW Wjxc+SXTo9uR3sAXCyryy3nuAtAmIKavReBH+ay+zdiJx3L2KSRTk7nfJpHGZRgguw1O6 3kPrLd03i/CXRX3qoWMszlWXfnyf9d9Ia+s= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index b20992d5ab..61541838e8 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -241,6 +241,7 @@ ProgramProcessorRegister ( UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; EFI_STATUS Status; + UINT64 CurrentValue; =20 // // Traverse Register Table of this logical processor @@ -263,6 +264,16 @@ ProgramProcessorRegister ( if (EFI_ERROR (Status)) { continue; } + if (RegisterTableEntry->TestThenWrite) { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + continue; + } + } Value =3D (UINTN) BitFieldWrite64 ( Value, RegisterTableEntry->ValidBitStart, @@ -275,6 +286,24 @@ ProgramProcessorRegister ( // The specified register is Model Specific Register // case Msr: + if (RegisterTableEntry->TestThenWrite) { + Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >=3D 64) { + if (Value =3D=3D RegisterTableEntry->Value) { + continue; + } + } else { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + continue; + } + } + } + // // If this function is called to restore register setting after INIT= signal, // there is no need to restore MSRs in register table. --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45427): https://edk2.groups.io/g/devel/message/45427 Mute This Topic: https://groups.io/mt/32839207/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed Apr 24 07:12:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45428+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45428+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565605920; cv=none; d=zoho.com; s=zohoarc; b=OG2VsUns/uV+Af3dIqftBKDB5Idyawx+1FYi/85d5VmuAdNX+rkKYdy59PCgcBktktDhGmvTSsIbKO4kgco/DTb6sbZmSqfkhcPXsfqOYrHOl1B5bzvoq+XCqnCYgEnBAqP7Xc/BrdqDm4OhiS5soAJfUY0xyDpS0YGbSZrR2d4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565605920; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=IGZJ4ZLQmdEDb42Pw2kLUR9plsCR/wW+pElHOE8FumM=; b=eTZKtOP/ZFqtZZUbA/SFSd4AnizdtDlSzkuuRuVmQ+lXZhNg/9BgfzFrh55q4Sibr9caoBS21IWdRx2JIJoprpNgpe0jB1kD/O3MZZ26awbS/GDWHBKKpV4M0Due9ehEuHClUUVc0em2RWFobBx+OT+rG4nUT1UsHUa7KPtfpRU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45428+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156560592032741.255565622448444; Mon, 12 Aug 2019 03:32:00 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Mon, 12 Aug 2019 03:31:59 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Aug 2019 03:31:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,377,1559545200"; d="scan'208";a="169999903" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga008.jf.intel.com with ESMTP; 12 Aug 2019 03:31:58 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v2 4/6] UefiCpuPkg/RegisterCpuFeaturesLib: Combine CR read/write action in one function. Date: Mon, 12 Aug 2019 18:31:50 +0800 Message-Id: <20190812103152.35164-5-eric.dong@intel.com> In-Reply-To: <20190812103152.35164-1-eric.dong@intel.com> References: <20190812103152.35164-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565605919; bh=ZkGn21J7nCt79FoBUokaQEmHxa9dtMbIqnmTzHpETws=; h=Cc:Date:From:Reply-To:Subject:To; b=weE68uGr2GV0rMW5Y/ASD3EHvohUk3+/r2aF65YAR+rEKoCxuA5LyRP1+lK2HZJF1UY PlU9YOR1ZGazTZ8FUbSxs1rp6IrJtCFLDbmKQGmA6BwxhTVCK0zJyzPpxXC+SE8+vHg2T bJPRIAHEZ0u8MoXFh3e5TDyrg2hdS5oL0Ys= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Acked-by: Laszlo Ersek --- .../CpuFeaturesInitialize.c | 112 ++++++++++-------- 1 file changed, 64 insertions(+), 48 deletions(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index fb0535edd6..ef7452e2b8 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -744,6 +744,58 @@ LibWaitForSemaphore ( ) !=3D Value); } =20 +/** + Read / write CR value. + + @param[in] CrIndex The CR index which need to read/write. + @param[in] Read Read or write. TRUE is read. + @param[in,out] CrValue CR value. + + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. +**/ +UINTN +ReadWriteCr ( + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue + ) +{ + switch (CrIndex) { + case 0: + if (Read) { + *CrValue =3D AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + break; + case 2: + if (Read) { + *CrValue =3D AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + break; + case 3: + if (Read) { + *CrValue =3D AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + break; + case 4: + if (Read) { + *CrValue =3D AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + break; + default: + return EFI_UNSUPPORTED;; + } + + return EFI_SUCCESS; +} + /** Initialize the CPU registers from a register table. =20 @@ -773,6 +825,7 @@ ProgramProcessorRegister ( UINTN ProcessorIndex; UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; + EFI_STATUS Status; =20 // // Traverse Register Table of this logical processor @@ -791,55 +844,18 @@ ProgramProcessorRegister ( // The specified register is Control Register // case ControlRegister: - switch (RegisterTableEntry->Index) { - case 0: - Value =3D AsmReadCr0 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr0 (Value); - break; - case 2: - Value =3D AsmReadCr2 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr2 (Value); - break; - case 3: - Value =3D AsmReadCr3 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr3 (Value); - break; - case 4: - Value =3D AsmReadCr4 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr4 (Value); - break; - case 8: - // - // Do we need to support CR8? - // - break; - default: - break; + Status =3D ReadWriteCr (RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { + continue; } + + Value =3D (UINTN) BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableE= ntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; // // The specified register is Model Specific Register --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45428): https://edk2.groups.io/g/devel/message/45428 Mute This Topic: https://groups.io/mt/32839208/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed Apr 24 07:12:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45429+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45429+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565605921; cv=none; d=zoho.com; s=zohoarc; b=BtoKOJzhuHvd51h5eYRnkuVhqMuKVC0UkNRD3DTCTmsb/xJjvVmyIbDUO//wPODNdPa3S4bdOjV0W+hy3frWRcxg0HhybYO1Pn+ug0lj0eZpGp6NKFTVukhFWfEWSyGKDMB8MQydVmCC1SqHsdk7Ee2AKTjj9SzH+/zcHRl1QWM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565605921; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=wXMf3xG1kp05RsXJnEfyvUPJrcX3RqiZlvksYX2hk64=; b=UjKOaFX/rwKV/WY/V5un1dBZ1472c9TMMH4m+9Tg0+s9zHlnQj9yH4ttCI84mnXeAwarlBA1r6nhNElBKOv3Wihe82FqVC7y9XF6/8ilWj7B5aALjt1nLFh9HMcmicB4MrXxk7Hzk1x6ZsbSDJxWw70Z99Y7cSjb3ZjSqpPHkgw= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45429+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565605921439704.921172844831; Mon, 12 Aug 2019 03:32:01 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Mon, 12 Aug 2019 03:32:00 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Aug 2019 03:32:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,377,1559545200"; d="scan'208";a="169999911" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga008.jf.intel.com with ESMTP; 12 Aug 2019 03:31:59 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v2 5/6] UefiCpuPkg/RegisterCpuFeaturesLib: Supports test then write new value logic. Date: Mon, 12 Aug 2019 18:31:51 +0800 Message-Id: <20190812103152.35164-6-eric.dong@intel.com> In-Reply-To: <20190812103152.35164-1-eric.dong@intel.com> References: <20190812103152.35164-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565605921; bh=lX3nIRJscoK1J9Zd9FY28gZ7dMRJlulpKbMzELiYi04=; h=Cc:Date:From:Reply-To:Subject:To; b=gnSUY/phbGsCfKElvbtlwCmQaP0mSMpVLRXRgOm3JMNDfpQosUg62DvyE62P8Tjnhrq EZ94rQ6z6HTOt2pNzRGtk3tALzWbb7BTKzT4IOKorCiNrOq8b7aytJph28JYSh4GhbHGP HzF2po1QwpwTipgPifWKDqZ1HCoSMPhU2Lo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Supports new logic which test current value before write new value. Only write new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Acked-by: Laszlo Ersek --- .../CpuFeaturesInitialize.c | 31 ++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index ef7452e2b8..6988a75bfe 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -826,6 +826,7 @@ ProgramProcessorRegister ( UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; EFI_STATUS Status; + UINT64 CurrentValue; =20 // // Traverse Register Table of this logical processor @@ -848,7 +849,16 @@ ProgramProcessorRegister ( if (EFI_ERROR (Status)) { continue; } - + if (RegisterTableEntry->TestThenWrite) { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + continue; + } + } Value =3D (UINTN) BitFieldWrite64 ( Value, RegisterTableEntry->ValidBitStart, @@ -857,10 +867,29 @@ ProgramProcessorRegister ( ); ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; + // // The specified register is Model Specific Register // case Msr: + if (RegisterTableEntry->TestThenWrite) { + Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >=3D 64) { + if (Value =3D=3D RegisterTableEntry->Value) { + continue; + } + } else { + CurrentValue =3D BitFieldRead64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + continue; + } + } + } + if (RegisterTableEntry->ValidBitLength >=3D 64) { // // If length is not less than 64 bits, then directly write without= reading --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45429): https://edk2.groups.io/g/devel/message/45429 Mute This Topic: https://groups.io/mt/32839209/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed Apr 24 07:12:55 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45430+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45430+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565605922; cv=none; d=zoho.com; s=zohoarc; b=T9P+t/30WbbENLK0fTEI656wJoylzzmjiPMNeUJjDK34vtXVRE1PdokqBrbtvuUb1wnMm/QnjQ0VI8Y7EIzeQunf+RcZjLsIj7UmjH4wMs0zlw46yCM54z/F66rSZ9QhNPOJOs/m07Nb5HHsrQyhbOgiZnL/wW7UGbfWjxypnaI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565605922; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=RSO9yZc7l2OnOttYC78n2edTkBwo6LACvArqdapz5vg=; b=nPbSju+BCJ17Aurc6A+K77fNzF7Ex7p3adc3bGPZYDia/YSkAPB7HINW2RHU4ZYELCc6w9x+DxNPO79nJU57M4vphtdnoYpQeH65E5Zy7PHWFkKsL7pJ4jQq7sLqX5gvnM4c04pWoJAYxaT7MHV1M/1HwbppOCvVEeLi+Ejz2j8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45430+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565605922852435.28416298705133; Mon, 12 Aug 2019 03:32:02 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Mon, 12 Aug 2019 03:32:02 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Aug 2019 03:32:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,377,1559545200"; d="scan'208";a="169999924" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga008.jf.intel.com with ESMTP; 12 Aug 2019 03:32:00 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch v2 6/6] UefiCpuPkg/CpuCommonFeaturesLib: Use new macros. Date: Mon, 12 Aug 2019 18:31:52 +0800 Message-Id: <20190812103152.35164-7-eric.dong@intel.com> In-Reply-To: <20190812103152.35164-1-eric.dong@intel.com> References: <20190812103152.35164-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565605922; bh=AOjlyiOSZqT2UkR5QWnYrkkBjqjO4krxANshK9VnYhc=; h=Cc:Date:From:Reply-To:Subject:To; b=Y1D62XdI8xORcK4+f0RSDrsiUxOncvQYnNkoVWyY5yA/UXdxFgRSIsQR3Xs3Kewaj/z W1utpMYzHFRGnh7835MzB5Z+EI0FQCXq6oa+c0CEM4wiUVXnr5Qhx5ZhPZtBRJx9dSHez RkPk33mVFdXnWdAOjf6wCDQksrqkhz/SANI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Below code is current implementation: if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_FEATURE_CONTROL, MSR_IA32_FEATURE_CONTROL_REGISTER, Bits.Lock, 1 ); } 1. In first normal boot, the Bits.Lock is 0, 1 will be added into the register table and then will set to the MSR. 2. Trig warm reboot, MSR value preserves. After normal boot phase, the Bits.Lock is 1, so it will not be added into the register table during the warm reboot phase. 3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is not added in register table, so it's still 0 after resume. This is not an expect behavior. The expect value is the value should always 1 after booting or resuming from S3. The root cause for this issue is 1. driver bases on current value to insert the "set value action" to the register table. 2. Some MSRs may reserve their value during warm reboot. The solution for this issue is using new added macros for the MSRs which preserve value during warm reboot. Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Acked-by: Laszlo Ersek --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 -- .../CpuCommonFeaturesLib.c | 8 +- .../CpuCommonFeaturesLib/FeatureControl.c | 141 ++++++------------ .../CpuCommonFeaturesLib/MachineCheck.c | 23 ++- 4 files changed, 58 insertions(+), 129 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 25d0174727..b2390e6c39 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -848,21 +848,6 @@ X2ApicInitialize ( IN BOOLEAN State ); =20 -/** - Prepares for the data used by CPU feature detection and initialization. - - @param[in] NumberOfProcessors The number of CPUs in the platform. - - @return Pointer to a buffer of CPU related configuration data. - - @note This service could be called by BSP only. -**/ -VOID * -EFIAPI -FeatureControlGetConfigData ( - IN UINTN NumberOfProcessors - ); - /** Prepares for the data used by CPU feature detection and initialization. =20 diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index fd43b8d662..f0dd3a3b43 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -91,7 +91,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) { Status =3D RegisterCpuFeature ( "Lock Feature Control Register", - FeatureControlGetConfigData, + NULL, LockFeatureControlRegisterSupport, LockFeatureControlRegisterInitialize, CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER, @@ -102,7 +102,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) { Status =3D RegisterCpuFeature ( "SMX", - FeatureControlGetConfigData, + NULL, SmxSupport, SmxInitialize, CPU_FEATURE_SMX, @@ -114,7 +114,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) { Status =3D RegisterCpuFeature ( "VMX", - FeatureControlGetConfigData, + NULL, VmxSupport, VmxInitialize, CPU_FEATURE_VMX, @@ -214,7 +214,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { Status =3D RegisterCpuFeature ( "LMCE", - FeatureControlGetConfigData, + NULL, LmceSupport, LmceInitialize, CPU_FEATURE_LMCE, diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/Uef= iCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c index 3712ef1e5c..6679df8ba4 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c @@ -8,28 +8,6 @@ =20 #include "CpuCommonFeatures.h" =20 -/** - Prepares for the data used by CPU feature detection and initialization. - - @param[in] NumberOfProcessors The number of CPUs in the platform. - - @return Pointer to a buffer of CPU related configuration data. - - @note This service could be called by BSP only. -**/ -VOID * -EFIAPI -FeatureControlGetConfigData ( - IN UINTN NumberOfProcessors - ) -{ - VOID *ConfigData; - - ConfigData =3D AllocateZeroPool (sizeof (MSR_IA32_FEATURE_CONTROL_REGIST= ER) * NumberOfProcessors); - ASSERT (ConfigData !=3D NULL); - return ConfigData; -} - /** Detects if VMX feature supported on current processor. =20 @@ -54,11 +32,6 @@ VmxSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return (CpuInfo->CpuIdVersionInfoEcx.Bits.VMX =3D=3D 1); } =20 @@ -88,8 +61,6 @@ VmxInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of EnableVmxOutsideSmx bit in the MSR_IA32_FEATURE_CONTROL = is core for // below processor type, only program MSR_IA32_FEATURE_CONTROL for threa= d 0 in each @@ -103,18 +74,15 @@ VmxInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.EnableVmxOutsideSmx, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.EnableVmxOutsideSmx, + (State) ? 1 : 0 + ); + return RETURN_SUCCESS; } =20 @@ -142,11 +110,6 @@ LockFeatureControlRegisterSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return TRUE; } =20 @@ -176,8 +139,6 @@ LockFeatureControlRegisterInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for // below processor type, only program MSR_IA32_FEATURE_CONTROL for threa= d 0 in each @@ -191,18 +152,15 @@ LockFeatureControlRegisterInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.Lock, - 1 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.Lock, + 1 + ); + return RETURN_SUCCESS; } =20 @@ -230,11 +188,6 @@ SmxSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return (CpuInfo->CpuIdVersionInfoEcx.Bits.SMX =3D=3D 1); } =20 @@ -265,7 +218,6 @@ SmxInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; RETURN_STATUS Status; =20 // @@ -288,35 +240,32 @@ SmxInitialize ( Status =3D RETURN_UNSUPPORTED; } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.SenterLocalFunctionEnables, - (State) ? 0x7F : 0 - ); - - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.SenterGlobalEnable, - (State) ? 1 : 0 - ); - - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.EnableVmxInsideSmx, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.SenterLocalFunctionEnables, + (State) ? 0x7F : 0 + ); + + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.SenterGlobalEnable, + (State) ? 1 : 0 + ); + + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.EnableVmxInsideSmx, + (State) ? 1 : 0 + ); + return Status; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiC= puPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 2528e0044e..01fd6bb54d 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -319,8 +319,6 @@ LmceInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of LcmeOn bit in the MSR_IA32_MISC_ENABLE is core for below= processor type, only program // MSR_IA32_MISC_ENABLE for thread 0 in each core. @@ -333,17 +331,14 @@ LmceInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.LmceOn, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.LmceOn, + (State) ? 1 : 0 + ); + return RETURN_SUCCESS; } --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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