From nobody Fri Mar 29 07:26:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45444+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45444+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565620979; cv=none; d=zoho.com; s=zohoarc; b=KBpmPaxg/0M8zRxRnMKyQXv1oVWE5pzkk6EAFkqwvYPTCv5CQSzGB7NdSFyXOWlk5GMv/SWJQt3chS3SmueVz28Hn6cdROhogXURAZ2vE2yEGeREoOsKXW+dlm4CGRK17siLDPYy+FFP9rWiPseyrbtpMUMQK0jfnbqASrGhyqw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565620979; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=KQvGlxlFjBh9NcrQfWof3SzTXIPhbEq5wvHEfaAh9oA=; b=gut3sleM0MuQiro4MrpYA7lJJ9+HhMPpyD4AOengWPQAfbRW1s3WOaeN6y7Jn8xvjj7c872Mkg98n8sjJjIyPi0t9si5s4XdQeS5IFNeKKZpG/gUXoCSu4XZT1GM4eOyIN0L4H9+V6m4dDh06gzeMXTedKrq+x/uLM13n+dp4OU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45444+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565620979584793.9058389217988; Mon, 12 Aug 2019 07:42:59 -0700 (PDT) Return-Path: X-Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by groups.io with SMTP; Sun, 11 Aug 2019 21:48:29 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Aug 2019 21:48:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,376,1559545200"; d="scan'208";a="187309652" X-Received: from iwenevel-dev01.amr.corp.intel.com ([10.9.70.66]) by orsmga002.jf.intel.com with ESMTP; 11 Aug 2019 21:48:28 -0700 From: Evelyn Wang To: devel@edk2.groups.io Cc: Jenny Huang , More Shih , Ray Ni , Rangasai V Chaganty Subject: [edk2-devel] [PATCH v2] IntelSiliconPkg-Vtd: A new PMR interface Date: Sun, 11 Aug 2019 21:48:19 -0700 Message-Id: <20190812044819.12280-1-iwen.evelyn.wang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,iwen.evelyn.wang@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565620979; bh=VpHOfH3Wnn6EcoFo/KJ5wTca7L47qUNqgxMnazPaENM=; h=Cc:Date:From:Reply-To:Subject:To; b=F4EkLGHRcVeOiWTdH24wWJFKmFF4loE/wFvP0+mMSI5HTB/3A44YWeJLttIsxa5fVUz YtuEMJiby/GgCzJ7CxqyJQGOnnQNt80v9EvMngmG7EelKV/Uy8y6b/GjZfuCd6zpKk81x z6t7I59XnUV5NFqzW/F5xna9gagcxl6XEsk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1770 1) IOMMU PMR feature should be generic to support different hardware architecture. Platforms may request no overlap between PMR regions and system reserve memory. Create an interface to control PLMR/PHMR regions. It allows silicon code to adjust PLMR/PHMR region base on the project needs. 2) DisableDMAr Function Code Optimization Optimize the flow to follow the VT-d spec requirements. 3) Renamed InitDmar() to InitGlobalVtd() The oringal function name is misleading 4) A new GetVtdPmrAlignmentLib for silicon code to get PMR alignment values. Signed-off-by: Evelyn Wang Cc: Jenny Huang Cc: More Shih Cc: Ray Ni Cc: Rangasai V Chaganty --- In V2: 1) Fixed the EFIAPI is missing in library API issue 2) Logs will be provided to make sure the backwards compatibility 3) Replaced BIT0 with EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL 4) Renamed GetVtdPmrAlignmentLib to PeiGetVtdPmrAlignmentLib 5) Fixed the indent in IntelVTdPmrPei.c 6) Follow VTd spec to define the data type of the SYSTEM_MEM_INFO_HOB Applied few changes coordinately --- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c = | 30 +++++++++++++++++++++++++++--- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c = | 4 ++-- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c = | 72 +++++++++++++++++++++++++++++++++++++++++++++++++= ----------------------- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c = | 29 ++++++++++++++++++++++++++--- Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Platfor= mVTdInfoSamplePei.c | 9 +++++---- Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPm= rAlignmentLib.c | 166 +++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.in= f | 5 ++++- Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLib.h = | 31 +++++++++++++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h = | 25 +++++++++++++++++++++++++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec = | 11 +++++++++-- Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc = | 3 ++- Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGetVtdPm= rAlignmentLib.inf | 32 ++++++++++++++++++++++++++++++++ 12 files changed, 378 insertions(+), 39 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 22bf821d2b..699639ba88 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -309,6 +309,8 @@ DisableDmar ( UINTN Index; UINTN SubIndex; UINT32 Reg32; + UINT32 Status; + UINT32 Command; =20 for (Index =3D 0; Index < mVtdUnitNumber; Index++) { DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index)); @@ -319,9 +321,31 @@ DisableDmar ( FlushWriteBuffer (Index); =20 // - // Disable VTd + // Disable Dmar // - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, B_GMCD_REG_SRTP); + // + // Set TE (Translation Enable: BIT31) of Global command register to ze= ro + // + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & ~B_GMCD_REG_TE); + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); + + // + // Poll on TE Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + + // + // Set SRTP (Set Root Table Pointer: BIT30) of Global command register= in order to update the root table pointerDisable VTd + // + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | B_GMCD_REG_SRTP); + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); + do { Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmr.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVT= dPmr.c index 37283f0fab..9103e53922 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -294,7 +294,7 @@ SetDmaProtectedRange ( UINTN Index; EFI_STATUS Status; =20 - DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] [0x%lx, = 0x%lx]\n", EngineMask, LowMemoryBase, LowMemoryLength, HighMemoryBase, High= MemoryLength)); + DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] [0x%016l= x, 0x%016lx]\n", EngineMask, LowMemoryBase, LowMemoryLength, HighMemoryBase= , HighMemoryLength)); =20 for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmrPei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Inte= lVTdPmrPei.c index ca099ed71d..faffb0a431 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -20,7 +20,7 @@ #include #include #include - +#include #include "IntelVTdPmrPei.h" =20 EFI_GUID mVTdInfoGuid =3D { @@ -424,38 +424,68 @@ InitDmaProtection ( UINTN MemoryAlignment; UINTN LowBottom; UINTN LowTop; - UINTN HighBottom; + UINT64 HighBottom; UINT64 HighTop; DMA_BUFFER_INFO *DmaBufferInfo; VOID *Hob; EFI_PEI_PPI_DESCRIPTOR *OldDescriptor; EDKII_IOMMU_PPI *OldIoMmuPpi; + SYSTEM_MEM_INFO_HOB *SysMemHob; + VOID *SysMemHobPtr; + + SysMemHob =3D NULL; + =20 Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); =20 - DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferS= ize)); + SysMemHobPtr =3D GetFirstGuidHob (&gSysMemInfoDataHobGuid); + + if (SysMemHobPtr =3D=3D NULL) { + // + // Calcuate the PMR memory alignment + // + LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo->Engine= Mask); + HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo->Engi= neMask); + if (LowMemoryAlignment < HighMemoryAlignment) { + MemoryAlignment =3D (UINTN)HighMemoryAlignment; + } else { + MemoryAlignment =3D LowMemoryAlignment; + } + ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D ALIGN_VALUE(DmaBufferInfo-= >DmaBufferSize, MemoryAlignment)); + + // + // Allocate memory for DMA buffer + // + DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SIZE= _TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); + ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); + if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { + DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); + return EFI_OUT_OF_RESOURCES; + } =20 - LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo->EngineMa= sk); - HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo->Engine= Mask); - if (LowMemoryAlignment < HighMemoryAlignment) { - MemoryAlignment =3D (UINTN)HighMemoryAlignment; + DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase + = DmaBufferInfo->DmaBufferSize; + DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo->DmaBufferBase; + LowBottom =3D 0; + LowTop =3D DmaBufferInfo->DmaBufferBase; + HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBuffer= Size; + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); } else { - MemoryAlignment =3D LowMemoryAlignment; - } - ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D ALIGN_VALUE(DmaBufferInfo->D= maBufferSize, MemoryAlignment)); - DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SIZE_T= O_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); - ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); - if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { - DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); - return EFI_OUT_OF_RESOURCES; + + // + // Get the PMR ranges information for the system hob + // + SysMemHob =3D GET_GUID_HOB_DATA (SysMemHobPtr); + DmaBufferInfo->DmaBufferBase =3D SysMemHob->ProtectedLowLimit; + LowBottom =3D SysMemHob->ProtectedLowBase; + LowTop =3D SysMemHob->ProtectedLowLimit; + HighBottom =3D SysMemHob->ProtectedHighBase; + HighTop =3D SysMemHob->ProtectedHighLimit; } =20 + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferS= ize)); DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", DmaBufferInfo->DmaBufferB= ase)); =20 - DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase + Dm= aBufferInfo->DmaBufferSize; - DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo->DmaBufferBase; - // // (Re)Install PPI. // @@ -472,10 +502,6 @@ InitDmaProtection ( } ASSERT_EFI_ERROR (Status); =20 - LowBottom =3D 0; - LowTop =3D DmaBufferInfo->DmaBufferBase; - HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSi= ze; - HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); =20 Status =3D SetDmaProtectedRange ( VTdInfo, diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdRe= g.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c index 4774a2ae5b..c9669426aa 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent =20 @@ -197,6 +197,8 @@ DisableDmar ( ) { UINT32 Reg32; + UINT32 Status; + UINT32 Command; =20 DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBase= Address)); =20 @@ -206,9 +208,30 @@ DisableDmar ( FlushWriteBuffer (VtdUnitBaseAddress); =20 // - // Disable VTd + // Disable Dmar // - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP); + // + // Set TE (Translation Enable: BIT31) of Global command register to zero + // + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & ~B_GMCD_REG_TE); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + // + // Poll on TE Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + + // + // Set SRTP (Set Root Table Pointer: BIT30) of Global command register i= n order to update the root table pointerDisable VTd + // + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | B_GMCD_REG_SRTP); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); do { Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSampl= ePei/PlatformVTdInfoSamplePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd= /PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c index 3698c3d3f1..6f6c14f7a9 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePei.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePei.c @@ -1,7 +1,7 @@ /** @file Platform VTd Info Sample PEI driver. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -166,15 +166,16 @@ EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDes= c =3D { =20 /** Initialize VTd register. + Initialize the VTd hardware unit which has INCLUDE_PCI_ALL set **/ VOID -InitDmar ( +InitGlobalVtd ( VOID ) { UINT32 MchBar; =20 - DEBUG ((DEBUG_INFO, "InitDmar\n")); + DEBUG ((DEBUG_INFO, "InitGlobalVtd\n")); =20 MchBar =3D PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0; PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 | BIT0); @@ -346,7 +347,7 @@ PlatformVTdInfoSampleInitialize ( DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized)); if (!SiliconInitialized) { Status =3D PeiServicesNotifyPpi (&mSiliconInitializedNotifyList); - InitDmar (); + InitGlobalVtd (); =20 Status =3D PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc); ASSERT_EFI_ERROR (Status); diff --git a/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib= /PeiGetVtdPmrAlignmentLib.c b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetV= tdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.c new file mode 100644 index 0000000000..5a205f29e0 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGet= VtdPmrAlignmentLib.c @@ -0,0 +1,166 @@ +/** @file + Library to get Global VTd PMR alignment information. + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef union { + struct { + UINT32 Low; + UINT32 High; + } Data32; + UINT64 Data; +} UINT64_STRUCT; + +/** + Get protected low memory alignment. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected low memory alignment. +**/ +UINT32 +EFIAPI +GetGlobalVTdPlmrAlignment ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Data32; + + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0xFFFFFFFF); + Data32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG); + Data32 =3D ~Data32 + 1; + + return Data32; +} + +/** + Get protected high memory alignment. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected high memory alignment. +**/ +UINT64_STRUCT +EFIAPI +GetGlobalVTdPhmrAlignment ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress + ) +{ + UINT64_STRUCT Data64; + + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0xFFFFFFFFFFFFFF= FF); + Data64.Data =3D MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG); + Data64.Data =3D ~Data64.Data + 1; + Data64.Data =3D Data64.Data & (LShiftU64 (1, HostAddressWidth) - 1); + + return Data64; +} + +/** + Get Global VT-d Protected Memory Aignment. + + @return protected high memory alignment. +**/ +UINTN +GetGlobalVtdPmrAlignment ( +) +{ + UINT32 LowMemoryAlignment; + UINT64_STRUCT HighMemoryAlignment; + UINTN MemoryAlignment; + UINT32 GlobalVTdBaseAddress; + EFI_STATUS Status; + UINTN VtdIndex; + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + EFI_ACPI_DMAR_DRHD_HEADER *DrhdHeader; + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; + + // + // Initialization + // + GlobalVTdBaseAddress =3D 0xFFFFFFFF; + LowMemoryAlignment =3D 0; + HighMemoryAlignment.Data =3D 0; + MemoryAlignment =3D 0; + Status =3D EFI_UNSUPPORTED; + VtdIndex =3D 0; + DmarHeader =3D NULL; + DrhdHeader =3D NULL; + AcpiDmarTable =3D NULL; + + // + // Fatch the PEI DMAR ACPU Table that created and installed in PlatformV= TdInfoSamplePei.c + // + Status =3D PeiServicesLocatePpi ( + &gEdkiiVTdInfoPpiGuid, + 0, + NULL, + (VOID **)&AcpiDmarTable + ); + if (EFI_ERROR (Status)) { + + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi gEdkiiVTdInfoPpiGuid failed= \n")); + Status =3D EFI_NOT_FOUND; + MemoryAlignment =3D SIZE_1MB; + + } else { + + // + // Seatch the DRHD structure with INCLUDE_PCI_ALL flag Set -> Global V= T-d + // + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTabl= e + 1)); + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Heade= r.Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + DrhdHeader =3D (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader; + if ((DrhdHeader->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL)= =3D=3D EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) { + GlobalVTdBaseAddress =3D (UINT32)DrhdHeader->RegisterBaseAddress; + DEBUG ((DEBUG_INFO," GlobalVTdBaseAddress: %x\n", GlobalVTdBase= Address)); + } + VtdIndex++; + + break; + + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader = + DmarHeader->Length); + } + + if (GlobalVTdBaseAddress =3D=3D 0xFFFFFFFF) { + + DEBUG ((DEBUG_ERROR, "Error! Please set INCLUDE_PCI_ALL flag to your= Global VT-d\n")); + MemoryAlignment =3D SIZE_1MB; + + } else { + // + // Get the alignment information from VT-d register + // + LowMemoryAlignment =3D GetGlobalVTdPlmrAlignment (AcpiDmarTable->Hos= tAddressWidth, GlobalVTdBaseAddress); + HighMemoryAlignment =3D GetGlobalVTdPhmrAlignment (AcpiDmarTable->Ho= stAddressWidth, GlobalVTdBaseAddress); + if (LowMemoryAlignment < HighMemoryAlignment.Data) { + MemoryAlignment =3D (UINTN)HighMemoryAlignment.Data; + } else { + MemoryAlignment =3D LowMemoryAlignment; + } + } + } + + return MemoryAlignment; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmrPei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/In= telVTdPmrPei.inf index 39b914cd00..2f6599d818 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.inf +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.inf @@ -4,7 +4,7 @@ # This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI # and provide DMA protection in PEI. # -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -40,6 +40,9 @@ IoLib CacheMaintenanceLib =20 +[Guids] + gSysMemInfoDataHobGuid ## CONSUMES + [Ppis] gEdkiiIoMmuPpiGuid ## PRODUCES gEdkiiVTdInfoPpiGuid ## CONSUMES diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlig= nmentLib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlig= nmentLib.h new file mode 100644 index 0000000000..537d013783 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/PeiGetVtdPmrAlignmentLi= b.h @@ -0,0 +1,31 @@ +/** @file + Get Global VTd PMR alignment information library. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + + +#ifndef __GET_VTD_PMR_ALIGN_LIB_H__ +#define __GET_VTD_PMR_ALIGN_LIB_H__ +#include + +/** + Get Global VT-d Protected Memory alignment. + + + @return protected high memory alignment. +**/ + +UINTN +GetGlobalVtdPmrAlignment ( +); + +#endif // __GET_VTD_PMR_ALIGN_LIB_H__ diff --git a/Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h b/Silico= n/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h new file mode 100644 index 0000000000..10153ac372 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/SysMemInfoHob.h @@ -0,0 +1,25 @@ +/** @file + The definition for VTD System information Hob. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef _SYS_MEM_INFO_HOB_H_ +#define _SYS_MEM_INFO_HOB_H_ + +// Platforms may request no overlap between PMR regions +// and system reserve memory. Create an interface to control PLMR/PHMR +// regions. It allows silicon code to adjust PLMR/PHMR region base on +// the project needs. +typedef struct { + UINT32 ProtectedLowBase; + UINT32 ProtectedLowLimit; + UINT64 ProtectedHighBase; + UINT64 ProtectedHighLimit; +} SYSTEM_MEM_INFO_HOB; + +#endif // _SYS_MEM_INFO_HOB_H_ + diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index fe5bfa0dc6..f1473ac60a 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -3,7 +3,7 @@ # # This package provides common open source Intel silicon modules. # -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -18,10 +18,14 @@ Include =20 [LibraryClasses.IA32, LibraryClasses.X64] - ## @libraryclass Provides services to access Microcode region on flash = device. + ## @libraryclass Provides services to access Microcode region on flash d= evice. # MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h =20 + ## @libraryclass Provides services to access VTd PMR information + # + PeiGetVtdPmrAlignmentLib|Include/Library/PeiGetVtdPmrAlignmentLib.h + [Guids] ## GUID for Package token space # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735} @@ -35,6 +39,9 @@ ## Include/Guid/MicrocodeFmp.h gMicrocodeFmpImageTypeIdGuid =3D { 0x96d4fdcd, 0x1502, 0x424d, { 0x= 9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } } =20 + ## HOB GUID to get memory information after MRC is done. The hob data wi= ll be used to set the PMR ranges + gSysMemInfoDataHobGuid =3D {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, 0x= b5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } } + [Ppis] gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } =20 diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dsc index 58b5b656ef..352d1e2b6d 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -1,7 +1,7 @@ ## @file # This package provides common open source Intel silicon modules. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -34,6 +34,7 @@ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/Microcod= eFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf + PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLi= b/PeiGetVtdPmrAlignmentLib.inf =20 [LibraryClasses.common.PEIM] PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf diff --git a/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib= /PeiGetVtdPmrAlignmentLib.inf b/Silicon/Intel/IntelSiliconPkg/Library/PeiGe= tVtdPmrAlignmentLib/PeiGetVtdPmrAlignmentLib.inf new file mode 100644 index 0000000000..ebb2cc2a7f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLib/PeiGet= VtdPmrAlignmentLib.inf @@ -0,0 +1,32 @@ +## @file +# Component INF file for the GetVtdPmrAlignment library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D PeiGetVtdPmrAlignmentLib +FILE_GUID =3D 0332BE93-0547-4D87-A7FA-0D9D76C53187 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D PeiGetVtdPmrAlignmentLib + +[Packages] +MdePkg/MdePkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] +PeiGetVtdPmrAlignmentLib.c + +[LibraryClasses] +DebugLib +BaseMemoryLib +MemoryAllocationLib +BaseLib +PeiServicesLib + +[Ppis] +gEdkiiVTdInfoPpiGuid ## CONSUMES --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45444): https://edk2.groups.io/g/devel/message/45444 Mute This Topic: https://groups.io/mt/32841447/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-