From nobody Tue Apr 23 17:04:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45255+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45255+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565331149; cv=none; d=zoho.com; s=zohoarc; b=Nl2HJyzMWrhq1O0irqLoVywM9rhnyZhw5Fz5cIKAarWvFik0wxs9L7fF/ToV1GxkkohEKIfT+H9PS6EFDalMLbkLV25AbeiS2/rKGeJAMMfvsQ7Xbvr9XXQ3UrblXtzHynGTBD0mv7IaZE0squ996NS74esMI53rh9cM/zOJOG0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565331149; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=JqB59/u+67NAhFJrnxM1dJGyL4g6z+KPWpBK1akZ/yc=; b=MP96eh4OHPAI7E0IGxXAGm4ETWzZWj71qAM5nztvrHgrZLTRNG+EzU+vDhZeYMh8RzdY9ZT/1fAM8+JYYJ6H0l+tpEuScqrhT6RYQmHim4szG73c9EDd72yRtXS5Menm4OSK1DGDUiwhzyieOQQDSsctBpHawhU40ZG12MoSzOM= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45255+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565331149863115.66150446315453; Thu, 8 Aug 2019 23:12:29 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 08 Aug 2019 23:12:29 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2019 23:12:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,364,1559545200"; d="scan'208";a="326540071" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga004.jf.intel.com with ESMTP; 08 Aug 2019 23:12:27 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch 1/4] UefiCpuPkg/RegisterCpuFeaturesLib: Add "detect before set" Micros. Date: Fri, 9 Aug 2019 14:11:56 +0800 Message-Id: <20190809061159.40248-2-eric.dong@intel.com> In-Reply-To: <20190809061159.40248-1-eric.dong@intel.com> References: <20190809061159.40248-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565331149; bh=Mqneg6SBcyGR137mZHU60zWiNWSROOL51lcDlCprOrA=; h=Cc:Date:From:Reply-To:Subject:To; b=V6IzQBe1Z4P1HEFa1dzD8xIXA4NnpEyOugURUHiXrXUUvqYrUXsK6conu7ssncZfYCR f7y+SC2oy7cs/pQqpAPRQvps2qdY3oHy8asXRiA4rb/jXo8pyiGQuFPNL2uQevrZSHtNi rgGub9Bv4EZO6ZMuXrPpxYX0jXkffVeo40w= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Add below new micros which test the current value before set the new value. Only set new value when current value not same as new value. CPU_REGISTER_TABLE_TEST_THEN_WRITE32 CPU_REGISTER_TABLE_TEST_THEN_WRITE64 CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek --- UefiCpuPkg/Include/AcpiCpuData.h | 1 + .../Include/Library/RegisterCpuFeaturesLib.h | 77 +++++++++++++++++-- .../RegisterCpuFeaturesLib.c | 14 +++- 3 files changed, 80 insertions(+), 12 deletions(-) diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuD= ata.h index b963a2f592..c764e209cf 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -81,6 +81,7 @@ typedef struct { UINT16 Reserved; // offset 10 - 11 UINT32 HighIndex; // offset 12-15, only valid for Me= moryMapped UINT64 Value; // offset 16-23 + UINT8 DetectIt; // 0ffset 24 } CPU_REGISTER_TABLE_ENTRY; =20 // diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index e420e7f075..87fe87acb7 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -335,6 +335,7 @@ SwitchBspAfterFeaturesInitialize ( @param[in] Index Index of the register to program @param[in] ValueMask Mask of bits in register to write @param[in] Value Value to write + @param[in] DetectIt Whether need to detect current Value before= writing. =20 @note This service could be called by BSP only. **/ @@ -345,7 +346,8 @@ CpuRegisterTableWrite ( IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT64 ValueMask, - IN UINT64 Value + IN UINT64 Value, + IN UINT8 DetectIt ); =20 /** @@ -385,9 +387,45 @@ PreSmmCpuRegisterTableWrite ( =20 @note This service could be called by BSP only. **/ -#define CPU_REGISTER_TABLE_WRITE32(ProcessorNumber, RegisterType, Index, V= alue) \ - do { = \ - CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT3= 2, Value); \ +#define CPU_REGISTER_TABLE_WRITE32(ProcessorNumber, RegisterType, Index, V= alue) \ + do { = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT3= 2, Value, FALSE); \ + } while(FALSE); + +/** + Adds a 32-bit register write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, and value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE32(ProcessorNumber, RegisterType= , Index, Value) \ + do { = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT3= 2, Value, TRUE); \ + } while(FALSE); + +/** + Adds a 64-bit register write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, and value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program + @param[in] Index Index of the register to program + @param[in] Value Value to write + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_WRITE64(ProcessorNumber, RegisterType, Index, V= alue) \ + do { = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT6= 4, Value, FALSE); \ } while(FALSE); =20 /** @@ -403,9 +441,9 @@ PreSmmCpuRegisterTableWrite ( =20 @note This service could be called by BSP only. **/ -#define CPU_REGISTER_TABLE_WRITE64(ProcessorNumber, RegisterType, Index, V= alue) \ - do { = \ - CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT6= 4, Value); \ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE64(ProcessorNumber, RegisterType= , Index, Value) \ + do { = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, MAX_UINT6= 4, Value, TRUE); \ } while(FALSE); =20 /** @@ -428,7 +466,30 @@ PreSmmCpuRegisterTableWrite ( UINT64 ValueMask; = \ ValueMask =3D MAX_UINT64; = \ ((Type *)(&ValueMask))->Field =3D 0; = \ - CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMas= k, Value); \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMas= k, Value, FALSE); \ + } while(FALSE); + +/** + Adds a bit field write entry in specified register table. + + This macro adds an entry in specified register table, with given registe= r type, + register index, bit field section, and value. + + @param[in] ProcessorNumber The index of the CPU to add a register tabl= e entry. + @param[in] RegisterType Type of the register to program. + @param[in] Index Index of the register to program. + @param[in] Type The data type name of a register structure. + @param[in] Field The bit fiel name in register structure to = write. + @param[in] Value Value to write to the bit field. + + @note This service could be called by BSP only. +**/ +#define CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD(ProcessorNumber, Register= Type, Index, Type, Field, Value) \ + do { = \ + UINT64 ValueMask; = \ + ValueMask =3D MAX_UINT64; = \ + ((Type *)(&ValueMask))->Field =3D 0; = \ + CpuRegisterTableWrite (ProcessorNumber, RegisterType, Index, ~ValueMas= k, Value, TRUE); \ } while(FALSE); =20 /** diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesL= ib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index 67885bf69b..152ab75988 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -1025,6 +1025,8 @@ EnlargeRegisterTable ( @param[in] ValidBitStart Start of the bit section @param[in] ValidBitLength Length of the bit section @param[in] Value Value to write + @param[in] DetectIt Whether need to detect current Value before= writing. + **/ VOID CpuRegisterTableWriteWorker ( @@ -1034,7 +1036,8 @@ CpuRegisterTableWriteWorker ( IN UINT64 Index, IN UINT8 ValidBitStart, IN UINT8 ValidBitLength, - IN UINT64 Value + IN UINT64 Value, + IN UINT8 DetectIt ) { CPU_FEATURES_DATA *CpuFeaturesData; @@ -1070,6 +1073,7 @@ CpuRegisterTableWriteWorker ( RegisterTableEntry[RegisterTable->TableLength].ValidBitStart =3D ValidB= itStart; RegisterTableEntry[RegisterTable->TableLength].ValidBitLength =3D ValidB= itLength; RegisterTableEntry[RegisterTable->TableLength].Value =3D Value; + RegisterTableEntry[RegisterTable->TableLength].DetectIt =3D Detect= It; =20 RegisterTable->TableLength++; } @@ -1085,6 +1089,7 @@ CpuRegisterTableWriteWorker ( @param[in] Index Index of the register to program @param[in] ValueMask Mask of bits in register to write @param[in] Value Value to write + @param[in] DetectIt Whether need to detect current Value before= writing. =20 @note This service could be called by BSP only. **/ @@ -1095,7 +1100,8 @@ CpuRegisterTableWrite ( IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT64 ValueMask, - IN UINT64 Value + IN UINT64 Value, + IN UINT8 DetectIt ) { UINT8 Start; @@ -1105,7 +1111,7 @@ CpuRegisterTableWrite ( Start =3D (UINT8)LowBitSet64 (ValueMask); End =3D (UINT8)HighBitSet64 (ValueMask); Length =3D End - Start + 1; - CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value); + CpuRegisterTableWriteWorker (FALSE, ProcessorNumber, RegisterType, Index= , Start, Length, Value, DetectIt); } =20 /** @@ -1139,7 +1145,7 @@ PreSmmCpuRegisterTableWrite ( Start =3D (UINT8)LowBitSet64 (ValueMask); End =3D (UINT8)HighBitSet64 (ValueMask); Length =3D End - Start + 1; - CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index,= Start, Length, Value); + CpuRegisterTableWriteWorker (TRUE, ProcessorNumber, RegisterType, Index,= Start, Length, Value, FALSE); } =20 /** --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45255): https://edk2.groups.io/g/devel/message/45255 Mute This Topic: https://groups.io/mt/32807819/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 17:04:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45256+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45256+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565331151; cv=none; d=zoho.com; s=zohoarc; b=QYCCGTaaqg9JiS4HJ65ai9ZEaTWWnsg3hFvvQT3tD/5VyttuvgBPOdo3B0YhAsUlImdx7edmnJKk6wEGylNcqG04cG/mWVkCfzpXywMcj8fDzDvlpfAsMeCiM25lg5y1bsSbb6keBhSUmdfi5zze97OABx1iAhSfY3LwgsVc4Gw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565331151; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=K9chs6KetunLExums2OOUwvBAtT0xmYFoO7EHXqHQHY=; b=MA7qfhAXG+F4JOCZySsWFjq/zPGXOqePP/GLcUxfKwX9hK9UPgTKovxA7UduaxGD0iyyjGvEPhfXKPfmcphu3Du9Tsr4HI8tg6IN0PKQQESgbIVA8s1Uq42K7hmJ6LWw2f9GtrMLwtBwSzYSKsoB7QKnjd6tUSiQrbE6/y8B/5U= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45256+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565331151107668.9614960506592; Thu, 8 Aug 2019 23:12:31 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 08 Aug 2019 23:12:30 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2019 23:12:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,364,1559545200"; d="scan'208";a="326540076" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga004.jf.intel.com with ESMTP; 08 Aug 2019 23:12:29 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch 2/4] UefiCpuPkg/RegisterCpuFeaturesLib: Supports detect before set new value logic. Date: Fri, 9 Aug 2019 14:11:57 +0800 Message-Id: <20190809061159.40248-3-eric.dong@intel.com> In-Reply-To: <20190809061159.40248-1-eric.dong@intel.com> References: <20190809061159.40248-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565331150; bh=0qhr15xcdSsStaQ8+XuihARWA11uTNDH6vX9CCa5kIY=; h=Cc:Date:From:Reply-To:Subject:To; b=fkSY7fuGJ0URog09FqYyJPody08d7vK/0oMI8qQC3EyXlzc+4Qbo8oxaJtPcDHynD6N MM0MyYb/louVqgMNFZIUMN5/Xb2ACsyvRcrdja1rj2AP6ZgigMtX85UFEcpUuY6gX2WMG Ss2yhzVZivyQGFIYcOOt7iU99HR3PVeKUDE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Supports new logic which detect current value before set new value. Only set new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek --- .../CpuFeaturesInitialize.c | 141 ++++++++++++------ 1 file changed, 93 insertions(+), 48 deletions(-) diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index fb0535edd6..2b8816e1d8 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -744,6 +744,58 @@ LibWaitForSemaphore ( ) !=3D Value); } =20 +/** + Read / write CR value. + + @param[in] CrIndex The CR index which need to read/write. + @param[in] Read Read or write. TRUE is read. + @param[in,out] CrValue CR value. + + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. +**/ +UINTN +ReadWriteCr ( + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue + ) +{ + switch (CrIndex) { + case 0: + if (Read) { + *CrValue =3D AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + break; + case 2: + if (Read) { + *CrValue =3D AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + break; + case 3: + if (Read) { + *CrValue =3D AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + break; + case 4: + if (Read) { + *CrValue =3D AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + break; + default: + return EFI_UNSUPPORTED;; + } + + return EFI_SUCCESS; +} + /** Initialize the CPU registers from a register table. =20 @@ -773,6 +825,8 @@ ProgramProcessorRegister ( UINTN ProcessorIndex; UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; + EFI_STATUS Status; + UINT64 CurrentValue; =20 // // Traverse Register Table of this logical processor @@ -791,60 +845,51 @@ ProgramProcessorRegister ( // The specified register is Control Register // case ControlRegister: - switch (RegisterTableEntry->Index) { - case 0: - Value =3D AsmReadCr0 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr0 (Value); - break; - case 2: - Value =3D AsmReadCr2 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr2 (Value); - break; - case 3: - Value =3D AsmReadCr3 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr3 (Value); - break; - case 4: - Value =3D AsmReadCr4 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - RegisterTableEntry->Value - ); - AsmWriteCr4 (Value); - break; - case 8: - // - // Do we need to support CR8? - // - break; - default: - break; + Status =3D ReadWriteCr(RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { + return; + } + if (RegisterTableEntry->DetectIt) { + CurrentValue =3D BitFieldRead64( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + return; + } } + Value =3D (UINTN) BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableE= ntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; + // // The specified register is Model Specific Register // case Msr: + if (RegisterTableEntry->DetectIt) { + Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >=3D 64) { + if (Value =3D=3D RegisterTableEntry->Value) { + return; + } + } else { + CurrentValue =3D BitFieldRead64( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + return; + } + } + } + if (RegisterTableEntry->ValidBitLength >=3D 64) { // // If length is not less than 64 bits, then directly write without= reading --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45256): https://edk2.groups.io/g/devel/message/45256 Mute This Topic: https://groups.io/mt/32807820/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 17:04:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45257+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45257+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565331152; cv=none; d=zoho.com; s=zohoarc; b=bDeiNVzNONU3oEBxSnBj7BUB0qF/cGd88pBtVaJqnPBPnSTN8AL8wfkQn4S2ToNlCz+TQL8cQbQ75FV7eJJpMg8qvU+9L9Nq9w4zwqM44lxvppvHeLqU+DF7H2AheYC10liuiRUh4MuCUJb9uEbgrX6cpnyOtYME9Pa6Hkk2zRw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565331152; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=PR+5/W6q09sMqRsrl04i6x3qiruyeoqsNgcjgptYOik=; b=KKWWziqXkImYlXSAE723YiR1Ep4iaHr2CSI8Y0sYD5zVRGqv1/rSlvURmt8Uwfqs/ZN2mFwAheqTPUxGa7Op7ZCE0dY2HqScZb5rZKtCyPYPmt4OvXSJJMuBHM05XePh1AoOBpaWnVp6NE0yIECx72Q8oEP6l4bt+5zijgW52JU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45257+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565331152339694.6143409778824; Thu, 8 Aug 2019 23:12:32 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 08 Aug 2019 23:12:31 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2019 23:12:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,364,1559545200"; d="scan'208";a="326540080" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga004.jf.intel.com with ESMTP; 08 Aug 2019 23:12:30 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch 3/4] UefiCpuPkg/PiSmmCpuDxeSmm: Supports detect before set new value logic. Date: Fri, 9 Aug 2019 14:11:58 +0800 Message-Id: <20190809061159.40248-4-eric.dong@intel.com> In-Reply-To: <20190809061159.40248-1-eric.dong@intel.com> References: <20190809061159.40248-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565331151; bh=ftKmadOk0HR/8MHVpAppxmGXYk42fLSCjMOIgW0cnVc=; h=Cc:Date:From:Reply-To:Subject:To; b=i6AWFTzdu8fmBUynCu+8wHVzDfjiVaPsodT/3EGmpHv88/rmI/jXaZdt6CxY4WMlOjz oCaOOOOtvD62hnvDwpTXure410vLO6rSfd8DENvPOWvWxQZEo1R1V7TNqUX54M19Zrsq5 4zQAWDjNwXVWoYrBABgojBYMq40/M6Ac9lA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Supports new logic which detect current value before set new value. Only set new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek --- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 135 ++++++++++++++++++++---------- 1 file changed, 92 insertions(+), 43 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/= CpuS3.c index d8c6b19ead..957f2896eb 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -159,6 +159,58 @@ S3WaitForSemaphore ( ) !=3D Value); } =20 +/** + Read / write CR value. + + @param[in] CrIndex The CR index which need to read/write. + @param[in] Read Read or write. TRUE is read. + @param[in,out] CrValue CR value. + + @retval EFI_SUCCESS means read/write success, else return EFI_UNSUPPO= RTED. +**/ +UINTN +ReadWriteCr ( + IN UINT32 CrIndex, + IN BOOLEAN Read, + IN OUT UINTN *CrValue + ) +{ + switch (CrIndex) { + case 0: + if (Read) { + *CrValue =3D AsmReadCr0 (); + } else { + AsmWriteCr0 (*CrValue); + } + break; + case 2: + if (Read) { + *CrValue =3D AsmReadCr2 (); + } else { + AsmWriteCr2 (*CrValue); + } + break; + case 3: + if (Read) { + *CrValue =3D AsmReadCr3 (); + } else { + AsmWriteCr3 (*CrValue); + } + break; + case 4: + if (Read) { + *CrValue =3D AsmReadCr4 (); + } else { + AsmWriteCr4 (*CrValue); + } + break; + default: + return EFI_UNSUPPORTED;; + } + + return EFI_SUCCESS; +} + /** Initialize the CPU registers from a register table. =20 @@ -188,6 +240,8 @@ ProgramProcessorRegister ( UINTN ProcessorIndex; UINTN ValidThreadCount; UINT32 *ValidCoreCountPerPackage; + EFI_STATUS Status; + UINT64 CurrentValue; =20 // // Traverse Register Table of this logical processor @@ -206,55 +260,50 @@ ProgramProcessorRegister ( // The specified register is Control Register // case ControlRegister: - switch (RegisterTableEntry->Index) { - case 0: - Value =3D AsmReadCr0 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr0 (Value); - break; - case 2: - Value =3D AsmReadCr2 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr2 (Value); - break; - case 3: - Value =3D AsmReadCr3 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr3 (Value); - break; - case 4: - Value =3D AsmReadCr4 (); - Value =3D (UINTN) BitFieldWrite64 ( - Value, - RegisterTableEntry->ValidBitStart, - RegisterTableEntry->ValidBitStart + RegisterTabl= eEntry->ValidBitLength - 1, - (UINTN) RegisterTableEntry->Value - ); - AsmWriteCr4 (Value); - break; - default: - break; + Status =3D ReadWriteCr(RegisterTableEntry->Index, TRUE, &Value); + if (EFI_ERROR (Status)) { + return; + } + if (RegisterTableEntry->DetectIt) { + CurrentValue =3D BitFieldRead64( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTable= Entry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + return; + } } + Value =3D (UINTN) BitFieldWrite64 ( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTableE= ntry->ValidBitLength - 1, + RegisterTableEntry->Value + ); + ReadWriteCr (RegisterTableEntry->Index, FALSE, &Value); break; // // The specified register is Model Specific Register // case Msr: + if (RegisterTableEntry->DetectIt) { + Value =3D (UINTN)AsmReadMsr64 (RegisterTableEntry->Index); + if (RegisterTableEntry->ValidBitLength >=3D 64) { + if (Value =3D=3D RegisterTableEntry->Value) { + return; + } + } else { + CurrentValue =3D BitFieldRead64( + Value, + RegisterTableEntry->ValidBitStart, + RegisterTableEntry->ValidBitStart + RegisterTab= leEntry->ValidBitLength - 1 + ); + if (CurrentValue =3D=3D RegisterTableEntry->Value) { + return; + } + } + } + // // If this function is called to restore register setting after INIT= signal, // there is no need to restore MSRs in register table. --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45257): https://edk2.groups.io/g/devel/message/45257 Mute This Topic: https://groups.io/mt/32807821/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 23 17:04:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45258+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45258+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565331154; cv=none; d=zoho.com; s=zohoarc; b=OAX9I4cHhVplLOCYn56HU2i5gapzV78QNgvVFaaXJJZ+OJPIRtCbaEh5ZruIWawvRjJSEFBx41G28YmQBZKHhZROFhV0NJd7/g9P1fibwqFhvt50niZx7iOVOa5+tFkBGLD5tDTRwvpbHXfUc+ntywzChmzl+9T2c6OrRENf62I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565331154; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=3ScyWFdHSOJGuKWAC131sz6h5NyXom/11dwrNiiMq5Q=; b=WIVW0GZDyrxd+RyDgEKh8pq+2J/0TiWBS9tL7co82yH2+XbyWYORHe2uBYQcAjMcUjU2X0FDGV7VcnEOJi6BDgzMoltggmjEop+LnVTgmwO7CYgO3CuMe1D3VYPGk4hf66du8PtVvZ6X847jRcIsfLHmw5NcfP8qtKjmwB38+Rc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45258+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565331154835197.28876926628095; Thu, 8 Aug 2019 23:12:34 -0700 (PDT) Return-Path: X-Received: from mga06.intel.com (mga06.intel.com []) by groups.io with SMTP; Thu, 08 Aug 2019 23:12:33 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Aug 2019 23:12:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,364,1559545200"; d="scan'208";a="326540086" X-Received: from ydong10-win10.ccr.corp.intel.com ([10.239.158.133]) by orsmga004.jf.intel.com with ESMTP; 08 Aug 2019 23:12:31 -0700 From: "Dong, Eric" To: devel@edk2.groups.io Cc: Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch 4/4] UefiCpuPkg/CpuCommonFeaturesLib: Use "Test then set" action. Date: Fri, 9 Aug 2019 14:11:59 +0800 Message-Id: <20190809061159.40248-5-eric.dong@intel.com> In-Reply-To: <20190809061159.40248-1-eric.dong@intel.com> References: <20190809061159.40248-1-eric.dong@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,eric.dong@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565331154; bh=vu8hEx2qSVlhtl28Z9jC+VnQAeTHlA6spAcAz5K94oo=; h=Cc:Date:From:Reply-To:Subject:To; b=ers9VPGdNDbBpASxu/7oLMvJ7GmCFdE8ysblka4xp/E5XwfpnVroG8Zw/hd0a53HfEY mwBo2ajn7gg9DhR272S5/PjmF0RpgDOxSeX438ppRGPtNKDemu+9ewHapqIWdP06e3AQR wYqbImr1Lzk+c5rZrnI0ZBpcbTa15UWLYgM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2040 Below code is current implementation: if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { CPU_REGISTER_TABLE_WRITE_FIELD ( ProcessorNumber, Msr, MSR_IA32_FEATURE_CONTROL, MSR_IA32_FEATURE_CONTROL_REGISTER, Bits.Lock, 1 ); } With below steps, the Bits.Lock bit will lose its value: 1. In first normal boot, the Bits.Lock is 0. 1 will be added into the register table and then will set to the MSR. 2. Trig warm reboot, MSR value preserves. After normal boot phase, the Bits.Lock is 1, so it will not be added into the register table during the warm reboot phase. 3. Trig S3 then resume, the Bits.Lock change to 0 and Bits.Lock is not added in register table during normal boot phase. so it's still 0 after resume.=20 This is not an expect behavior. The expect result is the value should always 1 after booting or resuming from S3. The root cause for this issue is 1. driver bases on current value to insert the "set value action" to the register table. 2. Some MSRs may reserve their value during warm reboot. So the insert action may be skip after warm reboot. The solution for this issue is: 1. Always add "Test then Set" action for above referred MSRs. 2. Detect current value before set new value. Only set new value when current value not same as new value. Signed-off-by: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek --- .../CpuCommonFeaturesLib/CpuCommonFeatures.h | 15 -- .../CpuCommonFeaturesLib.c | 8 +- .../CpuCommonFeaturesLib/FeatureControl.c | 141 ++++++------------ .../CpuCommonFeaturesLib/MachineCheck.c | 23 ++- 4 files changed, 58 insertions(+), 129 deletions(-) diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h b/= UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h index 25d0174727..b2390e6c39 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h @@ -848,21 +848,6 @@ X2ApicInitialize ( IN BOOLEAN State ); =20 -/** - Prepares for the data used by CPU feature detection and initialization. - - @param[in] NumberOfProcessors The number of CPUs in the platform. - - @return Pointer to a buffer of CPU related configuration data. - - @note This service could be called by BSP only. -**/ -VOID * -EFIAPI -FeatureControlGetConfigData ( - IN UINTN NumberOfProcessors - ); - /** Prepares for the data used by CPU feature detection and initialization. =20 diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c= b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c index fd43b8d662..f0dd3a3b43 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c @@ -91,7 +91,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER)) { Status =3D RegisterCpuFeature ( "Lock Feature Control Register", - FeatureControlGetConfigData, + NULL, LockFeatureControlRegisterSupport, LockFeatureControlRegisterInitialize, CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER, @@ -102,7 +102,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_SMX)) { Status =3D RegisterCpuFeature ( "SMX", - FeatureControlGetConfigData, + NULL, SmxSupport, SmxInitialize, CPU_FEATURE_SMX, @@ -114,7 +114,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_VMX)) { Status =3D RegisterCpuFeature ( "VMX", - FeatureControlGetConfigData, + NULL, VmxSupport, VmxInitialize, CPU_FEATURE_VMX, @@ -214,7 +214,7 @@ CpuCommonFeaturesLibConstructor ( if (IsCpuFeatureSupported (CPU_FEATURE_LMCE)) { Status =3D RegisterCpuFeature ( "LMCE", - FeatureControlGetConfigData, + NULL, LmceSupport, LmceInitialize, CPU_FEATURE_LMCE, diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c b/Uef= iCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c index 3712ef1e5c..6679df8ba4 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c @@ -8,28 +8,6 @@ =20 #include "CpuCommonFeatures.h" =20 -/** - Prepares for the data used by CPU feature detection and initialization. - - @param[in] NumberOfProcessors The number of CPUs in the platform. - - @return Pointer to a buffer of CPU related configuration data. - - @note This service could be called by BSP only. -**/ -VOID * -EFIAPI -FeatureControlGetConfigData ( - IN UINTN NumberOfProcessors - ) -{ - VOID *ConfigData; - - ConfigData =3D AllocateZeroPool (sizeof (MSR_IA32_FEATURE_CONTROL_REGIST= ER) * NumberOfProcessors); - ASSERT (ConfigData !=3D NULL); - return ConfigData; -} - /** Detects if VMX feature supported on current processor. =20 @@ -54,11 +32,6 @@ VmxSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return (CpuInfo->CpuIdVersionInfoEcx.Bits.VMX =3D=3D 1); } =20 @@ -88,8 +61,6 @@ VmxInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of EnableVmxOutsideSmx bit in the MSR_IA32_FEATURE_CONTROL = is core for // below processor type, only program MSR_IA32_FEATURE_CONTROL for threa= d 0 in each @@ -103,18 +74,15 @@ VmxInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.EnableVmxOutsideSmx, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.EnableVmxOutsideSmx, + (State) ? 1 : 0 + ); + return RETURN_SUCCESS; } =20 @@ -142,11 +110,6 @@ LockFeatureControlRegisterSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return TRUE; } =20 @@ -176,8 +139,6 @@ LockFeatureControlRegisterInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of Lock bit in the MSR_IA32_FEATURE_CONTROL is core for // below processor type, only program MSR_IA32_FEATURE_CONTROL for threa= d 0 in each @@ -191,18 +152,15 @@ LockFeatureControlRegisterInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.Lock, - 1 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.Lock, + 1 + ); + return RETURN_SUCCESS; } =20 @@ -230,11 +188,6 @@ SmxSupport ( IN VOID *ConfigData OPTIONAL ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - MsrRegister[ProcessorNumber].Uint64 =3D AsmReadMsr64 (MSR_IA32_FEATURE_C= ONTROL); return (CpuInfo->CpuIdVersionInfoEcx.Bits.SMX =3D=3D 1); } =20 @@ -265,7 +218,6 @@ SmxInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; RETURN_STATUS Status; =20 // @@ -288,35 +240,32 @@ SmxInitialize ( Status =3D RETURN_UNSUPPORTED; } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.SenterLocalFunctionEnables, - (State) ? 0x7F : 0 - ); - - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.SenterGlobalEnable, - (State) ? 1 : 0 - ); - - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.EnableVmxInsideSmx, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.SenterLocalFunctionEnables, + (State) ? 0x7F : 0 + ); + + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.SenterGlobalEnable, + (State) ? 1 : 0 + ); + + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.EnableVmxInsideSmx, + (State) ? 1 : 0 + ); + return Status; } diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c b/UefiC= puPkg/Library/CpuCommonFeaturesLib/MachineCheck.c index 2528e0044e..01fd6bb54d 100644 --- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c +++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c @@ -319,8 +319,6 @@ LmceInitialize ( IN BOOLEAN State ) { - MSR_IA32_FEATURE_CONTROL_REGISTER *MsrRegister; - // // The scope of LcmeOn bit in the MSR_IA32_MISC_ENABLE is core for below= processor type, only program // MSR_IA32_MISC_ENABLE for thread 0 in each core. @@ -333,17 +331,14 @@ LmceInitialize ( } } =20 - ASSERT (ConfigData !=3D NULL); - MsrRegister =3D (MSR_IA32_FEATURE_CONTROL_REGISTER *) ConfigData; - if (MsrRegister[ProcessorNumber].Bits.Lock =3D=3D 0) { - CPU_REGISTER_TABLE_WRITE_FIELD ( - ProcessorNumber, - Msr, - MSR_IA32_FEATURE_CONTROL, - MSR_IA32_FEATURE_CONTROL_REGISTER, - Bits.LmceOn, - (State) ? 1 : 0 - ); - } + CPU_REGISTER_TABLE_TEST_THEN_WRITE_FIELD ( + ProcessorNumber, + Msr, + MSR_IA32_FEATURE_CONTROL, + MSR_IA32_FEATURE_CONTROL_REGISTER, + Bits.LmceOn, + (State) ? 1 : 0 + ); + return RETURN_SUCCESS; } --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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