From nobody Tue Feb 10 02:55:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45168+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45168+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1565267035; cv=none; d=zoho.com; s=zohoarc; b=lWIyIaMtWwlpsmhqF+siqCH6I8lraukGy3FRbgXDw3ETC4/+n8UUTrNTcMVN5jCRlqTGTu6L54WrHaEn7r5eUu9VMx+VPapIiuaxMz2KEetf5yRaNzoXI9el1Rh30N6/Vnc0Ezdhyw0BeFJFyVMqbtauevP8vd3HbUxjD0pzWn0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565267035; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=VqN9zbQUxzVaKX9WGp6e5XRNxXS1Dv4BUkupgZbBHvk=; b=nZDsSUPJkBJrbXaQ4BhxHqkWhPeIdixiPt5K8BxFkqmRxzKBTCE7Zk9l8wOieQw7ZaaRSLzK2kJI+ATglX32SsEdL92N/5gMGqSDnQPhQYXghqEqjIIL29w/jBKCWOp0MgoDbzzmS/1Hz2vKEOLmhXkMc1WUGXmg6/a4LW4H3rI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45168+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565267034987574.0030214990504; Thu, 8 Aug 2019 05:23:54 -0700 (PDT) Return-Path: X-Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by groups.io with SMTP; Thu, 08 Aug 2019 05:23:54 -0700 X-Received: by mail-pf1-f196.google.com with SMTP id r1so44014590pfq.12 for ; Thu, 08 Aug 2019 05:23:54 -0700 (PDT) X-Gm-Message-State: APjAAAWtLXplMJJS3DXCOowWuU9ODv2lEPZuQJblHUYoUdjiHWKltBBf kWC6GY94KXkt+mfzrjVRW7my8f9N74U= X-Google-Smtp-Source: APXvYqxjGL+Kd2uyttXPZ3l4zlWtyJEtyS6A13OUuUEVNHS66znudjmmKpZP268dbJqe+NEwoBgnKg== X-Received: by 2002:a63:a66:: with SMTP id z38mr12891885pgk.247.1565267033160; Thu, 08 Aug 2019 05:23:53 -0700 (PDT) X-Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id f88sm2195424pjg.5.2019.08.08.05.23.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Aug 2019 05:23:52 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, okamoto.satoru@socionext.com, Masahisa Kojima Subject: [edk2-devel] [PATCH edk2-platforms v3 2/3] NetsecDxe: put phy in loopback mode to guarantee stable RXCLK input Date: Thu, 8 Aug 2019 21:23:34 +0900 Message-Id: <20190808122335.11883-3-masahisa.kojima@linaro.org> In-Reply-To: <20190808122335.11883-1-masahisa.kojima@linaro.org> References: <20190808122335.11883-1-masahisa.kojima@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,masahisa.kojima@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565267034; bh=ExDlT+0oUM9yaguSQc8M+3obSbIUsXil9che787qVH4=; h=Cc:Date:From:Reply-To:Subject:To; b=nqmojdEZW/A9vhlMXvzw1pJ73d8urJDTuKecjuQvegvXzMFjvIWwALq29eWHIHkCZv9 STdzSGI9nYYPQImZF5q7q13LIYXU0lbvTEKv9EagyXhv6AgZK9Vf5ZLgC5HNK0J8wUgnD LA1HmlYYPpvM0KhXK8BkSnwcBT+Oaq+U5jA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Satoru Okamoto NETSEC hardware requires stable RXCLK input upon initialization triggered with DISCORE =3D 0. However, RXCLK input could be unstable depending on phy chipset and deployed network environment, which could cause NETSEC to hang up during initialization. We solve this platform/environment dependent issue by temporarily putting phy in loopback mode, then we can expect the stable RXCLK input. Signed-off-by: Masahisa Kojima --- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_s= dk/src/ogma_misc.c | 72 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_s= dk/src/ogma_reg.h | 4 ++ 2 files changed, 76 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/SynQuacer/Drivers/Net/Ne= tsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c index 7481d2da2d24..5f6ddc0c745e 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_misc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_misc.c @@ -327,6 +327,60 @@ STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param ( return param; } =20 +STATIC +void +ogma_pre_init_microengine ( + ogma_handle_t ogma_handle + ) +{ + UINT16 Data; + + /* Remove dormant settings */ + Data =3D ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ~((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) | + (1U << OGMA_PHY_CONTROL_REG_ISOLATE)); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) | + (1U << OGMA_PHY_CONTROL_REG_ISOLATE))) !=3D 0); + + /* Put phy in loopback mode to guarantee RXCLK input */ + Data |=3D (1U << OGMA_PHY_CONTROL_REG_LOOPBACK); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) =3D=3D 0); +} + +STATIC +void +ogma_post_init_microengine ( + IN ogma_handle_t ogma_handle + ) +{ + UINT16 Data; + + /* Get phy back to normal operation */ + Data =3D ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ~(1U << OGMA_PHY_CONTROL_REG_LOOPBACK); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) !=3D 0); + + Data |=3D (1U << OGMA_PHY_CONTROL_REG_RESET); + + /* Apply software reset */ + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_RESET)) !=3D 0); +} + ogma_err_t ogma_init ( void *base_addr, pfdep_dev_handle_t dev_handle, @@ -551,6 +605,17 @@ ogma_err_t ogma_init ( ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL, ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) -= 1) ); =20 + /* + * Do pre-initialization tasks for microengine + * + * In particular, we put phy in loopback mode + * in order to make sure RXCLK keeps provided to mac + * irrespective of phy link status, + * which is required for microengine intialization. + * This will be disabled once microengine initialization complete. + */ + ogma_pre_init_microengine (ctrl_p); + /* start microengines */ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0); =20 @@ -573,6 +638,13 @@ ogma_err_t ogma_init ( goto err; } =20 + /* + * Do post-initialization tasks for microengine + * + * We put phy in normal mode and apply reset. + */ + ogma_post_init_microengine (ctrl_p); + /* clear microcode load end status */ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS, OGMA_TOP_IRQ_REG_ME_START); diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_reg.h b/Silicon/Socionext/SynQuacer/Drivers/Net/Net= secDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h index 30c716352b37..ca769084cb31 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_reg.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_reg.h @@ -138,8 +138,12 @@ /* bit fields for PHY CONTROL Register */ #define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6) #define OGMA_PHY_CONTROL_REG_DUPLEX_MODE (8) +#define OGMA_PHY_CONTROL_REG_ISOLATE (10) +#define OGMA_PHY_CONTROL_REG_POWER_DOWN (11) #define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE (12) #define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13) +#define OGMA_PHY_CONTROL_REG_LOOPBACK (14) +#define OGMA_PHY_CONTROL_REG_RESET (15) =20 /* bit fields for PHY STATUS Register */ #define OGMA_PHY_STATUS_REG_LINK_STATUS (2) --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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