From nobody Wed May 1 20:04:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45167+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45167+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1565267029; cv=none; d=zoho.com; s=zohoarc; b=Qg5iOq89UC6IXKGsQ1v9aU1H73+y+aMvlbFfeU3kCoRKWyXA6CCJztZA5cduNe+tmiw+xCzJjL124GBWTZV1nTkGvNoaJf2Guvq1JWebqnBXN4eplP2cBGZ/Lc3G5jWZxbuElPI5TbuMwwlulPax4PTcBDwqhScJDmvbzFxUOCY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565267029; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=6+tfBvGFswWh4JQg07qHLGufDlh4bD3RGVNzOapKI1E=; b=aIxc+pNii5RLtEbtSzH6N0RsZQ8oUtjS3DgEDv7QabH2fA4B40TmeU/0cUJz2vRvp9Pedd7rKaJgofyyFEzZZORtc/sfjBOLA0yi0Od2GnEqBSTfvVlt5KtsXM8JicEg6MciTuiHBF45uH5qpbpFjKJ0b4W89lTUX8T2CI/36AQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45167+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156526702934711.756609253650936; Thu, 8 Aug 2019 05:23:49 -0700 (PDT) Return-Path: X-Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by groups.io with SMTP; Thu, 08 Aug 2019 05:23:48 -0700 X-Received: by mail-pf1-f195.google.com with SMTP id y15so44038347pfn.5 for ; Thu, 08 Aug 2019 05:23:48 -0700 (PDT) X-Gm-Message-State: APjAAAWZiIKpXeeU9yJZtHrpKHsROYIwa+PsZe16cKr3g3iRp+Nqs+tL sMqSUYZZRvPPeJ7WXlV2COyeET9FXyA= X-Google-Smtp-Source: APXvYqx2CKRtVg0nPVejRuOnHmu/bPxYW9PrCKYoS5XJfIUMzemp34Pkki9lKn5Tl1VZQrM8tmmPww== X-Received: by 2002:a17:90a:bb0c:: with SMTP id u12mr3886009pjr.132.1565267027659; Thu, 08 Aug 2019 05:23:47 -0700 (PDT) X-Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id t96sm2252190pjb.1.2019.08.08.05.23.46 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Aug 2019 05:23:46 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, okamoto.satoru@socionext.com, Masahisa Kojima Subject: [edk2-devel] [PATCH edk2-platforms v3 1/3] NetsecDxe: embed phy address into NETSEC SDK internal structure Date: Thu, 8 Aug 2019 21:23:33 +0900 Message-Id: <20190808122335.11883-2-masahisa.kojima@linaro.org> In-Reply-To: <20190808122335.11883-1-masahisa.kojima@linaro.org> References: <20190808122335.11883-1-masahisa.kojima@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,masahisa.kojima@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565267029; bh=XcAdjoZy1BF6yz9GyxzctKtNPpcWAp7PbGUWzPOMao0=; h=Cc:Date:From:Reply-To:Subject:To; b=jCnYrJNGlY310Zc+KaLSFZWPTGs/450IhsB55b9d391zojbAF3UZ5v+63jMXculI6Mc NjfDqXQIfVAcmO+wXQdwTbqppR+a4OxsBXXASSwDGPfazpkirL6DHeHbc4U5rZnTUtGQ3 SwLUFLtcBcZr+nNKcxO+6UTbdZ0raiNnPg0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Satoru Okamoto This is a refactoring of phy address handling in Netsec driver. NETSEC SDK, low level driver for NetsecDxe, did not store phy address. User should specify the phy address as an argument to the SDK public functions. It prevented NETSEC SDK from internally controlling phy, and it also bothers user application with phy address management. With that, we encapsulate the phy address into NETSEC SDK. Signed-off-by: Masahisa Kojima Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c = | 10 ++-- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h = | 2 - Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_s= dk/include/ogma_api.h | 6 +- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_s= dk/src/ogma_gmac_access.c | 61 +++++--------------- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_s= dk/src/ogma_internal.h | 2 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_s= dk/src/ogma_misc.c | 6 ++ 6 files changed, 28 insertions(+), 59 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c index 160bb08a4632..0b91d4af44a3 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c @@ -59,6 +59,8 @@ Probe ( // phy-interface Param.gmac_config.phy_interface =3D OGMA_PHY_INTERFACE_RGMII; =20 + Param.phy_addr =3D LanDriver->Dev->Resources[2].AddrRangeMin; + // Read and save the Permanent MAC Address EepromBase =3D LanDriver->Dev->Resources[1].AddrRangeMin; GetCurrentMacAddress (EepromBase, LanDriver->SnpMode.PermanentAddress.Ad= dr); @@ -107,8 +109,6 @@ Probe ( return EFI_DEVICE_ERROR; } =20 - LanDriver->PhyAddress =3D LanDriver->Dev->Resources[2].AddrRangeMin; - ogma_enable_top_irq (LanDriver->Handle, OGMA_TOP_IRQ_REG_NRM_RX | OGMA_TOP_IRQ_REG_NRM_TX); =20 @@ -280,7 +280,7 @@ SnpInitialize ( ReturnUnlock (EFI_DEVICE_ERROR); } =20 - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, LanDriver->Phy= Address, + ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, &phy_link_status); if (ogma_err !=3D OGMA_ERR_OK) { DEBUG ((DEBUG_ERROR, @@ -438,7 +438,7 @@ NetsecPollPhyStatus ( LanDriver =3D INSTANCE_FROM_SNP_THIS (Snp); =20 // Update the media status - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, LanDriver->Phy= Address, + ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, &phy_link_status); if (ogma_err !=3D OGMA_ERR_OK) { DEBUG ((DEBUG_ERROR, @@ -662,7 +662,7 @@ SnpGetStatus ( LanDriver =3D INSTANCE_FROM_SNP_THIS (Snp); =20 // Update the media status - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, LanDriver->Phy= Address, + ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, &phy_link_status); if (ogma_err !=3D OGMA_ERR_OK) { DEBUG ((DEBUG_ERROR, diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h = b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h index 870833c8d31c..c95ff215199d 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h @@ -70,8 +70,6 @@ typedef struct { NON_DISCOVERABLE_DEVICE *Dev; =20 NETSEC_DEVICE_PATH DevicePath; - - UINTN PhyAddress; } NETSEC_DRIVER; =20 #define NETSEC_SIGNATURE SIGNATURE_32('n', 't', 's', 'c') diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/include/ogma_api.h b/Silicon/Socionext/SynQuacer/Drivers/Net= /NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h index 66f39150430b..be80dd9ae1fd 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/include/ogma_api.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/include/ogma_api.h @@ -318,6 +318,7 @@ struct ogma_param_s{ ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1]; ogma_gmac_config_t gmac_config; ogma_uint8 mac_addr[6]; + ogma_uint8 phy_addr; }; =20 struct ogma_tx_pkt_ctrl_s{ @@ -412,14 +413,12 @@ ogma_err_t ogma_set_gmac_mode ( =20 void ogma_set_phy_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 reg_addr, ogma_uint16 value ); =20 ogma_uint16 ogma_get_phy_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 reg_addr ); =20 @@ -660,7 +659,6 @@ ogma_err_t ogma_get_gmac_lpitimer_reg ( =20 void ogma_set_phy_mmd_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr, ogma_uint16 value @@ -668,14 +666,12 @@ void ogma_set_phy_mmd_reg ( =20 ogma_uint16 ogma_get_phy_mmd_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ); =20 ogma_err_t ogma_get_phy_link_status ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_phy_link_status_t *phy_link_status_p ); =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_gmac_access.c b/Silicon/Socionext/SynQuacer/Drivers= /Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c index 88c149c10466..150d25ac3fbf 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_gmac_access.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_gmac_access.c @@ -40,14 +40,12 @@ **********************************************************************/ static void ogma_set_phy_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 reg_addr, ogma_uint16 value ); =20 static ogma_uint16 ogma_get_phy_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 reg_addr ); =20 @@ -57,14 +55,12 @@ void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p); =20 static void ogma_set_phy_target_mmd_reg_addr ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ); =20 static void ogma_set_phy_mmd_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr, ogma_uint16 value @@ -72,7 +68,6 @@ static void ogma_set_phy_mmd_reg_sub ( =20 static ogma_uint16 ogma_get_phy_mmd_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ); @@ -435,7 +430,6 @@ ogma_err_t ogma_set_gmac_mode ( =20 static void ogma_set_phy_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 reg_addr, ogma_uint16 value ) @@ -447,7 +441,7 @@ static void ogma_set_phy_reg_sub ( OGMA_GMAC_REG_ADDR_GDR, value); =20 - cmd =3D ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) | + cmd =3D ( ( ctrl_p->param.phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) | ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) | ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) | OGMA_GMAC_GAR_REG_GW | @@ -466,7 +460,6 @@ static void ogma_set_phy_reg_sub ( =20 void ogma_set_phy_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 reg_addr, ogma_uint16 value ) @@ -476,27 +469,25 @@ void ogma_set_phy_reg ( =20 if (( ctrl_p =3D=3D NULL) || ( !ctrl_p->param.use_gmac_flag) - || ( phy_addr >=3D 32) || ( reg_addr >=3D 32) ) { pfdep_print( PFDEP_DEBUG_LEVEL_FATAL, "An error occurred at ogma_set_phy_reg.\nPlease set v= alid argument.\n"); return; } =20 - ogma_set_phy_reg_sub( ctrl_p, phy_addr, reg_addr, value); + ogma_set_phy_reg_sub( ctrl_p, reg_addr, value); =20 } =20 static ogma_uint16 ogma_get_phy_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 reg_addr ) { =20 ogma_uint32 cmd; =20 - cmd =3D ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) | + cmd =3D ( ( ctrl_p->param.phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) | ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) | ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) | OGMA_GMAC_GAR_REG_GB); @@ -516,7 +507,6 @@ static ogma_uint16 ogma_get_phy_reg_sub ( =20 ogma_uint16 ogma_get_phy_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 reg_addr ) { @@ -525,14 +515,13 @@ ogma_uint16 ogma_get_phy_reg ( =20 if ( ( ctrl_p =3D=3D NULL) || ( !ctrl_p->param.use_gmac_flag) - || ( phy_addr >=3D 32) || ( reg_addr >=3D 32) ) { pfdep_print( PFDEP_DEBUG_LEVEL_FATAL, "An error occurred at ogma_get_phy_reg.\nPlease set v= alid argument.\n"); return 0; } =20 - value =3D ogma_get_phy_reg_sub(ctrl_p, phy_addr, reg_addr); + value =3D ogma_get_phy_reg_sub(ctrl_p, reg_addr); =20 =20 return value; @@ -702,7 +691,6 @@ ogma_err_t ogma_get_gmac_status ( =20 static void ogma_set_phy_target_mmd_reg_addr ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ) @@ -713,21 +701,20 @@ static void ogma_set_phy_target_mmd_reg_addr ( cmd =3D ( ogma_uint32)dev_addr; =20 /*set command to MMD access control register */ - ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd); + ogma_set_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AC, cmd); =20 /* set MMD access address data register Write reg_addr */ - ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, reg= _addr); + ogma_set_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AAD, reg_addr); =20 /* write value to MMD ADDR */ cmd =3D ( (1U << 14) | dev_addr); =20 /* set command to MMD access control register */ - ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd); + ogma_set_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AC, cmd); } =20 static void ogma_set_phy_mmd_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr, ogma_uint16 value @@ -735,30 +722,27 @@ static void ogma_set_phy_mmd_reg_sub ( { /* set target mmd reg_addr */ ogma_set_phy_target_mmd_reg_addr( ctrl_p, - phy_addr, dev_addr, reg_addr); =20 /* Write value to MMD access address data register */ - ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, val= ue); + ogma_set_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AAD, value); =20 } =20 static ogma_uint16 ogma_get_phy_mmd_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ) { /* set target mmd reg_addr */ ogma_set_phy_target_mmd_reg_addr( ctrl_p, - phy_addr, dev_addr, reg_addr); =20 /* Read value for MMD access address data register */ - return ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_A= AD); + return ogma_get_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AAD); } =20 ogma_err_t ogma_set_gmac_lpictrl_reg ( @@ -878,7 +862,6 @@ ogma_err_t ogma_get_gmac_lpitimer_reg ( =20 void ogma_set_phy_mmd_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr, ogma_uint16 value @@ -890,8 +873,7 @@ void ogma_set_phy_mmd_reg ( return; } =20 - if ( ( phy_addr > 31U) || - ( dev_addr > 31U) ) { + if ( dev_addr > 31U) { return; } =20 @@ -900,7 +882,6 @@ void ogma_set_phy_mmd_reg ( } =20 ogma_set_phy_mmd_reg_sub ( ctrl_p, - phy_addr, dev_addr, reg_addr, value); @@ -911,7 +892,6 @@ void ogma_set_phy_mmd_reg ( =20 ogma_uint16 ogma_get_phy_mmd_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ) @@ -923,8 +903,7 @@ ogma_uint16 ogma_get_phy_mmd_reg ( return 0; } =20 - if ( ( phy_addr > 31U) || - ( dev_addr > 31U) ) { + if ( dev_addr > 31U) { return 0; } =20 @@ -933,7 +912,6 @@ ogma_uint16 ogma_get_phy_mmd_reg ( } =20 value =3D ogma_get_phy_mmd_reg_sub ( ctrl_p, - phy_addr, dev_addr, reg_addr); =20 @@ -943,7 +921,6 @@ ogma_uint16 ogma_get_phy_mmd_reg ( =20 ogma_err_t ogma_get_phy_link_status ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_phy_link_status_t *phy_link_status_p ) { @@ -955,10 +932,6 @@ ogma_err_t ogma_get_phy_link_status ( return OGMA_ERR_PARAM; } =20 - if ( phy_addr >=3D 32) { - return OGMA_ERR_RANGE; - } - if ( !ctrl_p->param.use_gmac_flag) { return OGMA_ERR_NOTAVAIL; } @@ -966,17 +939,17 @@ ogma_err_t ogma_get_phy_link_status ( pfdep_memset( phy_link_status_p, 0, sizeof( ogma_phy_link_status_t) ); =20 /* Read PHY CONTROL Register */ - tmp =3D ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_CONT= ROL); + tmp =3D ogma_get_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_CONTROL); =20 /* Read PHY STATUS Register */ - value =3D ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_ST= ATUS); + value =3D ogma_get_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_STATUS); =20 /* check latched_link_down_flag */ if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) =3D=3D 0) { phy_link_status_p->latched_link_down_flag =3D OGMA_TRUE; =20 /* Read PHY STATUS Register */ - value =3D ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADD= R_STATUS); + value =3D ogma_get_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_STATUS); =20 } =20 @@ -1036,12 +1009,10 @@ ogma_err_t ogma_get_phy_link_status ( =20 /* Read MASTER-SLAVE Control Register */ value =3D ogma_get_phy_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_REG_ADDR_MASTER_SLAVE_C= ONTROL); =20 /* Read MASTER-SLAVE Status Register */ tmp =3D ogma_get_phy_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_REG_ADDR_MASTER_SLAVE_STA= TUS); =20 /* Check Current Link Speed */ @@ -1061,12 +1032,10 @@ ogma_err_t ogma_get_phy_link_status ( =20 /* Read Auto-Negotiation Advertisement register */ value =3D ogma_get_phy_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_REG_ADDR_AUTO_NEGO_= ABILTY); =20 /* Read Auto-Negotiation Link Partner Base Page Ability re= gister */ tmp =3D ogma_get_phy_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_REG_ADDR_AUTO_NEGO_L= INK_PATNER_ABILTY); =20 value =3D ( ( ( value & tmp) >> OGMA_PHY_ANA_REG_TAF) & @@ -1109,13 +1078,11 @@ ogma_err_t ogma_get_phy_link_status ( =20 /* Read EEE advertisement register */ value =3D ogma_get_phy_mmd_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_DEV_ADDR_AUTO_NEGO, OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_= ADVERTISE); =20 /* Read EEE link partner ability register */ tmp =3D ogma_get_phy_mmd_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_DEV_ADDR_AUTO_NEGO, OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP= _ABILITY); =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_internal.h b/Silicon/Socionext/SynQuacer/Drivers/Ne= t/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h index ed09a7ada85d..a7bc69cf0777 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_internal.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_internal.h @@ -111,6 +111,8 @@ struct ogma_ctrl_s{ =20 pfdep_phys_addr_t dummy_desc_entry_phys_addr; =20 + ogma_uint8 phy_addr; + #ifdef OGMA_CONFIG_REC_STAT /** * Statistics information. diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/SynQuacer/Drivers/Net/Ne= tsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c index 4dec66313aa1..7481d2da2d24 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_misc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_misc.c @@ -388,6 +388,12 @@ ogma_err_t ogma_init ( return OGMA_ERR_DATA; } =20 + if ( param_p->phy_addr >=3D 32) { + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL, + "Error: phy_addr out of range\n"); + return OGMA_ERR_DATA; + } + ogma_err =3D ogma_probe_hardware( base_addr); =20 if ( ogma_err !=3D OGMA_ERR_OK) { --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45167): https://edk2.groups.io/g/devel/message/45167 Mute This Topic: https://groups.io/mt/32797722/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 20:04:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45168+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45168+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1565267035; cv=none; d=zoho.com; s=zohoarc; b=lWIyIaMtWwlpsmhqF+siqCH6I8lraukGy3FRbgXDw3ETC4/+n8UUTrNTcMVN5jCRlqTGTu6L54WrHaEn7r5eUu9VMx+VPapIiuaxMz2KEetf5yRaNzoXI9el1Rh30N6/Vnc0Ezdhyw0BeFJFyVMqbtauevP8vd3HbUxjD0pzWn0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565267035; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=VqN9zbQUxzVaKX9WGp6e5XRNxXS1Dv4BUkupgZbBHvk=; b=nZDsSUPJkBJrbXaQ4BhxHqkWhPeIdixiPt5K8BxFkqmRxzKBTCE7Zk9l8wOieQw7ZaaRSLzK2kJI+ATglX32SsEdL92N/5gMGqSDnQPhQYXghqEqjIIL29w/jBKCWOp0MgoDbzzmS/1Hz2vKEOLmhXkMc1WUGXmg6/a4LW4H3rI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45168+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565267034987574.0030214990504; Thu, 8 Aug 2019 05:23:54 -0700 (PDT) Return-Path: X-Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by groups.io with SMTP; Thu, 08 Aug 2019 05:23:54 -0700 X-Received: by mail-pf1-f196.google.com with SMTP id r1so44014590pfq.12 for ; Thu, 08 Aug 2019 05:23:54 -0700 (PDT) X-Gm-Message-State: APjAAAWtLXplMJJS3DXCOowWuU9ODv2lEPZuQJblHUYoUdjiHWKltBBf kWC6GY94KXkt+mfzrjVRW7my8f9N74U= X-Google-Smtp-Source: APXvYqxjGL+Kd2uyttXPZ3l4zlWtyJEtyS6A13OUuUEVNHS66znudjmmKpZP268dbJqe+NEwoBgnKg== X-Received: by 2002:a63:a66:: with SMTP id z38mr12891885pgk.247.1565267033160; Thu, 08 Aug 2019 05:23:53 -0700 (PDT) X-Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id f88sm2195424pjg.5.2019.08.08.05.23.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Aug 2019 05:23:52 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, okamoto.satoru@socionext.com, Masahisa Kojima Subject: [edk2-devel] [PATCH edk2-platforms v3 2/3] NetsecDxe: put phy in loopback mode to guarantee stable RXCLK input Date: Thu, 8 Aug 2019 21:23:34 +0900 Message-Id: <20190808122335.11883-3-masahisa.kojima@linaro.org> In-Reply-To: <20190808122335.11883-1-masahisa.kojima@linaro.org> References: <20190808122335.11883-1-masahisa.kojima@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,masahisa.kojima@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565267034; bh=ExDlT+0oUM9yaguSQc8M+3obSbIUsXil9che787qVH4=; h=Cc:Date:From:Reply-To:Subject:To; b=nqmojdEZW/A9vhlMXvzw1pJ73d8urJDTuKecjuQvegvXzMFjvIWwALq29eWHIHkCZv9 STdzSGI9nYYPQImZF5q7q13LIYXU0lbvTEKv9EagyXhv6AgZK9Vf5ZLgC5HNK0J8wUgnD LA1HmlYYPpvM0KhXK8BkSnwcBT+Oaq+U5jA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Satoru Okamoto NETSEC hardware requires stable RXCLK input upon initialization triggered with DISCORE =3D 0. However, RXCLK input could be unstable depending on phy chipset and deployed network environment, which could cause NETSEC to hang up during initialization. We solve this platform/environment dependent issue by temporarily putting phy in loopback mode, then we can expect the stable RXCLK input. Signed-off-by: Masahisa Kojima Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_s= dk/src/ogma_misc.c | 72 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/netsec_s= dk/src/ogma_reg.h | 4 ++ 2 files changed, 76 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/SynQuacer/Drivers/Net/Ne= tsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c index 7481d2da2d24..5f6ddc0c745e 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_misc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_misc.c @@ -327,6 +327,60 @@ STATIC ogma_uint32 ogma_calc_pkt_ctrl_reg_param ( return param; } =20 +STATIC +void +ogma_pre_init_microengine ( + ogma_handle_t ogma_handle + ) +{ + UINT16 Data; + + /* Remove dormant settings */ + Data =3D ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ~((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) | + (1U << OGMA_PHY_CONTROL_REG_ISOLATE)); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ((1U << OGMA_PHY_CONTROL_REG_POWER_DOWN) | + (1U << OGMA_PHY_CONTROL_REG_ISOLATE))) !=3D 0); + + /* Put phy in loopback mode to guarantee RXCLK input */ + Data |=3D (1U << OGMA_PHY_CONTROL_REG_LOOPBACK); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) =3D=3D 0); +} + +STATIC +void +ogma_post_init_microengine ( + IN ogma_handle_t ogma_handle + ) +{ + UINT16 Data; + + /* Get phy back to normal operation */ + Data =3D ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + ~(1U << OGMA_PHY_CONTROL_REG_LOOPBACK); + + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_LOOPBACK)) !=3D 0); + + Data |=3D (1U << OGMA_PHY_CONTROL_REG_RESET); + + /* Apply software reset */ + ogma_set_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL, Data); + + while ((ogma_get_phy_reg (ogma_handle, OGMA_PHY_REG_ADDR_CONTROL) & + (1U << OGMA_PHY_CONTROL_REG_RESET)) !=3D 0); +} + ogma_err_t ogma_init ( void *base_addr, pfdep_dev_handle_t dev_handle, @@ -551,6 +605,17 @@ ogma_err_t ogma_init ( ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DMA_TMR_CTRL, ( ogma_uint32)( ( OGMA_CONFIG_CLK_HZ / OGMA_CLK_MHZ) -= 1) ); =20 + /* + * Do pre-initialization tasks for microengine + * + * In particular, we put phy in loopback mode + * in order to make sure RXCLK keeps provided to mac + * irrespective of phy link status, + * which is required for microengine intialization. + * This will be disabled once microengine initialization complete. + */ + ogma_pre_init_microengine (ctrl_p); + /* start microengines */ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_DIS_CORE, 0); =20 @@ -573,6 +638,13 @@ ogma_err_t ogma_init ( goto err; } =20 + /* + * Do post-initialization tasks for microengine + * + * We put phy in normal mode and apply reset. + */ + ogma_post_init_microengine (ctrl_p); + /* clear microcode load end status */ ogma_write_reg( ctrl_p, OGMA_REG_ADDR_TOP_STATUS, OGMA_TOP_IRQ_REG_ME_START); diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_reg.h b/Silicon/Socionext/SynQuacer/Drivers/Net/Net= secDxe/netsec_for_uefi/netsec_sdk/src/ogma_reg.h index 30c716352b37..ca769084cb31 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_reg.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_reg.h @@ -138,8 +138,12 @@ /* bit fields for PHY CONTROL Register */ #define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_MSB (6) #define OGMA_PHY_CONTROL_REG_DUPLEX_MODE (8) +#define OGMA_PHY_CONTROL_REG_ISOLATE (10) +#define OGMA_PHY_CONTROL_REG_POWER_DOWN (11) #define OGMA_PHY_CONTROL_REG_AUTO_NEGO_ENABLE (12) #define OGMA_PHY_CONTROL_REG_SPEED_SELECTION_LSB (13) +#define OGMA_PHY_CONTROL_REG_LOOPBACK (14) +#define OGMA_PHY_CONTROL_REG_RESET (15) =20 /* bit fields for PHY STATUS Register */ #define OGMA_PHY_STATUS_REG_LINK_STATUS (2) --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45168): https://edk2.groups.io/g/devel/message/45168 Mute This Topic: https://groups.io/mt/32797724/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Wed May 1 20:04:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45169+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45169+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1565267041; cv=none; d=zoho.com; s=zohoarc; b=RqmiIul0TTiaJ5m4z3VSSY82jE1AdM5zT31CCmbKI6abSwcrPW+xnkrs1m6iUd8kn81MFr7q/R/th/s1n2ClK7cWmve22pjkyveYdFhqyG/lyCgl9U7yqrhwcNw382HqBbCVf0U3kcqHhSxqYWiM3Z18+ktbWphvE1tl3lGsx9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565267041; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=hbBQ+AcUb3U2Gjfa0QTrDAslzuf5LbCdVGGkeEnAHkU=; b=LcPRpE0ZTazwOH5tfCXNUHdTY+olAlkr6SmMPKmjyXXo9GQOiHge3A1vqbMH9G3/6p89SpE0TLSGFDJRxkVSdKK6yCs3zUnJX4HuhuFQ/CEfWDWlcbWMtNRQ463q5Z9A2QoRtBssrfd8FKowTj8e1Aw3IdzI9RLiFekul+h5Z5s= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45169+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15652670410718.336093853837497; Thu, 8 Aug 2019 05:24:01 -0700 (PDT) Return-Path: X-Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by groups.io with SMTP; Thu, 08 Aug 2019 05:24:00 -0700 X-Received: by mail-pf1-f195.google.com with SMTP id r7so44025362pfl.3 for ; Thu, 08 Aug 2019 05:24:00 -0700 (PDT) X-Gm-Message-State: APjAAAXOTkyRpfo4w8vEeb9UcZf3pt+/djLfgcuz4UA/V+NQ7SmZXgaa +Hh/ijVM4wZ73nBQUNrFtbUuFhyMZME= X-Google-Smtp-Source: APXvYqzcby6ugftDRkcsbu665OZmCa+XK3FnDJhPVsIxbKyip5JbMQ9afVwSXsZQj5gVd0Zy1+ybAA== X-Received: by 2002:a17:90a:ad86:: with SMTP id s6mr3897549pjq.42.1565267039421; Thu, 08 Aug 2019 05:23:59 -0700 (PDT) X-Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id z13sm96314905pfa.94.2019.08.08.05.23.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 08 Aug 2019 05:23:58 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, okamoto.satoru@socionext.com, Masahisa Kojima Subject: [edk2-devel] [PATCH edk2-platforms v3 3/3] NetsecDxe: SnpInitialize() waits for media linking up Date: Thu, 8 Aug 2019 21:23:35 +0900 Message-Id: <20190808122335.11883-4-masahisa.kojima@linaro.org> In-Reply-To: <20190808122335.11883-1-masahisa.kojima@linaro.org> References: <20190808122335.11883-1-masahisa.kojima@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,masahisa.kojima@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565267040; bh=epZUt2muoJC7HedzHoCY3DDreJHlivRsMJmdElzSeGE=; h=Cc:Date:From:Reply-To:Subject:To; b=bsrLL5c7bfojOkShhP2vq9/lYwxP88M8DgqsZ1iB5KGNBS9ENdFXu85HCX0nv8Lj3aP sVdyNYXGpAevjiN2Cc0m/6zLbkqnIQuv5S0ZqdWzhnaJpWkGhSExzb7rxGgFZdGYSI3/k ERbR600j463MGK4+gUnzZFZm3N1u+0VbSCA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Satoru Okamoto The latest NetsecDxe requires issueing phy reset at the last stage of initialization to safely exit loopback mode. However, as a result, it takes a couple of seconds for link state to get stable, which could cause auto-chosen pxeboot to fail due to MediaPresent check error. This patch adds link state check with 5s timeout in NetsecDxe initialization. The timeout value can be adjustable via configuration file. Signed-off-by: Masahisa Kojima Reviewed-by: Leif Lindholm --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 1 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c | 232 ++++= +++++----------- Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec | 1 + Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf | 1 + 4 files changed, 110 insertions(+), 125 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index 97fb8c410c60..9f8cb68cdd26 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -137,6 +137,7 @@ [PcdsFixedAtBuild] gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0 gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|36 gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|48 + gNetsecDxeTokenSpaceGuid.PcdMediaDetectTimeoutOnBoot|5 gNetsecDxeTokenSpaceGuid.PcdPauseTime|256 =20 gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase|0x08080000 diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c index 0b91d4af44a3..a304e02208fa 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c @@ -169,6 +169,98 @@ ExitUnlock: return Status; } =20 +EFI_STATUS +EFIAPI +NetsecUpdateLink ( + IN EFI_SIMPLE_NETWORK_PROTOCOL *Snp + ) +{ + NETSEC_DRIVER *LanDriver; + ogma_phy_link_status_t phy_link_status; + ogma_gmac_mode_t ogma_gmac_mode; + ogma_err_t ogma_err; + BOOLEAN ValidFlag; + ogma_gmac_mode_t GmacMode; + BOOLEAN RxRunningFlag; + BOOLEAN TxRunningFlag; + EFI_STATUS ErrorStatus; + + LanDriver =3D INSTANCE_FROM_SNP_THIS (Snp); + + // Update the media status + ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, + &phy_link_status); + if (ogma_err !=3D OGMA_ERR_OK) { + DEBUG ((DEBUG_ERROR, + "NETSEC: ogma_get_phy_link_status failed with error code: %d\n", + (INT32)ogma_err)); + ErrorStatus =3D EFI_DEVICE_ERROR; + goto Fail; + } + + // Update the GMAC status + ogma_err =3D ogma_get_gmac_status (LanDriver->Handle, &ValidFlag, &GmacM= ode, + &RxRunningFlag, &TxRunningFlag); + if (ogma_err !=3D OGMA_ERR_OK) { + DEBUG ((DEBUG_ERROR, + "NETSEC: ogma_get_gmac_status failed with error code: %d\n", + (INT32)ogma_err)); + ErrorStatus =3D EFI_DEVICE_ERROR; + goto Fail; + } + + // Stop GMAC when GMAC is running and physical link is down + if (RxRunningFlag && TxRunningFlag && !phy_link_status.up_flag) { + ogma_err =3D ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE); + if (ogma_err !=3D OGMA_ERR_OK) { + DEBUG ((DEBUG_ERROR, + "NETSEC: ogma_stop_gmac() failed with error status %d\n", + ogma_err)); + ErrorStatus =3D EFI_DEVICE_ERROR; + goto Fail; + } + } + + // Start GMAC when GMAC is stopped and physical link is up + if (!RxRunningFlag && !TxRunningFlag && phy_link_status.up_flag) { + ZeroMem (&ogma_gmac_mode, sizeof (ogma_gmac_mode_t)); + ogma_gmac_mode.link_speed =3D phy_link_status.link_speed; + ogma_gmac_mode.half_duplex_flag =3D (ogma_bool)phy_link_status.half_du= plex_flag; + if (!phy_link_status.half_duplex_flag && FixedPcdGet8 (PcdFlowCtrl)) { + ogma_gmac_mode.flow_ctrl_enable_flag =3D FixedPcdGet8 (PcdFlowCt= rl); + ogma_gmac_mode.flow_ctrl_start_threshold =3D FixedPcdGet16 (PcdFlowC= trlStartThreshold); + ogma_gmac_mode.flow_ctrl_stop_threshold =3D FixedPcdGet16 (PcdFlowC= trlStopThreshold); + ogma_gmac_mode.pause_time =3D FixedPcdGet16 (PcdPause= Time); + } + + ogma_err =3D ogma_set_gmac_mode (LanDriver->Handle, &ogma_gmac_mode); + if (ogma_err !=3D OGMA_ERR_OK) { + DEBUG ((DEBUG_ERROR, + "NETSEC: ogma_set_gmac() failed with error status %d\n", + (INT32)ogma_err)); + ErrorStatus =3D EFI_DEVICE_ERROR; + goto Fail; + } + + ogma_err =3D ogma_start_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE); + if (ogma_err !=3D OGMA_ERR_OK) { + DEBUG ((DEBUG_ERROR, + "NETSEC: ogma_start_gmac() failed with error status %d\n", + (INT32)ogma_err)); + ErrorStatus =3D EFI_DEVICE_ERROR; + goto Fail; + } + } + + /* Updating link status for external guery */ + Snp->Mode->MediaPresent =3D phy_link_status.up_flag; + return EFI_SUCCESS; + +Fail: + Snp->Mode->MediaPresent =3D FALSE; + return ErrorStatus; +} + /* * UEFI Initialize() function */ @@ -185,9 +277,9 @@ SnpInitialize ( EFI_TPL SavedTpl; EFI_STATUS Status; =20 - ogma_phy_link_status_t phy_link_status; ogma_err_t ogma_err; - ogma_gmac_mode_t ogma_gmac_mode; + + UINT32 Index; =20 // Check Snp Instance if (Snp =3D=3D NULL) { @@ -271,48 +363,18 @@ SnpInitialize ( ogma_disable_desc_ring_irq (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX, OGMA_CH_IRQ_REG_EMPTY); =20 - // Stop and restart the physical link - ogma_err =3D ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_stop_gmac() failed with error status %d\n", - ogma_err)); - ReturnUnlock (EFI_DEVICE_ERROR); - } - - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, - &phy_link_status); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_get_phy_link_status() failed error code %d\n", - (INT32)ogma_err)); - ReturnUnlock (EFI_DEVICE_ERROR); - } - - SetMem (&ogma_gmac_mode, sizeof (ogma_gmac_mode_t), 0); - ogma_gmac_mode.link_speed =3D phy_link_status.link_speed; - ogma_gmac_mode.half_duplex_flag =3D (ogma_bool)phy_link_status.half_dupl= ex_flag; - if ((!phy_link_status.half_duplex_flag) && FixedPcdGet8 (PcdFlowCtrl)) { - ogma_gmac_mode.flow_ctrl_enable_flag =3D FixedPcdGet8 (PcdFlowCtrl= ); - ogma_gmac_mode.flow_ctrl_start_threshold =3D FixedPcdGet16 (PcdFlowCtr= lStartThreshold); - ogma_gmac_mode.flow_ctrl_stop_threshold =3D FixedPcdGet16 (PcdFlowCtr= lStopThreshold); - ogma_gmac_mode.pause_time =3D FixedPcdGet16 (PcdPauseTi= me); - } - - ogma_err =3D ogma_set_gmac_mode (LanDriver->Handle, &ogma_gmac_mode); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_set_gmac() failed with error status %d\n", - (INT32)ogma_err)); - ReturnUnlock (EFI_DEVICE_ERROR); - } - - ogma_err =3D ogma_start_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_start_gmac() failed with error status %d\n", - (INT32)ogma_err)); - ReturnUnlock (EFI_DEVICE_ERROR); + // Wait for media linking up + for (Index =3D 0; Index < (UINT32)FixedPcdGet8 (PcdMediaDetectTimeoutOnB= oot) * 10; Index++) { + Status =3D NetsecUpdateLink (Snp); + if (Status !=3D EFI_SUCCESS) { + ReturnUnlock (EFI_DEVICE_ERROR); + } + + if (Snp->Mode->MediaPresent) { + break; + } + + MicroSecondDelay(100000); } =20 // Declare the driver as initialized @@ -420,14 +482,6 @@ NetsecPollPhyStatus ( ) { EFI_SIMPLE_NETWORK_PROTOCOL *Snp; - NETSEC_DRIVER *LanDriver; - ogma_phy_link_status_t phy_link_status; - ogma_gmac_mode_t ogma_gmac_mode; - ogma_err_t ogma_err; - BOOLEAN ValidFlag; - ogma_gmac_mode_t GmacMode; - BOOLEAN RxRunningFlag; - BOOLEAN TxRunningFlag; =20 Snp =3D (EFI_SIMPLE_NETWORK_PROTOCOL *)Context; if (Snp =3D=3D NULL) { @@ -435,66 +489,7 @@ NetsecPollPhyStatus ( return; } =20 - LanDriver =3D INSTANCE_FROM_SNP_THIS (Snp); - - // Update the media status - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, - &phy_link_status); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_get_phy_link_status failed with error code: %d\n", - (INT32)ogma_err)); - return; - } - - // Update the GMAC status - ogma_err =3D ogma_get_gmac_status (LanDriver->Handle, &ValidFlag, &GmacM= ode, - &RxRunningFlag, &TxRunningFlag); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_get_gmac_status failed with error code: %d\n", - (INT32)ogma_err)); - return; - } - - // Stop GMAC when GMAC is running and physical link is down - if (RxRunningFlag && TxRunningFlag && !phy_link_status.up_flag) { - ogma_err =3D ogma_stop_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_stop_gmac() failed with error status %d\n", - ogma_err)); - return; - } - } - - // Start GMAC when GMAC is stopped and physical link is up - if (!RxRunningFlag && !TxRunningFlag && phy_link_status.up_flag) { - ZeroMem (&ogma_gmac_mode, sizeof (ogma_gmac_mode_t)); - ogma_gmac_mode.link_speed =3D phy_link_status.link_speed; - ogma_gmac_mode.half_duplex_flag =3D (ogma_bool)phy_link_status.half_du= plex_flag; - if (!phy_link_status.half_duplex_flag && FixedPcdGet8 (PcdFlowCtrl)) { - ogma_gmac_mode.flow_ctrl_enable_flag =3D FixedPcdGet8 (PcdFlowCt= rl); - ogma_gmac_mode.flow_ctrl_start_threshold =3D FixedPcdGet16 (PcdFlowC= trlStartThreshold); - ogma_gmac_mode.flow_ctrl_stop_threshold =3D FixedPcdGet16 (PcdFlowC= trlStopThreshold); - ogma_gmac_mode.pause_time =3D FixedPcdGet16 (PcdPause= Time); - } - - ogma_err =3D ogma_set_gmac_mode (LanDriver->Handle, &ogma_gmac_mode); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_set_gmac() failed with error status %d\n", - (INT32)ogma_err)); - return; - } - - ogma_err =3D ogma_start_gmac (LanDriver->Handle, OGMA_TRUE, OGMA_TRUE); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_start_gmac() failed with error status %d\n", - (INT32)ogma_err)); - } - } + NetsecUpdateLink (Snp); } =20 /* @@ -631,7 +626,6 @@ SnpGetStatus ( pfdep_pkt_handle_t pkt_handle; LIST_ENTRY *Link; =20 - ogma_phy_link_status_t phy_link_status; ogma_err_t ogma_err; =20 // Check preliminaries @@ -661,18 +655,6 @@ SnpGetStatus ( // Find the LanDriver structure LanDriver =3D INSTANCE_FROM_SNP_THIS (Snp); =20 - // Update the media status - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, - &phy_link_status); - if (ogma_err !=3D OGMA_ERR_OK) { - DEBUG ((DEBUG_ERROR, - "NETSEC: ogma_get_phy_link_status failed with error code: %d\n", - (INT32)ogma_err)); - ReturnUnlock (EFI_DEVICE_ERROR); - } - - Snp->Mode->MediaPresent =3D phy_link_status.up_flag; - ogma_err =3D ogma_clean_tx_desc_ring (LanDriver->Handle, OGMA_DESC_RING_ID_NRM_TX); =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.de= c b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec index 6b9f60293879..3b1de62c6e31 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec @@ -37,4 +37,5 @@ [PcdsFixedAtBuild.common] gNetsecDxeTokenSpaceGuid.PcdFlowCtrl|0x0|UINT8|0x00000005 gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold|0x0|UINT16|0x00000006 gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold|0x0|UINT16|0x00000007 + gNetsecDxeTokenSpaceGuid.PcdMediaDetectTimeoutOnBoot|0x0|UINT8|0x00000009 gNetsecDxeTokenSpaceGuid.PcdPauseTime|0x0|UINT16|0x00000008 diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf index 49dd28efc65b..0fb06ba80bf4 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.inf @@ -61,4 +61,5 @@ [FixedPcd] gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStartThreshold gNetsecDxeTokenSpaceGuid.PcdFlowCtrlStopThreshold gNetsecDxeTokenSpaceGuid.PcdJumboPacket + gNetsecDxeTokenSpaceGuid.PcdMediaDetectTimeoutOnBoot gNetsecDxeTokenSpaceGuid.PcdPauseTime --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45169): https://edk2.groups.io/g/devel/message/45169 Mute This Topic: https://groups.io/mt/32797725/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-