From nobody Mon Apr 29 20:19:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+45212+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45212+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1565287094; cv=none; d=zoho.com; s=zohoarc; b=Bb17g+ONI3T7kTk7kOJ34mZmFgE/GW6fa9VIR57A9/S0Qlz2r5yITwU0JnspA0V352uNUY9imSEHOAPzEB6Tv5/Q4OYWzR4ZGmaD62couE1sIqdhis17oV0ZlfwdY5cjYc8pkaTLy4ePLVX1QQjXW5SCLkA4jcUkUAozPgi5KBg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1565287094; h=Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=b1S+M/GALK5Ljdim6KUDXp/KBMr3fa3TweNube7D/Bg=; b=E0MnY7AJZtr7pIsJASmODmAbRwGxzG5IvMIvZj9fiDIjTLcM3UXRzaHdH8K7jwo+8FTW/iSxNwvdFSrAYGLm83+Rwbg6rXCiC8jRNpVx2ZDtfKw+wHTgtLLvuf0JRr7QKMspGMQIOqsLDfYxDMp7pj6VLgdtvRBhCogM1Z6BleU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+45212+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1565287094095350.54933348628924; Thu, 8 Aug 2019 10:58:14 -0700 (PDT) Return-Path: X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by groups.io with SMTP; Wed, 07 Aug 2019 14:48:52 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 07 Aug 2019 14:48:52 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,358,1559545200"; d="scan'208";a="186140931" X-Received: from iwenevel-dev01.amr.corp.intel.com ([10.9.70.66]) by orsmga002.jf.intel.com with ESMTP; 07 Aug 2019 14:48:52 -0700 From: Evelyn Wang To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH] Extened PMR feature: allow silicon code to adjust PLMR/PHMR region base on the project needs Date: Wed, 7 Aug 2019 14:48:48 -0700 Message-Id: <20190807214848.7592-1-iwen.evelyn.wang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,iwen.evelyn.wang@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1565287093; bh=Uo8YSRAu06RiSN1LwdYQgX4KwB/xwsqCZm6fIpH5kTU=; h=Date:From:Reply-To:Subject:To; b=knBR673XkSr94GNfvBQteZOLP1kk2Q0pi3PXaM12SFS+5zg/DosEMwoFeRQXtdZdBD3 DyenrH44LgSMnLm/+OpOFAUSvEHRlybvpVuFop0A01bGQI36cPF3e+nkYMqkbWRWaQ1Jq 35vVKdp2PosUVIkECyA8hnrwhHxZ5YE2tpw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1770 1) IOMMU PMR feature should be generic to support different hardware archit= ecture. Some platforms may request no overlap between PMR regions and system reserv= e memory regions. Create an interface to control PLMR/PHMR regions. 2) DisableDMAr Function Code Optimization Currently, DisableDMAr flow functional-wise has no issues. However, it will= be great if we can optimize the flow to follow the VT-d spec requirements. 3) Renamed InitDmar() to InitGlobalVtd() The oringal function name is misleading Change-Id: Ia80394183522f7a4a921a75a1fa6e3779053d4eb Cc: Cc: Signed-off-by: Reviewed-by: --- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c | = 28 ++++++++++++++++++++++++++-- IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | = 76 ++++++++++++++++++++++++++++++++++++++++++++++++++---------------------= ----- IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf | = 5 ++++- IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c | = 27 +++++++++++++++++++++++++-- IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h | = 31 +++++++++++++++++++++++++++++++ IntelSiliconPkg/Include/SysMemInfoHob.h | = 28 ++++++++++++++++++++++++++++ IntelSiliconPkg/IntelSiliconPkg.dec | = 4 +++- IntelSiliconPkg/IntelSiliconPkg.dsc | = 3 ++- IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c | = 170 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++ IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.inf | = 38 ++++++++++++++++++++++++++++++++++++++ 10 files changed, 377 insertions(+), 33 deletions(-) diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c b/IntelSilico= nPkg/Feature/VTd/IntelVTdDxe/VtdReg.c index 8dbc83fa2d..6a66a860b4 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License which accompanies this distribution. The full text of the license may b= e found at @@ -315,6 +315,8 @@ DisableDmar ( UINTN Index; UINTN SubIndex; UINT32 Reg32; + UINT32 Status; + UINT32 Command; =20 for (Index =3D 0; Index < mVtdUnitNumber; Index++) { DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index)); @@ -327,7 +329,29 @@ DisableDmar ( // // Disable VTd // - MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, B_GMCD_REG_SRTP); + // + // Set TE (Translation Enable: BIT31) of Global command register to ze= ro + // + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & ~B_GMCD_REG_TE); + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); + + // + // Poll on TE Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + + // + // Set SRTP (Set Root Table Pointer: BIT30) of Global command register= in order to update the root table pointerDisable VTd + // + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | B_GMCD_REG_SRTP); + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, Command); + do { Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c b/= IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c index 27847f4331..c8a2cae5ff 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distr= ibution. @@ -26,7 +26,7 @@ #include #include #include - +#include #include "IntelVTdPmrPei.h" =20 EFI_GUID mVTdInfoGuid =3D { @@ -430,38 +430,65 @@ InitDmaProtection ( UINTN MemoryAlignment; UINTN LowBottom; UINTN LowTop; - UINTN HighBottom; + UINT64 HighBottom; UINT64 HighTop; DMA_BUFFER_INFO *DmaBufferInfo; VOID *Hob; EFI_PEI_PPI_DESCRIPTOR *OldDescriptor; EDKII_IOMMU_PPI *OldIoMmuPpi; + SYSTEM_MEM_INFO_HOB *SysMemHob; + VOID *SysMemHobPtr; =20 Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); - - DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferS= ize)); - - LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo->EngineMa= sk); - HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo->Engine= Mask); - if (LowMemoryAlignment < HighMemoryAlignment) { - MemoryAlignment =3D (UINTN)HighMemoryAlignment; + =20 + SysMemHobPtr =3D GetFirstGuidHob (&gSysMemInfoDataHobGuid); + =20 + if (SysMemHobPtr =3D=3D NULL) { + // + // Calcuate the PMR memory alignment + // + LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo->Engi= neMask); + HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo->En= gineMask); + if (LowMemoryAlignment < HighMemoryAlignment) { + MemoryAlignment =3D (UINTN)HighMemoryAlignment; + } else { + MemoryAlignment =3D LowMemoryAlignment; + } + ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D ALIGN_VALUE(DmaBufferInf= o->DmaBufferSize, MemoryAlignment)); + =20 + // + // Allocate memory for DMA buffer + // + DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SI= ZE_TO_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); + ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); + if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { + DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); + return EFI_OUT_OF_RESOURCES; + } + + DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase + = DmaBufferInfo->DmaBufferSize; + DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo->DmaBufferBase; + LowBottom =3D 0; + LowTop =3D DmaBufferInfo->DmaBufferBase; + HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBuffer= Size; + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); } else { - MemoryAlignment =3D LowMemoryAlignment; - } - ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D ALIGN_VALUE(DmaBufferInfo->D= maBufferSize, MemoryAlignment)); - DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SIZE_T= O_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); - ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); - if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { - DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); - return EFI_OUT_OF_RESOURCES; - } =20 + // + // Get the PMR ranges information for the hob + // + SysMemHob =3D GET_GUID_HOB_DATA (SysMemHobPtr); =20 + DmaBufferInfo->DmaBufferBase =3D SysMemHob->ProtectedLowLimit << 20; + LowBottom =3D SysMemHob->ProtectedLowBase; + LowTop =3D SysMemHob->ProtectedLowLimit << 20; + HighBottom =3D (UINT64) BASE_4GB; + HighTop =3D (UINT64) SysMemHob->ProtectedHighLimit << 20; + } + =20 + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferS= ize)); DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", DmaBufferInfo->DmaBufferB= ase)); =20 - DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase + Dm= aBufferInfo->DmaBufferSize; - DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo->DmaBufferBase; - // // (Re)Install PPI. // @@ -478,10 +505,7 @@ InitDmaProtection ( } ASSERT_EFI_ERROR (Status); =20 - LowBottom =3D 0; - LowTop =3D DmaBufferInfo->DmaBufferBase; - HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSi= ze; - HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); + =20 Status =3D SetDmaProtectedRange ( VTdInfo, diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf = b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf index 5b688d5cbf..427c9a830c 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf @@ -4,7 +4,7 @@ # This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI # and provide DMA protection in PEI. # -# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# This program and the accompanying materials # are licensed and made available under the terms and conditions of the BS= D License # which accompanies this distribution. The full text of the license may b= e found at @@ -46,6 +46,9 @@ IoLib CacheMaintenanceLib =20 +[Guids] + gSysMemInfoDataHobGuid ## CONSUMES + [Ppis] gEdkiiIoMmuPpiGuid ## PRODUCES gEdkiiVTdInfoPpiGuid ## CONSUMES diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c b/IntelSil= iconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c index 888905d40d..b6a3614e75 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c @@ -1,6 +1,6 @@ /** @file =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made availa= ble under the terms and conditions of the BSD License which accompanies this distr= ibution. @@ -203,6 +203,8 @@ DisableDmar ( ) { UINT32 Reg32; + UINT32 Status; + UINT32 Command; =20 DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBase= Address)); =20 @@ -214,7 +216,28 @@ DisableDmar ( // // Disable VTd // - MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP); + // + // Set TE (Translation Enable: BIT31) of Global command register to zero + // + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status & ~B_GMCD_REG_TE); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); + + // + // Poll on TE Status bit of Global status register to become zero + // + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D B_GSTS_REG_TE); + + // + // Set SRTP (Set Root Table Pointer: BIT30) of Global command register i= n order to update the root table pointerDisable VTd + // + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + Status =3D (Reg32 & 0x96FFFFFF); // Reset the one-shot bits + Command =3D (Status | B_GMCD_REG_SRTP); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Command); do { Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); diff --git a/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h b/Inte= lSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h new file mode 100644 index 0000000000..537d013783 --- /dev/null +++ b/IntelSiliconPkg/Include/Library/GetVtdPmrAlignmentLib.h @@ -0,0 +1,31 @@ +/** @file + Get Global VTd PMR alignment information library. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + + +#ifndef __GET_VTD_PMR_ALIGN_LIB_H__ +#define __GET_VTD_PMR_ALIGN_LIB_H__ +#include + +/** + Get Global VT-d Protected Memory alignment. + + + @return protected high memory alignment. +**/ + +UINTN +GetGlobalVtdPmrAlignment ( +); + +#endif // __GET_VTD_PMR_ALIGN_LIB_H__ diff --git a/IntelSiliconPkg/Include/SysMemInfoHob.h b/IntelSiliconPkg/Incl= ude/SysMemInfoHob.h new file mode 100644 index 0000000000..d3045b2c7a --- /dev/null +++ b/IntelSiliconPkg/Include/SysMemInfoHob.h @@ -0,0 +1,28 @@ +/** @file + The definition for VTD System information Hob. + + This is a lightweight VTd information report in PEI phase. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _SYS_MEM_INFO_HOB_H_ +#define _SYS_MEM_INFO_HOB_H_ + +typedef struct { + UINTN ProtectedLowBase; + UINTN ProtectedLowLimit; + UINTN ProtectedHighBase; + UINTN ProtectedHighLimit; +} SYSTEM_MEM_INFO_HOB; + +#endif // _SYS_MEM_INFO_HOB_H_ + diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSil= iconPkg.dec index c0cf58fa6c..d2efac71c0 100644 --- a/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/IntelSiliconPkg/IntelSiliconPkg.dec @@ -3,7 +3,7 @@ # # This package provides common open source Intel silicon modules. # -# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
# This program and the accompanying materials are licensed and made availa= ble under # the terms and conditions of the BSD License that accompanies this distri= bution. # The full text of the license may be found at @@ -27,6 +27,7 @@ ## @libraryclass Provides services to access Microcode region on flash = device. # MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h + GetVtdPmrAlignmentLib|Include/Library/GetVtdPmrAlignmentLib.h =20 [Guids] ## GUID for Package token space @@ -40,6 +41,7 @@ =20 ## Include/Guid/MicrocodeFmp.h gMicrocodeFmpImageTypeIdGuid =3D { 0x96d4fdcd, 0x1502, 0x424d, { 0x= 9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } } + gSysMemInfoDataHobGuid =3D {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, 0x= b5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } } =20 [Ppis] gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } diff --git a/IntelSiliconPkg/IntelSiliconPkg.dsc b/IntelSiliconPkg/IntelSil= iconPkg.dsc index 790870e2f1..99061e3715 100644 --- a/IntelSiliconPkg/IntelSiliconPkg.dsc +++ b/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -1,7 +1,7 @@ ## @file # This package provides common open source Intel silicon modules. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the= BSD License @@ -40,6 +40,7 @@ SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/Microcod= eFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf + GetVtdPmrAlignmentLib|IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetV= tdPmrAlignmentLib.inf =20 [LibraryClasses.common.PEIM] PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf diff --git a/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignme= ntLib.c b/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentL= ib.c new file mode 100644 index 0000000000..28fb8d4978 --- /dev/null +++ b/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.c @@ -0,0 +1,170 @@ +/** @file + Library to get Global VTd PMR alignment information. + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble under + the terms and conditions of the BSD License which accompanies this distr= ibution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef union { + struct { + UINT32 Low; + UINT32 High; + } Data32; + UINT64 Data; +} UINT64_STRUCT; + +/** + Get protected low memory alignment. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected low memory alignment. +**/ +UINT32 +GetGlobalVTdPlmrAlignment ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Data32; + + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0xFFFFFFFF); + Data32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG); + Data32 =3D ~Data32 + 1; + + return Data32; +} + +/** + Get protected high memory alignment. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected high memory alignment. +**/ +UINT64_STRUCT +GetGlobalVTdPhmrAlignment ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress + ) +{ + UINT64_STRUCT Data64; + + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0xFFFFFFFFFFFFFF= FF); + Data64.Data =3D MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG); + Data64.Data =3D ~Data64.Data + 1; + Data64.Data =3D Data64.Data & (LShiftU64 (1, HostAddressWidth) - 1); + + return Data64; +} + +/** + Get Global VT-d Protected Memory Aignment. + + @return protected high memory alignment. +**/ +UINTN +GetGlobalVtdPmrAlignment ( +) +{ + UINT32 LowMemoryAlignment; + UINT64_STRUCT HighMemoryAlignment; + UINTN MemoryAlignment; + UINT32 GlobalVTdBaseAddress; + EFI_STATUS Status; + UINTN VtdIndex; + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + EFI_ACPI_DMAR_DRHD_HEADER *DrhdHeader; + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; + + // + // Initialization + // + GlobalVTdBaseAddress =3D 0xFFFFFFFF; + LowMemoryAlignment =3D 0; + HighMemoryAlignment.Data =3D 0; + MemoryAlignment =3D 0; + Status =3D EFI_UNSUPPORTED; + VtdIndex =3D 0; + DmarHeader =3D NULL; + DrhdHeader =3D NULL; + AcpiDmarTable =3D NULL; + + // + // Fatch the PEI DMAR ACPU Table that created and installed in PlatformV= TdInfoSamplePei.c + // + Status =3D PeiServicesLocatePpi ( + &gEdkiiVTdInfoPpiGuid, + 0, + NULL, + (VOID **)&AcpiDmarTable + ); + if (EFI_ERROR (Status)) { + + DEBUG ((DEBUG_ERROR, "PeiServicesLocatePpi gEdkiiVTdInfoPpiGuid failed= \n")); + Status =3D EFI_NOT_FOUND; + MemoryAlignment =3D SIZE_1MB; + + } else { + + // + // Seatch the DRHD structure with INCLUDE_PCI_ALL flag Set -> Global V= T-d + // + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTabl= e + 1)); + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Heade= r.Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + DrhdHeader =3D (EFI_ACPI_DMAR_DRHD_HEADER *) DmarHeader; + if ((DrhdHeader->Flags & BIT0) =3D=3D BIT0) { + GlobalVTdBaseAddress =3D (UINT32)DrhdHeader->RegisterBaseAddress; + DEBUG ((DEBUG_INFO," GlobalVTdBaseAddress: %x\n", GlobalVTdBase= Address)); + } + VtdIndex++; + + break; + + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader = + DmarHeader->Length); + } + + if (GlobalVTdBaseAddress =3D=3D 0xFFFFFFFF) { + + DEBUG ((DEBUG_ERROR, "Error! Please set INCLUDE_PCI_ALL flag to your= Global VT-d\n")); + MemoryAlignment =3D SIZE_1MB; + + } else { + // + // Get the alignment information from VT-d register + // + LowMemoryAlignment =3D GetGlobalVTdPlmrAlignment (AcpiDmarTable->Hos= tAddressWidth, GlobalVTdBaseAddress); + HighMemoryAlignment =3D GetGlobalVTdPhmrAlignment (AcpiDmarTable->Ho= stAddressWidth, GlobalVTdBaseAddress); + if (LowMemoryAlignment < HighMemoryAlignment.Data) { + MemoryAlignment =3D (UINTN)HighMemoryAlignment.Data; + } else { + MemoryAlignment =3D LowMemoryAlignment; + } + } + } + + return MemoryAlignment; +} \ No newline at end of file diff --git a/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignme= ntLib.inf b/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmen= tLib.inf new file mode 100644 index 0000000000..2ef199c92e --- /dev/null +++ b/IntelSiliconPkg/Library/GetVtdPmrAlignmentLib/GetVtdPmrAlignmentLib.i= nf @@ -0,0 +1,38 @@ +## @file +# Component INF file for the GetVtdPmrAlignment library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials are licensed and made availa= ble under +# the terms and conditions of the BSD License which accompanies this distr= ibution. +# The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D GetVtdPmrAlignmentLib +FILE_GUID =3D 0332BE93-0547-4D87-A7FA-0D9D76C53187 +MODULE_TYPE =3D BASE +LIBRARY_CLASS =3D GetVtdPmrAlignmentLib + +[Packages] +MdePkg/MdePkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] +GetVtdPmrAlignmentLib.c + +[LibraryClasses] +DebugLib +BaseMemoryLib +MemoryAllocationLib +BaseLib +PeiServicesLib + +[Ppis] +gEdkiiVTdInfoPpiGuid --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#45212): https://edk2.groups.io/g/devel/message/45212 Mute This Topic: https://groups.io/mt/32798378/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-