From nobody Sat May 4 02:15:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+44475+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44475+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1564372292; cv=none; d=zoho.com; s=zohoarc; b=Om6qaHARMJwLFXZsIrjzUwBZrzm4QkWlNbnHZ8KEp0ueRP1tuTA6OP831L1C0m59hCi914ETDY0/Le8ttkUnBPlvS4WXWNbv5M/eWuveo2BPAbSsF/E4e89AiamjqrNfHwmlDIQBMEc4MTR66X9Q1NA7RnUmOVNW4vv9xrxrLwI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1564372292; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=7wSxOyyqOGq61s9qFJTp6Kd10SpxZHJjRz6CxflPjyE=; b=N02jBGAiffGua+fkFVyiGxNDt/zK0UMPFekGud87qDw1NUpAVJfxckpNowihl/NqrNptKO4rSozdHWfTYtzj2Ges4EnGkScL/F3BPKY/5Z5nHkRcRAQreiZpR2YOziCMQkHPY/cvm9XDVX1yAJ00bJbilrDX3cFIlUYBfUZ8JTg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44475+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1564372292008729.0316136794481; Sun, 28 Jul 2019 20:51:32 -0700 (PDT) Return-Path: X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by groups.io with SMTP; Sun, 28 Jul 2019 20:51:31 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jul 2019 20:51:30 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,321,1559545200"; d="scan'208";a="176260736" X-Received: from pidsbabios005.gar.corp.intel.com ([10.66.128.253]) by orsmga006.jf.intel.com with ESMTP; 28 Jul 2019 20:51:28 -0700 From: "Javeed, Ashraf" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao , Ray Ni , Hao A Wu Subject: [edk2-devel] [Patch V2] MdePkg/PciExpress21.h: Fix the PCI industry standard register defines Date: Mon, 29 Jul 2019 09:21:23 +0530 Message-Id: <20190729035123.12444-1-ashraf.javeed@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ashraf.javeed@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1564372291; bh=v8G+UvPZmadvrRC/4sYbPV2voyfRV0cG3edTBNUlaSo=; h=Cc:Date:From:Reply-To:Subject:To; b=rLDQSZJEmT2DlMNMPSCj3BbxzahL+o4RayQgM/13MjAIBKKUNV6PlY14BVVtFNKZR84 wTc4ia7c6U3rplvuTTME8Do7W9Dx25wBu6qmvoDC89EIBwn4Rabws/9Vi4BsFj3UJyase sXsZkW3scS9/XzJKUY9wUuJ9UlSkbl8W75w= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2007 The following two PCI Capability Structure registers are updated as per the PCI Base Specification Revision 4:- (1) The PCI Device capability register 2(PCI_REG_PCIE_DEVICE_CAPABILITY2) needs to be upgraded for the PCI features like - LN system CLS (LnSystemCLS), 10b Tag completer/requester register fields (TenBitTagCompleterSupported, TenBitTagRequesterSupported), Emergency power reduction support and initialization requirement (EmergencyPowerReductionSupported, EmergencyPowerReductionInitializationRequired), and FRS support (FrsSupported ). (2) The PCI Device Control register 2(PCI_REG_PCIE_DEVICE_CONTROL2) needs to be upgraded for the - Emergency power reduction request enabling (EmergencyPowerReductionRequest), and also the 10b Extended Tag enabling (TenBitTagRequesterEnable). The following two are defined as per the PCI Express Base Specification Revision 2.1:- (1) Defined macro definitions for all the ranges of Maximum Payload Sizes and Maximum Read Request Sizes register fields (2) Defined macro definitions for all the ranges of Completion Timeout value. Signed-off-by: Ashraf Javeed Cc: Michael D Kinney Cc: Liming Gao Cc: Ray Ni Cc: Hao A Wu --- In V2: Reserved field name change in PCI_REG_PCIE_DEVICE_CAPABILITY2 --- MdePkg/Include/IndustryStandard/PciExpress21.h | 39 ++++++++++++++++++++++= ++++++++++++++--- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/PciExpress21.h b/MdePkg/Includ= e/IndustryStandard/PciExpress21.h index d4003de74c..f17f570775 100644 --- a/MdePkg/Include/IndustryStandard/PciExpress21.h +++ b/MdePkg/Include/IndustryStandard/PciExpress21.h @@ -91,6 +91,24 @@ typedef union { UINT16 Uint16; } PCI_REG_PCIE_DEVICE_CONTROL; =20 +#define PCIE_MAX_PAYLOAD_SIZE_128B 0 +#define PCIE_MAX_PAYLOAD_SIZE_256B 1 +#define PCIE_MAX_PAYLOAD_SIZE_512B 2 +#define PCIE_MAX_PAYLOAD_SIZE_1024B 3 +#define PCIE_MAX_PAYLOAD_SIZE_2048B 4 +#define PCIE_MAX_PAYLOAD_SIZE_4096B 5 +#define PCIE_MAX_PAYLOAD_SIZE_RVSD1 6 +#define PCIE_MAX_PAYLOAD_SIZE_RVSD2 7 + +#define PCIE_MAX_READ_REQ_SIZE_128B 0 +#define PCIE_MAX_READ_REQ_SIZE_256B 1 +#define PCIE_MAX_READ_REQ_SIZE_512B 2 +#define PCIE_MAX_READ_REQ_SIZE_1024B 3 +#define PCIE_MAX_READ_REQ_SIZE_2048B 4 +#define PCIE_MAX_READ_REQ_SIZE_4096B 5 +#define PCIE_MAX_READ_REQ_SIZE_RVSD1 6 +#define PCIE_MAX_READ_REQ_SIZE_RVSD2 7 + typedef union { struct { UINT16 CorrectableError : 1; @@ -250,16 +268,30 @@ typedef union { UINT32 NoRoEnabledPrPrPassing : 1; UINT32 LtrMechanism : 1; UINT32 TphCompleter : 2; - UINT32 Reserved : 4; + UINT32 LnSystemCLS : 2; + UINT32 TenBitTagCompleterSupported : 1; + UINT32 TenBitTagRequesterSupported : 1; UINT32 Obff : 2; UINT32 ExtendedFmtField : 1; UINT32 EndEndTlpPrefix : 1; UINT32 MaxEndEndTlpPrefixes : 2; - UINT32 Reserved2 : 8; + UINT32 EmergencyPowerReductionSupported : 2; + UINT32 EmergencyPowerReductionInitializationRequired : 1; + UINT32 Reserved3 : 4; + UINT32 FrsSupported : 1; } Bits; UINT32 Uint32; } PCI_REG_PCIE_DEVICE_CAPABILITY2; =20 +#define PCIE_COMPLETION_TIMEOUT_NOT_SUPPORTED 0 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_SUPPORTED 1 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_SUPPORTED 2 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_SUPPORTED 3 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_SUPPORTED 6 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_SUPPORTED 7 +#define PCIE_COMPLETION_TIMEOUT_RANGE_B_C_D_SUPPORTED 14 +#define PCIE_COMPLETION_TIMEOUT_RANGE_A_B_C_D_SUPPORTED 15 + #define PCIE_DEVICE_CAPABILITY_OBFF_MESSAGE BIT0 #define PCIE_DEVICE_CAPABILITY_OBFF_WAKE BIT1 =20 @@ -273,7 +305,8 @@ typedef union { UINT16 IdoRequest : 1; UINT16 IdoCompletion : 1; UINT16 LtrMechanism : 2; - UINT16 Reserved : 2; + UINT16 EmergencyPowerReductionRequest : 1; + UINT16 TenBitTagRequesterEnable : 1; UINT16 Obff : 2; UINT16 EndEndTlpPrefixBlocking : 1; } Bits; --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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