From nobody Tue Feb 10 04:16:37 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+44137+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44137+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1563796659; cv=none; d=zoho.com; s=zohoarc; b=E/MKAaSfBWMzzm2jC40ebGY8OAR+GyVsBmYm9SL8KStdKiMat7+APTMATi3bqaoYU3tkDGgfZpOEoPsTiU0oKL0Zlb17VzUzboQVjNkSbu+D8zZTwiOBqTs6JVVFX+i/TlITW9R2cGigNXiD8amEA/NlEIwjex5BveT5w3HetzU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563796659; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=nJF0H1g6NbiZOpV5M8ZURTJ9EsDGjbQi3swtPJ0pNig=; b=XenFcrf17okmaCl+NBSwhiursffj7sKSjAt+Hb4bsJALFI5cZbo1FoJYgxxax/keKYabRWNZTUMRai2/MfQV3vn9SUgYIY6bbR9lzjkYNsXlRA0gZ74ijpVrLkiHNW3waKNybmpE/6Gi5ieje5N6XZkXGt9azd6GLMarV1GLbjU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44137+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1563796659107229.89925390792496; Mon, 22 Jul 2019 04:57:39 -0700 (PDT) Return-Path: X-Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) by groups.io with SMTP; Mon, 22 Jul 2019 04:57:38 -0700 X-Received: by mail-pg1-f195.google.com with SMTP id o13so17538384pgp.12 for ; Mon, 22 Jul 2019 04:57:38 -0700 (PDT) X-Gm-Message-State: APjAAAXtBVSH+p9NMzjXjOEwupzlv+63KDSB7PYfuNi8/ziqBvq0zyFI kr2z0zEUMFQOGu0y3cUXVsBLq/RKtHM= X-Google-Smtp-Source: APXvYqyP4DDsERQ43n+3LRwUuzC17WnIhWx/Mv6OItNWgHR2eJ/oBFO1Gc3FUzffZI1g3Sfap4EUEQ== X-Received: by 2002:a17:90a:fe5:: with SMTP id 92mr77682818pjz.35.1563796657110; Mon, 22 Jul 2019 04:57:37 -0700 (PDT) X-Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id 65sm39800656pff.148.2019.07.22.04.57.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Jul 2019 04:57:36 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, okamoto.satoru@socionext.com, Masahisa Kojima Subject: [edk2-devel] [edk2-platforms PATCH v1 1/3] NetsecDxe: embed phy address into NETSEC SDK internal structure Date: Mon, 22 Jul 2019 20:56:34 +0900 Message-Id: <20190722115636.3413-2-masahisa.kojima@linaro.org> In-Reply-To: <20190722115636.3413-1-masahisa.kojima@linaro.org> References: <20190722115636.3413-1-masahisa.kojima@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,masahisa.kojima@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1563796658; bh=DG7/sUbQlPUeT5NZLEKQxc1tp4v+qYT9zdqcxxVZGrI=; h=Cc:Date:From:Reply-To:Subject:To; b=kGXCtMTQ9kgqVAWrECtZMLVxbRTzMOY1XZePBWgosE1Z+8fL5vXOlwrEBtiIUbrDYGC ZqCzcPn79C0tWw4Zwz9Fg1SCH/CsEQ6PgcyVPVMbOsaq/709lbjCy0idgz44ifg7eG1jb iFGuoRIXv0m5vVqgkzTnvvbrutxs3TM91ik= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is a refactoring of phy address handling in Netsec driver. NETSEC SDK, low level driver for NetsecDxe, did not store phy address. User should specify the phy address as an argument to the SDK public functions. It prevented NETSEC SDK from internally controlling phy, and it also bothers user application with phy address management. With that, we encapsulate the phy address into NETSEC SDK. Signed-off-by: Masahisa Kojima Signed-off-by: Satoru Okamoto Reviewed-by: Leif Lindholm --- .../Drivers/Net/NetsecDxe/NetsecDxe.c | 10 +-- .../Drivers/Net/NetsecDxe/NetsecDxe.h | 2 - .../netsec_sdk/include/ogma_api.h | 6 +- .../netsec_sdk/src/ogma_gmac_access.c | 61 +++++-------------- .../netsec_sdk/src/ogma_internal.h | 2 + .../netsec_sdk/src/ogma_misc.c | 6 ++ 6 files changed, 28 insertions(+), 59 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c index 160bb08a4632..0b91d4af44a3 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.c @@ -59,6 +59,8 @@ Probe ( // phy-interface Param.gmac_config.phy_interface =3D OGMA_PHY_INTERFACE_RGMII; =20 + Param.phy_addr =3D LanDriver->Dev->Resources[2].AddrRangeMin; + // Read and save the Permanent MAC Address EepromBase =3D LanDriver->Dev->Resources[1].AddrRangeMin; GetCurrentMacAddress (EepromBase, LanDriver->SnpMode.PermanentAddress.Ad= dr); @@ -107,8 +109,6 @@ Probe ( return EFI_DEVICE_ERROR; } =20 - LanDriver->PhyAddress =3D LanDriver->Dev->Resources[2].AddrRangeMin; - ogma_enable_top_irq (LanDriver->Handle, OGMA_TOP_IRQ_REG_NRM_RX | OGMA_TOP_IRQ_REG_NRM_TX); =20 @@ -280,7 +280,7 @@ SnpInitialize ( ReturnUnlock (EFI_DEVICE_ERROR); } =20 - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, LanDriver->Phy= Address, + ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, &phy_link_status); if (ogma_err !=3D OGMA_ERR_OK) { DEBUG ((DEBUG_ERROR, @@ -438,7 +438,7 @@ NetsecPollPhyStatus ( LanDriver =3D INSTANCE_FROM_SNP_THIS (Snp); =20 // Update the media status - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, LanDriver->Phy= Address, + ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, &phy_link_status); if (ogma_err !=3D OGMA_ERR_OK) { DEBUG ((DEBUG_ERROR, @@ -662,7 +662,7 @@ SnpGetStatus ( LanDriver =3D INSTANCE_FROM_SNP_THIS (Snp); =20 // Update the media status - ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, LanDriver->Phy= Address, + ogma_err =3D ogma_get_phy_link_status (LanDriver->Handle, &phy_link_status); if (ogma_err !=3D OGMA_ERR_OK) { DEBUG ((DEBUG_ERROR, diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h = b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h index 870833c8d31c..c95ff215199d 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.h @@ -70,8 +70,6 @@ typedef struct { NON_DISCOVERABLE_DEVICE *Dev; =20 NETSEC_DEVICE_PATH DevicePath; - - UINTN PhyAddress; } NETSEC_DRIVER; =20 #define NETSEC_SIGNATURE SIGNATURE_32('n', 't', 's', 'c') diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/include/ogma_api.h b/Silicon/Socionext/SynQuacer/Drivers/Net= /NetsecDxe/netsec_for_uefi/netsec_sdk/include/ogma_api.h index 66f39150430b..be80dd9ae1fd 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/include/ogma_api.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/include/ogma_api.h @@ -318,6 +318,7 @@ struct ogma_param_s{ ogma_desc_ring_param_t desc_ring_param[OGMA_DESC_RING_ID_MAX+1]; ogma_gmac_config_t gmac_config; ogma_uint8 mac_addr[6]; + ogma_uint8 phy_addr; }; =20 struct ogma_tx_pkt_ctrl_s{ @@ -412,14 +413,12 @@ ogma_err_t ogma_set_gmac_mode ( =20 void ogma_set_phy_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 reg_addr, ogma_uint16 value ); =20 ogma_uint16 ogma_get_phy_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 reg_addr ); =20 @@ -660,7 +659,6 @@ ogma_err_t ogma_get_gmac_lpitimer_reg ( =20 void ogma_set_phy_mmd_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr, ogma_uint16 value @@ -668,14 +666,12 @@ void ogma_set_phy_mmd_reg ( =20 ogma_uint16 ogma_get_phy_mmd_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ); =20 ogma_err_t ogma_get_phy_link_status ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_phy_link_status_t *phy_link_status_p ); =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_gmac_access.c b/Silicon/Socionext/SynQuacer/Drivers= /Net/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_gmac_access.c index 88c149c10466..150d25ac3fbf 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_gmac_access.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_gmac_access.c @@ -40,14 +40,12 @@ **********************************************************************/ static void ogma_set_phy_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 reg_addr, ogma_uint16 value ); =20 static ogma_uint16 ogma_get_phy_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 reg_addr ); =20 @@ -57,14 +55,12 @@ void ogma_dump_gmac_stat (ogma_ctrl_t *ctrl_p); =20 static void ogma_set_phy_target_mmd_reg_addr ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ); =20 static void ogma_set_phy_mmd_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr, ogma_uint16 value @@ -72,7 +68,6 @@ static void ogma_set_phy_mmd_reg_sub ( =20 static ogma_uint16 ogma_get_phy_mmd_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ); @@ -435,7 +430,6 @@ ogma_err_t ogma_set_gmac_mode ( =20 static void ogma_set_phy_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 reg_addr, ogma_uint16 value ) @@ -447,7 +441,7 @@ static void ogma_set_phy_reg_sub ( OGMA_GMAC_REG_ADDR_GDR, value); =20 - cmd =3D ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) | + cmd =3D ( ( ctrl_p->param.phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) | ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) | ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) | OGMA_GMAC_GAR_REG_GW | @@ -466,7 +460,6 @@ static void ogma_set_phy_reg_sub ( =20 void ogma_set_phy_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 reg_addr, ogma_uint16 value ) @@ -476,27 +469,25 @@ void ogma_set_phy_reg ( =20 if (( ctrl_p =3D=3D NULL) || ( !ctrl_p->param.use_gmac_flag) - || ( phy_addr >=3D 32) || ( reg_addr >=3D 32) ) { pfdep_print( PFDEP_DEBUG_LEVEL_FATAL, "An error occurred at ogma_set_phy_reg.\nPlease set v= alid argument.\n"); return; } =20 - ogma_set_phy_reg_sub( ctrl_p, phy_addr, reg_addr, value); + ogma_set_phy_reg_sub( ctrl_p, reg_addr, value); =20 } =20 static ogma_uint16 ogma_get_phy_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 reg_addr ) { =20 ogma_uint32 cmd; =20 - cmd =3D ( ( phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) | + cmd =3D ( ( ctrl_p->param.phy_addr << OGMA_GMAC_GAR_REG_SHIFT_PA) | ( reg_addr << OGMA_GMAC_GAR_REG_SHIFT_GR) | ( OGMA_CLOCK_RANGE_IDX << OGMA_GMAC_GAR_REG_SHIFT_CR) | OGMA_GMAC_GAR_REG_GB); @@ -516,7 +507,6 @@ static ogma_uint16 ogma_get_phy_reg_sub ( =20 ogma_uint16 ogma_get_phy_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 reg_addr ) { @@ -525,14 +515,13 @@ ogma_uint16 ogma_get_phy_reg ( =20 if ( ( ctrl_p =3D=3D NULL) || ( !ctrl_p->param.use_gmac_flag) - || ( phy_addr >=3D 32) || ( reg_addr >=3D 32) ) { pfdep_print( PFDEP_DEBUG_LEVEL_FATAL, "An error occurred at ogma_get_phy_reg.\nPlease set v= alid argument.\n"); return 0; } =20 - value =3D ogma_get_phy_reg_sub(ctrl_p, phy_addr, reg_addr); + value =3D ogma_get_phy_reg_sub(ctrl_p, reg_addr); =20 =20 return value; @@ -702,7 +691,6 @@ ogma_err_t ogma_get_gmac_status ( =20 static void ogma_set_phy_target_mmd_reg_addr ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ) @@ -713,21 +701,20 @@ static void ogma_set_phy_target_mmd_reg_addr ( cmd =3D ( ogma_uint32)dev_addr; =20 /*set command to MMD access control register */ - ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd); + ogma_set_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AC, cmd); =20 /* set MMD access address data register Write reg_addr */ - ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, reg= _addr); + ogma_set_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AAD, reg_addr); =20 /* write value to MMD ADDR */ cmd =3D ( (1U << 14) | dev_addr); =20 /* set command to MMD access control register */ - ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AC, cmd); + ogma_set_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AC, cmd); } =20 static void ogma_set_phy_mmd_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr, ogma_uint16 value @@ -735,30 +722,27 @@ static void ogma_set_phy_mmd_reg_sub ( { /* set target mmd reg_addr */ ogma_set_phy_target_mmd_reg_addr( ctrl_p, - phy_addr, dev_addr, reg_addr); =20 /* Write value to MMD access address data register */ - ogma_set_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_AAD, val= ue); + ogma_set_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AAD, value); =20 } =20 static ogma_uint16 ogma_get_phy_mmd_reg_sub ( ogma_ctrl_t *ctrl_p, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ) { /* set target mmd reg_addr */ ogma_set_phy_target_mmd_reg_addr( ctrl_p, - phy_addr, dev_addr, reg_addr); =20 /* Read value for MMD access address data register */ - return ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_MMD_A= AD); + return ogma_get_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_MMD_AAD); } =20 ogma_err_t ogma_set_gmac_lpictrl_reg ( @@ -878,7 +862,6 @@ ogma_err_t ogma_get_gmac_lpitimer_reg ( =20 void ogma_set_phy_mmd_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr, ogma_uint16 value @@ -890,8 +873,7 @@ void ogma_set_phy_mmd_reg ( return; } =20 - if ( ( phy_addr > 31U) || - ( dev_addr > 31U) ) { + if ( dev_addr > 31U) { return; } =20 @@ -900,7 +882,6 @@ void ogma_set_phy_mmd_reg ( } =20 ogma_set_phy_mmd_reg_sub ( ctrl_p, - phy_addr, dev_addr, reg_addr, value); @@ -911,7 +892,6 @@ void ogma_set_phy_mmd_reg ( =20 ogma_uint16 ogma_get_phy_mmd_reg ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_uint8 dev_addr, ogma_uint16 reg_addr ) @@ -923,8 +903,7 @@ ogma_uint16 ogma_get_phy_mmd_reg ( return 0; } =20 - if ( ( phy_addr > 31U) || - ( dev_addr > 31U) ) { + if ( dev_addr > 31U) { return 0; } =20 @@ -933,7 +912,6 @@ ogma_uint16 ogma_get_phy_mmd_reg ( } =20 value =3D ogma_get_phy_mmd_reg_sub ( ctrl_p, - phy_addr, dev_addr, reg_addr); =20 @@ -943,7 +921,6 @@ ogma_uint16 ogma_get_phy_mmd_reg ( =20 ogma_err_t ogma_get_phy_link_status ( ogma_handle_t ogma_handle, - ogma_uint8 phy_addr, ogma_phy_link_status_t *phy_link_status_p ) { @@ -955,10 +932,6 @@ ogma_err_t ogma_get_phy_link_status ( return OGMA_ERR_PARAM; } =20 - if ( phy_addr >=3D 32) { - return OGMA_ERR_RANGE; - } - if ( !ctrl_p->param.use_gmac_flag) { return OGMA_ERR_NOTAVAIL; } @@ -966,17 +939,17 @@ ogma_err_t ogma_get_phy_link_status ( pfdep_memset( phy_link_status_p, 0, sizeof( ogma_phy_link_status_t) ); =20 /* Read PHY CONTROL Register */ - tmp =3D ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_CONT= ROL); + tmp =3D ogma_get_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_CONTROL); =20 /* Read PHY STATUS Register */ - value =3D ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADDR_ST= ATUS); + value =3D ogma_get_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_STATUS); =20 /* check latched_link_down_flag */ if ( ( value & ( 1U << OGMA_PHY_STATUS_REG_LINK_STATUS) ) =3D=3D 0) { phy_link_status_p->latched_link_down_flag =3D OGMA_TRUE; =20 /* Read PHY STATUS Register */ - value =3D ogma_get_phy_reg_sub( ctrl_p, phy_addr, OGMA_PHY_REG_ADD= R_STATUS); + value =3D ogma_get_phy_reg_sub( ctrl_p, OGMA_PHY_REG_ADDR_STATUS); =20 } =20 @@ -1036,12 +1009,10 @@ ogma_err_t ogma_get_phy_link_status ( =20 /* Read MASTER-SLAVE Control Register */ value =3D ogma_get_phy_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_REG_ADDR_MASTER_SLAVE_C= ONTROL); =20 /* Read MASTER-SLAVE Status Register */ tmp =3D ogma_get_phy_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_REG_ADDR_MASTER_SLAVE_STA= TUS); =20 /* Check Current Link Speed */ @@ -1061,12 +1032,10 @@ ogma_err_t ogma_get_phy_link_status ( =20 /* Read Auto-Negotiation Advertisement register */ value =3D ogma_get_phy_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_REG_ADDR_AUTO_NEGO_= ABILTY); =20 /* Read Auto-Negotiation Link Partner Base Page Ability re= gister */ tmp =3D ogma_get_phy_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_REG_ADDR_AUTO_NEGO_L= INK_PATNER_ABILTY); =20 value =3D ( ( ( value & tmp) >> OGMA_PHY_ANA_REG_TAF) & @@ -1109,13 +1078,11 @@ ogma_err_t ogma_get_phy_link_status ( =20 /* Read EEE advertisement register */ value =3D ogma_get_phy_mmd_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_DEV_ADDR_AUTO_NEGO, OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_= ADVERTISE); =20 /* Read EEE link partner ability register */ tmp =3D ogma_get_phy_mmd_reg_sub( ctrl_p, - phy_addr, OGMA_PHY_DEV_ADDR_AUTO_NEGO, OGMA_PHY_AUTO_NEGO_REG_ADDR_EEE_LP= _ABILITY); =20 diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_internal.h b/Silicon/Socionext/SynQuacer/Drivers/Ne= t/NetsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_internal.h index ed09a7ada85d..a7bc69cf0777 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_internal.h +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_internal.h @@ -111,6 +111,8 @@ struct ogma_ctrl_s{ =20 pfdep_phys_addr_t dummy_desc_entry_phys_addr; =20 + ogma_uint8 phy_addr; + #ifdef OGMA_CONFIG_REC_STAT /** * Statistics information. diff --git a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_u= efi/netsec_sdk/src/ogma_misc.c b/Silicon/Socionext/SynQuacer/Drivers/Net/Ne= tsecDxe/netsec_for_uefi/netsec_sdk/src/ogma_misc.c index 4dec66313aa1..7481d2da2d24 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_misc.c +++ b/Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/netsec_for_uefi/net= sec_sdk/src/ogma_misc.c @@ -388,6 +388,12 @@ ogma_err_t ogma_init ( return OGMA_ERR_DATA; } =20 + if ( param_p->phy_addr >=3D 32) { + pfdep_print( PFDEP_DEBUG_LEVEL_FATAL, + "Error: phy_addr out of range\n"); + return OGMA_ERR_DATA; + } + ogma_err =3D ogma_probe_hardware( base_addr); =20 if ( ogma_err !=3D OGMA_ERR_OK) { --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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