From nobody Sun May 5 11:24:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+44115+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44115+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1563783386; cv=none; d=zoho.com; s=zohoarc; b=WlDNm8I3sqdo0wuabKGFsAusmRzRlJqSJzeN/91tM16uk2FlYgSy1YcZZ0d+qbcVFe9V7tENJb6R27e/Ydp4CjwvjQZLABsxDysZcHJxCJObZG3o5t1tLt9F7VQW1OKeGUuij8853d5Djrd2BDLm7MqrM1UTVOUqAGq6GkHVFuo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563783386; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=aaCWhxY2HG5p9md9kkJSqeEhHcc90DjmXzqoYTDwZCE=; b=b+e+nfKHbsJqc+WKMhR4rY98jUP2sZmtkSYnPo4UGsNno9GKjRRQF8ZIgn30T43OdHvLClvdId/VEHRdW5SgWz/FVCfvT7I5u5UL5XmhQnlgu+7G5Jlp3cJohWxvnVdeSPAohSvQbspUftCiRV0wDyggt6rqpK5mY5blj9HHPOs= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44115+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1563783386986800.9541587062898; Mon, 22 Jul 2019 01:16:26 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Mon, 22 Jul 2019 01:16:26 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jul 2019 01:16:25 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,294,1559545200"; d="scan'208";a="252831288" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.9.16]) by orsmga001.jf.intel.com with ESMTP; 22 Jul 2019 01:16:24 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek Subject: [edk2-devel] [PATCH 1/4] UefiCpuPkg/MpInitLib: Enable 5-level paging for AP when BSP's enabled Date: Mon, 22 Jul 2019 16:15:44 +0800 Message-Id: <20190722081547.56100-2-ray.ni@intel.com> In-Reply-To: <20190722081547.56100-1-ray.ni@intel.com> References: <20190722081547.56100-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1563783386; bh=V+dvxn+laH7gtxPIarYqtcqGW/WYnxQQ2YDBxeVyimc=; h=Cc:Date:From:Reply-To:Subject:To; b=HqISPl0oFk5VFD+xy+Noy3nlr+z1mLlYGcRD8EwnAtzPamb2QNyTybPHD38vNPXH8e5 ekBCFpVx4AZucMfWPS2gSM425CkAGypt3dVsozGNGO979CXWE47LL2NkYvuI1qm5BHkr8 KFpP6voerHwM6ZASu3lSF5+U6GDp/xyCSr0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2008 MpInitLib is the library that's responsible to wake up APs to provide MP PPI and Protocol services. The patch synchronizes BSP's CR4.LA57 to each AP's CR4.LA57. Without this change, AP may enter to GP fault when BSP's 5-level page table is set to AP during AP wakes up. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 11 +++++++++++ UefiCpuPkg/Library/MpInitLib/MpLib.h | 6 +++++- UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 3 ++- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 14 +++++++++++++- 4 files changed, 31 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 6f51bc4ebf..e4691315e9 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -790,6 +790,7 @@ FillExchangeInfoData ( volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo; UINTN Size; IA32_SEGMENT_DESCRIPTOR *Selector; + IA32_CR4 Cr4; =20 ExchangeInfo =3D CpuMpData->MpCpuExchangeInfo; ExchangeInfo->Lock =3D 0; @@ -814,6 +815,16 @@ FillExchangeInfoData ( =20 ExchangeInfo->InitializeFloatingPointUnitsAddress =3D (UINTN)InitializeF= loatingPointUnits; =20 + // + // We can check either CPUID(7).ECX[bit16] or check CR4.LA57[bit12] + // to determin whether 5-Level Paging is enabled. + // Using latter way is simpler because it also eliminates the needs to + // check whether platform wants to enable it. + // + Cr4.UintN =3D AsmReadCr4 (); + ExchangeInfo->Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); + DEBUG ((DEBUG_INFO, "CpuMp: 5-Level Paging =3D %d\n", ExchangeInfo->Enab= le5LevelPaging)); + // // Get the BSP's data of GDT and IDT // diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index f89037c59e..fa7d6b32e9 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -1,7 +1,7 @@ /** @file Common header file for MP Initialize Library. =20 - Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -185,6 +185,10 @@ typedef struct { UINT16 ModeTransitionSegment; UINT32 ModeHighMemory; UINT16 ModeHighSegment; + // + // Enable5LevelPaging indicates whether 5-level paging is enabled in lon= g mode. + // + UINTN Enable5LevelPaging; } MP_CPU_EXCHANGE_INFO; =20 #pragma pack() diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b/UefiCpuPkg/Librar= y/MpInitLib/X64/MpEqu.inc index 467f54a860..58ef369342 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -40,3 +40,4 @@ ModeTransitionMemoryLocation equ LockLocation + 9= 4h ModeTransitionSegmentLocation equ LockLocation + 98h ModeHighMemoryLocation equ LockLocation + 9Ah ModeHighSegmentLocation equ LockLocation + 9Eh +Enable5LevelPagingLocation equ LockLocation + 0A0h diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index cea90f3d4d..b563c2ed3e 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Module Name: @@ -100,6 +100,18 @@ SkipEnableExecuteDisableBit: ; mov eax, cr4 bts eax, 5 + + mov esi, Enable5LevelPagingLocation + cmp byte [ebx + esi], 0 + jz SkipEnable5Paging + + ; + ; Enable 5 Level Paging + ; + bts eax, 12 ; Set LA57=3D1. + +SkipEnable5Paging: + mov cr4, eax =20 ; --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#44115): https://edk2.groups.io/g/devel/message/44115 Mute This Topic: https://groups.io/mt/32556532/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 11:24:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+44116+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44116+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1563783388; cv=none; d=zoho.com; s=zohoarc; b=aNqgfhCNIrChVvJJCc6BSk97Y4u7XrSyKgYeB8DdStpSVr267WONyWAsURBwjPYijxN2Be7gHq7uUp6o/y/iXQ3EzqMd7axZLBgW/rT+4py9Rqer4mdZu14GeFEekP6JMxd7fofk9vunrgw6nTCH3WGv+4aCvsEjwOHX5FImQvg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563783388; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=xuPlTLPlCWlObA4BlBLviIm9XyqoD0IvS0++XGplIGg=; b=ckHaJ1CXIsLjcJea/k93Zkkfqns2NGKlcRxPGdo9dTYnPrWiQQEpIFvBz3HcfhKSU3QT6pmU/JFnrGfH3wVTPQym4ovmsuGW2sxlyqK0VzpIIXFRMx8t62bubKdxsW+KCEuc1GHk5hG+j7FLDfZjoNs0ZyttGey5OSQ/dOO9Z2g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44116+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156378338837045.185238910724024; Mon, 22 Jul 2019 01:16:28 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Mon, 22 Jul 2019 01:16:27 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jul 2019 01:16:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,294,1559545200"; d="scan'208";a="252831297" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.9.16]) by orsmga001.jf.intel.com with ESMTP; 22 Jul 2019 01:16:26 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek Subject: [edk2-devel] [PATCH 2/4] UefiCpuPkg/CpuDxe: Support parsing 5-level page table Date: Mon, 22 Jul 2019 16:15:45 +0800 Message-Id: <20190722081547.56100-3-ray.ni@intel.com> In-Reply-To: <20190722081547.56100-1-ray.ni@intel.com> References: <20190722081547.56100-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1563783387; bh=jnJwQoAhIJCqwX2iHP0uHopxfeX5WZT9bpCwVhjH1zo=; h=Cc:Date:From:Reply-To:Subject:To; b=FnJtW1ePuNOMw3go9Lp/dWRFczkCkpnd1A4JDBw/0QwzevnxeC2C+fHsHpYQqhyFSoh uNLxfQ4JGTpEVZKXLDdpjqpMOQiwuZtbvSJmfuHN2t46u5QFFFGAhPPI5jbyb8+A2H1eh k2Qn9oEbxYKHUIEV9nn9FrrpMaHWBn7Xofg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2008 Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek --- UefiCpuPkg/CpuDxe/CpuPageTable.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTa= ble.c index c369b44f12..8e959eb2b7 100644 --- a/UefiCpuPkg/CpuDxe/CpuPageTable.c +++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c @@ -1,7 +1,7 @@ /** @file Page table management support. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -276,25 +276,43 @@ GetPageTableEntry ( UINTN Index2; UINTN Index3; UINTN Index4; + UINTN Index5; UINT64 *L1PageTable; UINT64 *L2PageTable; UINT64 *L3PageTable; UINT64 *L4PageTable; + UINT64 *L5PageTable; UINT64 AddressEncMask; + IA32_CR4 Cr4; + BOOLEAN Enable5LevelPaging; =20 ASSERT (PagingContext !=3D NULL); =20 + Index5 =3D ((UINTN)RShiftU64 (Address, 48)) & PAGING_PAE_INDEX_MASK; Index4 =3D ((UINTN)RShiftU64 (Address, 39)) & PAGING_PAE_INDEX_MASK; Index3 =3D ((UINTN)Address >> 30) & PAGING_PAE_INDEX_MASK; Index2 =3D ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK; Index1 =3D ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK; =20 + Cr4.UintN =3D AsmReadCr4 (); + Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); + // Make sure AddressEncMask is contained to smallest supported address f= ield. // AddressEncMask =3D PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGI= NG_1G_ADDRESS_MASK_64; =20 if (PagingContext->MachineType =3D=3D IMAGE_FILE_MACHINE_X64) { - L4PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTa= bleBase; + if (Enable5LevelPaging) { + L5PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.X64.Page= TableBase; + if (L5PageTable[Index5] =3D=3D 0) { + *PageAttribute =3D PageNone; + return NULL; + } + + L4PageTable =3D (UINT64 *)(UINTN)(L5PageTable[Index5] & ~AddressEncM= ask & PAGING_4K_ADDRESS_MASK_64); + } else { + L4PageTable =3D (UINT64 *)(UINTN)PagingContext->ContextData.X64.Page= TableBase; + } if (L4PageTable[Index4] =3D=3D 0) { *PageAttribute =3D PageNone; return NULL; --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#44116): https://edk2.groups.io/g/devel/message/44116 Mute This Topic: https://groups.io/mt/32556533/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 11:24:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+44117+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44117+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1563783389; cv=none; d=zoho.com; s=zohoarc; b=d+rVeE2YuL4PQOF0txXUa90lDQMe3vBR/KYgfCIMQZJ+WkKltq4KqLYJnZqw+CrNMnXGsYPrqcFka0gUkOReIS/GBBCsdSp14NLlFB2R0TTz506nGL/RWHoApgCpodtefVrUGTTiuVpBmNuuwr+tZJgZ7hh61OM+FOXHl2ZYDTU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563783389; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=cbfzTHp3ZsQys88AdHWPwC5iVQjO5IfzuxNF1W+5UR0=; b=g2NpQMFAROwL5oyybpZkzrAIIysQooSnKkAVLukQJ6IeWccYvz+cjfgfypTbX1418YDqcN13cT96juwIi1951iDpARD1+QELZIlvnSSp0fVCRnloYaTplOztOhbgkVQTE2bXdn6gMYBsA9uQlQH0a2PSq0xOr1piihbQ3Ot1Sjk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44117+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1563783389256187.992238288404; Mon, 22 Jul 2019 01:16:29 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Mon, 22 Jul 2019 01:16:28 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jul 2019 01:16:28 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,294,1559545200"; d="scan'208";a="252831302" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.9.16]) by orsmga001.jf.intel.com with ESMTP; 22 Jul 2019 01:16:27 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek Subject: [edk2-devel] [PATCH 3/4] MdeModulePkg/DxeIpl: Introduce PCD PcdUse5LevelPageTable Date: Mon, 22 Jul 2019 16:15:46 +0800 Message-Id: <20190722081547.56100-4-ray.ni@intel.com> In-Reply-To: <20190722081547.56100-1-ray.ni@intel.com> References: <20190722081547.56100-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1563783388; bh=PkHBkPgBmS5SdnAuOltdp76zQDLJJ1OZja1Y+W1b+sg=; h=Cc:Date:From:Reply-To:Subject:To; b=Vm4isHbZLb/WYaCbzkEZwu9u0ZBL27G0ltQEKwLmhKVqIjiI/vxWN1WsJN5QosD+l86 3Epd1/la/OVRmdRH5g3QtwKNKr0BJ9GJ+6eMXYrlxuEc+WlUW6FF0MPrlwC3UgvGy5hJ0 jf5oZYH4WAvS79oai01LTO3mVvq0s6KdGKw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2008 The PCD indicates if 5-Level Paging will be enabled in long mode. 5-Level Paging will not be enabled when the PCD is TRUE but CPU doesn't support 5-Level Paging. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Reviewed-by: Eric Dong --- MdeModulePkg/MdeModulePkg.dec | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 12e0bbf579..21388595a9 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -1991,6 +1991,13 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynami= c, PcdsDynamicEx] # @Prompt The address mask when memory encryption is enabled. gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0|U= INT64|0x30001047 =20 + ## Indicates if 5-Level Paging will be enabled in long mode. 5-Level Pag= ing will not be enabled + # when the PCD is TRUE but CPU doesn't support 5-Level Paging. + # TRUE - 5-Level Paging will be enabled.
+ # FALSE - 5-Level Paging will not be enabled.
+ # @Prompt Enable 5-Level Paging support in long mode.=20 + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable|FALSE|BOOLEAN|0x000= 1105F + ## Capsule In Ram is to use memory to deliver the capsules that will be = processed after system # reset.

# This PCD indicates if the Capsule In Ram is supported.
--=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#44117): https://edk2.groups.io/g/devel/message/44117 Mute This Topic: https://groups.io/mt/32556534/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 11:24:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+44118+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44118+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1563783390; cv=none; d=zoho.com; s=zohoarc; b=ILlWHyJ/GWHOhlDuTOf1vTNWMhFqGp2kuIrZcL0HqZtdbK0oJsx5AeeAwnyML1ZczszaVD2i2DCw9Gh0FIfGSluNFT/ZJDhPCSVU9XXNlIYDfsqjGt8hSMcbeisd5aGwJDKVtinsa7dnhRz9Jj+HwbRvBFp5hBzbYY9zdZh9XfE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1563783390; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=u1+Xllki9uMGtH3mvWpUV6vCZ6OBXvDqXOlSCFabvL8=; b=S5hHM0V4RRPvSaQuKNuPz2NMGzeZbv8OoNuMHIaz2x2FftHuayIXW6rRxxOg60b7fsRJJfJlFAVKY8bXgnG2EIFoaEFTQPTP4JCEFm5jrBdki8CiW1k0a28ZC7ul7b5wHXNGTbTq1cxh5AG/os14Gw66bkHWfzndbq3YVR0XMC8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+44118+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1563783390695844.8522148116274; Mon, 22 Jul 2019 01:16:30 -0700 (PDT) Return-Path: X-Received: from mga12.intel.com (mga12.intel.com []) by groups.io with SMTP; Mon, 22 Jul 2019 01:16:29 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Jul 2019 01:16:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,294,1559545200"; d="scan'208";a="252831309" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.9.16]) by orsmga001.jf.intel.com with ESMTP; 22 Jul 2019 01:16:28 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek Subject: [edk2-devel] [PATCH 4/4] MdeModulePkg/DxeIpl: Create 5-level page table for long mode Date: Mon, 22 Jul 2019 16:15:47 +0800 Message-Id: <20190722081547.56100-5-ray.ni@intel.com> In-Reply-To: <20190722081547.56100-1-ray.ni@intel.com> References: <20190722081547.56100-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1563783390; bh=EdQRDLXjvyC8mp8rZIO0MNfbI/Disd0dReQXAks1PeE=; h=Cc:Date:From:Reply-To:Subject:To; b=oXq29GzraxjfzLHT3WPvzBcX5DCbRbOR5RJSmih6/KuLXcLX0c9LD/R3245qIjw76Yl 0bJG60cgp5vNE/yaVrdlR/6ocAjmc5wgEdFeUzXXacEaW9Ec4XWsWUeBdUcVZQ1UCz/kR b0chfS7TvzlVoq9q8tMMmM2MCORhGhtu/go= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2008 DxeIpl is responsible to create page table for DXE phase running either in long mode or in 32bit mode with certain protection mechanism enabled (refer to ToBuildPageTable()). The patch updates DxeIpl to create 5-level page table for DXE phase running in long mode when PcdUse5LevelPageTable is TRUE and CPU supports 5-level page table. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 + .../Core/DxeIplPeim/X64/VirtualMemory.c | 227 ++++++++++++------ 2 files changed, 151 insertions(+), 77 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index abc3217b01..98bc17fc9d 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -110,6 +110,7 @@ [Pcd.IA32,Pcd.X64] gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##= SOMETIMES_CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index edc38e4525..a5bcdcc734 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -15,7 +15,7 @@ 2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:In= struction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy= stem Programmer's Guide, Intel =20 -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.
=20 SPDX-License-Identifier: BSD-2-Clause-Patent @@ -626,14 +626,19 @@ CreateIdentityMappingPageTables ( ) { UINT32 RegEax; + UINT32 RegEbx; + UINT32 RegEcx; UINT32 RegEdx; UINT8 PhysicalAddressBits; EFI_PHYSICAL_ADDRESS PageAddress; + UINTN IndexOfPml5Entries; UINTN IndexOfPml4Entries; UINTN IndexOfPdpEntries; UINTN IndexOfPageDirectoryEntrie= s; + UINT32 NumberOfPml5EntriesNeeded; UINT32 NumberOfPml4EntriesNeeded; UINT32 NumberOfPdpEntriesNeeded; + PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel5Entry; PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry; PAGE_MAP_AND_DIRECTORY_POINTER *PageMap; PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry; @@ -641,9 +646,11 @@ CreateIdentityMappingPageTables ( UINTN TotalPagesNum; UINTN BigPageAddress; VOID *Hob; + BOOLEAN Page5LevelSupport; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; UINT64 AddressEncMask; + IA32_CR4 Cr4; =20 // // Make sure AddressEncMask is contained to smallest supported address f= ield @@ -677,33 +684,66 @@ CreateIdentityMappingPageTables ( } } =20 + Page5LevelSupport =3D FALSE; + if (PcdGetBool (PcdUse5LevelPageTable)) { + AsmCpuidEx (0x7, 0, &RegEax, &RegEbx, &RegEcx, &RegEdx); + DEBUG ((DEBUG_INFO, "Cpuid(7/0): %08x/%08x/%08x/%08x\n", RegEax, RegEb= x, RegEcx, RegEdx)); + if ((RegEcx & BIT16) !=3D 0) { + Page5LevelSupport =3D TRUE; + } + } + + DEBUG ((DEBUG_INFO, "AddressBits/5LevelPaging/1GPage =3D %d/%d/%d\n", Ph= ysicalAddressBits, Page5LevelSupport, Page1GSupport)); + // - // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses. + // IA-32e paging translates 48-bit linear addresses to 52-bit physical a= ddresses + // when 5-Level Paging is disabled, + // due to either unsupported by HW, or disabled by PCD. // ASSERT (PhysicalAddressBits <=3D 52); - if (PhysicalAddressBits > 48) { + if (!Page5LevelSupport && PhysicalAddressBits > 48) { PhysicalAddressBits =3D 48; } =20 // // Calculate the table entries needed. // - if (PhysicalAddressBits <=3D 39 ) { - NumberOfPml4EntriesNeeded =3D 1; - NumberOfPdpEntriesNeeded =3D (UINT32)LShiftU64 (1, (PhysicalAddressBit= s - 30)); - } else { - NumberOfPml4EntriesNeeded =3D (UINT32)LShiftU64 (1, (PhysicalAddressBi= ts - 39)); - NumberOfPdpEntriesNeeded =3D 512; + NumberOfPml5EntriesNeeded =3D 1; + if (PhysicalAddressBits > 48) { + NumberOfPml5EntriesNeeded =3D (UINT32) LShiftU64 (1, PhysicalAddressBi= ts - 48); + PhysicalAddressBits =3D 48; } =20 + NumberOfPml4EntriesNeeded =3D 1; + if (PhysicalAddressBits > 39) { + NumberOfPml4EntriesNeeded =3D (UINT32) LShiftU64 (1, PhysicalAddressBi= ts - 39); + PhysicalAddressBits =3D 39; + } + + NumberOfPdpEntriesNeeded =3D 1; + ASSERT (PhysicalAddressBits > 30); + NumberOfPdpEntriesNeeded =3D (UINT32) LShiftU64 (1, PhysicalAddressBits = - 30); + // // Pre-allocate big pages to avoid later allocations. // if (!Page1GSupport) { - TotalPagesNum =3D (NumberOfPdpEntriesNeeded + 1) * NumberOfPml4Entries= Needed + 1; + TotalPagesNum =3D ((NumberOfPdpEntriesNeeded + 1) * NumberOfPml4Entrie= sNeeded + 1) * NumberOfPml5EntriesNeeded + 1; } else { - TotalPagesNum =3D NumberOfPml4EntriesNeeded + 1; + TotalPagesNum =3D (NumberOfPml4EntriesNeeded + 1) * NumberOfPml5Entrie= sNeeded + 1; + } + + // + // Substract the one page occupied by PML5 entries if 5-Level Paging is = disabled. + // + if (!Page5LevelSupport) { + TotalPagesNum--; } + + DEBUG ((DEBUG_INFO, "Pml5/Pml4/Pdp/TotalPage =3D %d/%d/%d/%d\n", + NumberOfPml5EntriesNeeded, NumberOfPml4EntriesNeeded, + NumberOfPdpEntriesNeeded, TotalPagesNum)); + BigPageAddress =3D (UINTN) AllocatePageTableMemory (TotalPagesNum); ASSERT (BigPageAddress !=3D 0); =20 @@ -711,92 +751,125 @@ CreateIdentityMappingPageTables ( // By architecture only one PageMapLevel4 exists - so lets allocate stor= age for it. // PageMap =3D (VOID *) BigPageAddress; - BigPageAddress +=3D SIZE_4KB; - - PageMapLevel4Entry =3D PageMap; - PageAddress =3D 0; - for (IndexOfPml4Entries =3D 0; IndexOfPml4Entries < NumberOfPml4EntriesN= eeded; IndexOfPml4Entries++, PageMapLevel4Entry++) { + if (Page5LevelSupport) { // - // Each PML4 entry points to a page of Page Directory Pointer entires. - // So lets allocate space for them and fill them in in the IndexOfPdpE= ntries loop. + // By architecture only one PageMapLevel5 exists - so lets allocate st= orage for it. // - PageDirectoryPointerEntry =3D (VOID *) BigPageAddress; - BigPageAddress +=3D SIZE_4KB; + PageMapLevel5Entry =3D PageMap; + BigPageAddress +=3D SIZE_4KB; + } + PageAddress =3D 0; =20 + for ( IndexOfPml5Entries =3D 0 + ; IndexOfPml5Entries < NumberOfPml5EntriesNeeded + ; IndexOfPml5Entries++, PageMapLevel5Entry++) { // - // Make a PML4 Entry + // Each PML5 entry points to a page of PML4 entires. + // So lets allocate space for them and fill them in in the IndexOfPml4= Entries loop. + // When 5-Level Paging is disabled, below allocation happens only once. // - PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEntr= y | AddressEncMask; - PageMapLevel4Entry->Bits.ReadWrite =3D 1; - PageMapLevel4Entry->Bits.Present =3D 1; + PageMapLevel4Entry =3D (VOID *) BigPageAddress; + BigPageAddress +=3D SIZE_4KB; =20 - if (Page1GSupport) { - PageDirectory1GEntry =3D (VOID *) PageDirectoryPointerEntry; + if (Page5LevelSupport) { + // + // Make a PML5 Entry + // + PageMapLevel5Entry->Uint64 =3D (UINT64) (UINTN) PageMapLevel4Entry; + PageMapLevel5Entry->Bits.ReadWrite =3D 1; + PageMapLevel5Entry->Bits.Present =3D 1; + } =20 - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries = < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += =3D SIZE_1GB) { - if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSize)= ) { - Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry, S= tackBase, StackSize); - } else { - // - // Fill in the Page Directory entries - // - PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | AddressEn= cMask; - PageDirectory1GEntry->Bits.ReadWrite =3D 1; - PageDirectory1GEntry->Bits.Present =3D 1; - PageDirectory1GEntry->Bits.MustBe1 =3D 1; - } - } - } else { - for (IndexOfPdpEntries =3D 0; IndexOfPdpEntries < NumberOfPdpEntries= Needed; IndexOfPdpEntries++, PageDirectoryPointerEntry++) { - // - // Each Directory Pointer entries points to a page of Page Directo= ry entires. - // So allocate space for them and fill them in in the IndexOfPageD= irectoryEntries loop. - // - PageDirectoryEntry =3D (VOID *) BigPageAddress; - BigPageAddress +=3D SIZE_4KB; + for ( IndexOfPml4Entries =3D 0 + ; IndexOfPml4Entries < (NumberOfPml5EntriesNeeded =3D=3D 1 ? Numbe= rOfPml4EntriesNeeded : 512) + ; IndexOfPml4Entries++, PageMapLevel4Entry++) { + // + // Each PML4 entry points to a page of Page Directory Pointer entire= s. + // So lets allocate space for them and fill them in in the IndexOfPd= pEntries loop. + // + PageDirectoryPointerEntry =3D (VOID *) BigPageAddress; + BigPageAddress +=3D SIZE_4KB; =20 - // - // Fill in a Page Directory Pointer Entries - // - PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirectory= Entry | AddressEncMask; - PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; - PageDirectoryPointerEntry->Bits.Present =3D 1; + // + // Make a PML4 Entry + // + PageMapLevel4Entry->Uint64 =3D (UINT64)(UINTN)PageDirectoryPointerEn= try | AddressEncMask; + PageMapLevel4Entry->Bits.ReadWrite =3D 1; + PageMapLevel4Entry->Bits.Present =3D 1; =20 - for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += =3D SIZE_2MB) { - if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackSiz= e)) { - // - // Need to split this 2M page that covers NULL or stack range. - // - Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize); + if (Page1GSupport) { + PageDirectory1GEntry =3D (VOID *) PageDirectoryPointerEntry; + + for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress= +=3D SIZE_1GB) { + if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSiz= e)) { + Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry,= StackBase, StackSize); } else { // // Fill in the Page Directory entries // - PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | AddressEn= cMask; - PageDirectoryEntry->Bits.ReadWrite =3D 1; - PageDirectoryEntry->Bits.Present =3D 1; - PageDirectoryEntry->Bits.MustBe1 =3D 1; + PageDirectory1GEntry->Uint64 =3D (UINT64)PageAddress | Address= EncMask; + PageDirectory1GEntry->Bits.ReadWrite =3D 1; + PageDirectory1GEntry->Bits.Present =3D 1; + PageDirectory1GEntry->Bits.MustBe1 =3D 1; } } - } + } else { + for ( IndexOfPdpEntries =3D 0 + ; IndexOfPdpEntries < (NumberOfPml4EntriesNeeded =3D=3D 1 ? Nu= mberOfPdpEntriesNeeded : 512) + ; IndexOfPdpEntries++, PageDirectoryPointerEntry++) { + // + // Each Directory Pointer entries points to a page of Page Direc= tory entires. + // So allocate space for them and fill them in in the IndexOfPag= eDirectoryEntries loop. + // + PageDirectoryEntry =3D (VOID *) BigPageAddress; + BigPageAddress +=3D SIZE_4KB; =20 - for (; IndexOfPdpEntries < 512; IndexOfPdpEntries++, PageDirectoryPo= interEntry++) { - ZeroMem ( - PageDirectoryPointerEntry, - sizeof(PAGE_MAP_AND_DIRECTORY_POINTER) - ); + // + // Fill in a Page Directory Pointer Entries + // + PageDirectoryPointerEntry->Uint64 =3D (UINT64)(UINTN)PageDirecto= ryEntry | AddressEncMask; + PageDirectoryPointerEntry->Bits.ReadWrite =3D 1; + PageDirectoryPointerEntry->Bits.Present =3D 1; + + for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntr= ies < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress= +=3D SIZE_2MB) { + if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackS= ize)) { + // + // Need to split this 2M page that covers NULL or stack rang= e. + // + Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry,= StackBase, StackSize); + } else { + // + // Fill in the Page Directory entries + // + PageDirectoryEntry->Uint64 =3D (UINT64)PageAddress | Address= EncMask; + PageDirectoryEntry->Bits.ReadWrite =3D 1; + PageDirectoryEntry->Bits.Present =3D 1; + PageDirectoryEntry->Bits.MustBe1 =3D 1; + } + } + } + + // + // Fill with null entry for unused PDPTE + // + ZeroMem (PageDirectoryPointerEntry, (512 - IndexOfPdpEntries) * si= zeof(PAGE_MAP_AND_DIRECTORY_POINTER)); } } + + // + // For the PML4 entries we are not using fill in a null entry. + // + ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE= _MAP_AND_DIRECTORY_POINTER)); } =20 - // - // For the PML4 entries we are not using fill in a null entry. - // - for (; IndexOfPml4Entries < 512; IndexOfPml4Entries++, PageMapLevel4Entr= y++) { - ZeroMem ( - PageMapLevel4Entry, - sizeof (PAGE_MAP_AND_DIRECTORY_POINTER) - ); + if (Page5LevelSupport) { + Cr4.UintN =3D AsmReadCr4 (); + Cr4.Bits.LA57 =3D 1; + AsmWriteCr4 (Cr4.UintN); + // + // For the PML5 entries we are not using fill in a null entry. + // + ZeroMem (PageMapLevel5Entry, (512 - IndexOfPml5Entries) * sizeof (PAGE= _MAP_AND_DIRECTORY_POINTER)); } =20 // --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#44118): https://edk2.groups.io/g/devel/message/44118 Mute This Topic: https://groups.io/mt/32556535/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-