From nobody Fri Mar 29 12:55:42 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+43329+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+43329+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1562298701; cv=none; d=zoho.com; s=zohoarc; b=eblvDfDxMg0RQzKW8rbDilxcFPnqd1HB5gu/4t/6lCKvt2xZgkJnKB4+K5WGO+LFw9szZQvw3lz5luJy5FHviT6DnYoPNR/pw36ERKX3VC2/MBFHhmSEdjFU6bMU/veAFfpHZqGK/SF8tWRdSMLpFQVcHIwDXwf10rwdhJPtVFU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1562298701; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=wRUXjWp4MzmFertIBnrGs4lu52OpDsgf50z2240Wtmg=; b=bQbSMnxkxjTlmGTVpJwzIiwJMUMSTv5wZte3ixbpDsJnZAm3egfTooUZq9fBLV2rX8xPdFRD+trwD9Y/b3TBU0ZN2TltWWlFwF9Aa2hUDXd/OxuOBZJH8+Eyt+luzZCU2koOxUTqlceQrdwOa7oaprhFbIXaNgeDOob5YKf596Y= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+43329+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15622987018261007.341503353341; Thu, 4 Jul 2019 20:51:41 -0700 (PDT) Return-Path: X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by groups.io with SMTP; Thu, 04 Jul 2019 20:51:33 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 04 Jul 2019 20:51:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,453,1557212400"; d="scan'208";a="339735920" X-Received: from ray-dev.ccr.corp.intel.com ([10.239.9.16]) by orsmga005.jf.intel.com with ESMTP; 04 Jul 2019 20:51:31 -0700 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Star Zeng , Michael D Kinney Subject: [edk2-devel] [PATCH] UefiCpuPkg/CpuFeature: Introduce FirstX to indicate 1st unit in parent scope. Date: Fri, 5 Jul 2019 11:51:04 +0800 Message-Id: <20190705035105.237012-1-ray.ni@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ray.ni@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1562298701; bh=5ZEuxUqyOXfhAK4Ap9q/BpIMrsZXfOi+lyhawYD6WxA=; h=Cc:Date:From:Reply-To:Subject:To; b=e43ejUn/lIv/Z8AElkj0rVmwebbMzLcibBngNopUnLkb6ioaGUy2quaWuyLDtvk7Rr1 geqBLS1OPHsd4VPlaCVgPCTmaf4QV1ZLko9UA8PmMtRAVJ0+lE1mGU5OLnn5wLGUON2nB 1dxsQWUMbEizCbJ9LvitjMZC0kkv5HW4n+c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1584 The flow of CPU feature initialization logic is: 1. BSP calls GetConfigDataFunc() for each thread/AP; 2. Each thread/AP calls SupportFunc() to detect its own capability; 3. BSP calls InitializeFunc() for each thead/AP. There is a design gap in step #3. For a package scope feature that only requires one thread of each package does the initialization operation, what InitializeFunc() currently does is to do the initialization operation only CPU physical location Core# is 0. But in certain platform, Core#0 might be disabled in hardware level which results the certain package scope feature isn't initialized at all. The patch adds a new field FistX to indicate the CPU's location in its parent scope. FirstX.Package is set for all APs/threads under first package; FirstX.Core is set for all APs/threads under first core of each package; FirstX.Thread is set for the AP/thread of each core. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Star Zeng Cc: Michael D Kinney Reviewed-by: Eric Dong --- .../Include/Library/RegisterCpuFeaturesLib.h | 19 +++++ .../CpuFeaturesInitialize.c | 74 +++++++++++++++++++ 2 files changed, 93 insertions(+) diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuP= kg/Include/Library/RegisterCpuFeaturesLib.h index 6f964027be..7c1e122ed7 100644 --- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h +++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h @@ -78,6 +78,20 @@ #define CPU_FEATURE_END MAX_UINT32 /// @} =20 +/// +/// The bit field to indicate whether the CPU is the first in its parent s= cope. +/// +typedef struct { + UINT32 Thread : 1; + UINT32 Core : 1; + UINT32 Module : 1; + UINT32 Tile : 1; + UINT32 Die : 1; + UINT32 Package : 1; + UINT32 Reserved : 26; +} REGISTER_CPU_FEATURE_FIRST_X; + =20 + /// /// CPU Information passed into the SupportFunc and InitializeFunc of the /// RegisterCpuFeature() library function. This structure contains inform= ation @@ -88,6 +102,11 @@ typedef struct { /// The package that the CPU resides /// EFI_PROCESSOR_INFORMATION ProcessorInfo; + + /// + /// The bit flag indicating whether the CPU is the first Thread/Core/Mod= ule/Tile/Die/Package in its parent scope. + /// + REGISTER_CPU_FEATURE_FIRST_X FirstX; /// /// The Display Family of the CPU computed from CPUID leaf CPUID_VERSION= _INFO /// diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitializ= e.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index aff7ad600c..c7858bc3a8 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -110,6 +110,9 @@ CpuInitDataInitialize ( EFI_CPU_PHYSICAL_LOCATION *Location; BOOLEAN *CoresVisited; UINTN Index; + UINT32 PackageIndex; + UINT32 CoreIndex; + UINT32 FirstIndex; ACPI_CPU_DATA *AcpiCpuData; CPU_STATUS_INFORMATION *CpuStatus; UINT32 *ValidCoreCountPerPackage; @@ -239,6 +242,77 @@ CpuInitDataInitialize ( ASSERT (CpuFeaturesData->CpuFlags.CoreSemaphoreCount !=3D NULL); CpuFeaturesData->CpuFlags.PackageSemaphoreCount =3D AllocateZeroPool (si= zeof (UINT32) * CpuStatus->PackageCount * CpuStatus->MaxCoreCount * CpuStat= us->MaxThreadCount); ASSERT (CpuFeaturesData->CpuFlags.PackageSemaphoreCount !=3D NULL); + + // + // Initialize CpuFeaturesData->InitOrder[].CpuInfo.FirstX + // + =20 + // + // Set FirstX.Package for each thread belonging to the first package. + // + FirstIndex =3D MAX_UINT32; + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorNum= ber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.Proc= essorInfo.Location; + FirstIndex =3D MIN (Location->Package, FirstIndex); + } + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorNum= ber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.Proc= essorInfo.Location; + if (Location->Package =3D=3D FirstIndex) { + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.FirstX.Package = =3D 1; + } + } + + // + // Set FirstX.Die/Tile/Module for each thread assuming: + // single Die under each package, single Tile under each Die, single Mo= dule under each Tile + // + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorNum= ber++) { + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.FirstX.Die =3D 1; + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.FirstX.Tile =3D 1; + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.FirstX.Module =3D = 1; + } + + for (PackageIndex =3D 0; PackageIndex < CpuStatus->PackageCount; Package= Index++) { + // + // Set FirstX.Core for each thread belonging to the first core of each= package. + // + FirstIndex =3D MAX_UINT32; + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorN= umber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.Pr= ocessorInfo.Location; + if (Location->Package =3D=3D PackageIndex) { + FirstIndex =3D MIN (Location->Core, FirstIndex); + } + } + + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; ProcessorN= umber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.Pr= ocessorInfo.Location; + if (Location->Package =3D=3D PackageIndex && Location->Core =3D=3D F= irstIndex) { + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.FirstX.Core = =3D 1; + } + } + } + + for (PackageIndex =3D 0; PackageIndex < CpuStatus->PackageCount; Package= Index++) { + for (CoreIndex =3D 0; CoreIndex < CpuStatus->MaxCoreCount; CoreIndex++= ) { + // + // Set FirstX.Thread for the first thread of each core. + // + FirstIndex =3D MAX_UINT32; + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; Processo= rNumber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.= ProcessorInfo.Location; + if (Location->Package =3D=3D PackageIndex && Location->Core =3D=3D= CoreIndex) { + FirstIndex =3D MIN (Location->Thread, FirstIndex); + } + } + + for (ProcessorNumber =3D 0; ProcessorNumber < NumberOfCpus; Processo= rNumber++) { + Location =3D &CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.= ProcessorInfo.Location; + if (Location->Package =3D=3D PackageIndex && Location->Core =3D=3D= CoreIndex && Location->Thread =3D=3D FirstIndex) { + CpuFeaturesData->InitOrder[ProcessorNumber].CpuInfo.FirstX.Threa= d =3D 1; + } + } + } + } } =20 /** --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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