From nobody Mon May 6 06:32:24 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+43075+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+43075+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1561950489; cv=none; d=zoho.com; s=zohoarc; b=OM4ecoAtfXeUoFvorR8nTS1GSCguL9vcm00tLLmYu+UJVga7PY0A1CebHgoh5kr6FFjMeKQAM3BFi6w6CZM1MtxY9t3a9zeAgQ3XBBtcLLt1ORvmSf9hztkb9rTXraKXO7uRJZAWwg5JB6+XF9BTNRYVl7r+QZzSWGGRpQR3yXg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561950489; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=+JvzbGId/1p1WR5ParsmHdH8M/G+S0n6tyZwYWsViE8=; b=MN3qKKxh6pN62BYuTqjhXNoE4CA03E6w1ssKxak/kuD1jqUAZ39Ve/POV/ZolxV/K/WoftwGQ24iU59azd+iyoGlWfd9LFUDA5z8dsDRtHjhOCJYFMjsctGhUtpreZbVCINcf00gCkrIt0dBTKRcENsNy10Awa+ZpyYQV9OUSmg= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+43075+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 156195048848321.544440605119917; Sun, 30 Jun 2019 20:08:08 -0700 (PDT) Return-Path: X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by groups.io with SMTP; Sun, 30 Jun 2019 20:07:31 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Jun 2019 20:07:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,437,1557212400"; d="scan'208";a="338482507" X-Received: from mdkinney-mobl2.amr.corp.intel.com ([10.251.143.61]) by orsmga005.jf.intel.com with ESMTP; 30 Jun 2019 20:07:11 -0700 From: "Michael D Kinney" To: devel@edk2.groups.io Cc: Zailiang Sun , Yi Qian Subject: [edk2-devel] [edk2-non-osi Patch] Vlv2SocBinPkg: Add initial binaries for Vlv2TbltDevicePkg Date: Sun, 30 Jun 2019 20:07:07 -0700 Message-Id: <20190701030707.5848-1-michael.d.kinney@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1561950487; bh=lJZPh0ksonnGuXS77+7uBQETXMyV2c69odNoKVacczU=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=UYt/AVbz7o4axXGKjbpZEc3j87Ic8mbozp5ddNdvIA11d8f8ljgrXqOoSORes9Jejtr d5sGczf7nfUriHbPFZmuteRElePIWGAJyclLxzX4Usv/J9km5lvTnBGwRUlxYfnWdRHoN dYR+JV+OCsWz3a7qs9pEm2JFGxgwQ/81Rbk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add the initial version of the binaries required to build Vlv2TbltDevicePkg in the edk2-platform repository Cc: Zailiang Sun Cc: Yi Qian Signed-off-by: Michael D Kinney --- .../RELEASE_VS2008x86/IA32/IntelGopDriver.efi | Bin 0 -> 60192 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../RELEASE_VS2008x86/X64/IntelGopDriver.efi | Bin 0 -> 75008 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../GOP/7.2.1011/VBT/MNW2/Vbt.bin | Bin 0 -> 4096 bytes .../GOP/7.2.1011/VBT/MNW2/vbt.bsf | 9216 +++++++++++ .../IA32DEBUG/IA32/CpuPeim.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.efi | Bin 0 -> 10624 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.inf | 137 + .../IA32DEBUG/IA32/DigitalThermalSensor.depex | 1 + .../IA32DEBUG/IA32/DigitalThermalSensor.efi | Bin 0 -> 14848 bytes .../IA32DEBUG/IA32/DigitalThermalSensor.inf | 190 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.efi | Bin 0 -> 12704 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.inf | 219 + .../IA32DEBUG/IA32/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../IA32DEBUG/IA32/GraphicDxeInitSmm.efi | Bin 0 -> 25088 bytes .../IA32DEBUG/IA32/GraphicDxeInitSmm.inf | 265 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.efi | Bin 0 -> 17984 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/ISPDxe.inf | 247 + .../IA32DEBUG/IA32/MemoryInit.depex | 1 + .../IA32DEBUG/IA32/MemoryInit.efi | Bin 0 -> 98304 bytes .../IA32DEBUG/IA32/MemoryInit.inf | 201 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../IA32DEBUG/IA32/PchBiosWriteProtect.depex | 1 + .../IA32DEBUG/IA32/PchBiosWriteProtect.efi | Bin 0 -> 11264 bytes .../IA32DEBUG/IA32/PchBiosWriteProtect.inf | 130 + .../IA32DEBUG/IA32/PchEarlyInitPeim.depex | 1 + .../IA32DEBUG/IA32/PchEarlyInitPeim.efi | Bin 0 -> 15040 bytes .../IA32DEBUG/IA32/PchEarlyInitPeim.inf | 97 + .../IA32DEBUG/IA32/PchInitDxe.depex | Bin 0 -> 126 bytes .../IA32DEBUG/IA32/PchInitDxe.efi | Bin 0 -> 102496 bytes .../IA32DEBUG/IA32/PchInitDxe.inf | 278 + .../IA32DEBUG/IA32/PchInitPeim.depex | 1 + .../IA32DEBUG/IA32/PchInitPeim.efi | Bin 0 -> 22976 bytes .../IA32DEBUG/IA32/PchInitPeim.inf | 150 + .../IA32DEBUG/IA32/PchInitSmm.depex | Bin 0 -> 162 bytes .../IA32DEBUG/IA32/PchInitSmm.efi | Bin 0 -> 35840 bytes .../IA32DEBUG/IA32/PchInitSmm.inf | 290 + .../IA32DEBUG/IA32/PchPcieSmm.depex | Bin 0 -> 108 bytes .../IA32DEBUG/IA32/PchPcieSmm.efi | Bin 0 -> 26112 bytes .../IA32DEBUG/IA32/PchPcieSmm.inf | 251 + .../IA32DEBUG/IA32/PchPolicyInitDxe.depex | 1 + .../IA32DEBUG/IA32/PchPolicyInitDxe.efi | Bin 0 -> 9440 bytes .../IA32DEBUG/IA32/PchPolicyInitDxe.inf | 123 + .../IA32DEBUG/IA32/PchReset.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchReset.efi | Bin 0 -> 12288 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchReset.inf | 137 + .../IA32DEBUG/IA32/PchS3SupportDxe.depex | 1 + .../IA32DEBUG/IA32/PchS3SupportDxe.efi | Bin 0 -> 25760 bytes .../IA32DEBUG/IA32/PchS3SupportDxe.inf | 257 + .../IA32DEBUG/IA32/PchSmbusArpDisabled.depex | 1 + .../IA32DEBUG/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 7616 bytes .../IA32DEBUG/IA32/PchSmbusArpDisabled.inf | 144 + .../IA32DEBUG/IA32/PchSmbusDxe.depex | 1 + .../IA32DEBUG/IA32/PchSmbusDxe.efi | Bin 0 -> 15552 bytes .../IA32DEBUG/IA32/PchSmbusDxe.inf | 214 + .../IA32DEBUG/IA32/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../IA32DEBUG/IA32/PchSmiDispatcher.efi | Bin 0 -> 24576 bytes .../IA32DEBUG/IA32/PchSmiDispatcher.inf | 181 + .../IA32DEBUG/IA32/PchSpiPeim.depex | 1 + .../IA32DEBUG/IA32/PchSpiPeim.efi | Bin 0 -> 10304 bytes .../IA32DEBUG/IA32/PchSpiPeim.inf | 139 + .../IA32DEBUG/IA32/PchSpiRuntime.depex | 1 + .../IA32DEBUG/IA32/PchSpiRuntime.efi | Bin 0 -> 23552 bytes .../IA32DEBUG/IA32/PchSpiRuntime.inf | 258 + .../IA32DEBUG/IA32/PchSpiSmm.depex | 1 + .../IA32DEBUG/IA32/PchSpiSmm.efi | Bin 0 -> 24064 bytes .../IA32DEBUG/IA32/PchSpiSmm.inf | 251 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.efi | Bin 0 -> 5984 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.inf | 137 + .../IA32DEBUG/IA32/PciHostBridge.depex | Bin 0 -> 54 bytes .../IA32DEBUG/IA32/PciHostBridge.efi | Bin 0 -> 22336 bytes .../IA32DEBUG/IA32/PciHostBridge.inf | 254 + .../IA32DEBUG/IA32/PeiSmmAccess.depex | 1 + .../IA32DEBUG/IA32/PeiSmmAccess.efi | Bin 0 -> 6208 bytes .../IA32DEBUG/IA32/PeiSmmAccess.inf | 132 + .../IA32DEBUG/IA32/PeiSmmControl.depex | 1 + .../IA32DEBUG/IA32/PeiSmmControl.efi | Bin 0 -> 5120 bytes .../IA32DEBUG/IA32/PeiSmmControl.inf | 110 + .../IA32DEBUG/IA32/PlatformCpuPolicy.depex | Bin 0 -> 72 bytes .../IA32DEBUG/IA32/PlatformCpuPolicy.efi | Bin 0 -> 17632 bytes .../IA32DEBUG/IA32/PlatformCpuPolicy.inf | 227 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.efi | Bin 0 -> 17472 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/PnpDxe.inf | 207 + .../IA32DEBUG/IA32/PowerManagement2.depex | 1 + .../IA32DEBUG/IA32/PowerManagement2.efi | Bin 0 -> 36352 bytes .../IA32DEBUG/IA32/PowerManagement2.inf | 270 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/ResetVec.com | Bin 0 -> 64 bytes .../IA32DEBUG/IA32/SataController.efi | Bin 0 -> 12128 bytes .../IA32DEBUG/IA32/SataController.inf | 204 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.efi | Bin 0 -> 7456 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/SeCUma.inf | 116 + .../Vlv2SocBinPkg/IA32DEBUG/IA32/SecCore.efi | Bin 0 -> 8864 bytes .../Vlv2SocBinPkg/IA32DEBUG/IA32/SecCore.inf | 130 + .../IA32DEBUG/IA32/SmmAccess.depex | Bin 0 -> 36 bytes .../IA32DEBUG/IA32/SmmAccess.efi | Bin 0 -> 10336 bytes .../IA32DEBUG/IA32/SmmAccess.inf | 210 + .../IA32DEBUG/IA32/SmmControl.depex | 1 + .../IA32DEBUG/IA32/SmmControl.efi | Bin 0 -> 11776 bytes .../IA32DEBUG/IA32/SmmControl.inf | 129 + .../IA32DEBUG/IA32/VlvInitDxe.depex | Bin 0 -> 126 bytes .../IA32DEBUG/IA32/VlvInitDxe.efi | Bin 0 -> 26656 bytes .../IA32DEBUG/IA32/VlvInitDxe.inf | 259 + .../IA32DEBUG/IA32/VlvInitPeim.depex | 1 + .../IA32DEBUG/IA32/VlvInitPeim.efi | Bin 0 -> 9120 bytes .../IA32DEBUG/IA32/VlvInitPeim.inf | 116 + .../IA32RELEASE/IA32/CpuPeim.depex | 1 + .../IA32RELEASE/IA32/CpuPeim.efi | Bin 0 -> 6080 bytes .../IA32RELEASE/IA32/CpuPeim.inf | 123 + .../IA32/DigitalThermalSensor.depex | 1 + .../IA32RELEASE/IA32/DigitalThermalSensor.efi | Bin 0 -> 6144 bytes .../IA32RELEASE/IA32/DigitalThermalSensor.inf | 182 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.depex | Bin 0 -> 108 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.efi | Bin 0 -> 3872 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/Dptf.inf | 213 + .../IA32RELEASE/IA32/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../IA32RELEASE/IA32/GraphicDxeInitSmm.efi | Bin 0 -> 9216 bytes .../IA32RELEASE/IA32/GraphicDxeInitSmm.inf | 259 + .../IA32RELEASE/IA32/ISPDxe.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.efi | Bin 0 -> 6144 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.inf | 241 + .../IA32RELEASE/IA32/MemoryInit.depex | 1 + .../IA32RELEASE/IA32/MemoryInit.efi | Bin 0 -> 93888 bytes .../IA32RELEASE/IA32/MemoryInit.inf | 196 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../IA32/PchBiosWriteProtect.depex | 1 + .../IA32RELEASE/IA32/PchBiosWriteProtect.efi | Bin 0 -> 2560 bytes .../IA32RELEASE/IA32/PchBiosWriteProtect.inf | 121 + .../IA32RELEASE/IA32/PchEarlyInitPeim.depex | 1 + .../IA32RELEASE/IA32/PchEarlyInitPeim.efi | Bin 0 -> 14752 bytes .../IA32RELEASE/IA32/PchEarlyInitPeim.inf | 97 + .../IA32RELEASE/IA32/PchInitDxe.depex | Bin 0 -> 126 bytes .../IA32RELEASE/IA32/PchInitDxe.efi | Bin 0 -> 61536 bytes .../IA32RELEASE/IA32/PchInitDxe.inf | 272 + .../IA32RELEASE/IA32/PchInitPeim.depex | 1 + .../IA32RELEASE/IA32/PchInitPeim.efi | Bin 0 -> 11776 bytes .../IA32RELEASE/IA32/PchInitPeim.inf | 136 + .../IA32RELEASE/IA32/PchInitSmm.depex | Bin 0 -> 162 bytes .../IA32RELEASE/IA32/PchInitSmm.efi | Bin 0 -> 18432 bytes .../IA32RELEASE/IA32/PchInitSmm.inf | 284 + .../IA32RELEASE/IA32/PchPcieSmm.depex | Bin 0 -> 108 bytes .../IA32RELEASE/IA32/PchPcieSmm.efi | Bin 0 -> 11264 bytes .../IA32RELEASE/IA32/PchPcieSmm.inf | 245 + .../IA32RELEASE/IA32/PchPolicyInitDxe.depex | 1 + .../IA32RELEASE/IA32/PchPolicyInitDxe.efi | Bin 0 -> 2368 bytes .../IA32RELEASE/IA32/PchPolicyInitDxe.inf | 109 + .../IA32RELEASE/IA32/PchReset.depex | 1 + .../IA32RELEASE/IA32/PchReset.efi | Bin 0 -> 3584 bytes .../IA32RELEASE/IA32/PchReset.inf | 130 + .../IA32RELEASE/IA32/PchS3SupportDxe.depex | 1 + .../IA32RELEASE/IA32/PchS3SupportDxe.efi | Bin 0 -> 13472 bytes .../IA32RELEASE/IA32/PchS3SupportDxe.inf | 251 + .../IA32/PchSmbusArpDisabled.depex | 1 + .../IA32RELEASE/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 3136 bytes .../IA32RELEASE/IA32/PchSmbusArpDisabled.inf | 130 + .../IA32RELEASE/IA32/PchSmbusDxe.depex | 1 + .../IA32RELEASE/IA32/PchSmbusDxe.efi | Bin 0 -> 4832 bytes .../IA32RELEASE/IA32/PchSmbusDxe.inf | 206 + .../IA32RELEASE/IA32/PchSmiDispatcher.depex | Bin 0 -> 72 bytes .../IA32RELEASE/IA32/PchSmiDispatcher.efi | Bin 0 -> 12288 bytes .../IA32RELEASE/IA32/PchSmiDispatcher.inf | 175 + .../IA32RELEASE/IA32/PchSpiPeim.depex | 1 + .../IA32RELEASE/IA32/PchSpiPeim.efi | Bin 0 -> 4384 bytes .../IA32RELEASE/IA32/PchSpiPeim.inf | 125 + .../IA32RELEASE/IA32/PchSpiRuntime.depex | 1 + .../IA32RELEASE/IA32/PchSpiRuntime.efi | Bin 0 -> 10240 bytes .../IA32RELEASE/IA32/PchSpiRuntime.inf | 252 + .../IA32RELEASE/IA32/PchSpiSmm.depex | 1 + .../IA32RELEASE/IA32/PchSpiSmm.efi | Bin 0 -> 9728 bytes .../IA32RELEASE/IA32/PchSpiSmm.inf | 245 + .../IA32RELEASE/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.efi | Bin 0 -> 1344 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PchUsb.inf | 124 + .../IA32RELEASE/IA32/PciHostBridge.depex | Bin 0 -> 54 bytes .../IA32RELEASE/IA32/PciHostBridge.efi | Bin 0 -> 9792 bytes .../IA32RELEASE/IA32/PciHostBridge.inf | 248 + .../IA32RELEASE/IA32/PeiSmmAccess.depex | 1 + .../IA32RELEASE/IA32/PeiSmmAccess.efi | Bin 0 -> 1664 bytes .../IA32RELEASE/IA32/PeiSmmAccess.inf | 119 + .../IA32RELEASE/IA32/PeiSmmControl.depex | 1 + .../IA32RELEASE/IA32/PeiSmmControl.efi | Bin 0 -> 960 bytes .../IA32RELEASE/IA32/PeiSmmControl.inf | 95 + .../IA32RELEASE/IA32/PlatformCpuPolicy.depex | Bin 0 -> 72 bytes .../IA32RELEASE/IA32/PlatformCpuPolicy.efi | Bin 0 -> 8064 bytes .../IA32RELEASE/IA32/PlatformCpuPolicy.inf | 216 + .../IA32RELEASE/IA32/PnpDxe.depex | Bin 0 -> 36 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PnpDxe.efi | Bin 0 -> 9664 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/PnpDxe.inf | 200 + .../IA32RELEASE/IA32/PowerManagement2.depex | 1 + .../IA32RELEASE/IA32/PowerManagement2.efi | Bin 0 -> 18432 bytes .../IA32RELEASE/IA32/PowerManagement2.inf | 264 + .../IA32RELEASE/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../IA32RELEASE/IA32/ResetVec.com | Bin 0 -> 64 bytes .../IA32RELEASE/IA32/SataController.efi | Bin 0 -> 3264 bytes .../IA32RELEASE/IA32/SataController.inf | 195 + .../IA32RELEASE/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.efi | Bin 0 -> 1856 bytes .../Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.inf | 101 + .../IA32RELEASE/IA32/SecCore.efi | Bin 0 -> 8000 bytes .../IA32RELEASE/IA32/SecCore.inf | 152 + .../IA32RELEASE/IA32/SmmAccess.depex | Bin 0 -> 36 bytes .../IA32RELEASE/IA32/SmmAccess.efi | Bin 0 -> 1984 bytes .../IA32RELEASE/IA32/SmmAccess.inf | 198 + .../IA32RELEASE/IA32/SmmControl.depex | 1 + .../IA32RELEASE/IA32/SmmControl.efi | Bin 0 -> 3072 bytes .../IA32RELEASE/IA32/SmmControl.inf | 122 + .../IA32RELEASE/IA32/VlvInitDxe.depex | Bin 0 -> 126 bytes .../IA32RELEASE/IA32/VlvInitDxe.efi | Bin 0 -> 16640 bytes .../IA32RELEASE/IA32/VlvInitDxe.inf | 253 + .../IA32RELEASE/IA32/VlvInitPeim.depex | 1 + .../IA32RELEASE/IA32/VlvInitPeim.efi | Bin 0 -> 3104 bytes .../IA32RELEASE/IA32/VlvInitPeim.inf | 101 + .../Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h | 72 + .../Vlv2SocBinPkg/Microcode/M0130673321.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130678806.inc | 12800 +++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679901.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679906.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0130679907.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M023067221D.inc | 13056 ++++++++++++++++ .../Vlv2SocBinPkg/Microcode/M0F30679909.inc | 13056 ++++++++++++++++ .../Microcode/MicrocodeUpdates.inf | 51 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/I211PcieUndiDxe/X64/E7006X3.EFI | Bin 0 -> 341536 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/RtkUndiDxe/IA32/RtkUndiDxe.efi | Bin 0 -> 78368 bytes ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../UNDI/RtkUndiDxe/X64/RtkUndiDxe.efi | Bin 0 -> 92064 bytes Silicon/Intel/Vlv2SocBinPkg/Vlv2SocBinPkg.dec | 36 + .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.efi | Bin 0 -> 10624 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.inf | 137 + .../X64DEBUG/IA32/MemoryInit.depex | 1 + .../X64DEBUG/IA32/MemoryInit.efi | Bin 0 -> 98304 bytes .../X64DEBUG/IA32/MemoryInit.inf | 201 + ...MAXUEFIFirmware-LicenseAgreement-Final.txt | 134 + .../X64DEBUG/IA32/PchEarlyInitPeim.depex | 1 + .../X64DEBUG/IA32/PchEarlyInitPeim.efi | Bin 0 -> 15040 bytes .../X64DEBUG/IA32/PchEarlyInitPeim.inf | 97 + .../X64DEBUG/IA32/PchInitPeim.depex | 1 + .../X64DEBUG/IA32/PchInitPeim.efi | Bin 0 -> 22976 bytes .../X64DEBUG/IA32/PchInitPeim.inf | 150 + .../X64DEBUG/IA32/PchSmbusArpDisabled.depex | 1 + .../X64DEBUG/IA32/PchSmbusArpDisabled.efi | Bin 0 -> 7616 bytes .../X64DEBUG/IA32/PchSmbusArpDisabled.inf | 144 + .../X64DEBUG/IA32/PchSpiPeim.depex | 1 + .../X64DEBUG/IA32/PchSpiPeim.efi | Bin 0 -> 10304 bytes .../X64DEBUG/IA32/PchSpiPeim.inf | 139 + .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.efi | Bin 0 -> 5984 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.inf | 137 + .../X64DEBUG/IA32/PeiSmmAccess.depex | 1 + .../X64DEBUG/IA32/PeiSmmAccess.efi | Bin 0 -> 6208 bytes .../X64DEBUG/IA32/PeiSmmAccess.inf | 132 + .../X64DEBUG/IA32/PeiSmmControl.depex | 1 + .../X64DEBUG/IA32/PeiSmmControl.efi | Bin 0 -> 5120 bytes .../X64DEBUG/IA32/PeiSmmControl.inf | 110 + .../Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.bin | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.com | Bin 0 -> 64 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.depex | 1 + .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.efi | Bin 0 -> 7456 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.inf | 116 + .../Vlv2SocBinPkg/X64DEBUG/IA32/SecCore.efi | Bin 0 -> 8864 bytes .../Vlv2SocBinPkg/X64DEBUG/IA32/SecCore.inf | 130 + .../X64DEBUG/IA32/VlvInitPeim.depex | 1 + .../X64DEBUG/IA32/VlvInitPeim.efi | Bin 0 -> 9120 bytes .../X64DEBUG/IA32/VlvInitPeim.inf | 116 + .../X64DEBUG/X64/DigitalThermalSensor.depex | 1 + .../X64DEBUG/X64/DigitalThermalSensor.efi | Bin 0 -> 32768 bytes .../X64DEBUG/X64/DigitalThermalSensor.inf | 190 + .../Vlv2SocBinPkg/X64DEBUG/X64/Dptf.depex | Bin 0 -> 108 bytes .../Intel/Vlv2SocBinPkg/X64DEBUG/X64/Dptf.efi | Bin 0 -> 29120 bytes .../Intel/Vlv2SocBinPkg/X64DEBUG/X64/Dptf.inf | 219 + .../X64DEBUG/X64/GraphicDxeInitSmm.depex | Bin 0 -> 162 bytes .../X64DEBUG/X64/GraphicDxeInitSmm.efi | Bin 0 -> 54272 bytes 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b/Silicon/Intel/Vlv2SocBinPkg/GOP/7.2.1011/RELEASE_VS2008x86/IA32/Minno= wBoardMAXUEFIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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=3DA$|AIE;~o)0A2Vih;f9w|9hH_i|y zyi6}2eD-YNsw;-24_i+F+57>-9Cej?n~o`%PcMxHUE^ntjl7dlGIK1Y@a{}>4^mN? zJe%#T;`hDk^NAX+>4L69+SUD^hWhgPl}_PL%2Dt;x>sO1$IJ#&3zd zpc>bN=3DQ<;}Y)-qEX9L1X#ZRq@+{!Sa)#J4w6vHh<)#Gjx+$yX1b7Oy%IM}{m8`GF)F<%@d(wZhBiPs} zG+bnnLl(MtE-iF( z%DlEvoX6i(n8&lK(92UV%;D>`g~NGP6=3DpD{4vLZ);$QZ{x}4*xfI-A45vr)i;kihO zhY_f%w;@~#*~lz}f<}l_m+CBBP7K>n3UTgXl|)KJYAVuqDL&`0Bpph+R0o!NRFeEU zslhHXTPC%N9#)syRHwA^T!nh`94A6)%KE^gH_wtrb$jYk?I?zWAayjNWtKx9zgvqT z{!b-DnJ#kB>u+9`sgK`M*M7*QH{a|=3DU(QR$q)Q+FMqvE**tXavVkjDX2}`kAdUIfK zqRUm+{!wQ37KAO4_Y!2F0;&a>O6u@3#loazACA16+dM1VpZ)jdKyGs&&!2s?IWVL- z;B5{d*9qr{{|;yV>PX1xnKe{vswx~D&XS*@p>rd%hK`B_tjLf%H?!Fa4`of5HPj{J z&k}Ms6vDuz`ld~md@;YW<=3Dgn0UgVQAy`qrW_p9Pl&O%z}U5k6O34V2WL;C0mIytXT zoeDv0+}(3=3Dz?k1tgih67*v4k*F3^pXRFV)7+Ek zEOlb#CR+$>u*`vCc=3D_@0IC+&tK44V!T-=3D`!*P`tn^KQwTvsXF>c8gM{W%@}mmf@=3D0 z)TE{$=3DCO z)*e3@I_m)LJVqU@Pg2(xd-z>t``_+iiHsoQss<6yK31MDj^Tf$Go7xF7o0MNQm-md zx(HqV?~?g{=3D%huq?cfG0EHLAfN@L5>e}mMTmf~@JDp1rb*Si(d*Nr^Reu`IbsA4v~u6kN$>|D)GJ)Y)7hdah-R$UO4Kg_dA2? zyzgfPqaE1C>&!p+k@t^>>%8CLQ*v;nailW7v@G?xG~qX&S=3DHLD+p&Y@ouDSr->M54 z6~?E_w;{mW7A)R#^mjpg=3DN`0b8(QZ*l(6cdj$_neY&-fpcm#4Fvj4o7V?D_i%-Lv1 zN%>kVA&Qm#`g2MJ!E_B@i*>0U<=3D1)dP5j+kpKy3b4y;l2id*MWZ#(r$`2z~4Ic)lP zuj*IF?^P$95*r#RMb}Bur}pIcR*C7JSieE!2rIW8+vusQBwr}Iszq*8a~#_m+|wP( zx0(mldyNH, ). Points should = be " + "listed in monotonically increasing order by ambient light= " + "illuminance (lux). A minimum of two points are required " + "(min and max)." + EndPage + + EndPage + EndPage =20 +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Display Configuration +;-------------------------------------------------------------------------= ----- + +Page "Display Configuration" + + Link "LFP" , "LFP" + Link "CRT" , "CRT" + Link "EFP 1" , "EFP 1" + Link "EFP 2" , "EFP 2" +=09 + TitleB "DisplayPort SSC configuration: "=20 + Combo $DP_SSC_Enb, " DisplayPort (External Connectors) Spread Spectrum= Clock:", &Disabled_Enabled_List, + Help "This feature allow OEMs to enable/disable SSC for external Displ= ayPort. " + "This feature is valid only the attached DisplayPort panel support SSC= . " + "\r\n" + + Combo $DP_SSC_Dongle_Enb, " DisplayPort Spread Spectrum Clock Enable/D= isable for Dongles:", &Disabled_Enabled_List, + Help "This feature is to enable or disable DisplayPort Dongle Spread S= pectrum Clock when dongle are used " + "and the attached DisplayPort panel should support SSC\r\n" + +=09 + Page "LFP" + Link "Close Table", ".." + =09 + Combo $Int_LFP1_Type , "Active Local Flat Panel Configuration",= &eDP_Config_List, + Help "This option select Device type. Save the configuration af= ter selecting this field to see display related settings." + + ; #IF ($Int_LFP1_Type =3D=3D 0x1806) + Combo $Int_LFP1_Port, "Select Output Port:", &LFP_Port_list, + Help "This feature specifies which DVO port the device is " + ;#ENDIF + =09 + Combo $Int_LFP1_AUX_Channel, "Select AUX Channel:", &Int_eDP_AUX_Channe= l_List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Device Type.= " =09 + =09 + ;Combo $Int_LFP1_Priority, "Primary LFP panel: ", &Yes_No_List, + ;Help "This feature will select if the panel is primary or not.= " + ; "The VLV platform has only one panel fitter. So, stretche= d mode will be only applicable " + ; "to primary panel . In secondary panel only native mode o= r " + ; "centering modes will be supported." + =09 + Combo $bmp_Panel_type, "Select Panel Type:", &Panel_List,=20 + Help "This feature selects the Local Flat Panel (LFP) the VBIOS= " + "and driver is to enable.\r\n"=20 + "\r\n" + "Note, a valid return from the system BIOS hook 5F40h will= " + "replace this default value.\r\n" + "\r\n" + "Default LFP parameter values:\r\n" + "\tPANEL #01: 640x480 LVDS\r\n" + "\tPANEL #02: 800x600 LVDS\r\n" + "\tPANEL #03: 1024x768 LVDS\r\n" + "\tPANEL #04: 1280x1024 LVDS\r\n " + "\tPANEL #05: 1400x1050 Reduced Blanking LVDS\r\n" + "\tPANEL #06: 1400x1050 Non-Reduced Blanking LVDS\r\n" + "\tPANEL #07: 1600x1200 LVDS\r\n" + "\tPANEL #08: 1280x768 LVDS\r\n" + "\tPANEL #09: 1680x1050 LVDS\r\n" + "\tPANEL #10: 1920x1200 LVDS\r\n" + "\tPANEL #11: Reserved\r\n" + "\tPANEL #12: Reserved\r\n " + "\tPANEL #13: Reserved\r\n" + "\tPANEL #14: 1280x800 LVDS\r\n" + "\tPANEL #15: 1280x600 LVDS\r\n" + "\tPANEL #16: Reserved" =20 + =09 + Combo $bmp_Panel_EDID, "Local Flat Panel (LFP) EDID Support: ", = &Disabled_Enabled_List, + Help "This feature, when enabled, will activate support for a L= FP " + "with an EDID. The video BIOS and drivers will load the E= DID " + "and use its data to set appropriate timing on current pan= el. " + "If disabled, there will be no attempt to read an EDID and= other methods " + "will be used to set panel timing." + "\r\n\r\nNote: The backlight data may need to be updated.= "=20 + "\r\n The option on page Gen= eral" + " Features must be correct for platform." + =09 + Combo $180_Deg_Rotation_Enable, "Enable 180 Degree Rotation:", &No_Ye= s_List, + Help "This feature when set to yes, will enable 180 Degree rotation " + "otherwise, the rotation functionality will be disabled." + =09 + Combo $Enable_Correction, "Gamma/Brightness/Contrast Correction Enable:"= , &Disabled_Enabled_List, + Help "This option will allow users to disable/enable Gamma/Brightness/Co= ntrast correction feature for eDP. By default it will be disabled.\r\n" + "On enabling one can find option for entering values for Red/Blue/Gree= n Palette Table under LFP Panel configuration.\r\n" + "Each Red/Blue/Green Palette Table has 256 entries/rows of 1-byte each= . Enter required values in these fields.\r\n" + =09 + EndPage =20 +=09 +=09 + + Page "CRT" + Link "Close Window" , ".." + + Combo $Int_CRT_Support, "CRT Device:", &Int_CRT_Device_Type_Lis= t, + Help "This option select CRT Device." + + Combo $CRT_DDC_GMBUS_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_Lis= t, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + + EndPage + + Page "EFP 1" + Link "Close Window" , ".." + + Combo $Int_EFP1_Type, "Device Type", &Int_EFP_Device_Type_List, + Help "This option specifies the Device Type." + + Combo $Int_EFP1_Port, "Select Output Port:", &Int_EFP_Port_List, + Help "This feature specifies which DVO port the device is " + + Combo $Int_EFP1_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + =09 + Combo $Int_EFP1_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel_= List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Devic= e Type."=09 + =09 + Combo $Int_EFP1_HDMI_LS_Type, "Select HDMI level shifter configura= tion:", &Hdmi_LS_List_VLV, + Help "This feature specifies the Level shifter configuration for HDMI. " + "This field is valid only if HDMI is selected for Device Type." + =09 + ;Combo $Int_EFP1_Dongle_Detect, "Select Dongle Detect:", &Disabled_En= abled_List, + ;Help "This option Enables/Disables detection of type of dongle= connected to DP port.\r\n" + ; "This option is used only by the GFX driver." + + Combo $Int_EFP1_Docked_Port, "Dockable: ", &No_Yes_List, + Help "This field describes if the Display Port is routed through Dock or= not."=09 + =09 + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Config= uration" + =09 + Page "DisplayPort Redriver Configuration" + + Combo $EFP1_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_Lis= t, + Help "This feature will describe if Non-dock topology/OnBoard Redriver = DP Link is present or not." + + Combo $EFP1_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_P= reEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" =20 + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n " + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n" + "\t-------------------------------------------------------------------= --------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + +=20 + Combo $EFP1_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" =20 + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n " + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n" + "\t-------------------------------------------------------------------= --------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + =09 + Title " " + + Combo $EFP1_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &N= o_Yes_List, + Help "This feature will describe if Dock Topology/Dock Redriver DP Link= is present or not.\r\n\r\n" + "Note: For Dock Topology to work SBIOS should implement a GOP Policy = Protocol to provide the" + " docking status of the platform to GOP.\n" + =09 + Combo $EFP1_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_Pr= eEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" =20 + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n " + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n" + "\t-------------------------------------------------------------------= --------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + Combo $EFP1_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VS= wing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" =20 + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n " + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n" + "\t-------------------------------------------------------------------= --------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + EndPage ; "DisplayPort Redriver Configuration" + =09 + EndPage + + =20 + Page "EFP 2" + Link "Close Window" , ".." + + Combo $Int_EFP2_Type, "Device Type:", &Int_EFP_Device_Type_List, + Help "This option specifies the Device Type." + + Combo $Int_EFP2_Port, "Select Output Port:", &Int_EFP_Port_List, + Help "This feature specifies which DVO port the device is " + =09 + Combo $Int_EFP2_DDC_Pin, "Select DDC Bus GPIO Pin Pair:", &GPIO_Pin_List, + Help "This feature specifies the GPIO pin pair " + "used as DDC bus by this device. If this device " + "doesn't support DDC bus, this field will be ignored." + =09 + Combo $Int_EFP2_AUX_Channel, "Select AUX Channel:", &Int_DP_AUX_Channel= _List, + Help "This feature specifies the AUX Channel for int-DisplayPort. " + "This field is valid only if integrated DP is selected for Devic= e Type."=09 + + Combo $Int_EFP2_HDMI_LS_Type, "Select HDMI level shifter configura= tion:", &Hdmi_LS_List_VLV, + Help "This feature specifies the Level shifter configuration for HDMI. " + "This field is valid only if HDMI is selected for Device Type." + =20 + ;Combo $Int_EFP2_Dongle_Detect, "Select Dongle Detect:", &Disab= led_Enabled_List, + ;Help "This option Enables/Disables detection of type of dongle= connected to DP port.\r\n" + ; "This option is used only by the GFX driver." + =20 + Combo $Int_EFP2_Docked_Port, "Dockable: ", &No_Yes_List, + Help "This field describes if the Display Port is routed through Dock or= not."=09 + =09 + Link "DisplayPort Redriver Configuration" , "DisplayPort Redriver Config= uration" + =09 + Page "DisplayPort Redriver Configuration" + + Combo $EFP2_OnBoard_Redriver_Present, "Non-dock topology:", &No_Yes_Lis= t, + Help "This feature will describe if Non-dock topology/OnBoard Redriver = DP Link is present or not." + + Combo $EFP2_OnBoard_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_P= reEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" =20 + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n " + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n" + "\t-------------------------------------------------------------------= --------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + +=20 + Combo $EFP2_OnBoard_VSwing_Level, " Voltage Swing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the OnBoard redriver DP link.\n" + "\r\n\n\t\t\tDefault Swing Setting Table\n" =20 + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n " + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n" + "\t-------------------------------------------------------------------= --------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + =09 + Title " " + + Combo $EFP2_OnDock_Redriver_Present, "Dock Topology: (Mobile only)", &N= o_Yes_List, + Help "This feature will describe if Dock Topology/Dock Redriver DP Link= is present or not.\r\n\r\n" + "Note: For Dock Topology to work SBIOS should implement a GOP Policy = Protocol to provide the" + " docking status of the platform to GOP.\n" + + Combo $EFP2_OnDock_PreEmph_Level, " Pre-Emphasis Level:", &eDP_Link_Pr= eEmp_List, + Help "This feature allows for the selection of " + "Pre-emphasis level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" =20 + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n " + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n" + "\t-------------------------------------------------------------------= --------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + Combo $EFP2_OnDock_VSwing_Level, " Voltage Swing Level:", &eDP_Link_VS= wing_List, + Help "This feature allows for the selection of " + "Voltage Swing level for the Dock redriver DP link." + "\r\n\n\t\t\tDefault Swing Setting Table\n" =20 + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t \t | \t\t PreEmphasis Levels\t\t |\n" + "\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Level 2(6.0dB) = | Level 3(9.5dB) |\n " + "\t-------------------------------------------------------------------= --------------------------------\n" + "\t| Level 0(400mV) | 400mV | 600mV | 800= mV | 1200mV |\n" + "\t| Level 1(600mV) | 600mV | 800mV | 120= 0mV | N/A |\n" + "\t| Level 2(800mV) | 800mV | 1200mV | N= /A | N/A |\n" + "\t| Level 3(1200mV) | 1200mV | N/A | = N/A | N/A |\n" + "\t-------------------------------------------------------------------= --------------------------------\n" + "\tColumn - Non-Transition VDiff \r\n" + "\tRow - Transition VDiff \r\n" + + EndPage ; "DisplayPort Redriver Configuration" + =09 + EndPage + =20 + =20 +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +; Page - LFP Panel configuration +;-------------------------------------------------------------------------= --- +Page "LFP Panel configuration" + Link "Panel #1 ", "Panel #1 " + Link "Panel #2 ", "Panel #2 " + Link "Panel #3 ", "Panel #3 " + Link "Panel #4 ", "Panel #4 " + Link "Panel #5 ", "Panel #5 " + Link "Panel #6 ", "Panel #6 " + Link "Panel #7 ", "Panel #7 " + Link "Panel #8 ", "Panel #8 " + Link "Panel #9 ", "Panel #9 " + Link "Panel #10 ", "Panel #10 " + Link "Panel #11 ", "Panel #11 " + Link "Panel #12 ", "Panel #12 " + Link "Panel #13 ", "Panel #13 " + Link "Panel #14 ", "Panel #14 " + Link "Panel #15 ", "Panel #15 " + Link "Panel #16 ", "Panel #16 " +#if($Enable_Correction =3D=3D 1) + Link "RGB Palette Table ", "RGB Palette Table " +#endif=09 + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #1 (640x480) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #1 " + + TitleB "Common LFP Features"=20 +=09 + EditText $Panel_Name_01, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver only. Pane= l name can be only of 13 characters maximum and rest of the characters will= be truncated. " + + Combo $Enable_Scaling_01, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_01, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_01, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + + Combo $DPS_Panel_Type_01, "\tDPS Panel Type:", &DPS_Panel_Type_List, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_01, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + + Combo $Blt_Control_01, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" +=09 +=09 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" +=09 + Combo $Enable_SSC01, "\teDP Spread Spectrum Clock:", &Disabled_Enabled_Li= st, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " +=09 + Combo $eDP_Panel_Color_Depth_01, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + =20 + Combo $eDP_VswingPreEmph_1, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_01, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction" + =09 + EditNum $eDP_Vcc_To_Hpd_Delay_01, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_01, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_01, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_01, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_01, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_01, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_01, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_01, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." =20 + =20 + Combo $eDP_Link_DataRate_01, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_01, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_01, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-Emphasis Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_01, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + EndPage +=09 + #endif + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_01 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_01 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_1, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_01, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_1, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_1, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_01, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_1, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + + EndPage + =20 +=09 +EndPage + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #2 (800x600) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #2 " + + TitleB "Common LFP Features"=20 + + EditText $Panel_Name_02, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_02, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_02, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_02, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_02, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_02, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_02, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" +=09 +=09 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" +=09 + Combo $Enable_SSC02, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " +=09 + Combo $eDP_Panel_Color_Depth_02, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_2, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephasis = table or Default/High Vswing Prephasis table.\r\n" + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_02, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_02, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_02, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_02, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_02, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_02, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_02, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_02, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =09 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_02, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_02, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_02, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_02, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_02, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_02 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_02 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_2, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_02, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_2, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_2, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_02, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_2, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage +=09 + +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #3 (1024x768 LVDS) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #3 " + + TitleB "Common LFP Features"=20 + + EditText $Panel_Name_03, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_03, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_03, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_03, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_03, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_03, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_03, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" + =20 + =09 + #if ($Int_LFP1_Type =3D=3D 0x1806) =09 + TitleB "Integrated eDP Features"=09 + =20 + Combo $Enable_SSC03, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " + =20 + + Combo $eDP_Panel_Color_Depth_03, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_3, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_03, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD en= able until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryin= g the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_03, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_03, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_03, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_03, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_03, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_03, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_03, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_03, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_03, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_03, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_03, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level value for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_03, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif + + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_03 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_03 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_3, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_03, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_3, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_3, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_03, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_3, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =09 + +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #4 (1280x1024 LVDS) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #4 " + + TitleB "Common LFP Features"=20 + + EditText $Panel_Name_04, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_04, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_04, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_04, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_04, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_04, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_04, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" + + + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" + =20 + Combo $Enable_SSC04, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_04, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_4, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_04, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon af= ter VDD enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time be= fore trying the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_04, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_04, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_04, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_04, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_04, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_04, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_04, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_04, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_04, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_04, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_04, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_04, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_04 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_04 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_4, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_04, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_4, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_4, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_04, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_4, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +=09 +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #5 (1400x1050 LVDS - Reduced Blank) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #5 " + + TitleB "Common LFP Features"=20 +=09 + EditText $Panel_Name_05, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_05, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_05, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_05, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_05, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_05, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_05, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" + =20 + =20 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" + + Combo $Enable_SSC05, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " + =20 +=09 + + Combo $eDP_Panel_Color_Depth_05, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_5, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_05, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_05, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_05, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_05, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_05, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_05, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_05, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_05, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_05, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_05, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_05, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_05, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_05, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_05 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_05 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_5, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_05, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_5, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_5, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_05, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_5, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage +=09 + +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #6 (1400x1050) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #6 " + + TitleB "Common LFP Features"=20 + + EditText $Panel_Name_06, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_06, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_06, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_06, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_06, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_06, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_06, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" +=09 +=09 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" + =20 + Combo $Enable_SSC06, "\teDP Spread Spectrum Clock:", &Disabled_Enabled= _List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " + =20 +=09 + Combo $eDP_Panel_Color_Depth_06, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_6, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_06, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_06, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_06, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_06, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_06, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_06, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_06, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_06, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_06, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_06, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_06, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_06, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_06, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_06 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_06 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_6, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_06, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_6, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_6, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_06, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_6, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage +=09 + + +EndPage + + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #7 (1600x1200) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #7 " + + TitleB "Common LFP Features"=20 +=09 + EditText $Panel_Name_07, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_07, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_07, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_07, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_07, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_07, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_07, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" + =20 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" + =20 + Combo $Enable_SSC07, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_07, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_7, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_07, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_07, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_07, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_07, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_07, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_07, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_07, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_07, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_07, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_07, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_07, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_07, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_07, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_07 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_07 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_7, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_07, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_7, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_7, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_07, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_7, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #8 (1280x768) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #8 " + + TitleB "Common LFP Features"=20 + + EditText $Panel_Name_08, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_08, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_08, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_08, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_08, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_08, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_08, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" +=09 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" + =20 + Combo $Enable_SSC08, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " +=09 +=09 + Combo $eDP_Panel_Color_Depth_08, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_8, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_08, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_08, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_08, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_08, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_08, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_08, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_08, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_08, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_08, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_08, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_08, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_08, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + =20 + Combo $eDP_Link_Vswing_Level_08, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + =09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_08 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_08 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_8, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_08, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_8, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_8, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + + EditNum $POST_BL_Brightness_08, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_8, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #9 (1680x1050) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #9 " + + TitleB "Common LFP Features"=20 +=09 + EditText $Panel_Name_09, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_09, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_09, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_09, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_09, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_09, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_09, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" +=09 + #if ($Int_LFP1_Type =3D=3D 0x1806)=09 + TitleB "Integrated eDP Features" + =20 + Combo $Enable_SSC09, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " +=09 + Combo $eDP_Panel_Color_Depth_09, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_9, "\tEdp Vswing Pre-emph table:", &eDP_Vswin= g_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_09, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction" + =09 + EditNum $eDP_Vcc_To_Hpd_Delay_09, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_09, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_09, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_09, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_09, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_09, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_09, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_09, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_09, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_09, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_09, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_09, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_09 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_09 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_9, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_09, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_9, " Inverter Polarity:", &Inv_Polarit= y_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_9, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_09, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_9, " PWM Inverter Frequency (Hz):", DEC, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #10 (1920x1200) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #10 " + + TitleB "Common LFP Features"=20 +=09 + EditText $Panel_Name_10, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_10, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_10, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_10, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_10, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_10, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_10, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" + =09 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features"=09 +=09 + Combo $Enable_SSC10, " \teDP Spread Spectrum Clock:", &Disabled_Enabl= ed_List, + Help "This feature will allow users to disable/enable Spread Spectrum = Clock for eDP.\r\n " + Combo $eDP_Panel_Color_Depth_10, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_10, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + Combo $eDP_T3_Optimization_10, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD e= nable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before tryi= ng the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_10, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_10, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_10, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_10, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_10, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_10, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_10, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_10, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_10, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_10, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_10, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_10, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_10 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_10 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_10, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_10, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_10, " Inverter Polarity:", &Inv_Polari= ty_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_10, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_10, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_10, " PWM Inverter Frequency (Hz):", DE= C, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #11 (Reserved) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #11 " + + TitleB "Common LFP Features"=20 +=09 + EditText $Panel_Name_11, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_11, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_11, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_11, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_11, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_11, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_11, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" + + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" +=09 + Combo $Enable_SSC11, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List, + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n " +=09 + Combo $eDP_Panel_Color_Depth_11, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + "This feature selects the Vswing Pre-emph settings to be used.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_11, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_11, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_11, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_11, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_11, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_11, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_11, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_11, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_11, " Is FastLinkTraining Fea= ture Supported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =09 + Combo $eDP_Link_DataRate_11, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_11, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_11, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_11, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_11 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_11 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_11, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_11, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_11, " Inverter Polarity:", &Inv_Polari= ty_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_11, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_11, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_11, " PWM Inverter Frequency (Hz):", DE= C, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #12 (Reserved) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #12 " + + TitleB "Common LFP Features"=20 + + EditText $Panel_Name_12, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_12, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_12, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_12, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_12, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_12, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_12, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" + =20 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" +=09 + Combo $Enable_SSC12, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List, + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_12, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_12, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_12, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_12, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_12, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_12, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_12, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_12, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_12, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_12, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_12, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_12, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_12, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_12, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_12, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_12 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_12 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_12, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_12, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_12, " Inverter Polarity:", &Inv_Polari= ty_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_12, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_12, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_12, " PWM Inverter Frequency (Hz):", DE= C, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #13 (Reserved) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #13 " + + TitleB "Common LFP Features"=20 + + EditText $Panel_Name_13, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_13, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_13, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_13, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_13, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_13, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_13, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" + + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features" + =20 + Combo $Enable_SSC13, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List, + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n " +=09 + + Combo $eDP_Panel_Color_Depth_13, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_13, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_13, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_13, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_13, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_13, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_13, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_13, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_13, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_13, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_13, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_13, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_13, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_13, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =20 + Combo $eDP_Link_Vswing_Level_13, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_13 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_13 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_13, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_13, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_13, " Inverter Polarity:", &Inv_Polari= ty_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_13, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_13, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_13, " PWM Inverter Frequency (Hz):", DE= C, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #14 (1280x800) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #14 " + + TitleB "Common LFP Features"=20 + + EditText $Panel_Name_14, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_14, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_14, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_14, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_14, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_14, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_14, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" +=09 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features"=09 + =20 + Combo $Enable_SSC14, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List, + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n " +=09 + Combo $eDP_Panel_Color_Depth_14, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_14, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" + + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_14, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction" + =09 + EditNum $eDP_Vcc_To_Hpd_Delay_14, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_14, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_14, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_14, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_14, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_14, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_14, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_14, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_14, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_14, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_14, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + =20 + Combo $eDP_Link_Vswing_Level_14, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage + =09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_14 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_14 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_14, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_14, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_14, " Inverter Polarity:", &Inv_Polari= ty_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_14, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_14, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_14, " PWM Inverter Frequency (Hz):", DE= C, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #15 (1280x600) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #15 " + + TitleB "Common LFP Features"=20 +=09 + EditText $Panel_Name_15, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_15, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_15, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_15, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_15, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_15, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_15, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" +=09 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features"=09 + =20 + Combo $Enable_SSC15, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List, + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n " + + Combo $eDP_Panel_Color_Depth_15, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_15, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_15, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction" + =09 + EditNum $eDP_Vcc_To_Hpd_Delay_15, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_15, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_15, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_15, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_15, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_15, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_15, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + =20 + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_15, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_15, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_15, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_15, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + Combo $eDP_Link_Vswing_Level_15, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif +=09 + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_15 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_15 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_15, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_15, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_15, " Inverter Polarity:", &Inv_Polari= ty_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_15, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_15, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + + EditNum $PWM_Frequency_15, " PWM Inverter Frequency (Hz):", DE= C, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Panel #16 (Reserved) Flat Panel parameters +;-------------------------------------------------------------------------= ----- + +Page "Panel #16 " + + TitleB "Common LFP Features"=20 +=09 + EditText $Panel_Name_16, "\tLFP Panel Name:",=20 + Help "This feature defines the LVDS panel name, used by driver onl= y. Panel name can be only of 13 characters maximum and rest of the characte= rs will be truncated. " + + Combo $Enable_Scaling_16, "\tScale to Target Resolution:", &No_Yes_List, + Help "Selecting this feature will make the graphics driver to enable S= caling feature by taking the Horizontal and Vertical resolution\r\n" + "from Target X-Res and Target Y-Res fields.\r\n" + + EditNum $Panel_Width_16, "\tTarget X-Res:", DEC, + Help "This value specifies the Target X-Resolution for this panel." + + EditNum $Panel_Height_16, "\tTarget Y-Res:", DEC, + Help "This value specifies the Target Y-Resolutoin for this panel." + + =20 + Combo $DPS_Panel_Type_16, " \tDPS Panel Type:", &DPS_Panel_Type_Li= st, + Help "This feature allows OEM to select the DPS Panel Type.\r\n " + "Intel SDRRS Technology is a feature of the Intel graphics dr= iver\r\n" + "which reduces display power\r\n" + "SDRRS:- Allows power savings when on battery mode and when a= lower refresh\r\n" + "rate will not adversely impact the user experience\r\n" + "Seamless:- Allows power savings when on battery mode and wh= en a lower refresh\r\n" + "rate will not adversely impact the user experience.Implement= s seamless refresh\r\n" + "rate switching, which eliminates the screen blink that occur= red\r\n"=20 + "during the refresh rate transitions\r\n" + + EditNum $Seamless_DRRS_Min_RR_16, "\tSeamless DRRS Minimum Refresh Rat= e (Hz):", DEC, + Help "Using this field the minimum Refresh Rate to be used for Seam= less DRRS feature can be entered in Hertz.\r\n\n" + "Note: Graphics driver will use this field only when EDID support is d= isabled in VBT configuration.\r\n" + =20 + Combo $Blt_Control_16, "\tBackLight Technology:", &Blt_Control_Type= _List, + Help "This feature allows OEM to select the Backlight Technology.\= r\n " + + Title " "=09 + Link "LFP PnP ID Table" , "LFP PnP ID" + Link "DTD Timings Table" , "DTD Timings" + Link "Backlight Control Parameters" , "Backlight Control Parameter= s" +=09 + #if ($Int_LFP1_Type =3D=3D 0x1806) + TitleB "Integrated eDP Features"=09 + =20 + Combo $Enable_SSC16, " \teDP Spread Spectrum Clock:", &Disabled_Enabled_= List, + Help "This feature will allow users to disable/enable Spread Spectrum Clo= ck for eDP.\r\n " +=09 + Combo $eDP_Panel_Color_Depth_16, "\tPanel Color Depth:", &eDP_Panel_Co= lor_Depth_List, + Help "This feature specifies the color depth of eDP panel used. " + + Combo $eDP_VswingPreEmph_16, "\tEdp Vswing Pre-emph table:", &eDP_Vswi= ng_Preemph_table_List, + Help "This feature allows the selection of Low power Vswing Prephas= is table or Default/High Vswing Prephasis table.\r\n" + "\r\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\t= \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | L= evel 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | Le= vel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV = | 350mV | \t\t| Level 0(400mV) | 400mV | 60= 0mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV = | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV |= 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N/= A | N/A | \t\t|Level 3(12000mV) | 12000mV |= N/A | N/A | N/A |\r\n" + "----------------------------------------------------------------------= -----------------------------\t\t------------------------------------------= ---------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + =09 + Link "eDP Panel Power Sequencing Parameters Table" , "eDP Panel Po= wer Sequencing" + Link "eDP Fast Link Training Configuration" , "eDP Fast Link Train= ing Configuration" +=09 + Page "eDP Panel Power Sequencing" + Link "Close Table", ".." + + Combo $eDP_T3_Optimization_16, "T3 optimization", &Disabled_Enabled_List, + Help "This feature enables or disables T3 optimization. \r\n" + "When enabled, VBIOS/Graphics driver will poll for AUX soon after VDD = enable until AUX passes or T3 time is reached\r\n" + "When disabled, VBIOS/Graphics driver will wait for T3 time before try= ing the first AUX transaction" + + EditNum $eDP_Vcc_To_Hpd_Delay_16, "LCDVCC to HPD high delay (T3):", D= EC, + Help "Using this field the delay from LCDVCC to HPD high can be sp= ecified in 100uS.\r\n" + "Valid Range: 0 to 200msec\r\n" + + EditNum $eDP_DataOn_To_BkltEnable_Delay_16, "Valid video data to Back= light Enable delay (T8):", DEC, + Help "Using this field the delay from Start of Valid video data fr= om Source to Backlight Enable can be specified in 100uS.\r\n" + "T8 is inclusive of T7.\r\n" + "Valid Range of T7: 0 to 50msec\r\n" + + EditNum $eDP_PwmOn_To_Bklt_Enable_Delay_16, "PWM-On To Backlight Enab= le delay:", DEC, + Help "Using this field the delay from PWM-On to Backlight Enable c= an be specified in 100uS.\r\n" + "Delay from PWM-On to Backlight Enable is included in delay from Va= lid video data to Backlight Enable (T8).\r\n" + "So it is expected that delay from PWM-On to Backlight Enable is le= ss than the delay from Valid video data to Backlight Enable (T8).\r\n" + + EditNum $eDP_Bklt_Disable_To_PwmOff_Delay_16, "Backlight Disable to P= WM-Off delay:", DEC, + Help "Using this field delay from Backlight Disable to PWM-Off can= be specified in 100uS.\r\n" + "Delay from Backlight Disable to PWM-Off is included in delay from = Backlight Disable to End of Valid video data (T9).\r\n" + "So it is expected that delay from Backlight Disable to PWM-Off del= ay is less than the delay from Backlight Disable to to End of Valid video d= ata (T9).\r\n" + =09 + EditNum $eDP_BkltDisable_To_DataOff_Delay_16, "Backlight Disable to E= nd of Valid video data delay (T9):", DEC, + Help "Using this field the delay from Backlight Disable to End of = Valid video data can be specified in 100uS.\r\n" + =09 + EditNum $eDP_DataOff_To_PowerOff_Delay_16, "End of Valid video data t= o Power-Off delay (T10):", DEC, + Help "Using this field delay from End of Valid video data from Sou= rce to Power-Off can be specified in 100uS.\r\n" + "Valid Range: 0 to 500 msec\r\n" + + EditNum $eDP_PowerCycle_Delay_16, "Power-off time (T12):", DEC, + Help "Using this field Power-off time can be specified in 100uS.\r= \n" + + EndPage + + Page "eDP Fast Link Training Configuration" + + Link "Close Table" , ".." + Combo $Fast_Link_Training_Supported_16, " Is FastLinkTraining Feature S= upported:", &No_Yes_List, + Help "This feature if set to Yes will enable " + "Fast Link Training for eDp, if Panel also supports it." + =20 + Combo $eDP_Link_DataRate_16, " Data Rate:", &eDP_Link_DataRate= _List, + Help "This feature allows for the selection of the " + "Data Rate for the embedded DP link. It will be used if th= e " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_LaneCount_16, " Lane Count:", &eDP_Link_LaneCo= unt_List, + Help "This feature allows for the selection of the " + "Lane Count (Port Width) for the embedded DP link. It will= be used if the " + "sink indicates that no aux handshake is required during l= ink training." + + Combo $eDP_Link_PreEmp_Level_16, " PreEmph Level:", &eDP_Link_= PreEmp_List, + Help "This feature allows for the selection of the " + "Pre-emphasis level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + =20 + Combo $eDP_Link_Vswing_Level_16, " VSwing Level:", &eDP_Link_V= Swing_List, + Help "This feature allows for the selection of the " + "Voltage Swing Level for the embedded DP link." + "\r\n\n\t\tLow power Swing Setting Table \t\t\t\t = Default Swing Setting Table \r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + " \t | \t\t PreEmphasis Levels\t\t | \t\= t \t | \t\t PreEmphasis Levels\t\t |\r\n" + "| VSwing Levels | Level 0(0dB) | Level 1(2.0dB) | Level 2(3.5dB) | = Level 3(4.8dB) | \t\t| VSwing Levels | Level 0(0dB) | Level 1(3.5dB) | L= evel 2(6.0dB) | Level 3(9.5dB) |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n" + "| Level 0(200mV) | 200mV | 250mV | 300mV= | 350mV | \t\t| Level 0(400mV) | 400mV | 6= 00mV | 800mV | 1200mV |\r\n" + "| Level 1(250mV) | 250mV | 300mV | 350mV= | N/A | \t\t| Level 1(600mV) | 600mV | = 800mV | 1200mV | N/A |\r\n" + "| Level 2(300mV) | 300mV | 350mV | N/A = | N/A | \t\t| Level 2(800mV) | 800mV = | 1200mV | N/A | N/A |\r\n" + "| Level 3(350mV) | 350mV | N/A | N= /A | N/A | \t\t|Level 3(12000mV) | 12000mV = | N/A | N/A | N/A |\r\n" + "---------------------------------------------------------------------= ------------------------------\t\t-----------------------------------------= ----------------------------------------------------------\r\n\n" + "Column - Non-Transition VDiff \r\n" + "Row - Transition VDiff \r\n" + + EndPage +=09 + #endif + + Page "DTD Timings" + =20 + Link "Close Table" , ".." + + Table $DVO_Tbl_16 " DTD Timings Values", + Column "Timings" , 1 byte , EHEX, + Help "This feature allows for the definition of the DTD " + "timings parameters related to the LFP. The " + "table is the 18-byte DTD structure defined in the " + "VESA EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + + EndPage + + Page "LFP PnP ID" + + Link "Close Table" , ".." + + Table $LVDS_PnP_ID_16 " LFP PnP ID Values", + Column "PnP ID" , 1 byte , EHEX, + Help "This feature allows the 10 bytes of EDID Vendor / " + "Product ID starting at offset 08h to be used as a " + "PnP ID.\r\n" + "\r\n" + " Table Definition:\r\n" + " Word: ID Manufacturer Name\r\n" + " Word: ID Product Code\r\n" + " DWord: ID Serial Number\r\n" + " Byte: Week of Manufacture\r\n" + " Byte: Year of Manufacture" + + EndPage + + Page "Backlight Control Parameters" + + Link "Close Table" , ".." + + Combo $BLC_Inv_Type_16, " Inverter Type:", &Inv_Type_List, + Help "This feature allows for the selection of the " + "Backlight Inverter type that is to be used to " + "control the backlight brightness of the LFP. When " + "PWM is selected, the driver and VBIOS will control " + "the backlight brightness via the integrated PWM " + "solution for the applicable chipsets. When I2C is " + "selected, the driver and VBIOS will control the " + "backlight brightness via the I2C solution for the " + "applicable chipsets. When None/External is " + "selected, the system BIOS will control the backlight " + "brightness via the external solution." + + Combo $Lfp_Pwm_Source_Selection_16, " Pwm Source Selection:", &Edp_P= wm_Source_List, + Help "This field allows to select the Source of the PWM to be used " + "for the selected Local Flat Panel.\r\n" + "\r\n" + =09 + Combo $BLC_Inv_Polarity_16, " Inverter Polarity:", &Inv_Polari= ty_List, + Help "This feature allows the backlight inverter polarity " + "to be specified.\r\n" + "\r\n" + "Normal means 0 value is minimum brightness.\r\n" + "Inverted means 0 value is maximum brightness." + + EditNum $BLC_Min_Brightness_16, " Minimum Brightness:", DEC, + Help "This feature allows defining the absolute minimum " + "backlight brightness setting. The graphics driver " + "will never decrease the backlight less than this " + "value. The value must be specified using normal " + "polarity semantics." + +EditNum $POST_BL_Brightness_16, " POST Backlight Intensity:", DEC, + Help "This feature is used to set default brightness value at P= OST." + "This is configurable field of 0-255. Value of 0 indicates= 0 brightness, 255 indicates maximum brightness. " + + EditNum $PWM_Frequency_16, " PWM Inverter Frequency (Hz):", DE= C, + Help "This feature allows for the definition of the " + "frequency needed for PWM Inverter.\r\n" + "\r\n" + "Note: The frequency range, entered as a decimal " + "number, for the integrated PWM is 200Hz - 40KHz." + EndPage + =20 +EndPage + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - RGB Palette Table +;-------------------------------------------------------------------------= ----- +#if($Enable_Correction =3D=3D 1) +Page "RGB Palette Table" + Link "Red Palette Table" , "Red Palette Table" + Link "Green Palette Table", "Green Palette Table" + Link "Blue Palette Table", "Blue Palette Table" +=09 + Page "Red Palette Table" + Link "Close Table" , ".." + Table $Red_Table "Red Palette Table", + Column "Red", 1 byte, EHEX, + Help "Enter values for Red Palette. Allowed range for entering values in= each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal." + EndPage +=09 + Page "Green Palette Table" + Link "Close Table" , ".." + Table $Green_Table "Green Palette Table", + Column "Green", 1 byte, EHEX, + Help "Enter values for Green Palette. Allowed range for entering values = in each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal= ." + EndPage +=09 + Page "Blue Palette Table" + Link "Close Table" , ".." + Table $Blue_Table "Blue Palette Table", + Column "Blue", 1 byte, EHEX, + Help "Enter values for Blue Palette. Allowed range for entering values i= n each row is 0-FF (in decimal 0-255). Input format is of type Hexadecimal." + EndPage +EndPage=09 +#endif + +=09 +EndPage ; "Integrated LFP Features" + + =20 + =20 +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Display Device Toggle Lists +;-------------------------------------------------------------------------= ----- + +Page "Display Device Toggle Lists" + + Link "Toggle/Capabilities List 1" , "Display Toggle List 1" + Link "Toggle/Capabilities List 2" , "Display Toggle List 2" + Link "Toggle/Capabilities List 3" , "Display Toggle List 3" + Link "Toggle/Capabilities List 4" , "Display Toggle List 4" + + Page "Display Toggle List 1" + + Link "Close Table" , ".." + + Table $Toggle_List1 "Display Toggle List 1", + Column "Display Select", 2 bytes, EHEX + Column "Reserved", 1 byte, DEC, + Help "These toggle lists are used by the video BIOS and " + "device drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "The video BIOS will 'OR' the bits of the two pipes " + "together to create a single pipe display device. " + "The Intel developed drivers will use the display " + "lists as they are. The divers also use this list to " + "get pipe information for ACPI switch display device " + "Hot Keys. Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "Display Select (Refer to VBIOS HLD for valid " + "selections):\r\n" + "\r\n" + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT" + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT" + + EndPage + + Page "Display Toggle List 2" + + Link "Close Table" , ".." + + Table $Toggle_List2 "Display Toggle List 2", + Column "Display Select", 2 bytes, EHEX + Column "Reserved", 1 byte, DEC, + Help "These toggle lists are used by the video BIOS and " + "device drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "The video BIOS will 'OR' the bits of the two pipes " + "together to create a single pipe display device. " + "The Intel developed drivers will use the display " + "lists as they are. The divers also use this list to " + "get pipe information for ACPI switch display device " + "Hot Keys. Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "Display Select (Refer to VBIOS HLD for valid " + "selections):\r\n" + "\r\n" + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT" + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT" + + EndPage + + Page "Display Toggle List 3" + + Link "Close Table" , ".." + + Table $Toggle_List3 "Display Toggle List 3", + Column "Display Select", 2 bytes, EHEX + Column "Reserved", 1 byte, DEC, + Help "These toggle lists are used by the video BIOS and " + "device drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "The video BIOS will 'OR' the bits of the two pipes " + "together to create a single pipe display device. " + "The Intel developed drivers will use the display " + "lists as they are. The divers also use this list to " + "get pipe information for ACPI switch display device " + "Hot Keys. Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "Display Select (Refer to VBIOS HLD for valid " + "selections):\r\n" + "\r\n" + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + ;"\tLFP2\tEFP2\tTV2\tCRT2\tLFP\tEFP\tTV\tCRT" + "\tLFP2\tEFP2\tEFP3\tCRT2\tLFP\tEFP\tTV\tCRT" + + EndPage + + Page "Display Toggle List 4" + + Link "Close Table" , ".." + + Table $Toggle_List4 "Display Toggle List 4", + Column "Display Select", 2 bytes, EHEX + Column "Reserved", 1 byte, DEC, + Help "These toggle lists are used by the video BIOS and " + "device drivers to help support the system BIOS with " + "switch display device Hot Keys. The basic algorithm " + "in the current display is found on the list and the " + "next settable display combination is set. If no " + "settable display combinations are found the function " + "returns fail.\r\n" + "\r\n" + "The video BIOS will 'OR' the bits of the two pipes " + "together to create a single pipe display device. " + "The Intel developed drivers will use the display " + "lists as they are. The divers also use this list to " + "get pipe information for ACPI switch display device " + "Hot Keys. Four lists are given to allow for multiple " + "Hot Keys or creative solutions.\r\n" + "\r\n" + "Display Select (Refer to VBIOS HLD for valid " + "selections):\r\n" + "\r\n" + "\tPipe A: Bits 7-0, Pipe B: Bits 15-8\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT" + EndPage + +EndPage + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Modes Removal Table +;-------------------------------------------------------------------------= ----- + +Page "Modes Removal Table" + + Table $Mode_Rem_Table "Modes Removal Table", + Column "X-Resolution", 2 bytes, DEC + Column "Y-Resolution", 2 bytes, DEC=20 + Column "BPP", 1 byte, DEC=20 + Column "Refresh Rate", 2 bytes, EHEX=20 + Column "Removal Flags", 1 byte, EHEX=20 + Column "Panel Type", 2 bytes, EHEX, + Help "This feature allows removing support for selected modes " + "resolutions.\r\n" + "\r\n" + "X-Resolution, Y-Resolution, and BPP in Decimal or " + "Hexadecimal (0FFFFh or 0FFh means disable all).\r\n" + "\r\n" + "Refresh Rate bitmap selection (0 =3D Do not remove, 1 =3D " + "Remove):\r\n" + "\r\n" + "\tBit 15-9 8 7 6 5 4 3 2 1 0 \r\n" + "\tRRate(Hz) Reserved 120 100 85 75 72 70 60 56 43i \r\n" + "\r\n" + "Removal Flags bitmap selection (0 =3D Do not remove, 1 =3D " + "Remove):\r\n" + "\r\n" + "\tBit 7 6 5 4 3 2= 1 0 \r\n" + "\tComponent Rsvd Rsvd LFP EFP Rsvd CRT Driver VBIOS \r\n" + "\r\n" + "\tNote: 1) In order to remove mode from both Windows and DOS, " + "both Bit 1 and Bit 0 must be set to 1.\r\n" + "\r\n" + "(Mobile only) Panel Type bitmap selection (0 =3D Do not " + "remove, 1 =3D Remove if panel is active):/r/n" + "\r\n" + "\tBit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 \r\n" + "\tType 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 \r\n" + "\r\n" + "\tNote: Default is to remove a mode resolution from all " + "panel types." +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - Display Configuration Removal Table +;-------------------------------------------------------------------------= ----- + +Page "Display Configuration Removal Table" + + Table $Dev_Removed_Table " Display Device Configuration Removal Tab= le", + Column "Pipe B" , 1 byte , BIN + Column "Pipe A" , 1 byte , BIN,=20 + =20 + Help "This feature allows blocking selected display configurations " + "by the video BIOS and driver.\r\n" + "\r\n" + "Display Devices are specified in the following bit patterns " + "(pipe A and B use the same bit pattern):\r\n" + "\r\n" + "\t7\t6\t5\t4\t3\t2\t1\t0 (lsb)\r\n" + "\tLFP2\tEFP2\tRsvd\tRsvd\tLFP\tEFP\tRsvd\tCRT\r\n" + "\r\n" + "Examples:\r\n" + "\tPipe B Pipe A\r\n" + "\t00000000b, 00000101b ; EFP & CRT on Pipe A\r\n" + "\t00001100b, 00000001b ; EFP & LFP on Pipe B and CRT on " + "Pipe A" +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D +; Page - OEM Customizable Mode 2.0 +;-------------------------------------------------------------------------= ----- + +Page "OEM Customizable Modes 2.0" + + Link "OEM Mode 1 Configuration", "OEM Mode #1" + Link "OEM Mode 2 Configuration", "OEM Mode #2" + Link "OEM Mode 3 Configuration", "OEM Mode #3" + Link "OEM Mode 4 Configuration", "OEM Mode #4" + Link "OEM Mode 5 Configuration", "OEM Mode #5" + Link "OEM Mode 6 Configuration", "OEM Mode #6" =20 + + Page "OEM Mode #1" + + Link "Close Table" , ".." + + Title " 8 bpp =3D VGA mode 60h / VESA mode 160h" + Title " 16 bpp =3D VGA mode 61h / VESA mode 161h" + Title " 32 bpp =3D VGA mode 62h / VESA mode 162h" + + EditNum $OEM_Mode_Flags1, "Support Flags:", BIN, + Help "Support flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + =20 + EditNum $OEM_Display_Flags1, "Display Flags:", BIN, + Help "Display Flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + EditNum $OEM_Mode_X1, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y1, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color1, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate1, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD1 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + EndPage + EndPage + =20 + Page "OEM Mode #2" + + Link "Close Table" , ".." + + Title " 8 bpp =3D VGA mode 63h / VESA mode 163h" + Title " 16 bpp =3D VGA mode 64h / VESA mode 164h" + Title " 32 bpp =3D VGA mode 65h / VESA mode 165h" + + EditNum $OEM_Mode_Flags2, "Support Flags:", BIN, + Help "Support flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + =20 + EditNum $OEM_Display_Flags2, "Display Flags:", BIN, + Help "Display Flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X2, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y2, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color2, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate2, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD2 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + EndPage + EndPage + + Page "OEM Mode #3" + + Link "Close Table" , ".." + + Title " 8 bpp =3D VGA mode 66h / VESA mode 166h" + Title " 16 bpp =3D VGA mode 67h / VESA mode 167h" + Title " 32 bpp =3D VGA mode 68h / VESA mode 168h" + + EditNum $OEM_Mode_Flags3, "Support Flags:", BIN, + Help "Support flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + =20 + EditNum $OEM_Display_Flags3, "Display Flags:", BIN, + Help "Display Flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X3, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y3, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color3, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate3, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD3 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + EndPage + EndPage + + Page "OEM Mode #4" + + Link "Close Table" , ".." + + Title " 8 bpp =3D VGA mode 69h / VESA mode 169h" + Title " 16 bpp =3D VGA mode 6Ah / VESA mode 16Ah" + Title " 32 bpp =3D VGA mode 6Bh / VESA mode 16Bh" + + EditNum $OEM_Mode_Flags4, "Support Flags:", BIN, + Help "Support flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + =20 + EditNum $OEM_Display_Flags4, "Display Flags:", BIN, + Help "Display Flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X4, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y4, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color4, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate4, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD4 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + EndPage + EndPage + + Page "OEM Mode #5" + + Link "Close Table" , ".." + + Title " 8 bpp =3D VGA mode 6Ch / VESA mode 16Ch" + Title " 16 bpp =3D VGA mode 6Dh / VESA mode 16Dh" + Title " 32 bpp =3D VGA mode 6Eh / VESA mode 16Eh" + + EditNum $OEM_Mode_Flags5, "Support Flags:", BIN, + Help "Support flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + =20 + EditNum $OEM_Display_Flags5, "Display Flags:", BIN, + Help "Display Flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X5, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y5, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color5, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate5, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD5 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + EndPage + EndPage + + Page "OEM Mode #6" + + Link "Close Table" , ".." + + Title " 8 bpp =3D VGA mode 6Fh / VESA mode 16Fh" + Title " 16 bpp =3D VGA mode 70h / VESA mode 170h" + Title " 32 bpp =3D VGA mode 71h / VESA mode 171h" + + EditNum $OEM_Mode_Flags6, "Support Flags:", BIN, + Help "Support flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tDriver" + "\tVBIOS" + "\r\n" + =20 + EditNum $OEM_Display_Flags6, "Display Flags:", BIN, + Help "Display Flags:" + "(0 =3D Disabled, 1 =3D Enabled)" + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tLFP2" + "\tEFP2" + "\tTV2" + "\tCRT2" + "\tLFP" + "\tEFP" + "\tTV" + "\tCRT" + "\r\n" + + Title "Mode Characteristics" + + EditNum $OEM_Mode_X6, " X Resolution:", DEC, + Help "X Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Y6, " Y Resolution:", DEC, + Help "Y Resolution in pixels (decimal)." + + EditNum $OEM_Mode_Color6, " Color Depth:", BIN, + Help "Color Depth, bits can be set simultaneously (binary)." + "\r\n\r\n" + "\tBit 7" + "\tBit 6" + "\tBit 5" + "\tBit 4" + "\tBit 3" + "\tBit 2" + "\tBit 1" + "\tBit 0" + "\r\n" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\tRsvd" + "\t32 BPP" + "\t16 BPP" + "\t8 BPP" + "\r\n" + + EditNum $OEM_Mode_RRate6, " Refresh Rate:", DEC, + Help "Refresh rate for OEM customizable mode (decimal)." + + Link "18 Bytes DTD" , "DTD" + + Page "DTD" + + Link "Close Table" , ".." + + Table $OEM_Mode_DTD6 " Detailed Timings Descriptor", + Column "Timings" , 1 byte , EHEX, + Help "This table is the 18-byte DTD(Detailed Timings" + " Descriptor) structure defined in the VESA" + " EDID version 1.x.\r\n" =20 + "\r\n" + "\tDB ?\t; Low Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; High Byte of DClk in 10 KHz\r\n" + "\tDB ?\t; Horizontal Active in pixels, LSB\r\n" + "\tDB ?\t; Horizontal Blanking in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Hor. Blanking\r\n" + "\tDB ?\t; Vertical Active in lines, LSB\r\n" + "\tDB ?\t; Vertical Blanking in lines, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Vert. Active\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Blanking\r\n" + "\tDB ?\t; HSync Offset from Hor. Blanking in pix., LSB\r\= n" + "\tDB ?\t; HSync Pulse Width in pixels, LSB\r\n" + "\tDB ?\t; Bit 7-4: Lower 4 bits of VSync Offset\r\n" + "\t \t; Bit 3-0: Lower 4 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Bit 7-6: Upper 2 bits of HSync Offset\r\n" + "\t \t; Bit 5-4: Upper 2 bits of HSync Pulse Width\r\n" + "\t \t; Bit 3-2: Upper 2 bits of VSync Offset\r\n" + "\t \t; Bit 1-0: Upper 2 bits of VSync Pulse Width\r\n" + "\tDB ?\t; Horizontal Image Size, LSB\r\n" + "\tDB ?\t; Vertical Image Size, LSB\r\n" + "\tDB ?\t; Bit 7-4: Upper 4 bits of Hor. Image Size\r\n" + "\t \t; Bit 3-0: Upper 4 bits of Vert. Image Size\r\n" + "\tDB 0\t; Horizontal Border in pixels\r\n" + "\tDB 0\t; Vertical Border in lines\r\n" + "\tDB ?\t; Flags:\r\n" + "\t \t; Bit 7: 0 =3D Non-interlaced, 1 =3D Interlac= ed\r\n" + "\t \t; Bit 6-5: 00 =3D Reserved\r\n" + "\t \t; Bit 4-3: 11 =3D Digital Separate\r\n" + "\t \t; Bit 2: Vertical Polarity (0 =3D Negative, 1= =3D Positive)\r\n" + "\t \t; Bit 1: Horizontal Polarity (0 =3D Negative,= 1 =3D Positive)\r\n" + "\t \t; Bit 0: 0 =3D Reserved" + EndPage + EndPage +EndPage + + +;=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D +; End of File +;-------------------------------------------------------------------------= ----- + =20 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.depex b/Sil= icon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/CpuPeim.depex new file mode 100644 index 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# CpuPeim.inf +# +# Abstract: +# +# Component description file for CPU module +# +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D CpuPeim + FILE_GUID =3D 01359d99-9446-456d-ada4-50a711c03adb + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PeimInitializeCpu + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|CpuPeim.efi + PEI_DEPEX|CpuPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x27B0 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiMasterBootModePpiGuid + + + gEfiSecPlatformInformationPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + gEfiPlatformCpuInfoGuid + + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git 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zl>agRIKPK~l7E`t&p*pQ&mZ6q^S|YN{4u_te~mxQzrnxFzssNJFY*#U#9!vG@+15h S&!mN=3Dsj)_UfBpYsf&T@bfgYd$ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSenso= r.inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.inf new file mode 100644 index 0000000..da142b4 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/DigitalThermalSensor.inf @@ -0,0 +1,190 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +# +#/*++ +# +#Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +#This software and associated documentation (if any) is furnished +#under a license and may only be used or copied in accordance +#with the terms of the license. Except as permitted by such +#license, no part of this software or documentation may be +#reproduced, stored in a retrieval system, or transmitted in any +#form or by any means without the express written consent of +#Intel Corporation. +# +# Module Name: +# +# DigitalThermalSensor.inf +# +# Abstract: +# +# Component description file for the DigitalThermalSensor SMM driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DigitalThermalSensor + FILE_GUID =3D 5122FA7B-17A3-4a8b-89AE-A93ADE92EADF + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InstallDigitalThermalSensor + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|DigitalThermalSensor.efi + SMM_DEPEX|DigitalThermalSensor.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3= 410 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x3418 + + +[Protocols.IA32] + gEfiGlobalNvsAreaProtocolGuid + + gEfiSmmIoTrapDispatch2ProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiMpServiceProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Libr= ary/AslUpdate/Dxe/AslUpdateLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/DTSHookL= ib/Smm/DTSHookLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/PlatSmmI= o/PlatSmmIo.inf +# Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/Ksc/Smm/= SmmKscLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2Proto= colGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfi= MpServiceProtocolGuid AND gEfiSmmSxDispatch2ProtocolGuid) = AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAcc= ess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid = AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid = AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEf= iRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArch= ProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProt= ocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolG= uid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS 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new file mode 100644 index 0000000..a59b48b --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/Dptf.inf @@ -0,0 +1,219 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +#**/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D Dptf + FILE_GUID =3D 1D000AE9-756B-4937-B736-1F3D96A5A8F0 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D DptfDriverEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|Dptf.efi + DXE_DEPEX|Dptf.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2D48 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= D40 + + +[Protocols.IA32] + # CONSUMED + gEfiAcpiSdtProtocolGuid + + # CONSUMED + gEfiAcpiTableProtocolGuid + + # CONSUMED + gEfiGlobalNvsAreaProtocolGuid + + gDxeVlvPlatformPolicyGuid + + gEfiI2cBusProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.= inf +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDrive= rLib.inf + +[Depex.IA32] +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND= gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformP= olicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +# DRIVER_BINDING =3D gSampleDrvDriverBinding +# COMPONENT_NAME =3D gSampleDrvComponentName +# COMPONENT_NAME2 =3D gSampleDrvComponentName2 +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/GraphicDxeInitSmm.d= epex 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licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# IspDxe.inf +# +# Abstract: +# +# + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D ISPDxe + FILE_GUID =3D 5A38B969-CD6A-4814-82E6-559F840BBC58 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ISPDxeEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|ISPDxe.efi + DXE_DEPEX|ISPDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x4= 110 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x4118 + + +[Protocols.IA32] + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.IA32] +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNv= sAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND = (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGui= d AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMon= otonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEf= iResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArch= ProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoco= lGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGui= d) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## 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b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MemoryInit.inf @@ -0,0 +1,201 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Mobile Silicon Support Module" and is +# licensed for Intel Mobile CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +#/*++ +# +# Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# MemoryInit.inf +# +# Abstract: +# +# Component description file for MemoryInit module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D MemoryInit + FILE_GUID =3D D4EE25EA-0B48-43ae-A016-4D6E8B6C43B3 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PeimMemoryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|MemoryInit.efi + PEI_DEPEX|MemoryInit.depex + +[PatchPcd.IA32] + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|0x00|0x17A30 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|0x01|0x16FF2 + + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|0x01|0x16FF4 + + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|0x01|0x16FF0 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|0x01|0x17000 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0x00|0x17A32 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|0x01|0x17008 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|0x02|0x17009 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|0x03|0x16FF3 + + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0x00|0x17A31 + + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|0x0b|0x16FF1 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|0x0b|0x16FF7 + + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|0x0c|0x17003 + + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|0x06|0x17002 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|0x06|0x16FF6 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|0x06|0x16FF5 + + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|0x20|0x17001 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046|0x17004 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 6FF8 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiReadOnlyVariable2PpiGuid + + + gSeCUmaPpiGuid + + gSeCfTPMPpiGuid + + gVlvMmioPolicyPpiGuid + + gPeiCapsulePpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + gEfiGlobalVariableGuid + + gEfiVlv2VariableGuid + + gEfiMemoryConfigDataGuid + + + gEfiAcpiVariableGuid + + + gEfiPlatformInfoGuid + + gEfiSetupVariableGuid + + gEfiMemoryOverwriteControlDataGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2DeviceRefCodePkg/Platform/Library/RamDebugLib/RamDebugLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf + +[Depex.IA32] +# gEfiPeiReadOnlyVariable2PpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /Fa$* /Oi /Od /DEFI_MEMORY_INIT /DSMM_SUPPORT /DMINNOW2_PO /DENBDT_PF_EN= ABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_= ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OP= TIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTI= ONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D= 1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /D= PCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D= LPDDR2_SUPPORT=3D0 /D DDR3_SUPPORT=3D1 /D LPDDR3_SUPPORT=3D0 /D DEBUG_MODE= =3D1 /D SEC_SUPPORT_FLAG /D FTPM_ENABLE /DDDR_DUAL_CHANNEL=3D1 +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MinnowBoardMAXUEFIF= irmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/= IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/MinnowBoardMAXUEFIFirmware= -LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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zT>nSEWgh(eu%BzZBhA?^cl-K(%}4tBf6ZS#-pxdQ^7a3=3DwKnme?M(jepsmaD&vzR6 z(-N0YMY0H}k*G&*wkPHx<5E=3Dqo&2*j_kV zI9)hf_-WzA!o|X`3vUHcD7oRCUSNuuwh2o1v>azSBCHC8U literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchEarlyInitPeim.in= f b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchEarlyInitPeim.inf new file mode 100644 index 0000000..ca923c9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchEarlyInitPeim.inf @@ -0,0 +1,97 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchEarlyInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Early Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchEarlyInitPeim + FILE_GUID =3D D9F5B28C-9FF1-47D6-B503-3DC23BD345FF + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PchEarlyInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|PchEarlyInitPeim.efi + PEI_DEPEX|PchEarlyInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 40 + + +[Protocols.IA32] + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitDxe.depex b/= Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchInitDxe.depex new file mode 100644 index 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitDxe.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchInitDxe + FILE_GUID =3D DE23ACEE-CF55-4fb6-AA77-984AB53DE823 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PchInitEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitDxe.efi + DXE_DEPEX|PchInitDxe.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 6C50 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x16C58 + + +[Protocols.IA32] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/Asl= Update/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[Depex.IA32] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGui= d AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (g= EfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND= (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocol= Guid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocol= Guid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AN= D gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTime= rArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArc= hProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProt= ocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS 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licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchInitPeim + FILE_GUID =3D FD236AE7-0791-48c4-B29E-29BDEEE1A838 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InstallPchInitPpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitPeim.efi + PEI_DEPEX|PchInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= 2B0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x52B8 + + +[Protocols.IA32] + +[Ppis.IA32] + ## CONSUMES + gEfiPeiMemoryDiscoveredPpiGuid + + ## CONSUMES + gPchPlatformPolicyPpiGuid + + gEfiPeiStallPpiGuid + + gPchPeiInitPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## HOB + gEfiPlatformInfoGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# gPchPlatformPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) 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z**Dk)dy{<&B-3i&Zhz4Jko{r%Blbt_kJ+EJKV^T${+#^<`!4$)d#8QBz1Plh{~HTE B!?*wd literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchS3SupportDxe.inf= b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchS3SupportDxe.inf new file mode 100644 index 0000000..92b2912 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchS3SupportDxe.inf @@ -0,0 +1,257 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +## @file +# Component description file for Pch Initialization driver +# +# Copyright (c) 1999 - 2011, Intel Corporation. All rights reserved.
+# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchS3SupportDxe + FILE_GUID =3D 14537da0-222a-4bbe-9a5c-212a3cbca9ef + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PchS3SupportEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchS3SupportDxe.efi + DXE_DEPEX|PchS3SupportDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 020 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x6028 + + +[Protocols.IA32] + # PROTOCOL ALWAYS_PRODUCED + gEfiPchS3SupportProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiFirmwareVolume2ProtocolGuid + + ## SOMETIMES_CONSUMES + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFileProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFile2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleFileSystemProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiFileInfoGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraAction= LibDebug.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +# MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 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z`hm$j{k%G?KBHD@R%q_m4Rd=3Dkq nZ&mgx^Q!t){#BP(i850&@6Oa`8Zz55y_r3kCo^xmH0pl=3DHoZc# literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled= .inf b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.inf new file mode 100644 index 0000000..42ac7ea --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmbusArpDisabled.inf @@ -0,0 +1,144 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmbusArpDisabled.inf +# +# Abstract: +# +# Component description file for PchSmbus module +# This version will NOT include ARP support. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchSmbusArpDisabled + FILE_GUID =3D D82D57AC-99F9-4c7a-B591-BBCF8A0E7FBE + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializePchSmbusPeim + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PchSmbusArpDisabled.efi + PEI_DEPEX|PchSmbusArpDisabled.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= C80 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1C88 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiStallPpiGuid + + gEfiPeiMemoryDiscoveredPpiGuid + + gEfiPeiSmbus2PpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + gEfiVLVTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + gEfiVLVTokenSpaceGuid.PcdTCSmbaIoBaseAddress + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# gPeiSmbusPolicyPpiGuid AND gEfiPeiStallPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) 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index 0000000..37a8491 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSmiDispatcher.inf @@ -0,0 +1,181 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmiDispatcher.inf +# +# Abstract: +# +# Component description file for the Pch SMI Dispatch Handlers module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchSmiDispatcher + FILE_GUID =3D 6BE18C9C-BF61-499e-88EC-5CD57430460C + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InitializePchSmmDispatcher + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchSmiDispatcher.efi + SMM_DEPEX|PchSmiDispatcher.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= 010 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5018 + + +[Protocols.IA32] + gEfiPciRootBridgeIoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + + + gEfiSmmIchnDispatchExProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiSmmPowerButtonDispatch2ProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid AND gEfiPciRootBridgeIoProtocolGuid) AND (gEf= iPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2Prot= ocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfi= MetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfi= RealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntime= ArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocol= Guid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid= AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) 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+# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiPeim.inf +# +# Abstract: +# +# Component description file for the SPI PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchSpiPeim + FILE_GUID =3D AA652CB9-2D52-4624-9FAE-D4E58B67CA46 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InstallPchSpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchSpiPeim.efi + PEI_DEPEX|PchSpiPeim.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 700 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2708 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiSpiPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# TRUE + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC (EBC is for build on= ly) +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) 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b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchSpiSmm.inf @@ -0,0 +1,251 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiSmm.inf +# +# Abstract: +# +# Component description file for the SPI SMM driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchSpiSmm + FILE_GUID =3D 27F4917B-A707-4aad-9676-26DF168CBF0D + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InstallPchSpi + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PchSpiSmm.efi + SMM_DEPEX|PchSpiSmm.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= 800 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5808 + + +[Protocols.IA32] + gEfiSmmSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtoc= olGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBas= e2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGu= id AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMo= notonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gE= fiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArc= hProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoc= olGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGu= id) + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK =3D IchSpiVirtualddressChangeEvent +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex b/Sili= con/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex new file mode 100644 index 0000000..05a6cfe --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PchUsb.depex @@ -0,0 +1 @@ +=02H=EF=BF=BD=08t=EF=BF=BD=EF=BF=BD=EF=BF=BDN=EF=BF=BD=EF=BF=BD=C4=BE=EF= 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchUsb.inf +# +# Abstract: +# +# Component description file for PCH USB PEIM +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchUsb + FILE_GUID =3D 3B873142-4252-49eb-BF17-105CD6F3E808 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializePchUsb + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchUsb.efi + PEI_DEPEX|PchUsb.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 660 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1668 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiUsbControllerPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# gEfiPeiMasterBootModePpiGuid AND gPchUsbPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS 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/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PeiSmmControl.inf new file mode 100644 index 0000000..6bd7d63 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PeiSmmControl.inf @@ -0,0 +1,110 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiSmmControl + FILE_GUID =3D FF456B9C-0DC7-4682-9E92-0DE84B6E4067 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmControlPeiDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PeiSmmControl.efi + PEI_DEPEX|PeiSmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 310 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1318 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= 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your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PlatformCpuPolicy.inf +# +# Abstract: +# +# Platform CPU driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PlatformCpuPolicy + FILE_GUID =3D cb933912-df8f-4305-b1f9-7b44fa11395c + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformCpuPolicyEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PlatformCpuPolicy.efi + DXE_DEPEX|PlatformCpuPolicy.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3= C70 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x3C78 + + +[Protocols.IA32] + gEfiFirmwareVolume2ProtocolGuid + + gEfiPlatformCpuProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## CONSUMES + gEfiStatusCodeRuntimeProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiPlatformCpuInfoGuid + + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + +[Depex.IA32] +# (gEfiFirmwareVolumeBlockProtocolGuid AND gEfiVariableArchProtocolGuid A= ND gEfiResetArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtoco= lGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArch= ProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid = AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolG= uid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiS= ecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWrite= ArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArch= ProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) 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z5}qENu1`-(FGS?L0kQK)`myxL3{^&ThAZRljEBfKuIK1y(Kt?*ue0iI(A}lmrF%p7 zzHYKUPM?ujn)sK*NlCp)|4hnF-jV!N^1pIZbA2;PIW8or{mD(&^!3avw1gIMlDa&-%0$Tsbr+ItYyA4D_( J(EpGA{twc??P>r3 literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PowerManagement2.in= f b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PowerManagement2.inf new file mode 100644 index 0000000..d9ac1f5 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/PowerManagement2.inf @@ -0,0 +1,270 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +# +#/*++ +# +#Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +#This software and associated documentation (if any) is furnished +#under a license and may only be used or copied in accordance +#with the terms of the license. Except as permitted by such +#license, no part of this software or documentation may be +#reproduced, stored in a retrieval system, or transmitted in any +#form or by any means without the express written consent of +#Intel Corporation. +# +#Module Name: +# +# PowerManagement.inf +# +#Abstract: +# +# Component description file for Power Management module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PowerManagement2 + FILE_GUID =3D 41E89AB0-BD3D-44b6-A431-E4836EFBF2CB + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InitializePowerManagement + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PowerManagement2.efi + SMM_DEPEX|PowerManagement2.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x8208 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x8= 200 + + +[Protocols.IA32] + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gPpmPlatformPolicyProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gPowerManagementAcpiTableStorageGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/IstAppl= et/Smm/IstApplet.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/ValleyV= iew/Smm/MchLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/SouthCl= uster/Smm/IchLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Libr= ary/AslUpdate/Dxe/AslUpdateLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/Library/Silverm= ont/Smm/SilvermontPpmLib.inf + +[Depex.IA32] +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid = AND gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2ProtocolGuid A= ND gEfiGlobalNvsAreaProtocolGuid AND gPpmPlatformPolicyProtocolGuid) AND= (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) = AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess= 2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND= gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND= gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRu= ntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchPro= tocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtoco= lGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid= AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SataController.inf +# +# Abstract: +# +# Component description file for PCH SATA controller Driver module. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SataController + FILE_GUID =3D BB65942B-521F-4ec3-BAF9-A92540CF60D2 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeSataControllerDriver + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|SataController.efi + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2D40 + + +[Protocols.IA32] + gEfiIdeControllerInitProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + gEfiPciIoProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gSataControllerDriverGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiLib/UefiLib.inf + +[Depex.IA32] +# (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchPr= otocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchPr= otocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolG= uid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gE= fiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVaria= bleArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git 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zm(NBP?#IIyAm+Pn;WBTZd=3D@X8c-6!lFPnv!!);C9403pMnCEqdOHdA zPWr>kF)!&1_d~9dJ`Cq!9d@E3%wda8gZ@o@gz%8VenMofgj>p0acjACTn)FL+rVw) zYPn4u;Zz*QsX3mD(JMh-NVvQ+$wk1h6ZBp>}k6!)~!MM>rn9mEv>G1V#c?HtDVW)G4VJR>1kYZ7S9`yMzsaV|V% zYaS{S9;g%So0H*O9_s;46DR!iX^|h|KC3dUz#J}f1Wv)EDJ}AY;&2K}OqnwtnLTs4BE)3D0~^cP=3DZmdN({=3Dbcdq5r(| z7Z%@FXpPJc{;wU8mn^=3Do+*(j>Ev$~T0{dac;MhZk{@cbGd`789{+!167C}I!)nVQE zo8SCq^@9&XJN{o?g1G2^*ia->fUKEt^Y~H*g?nU7NfY1@3uVV%$XCM;9zP~CrtaQ! zG3+XQqTia@M|ayrTE6d-uiXl?^O<5stFgKX-ztJ1fq-)BLpgb@Q9%*7 znVviS;pxAheqj39>5FDOGUJsQM`l=3DNu9^9}nVy+vW+u;?HLGdX(ODN~O`PqTy?^$p z*-6 +# +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SecCore + FILE_GUID =3D 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + MODULE_UNI_FILE =3D SecCore.uni + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + BIN|ResetVec.bin + PE32|SecCore.efi + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 188 + + +[Protocols.IA32] + +[Ppis.IA32] + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + + ## PRODUCES + gEfiTemporaryRamDonePpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitL= ib.inf +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraAction= LibDebug.inf +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibN= ull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + +[Depex.IA32] + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## 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a/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.inf b/Si= licon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.inf new file mode 100644 index 0000000..262dfd4 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32DEBUG/IA32/SmmControl.inf @@ -0,0 +1,129 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmControl + FILE_GUID =3D DD787473-07CE-4c63-82CE-930B33F39C09 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmControlDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|SmmControl.efi + DXE_DEPEX|SmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= A00 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2A08 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D VlvInitDxe + FILE_GUID =3D 93C81A74-B648-4f7f-925E-E4A0CDCC776D + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D VlvInitEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|VlvInitDxe.efi + DXE_DEPEX|VlvInitDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= AB0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5AB8 + + +[Protocols.IA32] + gDxeVlvPlatformPolicyGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + + gIgdOpRegionProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gBmpImageGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid= AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMono= tonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfi= ResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchP= rotocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocol= Guid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= 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b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/DigitalThermalSensor.inf @@ -0,0 +1,182 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Reference Module" and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +# +#/*++ +# +#Copyright (c) 1999 - 2013 Intel Corporation. All rights reserved +#This software and associated documentation (if any) is furnished +#under a license and may only be used or copied in accordance +#with the terms of the license. Except as permitted by such +#license, no part of this software or documentation may be +#reproduced, stored in a retrieval system, or transmitted in any +#form or by any means without the express written consent of +#Intel Corporation. +# +# Module Name: +# +# DigitalThermalSensor.inf +# +# Abstract: +# +# Component description file for the DigitalThermalSensor SMM driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D DigitalThermalSensor + FILE_GUID =3D 5122FA7B-17A3-4a8b-89AE-A93ADE92EADF + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InstallDigitalThermalSensor + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|DigitalThermalSensor.efi + SMM_DEPEX|DigitalThermalSensor.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 010 + + +[Protocols.IA32] + gEfiGlobalNvsAreaProtocolGuid + + gEfiSmmIoTrapDispatch2ProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiMpServiceProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/PowerManagement/SampleCode/Libr= ary/AslUpdate/Dxe/AslUpdateLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/DTSHookL= ib/Smm/DTSHookLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/PlatSmmI= o/PlatSmmIo.inf +# Vlv2TbltDevicePkg/Library/CpuIA32Lib/CpuIA32Lib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/CPU/Dts/SampleCode/Library/Ksc/Smm/= SmmKscLib.inf + +[Depex.IA32] +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmSwDispatch2Proto= colGuid AND gEfiGlobalNvsAreaProtocolGuid AND gEfi= MpServiceProtocolGuid AND gEfiSmmSxDispatch2ProtocolGuid) = AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAcc= ess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid = AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid = AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEf= iRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArch= ProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProt= ocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolG= uid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h 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Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +#**/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D Dptf + FILE_GUID =3D 1D000AE9-756B-4937-B736-1F3D96A5A8F0 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D DptfDriverEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|Dptf.efi + DXE_DEPEX|Dptf.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB= 40 + + +[Protocols.IA32] + # CONSUMED + gEfiAcpiSdtProtocolGuid + + # CONSUMED + gEfiAcpiTableProtocolGuid + + # CONSUMED + gEfiGlobalNvsAreaProtocolGuid + + gDxeVlvPlatformPolicyGuid + + gEfiI2cBusProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.= inf +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDrive= rLib.inf + +[Depex.IA32] +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND= gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformP= olicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +# DRIVER_BINDING =3D gSampleDrvDriverBinding +# COMPONENT_NAME =3D gSampleDrvComponentName +# COMPONENT_NAME2 =3D gSampleDrvComponentName2 +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) 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agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D GraphicDxeInitSmm + FILE_GUID =3D 99EC6206-AA45-4CAE-B630-866755241C8A + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D GraphicDxeInitSmmEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|GraphicDxeInitSmm.efi + SMM_DEPEX|GraphicDxeInitSmm.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= E00 + + +[Protocols.IA32] + gDxeVlvPlatformPolicyGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf +# MdePkg/Library/SmmIoLib/SmmIoLib.inf + +[Depex.IA32] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGui= d) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCp= uArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounte= rArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchPr= otocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid= AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gE= fiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfi= SmmAccess2ProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data /ALIGN:4096 +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.depex b/Si= licon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.depex new file mode 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f7uRLXU}tQd@zxBp-mYJ)59%`v8iT>`{lWhqv@^d6 literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.inf b/Sili= con/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.inf new file mode 100644 index 0000000..500ea05 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/ISPDxe.inf @@ -0,0 +1,241 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# IspDxe.inf +# +# Abstract: +# +# + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D ISPDxe + FILE_GUID =3D 5A38B969-CD6A-4814-82E6-559F840BBC58 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ISPDxeEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|ISPDxe.efi + DXE_DEPEX|ISPDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 3F0 + + +[Protocols.IA32] + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.IA32] +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNv= sAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND = (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGui= d AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMon= otonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEf= iResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArch= ProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoco= lGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGui= d) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 diff --git 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+1,195 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SataController.inf +# +# Abstract: +# +# Component description file for PCH SATA controller Driver module. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SataController + FILE_GUID =3D BB65942B-521F-4ec3-BAF9-A92540CF60D2 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeSataControllerDriver + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|SataController.efi + +[PatchPcd.IA32] + +[Protocols.IA32] + gEfiIdeControllerInitProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + gEfiPciIoProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gSataControllerDriverGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiLib/UefiLib.inf + +[Depex.IA32] +# (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchPr= otocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchPr= otocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolG= uid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gE= fiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVaria= bleArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.depex b/Si= licon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.depex new file mode 100644 index 0000000..3ec1c91 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.depex @@ -0,0 +1 @@ +=02=EF=BF=BDoL=1Fk=EF=BF=BD=EF=BF=BDH=EF=BF=BD=01=EF=BF=BD=EF=BF=BD=EF=BF= =BD=EF=BF=BD}V=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.efi b/Sili= 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z7(Ns8^RfEPGdzxuB{$^GEF1ymv$&?OFdTU-&r`tF{r&x&ue}a@(Bkv_(b{Kf&pC%& P@41Fu=3DUo?EJHCGdpQ7mr literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.inf b/Sili= con/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.inf new file mode 100644 index 0000000..665948b --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/SeCUma.inf @@ -0,0 +1,101 @@ +#/*++ +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SeCUma.inf +# +# Abstract: +# +# Component description file for SeCUma module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SeCUma + FILE_GUID =3D E4CEDF93-672A-4782-A7FD-5FC6D239377D + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SeCUmaEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|SeCUma.efi + PEI_DEPEX|SeCUma.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiStallPpiGuid + + gSeCUmaPpiGuid + + gPeiSeCPlatformPolicyPpiGuid + + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiStallPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) 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$(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= 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zM~c?Ye5kGth&oT4^UPZ8H$VOK)2knP1UtqRJJkO@_ubq-Shrif);-oQt#9UCH=3DEDb z=3Dg-WalV6qpueN=3D*K3he>BL&&>?ejmsU9(`uf~5;KEZDi=3DlLZ*WjWE8z;ey2JXh^_+ED-lDwqdBMDt*?F^9%>Hop+1c0K zcK2 +# +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SecCore + FILE_GUID =3D 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + MODULE_UNI_FILE =3D SecCore.uni + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|SecCore.efi + BIN|ResetVec.bin + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= CE8 + + +[Protocols.IA32] + +[Ppis.IA32] + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + + ## PRODUCES + gEfiTemporaryRamDonePpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitL= ib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf +# MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNul= l.inf +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibN= ull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + +[Depex.IA32] + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2011 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmControl + FILE_GUID =3D DD787473-07CE-4c63-82CE-930B33F39C09 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmControlDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|SmmControl.efi + DXE_DEPEX|SmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x8= 00 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + +[Depex.IA32] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO 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ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL 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z?e;8tu07A5Z+F^@>`Uy+>}B=3D}yW3uEueA&Ib@q*RpS{uEY=3D6|g#r}l-Df`p*t@h{a H+wK1cQZt-6 literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitDxe.inf b/= Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitDxe.inf new file mode 100644 index 0000000..448e0f9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitDxe.inf @@ -0,0 +1,253 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D VlvInitDxe + FILE_GUID =3D 93C81A74-B648-4f7f-925E-E4A0CDCC776D + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D VlvInitEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|VlvInitDxe.efi + DXE_DEPEX|VlvInitDxe.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3= 0D0 + + +[Protocols.IA32] + gDxeVlvPlatformPolicyGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + + gIgdOpRegionProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + gBmpImageGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.IA32] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid= AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMono= tonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfi= ResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchP= rotocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocol= Guid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex= b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex new file mode 100644 index 0000000..00c2f8d --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.depex @@ -0,0 +1 @@ +=02=C2=B2=EF=BF=BD}=EF=BF=BD"rC=EF=BF=BD,=EF=BF=BD2=D3=A6=EF=BF=BD=02=08;= =EF=BF=BD=EF=BF=BD=EF=BF=BD\=EF=BF=BDJ=EF=BF=BD=EF=BF=BD=06=EF=BF=BDB=EF=BF= =BD=18.=03=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/IA32RELEASE/IA32/VlvInitPeim.efi b= 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInitPeim.inf +# +# Abstract: +# +# Component description file for the VLV Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D VlvInitPeim + FILE_GUID =3D 24169E35-2454-4940-92BC-82321A2C7562 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D VlvInitPeiEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|VlvInitPeim.efi + PEI_DEPEX|VlvInitPeim.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gVlvPolicyPpiGuid + + gVlvPeiInitPpiGuid + + gEfiPeiReadOnlyVariable2PpiGuid + + +[Guids.IA32] + gEfiSetupVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= OCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $= (COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLK= GEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /D= SATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOO= T_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPI= LE /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNA= L_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTIO= N) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BU= ILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OP= TIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONV= ERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1= /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data +## MSFT:RELEASE_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.= h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:RELEASE_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:RELEASE_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:RELEASE_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 diff --git a/Silicon/Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h b/Silicon/Inte= l/Vlv2SocBinPkg/Include/Ppi/Cache.h new file mode 100644 index 0000000..b14d40e --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Include/Ppi/Cache.h @@ -0,0 +1,72 @@ +// +// This file contains an 'Intel Peripheral Driver' and is +// licensed for Intel CPUs and chipsets under the terms of your +// license agreement with Intel or your vendor. This file may +// be modified by the user, subject to additional terms of the +// license agreement +// +/** @file + + + Cache PPI definition. + +Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.
+This software and associated documentation (if any) is furnished +under a license and may only be used or copied in accordance +with the terms of the license. Except as permitted by such +license, no part of this software or documentation may be +reproduced, stored in a retrieval system, or transmitted in any +form or by any means without the express written consent of +Intel Corporation. + +**/ + +#ifndef _PEI_CACHE_PPI_H_ +#define _PEI_CACHE_PPI_H_ + +#define PEI_CACHE_PPI_GUID \ + { \ + 0xc153205a, 0xe898, 0x4c24, {0x86, 0x89, 0xa4, 0xb4, 0xbc, 0xc5, 0xc8,= 0xa2 } \ + } + +typedef struct _PEI_CACHE_PPI PEI_CACHE_PPI; + +// +// EFI_MEMORY_CACHE_TYPE +// +typedef INT32 EFI_MEMORY_CACHE_TYPE; + +// +// PEI_SET_CACHE_PPI +// +typedef +EFI_STATUS +(EFIAPI *PEI_SET_CACHE_PPI) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This, + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ); + +// +// PEI_RESET_CACHE_PPI +// +typedef +EFI_STATUS +(EFIAPI *PEI_RESET_CACHE_PPI) ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_CACHE_PPI *This + ); + +// +// PEI_CACHE_PPI +// +struct _PEI_CACHE_PPI { + PEI_SET_CACHE_PPI SetCache; + PEI_RESET_CACHE_PPI ResetCache; +}; + +extern EFI_GUID gPeiCachePpiGuid; + +#endif diff --git a/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc b/Silico= n/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc new file mode 100644 index 0000000..aefa4e2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130673321.inc @@ -0,0 +1,13056 @@ +dd 000000001h ; Header Version +dd 000000321h ; Patch ID +dd 001142014h ; DATE +dd 000030673h ; CPUID +dd 0984d6012h ; Checksum +dd 000000001h ; Loader Version +dd 000000001h ; Platform ID +dd 00000cbd0h ; Data size +dd 00000cc00h ; Total size +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h +dd 0000000a1h +dd 000020001h +dd 000000321h +dd 000000000h +dd 000000000h +dd 020140114h +dd 000003211h +dd 000000001h +dd 000030673h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 0000032f4h +dd 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file mode 100644 index 0000000..e5c50e8 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/M0130678806.inc @@ -0,0 +1,12800 @@ +dd 000000001h ; Header Version +dd 000000806h ; Patch ID +dd 011262013h ; DATE +dd 000030678h ; CPUID +dd 014d372a6h ; Checksum +dd 000000001h ; Loader Version +dd 000000001h ; Platform ID +dd 00000c7d0h ; Data size +dd 00000c800h ; Total size +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h ; reserved +dd 000000000h +dd 0000000a1h +dd 000020001h +dd 000000806h +dd 000000000h +dd 000000000h +dd 020131125h +dd 0000031f1h +dd 000000001h +dd 000030678h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 0000031f4h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 000000000h +dd 06fbddad0h +dd 097b60ec8h +dd 08252afd4h +dd 0e61f6d91h +dd 03542ee8ch +dd 084b597b4h +dd 0ec4d4fd9h +dd 0ffb27814h +dd 0156866dbh +dd 0c4bf175ah +dd 09d00ca4fh +dd 0b3e89a09h +dd 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+dd 0e6c219ebh +dd 040792f9fh +dd 0ce382acah +dd 049031196h +dd 09f99e1d0h +dd 010da299fh +dd 0e20103fdh +dd 0cb1ff4bah +dd 054137653h +dd 06ccbcae4h +dd 01b225379h +dd 0293f0143h +dd 0077a7d0fh +dd 0e6e0e7b6h +dd 025a8c9b5h +dd 067284ae4h +dd 035cfc4f1h +dd 0833ad665h +dd 09bf4fb0bh +dd 013b90783h +dd 0c3a94a2ah +dd 071b2756fh +dd 028832cach +dd 009514869h +dd 05ad02897h +dd 0ac973470h +dd 0ec1e6f9fh +dd 0fc71febbh +dd 059a286f7h +dd 0b448bbf7h diff --git a/Silicon/Intel/Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf b/S= ilicon/Intel/Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf new file mode 100644 index 0000000..e5b847d --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/MicrocodeUpdates.inf @@ -0,0 +1,51 @@ +#/*++ +# +# Copyright (c) 2005 - 2015, Intel Corporation. All rights reserved +# = =20 + +# This program and the accompanying materials are licensed and made availa= ble under + +# the terms and conditions of the BSD License that accompanies this distri= bution. =20 + +# The full text of the license may be found at = =20 + +# http://opensource.org/licenses/bsd-license.php. = =20 + +# = =20 + +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, = =20 + +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. =20 + +# = =20 + +# +# +# Module Name: +# +# MicrocodeUpdates.inf +# +# Abstract: +# +# List all of the microcode updates that you want included at build tim= e. +# +#--*/ + +[defines] +BASE_NAME =3D MicrocodeUpdates +FILE_GUID =3D 1FAE4D78-CB33-4f73-8881-A1EA8F5EDFEF +COMPONENT_TYPE =3D Microcode=20 +FFS_EXT =3D .ffs +MODULE_TYPE =3D USER_DEFINED + =20 +[sources.common] +M0F30679909.inc +M0130673321.inc +M0130678806.inc +M023067221D.inc + +[includes.common] + +[libraries.common] + +[nmake.common] diff --git a/Silicon/Intel/Vlv2SocBinPkg/Microcode/MinnowBoardMAXUEFIFirmwa= re-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/Microcode/Minno= wBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/Microcode/MinnowBoardMAXUEFIFirmware-Lice= nseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. Upon termination, the End User m= ust immediately destroy the Software or return all copies.=20 diff --git a/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmware-License= Agreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmwar= e-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/MinnowBoardMAXUEFIFirmware-LicenseAgreeme= nt-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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UNDI/I211PcieUndiDxe/X64/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.= txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/UNDI/I211PcieUndiDxe/X64/MinnowBoardMAXUE= FIFirmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. Upon termination, the End User m= ust immediately destroy the Software or return all copies.=20 diff --git a/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/IA32/MinnowBoardMA= XUEFIFirmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/UNDI= /RtkUndiDxe/IA32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/IA32/MinnowBoardMAXUEFIFi= rmware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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b/Silicon/Intel/Vlv2SocBinPkg/UNDI/RtkUndiDxe/X64/MinnowBoardMAXUEFIFir= mware-LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D Vlv2SocBinPkg.dec + PACKAGE_GUID =3D 7dbe088f-2e1a-475c-b006-55632c2a5489 + PACKAGE_VERSION =3D 0.9 + +[Includes] + Include + +[Ppis] + gPeiCachePpiGuid =3D { 0xC153205A, 0xE898, 0x4C24, { 0x86,= 0x89, 0xA4, 0xB4, 0xBC, 0xC5, 0xC8, 0xA2 }} diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex b/Sili= con/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.depex @@ -0,0 +1 @@ +=06=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.efi b/Silico= n/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/CpuPeim.efi new file mode 100644 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zlio-=3Dlhlb?^tI&2lTRjJN=3D{74O<9^!m$E%&cS>?s!&t}C}Gw>8(D+liXfmAgH6XYTIYhjaJjKAQVj?%v#ex%+bu{#lUoS2@t2Ap{!@zuoP z#3@NxN$ZlfC;c1v^5>-ZVrj4d0q%TQtPXBuPA?P1t#x0~!#`yhTu}t>^ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf b/Sil= icon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf new file mode 100644 index 0000000..79dd341 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MemoryInit.inf @@ -0,0 +1,201 @@ +#/*++ +# This file contains an 'Intel Peripheral Driver' and uniquely +# identified as "Intel Mobile Silicon Support Module" and is +# licensed for Intel Mobile CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +#--*/ +#/*++ +# +# Copyright (c) 2005 - 2012 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# MemoryInit.inf +# +# Abstract: +# +# Component description file for MemoryInit module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D MemoryInit + FILE_GUID =3D D4EE25EA-0B48-43ae-A016-4D6E8B6C43B3 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PeimMemoryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|MemoryInit.efi + PEI_DEPEX|MemoryInit.depex + +[PatchPcd.IA32] + gVlvRefCodePkgTokenSpaceGuid.PcdMemoryParameterPatchable|0x00|0x17A30 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableMemoryDown|0x01|0x16FF2 + + gVlvRefCodePkgTokenSpaceGuid.PcdDramSpeed|0x01|0x16FF4 + + gVlvRefCodePkgTokenSpaceGuid.PcdDramType|0x01|0x16FF0 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm0|0x01|0x17000 + + gVlvRefCodePkgTokenSpaceGuid.PcdEnableDimm1|0x00|0x17A32 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDataWidth|0x01|0x17008 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmDensity|0x02|0x17009 + + gVlvRefCodePkgTokenSpaceGuid.PcdDimmBusWidth|0x03|0x16FF3 + + gVlvRefCodePkgTokenSpaceGuid.PcdRankPerDimm|0x00|0x17A31 + + gVlvRefCodePkgTokenSpaceGuid.PcdTcl|0x0b|0x16FF1 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrpTrcd|0x0b|0x16FF7 + + gVlvRefCodePkgTokenSpaceGuid.PcdTwr|0x0c|0x17003 + + gVlvRefCodePkgTokenSpaceGuid.PcdTwtr|0x06|0x17002 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrrd|0x06|0x16FF6 + + gVlvRefCodePkgTokenSpaceGuid.PcdTrtp|0x06|0x16FF5 + + gVlvRefCodePkgTokenSpaceGuid.PcdTfaw|0x20|0x17001 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046|0x17004 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 6FF8 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiReadOnlyVariable2PpiGuid + + + gSeCUmaPpiGuid + + gSeCfTPMPpiGuid + + gVlvMmioPolicyPpiGuid + + gPeiCapsulePpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + gEfiGlobalVariableGuid + + gEfiVlv2VariableGuid + + gEfiMemoryConfigDataGuid + + + gEfiAcpiVariableGuid + + + gEfiPlatformInfoGuid + + gEfiSetupVariableGuid + + gEfiMemoryOverwriteControlDataGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibPei.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2DeviceRefCodePkg/Platform/Library/RamDebugLib/RamDebugLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf + +[Depex.IA32] +# gEfiPeiReadOnlyVariable2PpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /Fa$* /Oi /Od /DEFI_MEMORY_INIT /DSMM_SUPPORT /DMINNOW2_PO /DENBDT_PF_EN= ABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_= ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OP= TIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTI= ONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D= 1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /D= PCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) /D= LPDDR2_SUPPORT=3D0 /D DDR3_SUPPORT=3D1 /D LPDDR3_SUPPORT=3D0 /D DEBUG_MODE= =3D1 /D SEC_SUPPORT_FLAG /D FTPM_ENABLE /DDDR_DUAL_CHANNEL=3D1 +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MinnowBoardMAXUEFIFi= rmware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA= 32/MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/MinnowBoardMAXUEFIFirmware-= LicenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchEarlyInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Early Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchEarlyInitPeim + FILE_GUID =3D D9F5B28C-9FF1-47D6-B503-3DC23BD345FF + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PchEarlyInit + +[Packages.IA32] + MdePkg/MdePkg.dec + +[Binaries.IA32] + PE32|PchEarlyInitPeim.efi + PEI_DEPEX|PchEarlyInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 40 + + +[Protocols.IA32] + +[Ppis.IA32] + +[Guids.IA32] + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchInitPeim.depex b/= Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchInitPeim.depex new file mode 100644 index 0000000..0e34453 --- /dev/null +++ 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literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchInitPeim.inf b/Si= licon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchInitPeim.inf new file mode 100644 index 0000000..1a508fc --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchInitPeim.inf @@ -0,0 +1,150 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2016 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitPeim.inf +# +# Abstract: +# +# Component description file for the PCH Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchInitPeim + FILE_GUID =3D FD236AE7-0791-48c4-B29E-29BDEEE1A838 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InstallPchInitPpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|PchInitPeim.efi + PEI_DEPEX|PchInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= 2B0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x52B8 + + +[Protocols.IA32] + +[Ppis.IA32] + ## CONSUMES + gEfiPeiMemoryDiscoveredPpiGuid + + ## CONSUMES + gPchPlatformPolicyPpiGuid + + gEfiPeiStallPpiGuid + + gPchPeiInitPpiGuid + + gPchUsbPolicyPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## HOB + gEfiPlatformInfoGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# gPchPlatformPolicyPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.= depex b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.depex new file mode 100644 index 0000000..028e7ac --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSmbusArpDisabled.depex @@ -0,0 +1 @@ +=025=EF=BF=BDc=EF=BF=BD2=EF=BF=BDI=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF= =BF=BD=EF=BF=BD=1Al=02=EF=BF=BDoL=1Fk=EF=BF=BD=EF=BF=BDH=EF=BF=BD=01=EF=BF= =BD=EF=BF=BD=EF=BF=BD=EF=BF=BD}V=03=08 \ No newline at end of file diff --git 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zN>X3Ht(ow1a35ix0ocUfDv`}tC@S~$cinZDee)LJ(ZQ^UXifaB63xBd^HQhH7%e`O zvp;-%_p!RMpZ~~p-%o2&M~lC|WLd+aWfcc8?-b1)jLz~G{P%{3tbh2!oO{nOF)8^2 zy}e5vPnO=3DMFL?Bs-+w4uJzmr;38wC(PP|gyvO)`|Cedcrs>m{r5B`I(*5Z@>1{^8@d4w*#+ey&Gj7T-EU#L=3D zdHJs8A1)tXuFVuOe~|fH=3DF6GyWPXr&Ia9r2)r!Iu_7%-5dR9EJ;$YVCtar2inze9c z;mRE=3D?_T+Xm5;7`X=3DPe=3Dc6NDoUH0ACf$U#r_hx^VeJOjcX`w00bf4)#)2~gvrfca< Gu>S)mr?-v( literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSpiPeim.inf b/Sil= icon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSpiPeim.inf new file mode 100644 index 0000000..9b80bda --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchSpiPeim.inf @@ -0,0 +1,139 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiPeim.inf +# +# Abstract: +# +# Component description file for the SPI PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchSpiPeim + FILE_GUID =3D AA652CB9-2D52-4624-9FAE-D4E58B67CA46 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InstallPchSpi + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.IA32] + PE32|PchSpiPeim.efi + PEI_DEPEX|PchSpiPeim.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 700 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2708 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiSpiPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.IA32] +# TRUE + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC (EBC is for build on= ly) +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex new file mode 100644 index 0000000..05a6cfe --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.depex @@ -0,0 +1 @@ +=02H=EF=BF=BD=08t=EF=BF=BD=EF=BF=BD=EF=BF=BDN=EF=BF=BD=EF=BF=BD=C4=BE=EF= =BF=BD=EF=BF=BD=EF=BF=BD=10=02s=05+=EF=BF=BDN+1J=EF=BF=BD=1A=EF=BF=BDV{PD,= =03=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.efi b/Silicon= /Intel/Vlv2SocBinPkg/X64DEBUG/IA32/PchUsb.efi new file mode 100644 index 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This file may be +# modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmAccess.inf +# +# Abstract: +# +# Component description file for SmmAccess module +# +# Revision History: +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiSmmAccess + FILE_GUID =3D B4E0CDFC-30CD-4b29-A445-B0AA95A532E4 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmAccessDriverEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PeiSmmAccess.efi + PEI_DEPEX|PeiSmmAccess.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1780 + + +[Protocols.IA32] + +[Ppis.IA32] + gPeiSmmAccessPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid + + ## SOMETIMES_PRODUCES + gEfiPeiFirmwareVolumeInfo2PpiGuid + + +[Guids.IA32] + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + ## SOMETIMES_PRODUCES ## GUID # FV File System Guid. + gEfiFirmwareFileSystem2Guid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation StackHob + gEfiHobMemoryAllocStackGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation BspStoreHob + gEfiHobMemoryAllocBspStoreGuid + + ## SOMETIMES_PRODUCES ## HOB # MemoryAllocation ModuleHob + gEfiHobMemoryAllocModuleGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/PeiServicesLib/PeiServicesLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/PeiHobLib/PeiHobLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiMemoryDiscoveredPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SmmControl.inf +# +# Abstract: +# +# Component description file for SmmControl module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiSmmControl + FILE_GUID =3D FF456B9C-0DC7-4682-9E92-0DE84B6E4067 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmControlPeiDriverEntryInit + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|PeiSmmControl.efi + PEI_DEPEX|PeiSmmControl.depex + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x1= 310 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1318 + + +[Protocols.IA32] + gEfiSmmControl2ProtocolGuid + + +[Ppis.IA32] + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# TRUE + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) 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/DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_IA32_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_IA32_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_IA32_NASM_FLAGS =3D -Ox -f win32 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.bin b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.bin new file mode 100644 index 0000000000000000000000000000000000000000..fe3e741a3bb4bd78ea0bd2cf65e= 3ec14b77e2d4c GIT binary patch literal 64 scmaF&4gwgUV1Iz)YgrfvNGm$0w!i*&9xgIr!ppz^fxL<^6Cn@=3D0O7O~{r~^~ literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.com b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/ResetVec.com new file mode 100644 index 0000000000000000000000000000000000000000..fe3e741a3bb4bd78ea0bd2cf65e= 3ec14b77e2d4c GIT binary patch literal 64 scmaF&4gwgUV1Iz)YgrfvNGm$0w!i*&9xgIr!ppz^fxL<^6Cn@=3D0O7O~{r~^~ literal 0 HcmV?d00001 diff --git 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b/Silicon= /Intel/Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.inf new file mode 100644 index 0000000..c3d066f --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/IA32/SeCUma.inf @@ -0,0 +1,116 @@ +#/*++ +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SeCUma.inf +# +# Abstract: +# +# Component description file for SeCUma module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SeCUma + FILE_GUID =3D E4CEDF93-672A-4782-A7FD-5FC6D239377D + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SeCUmaEntry + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|SeCUma.efi + PEI_DEPEX|SeCUma.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x1C20 + + +[Protocols.IA32] + +[Ppis.IA32] + gEfiPeiStallPpiGuid + + gSeCUmaPpiGuid + + gPeiSeCPlatformPolicyPpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + +[Depex.IA32] +# gEfiPeiStallPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) 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This file may be +# modified by the user, subject to additional terms of the +# license agreement +# +## @file +# SecCore module that implements the SEC phase. +# NOTE: This module was replaced by UefiCpuPkg/SecCore/SecCore.inf +# +# This is the first module taking control of the platform upon power-on/r= eset. +# It implements the first phase of the security phase. The entry point fu= nction is +# _ModuleEntryPoint in PlatformSecLib. The entry point function will swit= ch to +# protected mode, setup flat memory model, enable temporary memory and +# call into SecStartup(). +# +# Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+# +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SecCore + FILE_GUID =3D 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + MODULE_UNI_FILE =3D SecCore.uni + +[Packages.IA32] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|SecCore.efi + BIN|ResetVec.bin + +[PatchPcd.IA32] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 188 + + +[Protocols.IA32] + +[Ppis.IA32] + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + + ## PRODUCES + gEfiTemporaryRamDonePpiGuid + + +[Guids.IA32] + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/PlatformHookSerialLib/PlatformHookSerialInitL= ib.inf +# Vlv2TbltDevicePkg/Library/PlatformCmosLib/PlatformCmosLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# DeviceCommonPkg/Library/CmosAccessLib/CmosAccessLib.inf +# UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +# MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# Vlv2TbltDevicePkg/Library/PlatformSecLib/PlatformSecLib.inf +# MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf +# MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraAction= LibDebug.inf +# MdeModulePkg/Library/CpuExceptionHandlerLibNull/CpuExceptionHandlerLibN= ull.inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf + +[Depex.IA32] + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OBJCOPY_FLAGS =3D objcopy not needed for +## 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the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInitPeim.inf +# +# Abstract: +# +# Component description file for the VLV Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D VlvInitPeim + FILE_GUID =3D 24169E35-2454-4940-92BC-82321A2C7562 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D VlvInitPeiEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.IA32] + PE32|VlvInitPeim.efi + PEI_DEPEX|VlvInitPeim.depex + +[PatchPcd.IA32] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x2260 + + +[Protocols.IA32] + +[Ppis.IA32] + gVlvPolicyPpiGuid + + gVlvPeiInitPpiGuid + + gEfiPeiReadOnlyVariable2PpiGuid + + +[Guids.IA32] + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + ## SOMETIMES_CONSUMES ## GUID + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.= inf +# MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLib= Idt.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDe= bugLibReportStatusCode.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not nee= ded for +## MSFT:DEBUG_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Ref= erenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /= DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_= WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) = $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTI= ONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION)= /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPP= ORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECU= RE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /coff = /Zd /Zi $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000= h /DNOCS_S3_SUPPORT +## MSFT:DEBUG_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /GS-= /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /Gy /Zi /G= m /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_E= NUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTI= ON) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_= OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPT= ION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_= SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_= SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE= /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_= VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION)= $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUIL= D_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTI= ONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVER= T_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /= DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC= /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO = /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPT= ION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_= FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPA= CT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CO= NFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_S= UPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUIL= D_OPTIONS) +## MSFT:DEBUG_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNO= RE:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.p= data,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_B= OOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_IA32_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_IA32_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/Dptf.inf @@ -0,0 +1,219 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +# +#**/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D Dptf + FILE_GUID =3D 1D000AE9-756B-4937-B736-1F3D96A5A8F0 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D DptfDriverEntry + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|Dptf.efi + DXE_DEPEX|Dptf.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x69F8 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 9F0 + + +[Protocols.X64] + # CONSUMED + gEfiAcpiSdtProtocolGuid + + # CONSUMED + gEfiAcpiTableProtocolGuid + + # CONSUMED + gEfiGlobalNvsAreaProtocolGuid + + gDxeVlvPlatformPolicyGuid + + gEfiI2cBusProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/I2CLib/I2CLib.= inf +# Vlv2DeviceRefCodePkg/Platform/Library/I2cStackLib/I2cDriverLib/I2cDrive= rLib.inf + +[Depex.X64] +# (gEfiVariableArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND= gEfiAcpiSdtProtocolGuid AND gEfiAcpiTableProtocolGuid AND gDxeVlvPlatformP= olicyGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +# DRIVER_BINDING =3D gSampleDrvDriverBinding +# COMPONENT_NAME =3D gSampleDrvComponentName +# COMPONENT_NAME2 =3D gSampleDrvComponentName2 +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) 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z9h_txjAd-nAxYLDOnE&SWc9vV(U~5WWF2-Q(q!~qmLJo_Iwq;Vm2^ZG>xiTQ zlFo9_@trMkrhW2 z^azmfMtlzbM_xjfL&iXy;_pY}#q-^N5q3;IY2LFb@hKvot4fckd4fz`iI9|1KT(d0S RI{&(j>yY{1&;Ljd{2zvYJU;*c literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/GraphicDxeInitSmm.inf= b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/GraphicDxeInitSmm.inf new file mode 100644 index 0000000..4e00475 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/GraphicDxeInitSmm.inf @@ -0,0 +1,265 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D GraphicDxeInitSmm + FILE_GUID =3D 99EC6206-AA45-4CAE-B630-866755241C8A + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D GraphicDxeInitSmmEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|GraphicDxeInitSmm.efi + SMM_DEPEX|GraphicDxeInitSmm.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xffffffff|0xC618 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC= 610 + + +[Protocols.X64] + gDxeVlvPlatformPolicyGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf +# MdePkg/Library/SmmIoLib/SmmIoLib.inf + +[Depex.X64] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGui= d) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCp= uArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounte= rArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchPr= otocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid= AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gE= fiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfi= SmmAccess2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 -g diff --git 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z&X95!s*q{oXZkxH>pLl9tTU?yEf|P?EpZRDQu?P_{Zj_0`XEjI`;brl`EjO`i8Zi2 zVuyDe*>QA-v*W~$Pj^_&>CKtVSj8sHy1S*H!o;j(p=3DSC*Sw~Aee>q# utR% literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.inf b/Silicon/= Intel/Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.inf new file mode 100644 index 0000000..5c67ab1 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/ISPDxe.inf @@ -0,0 +1,247 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# IspDxe.inf +# +# Abstract: +# +# + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D ISPDxe + FILE_GUID =3D 5A38B969-CD6A-4814-82E6-559F840BBC58 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D ISPDxeEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|ISPDxe.efi + DXE_DEPEX|ISPDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x9= 140 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x9148 + + +[Protocols.X64] + gEfiAcpiTableProtocolGuid + + gEfiAcpiSdtProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.X64] +# (gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid AND gEfiGlobalNv= sAreaProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND = (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGui= d AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMon= otonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEf= iResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArch= ProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoco= lGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGui= d) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/MinnowBoardMAXUEFIFir= mware-LicenseAgreement-Final.txt b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64= /MinnowBoardMAXUEFIFirmware-LicenseAgreement-Final.txt new file mode 100644 index 0000000..c5a77e9 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/MinnowBoardMAXUEFIFirmware-L= icenseAgreement-Final.txt @@ -0,0 +1,134 @@ +MinnowBoard MAX UEFI Development Kit (MB-UDK)=20 +PRODUCTION LICENSE AGREEMENT=20 + +IMPORTANT =EF=BF=BD READ BEFORE COPYING, INSTALLING OR USING.=20 + +Do not copy, install, use or load software identified in this Agreement or= any associated materials until you have carefully read the following terms= and conditions. By copying, installing, using or loading the software iden= tified in this Agreement or any associated materials, you agree to the term= s of this Agreement. If you do not wish to so agree, do not copy, install, = use or load the software or any associated materials. If you are an employ= ee, representative or agent of a legal entity, you represent and warrant th= at you have the authority to bind that legal entity to this Agreement. + +General Terms and Conditions=20 + +This agreement (=EF=BF=BDAgreement=EF=BF=BD) is by and between Licensee an= d Intel Corporation, a Delaware corporation, having its principal place of = business at 2200 Mission College Boulevard, Santa Clara, California 95054 (= =EF=BF=BDIntel=EF=BF=BD) and is effective as of the first date Licensee cop= ies, installs, uses or loads the software identified in this Agreement or a= ny associated materials (=EF=BF=BDEffective Date=EF=BF=BD). =20 + +1.0 DEFINITIONS=20 + +1.1 =EF=BF=BDASL Code=EF=BF=BD means code written in the =EF=BF=BDACPI so= urce language=EF=BF=BD and designed and delivered to Licensee by Intel and = designed to be compatible with Intel products. Such ASL Code remains ASL C= ode regardless of any legends in header files of the ASL Code.=20 +1.2 =EF=BF=BDAssembly Code=EF=BF=BD means code written in the =EF=BF=BDas= sembly source language=EF=BF=BD and designed and delivered to Licensee by I= ntel under this Agreement.=20 +1.3 =EF=BF=BDMBM-UDK=EF=BF=BD means the MinnowBoard MAX UEFI Development = Kit, which is an Intel implementation of the=20 +UEFI specification, and is based on the Intel=EF=BF=BD UEFI Development Ki= t 2014 (Intel=EF=BF=BD UDK2014), consisting of=20 +MB-UDK Libraries, ASL Code, DXE Driver, DXE Foundation Code, PEI Foundatio= n Code, Peripheral Drivers (including GOP and UEFI UNDI), PEI Modules, Asse= mbly Code, C Code and Reference Drivers together, as well as any and all do= cumentation and tools, provided by Intel for the purposes of implementation= .=20 +1.4 =EF=BF=BDMBM-UDK Libraries=EF=BF=BD means the core library services o= ffered in the MinnowBoard MAX UEFI Development=20 +Kit.=20 +1.5 =EF=BF=BDBoot Loader=EF=BF=BD means a device and use-case-specific fi= rmware program a computer=EF=BF=BDs processor uses to get the computer syst= em started after power-on, with some basic hardware initialization, until h= andoff to the operating system.=20 +1.6 =EF=BF=BDBSD License=EF=BF=BD means the Berkeley Software Distributio= n License, which is a family of permissive free software licenses created f= or the original Berkeley Software Distribution operating system.=20 +1.7 =EF=BF=BDC Code=EF=BF=BD means code written in the =EF=BF=BDC source = language=EF=BF=BD and designed and delivered to Licensee by Intel under thi= s Agreement.=20 +1.8 =EF=BF=BDCustomer=EF=BF=BD means Original Equipment Manufacturer (a c= ompany that makes computer systems for sale under its own brand name), Inde= pendent Authorized Developer (a company that performs services for Licensee= in the development of Licensee=EF=BF=BDs products), or Original Design Man= ufacturer (a company that=20 +designs and manufactures computer systems for Independent Authorized Devel= opers and Original Equipment Manufacturers) but excluding End Users.=20 +1.9 =EF=BF=BDDerived Object Code=EF=BF=BD means the subset of Derivative = Works that is the Object Code derived from Source Code or Derived Source Co= de.=20 +1.10 =EF=BF=BDDerived Source Code=EF=BF=BD means the subset of Derivative= Works that is the source code derived from Source Code by modifying the So= urce Code in any way.=20 +1.11 =EF=BF=BDDerivative Works=EF=BF=BD means those bodies of work define= d in 17 U.S.C. =EF=BF=BD101 as =EF=BF=BDderivative works=EF=BF=BD of existi= ng copyrighted material. For purposes of this Agreement, Derivative Works = include both Derived Source Code and Derived Object Code.=20 +1.12 =EF=BF=BDDXE Driver=EF=BF=BD means Driver Execution Environment driv= er, which is a hardware device driver compliant with the execution environm= ent as defined in the UEFI specification.=20 +1.13 =EF=BF=BDDXE Foundation Code=EF=BF=BD means the foundational Driver = Execution Environment code that provides the standard function and services= that are available to the DXE Drivers.=20 +1.14 =EF=BF=BDEnd User=EF=BF=BD means a purchaser or recipient or user of= Licensee=EF=BF=BDs computer products who does not resell Licensee=EF=BF=BD= s products in the normal course of the End User=EF=BF=BDs business. =20 +1.15 =EF=BF=BDFirmware=EF=BF=BD means the programming code that is insert= ed into the programmable read-only memory of a computer system, thus becomi= ng a permanent part of a particular computing device.=20 +1.16 =EF=BF=BDIntel Processor=EF=BF=BD means processors designed by Intel= and released by or on behalf of Intel and marketed under Intel=EF=BF=BDs (= or Intel licensed) trademarks.=20 +1.17 =EF=BF=BDLicensee=EF=BF=BD means the individual accepting these term= s or, if the individual is accepting these terms on behalf of a legal entit= y (such as a corporation, partnership, agency, etc.), =EF=BF=BDLicensee=EF= =BF=BD means the legal entity.=20 +1.18 =EF=BF=BDObject Code=EF=BF=BD means the binary version of the Source= Code, including all computer programming code, entirely in binary form, wh= ich is directly executable by a computer and includes those help, message, = overlay, and other files necessary for supporting the intended use of the e= xecutable code.=20 +1.19 =EF=BF=BDPEI Foundation Code=EF=BF=BD means Pre-extensible firmware = interface (=EF=BF=BDPEFI=EF=BF=BD) initialization foundation code, which pe= rforms basic hardware initialization in order to load and execute the DXE F= oundation Code.=20 +1.20 =EF=BF=BDPEI Modules=EF=BF=BD means PEFI initialization modules, whi= ch are code modules that perform basic environmental set up prior to initia= lization of DXE Foundation Code.=20 +1.21 =EF=BF=BDPeripheral Drivers=EF=BF=BD means code that initializes and= operates hardware devices that are peripheral to the Intel Processor.=20 +1.22 =EF=BF=BDReference Drivers=EF=BF=BD means those drivers supplied as= part of the Source Code that are marked or tagged by Intel as =EF=BF=BDref= erence drivers=EF=BF=BD.=20 +1.23 =EF=BF=BDSource Code=EF=BF=BD means the source code of the MB-UDK Li= braries and Reference Drivers delivered to Licensee by Intel under this Agr= eement, along with all Intel-delivered tools, documentation, specifications= , and schematics related thereto.=20 +1.24 =EF=BF=BDSubsidiaries=EF=BF=BD means, with respect to any legally re= cognizable entity, any entity Controlling, Controlled by, or under common C= ontrol with the entity. =EF=BF=BDControl=EF=BF=BD means (i) ownership of f= ifty percent (50%) or more of the outstanding shares representing the right= to vote for members of the directors or other managing officers of the ent= ity, or (ii) for an entity which does not have outstanding shares, fifty pe= rcent (50%) or more of the ownership interest representing the right to mak= e decisions for the entity. An entity will be deemed a Subsidiary only so = long as the Control exists.=20 +1.25 =EF=BF=BDUDK2014=EF=BF=BD means the Intel=EF=BF=BD UEFI Development = Kit 2014 (Intel=EF=BF=BD UDK2014), which is an openly available implementat= ion of the UEFI framework provided by Intel under BSD License terms.=20 +1.26 =EF=BF=BDUEFI=EF=BF=BD means the Unified Extensible Firmware Interf= ace, which is an industry standard detailing an interface that helps hand o= ff control of the system for the pre-boot environment (i.e., after the syst= em is powered on, but before the operating system starts) to an operating s= ystem.=20 + +2.0 LICENSE RIGHTS AND CONDITIONS=20 + +2.1 LIMITED COPYRIGHT LICENSE: Subject to the terms and conditions of thi= s Agreement, Intel grants to Licensee a limited, non-exclusive, non-transfe= rable, non-sublicensable, worldwide and royalty-free license under Intel=EF= =BF=BDs copyrights to: =20 +Reproduce and prepare Derivative Works of the Source Code solely for Licen= see=EF=BF=BDs own internal use, to design, develop, modify or debug Derivat= ive Works that operate in or in conjunction only with Intel Chipsets or Int= el Processors as specified in Exhibit A; =20 +Reproduce and distribute MB-UDK internally for Licensee=EF=BF=BDs own use = in developing and maintaining products or services supporting Intel Chipset= s or Intel Processors as specified in Exhibit A; and =20 +Distribute Object Code and Derived Object Code externally to Licensee=EF= =BF=BDs End Users, either directly or through Licensee=EF=BF=BDs usual dist= ribution channels and methods, but only for use with Intel Chipsets or Inte= l Processors as specified in Exhibit A. Licensee will distribute all Licens= ed Programs under an end user license agreement (=EF=BF=BDEnd User License= =EF=BF=BD) containing at a minimum the terms and conditions set forth in Ex= hibit B.=20 +2.2 ADDITIONAL CONDITIONS: The rights granted under this Agreement are al= so subject to the following=20 +limitations: =20 +Licensee will not make any statement that the Derivative Works are "certif= ied," or that performance is guaranteed, by Intel;=20 +Licensee will not disassemble, reverse engineer, or decompile any Object C= ode provided to Licensee.=20 +Licensee will not use Intel's name or trademarks without prior written per= mission; and=20 +Licensee may not disclose, distribute or make commercial use of the MB-UDK= as a stand-alone product.=20 +Except as specifically permitted in Sections 2.1, above, Licensee is not l= icensed to use the MB-UDK in any other manner, including for Licensee=EF=BF= =BDs other internal or business use or for use in association with any othe= r products. Licensee will not license MB-UDK to any third party. Licensee w= ill include all copyright notices in all full and partial copies of the MB-= UDK, including all Derived Source Code, and will not deface, obscure or alt= er any copyright notices. =20 +Licensee is not obligated to provide Intel with comments or suggestions re= garding Derived Source Code or the MB-UDK received under this Agreement. S= hould Licensee, however, provide Intel with designs, comments or suggestion= s for the modification, correction, improvement or enhancement of the MB-UD= K or Intel products which may embody the MB-UDK (collectively, =EF=BF=BDFee= dback=EF=BF=BD), then Licensee grants to Intel a non-exclusive, irrevocable= , worldwide, royalty-free license, including the right to sublicense Intel = licensees and customers, under Licensee=EF=BF=BDs intellectual property rig= hts in the Feedback, and the rights to use and disclose the Feedback in any= manner Intel chooses and to display, perform, copy, have copied, make, hav= e made, use, sell, offer to sell, and otherwise dispose of Intel=EF=BF=BDs = and its sublicenses=EF=BF=BD products embodying the Feedback in any manner = and via any media Intel chooses, but without reference to the source of the= Feedback. =20 + +3.0 DISCLAIMER OF WARRANTY=20 +Neither Intel nor its suppliers make any representation or warranty or con= dition of any kind whether express or implied (either in fact or by operati= on of law) with respect to the MB-UDK. Intel and its suppliers expressly d= isclaim all warranties or conditions of merchantability or fitness for a pa= rticular purpose. Intel and its suppliers do not warrant that the MB-UDK i= s error-free or that operation of the MB-UDK will be secure or uninterrupte= d and hereby disclaim any and all liability on account thereof. There is al= so no implied warranty of non-infringement. MB-UDK is licensed on an "as is= " basis and neither Intel nor its suppliers will provide any support, assis= tance, installation, training or other services. Intel and its suppliers m= ay provide any updates, enhancements or extensions at their sole discretion= .=20 + +4.0 LIMITATION OF LIABILITY=20 +In no event will Intel or its suppliers be liable for: (a) any representat= ion or warranty made to any third party by Licensee, any agent of Licensee = or distributor; (b) failure of the MB-UDK to perform as expected; (c) failu= re of the MB-UDK to provide security; or (d) any use of the MB-UDK or the r= esults or information obtained or decisions made by licensee=EF=BF=BDs use = of the MB-UDK.=20 +Intel and its suppliers will not be liable for any direct, indirect, speci= al, incidental or consequential damages of any kind, even if advised of the= possibility of these damages.=20 + +5.0 PROTECTION AND SECURITY=20 +Licensee acknowledges that information and materials disclosed or provided= to Licensee pursuant to this Agreement may contain Intel trade secrets. S= uch trade secrets are protected by the provisions of the applicable nondisc= losure agreement(s) between the parties. Licensee will not make MB-UDK or = Derivative Works available in whole or in part or in any form, to any perso= n other than Licensee's employees who are designated to work on Licensee's = development effort authorized hereunder and who have a specific need for ac= cess to MB-UDK. Licensee agrees to instruct these employees of his or her = obligations with respect to use, copying, protection, and security of MB-UD= K and associated documentation. Notwithstanding the earlier termination of= this Agreement, the obligations of this section are to remain in effect un= til the time as MB-UDK becomes publicly known, through no act or failure to= act on Licensee's or Subsidiary=EF=BF=BDs part.=20 + +6.0 ASSIGNMENT, SALE OR TRANSFER=20 +Licensee will not assign, sublicense, or otherwise transfer this Agreement= or any right or obligation hereunder without Intel's prior written consent= , which consent will not be unreasonably withheld in the event Licensee is = acquired by an entity that is not a competitor of Intel. Any attempt to do = so will be null and void.=20 + +TERMINATION=20 + +Licensee may terminate this Agreement and the licenses granted in the Agre= ement at any time upon Intel=EF=BF=BDs receipt of written notice. =20 +Intel may terminate this Agreement and any licenses granted in the Agreeme= nt at any time if Licensee fails to cure any material breach of this Agreem= ent within thirty (30) days after notice of the breach. Such termination w= ill not prejudice Intel's right to damages or any other remedy available at= law or in equity.=20 +Upon termination of the Agreement or any license granted hereunder for any= reason whatsoever, Licensee will completely remove MB-UDK from all Derived= Source Code. In the event of any termination, Licensee will, at Intel's op= tion, either return to Intel or destroy the original and all full or partia= l copies of MB-UDK, including those portions in Derived Source Code, and ce= rtify to Intel that they have been destroyed.=20 +The following sections will survive expiration or termination of this Agre= ement: sections 2.2, 2.3, 2.4, 3, 4, 5, 7, 8, 9 and 10. =20 + +OWNERSHIP=20 + +MB-UDK and all copies, and any updates provided by Intel, in whole or in p= art, are and will remain the property of Intel or its suppliers. Licensee = understands and agree that no license under any Intel patent, copyright (ex= cept as expressly described in Sections 2.1, above), trade secret or other = intellectual property right is granted or conferred upon Licensee in this A= greement or by the providing of the MB-UDK by Intel to Licensee hereunder, = either expressly, by implication, inducement, estoppel or otherwise, and th= at any further license under the intellectual property rights must be expre= ss and in writing. =20 +Title in and to the Derived Source Code will be held by Licensee or Licens= ee=EF=BF=BDs suppliers as appropriate, subject to Intel=EF=BF=BDs underlyin= g ownership of the MB-UDK.=20 + +9.0 EXPORT CONTROL=20 +Neither party will export, either directly or indirectly, any product, ser= vice or technical data or system incorporating the MB-UDK without first obt= aining any required license or other approval from the U.S. Department of C= ommerce or any other agency or department of the United States Government. = In the event any product or software is exported from the United States or= re-exported from a foreign destination by either party, that party will en= sure that the distribution and export/re-export or import of the product or= software is in compliance with all laws, regulations, orders, or other res= trictions of the U.S. Export Administration Regulations and the appropriate= foreign government. Both parties agree that neither it nor any of its Sub= sidiaries will export/re-export any software, technical data, process, prod= uct, or service, directly or indirectly, to any country for which the Unite= d States government or any agency thereof or the foreign government from wh= ere it is shipping requires an export license, or other governmental approv= al, without first obtaining the license or approval.=20 + +GENERAL=20 + +Any dispute arising directly under the express terms of this Agreement or = the grounds for termination of any rights granted under this Agreement will= be resolved as follows: First, within forty five (45) days from one party= =EF=BF=BDs written request to the other, senior executives of both parties = will meet to attempt to resolve the dispute. If the senior executives canno= t resolve the dispute, either party may then make a written demand for form= al dispute resolution by tendering to the other party notice of the dispute= and its intent to invoke the terms of this Section 10.1. The parties agree= to meet within ninety (90) days of the demand with an impartial mediator s= elected by mutual agreement to participate in a one-day, non-binding mediat= ion. In the event the parties cannot agree on a mediator, they will each se= lect one nominator, who will not at that time be employed by either party, = and the two nominators will agree on and appoint the mediator. If the parti= es have not resolved the dispute or claim within thirty (30) days after the= one-day, non-binding mediation, either party may begin litigation proceedi= ngs.=20 +This is the complete and exclusive Agreement between the parties relating = to this subject matter. No amendment will be effective unless in writing si= gned by authorized representatives of both parties.=20 +The terms and conditions stated in the Agreement are declared to be severa= ble. If any paragraph, provision, or clause in this Agreement will be found= or be held to be invalid or unenforceable in any jurisdiction in which thi= s Agreement is being performed, the remainder of this Agreement will be val= id and enforceable and the=20 +parties will use good faith to negotiate a substitute, valid and enforceab= le provision which most nearly effects the parties' intent in entering into= this Agreement.=20 +Any claim arising under or relating to this Agreement, will be governed by= the laws of the State of Delaware, excluding its conflicts of laws provisi= ons. The parties agree that all disputes and litigation regarding the abov= e defined claims will be subject to the exclusive jurisdiction of the court= s of the State of Delaware or of the Federal courts sitting in Delaware.=20 + +[END OF GENERAL TERMS AND CONDITIONS]=20 + +EXHIBIT A=20 +SUPPORTED PLATFORMS=20 +=20 +List of supported platforms with which the MB-UDK may be used:=20 + BayTrail-I Atom E3825, E3845, E3815,=20 + E38xx E3826, E3827=20 + +EXHIBIT B=20 +MINIMUM OBJECT CODE=20 +END-USER LICENSING TERMS=20 +=20 +Licensee will ensure that terms at least as restrictive and protective of = Intel=EF=BF=BDs interests as the following minimum terms, as described belo= w, are included in all End User Licenses. These minimum terms apply to dist= ribution of Licensed Programs (object code) only. =20 + +An End User may:=20 +Copy the Licensed Programs and accompanying materials (=EF=BF=BDSoftware= =EF=BF=BD) onto the End User=EF=BF=BDs computers for End User=EF=BF=BDs int= ernal use solely for development and maintenance of the End User=EF=BF=BDs = products supporting Intel Chipsets or Intel Processors.=20 + +An End User may not:=20 +Sublicense or further distribute the Software, or permit simultaneous use = of the Software by more than one user.=20 +Reverse engineer, decompile, or disassemble the Software.=20 +Use, copy, modify, sell or transfer the Software except as provided in thi= s Exhibit B.=20 +Remove any copyright notices from the Software or any copies thereof.=20 +Export or import Software in violation of any law, regulation, order or ot= her restriction of the United States government and its agencies, or any fo= reign government.=20 + +An End User will also be made aware of and agree that:=20 + +Title to the Software and all copies thereof remain with Licensee or its s= uppliers, as applicable, and the Software is copyrighted and protected by U= nited States and international copyright laws.=20 + +Except as expressly provided in this Exhibit B, End User is not granted an= y express or implied right under Intel patents, copyrights, trademarks or t= rade secret information.=20 + +The Software is provided =EF=BF=BDAS IS=EF=BF=BD without any express or im= plied warranty of any kind, including warranties=20 +of merchantability, noninfringement of third-party intellectual property o= r fitness for any particular purpose.=20 + +Liability to End User is completely disclaimed to the extent allowed by la= w, including without limitation all indirect, special, incidental, and cons= equential damages of any kind.=20 + +The technical data and Software covered by this license is a =EF=BF=BDComm= ercial Item,=EF=BF=BD as the term is defined by the FAR 2.101 (48 C.F.R. 2.= 101) and is =EF=BF=BDcommercial computer software=EF=BF=BD and =EF=BF=BDcom= mercial computer software documentation=EF=BF=BD as specified under FAR 12.= 212 (48 C.F.R. 12.212) or DFARS 227.7202 (48 C.F.R. 227.7202), as applicabl= e. This commercial computer software and related documentation is provided = to End Users for use by and on behalf of the U.S. Government, with only tho= se rights as are granted to all other End Users pursuant to the terms and c= onditions of the End User License. Use for or on behalf of the U.S. Governm= ent is permitted only if the party acquiring or using this software is prop= erly authorized by an appropriate U.S. Government official. This use by or = for the U.S. Government clause is in lieu of, and supersedes, any other FAR= , DFARS, or other provision that addresses Government rights in the compute= r software or documentation covered by this license.=20 + +The End User License may be terminated at any time if the End User is in b= reach of any of its terms and conditions. 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchBiosWriteProtect.inf +# +# Abstract: +# +# Component description file for the PchBiosWriteProtect driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchBiosWriteProtect + FILE_GUID =3D B8B8B609-0B6C-4b8c-A731-DE03A6C3F3DC + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InstallPchBiosWriteProtect + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchBiosWriteProtect.efi + SMM_DEPEX|PchBiosWriteProtect.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= E10 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5E18 + + +[Protocols.X64] + gDxePchPlatformPolicyProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf + +[Depex.X64] +# (gDxePchPlatformPolicyProtocolGuid AND gEfiSmmBase2ProtocolGuid = AND gEfiSmmIchnDispatchProtocolGuid AND gEfiSmmSwDispatch2Protoco= lGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProt= ocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCp= uArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounte= rArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchPr= otocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid= AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gE= fiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfi= SmmBase2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT 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a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf b/Sili= con/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf new file mode 100644 index 0000000..4ace397 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchInitDxe.inf @@ -0,0 +1,278 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitDxe.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchInitDxe + FILE_GUID =3D DE23ACEE-CF55-4fb6-AA77-984AB53DE823 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PchInitEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchInitDxe.efi + DXE_DEPEX|PchInitDxe.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 93C0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0x293C8 + + +[Protocols.X64] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/Asl= Update/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf + +[Depex.X64] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGui= d AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (g= EfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND= (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocol= Guid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocol= Guid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AN= D gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTime= rArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArc= hProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProt= ocolGuid AND gEfiAcpiSdtProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS 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contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchInitSmm.inf +# +# Abstract: +# +# Component description file for Pch Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchInitSmm + FILE_GUID =3D D7B10D4E-67E6-4C74-83E9-F9AF0ACC33CC + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D PchInitSmmEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchInitSmm.efi + SMM_DEPEX|PchInitSmm.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xF= 010 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xffffffff|0xF018 + + +[Protocols.X64] + ## CONSUMES + gDxePchPlatformPolicyProtocolGuid + + ## CONSUMES + gEfiPchS3SupportProtocolGuid + + ## PRODUCES + gEfiPchInfoProtocolGuid + + + gEfiAcpiTableProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + ## PRODUCES + gLpssDummyProtocolGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + gEfiAcpiSdtProtocolGuid + + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformInfoGuid + + gEfiEventExitBootServicesGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/SampleCode/Library/Asl= Update/Dxe/PchAslUpdateLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf + +[Depex.X64] +# (gDxePchPlatformPolicyProtocolGuid AND gDxePchPolicyUpdateProtocolGui= d AND gEfiPchS3SupportProtocolGuid AND gEfiSmmControl2ProtocolGuid) AND (g= EfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND= (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2Pr= otocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gE= fiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gE= fiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRunti= meArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtoc= olGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGu= id AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfiAcpiTableProtocolGuid AN= D gEfiAcpiSdtProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) 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license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchPcieSmm.inf +# +# Abstract: +# +# Component description file for PchPcieSmm driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchPcieSmm + FILE_GUID =3D acaeaa7a-c039-4424-88da-f42212ea0e55 + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InitializePchPcieSmm + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchPcieSmm.efi + SMM_DEPEX|PchPcieSmm.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC= C10 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xCC18 + + +[Protocols.X64] + ## CONSUMES + gEfiSmmIchnDispatchExProtocolGuid + + gDxePchPlatformPolicyProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf + +[Depex.X64] +# (gEfiSmmBase2ProtocolGuid AND gEfiSmmIchnDispatchExProtocolGuid AND gEf= iPchInfoProtocolGuid AND gDxePchPlatformPolicyProtocolGuid) AND (gEfiPcdPro= tocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGui= d) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetrono= meArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTim= eClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchPro= tocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AN= D gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gE= fiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= 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a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf b/Silico= n/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf new file mode 100644 index 0000000..8f249d7 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchReset.inf @@ -0,0 +1,137 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchReset.inf +# +# Abstract: +# +# Component description file for Reset module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchReset + FILE_GUID =3D F5883FC5-F8EE-4e44-B386-6021FB320C9B + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializePchReset + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchReset.efi + DXE_DEPEX|PchReset.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x6= 820 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x6828 + + +[Protocols.X64] + gEfiResetArchProtocolGuid + + gEfiPchExtendedResetProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiCapsuleVendorGuid + + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf +# Vlv2TbltDevicePkg/Library/ResetSystemLib/ResetSystemLib.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) 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zVx%|W+X(nINPnQqcOqT;xZ=3D49>19u-{B)!r;>$j@p0un<_%c5QX`RkTkv^vLOrOJ- zdS)8Om-cfE>0M7N{V*Na3EqGw6Y1xlQ8I!;(kE?jnl*R{PQ(mPvxd9rOkCrBa>gx4 zhoxJ?(necpr>0q_y7eq4{A);a(ySbovwkMhtTZc&=3D_zT}DNIMEStFT}&RC?x%j?WE zD|3l1=3Dk;0X)>&!iS!t)GTc@RsS8#+U{#!KM-TL|&q^GA@r!yUqZjDGgOY=3DEHr)TJN zf@(h#aHP8g>1k=3D!X-wJPy}m`4-;ETnh8f24Gt;dz(?(foXQW$aq@AkdVmaj-i1)Po|&nS)WLoWSw4nTIr||u7y9~5xJ1cHSkgXnW(4U?oR5Gd-nF6?SbvV?V;`Y+r!)K?UC&z+e^1sZm-?mxV>rnhV7fT kZ{5Ca`;P59x9{2BvAt{iq3wsaAKC6~e{=3DiJ2VElnAKY7aLI3~& literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchS3SupportDxe.inf b= /Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchS3SupportDxe.inf new file mode 100644 index 0000000..bdaeb10 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchS3SupportDxe.inf @@ -0,0 +1,257 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +## @file +# Component description file for Pch Initialization driver +# +# Copyright (c) 1999 - 2011, Intel Corporation. All rights reserved.
+# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +## + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchS3SupportDxe + FILE_GUID =3D 14537da0-222a-4bbe-9a5c-212a3cbca9ef + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PchS3SupportEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchS3SupportDxe.efi + DXE_DEPEX|PchS3SupportDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xD= A00 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0xf0000043|0xDA08 + + +[Protocols.X64] + # PROTOCOL ALWAYS_PRODUCED + gEfiPchS3SupportProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiFirmwareVolume2ProtocolGuid + + ## SOMETIMES_CONSUMES + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFileProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadFile2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleFileSystemProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiFileInfoGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraAction= LibDebug.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/DxeServicesLib/DxeServicesLib.inf +# MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPciExpressH= elpersLib/PchPciExpressHelpersLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) 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z!*zC&akgueEGInMFGtGu4O4@jE{0d}ewPQu4v)3*5#9t_j9D)n^wC^{e_X zB294_DYKl~{9l-V0^V^_+qv|Z`Dyt{n6{JXMt1$LRc@^%&OD%w@Pt9n=3Dcu7+KkcWvDTgl(`p zB!L#QC9kEhWoyf}mX?+sEk{~9TT-^CZO_^s*j~Q9di%ERE!#V`AKrd^yYZ0kA^$^J V524Xvd7nkcf++d-=3Dbxm3{|oWA-U9#t literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSmiDispatcher.inf = b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSmiDispatcher.inf new file mode 100644 index 0000000..75577cb --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSmiDispatcher.inf @@ -0,0 +1,181 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSmiDispatcher.inf +# +# Abstract: +# +# Component description file for the Pch SMI Dispatch Handlers module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchSmiDispatcher + FILE_GUID =3D 6BE18C9C-BF61-499e-88EC-5CD57430460C + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InitializePchSmmDispatcher + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|PchSmiDispatcher.efi + SMM_DEPEX|PchSmiDispatcher.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB= 020 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xB028 + + +[Protocols.X64] + gEfiPciRootBridgeIoProtocolGuid + + ## CONSUMES + gEfiSmmBase2ProtocolGuid + + + + gEfiSmmIchnDispatchExProtocolGuid + + gEfiSmmIchnDispatchProtocolGuid + + gEfiSmmSwDispatch2ProtocolGuid + + gEfiSmmPowerButtonDispatch2ProtocolGuid + + gEfiSmmSxDispatch2ProtocolGuid + + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + +[Depex.X64] +# (gEfiSmmBase2ProtocolGuid AND gEfiPciRootBridgeIoProtocolGuid) AND (gEf= iPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGuid) AND (gEfiSmmAccess2Prot= ocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfi= MetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfi= RealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntime= ArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocol= Guid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid= AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= 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zS6{=3D0|4|(18g01Jl8iK0f5mr#A>>@od@iFe`O{rSIe=3DJ zaRRR?pCS3KSD}491lPpDkhmABkk`b^>r>svsjhLx36;ke4)o!g{G|6tGI~%i#CspE z1wPbQ=3Dnwi4xCj1UZNvYP@D|t~1ejaATYOtGxA?aNw&ZTf-%_}xbW7!y+AVck)@|9e zW%HKiE!(zi-?DQ{%a*n+`?tKcrG1OF<=3D~b>Ta2wKThq3tZ#B1ixB9kbZuM^sY|Y&Y Tf&1kept%|G|M&S{tAYOm77uDB literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiRuntime.inf b/S= ilicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiRuntime.inf new file mode 100644 index 0000000..3beb231 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiRuntime.inf @@ -0,0 +1,258 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiRuntime.inf +# +# Abstract: +# +# Component description file for the SPI Runtime driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchSpiRuntime + FILE_GUID =3D C194C6EA-B68C-4981-B64B-9BD271474B20 + MODULE_TYPE =3D DXE_RUNTIME_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InstallPchSpi + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|PchSpiRuntime.efi + DXE_DEPEX|PchSpiRuntime.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB= A20 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xBA28 + + +[Protocols.X64] + gEfiSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## CONSUMES ## Event + gEfiEventVirtualAddressChangeGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## CONSUMES ## Event + gEfiEventExitBootServicesGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/DxeRuntimePciL= ibPciExpress/DxeRuntimePciLibPciExpress.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf + +[Depex.X64] +# (TRUE) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcd= ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gE= fiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCo= unterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetAr= chProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocol= Guid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AN= D gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK =3D IchSpiVirtualddressChangeEvent +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= 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a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.inf b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.inf new file mode 100644 index 0000000..2f06103 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PchSpiSmm.inf @@ -0,0 +1,251 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PchSpiSmm.inf +# +# Abstract: +# +# Component description file for the SPI SMM driver. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PchSpiSmm + FILE_GUID =3D 27F4917B-A707-4aad-9676-26DF168CBF0D + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InstallPchSpi + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|PchSpiSmm.efi + SMM_DEPEX|PchSpiSmm.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC= 610 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xC618 + + +[Protocols.X64] + gEfiSmmSpiProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiMdeModulePkgTokenSpaceGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdeModulePkg/Library/BasePlatformHookLibNull/BasePlatformHookLibNull.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdeModulePkg/Library/BaseSerialPortLib16550/BaseSerialPortLib16550.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf + +[Depex.X64] +# (gEfiSmmBase2ProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtoc= olGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBas= e2ProtocolGuid) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGu= id AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMo= notonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gE= fiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArc= hProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtoc= olGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGu= id) + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# +# VIRTUAL_ADDRESS_MAP_CALLBACK =3D IchSpiVirtualddressChangeEvent +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG /ALIGN:4096 +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) 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zx4p6L&^CA5k!_!Bv$m&i&)lB1-QFJ99^9U@J+$4~9^PKCy>NT!_R8(G+v~Qk-@bYK Jjvwg$`+pvACb0kj literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PciHostBridge.inf b/S= ilicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PciHostBridge.inf new file mode 100644 index 0000000..2ad6449 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PciHostBridge.inf @@ -0,0 +1,254 @@ +#/*++ +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# PciHostBridge.inf +# +# Abstract: +# +# Component description file for PciHostBridge module +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PciHostBridge + FILE_GUID =3D 9fd2360e-6b48-11d5-8e71-00902707b35e + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciHostBridgeEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|PciHostBridge.efi + DXE_DEPEX|PciHostBridge.depex + +[PatchPcd.X64] + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xB798 + + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xB= 790 + + +[Protocols.X64] + gEfiPciRootBridgeIoProtocolGuid + + gEfiPciHostBridgeResourceAllocationProtocolGuid + + gEfiMetronomeArchProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf + +[Depex.X64] +# (gEfiCpuIo2ProtocolGuid AND gEfiMetronomeArchProtocolGuid) AND (gEfiPc= dProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEf= iPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid = AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchProtocolGuid = AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolGuid AND gEf= iRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gEfiTimerArch= ProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVariableArchProt= ocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- /O1=3D/Od +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= 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b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/PlatformCpuPolicy.inf @@ -0,0 +1,227 @@ +# +# This file contains an 'Intel Peripheral Driver' and is +# licensed for Intel CPUs and chipsets under the terms of your +# license agreement with Intel or your vendor. This file may +# be modified by the user, subject to additional terms of the +# license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2009 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# PlatformCpuPolicy.inf +# +# Abstract: +# +# Platform CPU driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PlatformCpuPolicy + FILE_GUID =3D cb933912-df8f-4305-b1f9-7b44fa11395c + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformCpuPolicyEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|PlatformCpuPolicy.efi + DXE_DEPEX|PlatformCpuPolicy.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x7= D80 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x7D88 + + +[Protocols.X64] + gEfiFirmwareVolume2ProtocolGuid + + gEfiPlatformCpuProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## CONSUMES + gEfiStatusCodeRuntimeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gEfiPlatformCpuInfoGuid + + gEfiSetupVariableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeSpecificDataGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED + gEfiStatusCodeDataTypeDebugGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf + +[Depex.X64] +# (gEfiFirmwareVolumeBlockProtocolGuid AND gEfiVariableArchProtocolGuid A= ND gEfiResetArchProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtoco= lGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArch= ProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid = AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolG= uid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiS= ecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWrite= ArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArch= ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) 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ziSB{!Bi%>42fNMg6Wu4fwH|j*c27=3D^-s9`>_XK)^Jw{JSPgzezPi;?APfJg0kM@wo G<-Y(^-ZfkR literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf b/Silic= on/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf new file mode 100644 index 0000000..ff15e86 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/SmmAccess.inf @@ -0,0 +1,210 @@ +#/*++ +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# SmmAccess.inf +# +# Abstract: +# +# Component description file for the SmmAccess module +# {1323C7F8-DAD5-4126-A54B-7A05FBF4151} +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmAccess + FILE_GUID =3D 326E9CC6-9839-4885-B2ED-275903B668E1 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmAccessDriverEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + +[Binaries.X64] + PE32|SmmAccess.efi + DXE_DEPEX|SmmAccess.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x5= DE0 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0x5DE8 + + +[Protocols.X64] + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.X64] +# (gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPc= dProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEf= iBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProto= colGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchP= rotocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid A= ND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVaria= bleWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogT= imerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D 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zC?$A?NEag|dFVRcrp41W(WUETo0d%1lnzAN%ck|B>+|f|dA5<-S!I3m`lN~Sn~?U4 z(fZjg&}@BUw7#~%oG#TPdXy3$s!wz>kdi!KASJ#JBPF?IdK0cm?hK@iULQdpDb*)D zs)zDUKfBPsP?%Qls(05L_1X2g^?CJ0^=3D0*|>#OQ(>bKNytKVL~qkdO?Lw!?yOZ~z6 zL-nooX8p1H6ZP88_?<~RlXvPnojcQZx^}vE8auOh=3DI*35g4V?Mz_vZzDQ8yje*p3S BkADCF literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/VlvInitDxe.inf b/Sili= con/Intel/Vlv2SocBinPkg/X64DEBUG/X64/VlvInitDxe.inf new file mode 100644 index 0000000..33f7a05 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64DEBUG/X64/VlvInitDxe.inf @@ -0,0 +1,259 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D VlvInitDxe + FILE_GUID =3D 93C81A74-B648-4f7f-925E-E4A0CDCC776D + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D VlvInitEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + +[Binaries.X64] + PE32|VlvInitDxe.efi + DXE_DEPEX|VlvInitDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0xC= 620 + + ## CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x803805c6|0xC628 + + +[Protocols.X64] + gDxeVlvPlatformPolicyGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + + gIgdOpRegionProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gBmpImageGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# DeviceCommonPkg/Library/UsbDebugPortLib/UsbDebugPortLibDxe.inf +# MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.= inf +# Vlv2TbltDevicePkg/Library/SerialPortLib/SerialPortLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.X64] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid= AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMono= tonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfi= ResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchP= rotocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocol= Guid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:DEBUG_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not need= ed for +## MSFT:DEBUG_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Refe= renceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:DEBUG_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:DEBUG_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h /D= MINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_W= A_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $= (MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIO= NS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) = /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPO= RT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECUR= E_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_GENFW_FLAGS =3D --keepexceptiontable +## MSFT:DEBUG_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:DEBUG_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd /Zi +## MSFT:DEBUG_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:DEBUG_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs3276= 8 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /Zi /Gm /DMINNOW= 2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUIL= D_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICRO= CODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(= COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKG= EN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DS= ATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT= _BUILD_OPTIONS) /Od /Oy- +## MSFT:DEBUG_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:DEBUG_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPILE = /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_V= GA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) = $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD= _OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIO= NS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT= _BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /D= FTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /TC = /Dmain=3DReferenceAcpiTable +## MSFT:DEBUG_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:DEBUG_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGNOR= E:4001 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata,D /SECTION:.pd= ata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BO= OT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /DEBUG +## MSFT:DEBUG_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS) +## MSFT:DEBUG_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:DEBUG_VS2015x86_X64_MAKE_FLAGS =3D /nologo +## MSFT:DEBUG_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:DEBUG_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 -g diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/CpuPeim.depex b/Si= licon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/CpuPeim.depex new file mode 100644 index 0000000..2a47cc2 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/CpuPeim.depex @@ -0,0 +1 @@ +=06=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/CpuPeim.efi b/Sili= con/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/CpuPeim.efi new file mode 100644 index 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b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/IA32/VlvInitPeim.inf @@ -0,0 +1,101 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInitPeim.inf +# +# Abstract: +# +# Component description file for the VLV Init PEIM. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D VlvInitPeim + FILE_GUID =3D 24169E35-2454-4940-92BC-82321A2C7562 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D VlvInitPeiEntryPoint + +[Packages.IA32] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.IA32] + PE32|VlvInitPeim.efi + PEI_DEPEX|VlvInitPeim.depex + +[PatchPcd.IA32] + +[Protocols.IA32] + +[Ppis.IA32] + gVlvPolicyPpiGuid + + gVlvPeiInitPpiGuid + + gEfiPeiReadOnlyVariable2PpiGuid + + +[Guids.IA32] + gEfiSetupVariableGuid + + +[PcdEx.IA32] + +[LibraryClasses.IA32] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + +[Depex.IA32] +# gVlvPolicyPpiGuid AND gPchPeiInitPpiGuid + + + +[BuildOptions.IA32] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_IA32_SYMRENAME_FLAGS =3D Symbol renaming not n= eeded for +## MSFT:RELEASE_VS2015x86_IA32_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:R= eferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_IA32_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_IA32_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENU= M_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION= ) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OP= TIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTIO= N) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SU= PPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SE= CURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_IA32_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_IA32_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /cof= f /Zd $(VP_BUILD_OPTIONS) /D EDKII_GLUE_PciExpressBaseAddress=3D0E0000000h = /DNOCS_S3_SUPPORT +## MSFT:RELEASE_VS2015x86_IA32_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_IA32_CC_FLAGS =3D /nologo /arch:IA32 /c /WX /G= S- /W4 /Gs32768 /D UNICODE /O1b2 /GL /FIAutoGen.h /EHs-c- /GR- /GF /DMINNO= W2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUI= LD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICR= 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MSFT:RELEASE_VS2015x86_IA32_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /= TC /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_IA32_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_P= O /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_O= PTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCOD= E_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COM= PACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_= CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA= _SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BU= ILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_IA32_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IG= NORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdat= a,D /SECTION:.pdata,D /MACHINE:X86 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /= SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data +## 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terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D GraphicDxeInitSmm + FILE_GUID =3D 99EC6206-AA45-4CAE-B630-866755241C8A + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D GraphicDxeInitSmmEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|GraphicDxeInitSmm.efi + SMM_DEPEX|GraphicDxeInitSmm.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x2= 000 + + +[Protocols.X64] + gDxeVlvPlatformPolicyGuid + + gEdkiiSmmReadyToBootProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## CONSUMES + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + ## NOTIFY + ## CONSUMES + ## CONSUMES + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + ## CONSUMES + ## CONSUMES + gEfiSmmEndOfDxeProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## SOMETIMES_CONSUMES ## UNDEFINED # SmmSystemTable + ## SOMETIMES_PRODUCES ## UNDEFINED # SmmSystemTable + gEfiSmmLockBoxCommunicationGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf +# MdePkg/Library/SmmMemLib/SmmMemLib.inf +# MdePkg/Library/SmmIoLib/SmmIoLib.inf + +[Depex.X64] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiSmmBase2ProtocolGui= d) AND (gEfiSmmAccess2ProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCp= uArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounte= rArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchPr= otocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid= AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gE= fiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) AND (gEfi= SmmAccess2ProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not ne= eded for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Re= ferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) 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This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 2012 - 2013 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# SataController.inf +# +# Abstract: +# +# Component description file for PCH SATA controller Driver module. +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SataController + FILE_GUID =3D BB65942B-521F-4ec3-BAF9-A92540CF60D2 + MODULE_TYPE =3D UEFI_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D InitializeSataControllerDriver + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + +[Binaries.X64] + PE32|SataController.efi + +[PatchPcd.X64] + +[Protocols.X64] + gEfiIdeControllerInitProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + gEfiPciIoProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gSataControllerDriverGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdePkg/Library/UefiLib/UefiLib.inf + +[Depex.X64] +# (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGui= d) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid AND gEfiCpuArchPr= otocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMonotonicCounterArchPr= otocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfiResetArchProtocolG= uid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchProtocolGuid AND gE= fiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocolGuid AND gEfiVaria= bleArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not ne= eded for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Re= ferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32= 768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPIL= E /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL= _VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION= ) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUI= LD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPT= IONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVE= RT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 = /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /T= C /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO= /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OP= TION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE= _FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMP= ACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_C= ONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_= SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUI= LD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGN= ORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata= ,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /S= UBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h= /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_EN= UM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTIO= N) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_O= PTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTI= ON) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_S= UPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_S= ECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:RELEASE_VS2015x86_X64_MAKE_FLAGS =3D /nologo +## MSFT:RELEASE_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:RELEASE_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.depex b/S= ilicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.depex new file mode 100644 index 0000000000000000000000000000000000000000..b1a5ceab3b2eb73466f120b95a1= 915810dd0401f GIT binary patch literal 36 scmZSDU00wl<#k1HmIcEEb^C+9Oy52%7WPv6VE5_4y`w@V`Xp9~2N1?0i9=3DXO{%NW85cPV6|?s9BGWalBf zQcn2(&a0^m+`K+Mh^8*krDYrenw@B_kg5BBwN-Ei)%>5h1oPN91MQP7`6xFM_e-HFO}n3`Sc38(d0RW=3Di+egK(p2K*Wc7J?a4Ho;$#J zLKZHrnEhXZA&t`eb*Y&u=3Du$0JH6$;2hO~sSUcGT+DfS0-Xat|Jl@!4JXpT)H=3DZX#Z zKP}4lWjNhqL%8mV6wB*cXc8=3Dwc=3DiP-l|CtR3zbOK%4yqvOc|86X#eGk(`7w4mWn3A73YhY=3DaRB34_PlYixbP+`v|%k3fM~tVox+B zOvwEpfw%_oJJajnW64P_Zi-oW?CmgeNezH9uGZipftZ*-dfl=3D>zZ=3DB)(zt~h+V0F8 zgnt3)F%w26Gab0edGy2t{*>RK!9~--mJw5Zn2TL~Tm*L`mJ$Un8rvzVG-Rr|ve&29 zf<4L&DaA}T6n_H4lSm1k!@ct#!$c4{DqAUqh4&6kO$SnE55MsKjbUpCzZQS?>toaP zuRp{_@7tMcQNw-X>xQ=3D`UwZWD2ifC4o~q>DZ2J+QeICTA(erPTOSM|ZXDJNGz-{*&?-hgYnM literal 0 HcmV?d00001 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.inf b/Sil= icon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.inf new file mode 100644 index 0000000..234cd77 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmAccess.inf @@ -0,0 +1,198 @@ +#/*++ +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +#--*/ +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# +# Module Name: +# +# SmmAccess.inf +# +# Abstract: +# +# Component description file for the SmmAccess module +# {1323C7F8-DAD5-4126-A54B-7A05FBF4151} +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D SmmAccess + FILE_GUID =3D 326E9CC6-9839-4885-B2ED-275903B668E1 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmAccessDriverEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + +[Binaries.X64] + PE32|SmmAccess.efi + DXE_DEPEX|SmmAccess.depex + +[PatchPcd.X64] + +[Protocols.X64] + gEfiSmmAccess2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + ## CONSUMES ## SystemTable + gEfiHobListGuid + + +[PcdEx.X64] + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/DxeHobLib/DxeHobLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf + +[Depex.X64] +# (gEfiPciRootBridgeIoProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPc= dProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEf= iBdsArchProtocolGuid AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProto= colGuid AND gEfiMonotonicCounterArchProtocolGuid AND gEfiRealTimeClockArchP= rotocolGuid AND gEfiResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid A= ND gEfiSecurityArchProtocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVaria= bleWriteArchProtocolGuid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogT= imerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not ne= eded for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Re= ferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32= 768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPIL= E /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL= _VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION= ) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUI= LD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPT= IONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVE= RT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 = /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /T= C /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO= /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OP= TION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE= _FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMP= ACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_C= ONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_= SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUI= LD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGN= ORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata= ,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /S= UBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h= /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_EN= UM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTIO= N) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_O= PTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTI= ON) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_S= UPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_S= ECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:RELEASE_VS2015x86_X64_MAKE_FLAGS =3D /nologo +## MSFT:RELEASE_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:RELEASE_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmControl.depex b/= Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmControl.depex new file mode 100644 index 0000000..0dc7ce4 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmControl.depex @@ -0,0 +1 @@ +=02=EF=BF=BD=EF=BF=BD=13J&=EF=BF=BD>=EF=BF=BD=EF=BF=BD=EF=BF=BD=EF=BF=BD= =124/4=08 \ No newline at end of file diff --git a/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmControl.efi b/Si= licon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/SmmControl.efi new file mode 100644 index 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licon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/VlvInitDxe.inf new file mode 100644 index 0000000..0dcf3b3 --- /dev/null +++ b/Silicon/Intel/Vlv2SocBinPkg/X64RELEASE/X64/VlvInitDxe.inf @@ -0,0 +1,253 @@ +# +# This file contains a 'Sample Driver' and is licensed as such +# under the terms of your license agreement with Intel or your +# vendor. This file may be modified by the user, subject to +# the additional terms of the license agreement +# +#/*++ +# +# Copyright (c) 1999 - 2010 Intel Corporation. All rights reserved +# This software and associated documentation (if any) is furnished +# under a license and may only be used or copied in accordance +# with the terms of the license. Except as permitted by such +# license, no part of this software or documentation may be +# reproduced, stored in a retrieval system, or transmitted in any +# form or by any means without the express written consent of +# Intel Corporation. +# +# Module Name: +# +# VlvInit.inf +# +# Abstract: +# +# Component description file for SystemAgent Initialization driver +# +#--*/ + +# DO NOT EDIT +# FILE auto-generated + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D VlvInitDxe + FILE_GUID =3D 93C81A74-B648-4f7f-925E-E4A0CDCC776D + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D VlvInitEntryPoint + +[Packages.X64] + MdePkg/MdePkg.dec + Vlv2DeviceRefCodePkg/Vlv2DeviceRefCodePkg.dec + MdeModulePkg/MdeModulePkg.dec + Vlv2TbltDevicePkg/PlatformPkg.dec + +[Binaries.X64] + PE32|VlvInitDxe.efi + DXE_DEPEX|VlvInitDxe.depex + +[PatchPcd.X64] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x00000000e0000000|0x3= 910 + + +[Protocols.X64] + gDxeVlvPlatformPolicyGuid + + ## NOTIFY + gEfiDxeSmmReadyToLockProtocolGuid + + + gIgdOpRegionProtocolGuid + + gEfiGlobalNvsAreaProtocolGuid + + gEfiPciIoProtocolGuid + + gEfiFirmwareVolume2ProtocolGuid + + gEfiCpuIo2ProtocolGuid + + ## SOMETIMES_CONSUMES + gPcdProtocolGuid + + ## CONSUMES + gEfiPcdProtocolGuid + + ## SOMETIMES_CONSUMES + gGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGetPcdInfoProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiDevicePathProtocolGuid + + ## UNDEFINED + gEfiDebugPortProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmCommunicationProtocolGuid + + ## SOMETIMES_PRODUCES + gEfiDriverBindingProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSimpleTextOutProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiGraphicsOutputProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiHiiFontProtocolGuid + + ## SOMETIMES_CONSUMES # Consumes if gEfiGraphicsOutputProtocolGuid unins= talled + gEfiUgaDrawProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentNameProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiComponentName2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfigurationProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverConfiguration2ProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnosticsProtocolGuid + + ## SOMETIMES_PRODUCES # User chooses to produce it + gEfiDriverDiagnostics2ProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiLoadedImageProtocolGuid + + ## SOMETIMES_CONSUMES + gEfiSmmBase2ProtocolGuid + + ## NOTIFY + gEfiSmmReadyToLockProtocolGuid + + ## NOTIFY + gEdkiiSmmExitBootServicesProtocolGuid + + ## NOTIFY + gEdkiiSmmLegacyBootProtocolGuid + + +[Ppis.X64] + +[Guids.X64] + gBmpImageGuid + + ## CONSUMES ## SystemTable + gEfiDxeServicesTableGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVTUTF8Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100Guid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVT100PlusGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPcAnsiGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiUartDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiSasDevicePathGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualDiskGuid + + ## SOMETIMES_CONSUMES ## GUID + gEfiPersistentVirtualCdGuid + + ## SOMETIMES_CONSUMES ## GUID # Used to do smm communication + gEfiSmmLockBoxCommunicationGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventReadyToBootGuid + + ## SOMETIMES_CONSUMES ## Event + gEfiEventLegacyBootGuid + + ## SOMETIMES_CONSUMES ## Variable + gEfiGlobalVariableGuid + + gEfiMdeModulePkgTokenSpaceGuid + + +[PcdEx.X64] + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr + + ## CONSUMES + ## SOMETIMES_PRODUCES + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr + + +[LibraryClasses.X64] +## @LIB_INSTANCES +# MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf +# MdePkg/Library/DxePcdLib/DxePcdLib.inf +# MdePkg/Library/BaseLib/BaseLib.inf +# MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf +# MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf +# MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +# MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf +# MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf +# MdePkg/Library/BasePrintLib/BasePrintLib.inf +# MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf +# MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.= inf +# MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf +# MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf +# MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf +# Vlv2TbltDevicePkg/Library/SmbusLib/SmbusLib.inf +# Vlv2TbltDevicePkg/Library/IntelPchAcpiTimerLib/IntelPchAcpiTimerLib.inf +# MdePkg/Library/UefiLib/UefiLib.inf +# MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf +# MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf +# MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf +# Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Library/PchPlatformLib= /PchPlatformLib.inf + +[Depex.X64] +# (gDxeVlvPlatformPolicyGuid AND gEfiPciRootBridgeIoProtocol= Guid AND gEfiCpuIo2ProtocolGuid AND gEfiGlobalNvsA= reaProtocolGuid AND gEfiFirmwareVolume2ProtocolGuid AND gEfiHiiData= baseProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (= gEfiPcdProtocolGuid) AND (gEfiPcdProtocolGuid) AND (gEfiBdsArchProtocolGuid= AND gEfiCpuArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND gEfiMono= tonicCounterArchProtocolGuid AND gEfiRealTimeClockArchProtocolGuid AND gEfi= ResetArchProtocolGuid AND gEfiRuntimeArchProtocolGuid AND gEfiSecurityArchP= rotocolGuid AND gEfiTimerArchProtocolGuid AND gEfiVariableWriteArchProtocol= Guid AND gEfiVariableArchProtocolGuid AND gEfiWatchdogTimerArchProtocolGuid) + + + +[BuildOptions.X64] +## @AsBuilt +## MSFT:RELEASE_VS2015x86_X64_SYMRENAME_FLAGS =3D Symbol renaming not ne= eded for +## MSFT:RELEASE_VS2015x86_X64_ASLDLINK_FLAGS =3D /NODEFAULTLIB /ENTRY:Re= ferenceAcpiTable /SUBSYSTEM:CONSOLE +## MSFT:RELEASE_VS2015x86_X64_VFR_FLAGS =3D -l -n +## MSFT:RELEASE_VS2015x86_X64_PP_FLAGS =3D /nologo /E /TC /FIAutoGen.h = /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM= _WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION)= $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPT= IONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION= ) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUP= PORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SEC= URE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_GENFW_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_X64_SLINK_FLAGS =3D /NOLOGO /LTCG +## MSFT:RELEASE_VS2015x86_X64_ASM_FLAGS =3D /nologo /c /WX /W3 /Cx /Zd +## MSFT:RELEASE_VS2015x86_X64_ASL_FLAGS =3D=20 +## MSFT:RELEASE_VS2015x86_X64_CC_FLAGS =3D /nologo /c /WX /GS- /W4 /Gs32= 768 /D UNICODE /O1b2s /GL /Gy /FIAutoGen.h /EHs-c- /GR- /GF /DMINNOW2_PO /= DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTI= ON) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_F= REE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPAC= T_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CON= FIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SU= PPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD= _OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_NASMB_FLAGS =3D -f bin +## MSFT:RELEASE_VS2015x86_X64_VFRPP_FLAGS =3D /nologo /E /TC /DVFRCOMPIL= E /FI$(MODULE_NAME)StrDefs.h /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL= _VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION= ) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUI= LD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPT= IONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVE= RT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 = /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_ASLCC_FLAGS =3D /nologo /c /FIAutoGen.h /T= C /Dmain=3DReferenceAcpiTable +## MSFT:RELEASE_VS2015x86_X64_APP_FLAGS =3D /nologo /E /TC /DMINNOW2_PO= /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_ENUM_WA_BUILD_OP= TION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTION) $(MICROCODE= _FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_OPTIONS) $(COMP= ACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTION) /DCLKGEN_C= ONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_SUPPORT /DSATA_= SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_SECURE_BOOT_BUI= LD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OPTROM_FLAGS =3D -e +## MSFT:RELEASE_VS2015x86_X64_DLINK_FLAGS =3D /NOLOGO /NODEFAULTLIB /IGN= ORE:4001 /IGNORE:4254 /OPT:REF /OPT:ICF=3D10 /MAP /ALIGN:32 /SECTION:.xdata= ,D /SECTION:.pdata,D /Machine:X64 /LTCG /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /S= UBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /MERGE:.rdata= =3D.data +## MSFT:RELEASE_VS2015x86_X64_ASLPP_FLAGS =3D /nologo /E /C /FIAutoGen.h= /DMINNOW2_PO /DENBDT_PF_ENABLE=3D1 $(EXTERNAL_VGA_BUILD_OPTION) $(PCIE_EN= UM_WA_BUILD_OPTION) $(X0_WA_ENABLE_BUILD_OPTION) $(A0_WA_ENABLE_BUILD_OPTIO= N) $(MICROCODE_FREE_BUILD_OPTIONS) $(SIMICS_BUILD_OPTIONS) $(HYBRID_BUILD_O= PTIONS) $(COMPACT_BUILD_OPTIONS) $(VP_BUILD_OPTIONS) $(SYSCTL_ID_BUILD_OPTI= ON) /DCLKGEN_CONFIG_EXTRA=3D1 $(SYSCTL_X0_CONVERT_BOARD_OPTION) /DNOCS_S3_S= UPPORT /DSATA_SUPPORT=3D1 /DPCIESC_SUPPORT=3D1 /DFTPM_ENABLE $(DSC_BYTI_S= ECURE_BOOT_BUILD_OPTIONS) +## MSFT:RELEASE_VS2015x86_X64_OBJCOPY_FLAGS =3D objcopy not needed for +## MSFT:RELEASE_VS2015x86_X64_MAKE_FLAGS =3D /nologo +## MSFT:RELEASE_VS2015x86_X64_ASMLINK_FLAGS =3D /nologo /tiny +## MSFT:RELEASE_VS2015x86_X64_NASM_FLAGS =3D -Ox -f win64 --=20 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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