From nobody Tue Apr 30 04:44:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+42896+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42896+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1561554638; cv=none; d=zoho.com; s=zohoarc; b=dg2CKAr9WqJGFX67mn55J2oRrbGsp5cvnB7MedXVJph1E03uJV/KvEC36NJtCO17FxPYMoVN5KneztUaImZNQg0ZAfh9ic37edTfwqd6VX5Bni57DBKDZvbjIEBLHDvBTxpCL57WjprAetyLuia/J5fMglL6DlFI8avtCoNpGi0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561554638; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=94ZMnru54KDtW0Qsx5T1aWLaiZqa2ksglPRKxMuAD3I=; b=I949LyPhEBLAvlMGd1UzjloR3S4L7NrCSwBTFMJ+yl82IgpLXzcqkkOE50vReaCayMS1qKQIkBaylxo9Jh6MUXnWwKpOdrT1BpELSh9kiV+QrieK8mUrZjL51R4wbx4f0kIZoDpm2EkY/SsDSg7W4b9iPJ4aLOd6bhF4mJOtnHI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42896+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1561554638638346.7796334300573; Wed, 26 Jun 2019 06:10:38 -0700 (PDT) Return-Path: X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by groups.io with SMTP; Wed, 26 Jun 2019 06:10:36 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2019 06:10:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,420,1557212400"; d="scan'208";a="155862718" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.10.44]) by orsmga008.jf.intel.com with ESMTP; 26 Jun 2019 06:10:34 -0700 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: Mateusz Albecki , Hao A Wu Subject: [edk2-devel] [PATCH v4 1/2] MdeModulePkg/SdMmcOverride: Add GetOperatingParam notify phase Date: Wed, 26 Jun 2019 15:10:02 +0200 Message-Id: <20190626131003.3088-2-mateusz.albecki@intel.com> In-Reply-To: <20190626131003.3088-1-mateusz.albecki@intel.com> References: <20190626131003.3088-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1561554637; bh=JC/WOv0rHrx2pKJ79+rw3qt70m20E0CKYHO7u+ZT0K0=; h=Cc:Date:From:Reply-To:Subject:To; b=jr5QPkw51XpVf+97UWV3aReVi8b9md5olaBj0Wp9IiuVBsSP0DhHfkk66SmcbxlevOM s6vu/4qFfag6ICxYDkMDbjZ4ehgcVkC3bwJuPgiY2RXxMyJ/ted2sRk9n7yZtOL2/Ivfh h19Va7Z28TnztYkmE+J5TIymP1ZJ1Qp+49g= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D1882 The new notify phase allows platform to configure additional bus paramters in addition to parameters that can already be configured with capability override. Specifically we allow to configure bus width, clock frequency and driver strength. If platform doesn't wish to configure some of the parameters it can left it on default values and driver will assume it's standard behavior with respect to those parameters. The definition of the SD_MMC_BUS_MODE has been extended to incorporate SD card default speed and high speed. Cc: Hao A Wu Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu --- MdeModulePkg/Include/Protocol/SdMmcOverride.h | 60 +++++++++++++++++++++++= ---- 1 file changed, 53 insertions(+), 7 deletions(-) diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModulePkg/I= nclude/Protocol/SdMmcOverride.h index 9c8bf37efd..d44027260a 100644 --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h @@ -16,19 +16,66 @@ #define EDKII_SD_MMC_OVERRIDE_PROTOCOL_GUID \ { 0xeaf9e3c1, 0xc9cd, 0x46db, { 0xa5, 0xe5, 0x5a, 0x12, 0x4c, 0x83, 0x23= , 0x23 } } =20 -#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x2 +#define EDKII_SD_MMC_OVERRIDE_PROTOCOL_VERSION 0x3 =20 typedef struct _EDKII_SD_MMC_OVERRIDE EDKII_SD_MMC_OVERRIDE; =20 -// -// Bus timing modes -// +#define EDKII_SD_MMC_BUS_WIDTH_IGNORE MAX_UINT8 +#define EDKII_SD_MMC_CLOCK_FREQ_IGNORE MAX_UINT32 +#define EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE MAX_UINT8 + +typedef enum { + SdDriverStrengthTypeB =3D 0, + SdDriverStrengthTypeA, + SdDriverStrengthTypeC, + SdDriverStrengthTypeD, + SdDriverStrengthIgnore =3D EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE +} SD_DRIVER_STRENGTH_TYPE; + typedef enum { + EmmcDriverStrengthType0 =3D 0, + EmmcDriverStrengthType1, + EmmcDriverStrengthType2, + EmmcDriverStrengthType3, + EmmcDriverStrengthType4, + EmmcDriverStrengthIgnore =3D EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE +} EMMC_DRIVER_STRENGTH_TYPE; + +typedef union { + SD_DRIVER_STRENGTH_TYPE Sd; + EMMC_DRIVER_STRENGTH_TYPE Emmc; +} EDKII_SD_MMC_DRIVER_STRENGTH; + +typedef struct { + // + // The target width of the bus. If user tells driver to ignore it + // or specifies unsupported width driver will choose highest supported + // bus width for a given mode. + // + UINT8 BusWidth; + // + // The target clock frequency of the bus in MHz. If user tells driver to= ignore + // it or specifies unsupported frequency driver will choose highest supp= orted + // clock frequency for a given mode. + // + UINT32 ClockFreq; + // + // The target driver strength of the bus. If user tells driver to + // ignore it or specifies unsupported driver strength, driver will + // default to Type0 for eMMC cards and TypeB for SD cards. Driver streng= th + // setting is only considered if chosen bus timing supports them. + // + EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength; +} EDKII_SD_MMC_OPERATING_PARAMETERS; + +typedef enum { + SdMmcSdDs, + SdMmcSdHs, SdMmcUhsSdr12, SdMmcUhsSdr25, SdMmcUhsSdr50, - SdMmcUhsSdr104, SdMmcUhsDdr50, + SdMmcUhsSdr104, SdMmcMmcLegacy, SdMmcMmcHsSdr, SdMmcMmcHsDdr, @@ -43,10 +90,10 @@ typedef enum { EdkiiSdMmcInitHostPost, EdkiiSdMmcUhsSignaling, EdkiiSdMmcSwitchClockFreqPost, + EdkiiSdMmcGetOperatingParam } EDKII_SD_MMC_PHASE_TYPE; =20 /** - Override function for SDHCI capability bits =20 @param[in] ControllerHandle The EFI_HANDLE of the controller. @@ -70,7 +117,6 @@ EFI_STATUS ); =20 /** - Override function for SDHCI controller operations =20 @param[in] ControllerHandle The EFI_HANDLE of the controller. --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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View/Reply Online (#42896): https://edk2.groups.io/g/devel/message/42896 Mute This Topic: https://groups.io/mt/32214575/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue Apr 30 04:44:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+42897+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42897+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1561554641; cv=none; d=zoho.com; s=zohoarc; b=oSSRxLI+ouu0IX8VBGcxTiT65Ak4J5tKFDp2Ey9ODqgwJi/GByPzxOG2rprxLhCxmBgZtu0XNTyveZE9Fk2TFBQ2rYPnXIjzl0pX7MUNn1w2oHifzClSpt+nsHiOLNtYx9MjtMQGtY7S7agidwxzyZl9RVS4CAyXagytLM0pWYg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1561554641; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=zk9JXNK5EC2KEMtg5q2TwWUOEkFsfpUabjH8MYvyvwU=; b=S0UisSDcTV+gNRPdIjUy40Jr+bSDELT4HQivOMhxLlXHyBUbQGfYRuwt3y0UNYR+x0EYr10NCJg0jUYwrGnnGl9z4nGz7Je/RIBEHzKf4AsaLhAyf/NGaL42gTG/29WqQM6hhr3UB2ahAOwLOogdqX2F4oFtpJfOUBEOroQDSuo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42897+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 15615546416671006.0475276990379; Wed, 26 Jun 2019 06:10:41 -0700 (PDT) Return-Path: X-Received: from mga11.intel.com (mga11.intel.com []) by groups.io with SMTP; Wed, 26 Jun 2019 06:10:40 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 26 Jun 2019 06:10:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.63,420,1557212400"; d="scan'208";a="155862745" X-Received: from gklab-27-32.ger.corp.intel.com ([10.102.10.44]) by orsmga008.jf.intel.com with ESMTP; 26 Jun 2019 06:10:37 -0700 From: "Albecki, Mateusz" To: devel@edk2.groups.io Cc: "Albecki, Mateusz" , Hao A Wu Subject: [edk2-devel] [PATCH v4 2/2] MdeModulePkg/SdMmcHcDxe: Implement revision 3 of SdMmcOverrideProtocol Date: Wed, 26 Jun 2019 15:10:03 +0200 Message-Id: <20190626131003.3088-3-mateusz.albecki@intel.com> In-Reply-To: <20190626131003.3088-1-mateusz.albecki@intel.com> References: <20190626131003.3088-1-mateusz.albecki@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mateusz.albecki@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1561554641; bh=DXi0gT4OJvP8LpV4X9vbbINepTMGFM71IXE3++YvzvY=; h=Cc:Date:From:Reply-To:Subject:To; b=KHg6vzYg4+gMKrnZ97coXi7BDHILXcrT5L6M6qs80V9HtkU/JEhgwJV8YFaMvjEGf5A UBh/TxZFl8bnBqB36K9CvMb3HJ1fmV8sHz8CjWGQnAkKyYoly0TfbYuBpE3dQOYkjBPI+ ANkKJJIOi0F4FBHXvrPJz/xxFzvA9M1YdGM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Albecki, Mateusz" https://bugzilla.tianocore.org/show_bug.cgi?id=3D1882 Implement support for GetOperatingParamters notify phase in SdMmcHcDxe driver. GetOperatingParameters notify phase is signaled before we start card detection and initialization. Code has been updated for both eMMC and SD card controllers to take into consideration those new parameters. Initialization process has been divided into 2 steps. In the first step we bring the link up to the point where we can get card identification data(Extended CSD in eMMC case and SWITCH command response in SD card case). This data is later used along with controller capabilities and operating parameters passed in GetOperatingParameters phase to choose prefered bus settings in GetTargetBusSettings function. Those settings are later on to start bus training to high speeds. If user passes incompatible setting with selected bus timing driver will assume it's standard behavior with respect to that setting. For instance if HS400 has been selected as a target bus timing due to card and controller support bus width setting of 4 and 1 bit won't be respected and 8 bit setting will be choosen instead. Cc: Hao A Wu Signed-off-by: Mateusz Albecki Reviewed-by: Hao A Wu --- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 512 +++++++++++++++--= ---- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 410 ++++++++++++++--- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 52 ++- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 18 +- MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 34 ++ MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 19 + 6 files changed, 814 insertions(+), 231 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModulePkg= /Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c index deaf4468c9..3f4a8e5413 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c @@ -641,13 +641,13 @@ EmmcSwitchBusWidth ( Refer to EMMC Electrical Standard Spec 5.1 Section 6.6 and SD Host Contr= oller Simplified Spec 3.0 Figure 3-3 for details. =20 - @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL= instance. - @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Rca The relative device address to be assigned. - @param[in] HsTiming The value to be written to HS_TIMING field of = EXT_CSD register. - @param[in] Timing The bus mode timing indicator. - @param[in] ClockFreq The max clock frequency to be set, the unit is= MHz. + @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCO= L instance. + @param[in] Slot The slot number of the SD card to send the co= mmand to. + @param[in] Rca The relative device address to be assigned. + @param[in] DriverStrength Driver strength to set for speed modes that s= upport it. + @param[in] BusTiming The bus mode timing indicator. + @param[in] ClockFreq The max clock frequency to be set, the unit i= s MHz. =20 @retval EFI_SUCCESS The operation is done correctly. @retval Others The operation fails. @@ -659,8 +659,8 @@ EmmcSwitchBusTiming ( IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, IN UINT8 Slot, IN UINT16 Rca, - IN UINT8 HsTiming, - IN SD_MMC_BUS_MODE Timing, + IN EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength, + IN SD_MMC_BUS_MODE BusTiming, IN UINT32 ClockFreq ) { @@ -678,12 +678,29 @@ EmmcSwitchBusTiming ( // Access =3D 0x03; Index =3D OFFSET_OF (EMMC_EXT_CSD, HsTiming); - Value =3D HsTiming; CmdSet =3D 0; + switch (BusTiming) { + case SdMmcMmcHs400: + Value =3D (UINT8)((DriverStrength.Emmc << 4) | 3); + break; + case SdMmcMmcHs200: + Value =3D (UINT8)((DriverStrength.Emmc << 4) | 2); + break; + case SdMmcMmcHsSdr: + case SdMmcMmcHsDdr: + Value =3D 1; + break; + case SdMmcMmcLegacy: + Value =3D 0; + break; + default: + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Unsupported BusTiming(%d\= n)", BusTiming)); + return EFI_INVALID_PARAMETER; + } =20 Status =3D EmmcSwitch (PassThru, Slot, Access, Index, Value, CmdSet); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Switch to hstiming %d fails= with %r\n", HsTiming, Status)); + DEBUG ((DEBUG_ERROR, "EmmcSwitchBusTiming: Switch to bus timing %d fai= ls with %r\n", BusTiming, Status)); return Status; } =20 @@ -713,7 +730,7 @@ EmmcSwitchBusTiming ( Private->ControllerHandle, Slot, EdkiiSdMmcSwitchClockFreqPost, - &Timing + &BusTiming ); if (EFI_ERROR (Status)) { DEBUG (( @@ -739,10 +756,7 @@ EmmcSwitchBusTiming ( @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL= instance. @param[in] Slot The slot number of the SD card to send the com= mand to. @param[in] Rca The relative device address to be assigned. - @param[in] ClockFreq The max clock frequency to be set. - @param[in] IsDdr If TRUE, use dual data rate data simpling meth= od. Otherwise - use single data rate data simpling method. - @param[in] BusWidth The bus width to be set, it could be 4 or 8. + @param[in] BusMode Pointer to SD_MMC_BUS_SETTINGS structure conta= ining bus settings. =20 @retval EFI_SUCCESS The operation is done correctly. @retval Others The operation fails. @@ -754,25 +768,34 @@ EmmcSwitchToHighSpeed ( IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, IN UINT8 Slot, IN UINT16 Rca, - IN UINT32 ClockFreq, - IN BOOLEAN IsDdr, - IN UINT8 BusWidth + IN SD_MMC_BUS_SETTINGS *BusMode ) { EFI_STATUS Status; - UINT8 HsTiming; UINT8 HostCtrl1; - SD_MMC_BUS_MODE Timing; SD_MMC_HC_PRIVATE_DATA *Private; + BOOLEAN IsDdr; =20 Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); =20 - Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusWid= th); + if ((BusMode->BusTiming !=3D SdMmcMmcHsSdr && BusMode->BusTiming !=3D Sd= MmcMmcHsDdr) || + BusMode->ClockFreq > 52) { + return EFI_INVALID_PARAMETER; + } + + if (BusMode->BusTiming =3D=3D SdMmcMmcHsDdr) { + IsDdr =3D TRUE; + } else { + IsDdr =3D FALSE; + } + + Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, BusMod= e->BusWidth); if (EFI_ERROR (Status)) { return Status; } + // - // Set to Hight Speed timing + // Set to High Speed timing // HostCtrl1 =3D BIT2; Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (Hos= tCtrl1), &HostCtrl1); @@ -780,37 +803,25 @@ EmmcSwitchToHighSpeed ( return Status; } =20 - if (IsDdr) { - Timing =3D SdMmcMmcHsDdr; - } else if (ClockFreq =3D=3D 52) { - Timing =3D SdMmcMmcHsSdr; - } else { - Timing =3D SdMmcMmcLegacy; - } - - Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = Timing); + Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = BusMode->BusTiming); if (EFI_ERROR (Status)) { return Status; } =20 - HsTiming =3D 1; - Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, Ti= ming, ClockFreq); - - return Status; + return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverS= trength, BusMode->BusTiming, BusMode->ClockFreq); } =20 /** - Switch to the HS200 timing according to request. + Switch to the HS200 timing. This function assumes that eMMC bus is still= in legacy mode. =20 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Con= troller Simplified Spec 3.0 Figure 2-29 for details. =20 - @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL= instance. - @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Rca The relative device address to be assigned. - @param[in] ClockFreq The max clock frequency to be set. - @param[in] BusWidth The bus width to be set, it could be 4 or 8. + @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCO= L instance. + @param[in] Slot The slot number of the SD card to send the co= mmand to. + @param[in] Rca The relative device address to be assigned. + @param[in] BusMode Pointer to SD_MMC_BUS_SETTINGS structure cont= aining bus settings. =20 @retval EFI_SUCCESS The operation is done correctly. @retval Others The operation fails. @@ -822,30 +833,25 @@ EmmcSwitchToHS200 ( IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, IN UINT8 Slot, IN UINT16 Rca, - IN UINT32 ClockFreq, - IN UINT8 BusWidth + IN SD_MMC_BUS_SETTINGS *BusMode ) { EFI_STATUS Status; - UINT8 HsTiming; UINT16 ClockCtrl; - SD_MMC_BUS_MODE Timing; SD_MMC_HC_PRIVATE_DATA *Private; =20 Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); =20 - if ((BusWidth !=3D 4) && (BusWidth !=3D 8)) { + if (BusMode->BusTiming !=3D SdMmcMmcHs200 || + (BusMode->BusWidth !=3D 4 && BusMode->BusWidth !=3D 8)) { return EFI_INVALID_PARAMETER; } =20 - Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, FALSE, BusWid= th); + Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, FALSE, BusMod= e->BusWidth); if (EFI_ERROR (Status)) { return Status; } // - // Set to HS200/SDR104 timing - // - // // Stop bus clock at first // Status =3D SdMmcHcStopClock (PciIo, Slot); @@ -853,9 +859,7 @@ EmmcSwitchToHS200 ( return Status; } =20 - Timing =3D SdMmcMmcHs200; - - Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = Timing); + Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = BusMode->BusTiming); if (EFI_ERROR (Status)) { return Status; } @@ -881,28 +885,27 @@ EmmcSwitchToHS200 ( ClockCtrl =3D BIT2; Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_CLOCK_CTRL, sizeof (Clo= ckCtrl), &ClockCtrl); =20 - HsTiming =3D 2; - Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, Ti= ming, ClockFreq); + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->Dri= verStrength, BusMode->BusTiming, BusMode->ClockFreq); if (EFI_ERROR (Status)) { return Status; } =20 - Status =3D EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusWidth); + Status =3D EmmcTuningClkForHs200 (PciIo, PassThru, Slot, BusMode->BusWid= th); =20 return Status; } =20 /** - Switch to the HS400 timing according to request. + Switch to the HS400 timing. This function assumes that eMMC bus is still= in legacy mode. =20 Refer to EMMC Electrical Standard Spec 5.1 Section 6.6.8 and SD Host Con= troller Simplified Spec 3.0 Figure 2-29 for details. =20 - @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. - @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL= instance. - @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] Rca The relative device address to be assigned. - @param[in] ClockFreq The max clock frequency to be set. + @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCO= L instance. + @param[in] Slot The slot number of the SD card to send the co= mmand to. + @param[in] Rca The relative device address to be assigned. + @param[in] BusMode Pointer to SD_MMC_BUS_SETTINGS structure cont= aining bus settings. =20 @retval EFI_SUCCESS The operation is done correctly. @retval Others The operation fails. @@ -914,47 +917,314 @@ EmmcSwitchToHS400 ( IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, IN UINT8 Slot, IN UINT16 Rca, - IN UINT32 ClockFreq + IN SD_MMC_BUS_SETTINGS *BusMode ) { EFI_STATUS Status; - UINT8 HsTiming; - SD_MMC_BUS_MODE Timing; SD_MMC_HC_PRIVATE_DATA *Private; + SD_MMC_BUS_SETTINGS Hs200BusMode; + UINT32 HsFreq; + + if (BusMode->BusTiming !=3D SdMmcMmcHs400 || + BusMode->BusWidth !=3D 8) { + return EFI_INVALID_PARAMETER; + } =20 Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); + Hs200BusMode.BusTiming =3D SdMmcMmcHs200; + Hs200BusMode.BusWidth =3D BusMode->BusWidth; + Hs200BusMode.ClockFreq =3D BusMode->ClockFreq; + Hs200BusMode.DriverStrength =3D BusMode->DriverStrength; =20 - Status =3D EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, 8); + Status =3D EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, &Hs200BusMode); if (EFI_ERROR (Status)) { return Status; } + // - // Set to Hight Speed timing and set the clock frequency to a value less= than 52MHz. + // Set to High Speed timing and set the clock frequency to a value less = than or equal to 52MHz. + // This step is necessary to be able to switch Bus into 8 bit DDR mode w= hich is unsupported in HS200. // - HsTiming =3D 1; - Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, Sd= MmcMmcHsSdr, 52); + Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = SdMmcMmcHsSdr); if (EFI_ERROR (Status)) { return Status; } - // - // HS400 mode must use 8 data lines. - // - Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, TRUE, 8); + + HsFreq =3D BusMode->ClockFreq < 52 ? BusMode->ClockFreq : 52; + Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->Dri= verStrength, SdMmcMmcHsSdr, HsFreq); if (EFI_ERROR (Status)) { return Status; } =20 - Timing =3D SdMmcMmcHs400; + Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, TRUE, BusMode= ->BusWidth); + if (EFI_ERROR (Status)) { + return Status; + } =20 - Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = Timing); + Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = BusMode->BusTiming); if (EFI_ERROR (Status)) { return Status; } =20 - HsTiming =3D 3; - Status =3D EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, HsTiming, Ti= ming, ClockFreq); + return EmmcSwitchBusTiming (PciIo, PassThru, Slot, Rca, BusMode->DriverS= trength, BusMode->BusTiming, BusMode->ClockFreq); +} =20 - return Status; +/** + Check if passed BusTiming is supported in both controller and card. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] ExtCsd Pointer to the card's extended CSD + @param[in] BusTiming Bus timing to check + + @retval TRUE Both card and controller support given BusTiming + @retval FALSE Card or controller doesn't support given BusTiming +**/ +BOOLEAN +EmmcIsBusTimingSupported ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN EMMC_EXT_CSD *ExtCsd, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + BOOLEAN Supported; + SD_MMC_HC_SLOT_CAP *Capabilities; + + Capabilities =3D &Private->Capability[SlotIndex]; + + Supported =3D FALSE; + switch (BusTiming) { + case SdMmcMmcHs400: + if ((((ExtCsd->DeviceType & (BIT6 | BIT7)) !=3D 0) && (Capabilities= ->Hs400 !=3D 0)) && Capabilities->BusWidth8 !=3D 0) { + Supported =3D TRUE; + } + break; + case SdMmcMmcHs200: + if ((((ExtCsd->DeviceType & (BIT4 | BIT5)) !=3D 0) && (Capabilities= ->Sdr104 !=3D 0))) { + Supported =3D TRUE; + } + break; + case SdMmcMmcHsDdr: + if ((((ExtCsd->DeviceType & (BIT2 | BIT3)) !=3D 0) && (Capabilities= ->Ddr50 !=3D 0))) { + Supported =3D TRUE; + } + break; + case SdMmcMmcHsSdr: + if ((((ExtCsd->DeviceType & BIT1) !=3D 0) && (Capabilities->HighSpe= ed !=3D 0))) { + Supported =3D TRUE; + } + break; + case SdMmcMmcLegacy: + if ((ExtCsd->DeviceType & BIT0) !=3D 0) { + Supported =3D TRUE; + } + break; + default: + ASSERT (FALSE); + } + + return Supported; +} + +/** + Get the target bus timing to set on the link. This function + will try to select highest bus timing supported by card, controller + and the driver. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] ExtCsd Pointer to the card's extended CSD + + @return Bus timing value that should be set on link +**/ +SD_MMC_BUS_MODE +EmmcGetTargetBusTiming ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN EMMC_EXT_CSD *ExtCsd + ) +{ + SD_MMC_BUS_MODE BusTiming; + + // + // We start with highest bus timing that this driver currently supports = and + // return as soon as we find supported timing. + // + BusTiming =3D SdMmcMmcHs400; + while (BusTiming > SdMmcMmcLegacy) { + if (EmmcIsBusTimingSupported (Private, SlotIndex, ExtCsd, BusTiming)) { + break; + } + BusTiming--; + } + + return BusTiming; +} + +/** + Check if the passed bus width is supported by controller and card. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] BusTiming Bus timing set on the link + @param[in] BusWidth Bus width to check + + @retval TRUE Passed bus width is supported in current bus configuration + @retval FALSE Passed bus width is not supported in current bus configur= ation +**/ +BOOLEAN +EmmcIsBusWidthSupported ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN SD_MMC_BUS_MODE BusTiming, + IN UINT16 BusWidth + ) +{ + if (BusWidth =3D=3D 8 && Private->Capability[SlotIndex].BusWidth8 !=3D 0= ) { + return TRUE; + } else if (BusWidth =3D=3D 4 && BusTiming !=3D SdMmcMmcHs400) { + return TRUE; + } else if (BusWidth =3D=3D 1 && (BusTiming =3D=3D SdMmcMmcHsSdr || BusTi= ming =3D=3D SdMmcMmcLegacy)) { + return TRUE; + } + + return FALSE; +} + +/** + Get the target bus width to be set on the bus. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] ExtCsd Pointer to card's extended CSD + @param[in] BusTiming Bus timing set on the bus + + @return Bus width to be set on the bus +**/ +UINT8 +EmmcGetTargetBusWidth ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN EMMC_EXT_CSD *ExtCsd, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + UINT8 BusWidth; + UINT8 PreferredBusWidth; + + PreferredBusWidth =3D Private->Slot[SlotIndex].OperatingParameters.BusWi= dth; + + if (PreferredBusWidth !=3D EDKII_SD_MMC_BUS_WIDTH_IGNORE && + EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, PreferredBus= Width)) { + BusWidth =3D PreferredBusWidth; + } else if (EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, 8)) { + BusWidth =3D 8; + } else if (EmmcIsBusWidthSupported (Private, SlotIndex, BusTiming, 4)) { + BusWidth =3D 4; + } else { + BusWidth =3D 1; + } + + return BusWidth; +} + +/** + Get the target clock frequency to be set on the bus. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] ExtCsd Pointer to card's extended CSD + @param[in] BusTiming Bus timing to be set on the bus + + @return Value of the clock frequency to be set on bus in MHz +**/ +UINT32 +EmmcGetTargetClockFreq ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN EMMC_EXT_CSD *ExtCsd, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + UINT32 PreferredClockFreq; + UINT32 MaxClockFreq; + + PreferredClockFreq =3D Private->Slot[SlotIndex].OperatingParameters.Cloc= kFreq; + + switch (BusTiming) { + case SdMmcMmcHs400: + case SdMmcMmcHs200: + MaxClockFreq =3D 200; + break; + case SdMmcMmcHsSdr: + case SdMmcMmcHsDdr: + MaxClockFreq =3D 52; + break; + default: + MaxClockFreq =3D 26; + break; + } + + if (PreferredClockFreq !=3D EDKII_SD_MMC_CLOCK_FREQ_IGNORE && PreferredC= lockFreq < MaxClockFreq) { + return PreferredClockFreq; + } else { + return MaxClockFreq; + } +} + +/** + Get the driver strength to be set on bus. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] ExtCsd Pointer to card's extended CSD + @param[in] BusTiming Bus timing set on the bus + + @return Value of the driver strength to be set on the bus +**/ +EDKII_SD_MMC_DRIVER_STRENGTH +EmmcGetTargetDriverStrength ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN EMMC_EXT_CSD *ExtCsd, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + EDKII_SD_MMC_DRIVER_STRENGTH PreferredDriverStrength; + EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength; + + PreferredDriverStrength =3D Private->Slot[SlotIndex].OperatingParameters= .DriverStrength; + DriverStrength.Emmc =3D EmmcDriverStrengthType0; + + if (PreferredDriverStrength.Emmc !=3D EDKII_SD_MMC_DRIVER_STRENGTH_IGNOR= E && + (ExtCsd->DriverStrength & (BIT0 << PreferredDriverStrength.Emmc))) { + DriverStrength.Emmc =3D PreferredDriverStrength.Emmc; + } + + return DriverStrength; +} + +/** + Get the target settings for the bus mode. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] ExtCsd Pointer to card's extended CSD + @param[out] BusMode Target configuration of the bus +**/ +VOID +EmmcGetTargetBusMode ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN EMMC_EXT_CSD *ExtCsd, + OUT SD_MMC_BUS_SETTINGS *BusMode + ) +{ + BusMode->BusTiming =3D EmmcGetTargetBusTiming (Private, SlotIndex, ExtCs= d); + BusMode->BusWidth =3D EmmcGetTargetBusWidth (Private, SlotIndex, ExtCsd,= BusMode->BusTiming); + BusMode->ClockFreq =3D EmmcGetTargetClockFreq (Private, SlotIndex, ExtCs= d, BusMode->BusTiming); + BusMode->DriverStrength =3D EmmcGetTargetDriverStrength (Private, SlotIn= dex, ExtCsd, BusMode->BusTiming); } =20 /** @@ -983,10 +1253,7 @@ EmmcSetBusMode ( EFI_STATUS Status; EMMC_CSD Csd; EMMC_EXT_CSD ExtCsd; - UINT8 HsTiming; - BOOLEAN IsDdr; - UINT32 ClockFreq; - UINT8 BusWidth; + SD_MMC_BUS_SETTINGS BusMode; SD_MMC_HC_PRIVATE_DATA *Private; =20 Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); @@ -1004,85 +1271,30 @@ EmmcSetBusMode ( } =20 ASSERT (Private->BaseClkFreq[Slot] !=3D 0); + // - // Check if the Host Controller support 8bits bus width. - // - if (Private->Capability[Slot].BusWidth8 !=3D 0) { - BusWidth =3D 8; - } else { - BusWidth =3D 4; - } - // - // Get Deivce_Type from EXT_CSD register. + // Get Device_Type from EXT_CSD register. // Status =3D EmmcGetExtCsd (PassThru, Slot, &ExtCsd); if (EFI_ERROR (Status)) { DEBUG ((DEBUG_ERROR, "EmmcSetBusMode: GetExtCsd fails with %r\n", Stat= us)); return Status; } - // - // Calculate supported bus speed/bus width/clock frequency. - // - HsTiming =3D 0; - IsDdr =3D FALSE; - ClockFreq =3D 0; - if (((ExtCsd.DeviceType & (BIT4 | BIT5)) !=3D 0) && (Private->Capabilit= y[Slot].Sdr104 !=3D 0)) { - HsTiming =3D 2; - IsDdr =3D FALSE; - ClockFreq =3D 200; - } else if (((ExtCsd.DeviceType & (BIT2 | BIT3)) !=3D 0) && (Private->Ca= pability[Slot].Ddr50 !=3D 0)) { - HsTiming =3D 1; - IsDdr =3D TRUE; - ClockFreq =3D 52; - } else if (((ExtCsd.DeviceType & BIT1) !=3D 0) && (Private->Capability[= Slot].HighSpeed !=3D 0)) { - HsTiming =3D 1; - IsDdr =3D FALSE; - ClockFreq =3D 52; - } else if (((ExtCsd.DeviceType & BIT0) !=3D 0) && (Private->Capability[= Slot].HighSpeed !=3D 0)) { - HsTiming =3D 1; - IsDdr =3D FALSE; - ClockFreq =3D 26; - } - // - // Check if both of the device and the host controller support HS400 DDR= mode. - // - if (((ExtCsd.DeviceType & (BIT6 | BIT7)) !=3D 0) && (Private->Capabilit= y[Slot].Hs400 !=3D 0)) { - // - // The host controller supports 8bits bus. - // - ASSERT (BusWidth =3D=3D 8); - HsTiming =3D 3; - IsDdr =3D TRUE; - ClockFreq =3D 200; - } =20 - if ((ClockFreq =3D=3D 0) || (HsTiming =3D=3D 0)) { - // - // Continue using default setting. - // - return EFI_SUCCESS; - } + EmmcGetTargetBusMode (Private, Slot, &ExtCsd, &BusMode); =20 - DEBUG ((DEBUG_INFO, "EmmcSetBusMode: HsTiming %d ClockFreq %d BusWidth %= d Ddr %a\n", HsTiming, ClockFreq, BusWidth, IsDdr ? "TRUE":"FALSE")); + DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Target bus mode: timing =3D %d, wid= th =3D %d, clock freq =3D %d, driver strength =3D %d\n", + BusMode.BusTiming, BusMode.BusWidth, BusMode.Clo= ckFreq, BusMode.DriverStrength.Emmc)); =20 - if (HsTiming =3D=3D 3) { - // - // Execute HS400 timing switch procedure - // - Status =3D EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, ClockFreq); - } else if (HsTiming =3D=3D 2) { - // - // Execute HS200 timing switch procedure - // - Status =3D EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq, B= usWidth); + if (BusMode.BusTiming =3D=3D SdMmcMmcHs400) { + Status =3D EmmcSwitchToHS400 (PciIo, PassThru, Slot, Rca, &BusMode); + } else if (BusMode.BusTiming =3D=3D SdMmcMmcHs200) { + Status =3D EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, &BusMode); } else { - // - // Execute High Speed timing switch procedure - // - Status =3D EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, ClockFre= q, IsDdr, BusWidth); + Status =3D EmmcSwitchToHighSpeed (PciIo, PassThru, Slot, Rca, &BusMode= ); } =20 - DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Switch to %a %r\n", (HsTiming =3D= =3D 3) ? "HS400" : ((HsTiming =3D=3D 2) ? "HS200" : "HighSpeed"), Status)); + DEBUG ((DEBUG_INFO, "EmmcSetBusMode: Switch to %a %r\n", (BusMode.BusTim= ing =3D=3D SdMmcMmcHs400) ? "HS400" : ((BusMode.BusTiming =3D=3D SdMmcMmcHs= 200) ? "HS200" : "HighSpeed"), Status)); =20 return Status; } diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModulePkg/B= us/Pci/SdMmcPciHcDxe/SdDevice.c index 17936a5492..88ece5256c 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c @@ -313,10 +313,6 @@ SdCardSetRca ( return Status; } =20 - - - - /** Send command SELECT_DESELECT_CARD to the SD device to select/deselect it. =20 @@ -472,14 +468,14 @@ SdCardSetBusWidth ( =20 Refer to SD Physical Layer Simplified Spec 4.1 Section 4.7 for details. =20 - @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCOL= instance. - @param[in] Slot The slot number of the SD card to send the com= mand to. - @param[in] AccessMode The value for access mode group. - @param[in] CommandSystem The value for command set group. - @param[in] DriveStrength The value for drive length group. - @param[in] PowerLimit The value for power limit group. - @param[in] Mode Switch or check function. - @param[out] SwitchResp The return switch function status. + @param[in] PassThru A pointer to the EFI_SD_MMC_PASS_THRU_PROTOCO= L instance. + @param[in] Slot The slot number of the SD card to send the co= mmand to. + @param[in] BusTiming Target bus timing based on which access group= value will be set. + @param[in] CommandSystem The value for command set group. + @param[in] DriverStrength The value for driver strength group. + @param[in] PowerLimit The value for power limit group. + @param[in] Mode Switch or check function. + @param[out] SwitchResp The return switch function status. =20 @retval EFI_SUCCESS The operation is done correctly. @retval Others The operation fails. @@ -489,9 +485,9 @@ EFI_STATUS SdCardSwitch ( IN EFI_SD_MMC_PASS_THRU_PROTOCOL *PassThru, IN UINT8 Slot, - IN UINT8 AccessMode, + IN SD_MMC_BUS_MODE BusTiming, IN UINT8 CommandSystem, - IN UINT8 DriveStrength, + IN SD_DRIVER_STRENGTH_TYPE DriverStrength, IN UINT8 PowerLimit, IN BOOLEAN Mode, OUT UINT8 *SwitchResp @@ -502,6 +498,7 @@ SdCardSwitch ( EFI_SD_MMC_PASS_THRU_COMMAND_PACKET Packet; EFI_STATUS Status; UINT32 ModeValue; + UINT8 AccessMode; =20 ZeroMem (&SdMmcCmdBlk, sizeof (SdMmcCmdBlk)); ZeroMem (&SdMmcStatusBlk, sizeof (SdMmcStatusBlk)); @@ -516,14 +513,49 @@ SdCardSwitch ( SdMmcCmdBlk.ResponseType =3D SdMmcResponseTypeR1; =20 ModeValue =3D Mode ? BIT31 : 0; - SdMmcCmdBlk.CommandArgument =3D (AccessMode & 0xF) | ((PowerLimit & 0xF)= << 4) | \ - ((DriveStrength & 0xF) << 8) | ((DriveStre= ngth & 0xF) << 12) | \ + + switch (BusTiming) { + case SdMmcUhsDdr50: + AccessMode =3D 0x4; + break; + case SdMmcUhsSdr104: + AccessMode =3D 0x3; + break; + case SdMmcUhsSdr50: + AccessMode =3D 0x2; + break; + case SdMmcUhsSdr25: + case SdMmcSdHs: + AccessMode =3D 0x1; + break; + case SdMmcUhsSdr12: + case SdMmcSdDs: + AccessMode =3D 0; + break; + default: + AccessMode =3D 0xF; + } + + SdMmcCmdBlk.CommandArgument =3D (AccessMode & 0xF) | ((CommandSystem & 0= xF) << 4) | \ + ((DriverStrength & 0xF) << 8) | ((PowerLim= it & 0xF) << 12) | \ ModeValue; =20 Packet.InDataBuffer =3D SwitchResp; Packet.InTransferLength =3D 64; =20 Status =3D SdMmcPassThruPassThru (PassThru, Slot, &Packet, NULL); + if (EFI_ERROR (Status)) { + return Status; + } + + if (Mode) { + if ((((AccessMode & 0xF) !=3D 0xF) && ((SwitchResp[16] & 0xF) !=3D Acc= essMode) || + (((CommandSystem & 0xF) !=3D 0xF) && (((SwitchResp[16] >> 4) & 0xF= ) !=3D CommandSystem)) || + (((DriverStrength & 0xF) !=3D 0xF) && ((SwitchResp[15] & 0xF) !=3D= DriverStrength)) || + (((PowerLimit & 0xF) !=3D 0xF) && (((SwitchResp[15] >> 4) & 0xF) != =3D PowerLimit)))) { + return EFI_DEVICE_ERROR; + } + } =20 return Status; } @@ -748,6 +780,273 @@ SdCardSwitchBusWidth ( return Status; } =20 +/** + Check if passed BusTiming is supported in both controller and card. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] CardSupportedBusTimings Bitmask indicating which bus timings= are supported by card + @param[in] IsInUhsI Flag indicating if link is in UHS-I + + @retval TRUE Both card and controller support given BusTiming + @retval FALSE Card or controller doesn't support given BusTiming +**/ +BOOLEAN +SdIsBusTimingSupported ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN UINT8 CardSupportedBusTimings, + IN BOOLEAN IsInUhsI, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + SD_MMC_HC_SLOT_CAP *Capability; + + Capability =3D &Private->Capability[SlotIndex]; + + if (IsInUhsI) { + switch (BusTiming) { + case SdMmcUhsSdr104: + if ((Capability->Sdr104 !=3D 0) && ((CardSupportedBusTimings & BIT= 3) !=3D 0)) { + return TRUE; + } + break; + case SdMmcUhsDdr50: + if ((Capability->Ddr50 !=3D 0) && ((CardSupportedBusTimings & BIT4= ) !=3D 0)) { + return TRUE; + } + break; + case SdMmcUhsSdr50: + if ((Capability->Sdr50 !=3D 0) && ((CardSupportedBusTimings & BIT2= ) !=3D 0)) { + return TRUE; + } + break; + case SdMmcUhsSdr25: + if ((CardSupportedBusTimings & BIT1) !=3D 0) { + return TRUE; + } + break; + case SdMmcUhsSdr12: + if ((CardSupportedBusTimings & BIT0) !=3D 0) { + return TRUE; + } + break; + default: + break; + } + } else { + switch (BusTiming) { + case SdMmcSdHs: + if ((Capability->HighSpeed !=3D 0) && (CardSupportedBusTimings & B= IT1) !=3D 0) { + return TRUE; + } + break; + case SdMmcSdDs: + if ((CardSupportedBusTimings & BIT0) !=3D 0) { + return TRUE; + } + break; + default: + break; + } + } + + return FALSE; +} + +/** + Get the target bus timing to set on the link. This function + will try to select highest bus timing supported by card, controller + and the driver. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] CardSupportedBusTimings Bitmask indicating which bus timings= are supported by card + @param[in] IsInUhsI Flag indicating if link is in UHS-I + + @return Bus timing value that should be set on link +**/ +SD_MMC_BUS_MODE +SdGetTargetBusTiming ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN UINT8 CardSupportedBusTimings, + IN BOOLEAN IsInUhsI + ) +{ + SD_MMC_BUS_MODE BusTiming; + + if (IsInUhsI) { + BusTiming =3D SdMmcUhsSdr104; + } else { + BusTiming =3D SdMmcSdHs; + } + + while (BusTiming > SdMmcSdDs) { + if (SdIsBusTimingSupported (Private, SlotIndex, CardSupportedBusTiming= s, IsInUhsI, BusTiming)) { + break; + } + BusTiming--; + } + + return BusTiming; +} + +/** + Get the target bus width to be set on the bus. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] BusTiming Bus timing set on the bus + + @return Bus width to be set on the bus +**/ +UINT8 +SdGetTargetBusWidth ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + UINT8 BusWidth; + UINT8 PreferredBusWidth; + + PreferredBusWidth =3D Private->Slot[SlotIndex].OperatingParameters.BusWi= dth; + + if (BusTiming =3D=3D SdMmcSdDs || BusTiming =3D=3D SdMmcSdHs) { + if (PreferredBusWidth !=3D EDKII_SD_MMC_BUS_WIDTH_IGNORE && + (PreferredBusWidth =3D=3D 1 || PreferredBusWidth =3D=3D 4)) { + BusWidth =3D PreferredBusWidth; + } else { + BusWidth =3D 4; + } + } else { + // + // UHS-I modes support only 4-bit width. + // Switch to 4-bit has been done before calling this function anyway so + // this is purely informational. + // + BusWidth =3D 4; + } + + return BusWidth; +} + +/** + Get the target clock frequency to be set on the bus. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] BusTiming Bus timing to be set on the bus + + @return Value of the clock frequency to be set on bus in MHz +**/ +UINT32 +SdGetTargetBusClockFreq ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + UINT32 PreferredClockFreq; + UINT32 MaxClockFreq; + + PreferredClockFreq =3D Private->Slot[SlotIndex].OperatingParameters.Cloc= kFreq; + + switch (BusTiming) { + case SdMmcUhsSdr104: + MaxClockFreq =3D 208; + break; + case SdMmcUhsSdr50: + MaxClockFreq =3D 100; + break; + case SdMmcUhsDdr50: + case SdMmcUhsSdr25: + case SdMmcSdHs: + MaxClockFreq =3D 50; + break; + case SdMmcUhsSdr12: + case SdMmcSdDs: + default: + MaxClockFreq =3D 25; + } + + if (PreferredClockFreq !=3D EDKII_SD_MMC_CLOCK_FREQ_IGNORE && PreferredC= lockFreq < MaxClockFreq) { + return PreferredClockFreq; + } else { + return MaxClockFreq; + } +} + +/** + Get the driver strength to be set on bus. + + @param[in] Private Pointer to controller private d= ata + @param[in] SlotIndex Index of the slot in the contro= ller + @param[in] CardSupportedDriverStrengths Bitmask indicating which driver= strengths are supported on the card + @param[in] BusTiming Bus timing set on the bus + + @return Value of the driver strength to be set on the bus +**/ +EDKII_SD_MMC_DRIVER_STRENGTH +SdGetTargetDriverStrength ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN UINT8 CardSupportedDriverStrengths, + IN SD_MMC_BUS_MODE BusTiming + ) +{ + EDKII_SD_MMC_DRIVER_STRENGTH PreferredDriverStrength; + EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength; + + if (BusTiming =3D=3D SdMmcSdDs || BusTiming =3D=3D SdMmcSdHs) { + DriverStrength.Sd =3D SdDriverStrengthIgnore; + return DriverStrength; + } + + PreferredDriverStrength =3D Private->Slot[SlotIndex].OperatingParameters= .DriverStrength; + DriverStrength.Sd =3D SdDriverStrengthTypeB; + + if (PreferredDriverStrength.Sd !=3D EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE = && + (CardSupportedDriverStrengths & (BIT0 << PreferredDriverStrength.Sd)= )) { + + if ((PreferredDriverStrength.Sd =3D=3D SdDriverStrengthTypeA && + (Private->Capability[SlotIndex].DriverTypeA !=3D 0)) || + (PreferredDriverStrength.Sd =3D=3D SdDriverStrengthTypeC && + (Private->Capability[SlotIndex].DriverTypeC !=3D 0)) || + (PreferredDriverStrength.Sd =3D=3D SdDriverStrengthTypeD && + (Private->Capability[SlotIndex].DriverTypeD !=3D 0))) { + DriverStrength.Sd =3D PreferredDriverStrength.Sd; + } + } + + return DriverStrength; +} + +/** + Get the target settings for the bus mode. + + @param[in] Private Pointer to controller private data + @param[in] SlotIndex Index of the slot in the controller + @param[in] SwitchQueryResp Pointer to switch query response + @param[in] IsInUhsI Flag indicating if link is in UHS-I mode + @param[out] BusMode Target configuration of the bus +**/ +VOID +SdGetTargetBusMode ( + IN SD_MMC_HC_PRIVATE_DATA *Private, + IN UINT8 SlotIndex, + IN UINT8 *SwitchQueryResp, + IN BOOLEAN IsInUhsI, + OUT SD_MMC_BUS_SETTINGS *BusMode + ) +{ + BusMode->BusTiming =3D SdGetTargetBusTiming (Private, SlotIndex, SwitchQ= ueryResp[13], IsInUhsI); + BusMode->BusWidth =3D SdGetTargetBusWidth (Private, SlotIndex, BusMode->= BusTiming); + BusMode->ClockFreq =3D SdGetTargetBusClockFreq (Private, SlotIndex, BusM= ode->BusTiming); + BusMode->DriverStrength =3D SdGetTargetDriverStrength (Private, SlotInde= x, SwitchQueryResp[9], BusMode->BusTiming); +} + /** Switch the high speed timing according to request. =20 @@ -775,13 +1074,10 @@ SdCardSetBusMode ( { EFI_STATUS Status; SD_MMC_HC_SLOT_CAP *Capability; - UINT32 ClockFreq; - UINT8 BusWidth; - UINT8 AccessMode; UINT8 HostCtrl1; UINT8 SwitchResp[64]; - SD_MMC_BUS_MODE Timing; SD_MMC_HC_PRIVATE_DATA *Private; + SD_MMC_BUS_SETTINGS BusMode; =20 Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); =20 @@ -792,61 +1088,51 @@ SdCardSetBusMode ( return Status; } =20 - BusWidth =3D 4; - - Status =3D SdCardSwitchBusWidth (PciIo, PassThru, Slot, Rca, BusWidth); - if (EFI_ERROR (Status)) { - return Status; + if (S18A) { + // + // For UHS-I speed modes 4-bit data bus is requiered so we + // switch here irrespective of platform preference. + // + Status =3D SdCardSwitchBusWidth (PciIo, PassThru, Slot, Rca, 4); + if (EFI_ERROR (Status)) { + return Status; + } } + // // Get the supported bus speed from SWITCH cmd return data group #1. // - Status =3D SdCardSwitch (PassThru, Slot, 0xF, 0xF, 0xF, 0xF, FALSE, Swit= chResp); + Status =3D SdCardSwitch (PassThru, Slot, 0xFF, 0xF, SdDriverStrengthIgno= re, 0xF, FALSE, SwitchResp); if (EFI_ERROR (Status)) { return Status; } - // - // Calculate supported bus speed/bus width/clock frequency by host and d= evice capability. - // - ClockFreq =3D 0; - if (S18A && (Capability->Sdr104 !=3D 0) && ((SwitchResp[13] & BIT3) !=3D= 0)) { - ClockFreq =3D 208; - AccessMode =3D 3; - Timing =3D SdMmcUhsSdr104; - } else if (S18A && (Capability->Sdr50 !=3D 0) && ((SwitchResp[13] & BIT2= ) !=3D 0)) { - ClockFreq =3D 100; - AccessMode =3D 2; - Timing =3D SdMmcUhsSdr50; - } else if (S18A && (Capability->Ddr50 !=3D 0) && ((SwitchResp[13] & BIT4= ) !=3D 0)) { - ClockFreq =3D 50; - AccessMode =3D 4; - Timing =3D SdMmcUhsDdr50; - } else if ((SwitchResp[13] & BIT1) !=3D 0) { - ClockFreq =3D 50; - AccessMode =3D 1; - Timing =3D SdMmcUhsSdr25; - } else { - ClockFreq =3D 25; - AccessMode =3D 0; - Timing =3D SdMmcUhsSdr12; + + SdGetTargetBusMode (Private, Slot, SwitchResp, S18A, &BusMode); + + DEBUG ((DEBUG_INFO, "SdCardSetBusMode: Target bus mode: bus timing =3D %= d, bus width =3D %d, clock freq[MHz] =3D %d, driver strength =3D %d\n", + BusMode.BusTiming, BusMode.BusWidth, BusMode.Cloc= kFreq, BusMode.DriverStrength.Sd)); + + if (!S18A) { + Status =3D SdCardSwitchBusWidth (PciIo, PassThru, Slot, Rca, BusMode.B= usWidth); + if (EFI_ERROR (Status)) { + return Status; + } } =20 - Status =3D SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, TRUE= , SwitchResp); + Status =3D SdCardSwitch (PassThru, Slot, BusMode.BusTiming, 0xF, BusMode= .DriverStrength.Sd, 0xF, TRUE, SwitchResp); if (EFI_ERROR (Status)) { return Status; } =20 - if ((SwitchResp[16] & 0xF) !=3D AccessMode) { - DEBUG ((DEBUG_ERROR, "SdCardSetBusMode: Switch to AccessMode %d ClockF= req %d BusWidth %d fails! The Switch response is 0x%1x\n", AccessMode, Cloc= kFreq, BusWidth, SwitchResp[16] & 0xF)); - return EFI_DEVICE_ERROR; + Status =3D SdMmcSetDriverStrength (Private->PciIo, Slot, BusMode.DriverS= trength.Sd); + if (EFI_ERROR (Status)) { + return Status; } =20 - DEBUG ((DEBUG_INFO, "SdCardSetBusMode: Switch to AccessMode %d ClockFreq= %d BusWidth %d\n", AccessMode, ClockFreq, BusWidth)); - // - // Set to Hight Speed timing + // Set to High Speed timing // - if (AccessMode =3D=3D 1) { + if (BusMode.BusTiming =3D=3D SdMmcSdHs) { HostCtrl1 =3D BIT2; Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL1, sizeof (H= ostCtrl1), &HostCtrl1); if (EFI_ERROR (Status)) { @@ -854,12 +1140,12 @@ SdCardSetBusMode ( } } =20 - Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = Timing); + Status =3D SdMmcHcUhsSignaling (Private->ControllerHandle, PciIo, Slot, = BusMode.BusTiming); if (EFI_ERROR (Status)) { return Status; } =20 - Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, Private->B= aseClkFreq[Slot], Private->ControllerVersion[Slot]); + Status =3D SdMmcHcClockSupply (PciIo, Slot, BusMode.ClockFreq * 1000, Pr= ivate->BaseClkFreq[Slot], Private->ControllerVersion[Slot]); if (EFI_ERROR (Status)) { return Status; } @@ -869,7 +1155,7 @@ SdCardSetBusMode ( Private->ControllerHandle, Slot, EdkiiSdMmcSwitchClockFreqPost, - &Timing + &BusMode.BusTiming ); if (EFI_ERROR (Status)) { DEBUG (( @@ -882,7 +1168,7 @@ SdCardSetBusMode ( } } =20 - if ((AccessMode =3D=3D 3) || ((AccessMode =3D=3D 2) && (Capability->Tuni= ngSDR50 !=3D 0))) { + if ((BusMode.BusTiming =3D=3D SdMmcUhsSdr104) || ((BusMode.BusTiming =3D= =3D SdMmcUhsSdr50) && (Capability->TuningSDR50 !=3D 0))) { Status =3D SdCardTuningClock (PciIo, PassThru, Slot); if (EFI_ERROR (Status)) { return Status; diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c index 4881ee44cc..373f1bed45 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c @@ -28,6 +28,11 @@ EFI_DRIVER_BINDING_PROTOCOL gSdMmcPciHcDriverBinding =3D= { NULL }; =20 +#define SLOT_INIT_TEMPLATE {0, UnknownSlot, 0, 0, 0, \ + {EDKII_SD_MMC_BUS_WIDTH_IGNORE,\ + EDKII_SD_MMC_CLOCK_FREQ_IGNORE,\ + {EDKII_SD_MMC_DRIVER_STRENGTH_IGNORE}}} + // // Template for SD/MMC host controller private data. // @@ -50,8 +55,12 @@ SD_MMC_HC_PRIVATE_DATA gSdMmcPciHcTemplate =3D { // Queue INITIALIZE_LIST_HEAD_VARIABLE (gSdMmcPciHcTemplate.Queue), { // Slot - {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot,= 0, 0, 0}, - {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot, 0, 0, 0}, {0, UnknownSlot,= 0, 0, 0} + SLOT_INIT_TEMPLATE, + SLOT_INIT_TEMPLATE, + SLOT_INIT_TEMPLATE, + SLOT_INIT_TEMPLATE, + SLOT_INIT_TEMPLATE, + SLOT_INIT_TEMPLATE }, { // Capability {0}, @@ -328,6 +337,7 @@ SdMmcPciHcEnumerateDevice ( =20 return; } + /** Tests to see if this driver supports a given controller. If a child devi= ce is provided, it further tests to see if this driver supports creating a handle for th= e specified child device. @@ -619,7 +629,6 @@ SdMmcPciHcDriverBindingStart ( Support64BitDma =3D TRUE; for (Slot =3D FirstBar; Slot < (FirstBar + SlotNum); Slot++) { Private->Slot[Slot].Enable =3D TRUE; - // // Get SD/MMC Pci Host Controller Version // @@ -635,19 +644,34 @@ SdMmcPciHcDriverBindingStart ( =20 Private->BaseClkFreq[Slot] =3D Private->Capability[Slot].BaseClkFreq; =20 - if (mOverride !=3D NULL && mOverride->Capability !=3D NULL) { - Status =3D mOverride->Capability ( - Controller, - Slot, - &Private->Capability[Slot], - &Private->BaseClkFreq[Slot] - ); - if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n", - __FUNCTION__, Status)); - continue; + if (mOverride !=3D NULL) { + if (mOverride->Capability !=3D NULL) { + Status =3D mOverride->Capability ( + Controller, + Slot, + &Private->Capability[Slot], + &Private->BaseClkFreq[Slot] + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: Failed to override capability - %r\n", + __FUNCTION__, Status)); + continue; + } + } + + if (mOverride->NotifyPhase !=3D NULL) { + Status =3D mOverride->NotifyPhase ( + Controller, + Slot, + EdkiiSdMmcGetOperatingParam, + (VOID*)&Private->Slot[Slot].OperatingParamet= ers + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_WARN, "%a: Failed to get operating parameters, usi= ng defaults\n", __FUNCTION__)); + } } } + DumpCapabilityReg (Slot, &Private->Capability[Slot]); DEBUG (( DEBUG_INFO, diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h b/MdeModule= Pkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h index 77bbf83b76..c29e48767e 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h @@ -78,11 +78,12 @@ typedef enum { } EFI_SD_MMC_SLOT_TYPE; =20 typedef struct { - BOOLEAN Enable; - EFI_SD_MMC_SLOT_TYPE SlotType; - BOOLEAN MediaPresent; - BOOLEAN Initialized; - SD_MMC_CARD_TYPE CardType; + BOOLEAN Enable; + EFI_SD_MMC_SLOT_TYPE SlotType; + BOOLEAN MediaPresent; + BOOLEAN Initialized; + SD_MMC_CARD_TYPE CardType; + EDKII_SD_MMC_OPERATING_PARAMETERS OperatingParameters; } SD_MMC_HC_SLOT; =20 typedef struct { @@ -120,6 +121,13 @@ typedef struct { UINT32 BaseClkFreq[SD_MMC_HC_MAX_SLOT]; } SD_MMC_HC_PRIVATE_DATA; =20 +typedef struct { + SD_MMC_BUS_MODE BusTiming; + UINT8 BusWidth; + UINT32 ClockFreq; + EDKII_SD_MMC_DRIVER_STRENGTH DriverStrength; +} SD_MMC_BUS_SETTINGS; + #define SD_MMC_HC_TRB_SIG SIGNATURE_32 ('T', 'R', 'B', 'T') =20 // diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c index 5d1f977e55..b9d04e0f17 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c @@ -1339,6 +1339,40 @@ SdMmcHcUhsSignaling ( return EFI_SUCCESS; } =20 +/** + Set driver strength in host controller. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] SlotIndex The slot index of the card. + @param[in] DriverStrength DriverStrength to set in the controller. + + @retval EFI_SUCCESS Driver strength programmed successfully. + @retval Others Failed to set driver strength. +**/ +EFI_STATUS +SdMmcSetDriverStrength ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 SlotIndex, + IN SD_DRIVER_STRENGTH_TYPE DriverStrength + ) +{ + EFI_STATUS Status; + UINT16 HostCtrl2; + + if (DriverStrength =3D=3D SdDriverStrengthIgnore) { + return EFI_SUCCESS; + } + + HostCtrl2 =3D (UINT16)~SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK; + Status =3D SdMmcHcAndMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeo= f (HostCtrl2), &HostCtrl2); + if (EFI_ERROR (Status)) { + return Status; + } + + HostCtrl2 =3D (DriverStrength << 4) & SD_MMC_HC_CTRL_DRIVER_STRENGTH_MAS= K; + return SdMmcHcOrMmio (PciIo, SlotIndex, SD_MMC_HC_HOST_CTRL2, sizeof (Ho= stCtrl2), &HostCtrl2); +} + /** Turn on/off LED. =20 diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModulePk= g/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h index 0b0d415256..088c70451c 100644 --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h @@ -72,6 +72,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define SD_MMC_HC_CTRL_MMC_HS200 0x0003 #define SD_MMC_HC_CTRL_MMC_HS400 0x0005 =20 +#define SD_MMC_HC_CTRL_DRIVER_STRENGTH_MASK 0x0030 + // // The transfer modes supported by SD Host Controller // @@ -617,4 +619,21 @@ SdMmcHcUhsSignaling ( IN SD_MMC_BUS_MODE Timing ); =20 +/** + Set driver strength in host controller. + + @param[in] PciIo The PCI IO protocol instance. + @param[in] SlotIndex The slot index of the card. + @param[in] DriverStrength DriverStrength to set in the controller. + + @retval EFI_SUCCESS Driver strength programmed successfully. + @retval Others Failed to set driver strength. +**/ +EFI_STATUS +SdMmcSetDriverStrength ( + IN EFI_PCI_IO_PROTOCOL *PciIo, + IN UINT8 SlotIndex, + IN SD_DRIVER_STRENGTH_TYPE DriverStrength + ); + #endif --=20 2.14.1.windows.1 -------------------------------------------------------------------- Intel Technology Poland sp. z o.o. ul. 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