From nobody Fri Apr 19 08:12:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+42216+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42216+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1560268847; cv=none; d=zoho.com; s=zohoarc; b=nJZ24g5QzvglTedxu/G9QV9axR7gBkhQ/wCJBUIrXFzMEDwt1oaRyvjZwWqNV4EXAQDXzwLWUJszWAuoru5hJiRFlHihzD4+5bSZcJooAVsA+03GMWn6aHz8WzcyJH+zxosgzPhahb7+uf7ltu5crvPs4+nmmv6l/awzhTZTs8k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560268847; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=VZFy6JmV5TMii2SGlZHzLaup7mSVpmPHN7LusnMTC2Y=; b=hmugya1XKyBd17XJ4YFMVfhws7xLgSMZDPn4OUYq/z/yN1oybsXsIMUycWiTG8j4GGCaPQS7bgHTbmMkD6OowGu15cYqyM3nhXsMXumLWDnV/46AXWzHih1yXYzyHkaO2Wb+mIqTqzxhBYWNfkEp+vOqKkTbveZ9eecXaUtWRn8= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42216+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1560268847121261.6945737485654; Tue, 11 Jun 2019 09:00:47 -0700 (PDT) Return-Path: X-Received: from mail-pg1-f195.google.com (mail-pg1-f195.google.com [209.85.215.195]) by groups.io with SMTP; Tue, 11 Jun 2019 05:18:30 -0700 X-Received: by mail-pg1-f195.google.com with SMTP id n2so6871923pgp.11 for ; Tue, 11 Jun 2019 05:18:29 -0700 (PDT) X-Gm-Message-State: APjAAAUzIUmPcKNPAk9WvJawmcVlpNYvC/TEOkwHnHPoHPDbzge7z5BU nsl+bDA7WmwCrYiqJCNd7qxk/93TNKY= X-Google-Smtp-Source: APXvYqxXTgnDBuVcmZcLOKpovwKB28xnoXu2ov9rI/sEVXxKQLcCpjAQbuh4XA9BHTY9n3615I+AUw== X-Received: by 2002:a65:64d9:: with SMTP id t25mr20118041pgv.130.1560255508868; Tue, 11 Jun 2019 05:18:28 -0700 (PDT) X-Received: from localhost ([121.95.100.191]) by smtp.gmail.com with ESMTPSA id c69sm7914603pje.6.2019.06.11.05.18.27 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 11 Jun 2019 05:18:27 -0700 (PDT) From: "Masahisa Kojima" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, Masahisa Kojima Subject: [edk2-devel] [edk2-platforms PATCH] Platform/Socionext/DeveloperBox: add SMBIOS type 17 table Date: Tue, 11 Jun 2019 21:17:50 +0900 Message-Id: <20190611121750.3882-1-masahisa.kojima@linaro.org> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,masahisa.kojima@linaro.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1560268846; bh=F5UAt5mFJ0IBLvZBL179ZcEKz5Gx7ezZjQdFBepM0Sc=; h=Cc:Date:From:Reply-To:Subject:To; b=RXzytXgImT2fjC7/phQ5kpj56aVIe5e+YCwDwiA77/YfXpbdfDz51O/UPysNvEbKFkP xSLmQF0ZYc7aWZNLHKTO9pSc4t8DtPwDBCnwGSxFz4qmh5PtgUNyTvmKCb+Za1S40yBZ5 BoxmXF0fi6fQ49tp6juEKQ+gSR9wJme+OhI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds the SMBIOS type 17 table support for Developerbox platform. The SPDs on a I2C bus is only accessible by the SCP, so SCP-firmware stores SPDs in non-secure SRAM. This commit also reduces the uefi stack size to allocate space for SPDs. It requires 2KB, 512bytes * 4 DIMMs. Signed-off-by: Masahisa Kojima --- .../Socionext/DeveloperBox/DeveloperBox.dsc | 3 + .../DeveloperBox/DeveloperBox.dsc.inc | 2 +- .../SmbiosPlatformDxe/SmbiosPlatformDxe.c | 494 +++++++++++++----- .../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 2 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 3 + 5 files changed, 381 insertions(+), 123 deletions(-) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index 97fb8c410c..f247370694 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -147,6 +147,9 @@ =20 gSynQuacerTokenSpaceGuid.PcdDramInfoBase|0x2E00FFC0 =20 + # SCP-firmware stored SPD DDR4 data in non-secure SRAM + gSynQuacerTokenSpaceGuid.PcdSmbiosStoredSpdDDR4Address|0x2E00F000 + # # 96boards mezzanine support # diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc.inc b/Platfor= m/Socionext/DeveloperBox/DeveloperBox.dsc.inc index a10e48ca07..abb113e858 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc.inc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc.inc @@ -137,7 +137,7 @@ =20 # non-secure SRAM gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 - gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFFC0 + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xF000 =20 gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24 =20 diff --git a/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatfo= rmDxe.c b/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformD= xe.c index 6227b77877..da0fd2e6a5 100644 --- a/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.c +++ b/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.c @@ -10,17 +10,48 @@ **/ =20 #include +#include #include #include #include #include #include #include +#include #include #include =20 STATIC EFI_SMBIOS_PROTOCOL *mSmbios; =20 +#define SPD4_MEM_BUS_WIDTH_8BIT (0x00) +#define SPD4_MEM_BUS_WIDTH_16BIT (BIT0) +#define SPD4_MEM_BUS_WIDTH_32BIT (BIT1) +#define SPD4_MEM_BUS_WIDTH_64BIT (BIT0 | BIT1) + +#define SPD4_MEM_DEV_WIDTH_4BIT (0x00) +#define SPD4_MEM_DEV_WIDTH_8BIT (BIT0) +#define SPD4_MEM_DEV_WIDTH_16BIT (BIT1) +#define SPD4_MEM_DEV_WIDTH_32BIT (BIT0 | BIT1) + +#define SPD4_MEM_MODULE_TYPE_RDIMM 0x01 +#define SPD4_MEM_MODULE_TYPE_UDIMM 0x02 +#define SPD4_MEM_MODULE_TYPE_SODIMM 0x03 + +#define TYPE17_DEVICE_LOCATOR_LEN (8 + 1) +#define TYPE17_BANK_LOCATOR_LEN (20 + 1) +#define TYPE17_MANUFACTURER_NAME_LEN (30 + 1) +#define TYPE17_SERIAL_NUMBER_LEN (16 + 1) +#define TYPE17_ASSETTAG_LEN (16 + 1) +#define TYPE17_MODULE_PART_NUMBER_LEN (20 + 1) + +#define TYPE17_STRINGS_MAX_LEN (TYPE17_DEVICE_LOCATOR_LEN + \ + TYPE17_BANK_LOCATOR_LEN + \ + TYPE17_MANUFACTURER_NAME_LEN + \ + TYPE17_SERIAL_NUMBER_LEN + \ + TYPE17_ASSETTAG_LEN + \ + TYPE17_MODULE_PART_NUMBER_LEN + \ + 1/* null SMBIOS_TABLE_STRING termin= ator */ ) + // // Type definition and contents of the default SMBIOS table. // This table covers only the minimum structures required by @@ -69,7 +100,7 @@ typedef struct { =20 typedef struct { SMBIOS_TABLE_TYPE17 Base; - CHAR8 Strings[]; + CHAR8 Strings[TYPE17_STRINGS_MAX_LEN]; } ARM_TYPE17; =20 typedef struct { @@ -94,6 +125,69 @@ enum { SMBIOS_HANDLE_MEMORY, }; =20 +struct JEP106_MANUFACTURER_TABLE { + UINT16 ManufacturerId; + CHAR8 ManufacturerName[TYPE17_MANUFACTURER_NAME_LEN]; +}; + +STATIC CONST struct JEP106_MANUFACTURER_TABLE Manufacturer[] =3D { + {0x0010, "NEC\0"}, + {0x002C, "Micron Technology\0"}, + {0x003D, "Tektronix\0"}, + {0x0097, "Texas Instruments\0"}, + {0x00AD, "SK Hynix\0"}, + {0x00B3, "IDT\0"}, + {0x00C1, "Infineon\0"}, + {0x00CE, "Samsung\0"}, + {0x00DA, "Winbond Electronic\0"}, + {0x014F, "Transcend Information\0"}, + {0x0194, "Smart Modular\0"}, + {0x0198, "Kingston\0"}, + {0x02C8, "Agilent Technologies\0"}, + {0x02FE, "Elpida\0"}, + {0x030B, "Nanya Technology\0"}, + {0x0443, "Ramaxel Technology\0"}, + {0x04B3, "Inphi Corporation\0"}, + {0x04C8, "Powerchip Semiconductor\0"}, + {0x0551, "Qimonda\0"}, + {0x0557, "AENEON\0"}, + {0x059B, "Crucial Technology\0"}, + {0xFFFF, "Unknown\0"} +}; + +enum SPD4_SDRAM_CAPACITY { + SPD4_SDRAM_CAPACITY_256MBIT =3D 0, + SPD4_SDRAM_CAPACITY_512MBIT, + SPD4_SDRAM_CAPACITY_1GBIT, + SPD4_SDRAM_CAPACITY_2GBIT, + SPD4_SDRAM_CAPACITY_4GBIT, + SPD4_SDRAM_CAPACITY_8GBIT, + SPD4_SDRAM_CAPACITY_16GBIT, + SPD4_SDRAM_CAPACITY_32GBIT, + SPD4_SDRAM_CAPACITY_12GBIT, + SPD4_SDRAM_CAPACITY_24GBIT, + SPD4_SDRAM_CAPACITY_INVALID =3D 0xFF, +}; + +struct SPD4_SDRAM_CAPACITY_TABLE { + enum SPD4_SDRAM_CAPACITY Capacity; + UINT16 SizeMbit; +}; + +STATIC CONST struct SPD4_SDRAM_CAPACITY_TABLE CapacityTable[] =3D { + {SPD4_SDRAM_CAPACITY_256MBIT, 256 }, + {SPD4_SDRAM_CAPACITY_512MBIT, 512 }, + {SPD4_SDRAM_CAPACITY_1GBIT, (1 * 1024) }, + {SPD4_SDRAM_CAPACITY_2GBIT, (2 * 1024) }, + {SPD4_SDRAM_CAPACITY_4GBIT, (4 * 1024) }, + {SPD4_SDRAM_CAPACITY_8GBIT, (8 * 1024) }, + {SPD4_SDRAM_CAPACITY_16GBIT, (16 * 1024)}, + {SPD4_SDRAM_CAPACITY_32GBIT, (32 * 1024)}, + {SPD4_SDRAM_CAPACITY_12GBIT, (12 * 1024)}, + {SPD4_SDRAM_CAPACITY_24GBIT, (24 * 1024)}, + {SPD4_SDRAM_CAPACITY_INVALID, 0 }, +}; + // BIOS information (section 7.1) STATIC CONST ARM_TYPE0 mArmDefaultType0 =3D { { @@ -394,123 +488,6 @@ STATIC CONST ARM_TYPE16 mArmDefaultType16 =3D { } }; =20 -// Memory device -STATIC CONST ARM_TYPE17 mArmDefaultType17_1 =3D { - { - { // SMBIOS_STRUCTURE Hdr - EFI_SMBIOS_TYPE_MEMORY_DEVICE, - sizeof (SMBIOS_TABLE_TYPE17), - SMBIOS_HANDLE_PI_RESERVED, - }, - SMBIOS_HANDLE_MEMORY, // array to which this module belongs - 0xFFFE, // no errors - 72, // single DIMM with ECC - 64, // data width of this device (64-bits) - 0xFFFF, // size unknown - 0x09, // DIMM - 1, // part of a set - 1, // device locator - 0, // bank locator - MemoryTypeDdr4, // DDR4 - {}, // type detail - 0, // ? MHz - 0, // manufacturer - 0, // serial - 0, // asset tag - 0, // part number - 0, // rank - }, { - "DIMM1\0" - } -}; - -STATIC CONST ARM_TYPE17 mArmDefaultType17_2 =3D { - { - { // SMBIOS_STRUCTURE Hdr - EFI_SMBIOS_TYPE_MEMORY_DEVICE, - sizeof (SMBIOS_TABLE_TYPE17), - SMBIOS_HANDLE_PI_RESERVED, - }, - SMBIOS_HANDLE_MEMORY, // array to which this module belongs - 0xFFFE, // no errors - 72, // single DIMM with ECC - 64, // data width of this device (64-bits) - 0xFFFF, // size unknown - 0x09, // DIMM - 1, // part of a set - 1, // device locator - 0, // bank locator - MemoryTypeDdr4, // DDR4 - {}, // type detail - 0, // ? MHz - 0, // manufacturer - 0, // serial - 0, // asset tag - 0, // part number - 0, // rank - }, { - "DIMM2\0" - } -}; - -STATIC CONST ARM_TYPE17 mArmDefaultType17_3 =3D { - { - { // SMBIOS_STRUCTURE Hdr - EFI_SMBIOS_TYPE_MEMORY_DEVICE, - sizeof (SMBIOS_TABLE_TYPE17), - SMBIOS_HANDLE_PI_RESERVED, - }, - SMBIOS_HANDLE_MEMORY, // array to which this module belongs - 0xFFFE, // no errors - 72, // single DIMM with ECC - 64, // data width of this device (64-bits) - 0xFFFF, // size unknown - 0x09, // DIMM - 1, // part of a set - 1, // device locator - 0, // bank locator - MemoryTypeDdr4, // DDR4 - {}, // type detail - 0, // ? MHz - 0, // manufacturer - 0, // serial - 0, // asset tag - 0, // part number - 0, // rank - }, { - "DIMM3\0" - } -}; - -STATIC CONST ARM_TYPE17 mArmDefaultType17_4 =3D { - { - { // SMBIOS_STRUCTURE Hdr - EFI_SMBIOS_TYPE_MEMORY_DEVICE, - sizeof (SMBIOS_TABLE_TYPE17), - SMBIOS_HANDLE_PI_RESERVED, - }, - SMBIOS_HANDLE_MEMORY, // array to which this module belongs - 0xFFFE, // no errors - 72, // single DIMM with ECC - 64, // data width of this device (64-bits) - 0xFFFF, // size unknown - 0x09, // DIMM - 1, // part of a set - 1, // device locator - 0, // bank locator - MemoryTypeDdr4, // DDR4 - {}, // type detail - 0, // ? MHz - 0, // manufacturer - 0, // serial - 0, // asset tag - 0, // part number - 0, // rank - }, { - "DIMM4\0" - } -}; - // Memory array mapped address, this structure // is overridden by InstallMemoryStructure STATIC CONST ARM_TYPE19 mArmDefaultType19 =3D { @@ -559,13 +536,275 @@ STATIC SMBIOS_STRUCTURE * CONST FixedTables[] =3D { (SMBIOS_STRUCTURE *)&mArmDefaultType9_1.Base.Hdr, (SMBIOS_STRUCTURE *)&mArmDefaultType9_2.Base.Hdr, (SMBIOS_STRUCTURE *)&mArmDefaultType16.Base.Hdr, - (SMBIOS_STRUCTURE *)&mArmDefaultType17_1.Base.Hdr, - (SMBIOS_STRUCTURE *)&mArmDefaultType17_2.Base.Hdr, - (SMBIOS_STRUCTURE *)&mArmDefaultType17_3.Base.Hdr, - (SMBIOS_STRUCTURE *)&mArmDefaultType17_4.Base.Hdr, (SMBIOS_STRUCTURE *)&mArmDefaultType32.Base.Hdr, }; =20 +STATIC +UINT16 +GetPrimaryBusWidth ( + IN UINT8 SpdPrimaryBusWidth + ) +{ + UINT16 PrimaryBusWidth; + + switch (SpdPrimaryBusWidth) { + case SPD4_MEM_BUS_WIDTH_8BIT: + PrimaryBusWidth =3D 8; + break; + case SPD4_MEM_BUS_WIDTH_16BIT: + PrimaryBusWidth =3D 16; + break; + case SPD4_MEM_BUS_WIDTH_32BIT: + PrimaryBusWidth =3D 32; + break; + case SPD4_MEM_BUS_WIDTH_64BIT: + PrimaryBusWidth =3D 64; + break; + default: + PrimaryBusWidth =3D 0xFFFF; + break; + } + + return PrimaryBusWidth; +} + +STATIC +UINT16 +GetSdramDeviceWidth ( + IN UINT8 SpdSdramDeviceWidth + ) +{ + UINT16 SdramDeviceWidth; + + switch (SpdSdramDeviceWidth) { + case SPD4_MEM_DEV_WIDTH_4BIT: + SdramDeviceWidth =3D 4; + break; + case SPD4_MEM_DEV_WIDTH_8BIT: + SdramDeviceWidth =3D 8; + break; + case SPD4_MEM_DEV_WIDTH_16BIT: + SdramDeviceWidth =3D 16; + break; + case SPD4_MEM_DEV_WIDTH_32BIT: + SdramDeviceWidth =3D 32; + break; + default: + SdramDeviceWidth =3D 0; + break; + } + + return SdramDeviceWidth; +} + +STATIC +UINT16 +CaluculateModuleDramCapacityMB ( + IN SPD4_BASE_SECTION *Spd4Base + ) +{ + UINT32 SdramCapacityMbit =3D 0; + UINT16 PrimaryBusWidth =3D 0; + UINT8 SdramDeviceWidth =3D 0; + UINT8 RankCount =3D 0; + UINT16 DramSize; + UINT32 i; + + for (i =3D 0; CapacityTable[i].Capacity !=3D SPD4_SDRAM_CAPACITY_INVALID= ; i++) { + if (Spd4Base->SdramDensityAndBanks.Bits.Density =3D=3D CapacityTable[i= ].Capacity) { + SdramCapacityMbit =3D CapacityTable[i].SizeMbit; + break; + } + } + + PrimaryBusWidth =3D GetPrimaryBusWidth (Spd4Base->ModuleMemoryBusWidth.B= its.PrimaryBusWidth); + SdramDeviceWidth =3D GetSdramDeviceWidth (Spd4Base->ModuleOrganization.B= its.SdramDeviceWidth); + RankCount =3D Spd4Base->ModuleOrganization.Bits.RankCount + 1; + + if ((SdramCapacityMbit =3D=3D 0) || (PrimaryBusWidth =3D=3D 0xFFFF) || + (SdramDeviceWidth =3D=3D 0) || RankCount =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "Calculate DRAM size failed. Cap:%d, BusWidth:%d,= " + "DevWidth:%d, Rank:%d\n", SdramCapacityMbit, + PrimaryBusWidth, SdramDeviceWidth, RankCount)); + return 0xFFFF; + } + + // + //Total[MB] =3D SDRAM Capacity[Mb] / 8 * Primary Bus Width / + // SDRAM Width * Logical Ranks per DIMM + // + DramSize =3D (((SdramCapacityMbit >> 3) * PrimaryBusWidth) / SdramDevice= Width) * RankCount; + + return DramSize; +} + +STATIC +VOID +GetManufacturerName ( + IN UINT16 SpdManufacturerId, + OUT CHAR8 *ManufacturerStr + ) +{ + UINT16 ManufacturerId; + UINT32 i; + + ManufacturerId =3D SwapBytes16 (SpdManufacturerId); + ManufacturerId &=3D 0x7FFF; // ignore odd parity bit + + for (i =3D 0; Manufacturer[i].ManufacturerId !=3D 0xFFFF; i++) { + if (ManufacturerId =3D=3D Manufacturer[i].ManufacturerId) { + AsciiStrCpyS (ManufacturerStr, TYPE17_MANUFACTURER_NAME_LEN, + Manufacturer[i].ManufacturerName); + return; + } + } + + AsciiStrCpyS (ManufacturerStr, TYPE17_MANUFACTURER_NAME_LEN, + Manufacturer[i].ManufacturerName); +} + +STATIC +EFI_STATUS +InstallMemoryDeviceStructure ( + VOID + ) +{ + EFI_SMBIOS_HANDLE SmbiosHandle; + ARM_TYPE17 *Descriptor; + SPD_DDR4 *Spd; + UINT8 Slot; + + CHAR8 DeviceLocatorStr[TYPE17_DEVICE_LOCATOR_LEN] = =3D {0}; + CHAR8 BankLocatorStr[TYPE17_BANK_LOCATOR_LEN] =3D {0= }; + CHAR8 ManufacturerStr[TYPE17_MANUFACTURER_NAME_LEN] = =3D {0}; + CHAR8 SerialNumberStr[TYPE17_SERIAL_NUMBER_LEN] =3D = {0}; + CHAR8 AssetTagStr[] =3D "Unknown\0"; + CHAR8 PartNumberStr[TYPE17_MODULE_PART_NUMBER_LEN] = =3D {0}; + + Descriptor =3D AllocateZeroPool(sizeof (ARM_TYPE17)); + if (Descriptor =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Spd =3D (SPD_DDR4 *) FixedPcdGet32 (PcdSmbiosStoredSpdDDR4Address); + + for (Slot =3D 0; Slot < 4; Slot++, Spd++) { + SetMem (Descriptor, sizeof (ARM_TYPE17), 0); + // fill fixed parameters + Descriptor->Base.Hdr.Type =3D EFI_SMBIOS_TYPE_MEMORY_DEVICE; + Descriptor->Base.Hdr.Length =3D sizeof (SMBIOS_TABLE_TYPE17); + Descriptor->Base.Hdr.Handle =3D SMBIOS_HANDLE_PI_RESERVED; + Descriptor->Base.MemoryArrayHandle =3D SMBIOS_HANDLE_MEMORY; + Descriptor->Base.MemoryErrorInformationHandle =3D 0xFFFE; + Descriptor->Base.DeviceSet =3D 1; + Descriptor->Base.MemoryType =3D MemoryTypeDdr4; + Descriptor->Base.DeviceLocator =3D 1; + Descriptor->Base.BankLocator =3D 2; + Descriptor->Base.Manufacturer =3D 3; + Descriptor->Base.SerialNumber =3D 4; + Descriptor->Base.AssetTag =3D 5; + Descriptor->Base.PartNumber =3D 6; + + if (Spd->Base.Description.Data =3D=3D 0) { + // No DIMM inserted, fill the default parameters + CHAR8 DefaultStrings[] =3D "NO DIMM\0NO DIMM\0NO DIM= M\0NO DIMM\0NO DIMM\0"; + UINT8 DefaultStringsLen =3D 40; + + Descriptor->Base.TotalWidth =3D 0xFFFF; + Descriptor->Base.DataWidth =3D 0xFFFF; + Descriptor->Base.Size =3D 0; + Descriptor->Base.FormFactor =3D 0x09; + Descriptor->Base.DeviceSet =3D 1; + + Descriptor->Base.Attributes =3D 0; + Descriptor->Base.Speed =3D 0; + Descriptor->Base.ConfiguredMemoryClockSpeed =3D 0; + Descriptor->Base.MinimumVoltage =3D 0; + Descriptor->Base.MaximumVoltage =3D 0; + Descriptor->Base.ConfiguredVoltage =3D 0; + + AsciiSPrint (Descriptor->Strings, TYPE17_STRINGS_MAX_LEN, "DIMM %d\0= ", (Slot + 1)); + CopyMem ((Descriptor->Strings + (AsciiStrLen(Descriptor->Strings) + = 1)), + DefaultStrings, DefaultStringsLen); + } else { + CHAR8 *Temp; + + Descriptor->Base.TotalWidth =3D Descriptor->Base.DataWidth =3D + GetPrimaryBusWidth (Spd->Base.ModuleMemoryBusWidth.Bits.PrimaryBus= Width); + if (Spd->Base.ModuleMemoryBusWidth.Bits.BusWidthExtension) { + if (Descriptor->Base.TotalWidth !=3D 0xFFFF) { + Descriptor->Base.TotalWidth +=3D 8; + } + } + + Descriptor->Base.Size =3D CaluculateModuleDramCapacityMB ((SPD4_BASE= _SECTION *)Spd); + + switch (Spd->Base.ModuleType.Bits.ModuleType) { + case SPD4_MEM_MODULE_TYPE_RDIMM: + Descriptor->Base.FormFactor =3D 0x09; + Descriptor->Base.TypeDetail.Registered =3D 1; + Descriptor->Base.TypeDetail.Unbuffered =3D 0; + break; + case SPD4_MEM_MODULE_TYPE_UDIMM: + Descriptor->Base.FormFactor =3D 0x09; + Descriptor->Base.TypeDetail.Registered =3D 0; + Descriptor->Base.TypeDetail.Unbuffered =3D 1; + break; + case SPD4_MEM_MODULE_TYPE_SODIMM: + Descriptor->Base.FormFactor =3D 0x0D; + Descriptor->Base.TypeDetail.Registered =3D 0; + Descriptor->Base.TypeDetail.Unbuffered =3D 1; + break; + default: + Descriptor->Base.FormFactor =3D 0x01; + Descriptor->Base.TypeDetail.Registered =3D 0; + Descriptor->Base.TypeDetail.Unbuffered =3D 0; + break; + } + + Descriptor->Base.Attributes =3D Spd->Base.ModuleOrganization.Bits.Ra= nkCount + 1; + Descriptor->Base.Speed =3D 2133; + Descriptor->Base.ConfiguredMemoryClockSpeed =3D 2133; + Descriptor->Base.MinimumVoltage =3D 1200; + Descriptor->Base.MaximumVoltage =3D 1200; + Descriptor->Base.ConfiguredVoltage =3D 1200; + + AsciiSPrint (DeviceLocatorStr, sizeof(DeviceLocatorStr), "DIMM %d\0"= , (Slot + 1)); + AsciiSPrint (BankLocatorStr, sizeof(BankLocatorStr), "CHANNEL %d SLO= T %d\0", (Slot / 2), (Slot % 2)); + GetManufacturerName (Spd->ManufactureInfo.ModuleId.IdCode.Data, Manu= facturerStr); + AsciiSPrint (SerialNumberStr, TYPE17_SERIAL_NUMBER_LEN, "0x%08X\0", + SwapBytes32(Spd->ManufactureInfo.ModuleId.SerialNumber.= Data)); + // + // Module part number is not null terminated string in SPD DDR4, + // unused bytes are filled with 0x20(space). + // + CopyMem (PartNumberStr, + (CHAR8 *)Spd->ManufactureInfo.ModulePartNumber.ModulePartNu= mber, + TYPE17_MODULE_PART_NUMBER_LEN - 1); + + Temp =3D Descriptor->Strings; + AsciiStrnCpy (Temp, DeviceLocatorStr, TYPE17_DEVICE_LOCATOR_LEN); + Temp +=3D (AsciiStrLen (DeviceLocatorStr) + 1); + AsciiStrnCpy (Temp, BankLocatorStr, TYPE17_BANK_LOCATOR_LEN); + Temp +=3D (AsciiStrLen (BankLocatorStr) + 1); + AsciiStrnCpy (Temp, ManufacturerStr, TYPE17_MANUFACTURER_NAME_LEN); + Temp +=3D (AsciiStrLen (ManufacturerStr) + 1); + AsciiStrnCpy (Temp, SerialNumberStr, TYPE17_SERIAL_NUMBER_LEN); + Temp +=3D (AsciiStrLen (SerialNumberStr) + 1); + AsciiStrnCpy (Temp, AssetTagStr, TYPE17_ASSETTAG_LEN); + Temp +=3D (AsciiStrLen (AssetTagStr) + 1); + AsciiStrnCpy (Temp, PartNumberStr, TYPE17_MODULE_PART_NUMBER_LEN); + } + + SmbiosHandle =3D Descriptor->Base.Hdr.Handle; + mSmbios->Add (mSmbios, NULL, &SmbiosHandle, &Descriptor->Base.Hdr); + } + + FreePool (Descriptor); + + return EFI_SUCCESS; +} + STATIC EFI_STATUS InstallMemoryStructure ( @@ -587,6 +826,7 @@ InstallMemoryStructure ( return mSmbios->Add (mSmbios, NULL, &SmbiosHandle, &Descriptor->Base.Hdr= ); } =20 + STATIC VOID InstallAllStructures ( @@ -608,6 +848,16 @@ InstallAllStructures ( } } =20 + // + // SPD_DDR4 data is stored in Non Secure SRAM by SCP-firmware. + // Install Type17 record by analyzing SPD_DDR4 information. + // + Status =3D InstallMemoryDeviceStructure(); + if (EFI_ERROR(Status)) { + DEBUG ((DEBUG_WARN, "%a: failed to add SMBIOS type 17 table - %r\n", + __FUNCTION__, Status)); + } + for (Hob.Raw =3D GetHobList (); !END_OF_HOB_LIST (Hob); Hob.Raw =3D GET_NEXT_HOB (Hob)) { diff --git a/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatfo= rmDxe.inf b/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatfor= mDxe.inf index e711cbf6dc..abd4602e34 100644 --- a/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.i= nf +++ b/Platform/Socionext/DeveloperBox/SmbiosPlatformDxe/SmbiosPlatformDxe.i= nf @@ -21,6 +21,7 @@ ArmPkg/ArmPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec =20 [LibraryClasses] BaseMemoryLib @@ -34,6 +35,7 @@ [FixedPcd] gArmTokenSpaceGuid.PcdFdSize gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision + gSynQuacerTokenSpaceGuid.PcdSmbiosStoredSpdDDR4Address =20 [Protocols] gEfiSmbiosProtocolGuid # PROTOCOL ALWAYS_CONSUMED diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/= SynQuacer/SynQuacer.dec index e7197e2319..98b574bd32 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -43,6 +43,9 @@ # for capsule update gSynQuacerTokenSpaceGuid.PcdLowestSupportedFirmwareVersion|1|UINT32|0x00= 000009 =20 + # for SMBIOS Type17 + gSynQuacerTokenSpaceGuid.PcdSmbiosStoredSpdDDR4Address|0|UINT32|0x000000= 0A + [PcdsPatchableInModule, PcdsDynamic] # Enable both RC #0 and RC #1 by default gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x3|UINT8|0x00000007 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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