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X-ExtLoop1: 1 X-Received: from lgao4-mobl1.ccr.corp.intel.com ([10.255.29.227]) by FMSMGA003.fm.intel.com with ESMTP; 10 Jun 2019 08:36:48 -0700 From: "Liming Gao" To: devel@edk2.groups.io Cc: Michael D Kinney , Ray Ni , Rangasai V Chaganty Subject: [edk2-devel] [edk2-platform patch 1/2] Silicon/Intel: Import IntelSiliconPkg from edk2 repo master Date: Mon, 10 Jun 2019 23:36:26 +0800 Message-Id: <20190610153627.16864-2-liming.gao@intel.com> In-Reply-To: <20190610153627.16864-1-liming.gao@intel.com> References: <20190610153627.16864-1-liming.gao@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,liming.gao@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1560181015; bh=BjJwjyiIo46IWlFcw+KYELzlgIQ8cDFmTHlab4wWef4=; h=Cc:Date:From:Reply-To:Subject:To; b=iJbbKZnBlTW7TjoefJncGwpCYMDHs8sy0HLwV24ggWQlkENw6IR8Z0tUBuOZsUAUKMQ 5mS5kWxLWpJ3Z5WQ/SlpMnAP3s/K2dUtsxL68wzkoZDKCSUCpkhtMHfNFbYeHJNkRXoPR Xd/T3kvTMsuYKfEA6cz4U4vOak4EVE9nFiA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1890 Signed-off-by: Liming Gao Cc: Michael D Kinney Cc: Ray Ni Cc: Rangasai V Chaganty Reviewed-by: Ray Ni Reviewed-by: Sai Chaganty =20 --- .../MicrocodeFlashAccessLibNull.c | 36 + .../Capsule/MicrocodeUpdateDxe/MicrocodeFmp.c | 979 +++++++++++++++ .../Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.c | 1326 ++++++++++++++++= ++++ .../Feature/VTd/IntelVTdDxe/BmDma.c | 538 ++++++++ .../Feature/VTd/IntelVTdDxe/DmaProtection.c | 683 ++++++++++ .../Feature/VTd/IntelVTdDxe/DmarAcpiTable.c | 890 +++++++++++++ .../Feature/VTd/IntelVTdDxe/IntelVTdDxe.c | 400 ++++++ .../Feature/VTd/IntelVTdDxe/PciInfo.c | 373 ++++++ .../Feature/VTd/IntelVTdDxe/TranslationTable.c | 1026 +++++++++++++++ .../Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 152 +++ .../Feature/VTd/IntelVTdDxe/VtdReg.c | 561 +++++++++ .../Feature/VTd/IntelVTdPmrPei/DmarTable.c | 578 +++++++++ .../Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c | 420 +++++++ .../Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.c | 810 ++++++++++++ .../Feature/VTd/IntelVTdPmrPei/VtdReg.c | 287 +++++ .../PlatformVTdInfoSamplePei.c | 361 ++++++ .../PlatformVTdSampleDxe/PlatformVTdSampleDxe.c | 407 ++++++ .../DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.c | 81 ++ .../MicrocodeFlashAccessLibNull.inf | 34 + .../MicrocodeFlashAccessLibNull.uni | 16 + .../MicrocodeCapsulePdb/MicrocodeCapsulePdb.dsc | 27 + .../MicrocodeCapsulePdb/MicrocodeCapsulePdb.fdf | 26 + .../Feature/Capsule/MicrocodeCapsulePdb/Readme.md | 20 + .../MicrocodeCapsuleTxt/Microcode/Microcode.inf | 21 + .../MicrocodeCapsuleTxt/MicrocodeCapsuleTxt.dsc | 33 + .../MicrocodeCapsuleTxt/MicrocodeCapsuleTxt.fdf | 26 + .../Feature/Capsule/MicrocodeCapsuleTxt/Readme.md | 33 + .../Capsule/MicrocodeUpdateDxe/MicrocodeUpdate.h | 499 ++++++++ .../MicrocodeUpdateDxe/MicrocodeUpdateDxe.inf | 67 + .../MicrocodeUpdateDxe/MicrocodeUpdateDxe.uni | 15 + .../MicrocodeUpdateDxe/MicrocodeUpdateDxeExtra.uni | 14 + .../Feature/VTd/IntelVTdDxe/DmaProtection.h | 632 ++++++++++ .../Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf | 83 ++ .../Feature/VTd/IntelVTdDxe/IntelVTdDxe.uni | 14 + .../Feature/VTd/IntelVTdDxe/IntelVTdDxeExtra.uni | 14 + .../Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.h | 159 +++ .../Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf | 60 + .../Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.uni | 14 + .../VTd/IntelVTdPmrPei/IntelVTdPmrPeiExtra.uni | 14 + .../PlatformVTdInfoSamplePei.inf | 48 + .../PlatformVTdInfoSamplePei.uni | 14 + .../PlatformVTdInfoSamplePeiExtra.uni | 14 + .../PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf | 56 + .../PlatformVTdSampleDxe/PlatformVTdSampleDxe.uni | 14 + .../PlatformVTdSampleDxeExtra.uni | 14 + .../IntelSiliconPkg/Include/Guid/MicrocodeFmp.h | 15 + .../IndustryStandard/FirmwareInterfaceTable.h | 69 + .../Include/IndustryStandard/FirmwareVersionInfo.h | 54 + .../Include/IndustryStandard/IgdOpRegion.h | 149 +++ .../IntelSiliconPkg/Include/IndustryStandard/Vtd.h | 355 ++++++ .../Include/Library/MicrocodeFlashAccessLib.h | 33 + .../Intel/IntelSiliconPkg/Include/Ppi/VtdInfo.h | 37 + .../Include/Protocol/PlatformVtdPolicy.h | 143 +++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 80 ++ Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc | 86 ++ .../DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.inf | 38 + 56 files changed, 12948 insertions(+) create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/M= icrocodeFlashAccessLibNull/MicrocodeFlashAccessLibNull.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= UpdateDxe/MicrocodeFmp.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= UpdateDxe/MicrocodeUpdate.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/B= mDma.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/D= maProtection.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/D= marAcpiTable.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/I= ntelVTdDxe.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/P= ciInfo.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/T= ranslationTable.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/T= ranslationTableEx.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/V= tdReg.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPe= i/DmarTable.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPe= i/IntelVTdPmr.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPe= i/IntelVTdPmrPei.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPe= i/VtdReg.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdIn= foSamplePei/PlatformVTdInfoSamplePei.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSa= mpleDxe/PlatformVTdSampleDxe.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Library/DxeSmbiosDataHobL= ib/DxeSmbiosDataHobLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/M= icrocodeFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/M= icrocodeFlashAccessLibNull/MicrocodeFlashAccessLibNull.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= CapsulePdb/MicrocodeCapsulePdb.dsc create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= CapsulePdb/MicrocodeCapsulePdb.fdf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= CapsulePdb/Readme.md create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= CapsuleTxt/Microcode/Microcode.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= CapsuleTxt/MicrocodeCapsuleTxt.dsc create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= CapsuleTxt/MicrocodeCapsuleTxt.fdf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= CapsuleTxt/Readme.md create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= UpdateDxe/MicrocodeUpdate.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= UpdateDxe/MicrocodeUpdateDxe.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= UpdateDxe/MicrocodeUpdateDxe.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= UpdateDxe/MicrocodeUpdateDxeExtra.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/D= maProtection.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/I= ntelVTdDxe.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/I= ntelVTdDxe.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/I= ntelVTdDxeExtra.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPe= i/IntelVTdPmrPei.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPe= i/IntelVTdPmrPei.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPe= i/IntelVTdPmrPei.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPe= i/IntelVTdPmrPeiExtra.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdIn= foSamplePei/PlatformVTdInfoSamplePei.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdIn= foSamplePei/PlatformVTdInfoSamplePei.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdIn= foSamplePei/PlatformVTdInfoSamplePeiExtra.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSa= mpleDxe/PlatformVTdSampleDxe.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSa= mpleDxe/PlatformVTdSampleDxe.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSa= mpleDxe/PlatformVTdSampleDxeExtra.uni create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeFmp= .h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/= FirmwareInterfaceTable.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/= FirmwareVersionInfo.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/= IgdOpRegion.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/= Vtd.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/Microcode= FlashAccessLib.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Ppi/VtdInfo.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Protocol/Platform= VtdPolicy.h create mode 100644 Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec create mode 100644 Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc create mode 100644 Silicon/Intel/IntelSiliconPkg/Library/DxeSmbiosDataHobL= ib/DxeSmbiosDataHobLib.inf diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/Microcod= eFlashAccessLibNull/MicrocodeFlashAccessLibNull.c b/Silicon/Intel/IntelSili= conPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/MicrocodeFlashAc= cessLibNull.c new file mode 100644 index 0000000000..9fc10c398b --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashA= ccessLibNull/MicrocodeFlashAccessLibNull.c @@ -0,0 +1,36 @@ +/** @file + Microcode flash device access library NULL instance. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include + +/** + Perform microcode write opreation. + + @param[in] FlashAddress The address of flash device to be accessed. + @param[in] Buffer The pointer to the data buffer. + @param[in] Length The length of data buffer in bytes. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS +EFIAPI +MicrocodeFlashWrite ( + IN EFI_PHYSICAL_ADDRESS FlashAddress, + IN VOID *Buffer, + IN UINTN Length + ) +{ + CopyMem((VOID *)(UINTN)(FlashAddress), Buffer, Length); + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateD= xe/MicrocodeFmp.c b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microcode= UpdateDxe/MicrocodeFmp.c new file mode 100644 index 0000000000..40d302425d --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/Micr= ocodeFmp.c @@ -0,0 +1,979 @@ +/** @file + Produce FMP instance for Microcode. + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MicrocodeUpdate.h" + +// +// MicrocodeFmp driver private data +// +MICROCODE_FMP_PRIVATE_DATA *mMicrocodeFmpPrivate =3D NULL; + +EFI_FIRMWARE_MANAGEMENT_PROTOCOL mFirmwareManagementProtocol =3D { + FmpGetImageInfo, + FmpGetImage, + FmpSetImage, + FmpCheckImage, + FmpGetPackageInfo, + FmpSetPackageInfo +}; + +/** + Initialize Microcode Descriptor. + + @param[in] MicrocodeFmpPrivate private data structure to be initialized. + + @return EFI_SUCCESS Microcode Descriptor is initialized. +**/ +EFI_STATUS +InitializeMicrocodeDescriptor ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ); + +/** + Returns information about the current firmware image(s) of the device. + + This function allows a copy of the current firmware image to be created = and saved. + The saved copy could later been used, for example, in firmware image rec= overy or rollback. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEM= ENT_PROTOCOL instance. + @param[in, out] ImageInfoSize A pointer to the size, in bytes, of t= he ImageInfo buffer. + On input, this is the size of the buf= fer allocated by the caller. + On output, it is the size of the buff= er returned by the firmware + if the buffer was large enough, or th= e size of the buffer needed + to contain the image(s) information i= f the buffer was too small. + @param[in, out] ImageInfo A pointer to the buffer in which firm= ware places the current image(s) + information. The information is an ar= ray of EFI_FIRMWARE_IMAGE_DESCRIPTORs. + @param[out] DescriptorVersion A pointer to the location in which fi= rmware returns the version number + associated with the EFI_FIRMWARE_IMAG= E_DESCRIPTOR. + @param[out] DescriptorCount A pointer to the location in which fi= rmware returns the number of + descriptors or firmware images within= this device. + @param[out] DescriptorSize A pointer to the location in which fi= rmware returns the size, in bytes, + of an individual EFI_FIRMWARE_IMAGE_D= ESCRIPTOR. + @param[out] PackageVersion A version number that represents all = the firmware images in the device. + The format is vendor specific and new= version must have a greater value + than the old version. If PackageVersi= on is not supported, the value is + 0xFFFFFFFF. A value of 0xFFFFFFFE ind= icates that package version comparison + is to be performed using PackageVersi= onName. A value of 0xFFFFFFFD indicates + that package version update is in pro= gress. + @param[out] PackageVersionName A pointer to a pointer to a null-term= inated string representing the + package version name. The buffer is a= llocated by this function with + AllocatePool(), and it is the caller'= s responsibility to free it with a call + to FreePool(). + + @retval EFI_SUCCESS The device was successfully updated w= ith the new image. + @retval EFI_BUFFER_TOO_SMALL The ImageInfo buffer was too small. T= he current buffer size + needed to hold the image(s) informati= on is returned in ImageInfoSize. + @retval EFI_INVALID_PARAMETER ImageInfoSize is NULL. + @retval EFI_DEVICE_ERROR Valid information could not be return= ed. Possible corrupted image. + +**/ +EFI_STATUS +EFIAPI +FmpGetImageInfo ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN OUT UINTN *ImageInfoSize, + IN OUT EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageInfo, + OUT UINT32 *DescriptorVersion, + OUT UINT8 *DescriptorCount, + OUT UINTN *DescriptorSize, + OUT UINT32 *PackageVersion, + OUT CHAR16 **PackageVersionName + ) +{ + MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate; + UINTN Index; + + MicrocodeFmpPrivate =3D MICROCODE_FMP_PRIVATE_DATA_FROM_FMP(This); + + if(ImageInfoSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (*ImageInfoSize < sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR) * MicrocodeFm= pPrivate->DescriptorCount) { + *ImageInfoSize =3D sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR) * MicrocodeFm= pPrivate->DescriptorCount; + return EFI_BUFFER_TOO_SMALL; + } + + if (ImageInfo =3D=3D NULL || + DescriptorVersion =3D=3D NULL || + DescriptorCount =3D=3D NULL || + DescriptorSize =3D=3D NULL || + PackageVersion =3D=3D NULL || + PackageVersionName =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + *ImageInfoSize =3D sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR) * Microcod= eFmpPrivate->DescriptorCount; + *DescriptorSize =3D sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR); + *DescriptorCount =3D MicrocodeFmpPrivate->DescriptorCount; + *DescriptorVersion =3D EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION; + + // + // supports 1 ImageInfo descriptor + // + CopyMem(&ImageInfo[0], MicrocodeFmpPrivate->ImageDescriptor, sizeof(EFI_= FIRMWARE_IMAGE_DESCRIPTOR) * MicrocodeFmpPrivate->DescriptorCount); + for (Index =3D 0; Index < MicrocodeFmpPrivate->DescriptorCount; Index++)= { + if ((ImageInfo[Index].AttributesSetting & IMAGE_ATTRIBUTE_IN_USE) !=3D= 0) { + ImageInfo[Index].LastAttemptVersion =3D MicrocodeFmpPrivate->LastAtt= empt.LastAttemptVersion; + ImageInfo[Index].LastAttemptStatus =3D MicrocodeFmpPrivate->LastAtte= mpt.LastAttemptStatus; + } + } + + // + // package version + // + *PackageVersion =3D MicrocodeFmpPrivate->PackageVersion; + if (MicrocodeFmpPrivate->PackageVersionName !=3D NULL) { + *PackageVersionName =3D AllocateCopyPool(StrSize(MicrocodeFmpPrivate->= PackageVersionName), MicrocodeFmpPrivate->PackageVersionName); + } + + return EFI_SUCCESS; +} + +/** + Retrieves a copy of the current firmware image of the device. + + This function allows a copy of the current firmware image to be created = and saved. + The saved copy could later been used, for example, in firmware image rec= overy or rollback. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_= PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware = image(s) within the device. + The number is between 1 and DescriptorCou= nt. + @param[in,out] Image Points to the buffer where the current im= age is copied to. + @param[in,out] ImageSize On entry, points to the size of the buffe= r pointed to by Image, in bytes. + On return, points to the length of the im= age, in bytes. + + @retval EFI_SUCCESS The device was successfully updated with = the new image. + @retval EFI_BUFFER_TOO_SMALL The buffer specified by ImageSize is too = small to hold the + image. The current buffer size needed to = hold the image is returned + in ImageSize. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_NOT_FOUND The current image is not copied to the bu= ffer. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due = to an authentication failure. + +**/ +EFI_STATUS +EFIAPI +FmpGetImage ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + IN OUT VOID *Image, + IN OUT UINTN *ImageSize + ) +{ + MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate; + MICROCODE_INFO *MicrocodeInfo; + + if (Image =3D=3D NULL || ImageSize =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + MicrocodeFmpPrivate =3D MICROCODE_FMP_PRIVATE_DATA_FROM_FMP(This); + + if (ImageIndex =3D=3D 0 || ImageIndex > MicrocodeFmpPrivate->DescriptorC= ount || ImageSize =3D=3D NULL || Image =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + MicrocodeInfo =3D &MicrocodeFmpPrivate->MicrocodeInfo[ImageIndex - 1]; + + if (*ImageSize < MicrocodeInfo->TotalSize) { + *ImageSize =3D MicrocodeInfo->TotalSize; + return EFI_BUFFER_TOO_SMALL; + } + + *ImageSize =3D MicrocodeInfo->TotalSize; + CopyMem (Image, MicrocodeInfo->MicrocodeEntryPoint, MicrocodeInfo->Total= Size); + return EFI_SUCCESS; +} + +/** + Updates the firmware image of the device. + + This function updates the hardware with the new firmware image. + This function returns EFI_UNSUPPORTED if the firmware image is not updat= able. + If the firmware image is updatable, the function should perform the foll= owing minimal validations + before proceeding to do the firmware image update. + - Validate the image authentication if image has attribute + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED. The function returns + EFI_SECURITY_VIOLATION if the validation fails. + - Validate the image is a supported image for this device. The function = returns EFI_ABORTED if + the image is unsupported. The function can optionally provide more det= ailed information on + why the image is not a supported image. + - Validate the data from VendorCode if not null. Image validation must b= e performed before + VendorCode data validation. VendorCode data is ignored or considered i= nvalid if image + validation failed. The function returns EFI_ABORTED if the data is inv= alid. + + VendorCode enables vendor to implement vendor-specific firmware image up= date policy. Null if + the caller did not specify the policy or use the default policy. As an e= xample, vendor can implement + a policy to allow an option to force a firmware image update when the ab= ort reason is due to the new + firmware image version is older than the current firmware image version = or bad image checksum. + Sensitive operations such as those wiping the entire firmware image and = render the device to be + non-functional should be encoded in the image itself rather than passed = with the VendorCode. + AbortReason enables vendor to have the option to provide a more detailed= description of the abort + reason to the caller. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_= PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware = image(s) within the device. + The number is between 1 and DescriptorCou= nt. + @param[in] Image Points to the new image. + @param[in] ImageSize Size of the new image in bytes. + @param[in] VendorCode This enables vendor to implement vendor-s= pecific firmware image update policy. + Null indicates the caller did not specify= the policy or use the default policy. + @param[in] Progress A function used by the driver to report t= he progress of the firmware update. + @param[out] AbortReason A pointer to a pointer to a null-terminat= ed string providing more + details for the aborted operation. The bu= ffer is allocated by this function + with AllocatePool(), and it is the caller= 's responsibility to free it with a + call to FreePool(). + + @retval EFI_SUCCESS The device was successfully updated with = the new image. + @retval EFI_ABORTED The operation is aborted. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due = to an authentication failure. + +**/ +EFI_STATUS +EFIAPI +FmpSetImage ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + IN CONST VOID *Image, + IN UINTN ImageSize, + IN CONST VOID *VendorCode, + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, + OUT CHAR16 **AbortReason + ) +{ + EFI_STATUS Status; + EFI_STATUS VarStatus; + MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate; + + if (Image =3D=3D NULL || AbortReason =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + MicrocodeFmpPrivate =3D MICROCODE_FMP_PRIVATE_DATA_FROM_FMP(This); + *AbortReason =3D NULL; + + if (ImageIndex =3D=3D 0 || ImageIndex > MicrocodeFmpPrivate->DescriptorC= ount || Image =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Status =3D MicrocodeWrite(MicrocodeFmpPrivate, (VOID *)Image, ImageSize,= &MicrocodeFmpPrivate->LastAttempt.LastAttemptVersion, &MicrocodeFmpPrivate= ->LastAttempt.LastAttemptStatus, AbortReason); + DEBUG((DEBUG_INFO, "SetImage - LastAttempt Version - 0x%x, Status - 0x%x= \n", MicrocodeFmpPrivate->LastAttempt.LastAttemptVersion, MicrocodeFmpPriva= te->LastAttempt.LastAttemptStatus)); + VarStatus =3D gRT->SetVariable( + MICROCODE_FMP_LAST_ATTEMPT_VARIABLE_NAME, + &gEfiCallerIdGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_= ACCESS, + sizeof(MicrocodeFmpPrivate->LastAttempt), + &MicrocodeFmpPrivate->LastAttempt + ); + DEBUG((DEBUG_INFO, "SetLastAttempt - %r\n", VarStatus)); + + if (!EFI_ERROR(Status)) { + InitializeMicrocodeDescriptor(MicrocodeFmpPrivate); + DumpPrivateInfo (MicrocodeFmpPrivate); + } + + return Status; +} + +/** + Checks if the firmware image is valid for the device. + + This function allows firmware update application to validate the firmwar= e image without + invoking the SetImage() first. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_= PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware = image(s) within the device. + The number is between 1 and DescriptorCou= nt. + @param[in] Image Points to the new image. + @param[in] ImageSize Size of the new image in bytes. + @param[out] ImageUpdatable Indicates if the new image is valid for u= pdate. It also provides, + if available, additional information if t= he image is invalid. + + @retval EFI_SUCCESS The image was successfully checked. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due = to an authentication failure. + +**/ +EFI_STATUS +EFIAPI +FmpCheckImage ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + IN CONST VOID *Image, + IN UINTN ImageSize, + OUT UINT32 *ImageUpdatable + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Returns information about the firmware package. + + This function returns package information. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAG= EMENT_PROTOCOL instance. + @param[out] PackageVersion A version number that represents al= l the firmware images in the device. + The format is vendor specific and n= ew version must have a greater value + than the old version. If PackageVer= sion is not supported, the value is + 0xFFFFFFFF. A value of 0xFFFFFFFE i= ndicates that package version + comparison is to be performed using= PackageVersionName. A value of + 0xFFFFFFFD indicates that package v= ersion update is in progress. + @param[out] PackageVersionName A pointer to a pointer to a null-te= rminated string representing + the package version name. The buffe= r is allocated by this function with + AllocatePool(), and it is the calle= r's responsibility to free it with a + call to FreePool(). + @param[out] PackageVersionNameMaxLen The maximum length of package versi= on name if device supports update of + package version name. A value of 0 = indicates the device does not support + update of package version name. Len= gth is the number of Unicode characters, + including the terminating null char= acter. + @param[out] AttributesSupported Package attributes that are support= ed by this device. See 'Package Attribute + Definitions' for possible returned = values of this parameter. A value of 1 + indicates the attribute is supporte= d and the current setting value is + indicated in AttributesSetting. A v= alue of 0 indicates the attribute is not + supported and the current setting v= alue in AttributesSetting is meaningless. + @param[out] AttributesSetting Package attributes. See 'Package At= tribute Definitions' for possible returned + values of this parameter + + @retval EFI_SUCCESS The package information was success= fully returned. + @retval EFI_UNSUPPORTED The operation is not supported. + +**/ +EFI_STATUS +EFIAPI +FmpGetPackageInfo ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + OUT UINT32 *PackageVersion, + OUT CHAR16 **PackageVersionName, + OUT UINT32 *PackageVersionNameMaxLen, + OUT UINT64 *AttributesSupported, + OUT UINT64 *AttributesSetting + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Updates information about the firmware package. + + This function updates package information. + This function returns EFI_UNSUPPORTED if the package information is not = updatable. + VendorCode enables vendor to implement vendor-specific package informati= on update policy. + Null if the caller did not specify this policy or use the default policy. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_= PROTOCOL instance. + @param[in] Image Points to the authentication image. + Null if authentication is not required. + @param[in] ImageSize Size of the authentication image in bytes. + 0 if authentication is not required. + @param[in] VendorCode This enables vendor to implement vendor-s= pecific firmware + image update policy. + Null indicates the caller did not specify= this policy or use + the default policy. + @param[in] PackageVersion The new package version. + @param[in] PackageVersionName A pointer to the new null-terminated Unic= ode string representing + the package version name. + The string length is equal to or less tha= n the value returned in + PackageVersionNameMaxLen. + + @retval EFI_SUCCESS The device was successfully updated with = the new package + information. + @retval EFI_INVALID_PARAMETER The PackageVersionName length is longer t= han the value + returned in PackageVersionNameMaxLen. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due = to an authentication failure. + +**/ +EFI_STATUS +EFIAPI +FmpSetPackageInfo ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN CONST VOID *Image, + IN UINTN ImageSize, + IN CONST VOID *VendorCode, + IN UINT32 PackageVersion, + IN CONST CHAR16 *PackageVersionName + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Sort FIT microcode entries based upon MicrocodeEntryPoint, from low to h= igh. + + @param[in] MicrocodeFmpPrivate private data structure to be initialized. + +**/ +VOID +SortFitMicrocodeInfo ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ) +{ + FIT_MICROCODE_INFO *FitMicrocodeEntry; + FIT_MICROCODE_INFO *NextFitMicrocodeEntry; + FIT_MICROCODE_INFO TempFitMicrocodeEntry; + FIT_MICROCODE_INFO *FitMicrocodeEntryEnd; + + FitMicrocodeEntry =3D MicrocodeFmpPrivate->FitMicrocodeInfo; + NextFitMicrocodeEntry =3D FitMicrocodeEntry + 1; + FitMicrocodeEntryEnd =3D MicrocodeFmpPrivate->FitMicrocodeInfo + Microco= deFmpPrivate->FitMicrocodeEntryCount; + while (FitMicrocodeEntry < FitMicrocodeEntryEnd) { + while (NextFitMicrocodeEntry < FitMicrocodeEntryEnd) { + if (FitMicrocodeEntry->MicrocodeEntryPoint > NextFitMicrocodeEntry->= MicrocodeEntryPoint) { + CopyMem (&TempFitMicrocodeEntry, FitMicrocodeEntry, sizeof (FIT_MI= CROCODE_INFO)); + CopyMem (FitMicrocodeEntry, NextFitMicrocodeEntry, sizeof (FIT_MIC= ROCODE_INFO)); + CopyMem (NextFitMicrocodeEntry, &TempFitMicrocodeEntry, sizeof (FI= T_MICROCODE_INFO)); + } + + NextFitMicrocodeEntry =3D NextFitMicrocodeEntry + 1; + } + + FitMicrocodeEntry =3D FitMicrocodeEntry + 1; + NextFitMicrocodeEntry =3D FitMicrocodeEntry + 1; + } +} + +/** + Initialize FIT microcode information. + + @param[in] MicrocodeFmpPrivate private data structure to be initialized. + + @return EFI_SUCCESS FIT microcode information is initialized. + @return EFI_OUT_OF_RESOURCES No enough resource for the initialization. + @return EFI_DEVICE_ERROR There is something wrong in FIT microcode = entry. +**/ +EFI_STATUS +InitializeFitMicrocodeInfo ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ) +{ + UINT64 FitPointer; + FIRMWARE_INTERFACE_TABLE_ENTRY *FitEntry; + UINT32 EntryNum; + UINT32 MicrocodeEntryNum; + UINT32 Index; + UINTN Address; + VOID *MicrocodePatchAddress; + UINTN MicrocodePatchRegionSize; + FIT_MICROCODE_INFO *FitMicrocodeInfo; + FIT_MICROCODE_INFO *FitMicrocodeInfoNext; + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + CPU_MICROCODE_HEADER *MicrocodeEntryPointNext; + UINTN FitMicrocodeIndex; + MICROCODE_INFO *MicrocodeInfo; + UINTN MicrocodeIndex; + + if (MicrocodeFmpPrivate->FitMicrocodeInfo !=3D NULL) { + FreePool (MicrocodeFmpPrivate->FitMicrocodeInfo); + MicrocodeFmpPrivate->FitMicrocodeInfo =3D NULL; + MicrocodeFmpPrivate->FitMicrocodeEntryCount =3D 0; + } + + FitPointer =3D *(UINT64 *) (UINTN) FIT_POINTER_ADDRESS; + if ((FitPointer =3D=3D 0) || + (FitPointer =3D=3D 0xFFFFFFFFFFFFFFFF) || + (FitPointer =3D=3D 0xEEEEEEEEEEEEEEEE)) { + // + // No FIT table. + // + return EFI_SUCCESS; + } + FitEntry =3D (FIRMWARE_INTERFACE_TABLE_ENTRY *) (UINTN) FitPointer; + if ((FitEntry[0].Type !=3D FIT_TYPE_00_HEADER) || + (FitEntry[0].Address !=3D FIT_TYPE_00_SIGNATURE)) { + // + // Invalid FIT table, treat it as no FIT table. + // + return EFI_SUCCESS; + } + + EntryNum =3D *(UINT32 *)(&FitEntry[0].Size[0]) & 0xFFFFFF; + + // + // Calculate microcode entry number. + // + MicrocodeEntryNum =3D 0; + for (Index =3D 0; Index < EntryNum; Index++) { + if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) { + MicrocodeEntryNum++; + } + } + if (MicrocodeEntryNum =3D=3D 0) { + // + // No FIT microcode entry. + // + return EFI_SUCCESS; + } + + // + // Allocate buffer. + // + MicrocodeFmpPrivate->FitMicrocodeInfo =3D AllocateZeroPool (MicrocodeEnt= ryNum * sizeof (FIT_MICROCODE_INFO)); + if (MicrocodeFmpPrivate->FitMicrocodeInfo =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + MicrocodeFmpPrivate->FitMicrocodeEntryCount =3D MicrocodeEntryNum; + + MicrocodePatchAddress =3D MicrocodeFmpPrivate->MicrocodePatchAddress; + MicrocodePatchRegionSize =3D MicrocodeFmpPrivate->MicrocodePatchRegionSi= ze; + + // + // Collect microcode entry info. + // + MicrocodeEntryNum =3D 0; + for (Index =3D 0; Index < EntryNum; Index++) { + if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) { + Address =3D (UINTN) FitEntry[Index].Address; + if ((Address < (UINTN) MicrocodePatchAddress) || + (Address >=3D ((UINTN) MicrocodePatchAddress + MicrocodePatchReg= ionSize))) { + DEBUG (( + DEBUG_ERROR, + "InitializeFitMicrocodeInfo - Address (0x%x) is not in Microcode= Region\n", + Address + )); + goto ErrorExit; + } + FitMicrocodeInfo =3D &MicrocodeFmpPrivate->FitMicrocodeInfo[Microcod= eEntryNum]; + FitMicrocodeInfo->MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) A= ddress; + if ((*(UINT32 *) Address) =3D=3D 0xFFFFFFFF) { + // + // It is the empty slot as long as the first dword is 0xFFFF_FFFF. + // + FitMicrocodeInfo->Empty =3D TRUE; + } else { + FitMicrocodeInfo->Empty =3D FALSE; + } + MicrocodeEntryNum++; + } + } + + // + // Every microcode should have a FIT microcode entry. + // + for (MicrocodeIndex =3D 0; MicrocodeIndex < MicrocodeFmpPrivate->Descrip= torCount; MicrocodeIndex++) { + MicrocodeInfo =3D &MicrocodeFmpPrivate->MicrocodeInfo[MicrocodeIndex]; + for (FitMicrocodeIndex =3D 0; FitMicrocodeIndex < MicrocodeFmpPrivate-= >FitMicrocodeEntryCount; FitMicrocodeIndex++) { + FitMicrocodeInfo =3D &MicrocodeFmpPrivate->FitMicrocodeInfo[FitMicro= codeIndex]; + if (MicrocodeInfo->MicrocodeEntryPoint =3D=3D FitMicrocodeInfo->Micr= ocodeEntryPoint) { + FitMicrocodeInfo->TotalSize =3D MicrocodeInfo->TotalSize; + FitMicrocodeInfo->InUse =3D MicrocodeInfo->InUse; + break; + } + } + if (FitMicrocodeIndex >=3D MicrocodeFmpPrivate->FitMicrocodeEntryCount= ) { + DEBUG (( + DEBUG_ERROR, + "InitializeFitMicrocodeInfo - There is no FIT microcode entry for = Microcode (0x%x)\n", + MicrocodeInfo->MicrocodeEntryPoint + )); + goto ErrorExit; + } + } + + SortFitMicrocodeInfo (MicrocodeFmpPrivate); + + // + // Check overlap. + // + for (FitMicrocodeIndex =3D 0; FitMicrocodeIndex < MicrocodeFmpPrivate->F= itMicrocodeEntryCount - 1; FitMicrocodeIndex++) { + FitMicrocodeInfo =3D &MicrocodeFmpPrivate->FitMicrocodeInfo[FitMicroco= deIndex]; + MicrocodeEntryPoint =3D FitMicrocodeInfo->MicrocodeEntryPoint; + FitMicrocodeInfoNext =3D &MicrocodeFmpPrivate->FitMicrocodeInfo[FitMic= rocodeIndex + 1]; + MicrocodeEntryPointNext =3D FitMicrocodeInfoNext->MicrocodeEntryPoint; + if ((MicrocodeEntryPoint >=3D MicrocodeEntryPointNext) || + ((FitMicrocodeInfo->TotalSize !=3D 0) && + ((UINTN) MicrocodeEntryPoint + FitMicrocodeInfo->TotalSize) > + (UINTN) MicrocodeEntryPointNext)) { + DEBUG (( + DEBUG_ERROR, + "InitializeFitMicrocodeInfo - There is overlap between FIT microco= de entries (0x%x 0x%x)\n", + MicrocodeEntryPoint, + MicrocodeEntryPointNext + )); + goto ErrorExit; + } + } + + return EFI_SUCCESS; + +ErrorExit: + FreePool (MicrocodeFmpPrivate->FitMicrocodeInfo); + MicrocodeFmpPrivate->FitMicrocodeInfo =3D NULL; + MicrocodeFmpPrivate->FitMicrocodeEntryCount =3D 0; + return EFI_DEVICE_ERROR; +} + +/** + Initialize Processor Microcode Index. + + @param[in] MicrocodeFmpPrivate private data structure to be initialized. +**/ +VOID +InitializedProcessorMicrocodeIndex ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ) +{ + UINTN CpuIndex; + UINTN MicrocodeIndex; + UINTN TargetCpuIndex; + UINT32 AttemptStatus; + EFI_STATUS Status; + + for (CpuIndex =3D 0; CpuIndex < MicrocodeFmpPrivate->ProcessorCount; Cpu= Index++) { + if (MicrocodeFmpPrivate->ProcessorInfo[CpuIndex].MicrocodeIndex !=3D (= UINTN)-1) { + continue; + } + for (MicrocodeIndex =3D 0; MicrocodeIndex < MicrocodeFmpPrivate->Descr= iptorCount; MicrocodeIndex++) { + if (!MicrocodeFmpPrivate->MicrocodeInfo[MicrocodeIndex].InUse) { + continue; + } + TargetCpuIndex =3D CpuIndex; + Status =3D VerifyMicrocode( + MicrocodeFmpPrivate, + MicrocodeFmpPrivate->MicrocodeInfo[MicrocodeIndex].Microc= odeEntryPoint, + MicrocodeFmpPrivate->MicrocodeInfo[MicrocodeIndex].TotalS= ize, + FALSE, + &AttemptStatus, + NULL, + &TargetCpuIndex + ); + if (!EFI_ERROR(Status)) { + MicrocodeFmpPrivate->ProcessorInfo[CpuIndex].MicrocodeIndex =3D Mi= crocodeIndex; + } + } + } +} + +/** + Initialize Microcode Descriptor. + + @param[in] MicrocodeFmpPrivate private data structure to be initialized. + + @return EFI_SUCCESS Microcode Descriptor is initialized. + @return EFI_OUT_OF_RESOURCES No enough resource for the initialization. +**/ +EFI_STATUS +InitializeMicrocodeDescriptor ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ) +{ + EFI_STATUS Status; + UINT8 CurrentMicrocodeCount; + + CurrentMicrocodeCount =3D (UINT8)GetMicrocodeInfo (MicrocodeFmpPrivate, = 0, NULL, NULL); + + if (CurrentMicrocodeCount > MicrocodeFmpPrivate->DescriptorCount) { + if (MicrocodeFmpPrivate->ImageDescriptor !=3D NULL) { + FreePool(MicrocodeFmpPrivate->ImageDescriptor); + MicrocodeFmpPrivate->ImageDescriptor =3D NULL; + } + if (MicrocodeFmpPrivate->MicrocodeInfo !=3D NULL) { + FreePool(MicrocodeFmpPrivate->MicrocodeInfo); + MicrocodeFmpPrivate->MicrocodeInfo =3D NULL; + } + } else { + ZeroMem(MicrocodeFmpPrivate->ImageDescriptor, MicrocodeFmpPrivate->Des= criptorCount * sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR)); + ZeroMem(MicrocodeFmpPrivate->MicrocodeInfo, MicrocodeFmpPrivate->Descr= iptorCount * sizeof(MICROCODE_INFO)); + } + + MicrocodeFmpPrivate->DescriptorCount =3D CurrentMicrocodeCount; + + if (MicrocodeFmpPrivate->ImageDescriptor =3D=3D NULL) { + MicrocodeFmpPrivate->ImageDescriptor =3D AllocateZeroPool(MicrocodeFmp= Private->DescriptorCount * sizeof(EFI_FIRMWARE_IMAGE_DESCRIPTOR)); + if (MicrocodeFmpPrivate->ImageDescriptor =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + } + if (MicrocodeFmpPrivate->MicrocodeInfo =3D=3D NULL) { + MicrocodeFmpPrivate->MicrocodeInfo =3D AllocateZeroPool(MicrocodeFmpPr= ivate->DescriptorCount * sizeof(MICROCODE_INFO)); + if (MicrocodeFmpPrivate->MicrocodeInfo =3D=3D NULL) { + FreePool (MicrocodeFmpPrivate->ImageDescriptor); + return EFI_OUT_OF_RESOURCES; + } + } + + CurrentMicrocodeCount =3D (UINT8)GetMicrocodeInfo (MicrocodeFmpPrivate, = MicrocodeFmpPrivate->DescriptorCount, MicrocodeFmpPrivate->ImageDescriptor,= MicrocodeFmpPrivate->MicrocodeInfo); + ASSERT(CurrentMicrocodeCount =3D=3D MicrocodeFmpPrivate->DescriptorCount= ); + + InitializedProcessorMicrocodeIndex (MicrocodeFmpPrivate); + + Status =3D InitializeFitMicrocodeInfo (MicrocodeFmpPrivate); + if (EFI_ERROR(Status)) { + FreePool (MicrocodeFmpPrivate->ImageDescriptor); + FreePool (MicrocodeFmpPrivate->MicrocodeInfo); + DEBUG((DEBUG_ERROR, "InitializeFitMicrocodeInfo - %r\n", Status)); + return Status; + } + + return EFI_SUCCESS; +} + +/** + Initialize MicrocodeFmpDriver multiprocessor information. + + @param[in] MicrocodeFmpPrivate private data structure to be initialized. + + @return EFI_SUCCESS Processor information is initialized. + @return EFI_OUT_OF_RESOURCES No enough resource for the initialization. +**/ +EFI_STATUS +InitializeProcessorInfo ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ) +{ + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpService; + UINTN NumberOfProcessors; + UINTN NumberOfEnabledProcessors; + UINTN Index; + UINTN BspIndex; + + Status =3D gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID = **)&MpService); + ASSERT_EFI_ERROR(Status); + + MicrocodeFmpPrivate->MpService =3D MpService; + MicrocodeFmpPrivate->ProcessorCount =3D 0; + MicrocodeFmpPrivate->ProcessorInfo =3D NULL; + + Status =3D MpService->GetNumberOfProcessors (MpService, &NumberOfProcess= ors, &NumberOfEnabledProcessors); + ASSERT_EFI_ERROR(Status); + MicrocodeFmpPrivate->ProcessorCount =3D NumberOfProcessors; + + Status =3D MpService->WhoAmI (MpService, &BspIndex); + ASSERT_EFI_ERROR(Status); + MicrocodeFmpPrivate->BspIndex =3D BspIndex; + + MicrocodeFmpPrivate->ProcessorInfo =3D AllocateZeroPool (sizeof(PROCESSO= R_INFO) * MicrocodeFmpPrivate->ProcessorCount); + if (MicrocodeFmpPrivate->ProcessorInfo =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + for (Index =3D 0; Index < NumberOfProcessors; Index++) { + MicrocodeFmpPrivate->ProcessorInfo[Index].CpuIndex =3D Index; + MicrocodeFmpPrivate->ProcessorInfo[Index].MicrocodeIndex =3D (UINTN)-1; + if (Index =3D=3D BspIndex) { + CollectProcessorInfo (&MicrocodeFmpPrivate->ProcessorInfo[Index]); + } else { + Status =3D MpService->StartupThisAP ( + MpService, + CollectProcessorInfo, + Index, + NULL, + 0, + &MicrocodeFmpPrivate->ProcessorInfo[Index], + NULL + ); + ASSERT_EFI_ERROR(Status); + } + } + + return EFI_SUCCESS; +} + +/** + Dump private information. + + @param[in] MicrocodeFmpPrivate private data structure. +**/ +VOID +DumpPrivateInfo ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ) +{ + UINTN Index; + PROCESSOR_INFO *ProcessorInfo; + MICROCODE_INFO *MicrocodeInfo; + EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageDescriptor; + FIT_MICROCODE_INFO *FitMicrocodeInfo; + + DEBUG ((DEBUG_INFO, "ProcessorInfo:\n")); + DEBUG ((DEBUG_INFO, " ProcessorCount - 0x%x\n", MicrocodeFmpPrivate->Pr= ocessorCount)); + DEBUG ((DEBUG_INFO, " BspIndex - 0x%x\n", MicrocodeFmpPrivate->BspIndex= )); + + ProcessorInfo =3D MicrocodeFmpPrivate->ProcessorInfo; + for (Index =3D 0; Index < MicrocodeFmpPrivate->ProcessorCount; Index++) { + DEBUG (( + DEBUG_INFO, + " ProcessorInfo[0x%x] - 0x%08x, 0x%02x, 0x%08x, (0x%x)\n", + ProcessorInfo[Index].CpuIndex, + ProcessorInfo[Index].ProcessorSignature, + ProcessorInfo[Index].PlatformId, + ProcessorInfo[Index].MicrocodeRevision, + ProcessorInfo[Index].MicrocodeIndex + )); + } + + DEBUG ((DEBUG_INFO, "MicrocodeInfo:\n")); + MicrocodeInfo =3D MicrocodeFmpPrivate->MicrocodeInfo; + DEBUG ((DEBUG_INFO, " MicrocodeRegion - 0x%x - 0x%x\n", MicrocodeFmpPri= vate->MicrocodePatchAddress, MicrocodeFmpPrivate->MicrocodePatchRegionSize)= ); + DEBUG ((DEBUG_INFO, " MicrocodeCount - 0x%x\n", MicrocodeFmpPrivate->De= scriptorCount)); + for (Index =3D 0; Index < MicrocodeFmpPrivate->DescriptorCount; Index++)= { + DEBUG (( + DEBUG_INFO, + " MicrocodeInfo[0x%x] - 0x%08x, 0x%08x, (0x%x)\n", + Index, + MicrocodeInfo[Index].MicrocodeEntryPoint, + MicrocodeInfo[Index].TotalSize, + MicrocodeInfo[Index].InUse + )); + } + + ImageDescriptor =3D MicrocodeFmpPrivate->ImageDescriptor; + DEBUG ((DEBUG_VERBOSE, "ImageDescriptor:\n")); + for (Index =3D 0; Index < MicrocodeFmpPrivate->DescriptorCount; Index++)= { + DEBUG((DEBUG_VERBOSE, " ImageDescriptor (%d)\n", Index)); + DEBUG((DEBUG_VERBOSE, " ImageIndex - 0x%x\n", Imag= eDescriptor[Index].ImageIndex)); + DEBUG((DEBUG_VERBOSE, " ImageTypeId - %g\n", &Image= Descriptor[Index].ImageTypeId)); + DEBUG((DEBUG_VERBOSE, " ImageId - 0x%lx\n", Ima= geDescriptor[Index].ImageId)); + DEBUG((DEBUG_VERBOSE, " ImageIdName - %s\n", ImageD= escriptor[Index].ImageIdName)); + DEBUG((DEBUG_VERBOSE, " Version - 0x%x\n", Imag= eDescriptor[Index].Version)); + DEBUG((DEBUG_VERBOSE, " VersionName - %s\n", ImageD= escriptor[Index].VersionName)); + DEBUG((DEBUG_VERBOSE, " Size - 0x%x\n", Imag= eDescriptor[Index].Size)); + DEBUG((DEBUG_VERBOSE, " AttributesSupported - 0x%lx\n", Ima= geDescriptor[Index].AttributesSupported)); + DEBUG((DEBUG_VERBOSE, " AttributesSetting - 0x%lx\n", Ima= geDescriptor[Index].AttributesSetting)); + DEBUG((DEBUG_VERBOSE, " Compatibilities - 0x%lx\n", Ima= geDescriptor[Index].Compatibilities)); + DEBUG((DEBUG_VERBOSE, " LowestSupportedImageVersion - 0x%x\n", Imag= eDescriptor[Index].LowestSupportedImageVersion)); + DEBUG((DEBUG_VERBOSE, " LastAttemptVersion - 0x%x\n", Imag= eDescriptor[Index].LastAttemptVersion)); + DEBUG((DEBUG_VERBOSE, " LastAttemptStatus - 0x%x\n", Imag= eDescriptor[Index].LastAttemptStatus)); + DEBUG((DEBUG_VERBOSE, " HardwareInstance - 0x%lx\n", Ima= geDescriptor[Index].HardwareInstance)); + } + + if (MicrocodeFmpPrivate->FitMicrocodeInfo !=3D NULL) { + DEBUG ((DEBUG_INFO, "FitMicrocodeInfo:\n")); + FitMicrocodeInfo =3D MicrocodeFmpPrivate->FitMicrocodeInfo; + DEBUG ((DEBUG_INFO, " FitMicrocodeEntryCount - 0x%x\n", MicrocodeFmpP= rivate->FitMicrocodeEntryCount)); + for (Index =3D 0; Index < MicrocodeFmpPrivate->FitMicrocodeEntryCount;= Index++) { + DEBUG (( + DEBUG_INFO, + " FitMicrocodeInfo[0x%x] - 0x%08x, 0x%08x, (0x%x, 0x%x)\n", + Index, + FitMicrocodeInfo[Index].MicrocodeEntryPoint, + FitMicrocodeInfo[Index].TotalSize, + FitMicrocodeInfo[Index].InUse, + FitMicrocodeInfo[Index].Empty + )); + } + } +} + +/** + Initialize MicrocodeFmpDriver private data structure. + + @param[in] MicrocodeFmpPrivate private data structure to be initialized. + + @return EFI_SUCCESS private data is initialized. +**/ +EFI_STATUS +InitializePrivateData ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ) +{ + EFI_STATUS Status; + EFI_STATUS VarStatus; + UINTN VarSize; + BOOLEAN Result; + + MicrocodeFmpPrivate->Signature =3D MICROCODE_FMP_PRIVATE_DATA_SIGN= ATURE; + MicrocodeFmpPrivate->Handle =3D NULL; + CopyMem(&MicrocodeFmpPrivate->Fmp, &mFirmwareManagementProtocol, sizeof(= EFI_FIRMWARE_MANAGEMENT_PROTOCOL)); + + MicrocodeFmpPrivate->PackageVersion =3D 0x1; + MicrocodeFmpPrivate->PackageVersionName =3D L"Microcode"; + + MicrocodeFmpPrivate->LastAttempt.LastAttemptVersion =3D 0x0; + MicrocodeFmpPrivate->LastAttempt.LastAttemptStatus =3D 0x0; + VarSize =3D sizeof(MicrocodeFmpPrivate->LastAttempt); + VarStatus =3D gRT->GetVariable( + MICROCODE_FMP_LAST_ATTEMPT_VARIABLE_NAME, + &gEfiCallerIdGuid, + NULL, + &VarSize, + &MicrocodeFmpPrivate->LastAttempt + ); + DEBUG((DEBUG_INFO, "GetLastAttempt - %r\n", VarStatus)); + DEBUG((DEBUG_INFO, "GetLastAttempt Version - 0x%x, State - 0x%x\n", Micr= ocodeFmpPrivate->LastAttempt.LastAttemptVersion, MicrocodeFmpPrivate->LastA= ttempt.LastAttemptStatus)); + + Result =3D GetMicrocodeRegion(&MicrocodeFmpPrivate->MicrocodePatchAddres= s, &MicrocodeFmpPrivate->MicrocodePatchRegionSize); + if (!Result) { + DEBUG((DEBUG_ERROR, "Fail to get Microcode Region\n")); + return EFI_NOT_FOUND; + } + + Status =3D InitializeProcessorInfo (MicrocodeFmpPrivate); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "InitializeProcessorInfo - %r\n", Status)); + return Status; + } + + Status =3D InitializeMicrocodeDescriptor(MicrocodeFmpPrivate); + if (EFI_ERROR(Status)) { + FreePool (MicrocodeFmpPrivate->ProcessorInfo); + DEBUG((DEBUG_ERROR, "InitializeMicrocodeDescriptor - %r\n", Status)); + return Status; + } + + DumpPrivateInfo (MicrocodeFmpPrivate); + + return Status; +} + +/** + Microcode FMP module entrypoint + + @param[in] ImageHandle The firmware allocated handle for the EFI = image. + @param[in] SystemTable A pointer to the EFI System Table. + + @return EFI_SUCCESS Microcode FMP module is initialized. +**/ +EFI_STATUS +EFIAPI +MicrocodeFmpMain ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + // + // Initialize MicrocodeFmpPrivateData + // + mMicrocodeFmpPrivate =3D AllocateZeroPool (sizeof(MICROCODE_FMP_PRIVATE_= DATA)); + if (mMicrocodeFmpPrivate =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Status =3D InitializePrivateData(mMicrocodeFmpPrivate); + if (EFI_ERROR(Status)) { + FreePool(mMicrocodeFmpPrivate); + mMicrocodeFmpPrivate =3D NULL; + return Status; + } + + // + // Install FMP protocol. + // + Status =3D gBS->InstallProtocolInterface ( + &mMicrocodeFmpPrivate->Handle, + &gEfiFirmwareManagementProtocolGuid, + EFI_NATIVE_INTERFACE, + &mMicrocodeFmpPrivate->Fmp + ); + if (EFI_ERROR (Status)) { + FreePool(mMicrocodeFmpPrivate); + mMicrocodeFmpPrivate =3D NULL; + return Status; + } + + return Status; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateD= xe/MicrocodeUpdate.c b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microc= odeUpdateDxe/MicrocodeUpdate.c new file mode 100644 index 0000000000..84914973b9 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/Micr= ocodeUpdate.c @@ -0,0 +1,1326 @@ +/** @file + SetImage instance to update Microcode. + + Caution: This module requires additional review when modified. + This module will have external input - capsule image. + This external input must be validated carefully to avoid security issue = like + buffer overflow, integer overflow. + + MicrocodeWrite() and VerifyMicrocode() will receive untrusted input and = do basic validation. + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MicrocodeUpdate.h" + +/** + Get Microcode Region. + + @param[out] MicrocodePatchAddress The address of Microcode + @param[out] MicrocodePatchRegionSize The region size of Microcode + + @retval TRUE The Microcode region is returned. + @retval FALSE No Microcode region. +**/ +BOOLEAN +GetMicrocodeRegion ( + OUT VOID **MicrocodePatchAddress, + OUT UINTN *MicrocodePatchRegionSize + ) +{ + *MicrocodePatchAddress =3D (VOID *)(UINTN)PcdGet64(PcdCpuMicrocodePatchA= ddress); + *MicrocodePatchRegionSize =3D (UINTN)PcdGet64(PcdCpuMicrocodePatchRegion= Size); + + if ((*MicrocodePatchAddress =3D=3D NULL) || (*MicrocodePatchRegionSize = =3D=3D 0)) { + return FALSE; + } + + return TRUE; +} + +/** + Get Microcode update signature of currently loaded Microcode update. + + @return Microcode signature. + +**/ +UINT32 +GetCurrentMicrocodeSignature ( + VOID + ) +{ + UINT64 Signature; + + AsmWriteMsr64(MSR_IA32_BIOS_SIGN_ID, 0); + AsmCpuid(CPUID_VERSION_INFO, NULL, NULL, NULL, NULL); + Signature =3D AsmReadMsr64(MSR_IA32_BIOS_SIGN_ID); + return (UINT32)RShiftU64(Signature, 32); +} + +/** + Get current processor signature. + + @return current processor signature. +**/ +UINT32 +GetCurrentProcessorSignature ( + VOID + ) +{ + UINT32 RegEax; + AsmCpuid(CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL); + return RegEax; +} + +/** + Get current platform ID. + + @return current platform ID. +**/ +UINT8 +GetCurrentPlatformId ( + VOID + ) +{ + UINT8 PlatformId; + + PlatformId =3D (UINT8)AsmMsrBitFieldRead64(MSR_IA32_PLATFORM_ID, 50, 52); + return PlatformId; +} + +/** + Load new Microcode. + + @param[in] Address The address of new Microcode. + + @return Loaded Microcode signature. + +**/ +UINT32 +LoadMicrocode ( + IN UINT64 Address + ) +{ + AsmWriteMsr64(MSR_IA32_BIOS_UPDT_TRIG, Address); + return GetCurrentMicrocodeSignature(); +} + +/** + Load Microcode on an Application Processor. + The function prototype for invoking a function on an Application Process= or. + + @param[in,out] Buffer The pointer to private data buffer. +**/ +VOID +EFIAPI +MicrocodeLoadAp ( + IN OUT VOID *Buffer + ) +{ + MICROCODE_LOAD_BUFFER *MicrocodeLoadBuffer; + + MicrocodeLoadBuffer =3D Buffer; + MicrocodeLoadBuffer->Revision =3D LoadMicrocode (MicrocodeLoadBuffer->Ad= dress); +} + +/** + Load new Microcode on this processor + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] CpuIndex The index of the processor. + @param[in] Address The address of new Microcode. + + @return Loaded Microcode signature. + +**/ +UINT32 +LoadMicrocodeOnThis ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN UINTN CpuIndex, + IN UINT64 Address + ) +{ + EFI_STATUS Status; + EFI_MP_SERVICES_PROTOCOL *MpService; + MICROCODE_LOAD_BUFFER MicrocodeLoadBuffer; + + if (CpuIndex =3D=3D MicrocodeFmpPrivate->BspIndex) { + return LoadMicrocode (Address); + } else { + MpService =3D MicrocodeFmpPrivate->MpService; + MicrocodeLoadBuffer.Address =3D Address; + MicrocodeLoadBuffer.Revision =3D 0; + Status =3D MpService->StartupThisAP ( + MpService, + MicrocodeLoadAp, + CpuIndex, + NULL, + 0, + &MicrocodeLoadBuffer, + NULL + ); + ASSERT_EFI_ERROR(Status); + return MicrocodeLoadBuffer.Revision; + } +} + +/** + Collect processor information. + The function prototype for invoking a function on an Application Process= or. + + @param[in,out] Buffer The pointer to private data buffer. +**/ +VOID +EFIAPI +CollectProcessorInfo ( + IN OUT VOID *Buffer + ) +{ + PROCESSOR_INFO *ProcessorInfo; + + ProcessorInfo =3D Buffer; + ProcessorInfo->ProcessorSignature =3D GetCurrentProcessorSignature(); + ProcessorInfo->PlatformId =3D GetCurrentPlatformId(); + ProcessorInfo->MicrocodeRevision =3D GetCurrentMicrocodeSignature(); +} + +/** + Get current Microcode information. + + The ProcessorInformation (BspIndex/ProcessorCount/ProcessorInfo) + in MicrocodeFmpPrivate must be initialized. + + The MicrocodeInformation (DescriptorCount/ImageDescriptor/MicrocodeInfo) + in MicrocodeFmpPrivate may not be avaiable in this function. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] DescriptorCount The count of Microcode ImageDesc= riptor allocated. + @param[out] ImageDescriptor Microcode ImageDescriptor + @param[out] MicrocodeInfo Microcode information + + @return Microcode count +**/ +UINTN +GetMicrocodeInfo ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN UINTN DescriptorCount, OPTIONAL + OUT EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageDescriptor, OPTIONAL + OUT MICROCODE_INFO *MicrocodeInfo OPTIONAL + ) +{ + VOID *MicrocodePatchAddress; + UINTN MicrocodePatchRegionSize; + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN MicrocodeEnd; + UINTN TotalSize; + UINTN Count; + UINT64 ImageAttributes; + BOOLEAN IsInUse; + EFI_STATUS Status; + UINT32 AttemptStatus; + UINTN TargetCpuIndex; + + MicrocodePatchAddress =3D MicrocodeFmpPrivate->MicrocodePatchAddress; + MicrocodePatchRegionSize =3D MicrocodeFmpPrivate->MicrocodePatchRegionSi= ze; + + DEBUG((DEBUG_INFO, "Microcode Region - 0x%x - 0x%x\n", MicrocodePatchAdd= ress, MicrocodePatchRegionSize)); + + Count =3D 0; + + MicrocodeEnd =3D (UINTN)MicrocodePatchAddress + MicrocodePatchRegionSize; + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) MicrocodePatchA= ddress; + do { + if (MicrocodeEntryPoint->HeaderVersion =3D=3D 0x1 && MicrocodeEntryPoi= nt->LoaderRevision =3D=3D 0x1) { + // + // It is the microcode header. It is not the padding data between mi= crocode patches + // becasue the padding data should not include 0x00000001 and it sho= uld be the repeated + // byte format (like 0xXYXYXYXY....). + // + if (MicrocodeEntryPoint->DataSize =3D=3D 0) { + TotalSize =3D 2048; + } else { + TotalSize =3D MicrocodeEntryPoint->TotalSize; + } + + TargetCpuIndex =3D (UINTN)-1; + Status =3D VerifyMicrocode(MicrocodeFmpPrivate, MicrocodeEntryPoint,= TotalSize, FALSE, &AttemptStatus, NULL, &TargetCpuIndex); + if (!EFI_ERROR(Status)) { + IsInUse =3D TRUE; + ASSERT (TargetCpuIndex < MicrocodeFmpPrivate->ProcessorCount); + MicrocodeFmpPrivate->ProcessorInfo[TargetCpuIndex].MicrocodeIndex = =3D Count; + } else { + IsInUse =3D FALSE; + } + + if (ImageDescriptor !=3D NULL && DescriptorCount > Count) { + ImageDescriptor[Count].ImageIndex =3D (UINT8)(Count + 1); + CopyGuid (&ImageDescriptor[Count].ImageTypeId, &gMicrocodeFmpImage= TypeIdGuid); + ImageDescriptor[Count].ImageId =3D LShiftU64(MicrocodeEntryPoint->= ProcessorFlags, 32) + MicrocodeEntryPoint->ProcessorSignature.Uint32; + ImageDescriptor[Count].ImageIdName =3D NULL; + ImageDescriptor[Count].Version =3D MicrocodeEntryPoint->UpdateRevi= sion; + ImageDescriptor[Count].VersionName =3D NULL; + ImageDescriptor[Count].Size =3D TotalSize; + ImageAttributes =3D IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | IMAGE_ATTRIB= UTE_RESET_REQUIRED; + if (IsInUse) { + ImageAttributes |=3D IMAGE_ATTRIBUTE_IN_USE; + } + ImageDescriptor[Count].AttributesSupported =3D ImageAttributes | I= MAGE_ATTRIBUTE_IN_USE; + ImageDescriptor[Count].AttributesSetting =3D ImageAttributes; + ImageDescriptor[Count].Compatibilities =3D 0; + ImageDescriptor[Count].LowestSupportedImageVersion =3D MicrocodeEn= tryPoint->UpdateRevision; // do not support rollback + ImageDescriptor[Count].LastAttemptVersion =3D 0; + ImageDescriptor[Count].LastAttemptStatus =3D 0; + ImageDescriptor[Count].HardwareInstance =3D 0; + } + if (MicrocodeInfo !=3D NULL && DescriptorCount > Count) { + MicrocodeInfo[Count].MicrocodeEntryPoint =3D MicrocodeEntryPoint; + MicrocodeInfo[Count].TotalSize =3D TotalSize; + MicrocodeInfo[Count].InUse =3D IsInUse; + } + } else { + // + // It is the padding data between the microcode patches for microcod= e patches alignment. + // Because the microcode patch is the multiple of 1-KByte, the paddi= ng data should not + // exist if the microcode patch alignment value is not larger than 1= -KByte. So, the microcode + // alignment value should be larger than 1-KByte. We could skip SIZE= _1KB padding data to + // find the next possible microcode patch header. + // + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) Microcode= EntryPoint) + SIZE_1KB); + continue; + } + + Count++; + ASSERT(Count < 0xFF); + + // + // Get the next patch. + // + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEn= tryPoint) + TotalSize); + } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd)); + + return Count; +} + +/** + Return matched processor information. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] ProcessorSignature The processor signature to be mat= ched + @param[in] ProcessorFlags The processor flags to be matched + @param[in, out] TargetCpuIndex On input, the index of target CPU= which tries to match the Microcode. (UINTN)-1 means to try all. + On output, the index of target CP= U which matches the Microcode. + + @return matched processor information. +**/ +PROCESSOR_INFO * +GetMatchedProcessor ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN UINT32 ProcessorSignature, + IN UINT32 ProcessorFlags, + IN OUT UINTN *TargetCpuIndex + ) +{ + UINTN Index; + + if (*TargetCpuIndex !=3D (UINTN)-1) { + Index =3D *TargetCpuIndex; + if ((ProcessorSignature =3D=3D MicrocodeFmpPrivate->ProcessorInfo[Inde= x].ProcessorSignature) && + ((ProcessorFlags & (1 << MicrocodeFmpPrivate->ProcessorInfo[Index]= .PlatformId)) !=3D 0)) { + return &MicrocodeFmpPrivate->ProcessorInfo[Index]; + } else { + return NULL; + } + } + + for (Index =3D 0; Index < MicrocodeFmpPrivate->ProcessorCount; Index++) { + if ((ProcessorSignature =3D=3D MicrocodeFmpPrivate->ProcessorInfo[Inde= x].ProcessorSignature) && + ((ProcessorFlags & (1 << MicrocodeFmpPrivate->ProcessorInfo[Index]= .PlatformId)) !=3D 0)) { + *TargetCpuIndex =3D Index; + return &MicrocodeFmpPrivate->ProcessorInfo[Index]; + } + } + return NULL; +} + +/** + Verify Microcode. + + Caution: This function may receive untrusted input. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] Image The Microcode image buffer. + @param[in] ImageSize The size of Microcode image buffe= r in bytes. + @param[in] TryLoad Try to load Microcode or not. + @param[out] LastAttemptStatus The last attempt status, which wi= ll be recorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + @param[out] AbortReason A pointer to a pointer to a null-= terminated string providing more + details for the aborted operation= . The buffer is allocated by this function + with AllocatePool(), and it is th= e caller's responsibility to free it with a + call to FreePool(). + @param[in, out] TargetCpuIndex On input, the index of target CPU= which tries to match the Microcode. (UINTN)-1 means to try all. + On output, the index of target CP= U which matches the Microcode. + + @retval EFI_SUCCESS The Microcode image passes verificatio= n. + @retval EFI_VOLUME_CORRUPTED The Microcode image is corrupted. + @retval EFI_INCOMPATIBLE_VERSION The Microcode image version is incorre= ct. + @retval EFI_UNSUPPORTED The Microcode ProcessorSignature or Pr= ocessorFlags is incorrect. + @retval EFI_SECURITY_VIOLATION The Microcode image fails to load. +**/ +EFI_STATUS +VerifyMicrocode ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN VOID *Image, + IN UINTN ImageSize, + IN BOOLEAN TryLoad, + OUT UINT32 *LastAttemptStatus, + OUT CHAR16 **AbortReason, OPTIONAL + IN OUT UINTN *TargetCpuIndex + ) +{ + UINTN Index; + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN TotalSize; + UINTN DataSize; + UINT32 CurrentRevision; + PROCESSOR_INFO *ProcessorInfo; + UINT32 InCompleteCheckSum32; + UINT32 CheckSum32; + UINTN ExtendedTableLength; + UINT32 ExtendedTableCount; + CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; + CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; + BOOLEAN CorrectMicrocode; + + // + // Check HeaderVersion + // + MicrocodeEntryPoint =3D Image; + if (MicrocodeEntryPoint->HeaderVersion !=3D 0x1) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on HeaderVersion\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidHeaderVersion"), L= "InvalidHeaderVersion"); + } + return EFI_INCOMPATIBLE_VERSION; + } + // + // Check LoaderRevision + // + if (MicrocodeEntryPoint->LoaderRevision !=3D 0x1) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on LoaderRevision\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidLoaderVersion"), L= "InvalidLoaderVersion"); + } + return EFI_INCOMPATIBLE_VERSION; + } + // + // Check TotalSize + // + if (MicrocodeEntryPoint->DataSize =3D=3D 0) { + TotalSize =3D 2048; + } else { + TotalSize =3D MicrocodeEntryPoint->TotalSize; + } + if (TotalSize <=3D sizeof(CPU_MICROCODE_HEADER)) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - TotalSize too small\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidTotalSize"), L"Inv= alidTotalSize"); + } + return EFI_VOLUME_CORRUPTED; + } + if ((TotalSize & (SIZE_1KB - 1)) !=3D 0) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - TotalSize is not multiples of 1= 024 bytes (1 KBytes)\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidTotalSize"), L"Inv= alidTotalSize"); + } + return EFI_VOLUME_CORRUPTED; + } + if (TotalSize !=3D ImageSize) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - TotalSize not equal to ImageSiz= e\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidTotalSize"), L"Inv= alidTotalSize"); + } + return EFI_VOLUME_CORRUPTED; + } + // + // Check DataSize + // + if (MicrocodeEntryPoint->DataSize =3D=3D 0) { + DataSize =3D 2048 - sizeof(CPU_MICROCODE_HEADER); + } else { + DataSize =3D MicrocodeEntryPoint->DataSize; + } + if (DataSize > TotalSize - sizeof(CPU_MICROCODE_HEADER)) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - DataSize too big\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidDataSize"), L"Inva= lidDataSize"); + } + return EFI_VOLUME_CORRUPTED; + } + if ((DataSize & 0x3) !=3D 0) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - DataSize is not multiples of DW= ORDs\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidDataSize"), L"Inva= lidDataSize"); + } + return EFI_VOLUME_CORRUPTED; + } + // + // Check CheckSum32 + // + CheckSum32 =3D CalculateSum32((UINT32 *)MicrocodeEntryPoint, DataSize + = sizeof(CPU_MICROCODE_HEADER)); + if (CheckSum32 !=3D 0) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on CheckSum32\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INVALID_FORMAT; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidChecksum"), L"Inva= lidChecksum"); + } + return EFI_VOLUME_CORRUPTED; + } + InCompleteCheckSum32 =3D CheckSum32; + InCompleteCheckSum32 -=3D MicrocodeEntryPoint->ProcessorSignature.Uint32; + InCompleteCheckSum32 -=3D MicrocodeEntryPoint->ProcessorFlags; + InCompleteCheckSum32 -=3D MicrocodeEntryPoint->Checksum; + + // + // Check ProcessorSignature/ProcessorFlags + // + + ProcessorInfo =3D GetMatchedProcessor (MicrocodeFmpPrivate, MicrocodeEnt= ryPoint->ProcessorSignature.Uint32, MicrocodeEntryPoint->ProcessorFlags, Ta= rgetCpuIndex); + if (ProcessorInfo =3D=3D NULL) { + CorrectMicrocode =3D FALSE; + ExtendedTableLength =3D TotalSize - (DataSize + sizeof(CPU_MICROCODE_H= EADER)); + if (ExtendedTableLength !=3D 0) { + // + // Extended Table exist, check if the CPU in support list + // + ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *)((UIN= T8 *)(MicrocodeEntryPoint) + DataSize + sizeof(CPU_MICROCODE_HEADER)); + // + // Calculate Extended Checksum + // + if ((ExtendedTableLength > sizeof(CPU_MICROCODE_EXTENDED_TABLE_HEADE= R)) && ((ExtendedTableLength & 0x3) =3D=3D 0)) { + CheckSum32 =3D CalculateSum32((UINT32 *)ExtendedTableHeader, Exten= dedTableLength); + if (CheckSum32 !=3D 0) { + // + // Checksum incorrect + // + DEBUG((DEBUG_ERROR, "VerifyMicrocode - The checksum for extended= table is incorrect\n")); + } else { + // + // Checksum correct + // + ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignatureCou= nt; + if (ExtendedTableCount > (ExtendedTableLength - sizeof(CPU_MICRO= CODE_EXTENDED_TABLE_HEADER)) / sizeof(CPU_MICROCODE_EXTENDED_TABLE)) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - ExtendedTableCount %d i= s too big\n", ExtendedTableCount)); + } else { + ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *)(ExtendedTab= leHeader + 1); + for (Index =3D 0; Index < ExtendedTableCount; Index++) { + CheckSum32 =3D InCompleteCheckSum32; + CheckSum32 +=3D ExtendedTable->ProcessorSignature.Uint32; + CheckSum32 +=3D ExtendedTable->ProcessorFlag; + CheckSum32 +=3D ExtendedTable->Checksum; + if (CheckSum32 !=3D 0) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - The checksum for Ex= tendedTable entry with index 0x%x is incorrect\n", Index)); + } else { + // + // Verify Header + // + ProcessorInfo =3D GetMatchedProcessor (MicrocodeFmpPrivate= , ExtendedTable->ProcessorSignature.Uint32, ExtendedTable->ProcessorFlag, T= argetCpuIndex); + if (ProcessorInfo !=3D NULL) { + // + // Find one + // + CorrectMicrocode =3D TRUE; + break; + } + } + ExtendedTable++; + } + } + } + } + } + if (!CorrectMicrocode) { + if (TryLoad) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on Current ProcessorSi= gnature/ProcessorFlags\n")); + } + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"UnsupportedProcessorSig= nature/ProcessorFlags"), L"UnsupportedProcessorSignature/ProcessorFlags"); + } + return EFI_UNSUPPORTED; + } + } + + // + // Check UpdateRevision + // + CurrentRevision =3D ProcessorInfo->MicrocodeRevision; + if ((MicrocodeEntryPoint->UpdateRevision < CurrentRevision) || + (TryLoad && (MicrocodeEntryPoint->UpdateRevision =3D=3D CurrentRevis= ion))) { + if (TryLoad) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on UpdateRevision\n")); + } + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INCORRECT_VERSION; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"IncorrectRevision"), L"In= correctRevision"); + } + return EFI_INCOMPATIBLE_VERSION; + } + + // + // try load MCU + // + if (TryLoad) { + CurrentRevision =3D LoadMicrocodeOnThis(MicrocodeFmpPrivate, Processor= Info->CpuIndex, (UINTN)MicrocodeEntryPoint + sizeof(CPU_MICROCODE_HEADER)); + if (MicrocodeEntryPoint->UpdateRevision !=3D CurrentRevision) { + DEBUG((DEBUG_ERROR, "VerifyMicrocode - fail on LoadMicrocode\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_AUTH_ERROR; + if (AbortReason !=3D NULL) { + *AbortReason =3D AllocateCopyPool(sizeof(L"InvalidData"), L"Invali= dData"); + } + return EFI_SECURITY_VIOLATION; + } + } + + return EFI_SUCCESS; +} + +/** + Get next Microcode entrypoint. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] MicrocodeEntryPoint Current Microcode entrypoint + + @return next Microcode entrypoint. +**/ +CPU_MICROCODE_HEADER * +GetNextMicrocode ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint + ) +{ + UINTN Index; + + for (Index =3D 0; Index < MicrocodeFmpPrivate->DescriptorCount; Index++)= { + if (MicrocodeEntryPoint =3D=3D MicrocodeFmpPrivate->MicrocodeInfo[Inde= x].MicrocodeEntryPoint) { + if (Index =3D=3D (UINTN)MicrocodeFmpPrivate->DescriptorCount - 1) { + // it is last one + return NULL; + } else { + // return next one + return MicrocodeFmpPrivate->MicrocodeInfo[Index + 1].MicrocodeEntr= yPoint; + } + } + } + + ASSERT(FALSE); + return NULL; +} + +/** + Get next FIT Microcode entrypoint. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] MicrocodeEntryPoint Current Microcode entrypoint + + @return next FIT Microcode entrypoint. +**/ +CPU_MICROCODE_HEADER * +GetNextFitMicrocode ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN CPU_MICROCODE_HEADER *MicrocodeEntryPoint + ) +{ + UINTN Index; + + for (Index =3D 0; Index < MicrocodeFmpPrivate->FitMicrocodeEntryCount; I= ndex++) { + if (MicrocodeEntryPoint =3D=3D MicrocodeFmpPrivate->FitMicrocodeInfo[I= ndex].MicrocodeEntryPoint) { + if (Index =3D=3D (UINTN) MicrocodeFmpPrivate->FitMicrocodeEntryCount= - 1) { + // it is last one + return NULL; + } else { + // return next one + return MicrocodeFmpPrivate->FitMicrocodeInfo[Index + 1].MicrocodeE= ntryPoint; + } + } + } + + ASSERT(FALSE); + return NULL; +} + +/** + Find empty FIT Microcode entrypoint. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] ImageSize The size of Microcode image buffe= r in bytes. + @param[out] AvailableSize Available size of the empty FIT M= icrocode entrypoint. + + @return Empty FIT Microcode entrypoint. +**/ +CPU_MICROCODE_HEADER * +FindEmptyFitMicrocode ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN UINTN ImageSize, + OUT UINTN *AvailableSize + ) +{ + UINTN Index; + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + CPU_MICROCODE_HEADER *NextMicrocodeEntryPoint; + VOID *MicrocodePatchAddress; + UINTN MicrocodePatchRegionSize; + + MicrocodePatchAddress =3D MicrocodeFmpPrivate->MicrocodePatchAddress; + MicrocodePatchRegionSize =3D MicrocodeFmpPrivate->MicrocodePatchRegionSi= ze; + + for (Index =3D 0; Index < MicrocodeFmpPrivate->FitMicrocodeEntryCount; I= ndex++) { + if (MicrocodeFmpPrivate->FitMicrocodeInfo[Index].Empty) { + MicrocodeEntryPoint =3D MicrocodeFmpPrivate->FitMicrocodeInfo[Index]= .MicrocodeEntryPoint; + NextMicrocodeEntryPoint =3D GetNextFitMicrocode (MicrocodeFmpPrivate= , MicrocodeEntryPoint); + if (NextMicrocodeEntryPoint !=3D NULL) { + *AvailableSize =3D (UINTN) NextMicrocodeEntryPoint - (UINTN) Micro= codeEntryPoint; + } else { + *AvailableSize =3D (UINTN) MicrocodePatchAddress + MicrocodePatchR= egionSize - (UINTN) MicrocodeEntryPoint; + } + if (*AvailableSize >=3D ImageSize) { + return MicrocodeEntryPoint; + } + } + } + + return NULL; +} + +/** + Find unused FIT Microcode entrypoint. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] ImageSize The size of Microcode image buffe= r in bytes. + @param[out] AvailableSize Available size of the unused FIT = Microcode entrypoint. + + @return Unused FIT Microcode entrypoint. +**/ +CPU_MICROCODE_HEADER * +FindUnusedFitMicrocode ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN UINTN ImageSize, + OUT UINTN *AvailableSize + ) +{ + UINTN Index; + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + CPU_MICROCODE_HEADER *NextMicrocodeEntryPoint; + VOID *MicrocodePatchAddress; + UINTN MicrocodePatchRegionSize; + + MicrocodePatchAddress =3D MicrocodeFmpPrivate->MicrocodePatchAddress; + MicrocodePatchRegionSize =3D MicrocodeFmpPrivate->MicrocodePatchRegionSi= ze; + + for (Index =3D 0; Index < MicrocodeFmpPrivate->FitMicrocodeEntryCount; I= ndex++) { + if (!MicrocodeFmpPrivate->FitMicrocodeInfo[Index].InUse) { + MicrocodeEntryPoint =3D MicrocodeFmpPrivate->FitMicrocodeInfo[Index]= .MicrocodeEntryPoint; + NextMicrocodeEntryPoint =3D GetNextFitMicrocode (MicrocodeFmpPrivate= , MicrocodeEntryPoint); + if (NextMicrocodeEntryPoint !=3D NULL) { + *AvailableSize =3D (UINTN) NextMicrocodeEntryPoint - (UINTN) Micro= codeEntryPoint; + } else { + *AvailableSize =3D (UINTN) MicrocodePatchAddress + MicrocodePatchR= egionSize - (UINTN) MicrocodeEntryPoint; + } + if (*AvailableSize >=3D ImageSize) { + return MicrocodeEntryPoint; + } + } + } + + return NULL; +} + +/** + Get current Microcode used region size. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + + @return current Microcode used region size. +**/ +UINTN +GetCurrentMicrocodeUsedRegionSize ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ) +{ + if (MicrocodeFmpPrivate->DescriptorCount =3D=3D 0) { + return 0; + } + + return (UINTN)MicrocodeFmpPrivate->MicrocodeInfo[MicrocodeFmpPrivate->De= scriptorCount - 1].MicrocodeEntryPoint + + (UINTN)MicrocodeFmpPrivate->MicrocodeInfo[MicrocodeFmpPrivate->= DescriptorCount - 1].TotalSize + - (UINTN)MicrocodeFmpPrivate->MicrocodePatchAddress; +} + +/** + Update Microcode. + + @param[in] Address The flash address of Microcode. + @param[in] Image The Microcode image buffer. + @param[in] ImageSize The size of Microcode image buffer in by= tes. + @param[out] LastAttemptStatus The last attempt status, which will be r= ecorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + + @retval EFI_SUCCESS The Microcode image is updated. + @retval EFI_WRITE_PROTECTED The flash device is read only. +**/ +EFI_STATUS +UpdateMicrocode ( + IN UINT64 Address, + IN VOID *Image, + IN UINTN ImageSize, + OUT UINT32 *LastAttemptStatus + ) +{ + EFI_STATUS Status; + + DEBUG((DEBUG_INFO, "PlatformUpdate:")); + DEBUG((DEBUG_INFO, " Address - 0x%lx,", Address)); + DEBUG((DEBUG_INFO, " Length - 0x%x\n", ImageSize)); + + Status =3D MicrocodeFlashWrite ( + Address, + Image, + ImageSize + ); + if (!EFI_ERROR(Status)) { + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_SUCCESS; + } else { + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_UNSUCCESSFUL; + } + return Status; +} + +/** + Update Microcode flash region with FIT. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] TargetMicrocodeEntryPoint Target Microcode entrypoint to be= updated + @param[in] Image The Microcode image buffer. + @param[in] ImageSize The size of Microcode image buffe= r in bytes. + @param[out] LastAttemptStatus The last attempt status, which wi= ll be recorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + + @retval EFI_SUCCESS The Microcode image is written. + @retval EFI_WRITE_PROTECTED The flash device is read only. +**/ +EFI_STATUS +UpdateMicrocodeFlashRegionWithFit ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN CPU_MICROCODE_HEADER *TargetMicrocodeEntryPoint, + IN VOID *Image, + IN UINTN ImageSize, + OUT UINT32 *LastAttemptStatus + ) +{ + VOID *MicrocodePatchAddress; + UINTN MicrocodePatchRegionSize; + UINTN TargetTotalSize; + EFI_STATUS Status; + VOID *MicrocodePatchScratchBuffer; + UINT8 *ScratchBufferPtr; + UINTN ScratchBufferSize; + UINTN RestSize; + UINTN AvailableSize; + VOID *NextMicrocodeEntryPoint; + VOID *EmptyFitMicrocodeEntry; + VOID *UnusedFitMicrocodeEntry; + + DEBUG((DEBUG_INFO, "UpdateMicrocodeFlashRegionWithFit: Image - 0x%x, siz= e - 0x%x\n", Image, ImageSize)); + + MicrocodePatchAddress =3D MicrocodeFmpPrivate->MicrocodePatchAddress; + MicrocodePatchRegionSize =3D MicrocodeFmpPrivate->MicrocodePatchRegionSi= ze; + + MicrocodePatchScratchBuffer =3D AllocateZeroPool (MicrocodePatchRegionSi= ze); + if (MicrocodePatchScratchBuffer =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Fail to allocate Microcode Scratch buffer\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCE= S; + return EFI_OUT_OF_RESOURCES; + } + ScratchBufferPtr =3D MicrocodePatchScratchBuffer; + ScratchBufferSize =3D 0; + + // + // Target data collection + // + TargetTotalSize =3D 0; + AvailableSize =3D 0; + if (TargetMicrocodeEntryPoint !=3D NULL) { + if (TargetMicrocodeEntryPoint->DataSize =3D=3D 0) { + TargetTotalSize =3D 2048; + } else { + TargetTotalSize =3D TargetMicrocodeEntryPoint->TotalSize; + } + DEBUG((DEBUG_INFO, " TargetTotalSize - 0x%x\n", TargetTotalSize)); + NextMicrocodeEntryPoint =3D GetNextFitMicrocode (MicrocodeFmpPrivate, = TargetMicrocodeEntryPoint); + DEBUG((DEBUG_INFO, " NextMicrocodeEntryPoint - 0x%x\n", NextMicrocode= EntryPoint)); + if (NextMicrocodeEntryPoint !=3D NULL) { + ASSERT ((UINTN) NextMicrocodeEntryPoint >=3D ((UINTN) TargetMicrocod= eEntryPoint + TargetTotalSize)); + AvailableSize =3D (UINTN) NextMicrocodeEntryPoint - (UINTN) TargetMi= crocodeEntryPoint; + } else { + AvailableSize =3D (UINTN) MicrocodePatchAddress + MicrocodePatchRegi= onSize - (UINTN) TargetMicrocodeEntryPoint; + } + DEBUG((DEBUG_INFO, " AvailableSize - 0x%x\n", AvailableSize)); + ASSERT (AvailableSize >=3D TargetTotalSize); + } + // + // Total Size means the Microcode size. + // Available Size means the Microcode size plus the pad till (1) next Mi= crocode or (2) the end. + // + // (1) + // +------+-----------+-----+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+ + // | MCU1 | Microcode | PAD | MCU2 | Empty | + // +------+-----------+-----+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+ + // | TotalSize | + // |<-AvailableSize->| + // + // (2) + // +------+-----------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D+ + // | MCU | Microcode | Empty | + // +------+-----------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D+ + // | TotalSize | + // |<- AvailableSize ->| + // + + // + // Update based on policy + // + + // + // 1. If there is enough space to update old one in situ, replace old mi= crocode in situ. + // + if (AvailableSize >=3D ImageSize) { + DEBUG((DEBUG_INFO, "Replace old microcode in situ\n")); + // + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // |Other | Old Image | ... | Empty | + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // + // +------+---------+--+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // |Other |New Image|FF| ... | Empty | + // +------+---------+--+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // + // 1.1. Copy new image + CopyMem (ScratchBufferPtr, Image, ImageSize); + ScratchBufferSize +=3D ImageSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchBuf= ferSize; + // 1.2. Pad 0xFF + RestSize =3D AvailableSize - ImageSize; + if (RestSize > 0) { + SetMem (ScratchBufferPtr, RestSize, 0xFF); + ScratchBufferSize +=3D RestSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchB= ufferSize; + } + Status =3D UpdateMicrocode((UINTN)TargetMicrocodeEntryPoint, Microcode= PatchScratchBuffer, ScratchBufferSize, LastAttemptStatus); + return Status; + } + + // + // 2. If there is empty FIT microcode entry with enough space, use it. + // + EmptyFitMicrocodeEntry =3D FindEmptyFitMicrocode (MicrocodeFmpPrivate, I= mageSize, &AvailableSize); + if (EmptyFitMicrocodeEntry !=3D NULL) { + DEBUG((DEBUG_INFO, "Use empty FIT microcode entry\n")); + // 2.1. Copy new image + CopyMem (ScratchBufferPtr, Image, ImageSize); + ScratchBufferSize +=3D ImageSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchBuf= ferSize; + // 2.2. Pad 0xFF + RestSize =3D AvailableSize - ImageSize; + if (RestSize > 0) { + SetMem (ScratchBufferPtr, RestSize, 0xFF); + ScratchBufferSize +=3D RestSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchB= ufferSize; + } + Status =3D UpdateMicrocode ((UINTN) EmptyFitMicrocodeEntry, MicrocodeP= atchScratchBuffer, ScratchBufferSize, LastAttemptStatus); + if (!EFI_ERROR (Status) && (TargetMicrocodeEntryPoint !=3D NULL)) { + // + // Empty old microcode. + // + ScratchBufferPtr =3D MicrocodePatchScratchBuffer; + SetMem (ScratchBufferPtr, TargetTotalSize, 0xFF); + ScratchBufferSize =3D TargetTotalSize; + ScratchBufferPtr =3D (UINT8 *) MicrocodePatchScratchBuffer + Scratch= BufferSize; + UpdateMicrocode ((UINTN) TargetMicrocodeEntryPoint, MicrocodePatchSc= ratchBuffer, ScratchBufferSize, LastAttemptStatus); + } + return Status; + } + + // + // 3. If there is unused microcode entry with enough space, use it. + // + UnusedFitMicrocodeEntry =3D FindUnusedFitMicrocode (MicrocodeFmpPrivate,= ImageSize, &AvailableSize); + if (UnusedFitMicrocodeEntry !=3D NULL) { + DEBUG((DEBUG_INFO, "Use unused FIT microcode entry\n")); + // 3.1. Copy new image + CopyMem (ScratchBufferPtr, Image, ImageSize); + ScratchBufferSize +=3D ImageSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchBuf= ferSize; + // 3.2. Pad 0xFF + RestSize =3D AvailableSize - ImageSize; + if (RestSize > 0) { + SetMem (ScratchBufferPtr, RestSize, 0xFF); + ScratchBufferSize +=3D RestSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchB= ufferSize; + } + Status =3D UpdateMicrocode ((UINTN) UnusedFitMicrocodeEntry, Microcode= PatchScratchBuffer, ScratchBufferSize, LastAttemptStatus); + if (!EFI_ERROR (Status) && (TargetMicrocodeEntryPoint !=3D NULL)) { + // + // Empty old microcode. + // + ScratchBufferPtr =3D MicrocodePatchScratchBuffer; + SetMem (ScratchBufferPtr, TargetTotalSize, 0xFF); + ScratchBufferSize =3D TargetTotalSize; + ScratchBufferPtr =3D (UINT8 *) MicrocodePatchScratchBuffer + Scratch= BufferSize; + UpdateMicrocode ((UINTN) TargetMicrocodeEntryPoint, MicrocodePatchSc= ratchBuffer, ScratchBufferSize, LastAttemptStatus); + } + return Status; + } + + // + // 4. No usable FIT microcode entry. + // + DEBUG((DEBUG_ERROR, "No usable FIT microcode entry\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES; + Status =3D EFI_OUT_OF_RESOURCES; + + return Status; +} + +/** + Update Microcode flash region. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] TargetMicrocodeEntryPoint Target Microcode entrypoint to be= updated + @param[in] Image The Microcode image buffer. + @param[in] ImageSize The size of Microcode image buffe= r in bytes. + @param[out] LastAttemptStatus The last attempt status, which wi= ll be recorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + + @retval EFI_SUCCESS The Microcode image is written. + @retval EFI_WRITE_PROTECTED The flash device is read only. +**/ +EFI_STATUS +UpdateMicrocodeFlashRegion ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN CPU_MICROCODE_HEADER *TargetMicrocodeEntryPoint, + IN VOID *Image, + IN UINTN ImageSize, + OUT UINT32 *LastAttemptStatus + ) +{ + VOID *MicrocodePatchAddress; + UINTN MicrocodePatchRegionSize; + UINTN TargetTotalSize; + UINTN UsedRegionSize; + EFI_STATUS Status; + VOID *MicrocodePatchScratchBuffer; + UINT8 *ScratchBufferPtr; + UINTN ScratchBufferSize; + UINTN RestSize; + UINTN AvailableSize; + VOID *NextMicrocodeEntryPoint; + MICROCODE_INFO *MicrocodeInfo; + UINTN MicrocodeCount; + UINTN Index; + + DEBUG((DEBUG_INFO, "UpdateMicrocodeFlashRegion: Image - 0x%x, size - 0x%= x\n", Image, ImageSize)); + + MicrocodePatchAddress =3D MicrocodeFmpPrivate->MicrocodePatchAddress; + MicrocodePatchRegionSize =3D MicrocodeFmpPrivate->MicrocodePatchRegionSi= ze; + + MicrocodePatchScratchBuffer =3D AllocateZeroPool (MicrocodePatchRegionSi= ze); + if (MicrocodePatchScratchBuffer =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Fail to allocate Microcode Scratch buffer\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCE= S; + return EFI_OUT_OF_RESOURCES; + } + ScratchBufferPtr =3D MicrocodePatchScratchBuffer; + ScratchBufferSize =3D 0; + + // + // Target data collection + // + TargetTotalSize =3D 0; + AvailableSize =3D 0; + NextMicrocodeEntryPoint =3D NULL; + if (TargetMicrocodeEntryPoint !=3D NULL) { + if (TargetMicrocodeEntryPoint->DataSize =3D=3D 0) { + TargetTotalSize =3D 2048; + } else { + TargetTotalSize =3D TargetMicrocodeEntryPoint->TotalSize; + } + DEBUG((DEBUG_INFO, " TargetTotalSize - 0x%x\n", TargetTotalSize)); + NextMicrocodeEntryPoint =3D GetNextMicrocode(MicrocodeFmpPrivate, Targ= etMicrocodeEntryPoint); + DEBUG((DEBUG_INFO, " NextMicrocodeEntryPoint - 0x%x\n", NextMicrocode= EntryPoint)); + if (NextMicrocodeEntryPoint !=3D NULL) { + ASSERT ((UINTN)NextMicrocodeEntryPoint >=3D ((UINTN)TargetMicrocodeE= ntryPoint + TargetTotalSize)); + AvailableSize =3D (UINTN)NextMicrocodeEntryPoint - (UINTN)TargetMicr= ocodeEntryPoint; + } else { + AvailableSize =3D (UINTN)MicrocodePatchAddress + MicrocodePatchRegio= nSize - (UINTN)TargetMicrocodeEntryPoint; + } + DEBUG((DEBUG_INFO, " AvailableSize - 0x%x\n", AvailableSize)); + ASSERT (AvailableSize >=3D TargetTotalSize); + } + UsedRegionSize =3D GetCurrentMicrocodeUsedRegionSize(MicrocodeFmpPrivate= ); + DEBUG((DEBUG_INFO, " UsedRegionSize - 0x%x\n", UsedRegionSize)); + ASSERT (UsedRegionSize >=3D TargetTotalSize); + if (TargetMicrocodeEntryPoint !=3D NULL) { + ASSERT ((UINTN)MicrocodePatchAddress + UsedRegionSize >=3D ((UINTN)Tar= getMicrocodeEntryPoint + TargetTotalSize)); + } + // + // Total Size means the Microcode size. + // Available Size means the Microcode size plus the pad till (1) next Mi= crocode or (2) the end. + // + // (1) + // +------+-----------+-----+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+ + // | MCU1 | Microcode | PAD | MCU2 | Empty | + // +------+-----------+-----+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+ + // | TotalSize | + // |<-AvailableSize->| + // |<- UsedRegionSize ->| + // + // (2) + // +------+-----------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D+ + // | MCU | Microcode | Empty | + // +------+-----------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D+ + // | TotalSize | + // |<- AvailableSize ->| + // |<-UsedRegionSize->| + // + + // + // Update based on policy + // + + // + // 1. If there is enough space to update old one in situ, replace old mi= crocode in situ. + // + if (AvailableSize >=3D ImageSize) { + DEBUG((DEBUG_INFO, "Replace old microcode in situ\n")); + // + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // |Other | Old Image | ... | Empty | + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // + // +------+---------+--+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // |Other |New Image|FF| ... | Empty | + // +------+---------+--+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // + // 1.1. Copy new image + CopyMem (ScratchBufferPtr, Image, ImageSize); + ScratchBufferSize +=3D ImageSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchBuf= ferSize; + // 1.2. Pad 0xFF + RestSize =3D AvailableSize - ImageSize; + if (RestSize > 0) { + SetMem (ScratchBufferPtr, RestSize, 0xFF); + ScratchBufferSize +=3D RestSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchB= ufferSize; + } + Status =3D UpdateMicrocode((UINTN)TargetMicrocodeEntryPoint, Microcode= PatchScratchBuffer, ScratchBufferSize, LastAttemptStatus); + return Status; + } + + // + // 2. If there is enough space to remove old one and add new one, reorg = and replace old microcode. + // + if (MicrocodePatchRegionSize - (UsedRegionSize - TargetTotalSize) >=3D I= mageSize) { + if (TargetMicrocodeEntryPoint =3D=3D NULL) { + DEBUG((DEBUG_INFO, "Append new microcode\n")); + // + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+ + // |Other1| Other |Other2| Empty | + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+ + // + // +------+------------+------+-----------+=3D=3D=3D=3D=3D=3D=3D+ + // |Other1| Other |Other2| New Image | Empty | + // +------+------------+------+-----------+=3D=3D=3D=3D=3D=3D=3D+ + // + Status =3D UpdateMicrocode((UINTN)MicrocodePatchAddress + UsedRegion= Size, Image, ImageSize, LastAttemptStatus); + } else { + DEBUG((DEBUG_INFO, "Reorg and replace old microcode\n")); + // + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+ + // |Other | Old Image | ... | Empty | + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D+ + // + // +------+---------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D+ + // |Other | New Image | ... | Empty | + // +------+---------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D+ + // + // 2.1. Copy new image + CopyMem (ScratchBufferPtr, Image, ImageSize); + ScratchBufferSize +=3D ImageSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchB= ufferSize; + // 2.2. Copy rest images after the old image. + if (NextMicrocodeEntryPoint !=3D 0) { + RestSize =3D (UINTN)MicrocodePatchAddress + UsedRegionSize - ((UIN= TN)NextMicrocodeEntryPoint); + CopyMem (ScratchBufferPtr, NextMicrocodeEntryPoint, RestSize); + ScratchBufferSize +=3D RestSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + Scratc= hBufferSize; + } + Status =3D UpdateMicrocode((UINTN)TargetMicrocodeEntryPoint, Microco= dePatchScratchBuffer, ScratchBufferSize, LastAttemptStatus); + } + return Status; + } + + // + // 3. The new image can be put in MCU region, but not all others can be = put. + // So all the unused MCU is removed. + // + if (MicrocodePatchRegionSize >=3D ImageSize) { + // + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // |Other1| Old Image |Other2| Empty | + // +------+------------+------+=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ + // + // +-------------------------------------+--------+ + // | New Image | Other | + // +-------------------------------------+--------+ + // + DEBUG((DEBUG_INFO, "Add new microcode from beginning\n")); + + MicrocodeCount =3D MicrocodeFmpPrivate->DescriptorCount; + MicrocodeInfo =3D MicrocodeFmpPrivate->MicrocodeInfo; + + // 3.1. Copy new image + CopyMem (ScratchBufferPtr, Image, ImageSize); + ScratchBufferSize +=3D ImageSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchBuf= ferSize; + // 3.2. Copy some others to rest buffer + for (Index =3D 0; Index < MicrocodeCount; Index++) { + if (!MicrocodeInfo[Index].InUse) { + continue; + } + if (MicrocodeInfo[Index].MicrocodeEntryPoint =3D=3D TargetMicrocodeE= ntryPoint) { + continue; + } + if (MicrocodeInfo[Index].TotalSize <=3D MicrocodePatchRegionSize - S= cratchBufferSize) { + CopyMem (ScratchBufferPtr, MicrocodeInfo[Index].MicrocodeEntryPoin= t, MicrocodeInfo[Index].TotalSize); + ScratchBufferSize +=3D MicrocodeInfo[Index].TotalSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + Scratc= hBufferSize; + } + } + // 3.3. Pad 0xFF + RestSize =3D MicrocodePatchRegionSize - ScratchBufferSize; + if (RestSize > 0) { + SetMem (ScratchBufferPtr, RestSize, 0xFF); + ScratchBufferSize +=3D RestSize; + ScratchBufferPtr =3D (UINT8 *)MicrocodePatchScratchBuffer + ScratchB= ufferSize; + } + Status =3D UpdateMicrocode((UINTN)MicrocodePatchAddress, MicrocodePatc= hScratchBuffer, ScratchBufferSize, LastAttemptStatus); + return Status; + } + + // + // 4. The new image size is bigger than the whole MCU region. + // + DEBUG((DEBUG_ERROR, "Microcode too big\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCES; + Status =3D EFI_OUT_OF_RESOURCES; + + return Status; +} + +/** + Write Microcode. + + Caution: This function may receive untrusted input. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] Image The Microcode image buffer. + @param[in] ImageSize The size of Microcode image buffer in b= ytes. + @param[out] LastAttemptVersion The last attempt version, which will be= recorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + @param[out] LastAttemptStatus The last attempt status, which will be = recorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + @param[out] AbortReason A pointer to a pointer to a null-termin= ated string providing more + details for the aborted operation. The = buffer is allocated by this function + with AllocatePool(), and it is the call= er's responsibility to free it with a + call to FreePool(). + + @retval EFI_SUCCESS The Microcode image is written. + @retval EFI_VOLUME_CORRUPTED The Microcode image is corrupted. + @retval EFI_INCOMPATIBLE_VERSION The Microcode image version is incorre= ct. + @retval EFI_SECURITY_VIOLATION The Microcode image fails to load. + @retval EFI_WRITE_PROTECTED The flash device is read only. +**/ +EFI_STATUS +MicrocodeWrite ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN VOID *Image, + IN UINTN ImageSize, + OUT UINT32 *LastAttemptVersion, + OUT UINT32 *LastAttemptStatus, + OUT CHAR16 **AbortReason + ) +{ + EFI_STATUS Status; + VOID *AlignedImage; + CPU_MICROCODE_HEADER *TargetMicrocodeEntryPoint; + UINTN TargetCpuIndex; + UINTN TargetMicrcodeIndex; + + // + // MCU must be 16 bytes aligned + // + AlignedImage =3D AllocateCopyPool(ImageSize, Image); + if (AlignedImage =3D=3D NULL) { + DEBUG((DEBUG_ERROR, "Fail to allocate aligned image\n")); + *LastAttemptStatus =3D LAST_ATTEMPT_STATUS_ERROR_INSUFFICIENT_RESOURCE= S; + return EFI_OUT_OF_RESOURCES; + } + + TargetCpuIndex =3D (UINTN)-1; + Status =3D VerifyMicrocode(MicrocodeFmpPrivate, AlignedImage, ImageSize,= TRUE, LastAttemptStatus, AbortReason, &TargetCpuIndex); + if (EFI_ERROR(Status)) { + DEBUG((DEBUG_ERROR, "Fail to verify Microcode Region\n")); + FreePool(AlignedImage); + return Status; + } + DEBUG((DEBUG_INFO, "Pass VerifyMicrocode\n")); + *LastAttemptVersion =3D ((CPU_MICROCODE_HEADER *)Image)->UpdateRevision; + + DEBUG((DEBUG_INFO, " TargetCpuIndex - 0x%x\n", TargetCpuIndex)); + ASSERT (TargetCpuIndex < MicrocodeFmpPrivate->ProcessorCount); + TargetMicrcodeIndex =3D MicrocodeFmpPrivate->ProcessorInfo[TargetCpuInde= x].MicrocodeIndex; + DEBUG((DEBUG_INFO, " TargetMicrcodeIndex - 0x%x\n", TargetMicrcodeIndex= )); + if (TargetMicrcodeIndex !=3D (UINTN)-1) { + ASSERT (TargetMicrcodeIndex < MicrocodeFmpPrivate->DescriptorCount); + TargetMicrocodeEntryPoint =3D MicrocodeFmpPrivate->MicrocodeInfo[Targe= tMicrcodeIndex].MicrocodeEntryPoint; + } else { + TargetMicrocodeEntryPoint =3D NULL; + } + DEBUG((DEBUG_INFO, " TargetMicrocodeEntryPoint - 0x%x\n", TargetMicroco= deEntryPoint)); + + if (MicrocodeFmpPrivate->FitMicrocodeInfo !=3D NULL) { + Status =3D UpdateMicrocodeFlashRegionWithFit ( + MicrocodeFmpPrivate, + TargetMicrocodeEntryPoint, + AlignedImage, + ImageSize, + LastAttemptStatus + ); + } else { + Status =3D UpdateMicrocodeFlashRegion ( + MicrocodeFmpPrivate, + TargetMicrocodeEntryPoint, + AlignedImage, + ImageSize, + LastAttemptStatus + ); + } + + FreePool(AlignedImage); + + return Status; +} + + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c = b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c new file mode 100644 index 0000000000..0bd4e818ab --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/BmDma.c @@ -0,0 +1,538 @@ +/** @file + BmDma related function + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DmaProtection.h" + +// TBD: May make it a policy +#define DMA_MEMORY_TOP MAX_UINTN +//#define DMA_MEMORY_TOP 0x0000000001FFFFFFULL + +#define MAP_HANDLE_INFO_SIGNATURE SIGNATURE_32 ('H', 'M', 'A', 'P') +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_HANDLE DeviceHandle; + UINT64 IoMmuAccess; +} MAP_HANDLE_INFO; +#define MAP_HANDLE_INFO_FROM_LINK(a) CR (a, MAP_HANDLE_INFO, Link, MAP_HAN= DLE_INFO_SIGNATURE) + +#define MAP_INFO_SIGNATURE SIGNATURE_32 ('D', 'M', 'A', 'P') +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EDKII_IOMMU_OPERATION Operation; + UINTN NumberOfBytes; + UINTN NumberOfPages; + EFI_PHYSICAL_ADDRESS HostAddress; + EFI_PHYSICAL_ADDRESS DeviceAddress; + LIST_ENTRY HandleList; +} MAP_INFO; +#define MAP_INFO_FROM_LINK(a) CR (a, MAP_INFO, Link, MAP_INFO_SIGNATURE) + +LIST_ENTRY gMaps =3D INITIALIZE_LIST_HEAD_VARIABLE(= gMaps); + +/** + This function fills DeviceHandle/IoMmuAccess to the MAP_HANDLE_INFO, + based upon the DeviceAddress. + + @param[in] DeviceHandle The device who initiates the DMA access re= quest. + @param[in] DeviceAddress The base of device memory address to be us= ed as the DMA memory. + @param[in] Length The length of device memory address to be = used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + +**/ +VOID +SyncDeviceHandleToMapInfo ( + IN EFI_HANDLE DeviceHandle, + IN EFI_PHYSICAL_ADDRESS DeviceAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ) +{ + MAP_INFO *MapInfo; + MAP_HANDLE_INFO *MapHandleInfo; + LIST_ENTRY *Link; + EFI_TPL OriginalTpl; + + // + // Find MapInfo according to DeviceAddress + // + OriginalTpl =3D gBS->RaiseTPL (VTD_TPL_LEVEL); + MapInfo =3D NULL; + for (Link =3D GetFirstNode (&gMaps) + ; !IsNull (&gMaps, Link) + ; Link =3D GetNextNode (&gMaps, Link) + ) { + MapInfo =3D MAP_INFO_FROM_LINK (Link); + if (MapInfo->DeviceAddress =3D=3D DeviceAddress) { + break; + } + } + if ((MapInfo =3D=3D NULL) || (MapInfo->DeviceAddress !=3D DeviceAddress)= ) { + DEBUG ((DEBUG_ERROR, "SyncDeviceHandleToMapInfo: DeviceAddress(0x%lx) = - not found\n", DeviceAddress)); + gBS->RestoreTPL (OriginalTpl); + return ; + } + + // + // Find MapHandleInfo according to DeviceHandle + // + MapHandleInfo =3D NULL; + for (Link =3D GetFirstNode (&MapInfo->HandleList) + ; !IsNull (&MapInfo->HandleList, Link) + ; Link =3D GetNextNode (&MapInfo->HandleList, Link) + ) { + MapHandleInfo =3D MAP_HANDLE_INFO_FROM_LINK (Link); + if (MapHandleInfo->DeviceHandle =3D=3D DeviceHandle) { + break; + } + } + if ((MapHandleInfo !=3D NULL) && (MapHandleInfo->DeviceHandle =3D=3D Dev= iceHandle)) { + MapHandleInfo->IoMmuAccess =3D IoMmuAccess; + gBS->RestoreTPL (OriginalTpl); + return ; + } + + // + // No DeviceHandle + // Initialize and insert the MAP_HANDLE_INFO structure + // + MapHandleInfo =3D AllocatePool (sizeof (MAP_HANDLE_INFO)); + if (MapHandleInfo =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "SyncDeviceHandleToMapInfo: %r\n", EFI_OUT_OF_RES= OURCES)); + gBS->RestoreTPL (OriginalTpl); + return ; + } + + MapHandleInfo->Signature =3D MAP_HANDLE_INFO_SIGNATURE; + MapHandleInfo->DeviceHandle =3D DeviceHandle; + MapHandleInfo->IoMmuAccess =3D IoMmuAccess; + + InsertTailList (&MapInfo->HandleList, &MapHandleInfo->Link); + gBS->RestoreTPL (OriginalTpl); + + return ; +} + +/** + Provides the controller-specific addresses required to access system mem= ory from a + DMA bus master. + + @param This The protocol instance pointer. + @param Operation Indicates if the bus master is going to re= ad or write to system memory. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes On input the number of bytes to map. On ou= tput the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned Numb= erOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a comm= on buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requ= ested address. + +**/ +EFI_STATUS +EFIAPI +IoMmuMap ( + IN EDKII_IOMMU_PROTOCOL *This, + IN EDKII_IOMMU_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + MAP_INFO *MapInfo; + EFI_PHYSICAL_ADDRESS DmaMemoryTop; + BOOLEAN NeedRemap; + EFI_TPL OriginalTpl; + + if (NumberOfBytes =3D=3D NULL || DeviceAddress =3D=3D NULL || + Mapping =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_INVALID_PARAMETER)); + return EFI_INVALID_PARAMETER; + } + + DEBUG ((DEBUG_VERBOSE, "IoMmuMap: =3D=3D> 0x%08x - 0x%08x (%x)\n", HostA= ddress, *NumberOfBytes, Operation)); + + // + // Make sure that Operation is valid + // + if ((UINT32) Operation >=3D EdkiiIoMmuOperationMaximum) { + DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_INVALID_PARAMETER)); + return EFI_INVALID_PARAMETER; + } + NeedRemap =3D FALSE; + PhysicalAddress =3D (EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress; + + DmaMemoryTop =3D DMA_MEMORY_TOP; + + // + // Alignment check + // + if ((*NumberOfBytes !=3D ALIGN_VALUE(*NumberOfBytes, SIZE_4KB)) || + (PhysicalAddress !=3D ALIGN_VALUE(PhysicalAddress, SIZE_4KB))) { + if ((Operation =3D=3D EdkiiIoMmuOperationBusMasterCommonBuffer) || + (Operation =3D=3D EdkiiIoMmuOperationBusMasterCommonBuffer64)) { + // + // The input buffer might be a subset from IoMmuAllocateBuffer. + // Skip the check. + // + } else { + NeedRemap =3D TRUE; + } + } + + if ((PhysicalAddress + *NumberOfBytes) >=3D DMA_MEMORY_TOP) { + NeedRemap =3D TRUE; + } + + if (((Operation !=3D EdkiiIoMmuOperationBusMasterRead64 && + Operation !=3D EdkiiIoMmuOperationBusMasterWrite64 && + Operation !=3D EdkiiIoMmuOperationBusMasterCommonBuffer64)) && + ((PhysicalAddress + *NumberOfBytes) > SIZE_4GB)) { + // + // If the root bridge or the device cannot handle performing DMA above + // 4GB but any part of the DMA transfer being mapped is above 4GB, then + // map the DMA transfer to a buffer below 4GB. + // + NeedRemap =3D TRUE; + DmaMemoryTop =3D MIN (DmaMemoryTop, SIZE_4GB - 1); + } + + if (Operation =3D=3D EdkiiIoMmuOperationBusMasterCommonBuffer || + Operation =3D=3D EdkiiIoMmuOperationBusMasterCommonBuffer64) { + if (NeedRemap) { + // + // Common Buffer operations can not be remapped. If the common buff= er + // is above 4GB, then it is not possible to generate a mapping, so r= eturn + // an error. + // + DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_UNSUPPORTED)); + return EFI_UNSUPPORTED; + } + } + + // + // Allocate a MAP_INFO structure to remember the mapping when Unmap() is + // called later. + // + MapInfo =3D AllocatePool (sizeof (MAP_INFO)); + if (MapInfo =3D=3D NULL) { + *NumberOfBytes =3D 0; + DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", EFI_OUT_OF_RESOURCES)); + return EFI_OUT_OF_RESOURCES; + } + + // + // Initialize the MAP_INFO structure + // + MapInfo->Signature =3D MAP_INFO_SIGNATURE; + MapInfo->Operation =3D Operation; + MapInfo->NumberOfBytes =3D *NumberOfBytes; + MapInfo->NumberOfPages =3D EFI_SIZE_TO_PAGES (MapInfo->NumberOfBytes= ); + MapInfo->HostAddress =3D PhysicalAddress; + MapInfo->DeviceAddress =3D DmaMemoryTop; + InitializeListHead(&MapInfo->HandleList); + + // + // Allocate a buffer below 4GB to map the transfer to. + // + if (NeedRemap) { + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiBootServicesData, + MapInfo->NumberOfPages, + &MapInfo->DeviceAddress + ); + if (EFI_ERROR (Status)) { + FreePool (MapInfo); + *NumberOfBytes =3D 0; + DEBUG ((DEBUG_ERROR, "IoMmuMap: %r\n", Status)); + return Status; + } + + // + // If this is a read operation from the Bus Master's point of view, + // then copy the contents of the real buffer into the mapped buffer + // so the Bus Master can read the contents of the real buffer. + // + if (Operation =3D=3D EdkiiIoMmuOperationBusMasterRead || + Operation =3D=3D EdkiiIoMmuOperationBusMasterRead64) { + CopyMem ( + (VOID *) (UINTN) MapInfo->DeviceAddress, + (VOID *) (UINTN) MapInfo->HostAddress, + MapInfo->NumberOfBytes + ); + } + } else { + MapInfo->DeviceAddress =3D MapInfo->HostAddress; + } + + OriginalTpl =3D gBS->RaiseTPL (VTD_TPL_LEVEL); + InsertTailList (&gMaps, &MapInfo->Link); + gBS->RestoreTPL (OriginalTpl); + + // + // The DeviceAddress is the address of the maped buffer below 4GB + // + *DeviceAddress =3D MapInfo->DeviceAddress; + // + // Return a pointer to the MAP_INFO structure in Mapping + // + *Mapping =3D MapInfo; + + DEBUG ((DEBUG_VERBOSE, "IoMmuMap: 0x%08x - 0x%08x <=3D=3D\n", *DeviceAdd= ress, *Mapping)); + + return EFI_SUCCESS; +} + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This The protocol instance pointer. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned b= y Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target s= ystem memory. +**/ +EFI_STATUS +EFIAPI +IoMmuUnmap ( + IN EDKII_IOMMU_PROTOCOL *This, + IN VOID *Mapping + ) +{ + MAP_INFO *MapInfo; + MAP_HANDLE_INFO *MapHandleInfo; + LIST_ENTRY *Link; + EFI_TPL OriginalTpl; + + DEBUG ((DEBUG_VERBOSE, "IoMmuUnmap: 0x%08x\n", Mapping)); + + if (Mapping =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "IoMmuUnmap: %r\n", EFI_INVALID_PARAMETER)); + return EFI_INVALID_PARAMETER; + } + + OriginalTpl =3D gBS->RaiseTPL (VTD_TPL_LEVEL); + MapInfo =3D NULL; + for (Link =3D GetFirstNode (&gMaps) + ; !IsNull (&gMaps, Link) + ; Link =3D GetNextNode (&gMaps, Link) + ) { + MapInfo =3D MAP_INFO_FROM_LINK (Link); + if (MapInfo =3D=3D Mapping) { + break; + } + } + // + // Mapping is not a valid value returned by Map() + // + if (MapInfo !=3D Mapping) { + gBS->RestoreTPL (OriginalTpl); + DEBUG ((DEBUG_ERROR, "IoMmuUnmap: %r\n", EFI_INVALID_PARAMETER)); + return EFI_INVALID_PARAMETER; + } + RemoveEntryList (&MapInfo->Link); + gBS->RestoreTPL (OriginalTpl); + + // + // remove all nodes in MapInfo->HandleList + // + while (!IsListEmpty (&MapInfo->HandleList)) { + MapHandleInfo =3D MAP_HANDLE_INFO_FROM_LINK (MapInfo->HandleList.Forwa= rdLink); + RemoveEntryList (&MapHandleInfo->Link); + FreePool (MapHandleInfo); + } + + if (MapInfo->DeviceAddress !=3D MapInfo->HostAddress) { + // + // If this is a write operation from the Bus Master's point of view, + // then copy the contents of the mapped buffer into the real buffer + // so the processor can read the contents of the real buffer. + // + if (MapInfo->Operation =3D=3D EdkiiIoMmuOperationBusMasterWrite || + MapInfo->Operation =3D=3D EdkiiIoMmuOperationBusMasterWrite64) { + CopyMem ( + (VOID *) (UINTN) MapInfo->HostAddress, + (VOID *) (UINTN) MapInfo->DeviceAddress, + MapInfo->NumberOfBytes + ); + } + + // + // Free the mapped buffer and the MAP_INFO structure. + // + gBS->FreePages (MapInfo->DeviceAddress, MapInfo->NumberOfPages); + } + + FreePool (Mapping); + return EFI_SUCCESS; +} + +/** + Allocates pages that are suitable for an OperationBusMasterCommonBuffer = or + OperationBusMasterCommonBuffer64 mapping. + + @param This The protocol instance pointer. + @param Type This parameter is not used and must be ign= ored. + @param MemoryType The type of memory to allocate, EfiBootSer= vicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory = address of the + allocated range. + @param Attributes The requested bit mask of attributes for t= he allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal = attribute bits are + MEMORY_WRITE_COMBINE, MEMORY_CACHED and DU= AL_ADDRESS_CYCLE. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +EFI_STATUS +EFIAPI +IoMmuAllocateBuffer ( + IN EDKII_IOMMU_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + + DEBUG ((DEBUG_VERBOSE, "IoMmuAllocateBuffer: =3D=3D> 0x%08x\n", Pages)); + + // + // Validate Attributes + // + if ((Attributes & EDKII_IOMMU_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) != =3D 0) { + DEBUG ((DEBUG_ERROR, "IoMmuAllocateBuffer: %r\n", EFI_UNSUPPORTED)); + return EFI_UNSUPPORTED; + } + + // + // Check for invalid inputs + // + if (HostAddress =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "IoMmuAllocateBuffer: %r\n", EFI_INVALID_PARAMETE= R)); + return EFI_INVALID_PARAMETER; + } + + // + // The only valid memory types are EfiBootServicesData and + // EfiRuntimeServicesData + // + if (MemoryType !=3D EfiBootServicesData && + MemoryType !=3D EfiRuntimeServicesData) { + DEBUG ((DEBUG_ERROR, "IoMmuAllocateBuffer: %r\n", EFI_INVALID_PARAMETE= R)); + return EFI_INVALID_PARAMETER; + } + + PhysicalAddress =3D DMA_MEMORY_TOP; + if ((Attributes & EDKII_IOMMU_ATTRIBUTE_DUAL_ADDRESS_CYCLE) =3D=3D 0) { + // + // Limit allocations to memory below 4GB + // + PhysicalAddress =3D MIN (PhysicalAddress, SIZE_4GB - 1); + } + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + MemoryType, + Pages, + &PhysicalAddress + ); + if (!EFI_ERROR (Status)) { + *HostAddress =3D (VOID *) (UINTN) PhysicalAddress; + } + + DEBUG ((DEBUG_VERBOSE, "IoMmuAllocateBuffer: 0x%08x <=3D=3D\n", *HostAdd= ress)); + + return Status; +} + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param This The protocol instance pointer. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allo= cated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress = and Pages + was not allocated with AllocateBuffer(). + +**/ +EFI_STATUS +EFIAPI +IoMmuFreeBuffer ( + IN EDKII_IOMMU_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ) +{ + DEBUG ((DEBUG_VERBOSE, "IoMmuFreeBuffer: 0x%\n", Pages)); + return gBS->FreePages ((EFI_PHYSICAL_ADDRESS) (UINTN) HostAddress, Pages= ); +} + +/** + Get device information from mapping. + + @param[in] Mapping The mapping. + @param[out] DeviceAddress The device address of the mapping. + @param[out] NumberOfPages The number of pages of the mapping. + + @retval EFI_SUCCESS The device information is returned. + @retval EFI_INVALID_PARAMETER The mapping is invalid. +**/ +EFI_STATUS +GetDeviceInfoFromMapping ( + IN VOID *Mapping, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT UINTN *NumberOfPages + ) +{ + MAP_INFO *MapInfo; + LIST_ENTRY *Link; + + if (Mapping =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + MapInfo =3D NULL; + for (Link =3D GetFirstNode (&gMaps) + ; !IsNull (&gMaps, Link) + ; Link =3D GetNextNode (&gMaps, Link) + ) { + MapInfo =3D MAP_INFO_FROM_LINK (Link); + if (MapInfo =3D=3D Mapping) { + break; + } + } + // + // Mapping is not a valid value returned by Map() + // + if (MapInfo !=3D Mapping) { + return EFI_INVALID_PARAMETER; + } + + *DeviceAddress =3D MapInfo->DeviceAddress; + *NumberOfPages =3D MapInfo->NumberOfPages; + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProte= ction.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtecti= on.c new file mode 100644 index 0000000000..956ebb2d3d --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c @@ -0,0 +1,683 @@ +/** @file + + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DmaProtection.h" + +UINT64 mBelow4GMemoryLimit; +UINT64 mAbove4GMemoryLimit; + +EDKII_PLATFORM_VTD_POLICY_PROTOCOL *mPlatformVTdPolicy; + +VTD_ACCESS_REQUEST *mAccessRequest =3D NULL; +UINTN mAccessRequestCount =3D 0; +UINTN mAccessRequestMaxCount =3D 0; + +/** + Append VTd Access Request to global. + + @param[in] Segment The Segment used to identify a VTd engine. + @param[in] SourceId The SourceId used to identify a VTd engine= and table entry. + @param[in] BaseAddress The base of device memory address to be us= ed as the DMA memory. + @param[in] Length The length of device memory address to be = used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory rang= e specified by BaseAddress and Length. + @retval EFI_INVALID_PARAMETER BaseAddress is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is 0. + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinati= on of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not support= ed by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory rang= e specified by BaseAddress and Length. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available t= o modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while a= ttempting the operation. + +**/ +EFI_STATUS +RequestAccessAttribute ( + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ) +{ + VTD_ACCESS_REQUEST *NewAccessRequest; + UINTN Index; + + // + // Optimization for memory. + // + // If the last record is to IoMmuAccess=3D0, + // Check previous records and remove the matched entry. + // + if (IoMmuAccess =3D=3D 0) { + for (Index =3D 0; Index < mAccessRequestCount; Index++) { + if ((mAccessRequest[Index].Segment =3D=3D Segment) && + (mAccessRequest[Index].SourceId.Uint16 =3D=3D SourceId.Uint16) && + (mAccessRequest[Index].BaseAddress =3D=3D BaseAddress) && + (mAccessRequest[Index].Length =3D=3D Length) && + (mAccessRequest[Index].IoMmuAccess !=3D 0)) { + // + // Remove this record [Index]. + // No need to add the new record. + // + if (Index !=3D mAccessRequestCount - 1) { + CopyMem ( + &mAccessRequest[Index], + &mAccessRequest[Index + 1], + sizeof (VTD_ACCESS_REQUEST) * (mAccessRequestCount - 1 - Index) + ); + } + ZeroMem (&mAccessRequest[mAccessRequestCount - 1], sizeof(VTD_ACCE= SS_REQUEST)); + mAccessRequestCount--; + return EFI_SUCCESS; + } + } + } + + if (mAccessRequestCount >=3D mAccessRequestMaxCount) { + NewAccessRequest =3D AllocateZeroPool (sizeof(*NewAccessRequest) * (mA= ccessRequestMaxCount + MAX_VTD_ACCESS_REQUEST)); + if (NewAccessRequest =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + mAccessRequestMaxCount +=3D MAX_VTD_ACCESS_REQUEST; + if (mAccessRequest !=3D NULL) { + CopyMem (NewAccessRequest, mAccessRequest, sizeof(*NewAccessRequest)= * mAccessRequestCount); + FreePool (mAccessRequest); + } + mAccessRequest =3D NewAccessRequest; + } + + ASSERT (mAccessRequestCount < mAccessRequestMaxCount); + + mAccessRequest[mAccessRequestCount].Segment =3D Segment; + mAccessRequest[mAccessRequestCount].SourceId =3D SourceId; + mAccessRequest[mAccessRequestCount].BaseAddress =3D BaseAddress; + mAccessRequest[mAccessRequestCount].Length =3D Length; + mAccessRequest[mAccessRequestCount].IoMmuAccess =3D IoMmuAccess; + + mAccessRequestCount++; + + return EFI_SUCCESS; +} + +/** + Process Access Requests from before DMAR table is installed. + +**/ +VOID +ProcessRequestedAccessAttribute ( + VOID + ) +{ + UINTN Index; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "ProcessRequestedAccessAttribute ...\n")); + + for (Index =3D 0; Index < mAccessRequestCount; Index++) { + DEBUG (( + DEBUG_INFO, + "PCI(S%x.B%x.D%x.F%x) ", + mAccessRequest[Index].Segment, + mAccessRequest[Index].SourceId.Bits.Bus, + mAccessRequest[Index].SourceId.Bits.Device, + mAccessRequest[Index].SourceId.Bits.Function + )); + DEBUG (( + DEBUG_INFO, + "(0x%lx~0x%lx) - %lx\n", + mAccessRequest[Index].BaseAddress, + mAccessRequest[Index].Length, + mAccessRequest[Index].IoMmuAccess + )); + Status =3D SetAccessAttribute ( + mAccessRequest[Index].Segment, + mAccessRequest[Index].SourceId, + mAccessRequest[Index].BaseAddress, + mAccessRequest[Index].Length, + mAccessRequest[Index].IoMmuAccess + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SetAccessAttribute %r: ", Status)); + } + } + + if (mAccessRequest !=3D NULL) { + FreePool (mAccessRequest); + } + mAccessRequest =3D NULL; + mAccessRequestCount =3D 0; + mAccessRequestMaxCount =3D 0; + + DEBUG ((DEBUG_INFO, "ProcessRequestedAccessAttribute Done\n")); +} + +/** + return the UEFI memory information. + + @param[out] Below4GMemoryLimit The below 4GiB memory limit + @param[out] Above4GMemoryLimit The above 4GiB memory limit +**/ +VOID +ReturnUefiMemoryMap ( + OUT UINT64 *Below4GMemoryLimit, + OUT UINT64 *Above4GMemoryLimit + ) +{ + EFI_STATUS Status; + EFI_MEMORY_DESCRIPTOR *EfiMemoryMap; + EFI_MEMORY_DESCRIPTOR *EfiMemoryMapEnd; + EFI_MEMORY_DESCRIPTOR *EfiEntry; + EFI_MEMORY_DESCRIPTOR *NextEfiEntry; + EFI_MEMORY_DESCRIPTOR TempEfiEntry; + UINTN EfiMemoryMapSize; + UINTN EfiMapKey; + UINTN EfiDescriptorSize; + UINT32 EfiDescriptorVersion; + UINT64 MemoryBlockLength; + + *Below4GMemoryLimit =3D 0; + *Above4GMemoryLimit =3D 0; + + // + // Get the EFI memory map. + // + EfiMemoryMapSize =3D 0; + EfiMemoryMap =3D NULL; + Status =3D gBS->GetMemoryMap ( + &EfiMemoryMapSize, + EfiMemoryMap, + &EfiMapKey, + &EfiDescriptorSize, + &EfiDescriptorVersion + ); + ASSERT (Status =3D=3D EFI_BUFFER_TOO_SMALL); + + do { + // + // Use size returned back plus 1 descriptor for the AllocatePool. + // We don't just multiply by 2 since the "for" loop below terminates on + // EfiMemoryMapEnd which is dependent upon EfiMemoryMapSize. Otherwize + // we process bogus entries and create bogus E820 entries. + // + EfiMemoryMap =3D (EFI_MEMORY_DESCRIPTOR *) AllocatePool (EfiMemoryMapS= ize); + ASSERT (EfiMemoryMap !=3D NULL); + Status =3D gBS->GetMemoryMap ( + &EfiMemoryMapSize, + EfiMemoryMap, + &EfiMapKey, + &EfiDescriptorSize, + &EfiDescriptorVersion + ); + if (EFI_ERROR (Status)) { + FreePool (EfiMemoryMap); + } + } while (Status =3D=3D EFI_BUFFER_TOO_SMALL); + + ASSERT_EFI_ERROR (Status); + + // + // Sort memory map from low to high + // + EfiEntry =3D EfiMemoryMap; + NextEfiEntry =3D NEXT_MEMORY_DESCRIPTOR (EfiEntry, EfiDescriptorSize); + EfiMemoryMapEnd =3D (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) EfiMemoryMap + = EfiMemoryMapSize); + while (EfiEntry < EfiMemoryMapEnd) { + while (NextEfiEntry < EfiMemoryMapEnd) { + if (EfiEntry->PhysicalStart > NextEfiEntry->PhysicalStart) { + CopyMem (&TempEfiEntry, EfiEntry, sizeof (EFI_MEMORY_DESCRIPTOR)); + CopyMem (EfiEntry, NextEfiEntry, sizeof (EFI_MEMORY_DESCRIPTOR)); + CopyMem (NextEfiEntry, &TempEfiEntry, sizeof (EFI_MEMORY_DESCRIPTO= R)); + } + + NextEfiEntry =3D NEXT_MEMORY_DESCRIPTOR (NextEfiEntry, EfiDescriptor= Size); + } + + EfiEntry =3D NEXT_MEMORY_DESCRIPTOR (EfiEntry, EfiDescriptorSize); + NextEfiEntry =3D NEXT_MEMORY_DESCRIPTOR (EfiEntry, EfiDescriptorSize); + } + + // + // + // + DEBUG ((DEBUG_INFO, "MemoryMap:\n")); + EfiEntry =3D EfiMemoryMap; + EfiMemoryMapEnd =3D (EFI_MEMORY_DESCRIPTOR *) ((UINT8 *) EfiMemoryMap + = EfiMemoryMapSize); + while (EfiEntry < EfiMemoryMapEnd) { + MemoryBlockLength =3D (UINT64) (LShiftU64 (EfiEntry->NumberOfPages, 12= )); + DEBUG ((DEBUG_INFO, "Entry(0x%02x) 0x%016lx - 0x%016lx\n", EfiEntry->T= ype, EfiEntry->PhysicalStart, EfiEntry->PhysicalStart + MemoryBlockLength)); + switch (EfiEntry->Type) { + case EfiLoaderCode: + case EfiLoaderData: + case EfiBootServicesCode: + case EfiBootServicesData: + case EfiConventionalMemory: + case EfiRuntimeServicesCode: + case EfiRuntimeServicesData: + case EfiACPIReclaimMemory: + case EfiACPIMemoryNVS: + case EfiReservedMemoryType: + if ((EfiEntry->PhysicalStart + MemoryBlockLength) <=3D BASE_1MB) { + // + // Skip the memory block is under 1MB + // + } else if (EfiEntry->PhysicalStart >=3D BASE_4GB) { + if (*Above4GMemoryLimit < EfiEntry->PhysicalStart + MemoryBlockLen= gth) { + *Above4GMemoryLimit =3D EfiEntry->PhysicalStart + MemoryBlockLen= gth; + } + } else { + if (*Below4GMemoryLimit < EfiEntry->PhysicalStart + MemoryBlockLen= gth) { + *Below4GMemoryLimit =3D EfiEntry->PhysicalStart + MemoryBlockLen= gth; + } + } + break; + } + EfiEntry =3D NEXT_MEMORY_DESCRIPTOR (EfiEntry, EfiDescriptorSize); + } + + FreePool (EfiMemoryMap); + + DEBUG ((DEBUG_INFO, "Result:\n")); + DEBUG ((DEBUG_INFO, "Below4GMemoryLimit: 0x%016lx\n", *Below4GMemoryLim= it)); + DEBUG ((DEBUG_INFO, "Above4GMemoryLimit: 0x%016lx\n", *Above4GMemoryLim= it)); + + return ; +} + +/** + The scan bus callback function to always enable page attribute. + + @param[in] Context The context of the callback. + @param[in] Segment The segment of the source. + @param[in] Bus The bus of the source. + @param[in] Device The device of the source. + @param[in] Function The function of the source. + + @retval EFI_SUCCESS The VTd entry is updated to always enable = all DMA access for the specific device. +**/ +EFI_STATUS +EFIAPI +ScanBusCallbackAlwaysEnablePageAttribute ( + IN VOID *Context, + IN UINT16 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function + ) +{ + VTD_SOURCE_ID SourceId; + EFI_STATUS Status; + + SourceId.Bits.Bus =3D Bus; + SourceId.Bits.Device =3D Device; + SourceId.Bits.Function =3D Function; + Status =3D AlwaysEnablePageAttribute (Segment, SourceId); + return Status; +} + +/** + Always enable the VTd page attribute for the device in the DeviceScope. + + @param[in] DeviceScope the input device scope data structure + + @retval EFI_SUCCESS The VTd entry is updated to always enable = all DMA access for the specific device in the device scope. +**/ +EFI_STATUS +AlwaysEnablePageAttributeDeviceScope ( + IN EDKII_PLATFORM_VTD_DEVICE_SCOPE *DeviceScope + ) +{ + UINT8 Bus; + UINT8 Device; + UINT8 Function; + VTD_SOURCE_ID SourceId; + UINT8 SecondaryBusNumber; + EFI_STATUS Status; + + Status =3D GetPciBusDeviceFunction (DeviceScope->SegmentNumber, &DeviceS= cope->DeviceScope, &Bus, &Device, &Function); + + if (DeviceScope->DeviceScope.Type =3D=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYP= E_PCI_BRIDGE) { + // + // Need scan the bridge and add all devices. + // + SecondaryBusNumber =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Device= Scope->SegmentNumber, Bus, Device, Function, PCI_BRIDGE_SECONDARY_BUS_REGIS= TER_OFFSET)); + Status =3D ScanPciBus (NULL, DeviceScope->SegmentNumber, SecondaryBusN= umber, ScanBusCallbackAlwaysEnablePageAttribute); + return Status; + } else { + SourceId.Bits.Bus =3D Bus; + SourceId.Bits.Device =3D Device; + SourceId.Bits.Function =3D Function; + Status =3D AlwaysEnablePageAttribute (DeviceScope->SegmentNumber, Sour= ceId); + return Status; + } +} + +/** + Always enable the VTd page attribute for the device matching DeviceId. + + @param[in] PciDeviceId the input PCI device ID + + @retval EFI_SUCCESS The VTd entry is updated to always enable = all DMA access for the specific device matching DeviceId. +**/ +EFI_STATUS +AlwaysEnablePageAttributePciDeviceId ( + IN EDKII_PLATFORM_VTD_PCI_DEVICE_ID *PciDeviceId + ) +{ + UINTN VtdIndex; + UINTN PciIndex; + PCI_DEVICE_DATA *PciDeviceData; + EFI_STATUS Status; + + for (VtdIndex =3D 0; VtdIndex < mVtdUnitNumber; VtdIndex++) { + for (PciIndex =3D 0; PciIndex < mVtdUnitInformation[VtdIndex].PciDevic= eInfo.PciDeviceDataNumber; PciIndex++) { + PciDeviceData =3D &mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDe= viceData[PciIndex]; + + if (((PciDeviceId->VendorId =3D=3D 0xFFFF) || (PciDeviceId->VendorId= =3D=3D PciDeviceData->PciDeviceId.VendorId)) && + ((PciDeviceId->DeviceId =3D=3D 0xFFFF) || (PciDeviceId->DeviceId= =3D=3D PciDeviceData->PciDeviceId.DeviceId)) && + ((PciDeviceId->RevisionId =3D=3D 0xFF) || (PciDeviceId->Revision= Id =3D=3D PciDeviceData->PciDeviceId.RevisionId)) && + ((PciDeviceId->SubsystemVendorId =3D=3D 0xFFFF) || (PciDeviceId-= >SubsystemVendorId =3D=3D PciDeviceData->PciDeviceId.SubsystemVendorId)) && + ((PciDeviceId->SubsystemDeviceId =3D=3D 0xFFFF) || (PciDeviceId-= >SubsystemDeviceId =3D=3D PciDeviceData->PciDeviceId.SubsystemDeviceId)) ) { + Status =3D AlwaysEnablePageAttribute (mVtdUnitInformation[VtdIndex= ].Segment, PciDeviceData->PciSourceId); + if (EFI_ERROR(Status)) { + continue; + } + } + } + } + return EFI_SUCCESS; +} + +/** + Always enable the VTd page attribute for the device. + + @param[in] DeviceInfo the exception device information + + @retval EFI_SUCCESS The VTd entry is updated to always enable = all DMA access for the specific device in the device info. +**/ +EFI_STATUS +AlwaysEnablePageAttributeExceptionDeviceInfo ( + IN EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO *DeviceInfo + ) +{ + switch (DeviceInfo->Type) { + case EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_DEVICE_SCOPE: + return AlwaysEnablePageAttributeDeviceScope ((VOID *)(DeviceInfo + 1)); + case EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_PCI_DEVICE_ID: + return AlwaysEnablePageAttributePciDeviceId ((VOID *)(DeviceInfo + 1)); + default: + return EFI_UNSUPPORTED; + } +} + +/** + Initialize platform VTd policy. +**/ +VOID +InitializePlatformVTdPolicy ( + VOID + ) +{ + EFI_STATUS Status; + UINTN DeviceInfoCount; + VOID *DeviceInfo; + EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO *ThisDeviceInfo; + UINTN Index; + + // + // It is optional. + // + Status =3D gBS->LocateProtocol ( + &gEdkiiPlatformVTdPolicyProtocolGuid, + NULL, + (VOID **)&mPlatformVTdPolicy + ); + if (!EFI_ERROR(Status)) { + DEBUG ((DEBUG_INFO, "InitializePlatformVTdPolicy\n")); + Status =3D mPlatformVTdPolicy->GetExceptionDeviceList (mPlatformVTdPol= icy, &DeviceInfoCount, &DeviceInfo); + if (!EFI_ERROR(Status)) { + ThisDeviceInfo =3D DeviceInfo; + for (Index =3D 0; Index < DeviceInfoCount; Index++) { + if (ThisDeviceInfo->Type =3D=3D EDKII_PLATFORM_VTD_EXCEPTION_DEVIC= E_INFO_TYPE_END) { + break; + } + AlwaysEnablePageAttributeExceptionDeviceInfo (ThisDeviceInfo); + ThisDeviceInfo =3D (VOID *)((UINTN)ThisDeviceInfo + ThisDeviceInfo= ->Length); + } + FreePool (DeviceInfo); + } + } +} + +/** + Setup VTd engine. +**/ +VOID +SetupVtd ( + VOID + ) +{ + EFI_STATUS Status; + VOID *PciEnumerationComplete; + UINTN Index; + UINT64 Below4GMemoryLimit; + UINT64 Above4GMemoryLimit; + + // + // PCI Enumeration must be done + // + Status =3D gBS->LocateProtocol ( + &gEfiPciEnumerationCompleteProtocolGuid, + NULL, + &PciEnumerationComplete + ); + ASSERT_EFI_ERROR (Status); + + ReturnUefiMemoryMap (&Below4GMemoryLimit, &Above4GMemoryLimit); + Below4GMemoryLimit =3D ALIGN_VALUE_UP(Below4GMemoryLimit, SIZE_256MB); + DEBUG ((DEBUG_INFO, " Adjusted Below4GMemoryLimit: 0x%016lx\n", Below4GM= emoryLimit)); + + mBelow4GMemoryLimit =3D Below4GMemoryLimit; + mAbove4GMemoryLimit =3D Above4GMemoryLimit; + + // + // 1. setup + // + DEBUG ((DEBUG_INFO, "ParseDmarAcpiTable\n")); + Status =3D ParseDmarAcpiTableDrhd (); + if (EFI_ERROR (Status)) { + return; + } + DEBUG ((DEBUG_INFO, "PrepareVtdConfig\n")); + PrepareVtdConfig (); + + // + // 2. initialization + // + DEBUG ((DEBUG_INFO, "SetupTranslationTable\n")); + Status =3D SetupTranslationTable (); + if (EFI_ERROR (Status)) { + return; + } + + InitializePlatformVTdPolicy (); + + ParseDmarAcpiTableRmrr (); + + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) =3D=3D 0) { + // + // Support IOMMU access attribute request recording before DMAR table = is installed. + // Here is to process the requests. + // + ProcessRequestedAccessAttribute (); + } + + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + DEBUG ((DEBUG_INFO,"VTD Unit %d (Segment: %04x)\n", Index, mVtdUnitInf= ormation[Index].Segment)); + if (mVtdUnitInformation[Index].ExtRootEntryTable !=3D NULL) { + DumpDmarExtContextEntryTable (mVtdUnitInformation[Index].ExtRootEntr= yTable); + } + if (mVtdUnitInformation[Index].RootEntryTable !=3D NULL) { + DumpDmarContextEntryTable (mVtdUnitInformation[Index].RootEntryTable= ); + } + } + + // + // 3. enable + // + DEBUG ((DEBUG_INFO, "EnableDmar\n")); + Status =3D EnableDmar (); + if (EFI_ERROR (Status)) { + return; + } + DEBUG ((DEBUG_INFO, "DumpVtdRegs\n")); + DumpVtdRegsAll (); +} + +/** + Notification function of ACPI Table change. + + This is a notification function registered on ACPI Table change event. + + @param Event Event whose notification function is being invoked. + @param Context Pointer to the notification function's context. + +**/ +VOID +EFIAPI +AcpiNotificationFunc ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + + Status =3D GetDmarAcpiTable (); + if (EFI_ERROR (Status)) { + if (Status =3D=3D EFI_ALREADY_STARTED) { + gBS->CloseEvent (Event); + } + return; + } + SetupVtd (); + gBS->CloseEvent (Event); +} + +/** + Exit boot service callback function. + + @param[in] Event The event handle. + @param[in] Context The event content. +**/ +VOID +EFIAPI +OnExitBootServices ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN VtdIndex; + + DEBUG ((DEBUG_INFO, "Vtd OnExitBootServices\n")); + DumpVtdRegsAll (); + + DEBUG ((DEBUG_INFO, "Invalidate all\n")); + for (VtdIndex =3D 0; VtdIndex < mVtdUnitNumber; VtdIndex++) { + FlushWriteBuffer (VtdIndex); + + InvalidateContextCache (VtdIndex); + + InvalidateIOTLB (VtdIndex); + } + + if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT1) =3D=3D 0) { + DisableDmar (); + DumpVtdRegsAll (); + } +} + +/** + Legacy boot callback function. + + @param[in] Event The event handle. + @param[in] Context The event content. +**/ +VOID +EFIAPI +OnLegacyBoot ( + EFI_EVENT Event, + VOID *Context + ) +{ + DEBUG ((DEBUG_INFO, "Vtd OnLegacyBoot\n")); + DumpVtdRegsAll (); + DisableDmar (); + DumpVtdRegsAll (); +} + +/** + Initialize DMA protection. +**/ +VOID +InitializeDmaProtection ( + VOID + ) +{ + EFI_STATUS Status; + EFI_EVENT ExitBootServicesEvent; + EFI_EVENT LegacyBootEvent; + EFI_EVENT EventAcpi10; + EFI_EVENT EventAcpi20; + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + VTD_TPL_LEVEL, + AcpiNotificationFunc, + NULL, + &gEfiAcpi10TableGuid, + &EventAcpi10 + ); + ASSERT_EFI_ERROR (Status); + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + VTD_TPL_LEVEL, + AcpiNotificationFunc, + NULL, + &gEfiAcpi20TableGuid, + &EventAcpi20 + ); + ASSERT_EFI_ERROR (Status); + + // + // Signal the events initially for the case + // that DMAR table has been installed. + // + gBS->SignalEvent (EventAcpi20); + gBS->SignalEvent (EventAcpi10); + + Status =3D gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + OnExitBootServices, + NULL, + &gEfiEventExitBootServicesGuid, + &ExitBootServicesEvent + ); + ASSERT_EFI_ERROR (Status); + + Status =3D EfiCreateEventLegacyBootEx ( + TPL_CALLBACK, + OnLegacyBoot, + NULL, + &LegacyBootEvent + ); + ASSERT_EFI_ERROR (Status); + + return ; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpi= Table.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTab= le.c new file mode 100644 index 0000000000..52bc189078 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmarAcpiTable.c @@ -0,0 +1,890 @@ +/** @file + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DmaProtection.h" + +#pragma pack(1) + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT32 Entry; +} RSDT_TABLE; + +typedef struct { + EFI_ACPI_DESCRIPTION_HEADER Header; + UINT64 Entry; +} XSDT_TABLE; + +#pragma pack() + +EFI_ACPI_DMAR_HEADER *mAcpiDmarTable =3D NULL; + +/** + Dump DMAR DeviceScopeEntry. + + @param[in] DmarDeviceScopeEntry DMAR DeviceScopeEntry +**/ +VOID +DumpDmarDeviceScopeEntry ( + IN EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry + ) +{ + UINTN PciPathNumber; + UINTN PciPathIndex; + EFI_ACPI_DMAR_PCI_PATH *PciPath; + + if (DmarDeviceScopeEntry =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *****************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * DMA-Remapping Device Scope Entry Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *****************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " DMAR Device Scope Entry address ...................... 0x%016lx\n= " : + " DMAR Device Scope Entry address ...................... 0x%08x\n", + DmarDeviceScopeEntry + )); + DEBUG ((DEBUG_INFO, + " Device Scope Entry Type ............................ 0x%02x\n", + DmarDeviceScopeEntry->Type + )); + switch (DmarDeviceScopeEntry->Type) { + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT: + DEBUG ((DEBUG_INFO, + " PCI Endpoint Device\n" + )); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE: + DEBUG ((DEBUG_INFO, + " PCI Sub-hierachy\n" + )); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC: + DEBUG ((DEBUG_INFO, + " IOAPIC\n" + )); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET: + DEBUG ((DEBUG_INFO, + " MSI Capable HPET\n" + )); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE: + DEBUG ((DEBUG_INFO, + " ACPI Namespace Device\n" + )); + break; + default: + break; + } + DEBUG ((DEBUG_INFO, + " Length ............................................. 0x%02x\n", + DmarDeviceScopeEntry->Length + )); + DEBUG ((DEBUG_INFO, + " Enumeration ID ..................................... 0x%02x\n", + DmarDeviceScopeEntry->EnumerationId + )); + DEBUG ((DEBUG_INFO, + " Starting Bus Number ................................ 0x%02x\n", + DmarDeviceScopeEntry->StartBusNumber + )); + + PciPathNumber =3D (DmarDeviceScopeEntry->Length - sizeof(EFI_ACPI_DMAR_D= EVICE_SCOPE_STRUCTURE_HEADER)) / sizeof(EFI_ACPI_DMAR_PCI_PATH); + PciPath =3D (EFI_ACPI_DMAR_PCI_PATH *)(DmarDeviceScopeEntry + 1); + for (PciPathIndex =3D 0; PciPathIndex < PciPathNumber; PciPathIndex++) { + DEBUG ((DEBUG_INFO, + " Device ............................................. 0x%02x\n= ", + PciPath[PciPathIndex].Device + )); + DEBUG ((DEBUG_INFO, + " Function ........................................... 0x%02x\n= ", + PciPath[PciPathIndex].Function + )); + } + + DEBUG ((DEBUG_INFO, + " *****************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR ANDD table. + + @param[in] Andd DMAR ANDD table +**/ +VOID +DumpDmarAndd ( + IN EFI_ACPI_DMAR_ANDD_HEADER *Andd + ) +{ + if (Andd =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * ACPI Name-space Device Declaration Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " ANDD address ........................................... 0x%016lx\n= " : + " ANDD address ........................................... 0x%08x\n", + Andd + )); + DEBUG ((DEBUG_INFO, + " Type ................................................. 0x%04x\n", + Andd->Header.Type + )); + DEBUG ((DEBUG_INFO, + " Length ............................................... 0x%04x\n", + Andd->Header.Length + )); + DEBUG ((DEBUG_INFO, + " ACPI Device Number ................................... 0x%02x\n", + Andd->AcpiDeviceNumber + )); + DEBUG ((DEBUG_INFO, + " ACPI Object Name ..................................... '%a'\n", + (Andd + 1) + )); + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR RHSA table. + + @param[in] Rhsa DMAR RHSA table +**/ +VOID +DumpDmarRhsa ( + IN EFI_ACPI_DMAR_RHSA_HEADER *Rhsa + ) +{ + if (Rhsa =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * Remapping Hardware Status Affinity Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " RHSA address ........................................... 0x%016lx\n= " : + " RHSA address ........................................... 0x%08x\n", + Rhsa + )); + DEBUG ((DEBUG_INFO, + " Type ................................................. 0x%04x\n", + Rhsa->Header.Type + )); + DEBUG ((DEBUG_INFO, + " Length ............................................... 0x%04x\n", + Rhsa->Header.Length + )); + DEBUG ((DEBUG_INFO, + " Register Base Address ................................ 0x%016lx\n= ", + Rhsa->RegisterBaseAddress + )); + DEBUG ((DEBUG_INFO, + " Proximity Domain ..................................... 0x%08x\n", + Rhsa->ProximityDomain + )); + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR ATSR table. + + @param[in] Atsr DMAR ATSR table +**/ +VOID +DumpDmarAtsr ( + IN EFI_ACPI_DMAR_ATSR_HEADER *Atsr + ) +{ + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry; + INTN AtsrLen; + + if (Atsr =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * Root Port ATS Capability Reporting Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " ATSR address ........................................... 0x%016lx\n= " : + " ATSR address ........................................... 0x%08x\n", + Atsr + )); + DEBUG ((DEBUG_INFO, + " Type ................................................. 0x%04x\n", + Atsr->Header.Type + )); + DEBUG ((DEBUG_INFO, + " Length ............................................... 0x%04x\n", + Atsr->Header.Length + )); + DEBUG ((DEBUG_INFO, + " Flags ................................................ 0x%02x\n", + Atsr->Flags + )); + DEBUG ((DEBUG_INFO, + " ALL_PORTS .......................................... 0x%02x\n", + Atsr->Flags & EFI_ACPI_DMAR_ATSR_FLAGS_ALL_PORTS + )); + DEBUG ((DEBUG_INFO, + " Segment Number ....................................... 0x%04x\n", + Atsr->SegmentNumber + )); + + AtsrLen =3D Atsr->Header.Length - sizeof(EFI_ACPI_DMAR_ATSR_HEADER); + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)= (Atsr + 1); + while (AtsrLen > 0) { + DumpDmarDeviceScopeEntry (DmarDeviceScopeEntry); + AtsrLen -=3D DmarDeviceScopeEntry->Length; + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER = *)((UINTN)DmarDeviceScopeEntry + DmarDeviceScopeEntry->Length); + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR RMRR table. + + @param[in] Rmrr DMAR RMRR table +**/ +VOID +DumpDmarRmrr ( + IN EFI_ACPI_DMAR_RMRR_HEADER *Rmrr + ) +{ + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry; + INTN RmrrLen; + + if (Rmrr =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * Reserved Memory Region Reporting Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " RMRR address ........................................... 0x%016lx\n= " : + " RMRR address ........................................... 0x%08x\n", + Rmrr + )); + DEBUG ((DEBUG_INFO, + " Type ................................................. 0x%04x\n", + Rmrr->Header.Type + )); + DEBUG ((DEBUG_INFO, + " Length ............................................... 0x%04x\n", + Rmrr->Header.Length + )); + DEBUG ((DEBUG_INFO, + " Segment Number ....................................... 0x%04x\n", + Rmrr->SegmentNumber + )); + DEBUG ((DEBUG_INFO, + " Reserved Memory Region Base Address .................. 0x%016lx\n= ", + Rmrr->ReservedMemoryRegionBaseAddress + )); + DEBUG ((DEBUG_INFO, + " Reserved Memory Region Limit Address ................. 0x%016lx\n= ", + Rmrr->ReservedMemoryRegionLimitAddress + )); + + RmrrLen =3D Rmrr->Header.Length - sizeof(EFI_ACPI_DMAR_RMRR_HEADER); + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)= (Rmrr + 1); + while (RmrrLen > 0) { + DumpDmarDeviceScopeEntry (DmarDeviceScopeEntry); + RmrrLen -=3D DmarDeviceScopeEntry->Length; + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER = *)((UINTN)DmarDeviceScopeEntry + DmarDeviceScopeEntry->Length); + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR DRHD table. + + @param[in] Drhd DMAR DRHD table +**/ +VOID +DumpDmarDrhd ( + IN EFI_ACPI_DMAR_DRHD_HEADER *Drhd + ) +{ + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry; + INTN DrhdLen; + + if (Drhd =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * DMA-Remapping Hardware Definition Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " DRHD address ........................................... 0x%016lx\n= " : + " DRHD address ........................................... 0x%08x\n", + Drhd + )); + DEBUG ((DEBUG_INFO, + " Type ................................................. 0x%04x\n", + Drhd->Header.Type + )); + DEBUG ((DEBUG_INFO, + " Length ............................................... 0x%04x\n", + Drhd->Header.Length + )); + DEBUG ((DEBUG_INFO, + " Flags ................................................ 0x%02x\n", + Drhd->Flags + )); + DEBUG ((DEBUG_INFO, + " INCLUDE_PCI_ALL .................................... 0x%02x\n", + Drhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL + )); + DEBUG ((DEBUG_INFO, + " Segment Number ....................................... 0x%04x\n", + Drhd->SegmentNumber + )); + DEBUG ((DEBUG_INFO, + " Register Base Address ................................ 0x%016lx\n= ", + Drhd->RegisterBaseAddress + )); + + DrhdLen =3D Drhd->Header.Length - sizeof(EFI_ACPI_DMAR_DRHD_HEADER); + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)= (Drhd + 1); + while (DrhdLen > 0) { + DumpDmarDeviceScopeEntry (DmarDeviceScopeEntry); + DrhdLen -=3D DmarDeviceScopeEntry->Length; + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER = *)((UINTN)DmarDeviceScopeEntry + DmarDeviceScopeEntry->Length); + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR ACPI table. + + @param[in] Dmar DMAR ACPI table +**/ +VOID +DumpAcpiDMAR ( + IN EFI_ACPI_DMAR_HEADER *Dmar + ) +{ + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + INTN DmarLen; + + if (Dmar =3D=3D NULL) { + return; + } + + // + // Dump Dmar table + // + DEBUG ((DEBUG_INFO, + "*********************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + "* DMAR Table = *\n" + )); + DEBUG ((DEBUG_INFO, + "*********************************************************************= ********\n" + )); + + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + "DMAR address ............................................. 0x%016lx\n= " : + "DMAR address ............................................. 0x%08x\n", + Dmar + )); + + DEBUG ((DEBUG_INFO, + " Table Contents:\n" + )); + DEBUG ((DEBUG_INFO, + " Host Address Width ................................... 0x%02x\n", + Dmar->HostAddressWidth + )); + DEBUG ((DEBUG_INFO, + " Flags ................................................ 0x%02x\n", + Dmar->Flags + )); + DEBUG ((DEBUG_INFO, + " INTR_REMAP ......................................... 0x%02x\n", + Dmar->Flags & EFI_ACPI_DMAR_FLAGS_INTR_REMAP + )); + DEBUG ((DEBUG_INFO, + " X2APIC_OPT_OUT_SET ................................. 0x%02x\n", + Dmar->Flags & EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT + )); + DEBUG ((DEBUG_INFO, + " DMA_CTRL_PLATFORM_OPT_IN_FLAG ...................... 0x%02x\n", + Dmar->Flags & EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG + )); + + DmarLen =3D Dmar->Header.Length - sizeof(EFI_ACPI_DMAR_HEADER); + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)(Dmar + 1); + while (DmarLen > 0) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + DumpDmarDrhd ((EFI_ACPI_DMAR_DRHD_HEADER *)DmarHeader); + break; + case EFI_ACPI_DMAR_TYPE_RMRR: + DumpDmarRmrr ((EFI_ACPI_DMAR_RMRR_HEADER *)DmarHeader); + break; + case EFI_ACPI_DMAR_TYPE_ATSR: + DumpDmarAtsr ((EFI_ACPI_DMAR_ATSR_HEADER *)DmarHeader); + break; + case EFI_ACPI_DMAR_TYPE_RHSA: + DumpDmarRhsa ((EFI_ACPI_DMAR_RHSA_HEADER *)DmarHeader); + break; + case EFI_ACPI_DMAR_TYPE_ANDD: + DumpDmarAndd ((EFI_ACPI_DMAR_ANDD_HEADER *)DmarHeader); + break; + default: + break; + } + DmarLen -=3D DmarHeader->Length; + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } + + DEBUG ((DEBUG_INFO, + "*********************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR ACPI table. +**/ +VOID +VtdDumpDmarTable ( + VOID + ) +{ + DumpAcpiDMAR ((EFI_ACPI_DMAR_HEADER *)(UINTN)mAcpiDmarTable); +} + +/** + Get PCI device information from DMAR DevScopeEntry. + + @param[in] Segment The segment number. + @param[in] DmarDevScopeEntry DMAR DevScopeEntry + @param[out] Bus The bus number. + @param[out] Device The device number. + @param[out] Function The function number. + + @retval EFI_SUCCESS The PCI device information is returned. +**/ +EFI_STATUS +GetPciBusDeviceFunction ( + IN UINT16 Segment, + IN EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDevScopeEntry, + OUT UINT8 *Bus, + OUT UINT8 *Device, + OUT UINT8 *Function + ) +{ + EFI_ACPI_DMAR_PCI_PATH *DmarPciPath; + UINT8 MyBus; + UINT8 MyDevice; + UINT8 MyFunction; + + DmarPciPath =3D (EFI_ACPI_DMAR_PCI_PATH *)((UINTN)(DmarDevScopeEntry + 1= )); + MyBus =3D DmarDevScopeEntry->StartBusNumber; + MyDevice =3D DmarPciPath->Device; + MyFunction =3D DmarPciPath->Function; + + switch (DmarDevScopeEntry->Type) { + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT: + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE: + while ((UINTN)DmarPciPath + sizeof(EFI_ACPI_DMAR_PCI_PATH) < (UINTN)Dm= arDevScopeEntry + DmarDevScopeEntry->Length) { + MyBus =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Segment, MyBus, M= yDevice, MyFunction, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); + DmarPciPath ++; + MyDevice =3D DmarPciPath->Device; + MyFunction =3D DmarPciPath->Function; + } + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC: + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET: + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE: + break; + } + + *Bus =3D MyBus; + *Device =3D MyDevice; + *Function =3D MyFunction; + + return EFI_SUCCESS; +} + +/** + Process DMAR DHRD table. + + @param[in] VtdIndex The index of VTd engine. + @param[in] DmarDrhd The DRHD table. + + @retval EFI_SUCCESS The DRHD table is processed. +**/ +EFI_STATUS +ProcessDhrd ( + IN UINTN VtdIndex, + IN EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd + ) +{ + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDevScopeEntry; + UINT8 Bus; + UINT8 Device; + UINT8 Function; + UINT8 SecondaryBusNumber; + EFI_STATUS Status; + VTD_SOURCE_ID SourceId; + + mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress =3D (UINTN)DmarDrhd->Re= gisterBaseAddress; + DEBUG ((DEBUG_INFO," VTD (%d) BaseAddress - 0x%016lx\n", VtdIndex, Dma= rDrhd->RegisterBaseAddress)); + + mVtdUnitInformation[VtdIndex].Segment =3D DmarDrhd->SegmentNumber; + + if ((DmarDrhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) !=3D 0)= { + mVtdUnitInformation[VtdIndex].PciDeviceInfo.IncludeAllFlag =3D TRUE; + DEBUG ((DEBUG_INFO," ProcessDhrd: with INCLUDE ALL\n")); + + Status =3D ScanPciBus((VOID *)VtdIndex, DmarDrhd->SegmentNumber, 0, Sc= anBusCallbackRegisterPciDevice); + if (EFI_ERROR (Status)) { + return Status; + } + } else { + mVtdUnitInformation[VtdIndex].PciDeviceInfo.IncludeAllFlag =3D FALSE; + DEBUG ((DEBUG_INFO," ProcessDhrd: without INCLUDE ALL\n")); + } + + DmarDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)((U= INTN)(DmarDrhd + 1)); + while ((UINTN)DmarDevScopeEntry < (UINTN)DmarDrhd + DmarDrhd->Header.Len= gth) { + + Status =3D GetPciBusDeviceFunction (DmarDrhd->SegmentNumber, DmarDevSc= opeEntry, &Bus, &Device, &Function); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO," ProcessDhrd: ")); + switch (DmarDevScopeEntry->Type) { + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT: + DEBUG ((DEBUG_INFO,"PCI Endpoint")); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE: + DEBUG ((DEBUG_INFO,"PCI-PCI bridge")); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_IOAPIC: + DEBUG ((DEBUG_INFO,"IOAPIC")); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_MSI_CAPABLE_HPET: + DEBUG ((DEBUG_INFO,"MSI Capable HPET")); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_ACPI_NAMESPACE_DEVICE: + DEBUG ((DEBUG_INFO,"ACPI Namespace Device")); + break; + } + DEBUG ((DEBUG_INFO," S%04x B%02x D%02x F%02x\n", DmarDrhd->SegmentNumb= er, Bus, Device, Function)); + + SourceId.Bits.Bus =3D Bus; + SourceId.Bits.Device =3D Device; + SourceId.Bits.Function =3D Function; + + Status =3D RegisterPciDevice (VtdIndex, DmarDrhd->SegmentNumber, Sourc= eId, DmarDevScopeEntry->Type, TRUE); + if (EFI_ERROR (Status)) { + // + // There might be duplication for special device other than standard= PCI device. + // + switch (DmarDevScopeEntry->Type) { + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT: + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE: + return Status; + } + } + + switch (DmarDevScopeEntry->Type) { + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE: + SecondaryBusNumber =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Dmar= Drhd->SegmentNumber, Bus, Device, Function, PCI_BRIDGE_SECONDARY_BUS_REGIST= ER_OFFSET)); + Status =3D ScanPciBus ((VOID *)VtdIndex, DmarDrhd->SegmentNumber, Se= condaryBusNumber, ScanBusCallbackRegisterPciDevice); + if (EFI_ERROR (Status)) { + return Status; + } + break; + default: + break; + } + + DmarDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)(= (UINTN)DmarDevScopeEntry + DmarDevScopeEntry->Length); + } + + return EFI_SUCCESS; +} + +/** + Process DMAR RMRR table. + + @param[in] DmarRmrr The RMRR table. + + @retval EFI_SUCCESS The RMRR table is processed. +**/ +EFI_STATUS +ProcessRmrr ( + IN EFI_ACPI_DMAR_RMRR_HEADER *DmarRmrr + ) +{ + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDevScopeEntry; + UINT8 Bus; + UINT8 Device; + UINT8 Function; + EFI_STATUS Status; + VTD_SOURCE_ID SourceId; + + DEBUG ((DEBUG_INFO," RMRR (Base 0x%016lx, Limit 0x%016lx)\n", DmarRmrr-= >ReservedMemoryRegionBaseAddress, DmarRmrr->ReservedMemoryRegionLimitAddres= s)); + + DmarDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)((U= INTN)(DmarRmrr + 1)); + while ((UINTN)DmarDevScopeEntry < (UINTN)DmarRmrr + DmarRmrr->Header.Len= gth) { + if (DmarDevScopeEntry->Type !=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_= ENDPOINT) { + DEBUG ((DEBUG_INFO,"RMRR DevScopeEntryType is not endpoint, type[0x%= x] \n", DmarDevScopeEntry->Type)); + return EFI_DEVICE_ERROR; + } + + Status =3D GetPciBusDeviceFunction (DmarRmrr->SegmentNumber, DmarDevSc= opeEntry, &Bus, &Device, &Function); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO,"RMRR S%04x B%02x D%02x F%02x\n", DmarRmrr->Segment= Number, Bus, Device, Function)); + + SourceId.Bits.Bus =3D Bus; + SourceId.Bits.Device =3D Device; + SourceId.Bits.Function =3D Function; + Status =3D SetAccessAttribute ( + DmarRmrr->SegmentNumber, + SourceId, + DmarRmrr->ReservedMemoryRegionBaseAddress, + DmarRmrr->ReservedMemoryRegionLimitAddress + 1 - DmarRmrr->= ReservedMemoryRegionBaseAddress, + EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE + ); + if (EFI_ERROR (Status)) { + return Status; + } + + DmarDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)(= (UINTN)DmarDevScopeEntry + DmarDevScopeEntry->Length); + } + + return EFI_SUCCESS; +} + +/** + Get VTd engine number. +**/ +UINTN +GetVtdEngineNumber ( + VOID + ) +{ + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + UINTN VtdIndex; + + VtdIndex =3D 0; + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(mAcpiDmarTable= + 1)); + while ((UINTN)DmarHeader < (UINTN)mAcpiDmarTable + mAcpiDmarTable->Heade= r.Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + VtdIndex++; + break; + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } + return VtdIndex ; +} + +/** + Parse DMAR DRHD table. + + @return EFI_SUCCESS The DMAR DRHD table is parsed. +**/ +EFI_STATUS +ParseDmarAcpiTableDrhd ( + VOID + ) +{ + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + EFI_STATUS Status; + UINTN VtdIndex; + + mVtdUnitNumber =3D GetVtdEngineNumber (); + DEBUG ((DEBUG_INFO," VtdUnitNumber - %d\n", mVtdUnitNumber)); + ASSERT (mVtdUnitNumber > 0); + if (mVtdUnitNumber =3D=3D 0) { + return EFI_DEVICE_ERROR; + } + + mVtdUnitInformation =3D AllocateZeroPool (sizeof(*mVtdUnitInformation) *= mVtdUnitNumber); + ASSERT (mVtdUnitInformation !=3D NULL); + if (mVtdUnitInformation =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + VtdIndex =3D 0; + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(mAcpiDmarTable= + 1)); + while ((UINTN)DmarHeader < (UINTN)mAcpiDmarTable + mAcpiDmarTable->Heade= r.Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + ASSERT (VtdIndex < mVtdUnitNumber); + Status =3D ProcessDhrd (VtdIndex, (EFI_ACPI_DMAR_DRHD_HEADER *)DmarH= eader); + if (EFI_ERROR (Status)) { + return Status; + } + VtdIndex++; + + break; + + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } + ASSERT (VtdIndex =3D=3D mVtdUnitNumber); + + for (VtdIndex =3D 0; VtdIndex < mVtdUnitNumber; VtdIndex++) { + DumpPciDeviceInfo (VtdIndex); + } + return EFI_SUCCESS ; +} + +/** + Parse DMAR DRHD table. + + @return EFI_SUCCESS The DMAR DRHD table is parsed. +**/ +EFI_STATUS +ParseDmarAcpiTableRmrr ( + VOID + ) +{ + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + EFI_STATUS Status; + + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(mAcpiDmarTable= + 1)); + while ((UINTN)DmarHeader < (UINTN)mAcpiDmarTable + mAcpiDmarTable->Heade= r.Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_RMRR: + Status =3D ProcessRmrr ((EFI_ACPI_DMAR_RMRR_HEADER *)DmarHeader); + if (EFI_ERROR (Status)) { + return Status; + } + break; + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } + return EFI_SUCCESS ; +} + +/** + Get the DMAR ACPI table. + + @retval EFI_SUCCESS The DMAR ACPI table is got. + @retval EFI_ALREADY_STARTED The DMAR ACPI table has been got previousl= y. + @retval EFI_NOT_FOUND The DMAR ACPI table is not found. +**/ +EFI_STATUS +GetDmarAcpiTable ( + VOID + ) +{ + if (mAcpiDmarTable !=3D NULL) { + return EFI_ALREADY_STARTED; + } + + mAcpiDmarTable =3D (EFI_ACPI_DMAR_HEADER *) EfiLocateFirstAcpiTable ( + EFI_ACPI_4_0_DMA_REMAPPING_T= ABLE_SIGNATURE + ); + if (mAcpiDmarTable =3D=3D NULL) { + return EFI_NOT_FOUND; + } + DEBUG ((DEBUG_INFO,"DMAR Table - 0x%08x\n", mAcpiDmarTable)); + VtdDumpDmarTable(); + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTd= Dxe.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c new file mode 100644 index 0000000000..a6287be2cf --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c @@ -0,0 +1,400 @@ +/** @file + Intel VTd driver. + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DmaProtection.h" + +/** + Provides the controller-specific addresses required to access system mem= ory from a + DMA bus master. + + @param This The protocol instance pointer. + @param Operation Indicates if the bus master is going to re= ad or write to system memory. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes On input the number of bytes to map. On ou= tput the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned Numb= erOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a comm= on buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requ= ested address. + +**/ +EFI_STATUS +EFIAPI +IoMmuMap ( + IN EDKII_IOMMU_PROTOCOL *This, + IN EDKII_IOMMU_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This The protocol instance pointer. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned b= y Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target s= ystem memory. +**/ +EFI_STATUS +EFIAPI +IoMmuUnmap ( + IN EDKII_IOMMU_PROTOCOL *This, + IN VOID *Mapping + ); + +/** + Allocates pages that are suitable for an OperationBusMasterCommonBuffer = or + OperationBusMasterCommonBuffer64 mapping. + + @param This The protocol instance pointer. + @param Type This parameter is not used and must be ign= ored. + @param MemoryType The type of memory to allocate, EfiBootSer= vicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory = address of the + allocated range. + @param Attributes The requested bit mask of attributes for t= he allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal = attribute bits are + MEMORY_WRITE_COMBINE, MEMORY_CACHED and DU= AL_ADDRESS_CYCLE. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + +**/ +EFI_STATUS +EFIAPI +IoMmuAllocateBuffer ( + IN EDKII_IOMMU_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param This The protocol instance pointer. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allo= cated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress = and Pages + was not allocated with AllocateBuffer(). + +**/ +EFI_STATUS +EFIAPI +IoMmuFreeBuffer ( + IN EDKII_IOMMU_PROTOCOL *This, + IN UINTN Pages, + IN VOID *HostAddress + ); + +/** + This function fills DeviceHandle/IoMmuAccess to the MAP_HANDLE_INFO, + based upon the DeviceAddress. + + @param[in] DeviceHandle The device who initiates the DMA access re= quest. + @param[in] DeviceAddress The base of device memory address to be us= ed as the DMA memory. + @param[in] Length The length of device memory address to be = used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + +**/ +VOID +SyncDeviceHandleToMapInfo ( + IN EFI_HANDLE DeviceHandle, + IN EFI_PHYSICAL_ADDRESS DeviceAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ); + +/** + Convert the DeviceHandle to SourceId and Segment. + + @param[in] DeviceHandle The device who initiates the DMA access re= quest. + @param[out] Segment The Segment used to identify a VTd engine. + @param[out] SourceId The SourceId used to identify a VTd engine= and table entry. + + @retval EFI_SUCCESS The Segment and SourceId are returned. + @retval EFI_INVALID_PARAMETER DeviceHandle is an invalid handle. + @retval EFI_UNSUPPORTED DeviceHandle is unknown by the IOMMU. +**/ +EFI_STATUS +DeviceHandleToSourceId ( + IN EFI_HANDLE DeviceHandle, + OUT UINT16 *Segment, + OUT VTD_SOURCE_ID *SourceId + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN Seg; + UINTN Bus; + UINTN Dev; + UINTN Func; + EFI_STATUS Status; + EDKII_PLATFORM_VTD_DEVICE_INFO DeviceInfo; + + Status =3D EFI_NOT_FOUND; + if (mPlatformVTdPolicy !=3D NULL) { + Status =3D mPlatformVTdPolicy->GetDeviceId (mPlatformVTdPolicy, Device= Handle, &DeviceInfo); + if (!EFI_ERROR(Status)) { + *Segment =3D DeviceInfo.Segment; + *SourceId =3D DeviceInfo.SourceId; + return EFI_SUCCESS; + } + } + + Status =3D gBS->HandleProtocol (DeviceHandle, &gEfiPciIoProtocolGuid, (V= OID **)&PciIo); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + Status =3D PciIo->GetLocation (PciIo, &Seg, &Bus, &Dev, &Func); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + *Segment =3D (UINT16)Seg; + SourceId->Bits.Bus =3D (UINT8)Bus; + SourceId->Bits.Device =3D (UINT8)Dev; + SourceId->Bits.Function =3D (UINT8)Func; + + return EFI_SUCCESS; +} + +/** + Set IOMMU attribute for a system memory. + + If the IOMMU protocol exists, the system memory cannot be used + for DMA by default. + + When a device requests a DMA access for a system memory, + the device driver need use SetAttribute() to update the IOMMU + attribute to request DMA access (read and/or write). + + The DeviceHandle is used to identify which device submits the request. + The IOMMU implementation need translate the device path to an IOMMU devi= ce ID, + and set IOMMU hardware register accordingly. + 1) DeviceHandle can be a standard PCI device. + The memory for BusMasterRead need set EDKII_IOMMU_ACCESS_READ. + The memory for BusMasterWrite need set EDKII_IOMMU_ACCESS_WRITE. + The memory for BusMasterCommonBuffer need set EDKII_IOMMU_ACCESS_READ= |EDKII_IOMMU_ACCESS_WRITE. + After the memory is used, the memory need set 0 to keep it being prot= ected. + 2) DeviceHandle can be an ACPI device (ISA, I2C, SPI, etc). + The memory for DMA access need set EDKII_IOMMU_ACCESS_READ and/or EDK= II_IOMMU_ACCESS_WRITE. + + @param[in] This The protocol instance pointer. + @param[in] DeviceHandle The device who initiates the DMA access re= quest. + @param[in] DeviceAddress The base of device memory address to be us= ed as the DMA memory. + @param[in] Length The length of device memory address to be = used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by DeviceAddress and Length. + @retval EFI_INVALID_PARAMETER DeviceHandle is an invalid handle. + @retval EFI_INVALID_PARAMETER DeviceAddress is not IoMmu Page size alig= ned. + @retval EFI_INVALID_PARAMETER Length is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is 0. + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED DeviceHandle is unknown by the IOMMU. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by DeviceAddress and Length. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. + +**/ +EFI_STATUS +VTdSetAttribute ( + IN EDKII_IOMMU_PROTOCOL *This, + IN EFI_HANDLE DeviceHandle, + IN EFI_PHYSICAL_ADDRESS DeviceAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ) +{ + EFI_STATUS Status; + UINT16 Segment; + VTD_SOURCE_ID SourceId; + CHAR8 PerfToken[sizeof("VTD(S0000.B00.D00.F00)")]; + UINT32 Identifier; + + DumpVtdIfError (); + + Status =3D DeviceHandleToSourceId (DeviceHandle, &Segment, &SourceId); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((DEBUG_VERBOSE, "IoMmuSetAttribute: ")); + DEBUG ((DEBUG_VERBOSE, "PCI(S%x.B%x.D%x.F%x) ", Segment, SourceId.Bits.B= us, SourceId.Bits.Device, SourceId.Bits.Function)); + DEBUG ((DEBUG_VERBOSE, "(0x%lx~0x%lx) - %lx\n", DeviceAddress, Length, I= oMmuAccess)); + + if (mAcpiDmarTable =3D=3D NULL) { + // + // Record the entry to driver global variable. + // As such once VTd is activated, the setting can be adopted. + // + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) !=3D 0) { + // + // Force no IOMMU access attribute request recording before DMAR tab= le is installed. + // + ASSERT_EFI_ERROR (EFI_NOT_READY); + return EFI_NOT_READY; + } + Status =3D RequestAccessAttribute (Segment, SourceId, DeviceAddress, L= ength, IoMmuAccess); + } else { + PERF_CODE ( + AsciiSPrint (PerfToken, sizeof(PerfToken), "S%04xB%02xD%02xF%01x", S= egment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function); + Identifier =3D (Segment << 16) | SourceId.Uint16; + PERF_START_EX (gImageHandle, PerfToken, "IntelVTD", 0, Identifier); + ); + + Status =3D SetAccessAttribute (Segment, SourceId, DeviceAddress, Lengt= h, IoMmuAccess); + + PERF_CODE ( + Identifier =3D (Segment << 16) | SourceId.Uint16; + PERF_END_EX (gImageHandle, PerfToken, "IntelVTD", 0, Identifier); + ); + } + + if (!EFI_ERROR(Status)) { + SyncDeviceHandleToMapInfo ( + DeviceHandle, + DeviceAddress, + Length, + IoMmuAccess + ); + } + + return Status; +} + +/** + Set IOMMU attribute for a system memory. + + If the IOMMU protocol exists, the system memory cannot be used + for DMA by default. + + When a device requests a DMA access for a system memory, + the device driver need use SetAttribute() to update the IOMMU + attribute to request DMA access (read and/or write). + + The DeviceHandle is used to identify which device submits the request. + The IOMMU implementation need translate the device path to an IOMMU devi= ce ID, + and set IOMMU hardware register accordingly. + 1) DeviceHandle can be a standard PCI device. + The memory for BusMasterRead need set EDKII_IOMMU_ACCESS_READ. + The memory for BusMasterWrite need set EDKII_IOMMU_ACCESS_WRITE. + The memory for BusMasterCommonBuffer need set EDKII_IOMMU_ACCESS_READ= |EDKII_IOMMU_ACCESS_WRITE. + After the memory is used, the memory need set 0 to keep it being prot= ected. + 2) DeviceHandle can be an ACPI device (ISA, I2C, SPI, etc). + The memory for DMA access need set EDKII_IOMMU_ACCESS_READ and/or EDK= II_IOMMU_ACCESS_WRITE. + + @param[in] This The protocol instance pointer. + @param[in] DeviceHandle The device who initiates the DMA access re= quest. + @param[in] Mapping The mapping value returned from Map(). + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by DeviceAddress and Length. + @retval EFI_INVALID_PARAMETER DeviceHandle is an invalid handle. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by Map(). + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED DeviceHandle is unknown by the IOMMU. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by Mapping. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. + +**/ +EFI_STATUS +EFIAPI +IoMmuSetAttribute ( + IN EDKII_IOMMU_PROTOCOL *This, + IN EFI_HANDLE DeviceHandle, + IN VOID *Mapping, + IN UINT64 IoMmuAccess + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS DeviceAddress; + UINTN NumberOfPages; + EFI_TPL OriginalTpl; + + OriginalTpl =3D gBS->RaiseTPL (VTD_TPL_LEVEL); + + Status =3D GetDeviceInfoFromMapping (Mapping, &DeviceAddress, &NumberOfP= ages); + if (!EFI_ERROR(Status)) { + Status =3D VTdSetAttribute ( + This, + DeviceHandle, + DeviceAddress, + EFI_PAGES_TO_SIZE(NumberOfPages), + IoMmuAccess + ); + } + + gBS->RestoreTPL (OriginalTpl); + + return Status; +} + +EDKII_IOMMU_PROTOCOL mIntelVTd =3D { + EDKII_IOMMU_PROTOCOL_REVISION, + IoMmuSetAttribute, + IoMmuMap, + IoMmuUnmap, + IoMmuAllocateBuffer, + IoMmuFreeBuffer, +}; + +/** + Initialize the VTd driver. + + @param[in] ImageHandle ImageHandle of the loaded driver + @param[in] SystemTable Pointer to the System Table + + @retval EFI_SUCCESS The Protocol is installed. + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occurred attempting to ini= tialize the driver. + +**/ +EFI_STATUS +EFIAPI +IntelVTdInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT0) =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + InitializeDmaProtection (); + + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEdkiiIoMmuProtocolGuid, &mIntelVTd, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.= c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c new file mode 100644 index 0000000000..4af376b350 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/PciInfo.c @@ -0,0 +1,373 @@ +/** @file + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DmaProtection.h" + +/** + Return the index of PCI data. + + @param[in] VtdIndex The index used to identify a VTd engine. + @param[in] Segment The Segment used to identify a VTd engine. + @param[in] SourceId The SourceId used to identify a VTd engine= and table entry. + + @return The index of the PCI data. + @retval (UINTN)-1 The PCI data is not found. +**/ +UINTN +GetPciDataIndex ( + IN UINTN VtdIndex, + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId + ) +{ + UINTN Index; + VTD_SOURCE_ID *PciSourceId; + + if (Segment !=3D mVtdUnitInformation[VtdIndex].Segment) { + return (UINTN)-1; + } + + for (Index =3D 0; Index < mVtdUnitInformation[VtdIndex].PciDeviceInfo.Pc= iDeviceDataNumber; Index++) { + PciSourceId =3D &mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDevice= Data[Index].PciSourceId; + if ((PciSourceId->Bits.Bus =3D=3D SourceId.Bits.Bus) && + (PciSourceId->Bits.Device =3D=3D SourceId.Bits.Device) && + (PciSourceId->Bits.Function =3D=3D SourceId.Bits.Function) ) { + return Index; + } + } + + return (UINTN)-1; +} + +/** + Register PCI device to VTd engine. + + @param[in] VtdIndex The index of VTd engine. + @param[in] Segment The segment of the source. + @param[in] SourceId The SourceId of the source. + @param[in] DeviceType The DMAR device scope type. + @param[in] CheckExist TRUE: ERROR will be returned if the PC= I device is already registered. + FALSE: SUCCESS will be returned if the= PCI device is registered. + + @retval EFI_SUCCESS The PCI device is registered. + @retval EFI_OUT_OF_RESOURCES No enough resource to register a new PCI d= evice. + @retval EFI_ALREADY_STARTED The device is already registered. +**/ +EFI_STATUS +RegisterPciDevice ( + IN UINTN VtdIndex, + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId, + IN UINT8 DeviceType, + IN BOOLEAN CheckExist + ) +{ + PCI_DEVICE_INFORMATION *PciDeviceInfo; + VTD_SOURCE_ID *PciSourceId; + UINTN PciDataIndex; + UINTN Index; + PCI_DEVICE_DATA *NewPciDeviceData; + EDKII_PLATFORM_VTD_PCI_DEVICE_ID *PciDeviceId; + + PciDeviceInfo =3D &mVtdUnitInformation[VtdIndex].PciDeviceInfo; + + if (PciDeviceInfo->IncludeAllFlag) { + // + // Do not register device in other VTD Unit + // + for (Index =3D 0; Index < VtdIndex; Index++) { + PciDataIndex =3D GetPciDataIndex (Index, Segment, SourceId); + if (PciDataIndex !=3D (UINTN)-1) { + DEBUG ((DEBUG_INFO, " RegisterPciDevice: PCI S%04x B%02x D%02x F%= 02x already registered by Other Vtd(%d)\n", Segment, SourceId.Bits.Bus, Sou= rceId.Bits.Device, SourceId.Bits.Function, Index)); + return EFI_SUCCESS; + } + } + } + + PciDataIndex =3D GetPciDataIndex (VtdIndex, Segment, SourceId); + if (PciDataIndex =3D=3D (UINTN)-1) { + // + // Register new + // + + if (PciDeviceInfo->PciDeviceDataNumber >=3D PciDeviceInfo->PciDeviceDa= taMaxNumber) { + // + // Reallocate + // + NewPciDeviceData =3D AllocateZeroPool (sizeof(*NewPciDeviceData) * (= PciDeviceInfo->PciDeviceDataMaxNumber + MAX_VTD_PCI_DATA_NUMBER)); + if (NewPciDeviceData =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + PciDeviceInfo->PciDeviceDataMaxNumber +=3D MAX_VTD_PCI_DATA_NUMBER; + if (PciDeviceInfo->PciDeviceData !=3D NULL) { + CopyMem (NewPciDeviceData, PciDeviceInfo->PciDeviceData, sizeof(*N= ewPciDeviceData) * PciDeviceInfo->PciDeviceDataNumber); + FreePool (PciDeviceInfo->PciDeviceData); + } + PciDeviceInfo->PciDeviceData =3D NewPciDeviceData; + } + + ASSERT (PciDeviceInfo->PciDeviceDataNumber < PciDeviceInfo->PciDeviceD= ataMaxNumber); + + PciSourceId =3D &PciDeviceInfo->PciDeviceData[PciDeviceInfo->PciDevice= DataNumber].PciSourceId; + PciSourceId->Bits.Bus =3D SourceId.Bits.Bus; + PciSourceId->Bits.Device =3D SourceId.Bits.Device; + PciSourceId->Bits.Function =3D SourceId.Bits.Function; + + DEBUG ((DEBUG_INFO, " RegisterPciDevice: PCI S%04x B%02x D%02x F%02x"= , Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function)= ); + + PciDeviceId =3D &PciDeviceInfo->PciDeviceData[PciDeviceInfo->PciDevice= DataNumber].PciDeviceId; + if ((DeviceType =3D=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT) = || + (DeviceType =3D=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE)) { + PciDeviceId->VendorId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRES= S(Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function,= PCI_VENDOR_ID_OFFSET)); + PciDeviceId->DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRES= S(Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function,= PCI_DEVICE_ID_OFFSET)); + PciDeviceId->RevisionId =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS= (Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function, = PCI_REVISION_ID_OFFSET)); + + DEBUG ((DEBUG_INFO, " (%04x:%04x:%02x", PciDeviceId->VendorId, PciDe= viceId->DeviceId, PciDeviceId->RevisionId)); + + if (DeviceType =3D=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT)= { + PciDeviceId->SubsystemVendorId =3D PciSegmentRead16 (PCI_SEGMENT_L= IB_ADDRESS(Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.= Function, PCI_SUBSYSTEM_VENDOR_ID_OFFSET)); + PciDeviceId->SubsystemDeviceId =3D PciSegmentRead16 (PCI_SEGMENT_L= IB_ADDRESS(Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.= Function, PCI_SUBSYSTEM_ID_OFFSET)); + DEBUG ((DEBUG_INFO, ":%04x:%04x", PciDeviceId->SubsystemVendorId, = PciDeviceId->SubsystemDeviceId)); + } + DEBUG ((DEBUG_INFO, ")")); + } + + PciDeviceInfo->PciDeviceData[PciDeviceInfo->PciDeviceDataNumber].Devic= eType =3D DeviceType; + + if ((DeviceType !=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT) && + (DeviceType !=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE)) { + DEBUG ((DEBUG_INFO, " (*)")); + } + DEBUG ((DEBUG_INFO, "\n")); + + PciDeviceInfo->PciDeviceDataNumber++; + } else { + if (CheckExist) { + DEBUG ((DEBUG_INFO, " RegisterPciDevice: PCI S%04x B%02x D%02x F%02= x already registered\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, = SourceId.Bits.Function)); + return EFI_ALREADY_STARTED; + } + } + + return EFI_SUCCESS; +} + +/** + The scan bus callback function to register PCI device. + + @param[in] Context The context of the callback. + @param[in] Segment The segment of the source. + @param[in] Bus The bus of the source. + @param[in] Device The device of the source. + @param[in] Function The function of the source. + + @retval EFI_SUCCESS The PCI device is registered. +**/ +EFI_STATUS +EFIAPI +ScanBusCallbackRegisterPciDevice ( + IN VOID *Context, + IN UINT16 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function + ) +{ + VTD_SOURCE_ID SourceId; + UINTN VtdIndex; + UINT8 BaseClass; + UINT8 SubClass; + UINT8 DeviceType; + EFI_STATUS Status; + + VtdIndex =3D (UINTN)Context; + SourceId.Bits.Bus =3D Bus; + SourceId.Bits.Device =3D Device; + SourceId.Bits.Function =3D Function; + + DeviceType =3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT; + BaseClass =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, Dev= ice, Function, PCI_CLASSCODE_OFFSET + 2)); + if (BaseClass =3D=3D PCI_CLASS_BRIDGE) { + SubClass =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus, De= vice, Function, PCI_CLASSCODE_OFFSET + 1)); + if (SubClass =3D=3D PCI_CLASS_BRIDGE_P2P) { + DeviceType =3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE; + } + } + + Status =3D RegisterPciDevice (VtdIndex, Segment, SourceId, DeviceType, F= ALSE); + return Status; +} + +/** + Scan PCI bus and invoke callback function for each PCI devices under the= bus. + + @param[in] Context The context of the callback function. + @param[in] Segment The segment of the source. + @param[in] Bus The bus of the source. + @param[in] Callback The callback function in PCI scan. + + @retval EFI_SUCCESS The PCI devices under the bus are scaned. +**/ +EFI_STATUS +ScanPciBus ( + IN VOID *Context, + IN UINT16 Segment, + IN UINT8 Bus, + IN SCAN_BUS_FUNC_CALLBACK_FUNC Callback + ) +{ + UINT8 Device; + UINT8 Function; + UINT8 SecondaryBusNumber; + UINT8 HeaderType; + UINT8 BaseClass; + UINT8 SubClass; + UINT16 VendorID; + UINT16 DeviceID; + EFI_STATUS Status; + + // Scan the PCI bus for devices + for (Device =3D 0; Device <=3D PCI_MAX_DEVICE; Device++) { + for (Function =3D 0; Function <=3D PCI_MAX_FUNC; Function++) { + VendorID =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus= , Device, Function, PCI_VENDOR_ID_OFFSET)); + DeviceID =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus= , Device, Function, PCI_DEVICE_ID_OFFSET)); + if (VendorID =3D=3D 0xFFFF && DeviceID =3D=3D 0xFFFF) { + if (Function =3D=3D 0) { + // + // If function 0 is not implemented, do not scan other functions. + // + break; + } + continue; + } + + Status =3D Callback (Context, Segment, Bus, Device, Function); + if (EFI_ERROR (Status)) { + return Status; + } + + BaseClass =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus,= Device, Function, PCI_CLASSCODE_OFFSET + 2)); + if (BaseClass =3D=3D PCI_CLASS_BRIDGE) { + SubClass =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Segment, Bus= , Device, Function, PCI_CLASSCODE_OFFSET + 1)); + if (SubClass =3D=3D PCI_CLASS_BRIDGE_P2P) { + SecondaryBusNumber =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(= Segment, Bus, Device, Function, PCI_BRIDGE_SECONDARY_BUS_REGISTER_OFFSET)); + DEBUG ((DEBUG_INFO," ScanPciBus: PCI bridge S%04x B%02x D%02x F= %02x (SecondBus:%02x)\n", Segment, Bus, Device, Function, SecondaryBusNumbe= r)); + if (SecondaryBusNumber !=3D 0) { + Status =3D ScanPciBus (Context, Segment, SecondaryBusNumber, C= allback); + if (EFI_ERROR (Status)) { + return Status; + } + } + } + } + + if (Function =3D=3D 0) { + HeaderType =3D PciSegmentRead8 (PCI_SEGMENT_LIB_ADDRESS(Segment, B= us, Device, 0, PCI_HEADER_TYPE_OFFSET)); + if ((HeaderType & HEADER_TYPE_MULTI_FUNCTION) =3D=3D 0x00) { + // + // It is not a multi-function device, do not scan other function= s. + // + break; + } + } + } + } + + return EFI_SUCCESS; +} + +/** + Dump the PCI device information managed by this VTd engine. + + @param[in] VtdIndex The index of VTd engine. +**/ +VOID +DumpPciDeviceInfo ( + IN UINTN VtdIndex + ) +{ + UINTN Index; + + DEBUG ((DEBUG_INFO,"PCI Device Information (Number 0x%x, IncludeAll - %d= ):\n", + mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceDataNumber, + mVtdUnitInformation[VtdIndex].PciDeviceInfo.IncludeAllFlag + )); + for (Index =3D 0; Index < mVtdUnitInformation[VtdIndex].PciDeviceInfo.Pc= iDeviceDataNumber; Index++) { + DEBUG ((DEBUG_INFO," S%04x B%02x D%02x F%02x\n", + mVtdUnitInformation[VtdIndex].Segment, + mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceData[Index].Pci= SourceId.Bits.Bus, + mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceData[Index].Pci= SourceId.Bits.Device, + mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceData[Index].Pci= SourceId.Bits.Function + )); + } +} + +/** + Find the VTd index by the Segment and SourceId. + + @param[in] Segment The segment of the source. + @param[in] SourceId The SourceId of the source. + @param[out] ExtContextEntry The ExtContextEntry of the source. + @param[out] ContextEntry The ContextEntry of the source. + + @return The index of the VTd engine. + @retval (UINTN)-1 The VTd engine is not found. +**/ +UINTN +FindVtdIndexByPciDevice ( + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId, + OUT VTD_EXT_CONTEXT_ENTRY **ExtContextEntry, + OUT VTD_CONTEXT_ENTRY **ContextEntry + ) +{ + UINTN VtdIndex; + VTD_ROOT_ENTRY *RootEntry; + VTD_CONTEXT_ENTRY *ContextEntryTable; + VTD_CONTEXT_ENTRY *ThisContextEntry; + VTD_EXT_ROOT_ENTRY *ExtRootEntry; + VTD_EXT_CONTEXT_ENTRY *ExtContextEntryTable; + VTD_EXT_CONTEXT_ENTRY *ThisExtContextEntry; + UINTN PciDataIndex; + + for (VtdIndex =3D 0; VtdIndex < mVtdUnitNumber; VtdIndex++) { + if (Segment !=3D mVtdUnitInformation[VtdIndex].Segment) { + continue; + } + + PciDataIndex =3D GetPciDataIndex (VtdIndex, Segment, SourceId); + if (PciDataIndex =3D=3D (UINTN)-1) { + continue; + } + +// DEBUG ((DEBUG_INFO,"FindVtdIndex(0x%x) for S%04x B%02x D%02x F%02x\n= ", VtdIndex, Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bit= s.Function)); + + if (mVtdUnitInformation[VtdIndex].ExtRootEntryTable !=3D 0) { + ExtRootEntry =3D &mVtdUnitInformation[VtdIndex].ExtRootEntryTable[So= urceId.Index.RootIndex]; + ExtContextEntryTable =3D (VTD_EXT_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_= ADDRESS(ExtRootEntry->Bits.LowerContextTablePointerLo, ExtRootEntry->Bits.L= owerContextTablePointerHi) ; + ThisExtContextEntry =3D &ExtContextEntryTable[SourceId.Index.Contex= tIndex]; + if (ThisExtContextEntry->Bits.AddressWidth =3D=3D 0) { + continue; + } + *ExtContextEntry =3D ThisExtContextEntry; + *ContextEntry =3D NULL; + } else { + RootEntry =3D &mVtdUnitInformation[VtdIndex].RootEntryTable[SourceId= .Index.RootIndex]; + ContextEntryTable =3D (VTD_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS= (RootEntry->Bits.ContextTablePointerLo, RootEntry->Bits.ContextTablePointer= Hi) ; + ThisContextEntry =3D &ContextEntryTable[SourceId.Index.ContextIndex= ]; + if (ThisContextEntry->Bits.AddressWidth =3D=3D 0) { + continue; + } + *ExtContextEntry =3D NULL; + *ContextEntry =3D ThisContextEntry; + } + + return VtdIndex; + } + + return (UINTN)-1; +} + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c new file mode 100644 index 0000000000..fcff0925b8 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c @@ -0,0 +1,1026 @@ +/** @file + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DmaProtection.h" + +/** + Create extended context entry. + + @param[in] VtdIndex The index of the VTd engine. + + @retval EFI_SUCCESS The extended context entry is created. + @retval EFI_OUT_OF_RESOURCE No enough resource to create extended conte= xt entry. +**/ +EFI_STATUS +CreateExtContextEntry ( + IN UINTN VtdIndex + ); + +/** + Allocate zero pages. + + @param[in] Pages the number of pages. + + @return the page address. + @retval NULL No resource to allocate pages. +**/ +VOID * +EFIAPI +AllocateZeroPages ( + IN UINTN Pages + ) +{ + VOID *Addr; + + Addr =3D AllocatePages (Pages); + if (Addr =3D=3D NULL) { + return NULL; + } + ZeroMem (Addr, EFI_PAGES_TO_SIZE(Pages)); + return Addr; +} + +/** + Set second level paging entry attribute based upon IoMmuAccess. + + @param[in] PtEntry The paging entry. + @param[in] IoMmuAccess The IOMMU access. +**/ +VOID +SetSecondLevelPagingEntryAttribute ( + IN VTD_SECOND_LEVEL_PAGING_ENTRY *PtEntry, + IN UINT64 IoMmuAccess + ) +{ + PtEntry->Bits.Read =3D ((IoMmuAccess & EDKII_IOMMU_ACCESS_READ) !=3D 0); + PtEntry->Bits.Write =3D ((IoMmuAccess & EDKII_IOMMU_ACCESS_WRITE) !=3D 0= ); +} + +/** + Create context entry. + + @param[in] VtdIndex The index of the VTd engine. + + @retval EFI_SUCCESS The context entry is created. + @retval EFI_OUT_OF_RESOURCE No enough resource to create context entry. +**/ +EFI_STATUS +CreateContextEntry ( + IN UINTN VtdIndex + ) +{ + UINTN Index; + VOID *Buffer; + UINTN RootPages; + UINTN ContextPages; + VTD_ROOT_ENTRY *RootEntry; + VTD_CONTEXT_ENTRY *ContextEntryTable; + VTD_CONTEXT_ENTRY *ContextEntry; + VTD_SOURCE_ID *PciSourceId; + VTD_SOURCE_ID SourceId; + UINTN MaxBusNumber; + UINTN EntryTablePages; + + MaxBusNumber =3D 0; + for (Index =3D 0; Index < mVtdUnitInformation[VtdIndex].PciDeviceInfo.Pc= iDeviceDataNumber; Index++) { + PciSourceId =3D &mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDevice= Data[Index].PciSourceId; + if (PciSourceId->Bits.Bus > MaxBusNumber) { + MaxBusNumber =3D PciSourceId->Bits.Bus; + } + } + DEBUG ((DEBUG_INFO," MaxBusNumber - 0x%x\n", MaxBusNumber)); + + RootPages =3D EFI_SIZE_TO_PAGES (sizeof (VTD_ROOT_ENTRY) * VTD_ROOT_ENTR= Y_NUMBER); + ContextPages =3D EFI_SIZE_TO_PAGES (sizeof (VTD_CONTEXT_ENTRY) * VTD_CON= TEXT_ENTRY_NUMBER); + EntryTablePages =3D RootPages + ContextPages * (MaxBusNumber + 1); + Buffer =3D AllocateZeroPages (EntryTablePages); + if (Buffer =3D=3D NULL) { + DEBUG ((DEBUG_INFO,"Could not Alloc Root Entry Table.. \n")); + return EFI_OUT_OF_RESOURCES; + } + mVtdUnitInformation[VtdIndex].RootEntryTable =3D (VTD_ROOT_ENTRY *)Buffe= r; + Buffer =3D (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (RootPages); + + for (Index =3D 0; Index < mVtdUnitInformation[VtdIndex].PciDeviceInfo.Pc= iDeviceDataNumber; Index++) { + PciSourceId =3D &mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDevice= Data[Index].PciSourceId; + + SourceId.Bits.Bus =3D PciSourceId->Bits.Bus; + SourceId.Bits.Device =3D PciSourceId->Bits.Device; + SourceId.Bits.Function =3D PciSourceId->Bits.Function; + + RootEntry =3D &mVtdUnitInformation[VtdIndex].RootEntryTable[SourceId.I= ndex.RootIndex]; + if (RootEntry->Bits.Present =3D=3D 0) { + RootEntry->Bits.ContextTablePointerLo =3D (UINT32) RShiftU64 ((UINT= 64)(UINTN)Buffer, 12); + RootEntry->Bits.ContextTablePointerHi =3D (UINT32) RShiftU64 ((UINT= 64)(UINTN)Buffer, 32); + RootEntry->Bits.Present =3D 1; + Buffer =3D (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages); + } + + ContextEntryTable =3D (VTD_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(R= ootEntry->Bits.ContextTablePointerLo, RootEntry->Bits.ContextTablePointerHi= ) ; + ContextEntry =3D &ContextEntryTable[SourceId.Index.ContextIndex]; + ContextEntry->Bits.TranslationType =3D 0; + ContextEntry->Bits.FaultProcessingDisable =3D 0; + ContextEntry->Bits.Present =3D 0; + + DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInform= ation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.= Bits.Function)); + + switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { + case BIT1: + ContextEntry->Bits.AddressWidth =3D 0x1; + break; + case BIT2: + ContextEntry->Bits.AddressWidth =3D 0x2; + break; + } + } + + FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Roo= tEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); + + return EFI_SUCCESS; +} + +/** + Create second level paging entry table. + + @param[in] VtdIndex The index of the VTd engine. + @param[in] SecondLevelPagingEntry The second level paging entry. + @param[in] MemoryBase The base of the memory. + @param[in] MemoryLimit The limit of the memory. + @param[in] IoMmuAccess The IOMMU access. + + @return The second level paging entry. +**/ +VTD_SECOND_LEVEL_PAGING_ENTRY * +CreateSecondLevelPagingEntryTable ( + IN UINTN VtdIndex, + IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry, + IN UINT64 MemoryBase, + IN UINT64 MemoryLimit, + IN UINT64 IoMmuAccess + ) +{ + UINTN Index4; + UINTN Index3; + UINTN Index2; + UINTN Lvl4Start; + UINTN Lvl4End; + UINTN Lvl3Start; + UINTN Lvl3End; + VTD_SECOND_LEVEL_PAGING_ENTRY *Lvl4PtEntry; + VTD_SECOND_LEVEL_PAGING_ENTRY *Lvl3PtEntry; + VTD_SECOND_LEVEL_PAGING_ENTRY *Lvl2PtEntry; + UINT64 BaseAddress; + UINT64 EndAddress; + + if (MemoryLimit =3D=3D 0) { + return EFI_SUCCESS; + } + + BaseAddress =3D ALIGN_VALUE_LOW(MemoryBase, SIZE_2MB); + EndAddress =3D ALIGN_VALUE_UP(MemoryLimit, SIZE_2MB); + DEBUG ((DEBUG_INFO,"CreateSecondLevelPagingEntryTable: BaseAddress - 0x%= 016lx, EndAddress - 0x%016lx\n", BaseAddress, EndAddress)); + + if (SecondLevelPagingEntry =3D=3D NULL) { + SecondLevelPagingEntry =3D AllocateZeroPages (1); + if (SecondLevelPagingEntry =3D=3D NULL) { + DEBUG ((DEBUG_ERROR,"Could not Alloc LVL4 PT. \n")); + return NULL; + } + FlushPageTableMemory (VtdIndex, (UINTN)SecondLevelPagingEntry, EFI_PAG= ES_TO_SIZE(1)); + } + + // + // If no access is needed, just create not present entry. + // + if (IoMmuAccess =3D=3D 0) { + return SecondLevelPagingEntry; + } + + Lvl4Start =3D RShiftU64 (BaseAddress, 39) & 0x1FF; + Lvl4End =3D RShiftU64 (EndAddress - 1, 39) & 0x1FF; + + DEBUG ((DEBUG_INFO," Lvl4Start - 0x%x, Lvl4End - 0x%x\n", Lvl4Start, Lv= l4End)); + + Lvl4PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)SecondLevelPagingEntry; + for (Index4 =3D Lvl4Start; Index4 <=3D Lvl4End; Index4++) { + if (Lvl4PtEntry[Index4].Uint64 =3D=3D 0) { + Lvl4PtEntry[Index4].Uint64 =3D (UINT64)(UINTN)AllocateZeroPages (1); + if (Lvl4PtEntry[Index4].Uint64 =3D=3D 0) { + DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL4 PAGE FAIL (0x%x)!!!!!!\n= ", Index4)); + ASSERT(FALSE); + return NULL; + } + FlushPageTableMemory (VtdIndex, (UINTN)Lvl4PtEntry[Index4].Uint64, S= IZE_4KB); + SetSecondLevelPagingEntryAttribute (&Lvl4PtEntry[Index4], EDKII_IOMM= U_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); + } + + Lvl3Start =3D RShiftU64 (BaseAddress, 30) & 0x1FF; + if (ALIGN_VALUE_LOW(BaseAddress + SIZE_1GB, SIZE_1GB) <=3D EndAddress)= { + Lvl3End =3D SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTRY) - 1; + } else { + Lvl3End =3D RShiftU64 (EndAddress - 1, 30) & 0x1FF; + } + DEBUG ((DEBUG_INFO," Lvl4(0x%x): Lvl3Start - 0x%x, Lvl3End - 0x%x\n",= Index4, Lvl3Start, Lvl3End)); + + Lvl3PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_ADD= RESS(Lvl4PtEntry[Index4].Bits.AddressLo, Lvl4PtEntry[Index4].Bits.AddressHi= ); + for (Index3 =3D Lvl3Start; Index3 <=3D Lvl3End; Index3++) { + if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) { + Lvl3PtEntry[Index3].Uint64 =3D (UINT64)(UINTN)AllocateZeroPages (1= ); + if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) { + DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL3 PAGE FAIL (0x%x, 0x%x)= !!!!!!\n", Index4, Index3)); + ASSERT(FALSE); + return NULL; + } + FlushPageTableMemory (VtdIndex, (UINTN)Lvl3PtEntry[Index3].Uint64,= SIZE_4KB); + SetSecondLevelPagingEntryAttribute (&Lvl3PtEntry[Index3], EDKII_IO= MMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); + } + + Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_A= DDRESS(Lvl3PtEntry[Index3].Bits.AddressLo, Lvl3PtEntry[Index3].Bits.Address= Hi); + for (Index2 =3D 0; Index2 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_= ENTRY); Index2++) { + Lvl2PtEntry[Index2].Uint64 =3D BaseAddress; + SetSecondLevelPagingEntryAttribute (&Lvl2PtEntry[Index2], IoMmuAcc= ess); + Lvl2PtEntry[Index2].Bits.PageSize =3D 1; + BaseAddress +=3D SIZE_2MB; + if (BaseAddress >=3D MemoryLimit) { + break; + } + } + FlushPageTableMemory (VtdIndex, (UINTN)Lvl2PtEntry, SIZE_4KB); + if (BaseAddress >=3D MemoryLimit) { + break; + } + } + FlushPageTableMemory (VtdIndex, (UINTN)&Lvl3PtEntry[Lvl3Start], (UINTN= )&Lvl3PtEntry[Lvl3End + 1] - (UINTN)&Lvl3PtEntry[Lvl3Start]); + if (BaseAddress >=3D MemoryLimit) { + break; + } + } + FlushPageTableMemory (VtdIndex, (UINTN)&Lvl4PtEntry[Lvl4Start], (UINTN)&= Lvl4PtEntry[Lvl4End + 1] - (UINTN)&Lvl4PtEntry[Lvl4Start]); + + return SecondLevelPagingEntry; +} + +/** + Create second level paging entry. + + @param[in] VtdIndex The index of the VTd engine. + @param[in] IoMmuAccess The IOMMU access. + + @return The second level paging entry. +**/ +VTD_SECOND_LEVEL_PAGING_ENTRY * +CreateSecondLevelPagingEntry ( + IN UINTN VtdIndex, + IN UINT64 IoMmuAccess + ) +{ + VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry; + + SecondLevelPagingEntry =3D NULL; + SecondLevelPagingEntry =3D CreateSecondLevelPagingEntryTable (VtdIndex, = SecondLevelPagingEntry, 0, mBelow4GMemoryLimit, IoMmuAccess); + if (SecondLevelPagingEntry =3D=3D NULL) { + return NULL; + } + + if (mAbove4GMemoryLimit !=3D 0) { + ASSERT (mAbove4GMemoryLimit > BASE_4GB); + SecondLevelPagingEntry =3D CreateSecondLevelPagingEntryTable (VtdIndex= , SecondLevelPagingEntry, SIZE_4GB, mAbove4GMemoryLimit, IoMmuAccess); + if (SecondLevelPagingEntry =3D=3D NULL) { + return NULL; + } + } + + return SecondLevelPagingEntry; +} + +/** + Setup VTd translation table. + + @retval EFI_SUCCESS Setup translation table successfully. + @retval EFI_OUT_OF_RESOURCE Setup translation table fail. +**/ +EFI_STATUS +SetupTranslationTable ( + VOID + ) +{ + EFI_STATUS Status; + UINTN Index; + + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + DEBUG((DEBUG_INFO, "CreateContextEntry - %d\n", Index)); + if (mVtdUnitInformation[Index].ECapReg.Bits.ECS) { + Status =3D CreateExtContextEntry (Index); + } else { + Status =3D CreateContextEntry (Index); + } + if (EFI_ERROR (Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} + +/** + Dump DMAR context entry table. + + @param[in] RootEntry DMAR root entry. +**/ +VOID +DumpDmarContextEntryTable ( + IN VTD_ROOT_ENTRY *RootEntry + ) +{ + UINTN Index; + UINTN Index2; + VTD_CONTEXT_ENTRY *ContextEntry; + + DEBUG ((DEBUG_INFO,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D\n")); + DEBUG ((DEBUG_INFO,"DMAR Context Entry Table:\n")); + + DEBUG ((DEBUG_INFO,"RootEntry Address - 0x%x\n", RootEntry)); + + for (Index =3D 0; Index < VTD_ROOT_ENTRY_NUMBER; Index++) { + if ((RootEntry[Index].Uint128.Uint64Lo !=3D 0) || (RootEntry[Index].Ui= nt128.Uint64Hi !=3D 0)) { + DEBUG ((DEBUG_INFO," RootEntry(0x%02x) B%02x - 0x%016lx %016lx\n", + Index, Index, RootEntry[Index].Uint128.Uint64Hi, RootEntry[Index].= Uint128.Uint64Lo)); + } + if (RootEntry[Index].Bits.Present =3D=3D 0) { + continue; + } + ContextEntry =3D (VTD_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS(RootEn= try[Index].Bits.ContextTablePointerLo, RootEntry[Index].Bits.ContextTablePo= interHi); + for (Index2 =3D 0; Index2 < VTD_CONTEXT_ENTRY_NUMBER; Index2++) { + if ((ContextEntry[Index2].Uint128.Uint64Lo !=3D 0) || (ContextEntry[= Index2].Uint128.Uint64Hi !=3D 0)) { + DEBUG ((DEBUG_INFO," ContextEntry(0x%02x) D%02xF%02x - 0x%016lx= %016lx\n", + Index2, Index2 >> 3, Index2 & 0x7, ContextEntry[Index2].Uint128.= Uint64Hi, ContextEntry[Index2].Uint128.Uint64Lo)); + } + if (ContextEntry[Index2].Bits.Present =3D=3D 0) { + continue; + } + DumpSecondLevelPagingEntry ((VOID *)(UINTN)VTD_64BITS_ADDRESS(Contex= tEntry[Index2].Bits.SecondLevelPageTranslationPointerLo, ContextEntry[Index= 2].Bits.SecondLevelPageTranslationPointerHi)); + } + } + DEBUG ((DEBUG_INFO,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D\n")); +} + +/** + Dump DMAR second level paging entry. + + @param[in] SecondLevelPagingEntry The second level paging entry. +**/ +VOID +DumpSecondLevelPagingEntry ( + IN VOID *SecondLevelPagingEntry + ) +{ + UINTN Index4; + UINTN Index3; + UINTN Index2; + UINTN Index1; + VTD_SECOND_LEVEL_PAGING_ENTRY *Lvl4PtEntry; + VTD_SECOND_LEVEL_PAGING_ENTRY *Lvl3PtEntry; + VTD_SECOND_LEVEL_PAGING_ENTRY *Lvl2PtEntry; + VTD_SECOND_LEVEL_PAGING_ENTRY *Lvl1PtEntry; + + DEBUG ((DEBUG_VERBOSE,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\= n")); + DEBUG ((DEBUG_VERBOSE,"DMAR Second Level Page Table:\n")); + + DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry Base - 0x%x\n", SecondLeve= lPagingEntry)); + Lvl4PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)SecondLevelPagingEntry; + for (Index4 =3D 0; Index4 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_ENTR= Y); Index4++) { + if (Lvl4PtEntry[Index4].Uint64 !=3D 0) { + DEBUG ((DEBUG_VERBOSE," Lvl4Pt Entry(0x%03x) - 0x%016lx\n", Index4,= Lvl4PtEntry[Index4].Uint64)); + } + if (Lvl4PtEntry[Index4].Uint64 =3D=3D 0) { + continue; + } + Lvl3PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_ADD= RESS(Lvl4PtEntry[Index4].Bits.AddressLo, Lvl4PtEntry[Index4].Bits.AddressHi= ); + for (Index3 =3D 0; Index3 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_EN= TRY); Index3++) { + if (Lvl3PtEntry[Index3].Uint64 !=3D 0) { + DEBUG ((DEBUG_VERBOSE," Lvl3Pt Entry(0x%03x) - 0x%016lx\n", Ind= ex3, Lvl3PtEntry[Index3].Uint64)); + } + if (Lvl3PtEntry[Index3].Uint64 =3D=3D 0) { + continue; + } + + Lvl2PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BITS_A= DDRESS(Lvl3PtEntry[Index3].Bits.AddressLo, Lvl3PtEntry[Index3].Bits.Address= Hi); + for (Index2 =3D 0; Index2 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAGING_= ENTRY); Index2++) { + if (Lvl2PtEntry[Index2].Uint64 !=3D 0) { + DEBUG ((DEBUG_VERBOSE," Lvl2Pt Entry(0x%03x) - 0x%016lx\n",= Index2, Lvl2PtEntry[Index2].Uint64)); + } + if (Lvl2PtEntry[Index2].Uint64 =3D=3D 0) { + continue; + } + if (Lvl2PtEntry[Index2].Bits.PageSize =3D=3D 0) { + Lvl1PtEntry =3D (VTD_SECOND_LEVEL_PAGING_ENTRY *)(UINTN)VTD_64BI= TS_ADDRESS(Lvl2PtEntry[Index2].Bits.AddressLo, Lvl2PtEntry[Index2].Bits.Add= ressHi); + for (Index1 =3D 0; Index1 < SIZE_4KB/sizeof(VTD_SECOND_LEVEL_PAG= ING_ENTRY); Index1++) { + if (Lvl1PtEntry[Index1].Uint64 !=3D 0) { + DEBUG ((DEBUG_VERBOSE," Lvl1Pt Entry(0x%03x) - 0x%016= lx\n", Index1, Lvl1PtEntry[Index1].Uint64)); + } + } + } + } + } + } + DEBUG ((DEBUG_VERBOSE,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\= n")); +} + +/** + Invalid page entry. + + @param VtdIndex The VTd engine index. +**/ +VOID +InvalidatePageEntry ( + IN UINTN VtdIndex + ) +{ + if (mVtdUnitInformation[VtdIndex].HasDirtyContext || mVtdUnitInformation= [VtdIndex].HasDirtyPages) { + InvalidateVtdIOTLBGlobal (VtdIndex); + } + mVtdUnitInformation[VtdIndex].HasDirtyContext =3D FALSE; + mVtdUnitInformation[VtdIndex].HasDirtyPages =3D FALSE; +} + +#define VTD_PG_R BIT0 +#define VTD_PG_W BIT1 +#define VTD_PG_X BIT2 +#define VTD_PG_EMT (BIT3 | BIT4 | BIT5) +#define VTD_PG_TM (BIT62) + +#define VTD_PG_PS BIT7 + +#define PAGE_PROGATE_BITS (VTD_PG_TM | VTD_PG_EMT | VTD_PG_W | VT= D_PG_R) + +#define PAGING_4K_MASK 0xFFF +#define PAGING_2M_MASK 0x1FFFFF +#define PAGING_1G_MASK 0x3FFFFFFF + +#define PAGING_VTD_INDEX_MASK 0x1FF + +#define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull +#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull +#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull + +typedef enum { + PageNone, + Page4K, + Page2M, + Page1G, +} PAGE_ATTRIBUTE; + +typedef struct { + PAGE_ATTRIBUTE Attribute; + UINT64 Length; + UINT64 AddressMask; +} PAGE_ATTRIBUTE_TABLE; + +PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { + {Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64}, + {Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64}, + {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, +}; + +/** + Return length according to page attributes. + + @param[in] PageAttributes The page attribute of the page entry. + + @return The length of page entry. +**/ +UINTN +PageAttributeToLength ( + IN PAGE_ATTRIBUTE PageAttribute + ) +{ + UINTN Index; + for (Index =3D 0; Index < sizeof(mPageAttributeTable)/sizeof(mPageAttrib= uteTable[0]); Index++) { + if (PageAttribute =3D=3D mPageAttributeTable[Index].Attribute) { + return (UINTN)mPageAttributeTable[Index].Length; + } + } + return 0; +} + +/** + Return page table entry to match the address. + + @param[in] VtdIndex The index used to identify a VTd e= ngine. + @param[in] SecondLevelPagingEntry The second level paging entry in V= Td table for the device. + @param[in] Address The address to be checked. + @param[out] PageAttributes The page attribute of the page ent= ry. + + @return The page entry. +**/ +VOID * +GetSecondLevelPageTableEntry ( + IN UINTN VtdIndex, + IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry, + IN PHYSICAL_ADDRESS Address, + OUT PAGE_ATTRIBUTE *PageAttribute + ) +{ + UINTN Index1; + UINTN Index2; + UINTN Index3; + UINTN Index4; + UINT64 *L1PageTable; + UINT64 *L2PageTable; + UINT64 *L3PageTable; + UINT64 *L4PageTable; + + Index4 =3D ((UINTN)RShiftU64 (Address, 39)) & PAGING_VTD_INDEX_MASK; + Index3 =3D ((UINTN)Address >> 30) & PAGING_VTD_INDEX_MASK; + Index2 =3D ((UINTN)Address >> 21) & PAGING_VTD_INDEX_MASK; + Index1 =3D ((UINTN)Address >> 12) & PAGING_VTD_INDEX_MASK; + + L4PageTable =3D (UINT64 *)SecondLevelPagingEntry; + if (L4PageTable[Index4] =3D=3D 0) { + L4PageTable[Index4] =3D (UINT64)(UINTN)AllocateZeroPages (1); + if (L4PageTable[Index4] =3D=3D 0) { + DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL4 PAGE FAIL (0x%x)!!!!!!\n",= Index4)); + ASSERT(FALSE); + *PageAttribute =3D PageNone; + return NULL; + } + FlushPageTableMemory (VtdIndex, (UINTN)L4PageTable[Index4], SIZE_4KB); + SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&= L4PageTable[Index4], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); + FlushPageTableMemory (VtdIndex, (UINTN)&L4PageTable[Index4], sizeof(L4= PageTable[Index4])); + } + + L3PageTable =3D (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDRES= S_MASK_64); + if (L3PageTable[Index3] =3D=3D 0) { + L3PageTable[Index3] =3D (UINT64)(UINTN)AllocateZeroPages (1); + if (L3PageTable[Index3] =3D=3D 0) { + DEBUG ((DEBUG_ERROR,"!!!!!! ALLOCATE LVL3 PAGE FAIL (0x%x, 0x%x)!!!!= !!\n", Index4, Index3)); + ASSERT(FALSE); + *PageAttribute =3D PageNone; + return NULL; + } + FlushPageTableMemory (VtdIndex, (UINTN)L3PageTable[Index3], SIZE_4KB); + SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&= L3PageTable[Index3], EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCESS_WRITE); + FlushPageTableMemory (VtdIndex, (UINTN)&L3PageTable[Index3], sizeof(L3= PageTable[Index3])); + } + if ((L3PageTable[Index3] & VTD_PG_PS) !=3D 0) { + // 1G + *PageAttribute =3D Page1G; + return &L3PageTable[Index3]; + } + + L2PageTable =3D (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRES= S_MASK_64); + if (L2PageTable[Index2] =3D=3D 0) { + L2PageTable[Index2] =3D Address & PAGING_2M_ADDRESS_MASK_64; + SetSecondLevelPagingEntryAttribute ((VTD_SECOND_LEVEL_PAGING_ENTRY *)&= L2PageTable[Index2], 0); + L2PageTable[Index2] |=3D VTD_PG_PS; + FlushPageTableMemory (VtdIndex, (UINTN)&L2PageTable[Index2], sizeof(L2= PageTable[Index2])); + } + if ((L2PageTable[Index2] & VTD_PG_PS) !=3D 0) { + // 2M + *PageAttribute =3D Page2M; + return &L2PageTable[Index2]; + } + + // 4k + L1PageTable =3D (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRES= S_MASK_64); + if ((L1PageTable[Index1] =3D=3D 0) && (Address !=3D 0)) { + *PageAttribute =3D PageNone; + return NULL; + } + *PageAttribute =3D Page4K; + return &L1PageTable[Index1]; +} + +/** + Modify memory attributes of page entry. + + @param[in] VtdIndex The index used to identify a VTd engine. + @param[in] PageEntry The page entry. + @param[in] IoMmuAccess The IOMMU access. + @param[out] IsModified TRUE means page table modified. FALSE mean= s page table not modified. +**/ +VOID +ConvertSecondLevelPageEntryAttribute ( + IN UINTN VtdIndex, + IN VTD_SECOND_LEVEL_PAGING_ENTRY *PageEntry, + IN UINT64 IoMmuAccess, + OUT BOOLEAN *IsModified + ) +{ + UINT64 CurrentPageEntry; + UINT64 NewPageEntry; + + CurrentPageEntry =3D PageEntry->Uint64; + SetSecondLevelPagingEntryAttribute (PageEntry, IoMmuAccess); + FlushPageTableMemory (VtdIndex, (UINTN)PageEntry, sizeof(*PageEntry)); + NewPageEntry =3D PageEntry->Uint64; + if (CurrentPageEntry !=3D NewPageEntry) { + *IsModified =3D TRUE; + DEBUG ((DEBUG_VERBOSE, "ConvertSecondLevelPageEntryAttribute 0x%lx", C= urrentPageEntry)); + DEBUG ((DEBUG_VERBOSE, "->0x%lx\n", NewPageEntry)); + } else { + *IsModified =3D FALSE; + } +} + +/** + This function returns if there is need to split page entry. + + @param[in] BaseAddress The base address to be checked. + @param[in] Length The length to be checked. + @param[in] PageAttribute The page attribute of the page entry. + + @retval SplitAttributes on if there is need to split page entry. +**/ +PAGE_ATTRIBUTE +NeedSplitPage ( + IN PHYSICAL_ADDRESS BaseAddress, + IN UINT64 Length, + IN PAGE_ATTRIBUTE PageAttribute + ) +{ + UINT64 PageEntryLength; + + PageEntryLength =3D PageAttributeToLength (PageAttribute); + + if (((BaseAddress & (PageEntryLength - 1)) =3D=3D 0) && (Length >=3D Pag= eEntryLength)) { + return PageNone; + } + + if (((BaseAddress & PAGING_2M_MASK) !=3D 0) || (Length < SIZE_2MB)) { + return Page4K; + } + + return Page2M; +} + +/** + This function splits one page entry to small page entries. + + @param[in] VtdIndex The index used to identify a VTd engine. + @param[in] PageEntry The page entry to be splitted. + @param[in] PageAttribute The page attribute of the page entry. + @param[in] SplitAttribute How to split the page entry. + + @retval RETURN_SUCCESS The page entry is splitted. + @retval RETURN_UNSUPPORTED The page entry does not support to be = splitted. + @retval RETURN_OUT_OF_RESOURCES No resource to split page entry. +**/ +RETURN_STATUS +SplitSecondLevelPage ( + IN UINTN VtdIndex, + IN VTD_SECOND_LEVEL_PAGING_ENTRY *PageEntry, + IN PAGE_ATTRIBUTE PageAttribute, + IN PAGE_ATTRIBUTE SplitAttribute + ) +{ + UINT64 BaseAddress; + UINT64 *NewPageEntry; + UINTN Index; + + ASSERT (PageAttribute =3D=3D Page2M || PageAttribute =3D=3D Page1G); + + if (PageAttribute =3D=3D Page2M) { + // + // Split 2M to 4K + // + ASSERT (SplitAttribute =3D=3D Page4K); + if (SplitAttribute =3D=3D Page4K) { + NewPageEntry =3D AllocateZeroPages (1); + DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry)); + if (NewPageEntry =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + BaseAddress =3D PageEntry->Uint64 & PAGING_2M_ADDRESS_MASK_64; + for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + NewPageEntry[Index] =3D (BaseAddress + SIZE_4KB * Index) | (PageEn= try->Uint64 & PAGE_PROGATE_BITS); + } + FlushPageTableMemory (VtdIndex, (UINTN)NewPageEntry, SIZE_4KB); + + PageEntry->Uint64 =3D (UINT64)(UINTN)NewPageEntry; + SetSecondLevelPagingEntryAttribute (PageEntry, EDKII_IOMMU_ACCESS_RE= AD | EDKII_IOMMU_ACCESS_WRITE); + FlushPageTableMemory (VtdIndex, (UINTN)PageEntry, sizeof(*PageEntry)= ); + return RETURN_SUCCESS; + } else { + return RETURN_UNSUPPORTED; + } + } else if (PageAttribute =3D=3D Page1G) { + // + // Split 1G to 2M + // No need support 1G->4K directly, we should use 1G->2M, then 2M->4K = to get more compact page table. + // + ASSERT (SplitAttribute =3D=3D Page2M || SplitAttribute =3D=3D Page4K); + if ((SplitAttribute =3D=3D Page2M || SplitAttribute =3D=3D Page4K)) { + NewPageEntry =3D AllocateZeroPages (1); + DEBUG ((DEBUG_VERBOSE, "Split - 0x%x\n", NewPageEntry)); + if (NewPageEntry =3D=3D NULL) { + return RETURN_OUT_OF_RESOURCES; + } + BaseAddress =3D PageEntry->Uint64 & PAGING_1G_ADDRESS_MASK_64; + for (Index =3D 0; Index < SIZE_4KB / sizeof(UINT64); Index++) { + NewPageEntry[Index] =3D (BaseAddress + SIZE_2MB * Index) | VTD_PG_= PS | (PageEntry->Uint64 & PAGE_PROGATE_BITS); + } + FlushPageTableMemory (VtdIndex, (UINTN)NewPageEntry, SIZE_4KB); + + PageEntry->Uint64 =3D (UINT64)(UINTN)NewPageEntry; + SetSecondLevelPagingEntryAttribute (PageEntry, EDKII_IOMMU_ACCESS_RE= AD | EDKII_IOMMU_ACCESS_WRITE); + FlushPageTableMemory (VtdIndex, (UINTN)PageEntry, sizeof(*PageEntry)= ); + return RETURN_SUCCESS; + } else { + return RETURN_UNSUPPORTED; + } + } else { + return RETURN_UNSUPPORTED; + } +} + +/** + Set VTd attribute for a system memory on second level page entry + + @param[in] VtdIndex The index used to identify a VTd eng= ine. + @param[in] DomainIdentifier The domain ID of the source. + @param[in] SecondLevelPagingEntry The second level paging entry in VTd= table for the device. + @param[in] BaseAddress The base of device memory address to= be used as the DMA memory. + @param[in] Length The length of device memory address = to be used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by BaseAddress and Length. + @retval EFI_INVALID_PARAMETER BaseAddress is not IoMmu Page size aligne= d. + @retval EFI_INVALID_PARAMETER Length is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is 0. + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by BaseAddress and Length. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. +**/ +EFI_STATUS +SetSecondLevelPagingAttribute ( + IN UINTN VtdIndex, + IN UINT16 DomainIdentifier, + IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ) +{ + VTD_SECOND_LEVEL_PAGING_ENTRY *PageEntry; + PAGE_ATTRIBUTE PageAttribute; + UINTN PageEntryLength; + PAGE_ATTRIBUTE SplitAttribute; + EFI_STATUS Status; + BOOLEAN IsEntryModified; + + DEBUG ((DEBUG_VERBOSE,"SetSecondLevelPagingAttribute (%d) (0x%016lx - 0x= %016lx : %x) \n", VtdIndex, BaseAddress, Length, IoMmuAccess)); + DEBUG ((DEBUG_VERBOSE," SecondLevelPagingEntry Base - 0x%x\n", SecondLe= velPagingEntry)); + + if (BaseAddress !=3D ALIGN_VALUE(BaseAddress, SIZE_4KB)) { + DEBUG ((DEBUG_ERROR, "SetSecondLevelPagingAttribute - Invalid Alignmen= t\n")); + return EFI_UNSUPPORTED; + } + if (Length !=3D ALIGN_VALUE(Length, SIZE_4KB)) { + DEBUG ((DEBUG_ERROR, "SetSecondLevelPagingAttribute - Invalid Alignmen= t\n")); + return EFI_UNSUPPORTED; + } + + while (Length !=3D 0) { + PageEntry =3D GetSecondLevelPageTableEntry (VtdIndex, SecondLevelPagin= gEntry, BaseAddress, &PageAttribute); + if (PageEntry =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "PageEntry - NULL\n")); + return RETURN_UNSUPPORTED; + } + PageEntryLength =3D PageAttributeToLength (PageAttribute); + SplitAttribute =3D NeedSplitPage (BaseAddress, Length, PageAttribute); + if (SplitAttribute =3D=3D PageNone) { + ConvertSecondLevelPageEntryAttribute (VtdIndex, PageEntry, IoMmuAcce= ss, &IsEntryModified); + if (IsEntryModified) { + mVtdUnitInformation[VtdIndex].HasDirtyPages =3D TRUE; + } + // + // Convert success, move to next + // + BaseAddress +=3D PageEntryLength; + Length -=3D PageEntryLength; + } else { + Status =3D SplitSecondLevelPage (VtdIndex, PageEntry, PageAttribute,= SplitAttribute); + if (RETURN_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "SplitSecondLevelPage - %r\n", Status)); + return RETURN_UNSUPPORTED; + } + mVtdUnitInformation[VtdIndex].HasDirtyPages =3D TRUE; + // + // Just split current page + // Convert success in next around + // + } + } + + return EFI_SUCCESS; +} + +/** + Set VTd attribute for a system memory. + + @param[in] VtdIndex The index used to identify a VTd eng= ine. + @param[in] DomainIdentifier The domain ID of the source. + @param[in] SecondLevelPagingEntry The second level paging entry in VTd= table for the device. + @param[in] BaseAddress The base of device memory address to= be used as the DMA memory. + @param[in] Length The length of device memory address = to be used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by BaseAddress and Length. + @retval EFI_INVALID_PARAMETER BaseAddress is not IoMmu Page size aligne= d. + @retval EFI_INVALID_PARAMETER Length is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is 0. + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by BaseAddress and Length. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. +**/ +EFI_STATUS +SetPageAttribute ( + IN UINTN VtdIndex, + IN UINT16 DomainIdentifier, + IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ) +{ + EFI_STATUS Status; + Status =3D EFI_NOT_FOUND; + if (SecondLevelPagingEntry !=3D NULL) { + Status =3D SetSecondLevelPagingAttribute (VtdIndex, DomainIdentifier, = SecondLevelPagingEntry, BaseAddress, Length, IoMmuAccess); + } + return Status; +} + +/** + Set VTd attribute for a system memory. + + @param[in] Segment The Segment used to identify a VTd engine. + @param[in] SourceId The SourceId used to identify a VTd engine= and table entry. + @param[in] BaseAddress The base of device memory address to be us= ed as the DMA memory. + @param[in] Length The length of device memory address to be = used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by BaseAddress and Length. + @retval EFI_INVALID_PARAMETER BaseAddress is not IoMmu Page size aligne= d. + @retval EFI_INVALID_PARAMETER Length is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is 0. + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by BaseAddress and Length. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. +**/ +EFI_STATUS +SetAccessAttribute ( + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ) +{ + UINTN VtdIndex; + EFI_STATUS Status; + VTD_EXT_CONTEXT_ENTRY *ExtContextEntry; + VTD_CONTEXT_ENTRY *ContextEntry; + VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry; + UINT64 Pt; + UINTN PciDataIndex; + UINT16 DomainIdentifier; + + SecondLevelPagingEntry =3D NULL; + + DEBUG ((DEBUG_VERBOSE,"SetAccessAttribute (S%04x B%02x D%02x F%02x) (0x%= 016lx - 0x%08x, %x)\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, S= ourceId.Bits.Function, BaseAddress, (UINTN)Length, IoMmuAccess)); + + VtdIndex =3D FindVtdIndexByPciDevice (Segment, SourceId, &ExtContextEntr= y, &ContextEntry); + if (VtdIndex =3D=3D (UINTN)-1) { + DEBUG ((DEBUG_ERROR,"SetAccessAttribute - Pci device (S%04x B%02x D%02= x F%02x) not found!\n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, S= ourceId.Bits.Function)); + return EFI_DEVICE_ERROR; + } + + PciDataIndex =3D GetPciDataIndex (VtdIndex, Segment, SourceId); + mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDeviceData[PciDataIndex].= AccessCount++; + // + // DomainId should not be 0. + // + DomainIdentifier =3D (UINT16)(PciDataIndex + 1); + + if (ExtContextEntry !=3D NULL) { + if (ExtContextEntry->Bits.Present =3D=3D 0) { + SecondLevelPagingEntry =3D CreateSecondLevelPagingEntry (VtdIndex, 0= ); + DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%= 02x F%02x) New\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, Sour= ceId.Bits.Device, SourceId.Bits.Function)); + Pt =3D (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 12); + + ExtContextEntry->Bits.SecondLevelPageTranslationPointerLo =3D (UINT3= 2) Pt; + ExtContextEntry->Bits.SecondLevelPageTranslationPointerHi =3D (UINT3= 2) RShiftU64(Pt, 20); + ExtContextEntry->Bits.DomainIdentifier =3D DomainIdentifier; + ExtContextEntry->Bits.Present =3D 1; + FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry, sizeof(*ExtC= ontextEntry)); + DumpDmarExtContextEntryTable (mVtdUnitInformation[VtdIndex].ExtRootE= ntryTable); + mVtdUnitInformation[VtdIndex].HasDirtyContext =3D TRUE; + } else { + SecondLevelPagingEntry =3D (VOID *)(UINTN)VTD_64BITS_ADDRESS(ExtCont= extEntry->Bits.SecondLevelPageTranslationPointerLo, ExtContextEntry->Bits.S= econdLevelPageTranslationPointerHi); + DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%= 02x F%02x)\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, SourceId= .Bits.Device, SourceId.Bits.Function)); + } + } else if (ContextEntry !=3D NULL) { + if (ContextEntry->Bits.Present =3D=3D 0) { + SecondLevelPagingEntry =3D CreateSecondLevelPagingEntry (VtdIndex, 0= ); + DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%= 02x F%02x) New\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, Sour= ceId.Bits.Device, SourceId.Bits.Function)); + Pt =3D (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 12); + + ContextEntry->Bits.SecondLevelPageTranslationPointerLo =3D (UINT32) = Pt; + ContextEntry->Bits.SecondLevelPageTranslationPointerHi =3D (UINT32) = RShiftU64(Pt, 20); + ContextEntry->Bits.DomainIdentifier =3D DomainIdentifier; + ContextEntry->Bits.Present =3D 1; + FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry, sizeof(*Context= Entry)); + DumpDmarContextEntryTable (mVtdUnitInformation[VtdIndex].RootEntryTa= ble); + mVtdUnitInformation[VtdIndex].HasDirtyContext =3D TRUE; + } else { + SecondLevelPagingEntry =3D (VOID *)(UINTN)VTD_64BITS_ADDRESS(Context= Entry->Bits.SecondLevelPageTranslationPointerLo, ContextEntry->Bits.SecondL= evelPageTranslationPointerHi); + DEBUG ((DEBUG_VERBOSE,"SecondLevelPagingEntry - 0x%x (S%04x B%02x D%= 02x F%02x)\n", SecondLevelPagingEntry, Segment, SourceId.Bits.Bus, SourceId= .Bits.Device, SourceId.Bits.Function)); + } + } + + // + // Do not update FixedSecondLevelPagingEntry + // + if (SecondLevelPagingEntry !=3D mVtdUnitInformation[VtdIndex].FixedSecon= dLevelPagingEntry) { + Status =3D SetPageAttribute ( + VtdIndex, + DomainIdentifier, + SecondLevelPagingEntry, + BaseAddress, + Length, + IoMmuAccess + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR,"SetPageAttribute - %r\n", Status)); + return Status; + } + } + + InvalidatePageEntry (VtdIndex); + + return EFI_SUCCESS; +} + +/** + Always enable the VTd page attribute for the device. + + @param[in] Segment The Segment used to identify a VTd engine. + @param[in] SourceId The SourceId used to identify a VTd engine= and table entry. + + @retval EFI_SUCCESS The VTd entry is updated to always enable = all DMA access for the specific device. +**/ +EFI_STATUS +AlwaysEnablePageAttribute ( + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId + ) +{ + UINTN VtdIndex; + VTD_EXT_CONTEXT_ENTRY *ExtContextEntry; + VTD_CONTEXT_ENTRY *ContextEntry; + VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry; + UINT64 Pt; + + DEBUG ((DEBUG_INFO,"AlwaysEnablePageAttribute (S%04x B%02x D%02x F%02x)\= n", Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Functio= n)); + + VtdIndex =3D FindVtdIndexByPciDevice (Segment, SourceId, &ExtContextEntr= y, &ContextEntry); + if (VtdIndex =3D=3D (UINTN)-1) { + DEBUG ((DEBUG_ERROR,"AlwaysEnablePageAttribute - Pci device (S%04x B%0= 2x D%02x F%02x) not found!\n", Segment, SourceId.Bits.Bus, SourceId.Bits.De= vice, SourceId.Bits.Function)); + return EFI_DEVICE_ERROR; + } + + if (mVtdUnitInformation[VtdIndex].FixedSecondLevelPagingEntry =3D=3D 0) { + DEBUG((DEBUG_INFO, "CreateSecondLevelPagingEntry - %d\n", VtdIndex)); + mVtdUnitInformation[VtdIndex].FixedSecondLevelPagingEntry =3D CreateSe= condLevelPagingEntry (VtdIndex, EDKII_IOMMU_ACCESS_READ | EDKII_IOMMU_ACCES= S_WRITE); + } + + SecondLevelPagingEntry =3D mVtdUnitInformation[VtdIndex].FixedSecondLeve= lPagingEntry; + Pt =3D (UINT64)RShiftU64 ((UINT64)(UINTN)SecondLevelPagingEntry, 12); + if (ExtContextEntry !=3D NULL) { + ExtContextEntry->Bits.SecondLevelPageTranslationPointerLo =3D (UINT32)= Pt; + ExtContextEntry->Bits.SecondLevelPageTranslationPointerHi =3D (UINT32)= RShiftU64(Pt, 20); + ExtContextEntry->Bits.DomainIdentifier =3D ((1 << (UINT8)((UINTN)mVtdU= nitInformation[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1); + ExtContextEntry->Bits.Present =3D 1; + FlushPageTableMemory (VtdIndex, (UINTN)ExtContextEntry, sizeof(*ExtCon= textEntry)); + } else if (ContextEntry !=3D NULL) { + ContextEntry->Bits.SecondLevelPageTranslationPointerLo =3D (UINT32) Pt; + ContextEntry->Bits.SecondLevelPageTranslationPointerHi =3D (UINT32) RS= hiftU64(Pt, 20); + ContextEntry->Bits.DomainIdentifier =3D ((1 << (UINT8)((UINTN)mVtdUnit= Information[VtdIndex].CapReg.Bits.ND * 2 + 4)) - 1); + ContextEntry->Bits.Present =3D 1; + FlushPageTableMemory (VtdIndex, (UINTN)ContextEntry, sizeof(*ContextEn= try)); + } + + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transl= ationTableEx.c new file mode 100644 index 0000000000..ee8c9e3ad2 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= eEx.c @@ -0,0 +1,152 @@ +/** @file + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DmaProtection.h" + +/** + Create extended context entry. + + @param[in] VtdIndex The index of the VTd engine. + + @retval EFI_SUCCESS The extended context entry is created. + @retval EFI_OUT_OF_RESOURCE No enough resource to create extended conte= xt entry. +**/ +EFI_STATUS +CreateExtContextEntry ( + IN UINTN VtdIndex + ) +{ + UINTN Index; + VOID *Buffer; + UINTN RootPages; + UINTN ContextPages; + VTD_EXT_ROOT_ENTRY *ExtRootEntry; + VTD_EXT_CONTEXT_ENTRY *ExtContextEntryTable; + VTD_EXT_CONTEXT_ENTRY *ExtContextEntry; + VTD_SOURCE_ID *PciSourceId; + VTD_SOURCE_ID SourceId; + UINTN MaxBusNumber; + UINTN EntryTablePages; + + MaxBusNumber =3D 0; + for (Index =3D 0; Index < mVtdUnitInformation[VtdIndex].PciDeviceInfo.Pc= iDeviceDataNumber; Index++) { + PciSourceId =3D &mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDevice= Data[Index].PciSourceId; + if (PciSourceId->Bits.Bus > MaxBusNumber) { + MaxBusNumber =3D PciSourceId->Bits.Bus; + } + } + DEBUG ((DEBUG_INFO," MaxBusNumber - 0x%x\n", MaxBusNumber)); + + RootPages =3D EFI_SIZE_TO_PAGES (sizeof (VTD_EXT_ROOT_ENTRY) * VTD_ROOT_= ENTRY_NUMBER); + ContextPages =3D EFI_SIZE_TO_PAGES (sizeof (VTD_EXT_CONTEXT_ENTRY) * VTD= _CONTEXT_ENTRY_NUMBER); + EntryTablePages =3D RootPages + ContextPages * (MaxBusNumber + 1); + Buffer =3D AllocateZeroPages (EntryTablePages); + if (Buffer =3D=3D NULL) { + DEBUG ((DEBUG_INFO,"Could not Alloc Root Entry Table.. \n")); + return EFI_OUT_OF_RESOURCES; + } + mVtdUnitInformation[VtdIndex].ExtRootEntryTable =3D (VTD_EXT_ROOT_ENTRY = *)Buffer; + Buffer =3D (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (RootPages); + + for (Index =3D 0; Index < mVtdUnitInformation[VtdIndex].PciDeviceInfo.Pc= iDeviceDataNumber; Index++) { + PciSourceId =3D &mVtdUnitInformation[VtdIndex].PciDeviceInfo.PciDevice= Data[Index].PciSourceId; + + SourceId.Bits.Bus =3D PciSourceId->Bits.Bus; + SourceId.Bits.Device =3D PciSourceId->Bits.Device; + SourceId.Bits.Function =3D PciSourceId->Bits.Function; + + ExtRootEntry =3D &mVtdUnitInformation[VtdIndex].ExtRootEntryTable[Sour= ceId.Index.RootIndex]; + if (ExtRootEntry->Bits.LowerPresent =3D=3D 0) { + ExtRootEntry->Bits.LowerContextTablePointerLo =3D (UINT32) RShiftU6= 4 ((UINT64)(UINTN)Buffer, 12); + ExtRootEntry->Bits.LowerContextTablePointerHi =3D (UINT32) RShiftU6= 4 ((UINT64)(UINTN)Buffer, 32); + ExtRootEntry->Bits.LowerPresent =3D 1; + ExtRootEntry->Bits.UpperContextTablePointerLo =3D (UINT32) RShiftU6= 4 ((UINT64)(UINTN)Buffer, 12) + 1; + ExtRootEntry->Bits.UpperContextTablePointerHi =3D (UINT32) RShiftU6= 4 (RShiftU64 ((UINT64)(UINTN)Buffer, 12) + 1, 20); + ExtRootEntry->Bits.UpperPresent =3D 1; + Buffer =3D (UINT8 *)Buffer + EFI_PAGES_TO_SIZE (ContextPages); + } + + ExtContextEntryTable =3D (VTD_EXT_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_AD= DRESS(ExtRootEntry->Bits.LowerContextTablePointerLo, ExtRootEntry->Bits.Low= erContextTablePointerHi) ; + ExtContextEntry =3D &ExtContextEntryTable[SourceId.Index.ContextIndex]; + ExtContextEntry->Bits.TranslationType =3D 0; + ExtContextEntry->Bits.FaultProcessingDisable =3D 0; + ExtContextEntry->Bits.Present =3D 0; + + DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInfor= mation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId= .Bits.Function)); + + switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { + case BIT1: + ExtContextEntry->Bits.AddressWidth =3D 0x1; + break; + case BIT2: + ExtContextEntry->Bits.AddressWidth =3D 0x2; + break; + } + } + + FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ext= RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); + + return EFI_SUCCESS; +} + +/** + Dump DMAR extended context entry table. + + @param[in] ExtRootEntry DMAR extended root entry. +**/ +VOID +DumpDmarExtContextEntryTable ( + IN VTD_EXT_ROOT_ENTRY *ExtRootEntry + ) +{ + UINTN Index; + UINTN Index2; + VTD_EXT_CONTEXT_ENTRY *ExtContextEntry; + + DEBUG ((DEBUG_INFO,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D\n")); + DEBUG ((DEBUG_INFO,"DMAR ExtContext Entry Table:\n")); + + DEBUG ((DEBUG_INFO,"ExtRootEntry Address - 0x%x\n", ExtRootEntry)); + + for (Index =3D 0; Index < VTD_ROOT_ENTRY_NUMBER; Index++) { + if ((ExtRootEntry[Index].Uint128.Uint64Lo !=3D 0) || (ExtRootEntry[Ind= ex].Uint128.Uint64Hi !=3D 0)) { + DEBUG ((DEBUG_INFO," ExtRootEntry(0x%02x) B%02x - 0x%016lx %016lx\n= ", + Index, Index, ExtRootEntry[Index].Uint128.Uint64Hi, ExtRootEntry[I= ndex].Uint128.Uint64Lo)); + } + if (ExtRootEntry[Index].Bits.LowerPresent =3D=3D 0) { + continue; + } + ExtContextEntry =3D (VTD_EXT_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS= (ExtRootEntry[Index].Bits.LowerContextTablePointerLo, ExtRootEntry[Index].B= its.LowerContextTablePointerHi); + for (Index2 =3D 0; Index2 < VTD_CONTEXT_ENTRY_NUMBER/2; Index2++) { + if ((ExtContextEntry[Index2].Uint256.Uint64_1 !=3D 0) || (ExtContext= Entry[Index2].Uint256.Uint64_2 !=3D 0) || + (ExtContextEntry[Index2].Uint256.Uint64_3 !=3D 0) || (ExtContext= Entry[Index2].Uint256.Uint64_4 !=3D 0)) { + DEBUG ((DEBUG_INFO," ExtContextEntryLower(0x%02x) D%02xF%02x - = 0x%016lx %016lx %016lx %016lx\n", + Index2, Index2 >> 3, Index2 & 0x7, ExtContextEntry[Index2].Uint2= 56.Uint64_4, ExtContextEntry[Index2].Uint256.Uint64_3, ExtContextEntry[Inde= x2].Uint256.Uint64_2, ExtContextEntry[Index2].Uint256.Uint64_1)); + } + if (ExtContextEntry[Index2].Bits.Present =3D=3D 0) { + continue; + } + DumpSecondLevelPagingEntry ((VOID *)(UINTN)VTD_64BITS_ADDRESS(ExtCon= textEntry[Index2].Bits.SecondLevelPageTranslationPointerLo, ExtContextEntry= [Index2].Bits.SecondLevelPageTranslationPointerHi)); + } + + if (ExtRootEntry[Index].Bits.UpperPresent =3D=3D 0) { + continue; + } + ExtContextEntry =3D (VTD_EXT_CONTEXT_ENTRY *)(UINTN)VTD_64BITS_ADDRESS= (ExtRootEntry[Index].Bits.UpperContextTablePointerLo, ExtRootEntry[Index].B= its.UpperContextTablePointerHi); + for (Index2 =3D 0; Index2 < VTD_CONTEXT_ENTRY_NUMBER/2; Index2++) { + if ((ExtContextEntry[Index2].Uint256.Uint64_1 !=3D 0) || (ExtContext= Entry[Index2].Uint256.Uint64_2 !=3D 0) || + (ExtContextEntry[Index2].Uint256.Uint64_3 !=3D 0) || (ExtContext= Entry[Index2].Uint256.Uint64_4 !=3D 0)) { + DEBUG ((DEBUG_INFO," ExtContextEntryUpper(0x%02x) D%02xF%02x - = 0x%016lx %016lx %016lx %016lx\n", + Index2, (Index2 + 128) >> 3, (Index2 + 128) & 0x7, ExtContextEnt= ry[Index2].Uint256.Uint64_4, ExtContextEntry[Index2].Uint256.Uint64_3, ExtC= ontextEntry[Index2].Uint256.Uint64_2, ExtContextEntry[Index2].Uint256.Uint6= 4_1)); + } + if (ExtContextEntry[Index2].Bits.Present =3D=3D 0) { + continue; + } + } + } + DEBUG ((DEBUG_INFO,"=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D\n")); +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c= b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c new file mode 100644 index 0000000000..22bf821d2b --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/VtdReg.c @@ -0,0 +1,561 @@ +/** @file + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "DmaProtection.h" + +UINTN mVtdUnitNumber; +VTD_UNIT_INFORMATION *mVtdUnitInformation; + +BOOLEAN mVtdEnabled; + +/** + Flush VTD page table and context table memory. + + This action is to make sure the IOMMU engine can get final data in memor= y. + + @param[in] VtdIndex The index used to identify a VTd engine. + @param[in] Base The base address of memory to be flushed. + @param[in] Size The size of memory in bytes to be flushed. +**/ +VOID +FlushPageTableMemory ( + IN UINTN VtdIndex, + IN UINTN Base, + IN UINTN Size + ) +{ + if (mVtdUnitInformation[VtdIndex].ECapReg.Bits.C =3D=3D 0) { + WriteBackDataCacheRange ((VOID *)Base, Size); + } +} + +/** + Flush VTd engine write buffer. + + @param[in] VtdIndex The index used to identify a VTd engine. +**/ +VOID +FlushWriteBuffer ( + IN UINTN VtdIndex + ) +{ + UINT32 Reg32; + + if (mVtdUnitInformation[VtdIndex].CapReg.Bits.RWBF !=3D 0) { + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress= + R_GSTS_REG); + MmioWrite32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_GCMD= _REG, Reg32 | B_GMCD_REG_WBF); + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddre= ss + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_WBF) !=3D 0); + } +} + +/** + Invalidate VTd context cache. + + @param[in] VtdIndex The index used to identify a VTd engine. +**/ +EFI_STATUS +InvalidateContextCache ( + IN UINTN VtdIndex + ) +{ + UINT64 Reg64; + + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_CCMD_REG); + if ((Reg64 & B_CCMD_REG_ICC) !=3D 0) { + DEBUG ((DEBUG_ERROR,"ERROR: InvalidateContextCache: B_CCMD_REG_ICC is = set for VTD(%d)\n",VtdIndex)); + return EFI_DEVICE_ERROR; + } + + Reg64 &=3D ((~B_CCMD_REG_ICC) & (~B_CCMD_REG_CIRG_MASK)); + Reg64 |=3D (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_GLOBAL); + MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + R_CCMD_R= EG, Reg64); + + do { + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress= + R_CCMD_REG); + } while ((Reg64 & B_CCMD_REG_ICC) !=3D 0); + + return EFI_SUCCESS; +} + +/** + Invalidate VTd IOTLB. + + @param[in] VtdIndex The index used to identify a VTd engine. +**/ +EFI_STATUS +InvalidateIOTLB ( + IN UINTN VtdIndex + ) +{ + UINT64 Reg64; + + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG); + if ((Reg64 & B_IOTLB_REG_IVT) !=3D 0) { + DEBUG ((DEBUG_ERROR,"ERROR: InvalidateIOTLB: B_IOTLB_REG_IVT is set fo= r VTD(%d)\n", VtdIndex)); + return EFI_DEVICE_ERROR; + } + + Reg64 &=3D ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK)); + Reg64 |=3D (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_GLOBAL); + MmioWrite64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress + (mVtdUni= tInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG, Reg64); + + do { + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress= + (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG); + } while ((Reg64 & B_IOTLB_REG_IVT) !=3D 0); + + return EFI_SUCCESS; +} + +/** + Invalid VTd global IOTLB. + + @param[in] VtdIndex The index of VTd engine. + + @retval EFI_SUCCESS VTd global IOTLB is invalidated. + @retval EFI_DEVICE_ERROR VTd global IOTLB is not invalidated. +**/ +EFI_STATUS +InvalidateVtdIOTLBGlobal ( + IN UINTN VtdIndex + ) +{ + if (!mVtdEnabled) { + return EFI_SUCCESS; + } + + DEBUG((DEBUG_VERBOSE, "InvalidateVtdIOTLBGlobal(%d)\n", VtdIndex)); + + // + // Write Buffer Flush before invalidation + // + FlushWriteBuffer (VtdIndex); + + // + // Invalidate the context cache + // + if (mVtdUnitInformation[VtdIndex].HasDirtyContext) { + InvalidateContextCache (VtdIndex); + } + + // + // Invalidate the IOTLB cache + // + if (mVtdUnitInformation[VtdIndex].HasDirtyContext || mVtdUnitInformation= [VtdIndex].HasDirtyPages) { + InvalidateIOTLB (VtdIndex); + } + + return EFI_SUCCESS; +} + +/** + Prepare VTD configuration. +**/ +VOID +PrepareVtdConfig ( + VOID + ) +{ + UINTN Index; + UINTN DomainNumber; + + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + DEBUG ((DEBUG_INFO, "Dump VTd Capability (%d)\n", Index)); + mVtdUnitInformation[Index].CapReg.Uint64 =3D MmioRead64 (mVtdUnitInfor= mation[Index].VtdUnitBaseAddress + R_CAP_REG); + DumpVtdCapRegs (&mVtdUnitInformation[Index].CapReg); + mVtdUnitInformation[Index].ECapReg.Uint64 =3D MmioRead64 (mVtdUnitInfo= rmation[Index].VtdUnitBaseAddress + R_ECAP_REG); + DumpVtdECapRegs (&mVtdUnitInformation[Index].ECapReg); + + if ((mVtdUnitInformation[Index].CapReg.Bits.SLLPS & BIT0) =3D=3D 0) { + DEBUG((DEBUG_WARN, "!!!! 2MB super page is not supported on VTD %d != !!!\n", Index)); + } + if ((mVtdUnitInformation[Index].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD= %d !!!!\n", Index)); + return ; + } + + DomainNumber =3D (UINTN)1 << (UINT8)((UINTN)mVtdUnitInformation[Index]= .CapReg.Bits.ND * 2 + 4); + if (mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber >=3D = DomainNumber) { + DEBUG((DEBUG_ERROR, "!!!! Pci device Number(0x%x) >=3D DomainNumber(= 0x%x) !!!!\n", mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceDataNumber= , DomainNumber)); + return ; + } + } + return ; +} + +/** + Disable PMR in all VTd engine. +**/ +VOID +DisablePmr ( + VOID + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + UINTN Index; + + DEBUG ((DEBUG_INFO,"DisablePmr\n")); + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + CapReg.Uint64 =3D MmioRead64 (mVtdUnitInformation[Index].VtdUnitBaseAd= dress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + continue ; + } + + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_PMEN_ENABLE_REG); + if ((Reg32 & BIT0) !=3D 0) { + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_PMEN_= ENABLE_REG, 0x0); + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddres= s + R_PMEN_ENABLE_REG); + } while((Reg32 & BIT0) !=3D 0); + DEBUG ((DEBUG_INFO,"Pmr(%d) disabled\n", Index)); + } else { + DEBUG ((DEBUG_INFO,"Pmr(%d) not enabled\n", Index)); + } + } + return ; +} + +/** + Enable DMAR translation. + + @retval EFI_SUCCESS DMAR translation is enabled. + @retval EFI_DEVICE_ERROR DMAR translation is not enabled. +**/ +EFI_STATUS +EnableDmar ( + VOID + ) +{ + UINTN Index; + UINT32 Reg32; + + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%d] \n", Index)); + + if (mVtdUnitInformation[Index].ExtRootEntryTable !=3D NULL) { + DEBUG((DEBUG_INFO, "ExtRootEntryTable 0x%x \n", mVtdUnitInformation[= Index].ExtRootEntryTable)); + MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADD= R_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].ExtRootEntryTable | BIT11); + } else { + DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", mVtdUnitInformation[Ind= ex].RootEntryTable)); + MmioWrite64 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_RTADD= R_REG, (UINT64)(UINTN)mVtdUnitInformation[Index].RootEntryTable); + } + + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, B_GMCD_REG_SRTP); + + DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n")= ); + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); + } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + + // + // Init DMAr Fault Event and Data registers + // + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_FEDATA_REG); + + // + // Write Buffer Flush before invalidation + // + FlushWriteBuffer (Index); + + // + // Invalidate the context cache + // + InvalidateContextCache (Index); + + // + // Invalidate the IOTLB cache + // + InvalidateIOTLB (Index); + + // + // Enable VTd + // + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, B_GMCD_REG_TE); + DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n")); + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0); + + DEBUG ((DEBUG_INFO,"VTD (%d) enabled!<<<<<<\n",Index)); + } + + // + // Need disable PMR, since we already setup translation table. + // + DisablePmr (); + + mVtdEnabled =3D TRUE; + + return EFI_SUCCESS; +} + +/** + Disable DMAR translation. + + @retval EFI_SUCCESS DMAR translation is disabled. + @retval EFI_DEVICE_ERROR DMAR translation is not disabled. +**/ +EFI_STATUS +DisableDmar ( + VOID + ) +{ + UINTN Index; + UINTN SubIndex; + UINT32 Reg32; + + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%d] \n", Index)); + + // + // Write Buffer Flush before invalidation + // + FlushWriteBuffer (Index); + + // + // Disable VTd + // + MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_RE= G, B_GMCD_REG_SRTP); + do { + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = + R_GSTS_REG); + } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + + Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + = R_GSTS_REG); + DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32)); + + DEBUG ((DEBUG_INFO,"VTD (%d) Disabled!<<<<<<\n",Index)); + } + + mVtdEnabled =3D FALSE; + + for (Index =3D 0; Index < mVtdUnitNumber; Index++) { + DEBUG((DEBUG_INFO, "engine [%d] access\n", Index)); + for (SubIndex =3D 0; SubIndex < mVtdUnitInformation[Index].PciDeviceIn= fo.PciDeviceDataNumber; SubIndex++) { + DEBUG ((DEBUG_INFO, " PCI S%04X B%02x D%02x F%02x - %d\n", + mVtdUnitInformation[Index].Segment, + mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciS= ourceId.Bits.Bus, + mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciS= ourceId.Bits.Device, + mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].PciS= ourceId.Bits.Function, + mVtdUnitInformation[Index].PciDeviceInfo.PciDeviceData[Index].Acce= ssCount + )); + } + } + + return EFI_SUCCESS; +} + +/** + Dump VTd capability registers. + + @param[in] CapReg The capability register. +**/ +VOID +DumpVtdCapRegs ( + IN VTD_CAP_REG *CapReg + ) +{ + DEBUG((DEBUG_INFO, " CapReg:\n", CapReg->Uint64)); + DEBUG((DEBUG_INFO, " ND - 0x%x\n", CapReg->Bits.ND)); + DEBUG((DEBUG_INFO, " AFL - 0x%x\n", CapReg->Bits.AFL)); + DEBUG((DEBUG_INFO, " RWBF - 0x%x\n", CapReg->Bits.RWBF)); + DEBUG((DEBUG_INFO, " PLMR - 0x%x\n", CapReg->Bits.PLMR)); + DEBUG((DEBUG_INFO, " PHMR - 0x%x\n", CapReg->Bits.PHMR)); + DEBUG((DEBUG_INFO, " CM - 0x%x\n", CapReg->Bits.CM)); + DEBUG((DEBUG_INFO, " SAGAW - 0x%x\n", CapReg->Bits.SAGAW)); + DEBUG((DEBUG_INFO, " MGAW - 0x%x\n", CapReg->Bits.MGAW)); + DEBUG((DEBUG_INFO, " ZLR - 0x%x\n", CapReg->Bits.ZLR)); + DEBUG((DEBUG_INFO, " FRO - 0x%x\n", CapReg->Bits.FRO)); + DEBUG((DEBUG_INFO, " SLLPS - 0x%x\n", CapReg->Bits.SLLPS)); + DEBUG((DEBUG_INFO, " PSI - 0x%x\n", CapReg->Bits.PSI)); + DEBUG((DEBUG_INFO, " NFR - 0x%x\n", CapReg->Bits.NFR)); + DEBUG((DEBUG_INFO, " MAMV - 0x%x\n", CapReg->Bits.MAMV)); + DEBUG((DEBUG_INFO, " DWD - 0x%x\n", CapReg->Bits.DWD)); + DEBUG((DEBUG_INFO, " DRD - 0x%x\n", CapReg->Bits.DRD)); + DEBUG((DEBUG_INFO, " FL1GP - 0x%x\n", CapReg->Bits.FL1GP)); + DEBUG((DEBUG_INFO, " PI - 0x%x\n", CapReg->Bits.PI)); +} + +/** + Dump VTd extended capability registers. + + @param[in] ECapReg The extended capability register. +**/ +VOID +DumpVtdECapRegs ( + IN VTD_ECAP_REG *ECapReg + ) +{ + DEBUG((DEBUG_INFO, " ECapReg:\n", ECapReg->Uint64)); + DEBUG((DEBUG_INFO, " C - 0x%x\n", ECapReg->Bits.C)); + DEBUG((DEBUG_INFO, " QI - 0x%x\n", ECapReg->Bits.QI)); + DEBUG((DEBUG_INFO, " DT - 0x%x\n", ECapReg->Bits.DT)); + DEBUG((DEBUG_INFO, " IR - 0x%x\n", ECapReg->Bits.IR)); + DEBUG((DEBUG_INFO, " EIM - 0x%x\n", ECapReg->Bits.EIM)); + DEBUG((DEBUG_INFO, " PT - 0x%x\n", ECapReg->Bits.PT)); + DEBUG((DEBUG_INFO, " SC - 0x%x\n", ECapReg->Bits.SC)); + DEBUG((DEBUG_INFO, " IRO - 0x%x\n", ECapReg->Bits.IRO)); + DEBUG((DEBUG_INFO, " MHMV - 0x%x\n", ECapReg->Bits.MHMV)); + DEBUG((DEBUG_INFO, " ECS - 0x%x\n", ECapReg->Bits.ECS)); + DEBUG((DEBUG_INFO, " MTS - 0x%x\n", ECapReg->Bits.MTS)); + DEBUG((DEBUG_INFO, " NEST - 0x%x\n", ECapReg->Bits.NEST)); + DEBUG((DEBUG_INFO, " DIS - 0x%x\n", ECapReg->Bits.DIS)); + DEBUG((DEBUG_INFO, " PASID - 0x%x\n", ECapReg->Bits.PASID)); + DEBUG((DEBUG_INFO, " PRS - 0x%x\n", ECapReg->Bits.PRS)); + DEBUG((DEBUG_INFO, " ERS - 0x%x\n", ECapReg->Bits.ERS)); + DEBUG((DEBUG_INFO, " SRS - 0x%x\n", ECapReg->Bits.SRS)); + DEBUG((DEBUG_INFO, " NWFS - 0x%x\n", ECapReg->Bits.NWFS)); + DEBUG((DEBUG_INFO, " EAFS - 0x%x\n", ECapReg->Bits.EAFS)); + DEBUG((DEBUG_INFO, " PSS - 0x%x\n", ECapReg->Bits.PSS)); +} + +/** + Dump VTd registers. + + @param[in] VtdIndex The index of VTd engine. +**/ +VOID +DumpVtdRegs ( + IN UINTN VtdIndex + ) +{ + UINTN Index; + UINT64 Reg64; + VTD_FRCD_REG FrcdReg; + VTD_CAP_REG CapReg; + UINT32 Reg32; + VTD_SOURCE_ID SourceId; + + DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) Begin ####\n", VtdIndex)); + + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_VER_REG); + DEBUG((DEBUG_INFO, " VER_REG - 0x%08x\n", Reg32)); + + CapReg.Uint64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseA= ddress + R_CAP_REG); + DEBUG((DEBUG_INFO, " CAP_REG - 0x%016lx\n", CapReg.Uint64)); + + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_ECAP_REG); + DEBUG((DEBUG_INFO, " ECAP_REG - 0x%016lx\n", Reg64)); + + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_GSTS_REG); + DEBUG((DEBUG_INFO, " GSTS_REG - 0x%08x \n", Reg32)); + + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_RTADDR_REG); + DEBUG((DEBUG_INFO, " RTADDR_REG - 0x%016lx\n", Reg64)); + + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_CCMD_REG); + DEBUG((DEBUG_INFO, " CCMD_REG - 0x%016lx\n", Reg64)); + + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_FSTS_REG); + DEBUG((DEBUG_INFO, " FSTS_REG - 0x%08x\n", Reg32)); + + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_FECTL_REG); + DEBUG((DEBUG_INFO, " FECTL_REG - 0x%08x\n", Reg32)); + + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_FEDATA_REG); + DEBUG((DEBUG_INFO, " FEDATA_REG - 0x%08x\n", Reg32)); + + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_FEADDR_REG); + DEBUG((DEBUG_INFO, " FEADDR_REG - 0x%08x\n",Reg32)); + + Reg32 =3D MmioRead32 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += R_FEUADDR_REG); + DEBUG((DEBUG_INFO, " FEUADDR_REG - 0x%08x\n",Reg32)); + + for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { + FrcdReg.Uint64[0] =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUni= tBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG)); + FrcdReg.Uint64[1] =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUni= tBaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof= (UINT64))); + DEBUG((DEBUG_INFO, " FRCD_REG[%d] - 0x%016lx %016lx\n", Index, FrcdRe= g.Uint64[1], FrcdReg.Uint64[0])); + if (FrcdReg.Uint64[1] !=3D 0 || FrcdReg.Uint64[0] !=3D 0) { + DEBUG((DEBUG_INFO, " Fault Info - 0x%016lx\n", VTD_64BITS_ADDRESS= (FrcdReg.Bits.FILo, FrcdReg.Bits.FIHi))); + SourceId.Uint16 =3D (UINT16)FrcdReg.Bits.SID; + DEBUG((DEBUG_INFO, " Source - B%02x D%02x F%02x\n", SourceId.Bits= .Bus, SourceId.Bits.Device, SourceId.Bits.Function)); + DEBUG((DEBUG_INFO, " Type - %x (%a)\n", FrcdReg.Bits.T, FrcdReg.B= its.T ? "read" : "write")); + DEBUG((DEBUG_INFO, " Reason - %x (Refer to VTd Spec, Appendix A)\= n", FrcdReg.Bits.FR)); + } + } + + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IVA_REG); + DEBUG((DEBUG_INFO, " IVA_REG - 0x%016lx\n",Reg64)); + + Reg64 =3D MmioRead64 (mVtdUnitInformation[VtdIndex].VtdUnitBaseAddress += (mVtdUnitInformation[VtdIndex].ECapReg.Bits.IRO * 16) + R_IOTLB_REG); + DEBUG((DEBUG_INFO, " IOTLB_REG - 0x%016lx\n",Reg64)); + + DEBUG((DEBUG_INFO, "#### DumpVtdRegs(%d) End ####\n", VtdIndex)); +} + +/** + Dump VTd registers for all VTd engine. +**/ +VOID +DumpVtdRegsAll ( + VOID + ) +{ + UINTN Num; + + for (Num =3D 0; Num < mVtdUnitNumber; Num++) { + DumpVtdRegs (Num); + } +} + +/** + Dump VTd registers if there is error. +**/ +VOID +DumpVtdIfError ( + VOID + ) +{ + UINTN Num; + UINTN Index; + VTD_FRCD_REG FrcdReg; + VTD_CAP_REG CapReg; + UINT32 Reg32; + BOOLEAN HasError; + + for (Num =3D 0; Num < mVtdUnitNumber; Num++) { + HasError =3D FALSE; + Reg32 =3D MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_= FSTS_REG); + if (Reg32 !=3D 0) { + HasError =3D TRUE; + } + Reg32 =3D MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_= FECTL_REG); + if ((Reg32 & BIT30) !=3D 0) { + HasError =3D TRUE; + } + + CapReg.Uint64 =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnitBaseAddr= ess + R_CAP_REG); + for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { + FrcdReg.Uint64[0] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnitBa= seAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG)); + FrcdReg.Uint64[1] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnitBa= seAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UI= NT64))); + if (FrcdReg.Bits.F !=3D 0) { + HasError =3D TRUE; + } + } + + if (HasError) { + REPORT_STATUS_CODE (EFI_ERROR_CODE, PcdGet32 (PcdErrorCodeVTdError)); + DEBUG((DEBUG_INFO, "\n#### ERROR ####\n")); + DumpVtdRegs (Num); + DEBUG((DEBUG_INFO, "#### ERROR ####\n\n")); + // + // Clear + // + for (Index =3D 0; Index < (UINTN)CapReg.Bits.NFR + 1; Index++) { + FrcdReg.Uint64[1] =3D MmioRead64 (mVtdUnitInformation[Num].VtdUnit= BaseAddress + ((CapReg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(= UINT64))); + if (FrcdReg.Bits.F !=3D 0) { + // + // Software writes the value read from this field (F) to Clear i= t. + // + MmioWrite64 (mVtdUnitInformation[Num].VtdUnitBaseAddress + ((Cap= Reg.Bits.FRO * 16) + (Index * 16) + R_FRCD_REG + sizeof(UINT64)), FrcdReg.U= int64[1]); + } + } + MmioWrite32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_RE= G, MmioRead32 (mVtdUnitInformation[Num].VtdUnitBaseAddress + R_FSTS_REG)); + } + } +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarT= able.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable= .c new file mode 100644 index 0000000000..d920d136f1 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/DmarTable.c @@ -0,0 +1,578 @@ +/** @file + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "IntelVTdPmrPei.h" + +/** + Dump DMAR DeviceScopeEntry. + + @param[in] DmarDeviceScopeEntry DMAR DeviceScopeEntry +**/ +VOID +DumpDmarDeviceScopeEntry ( + IN EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry + ) +{ + UINTN PciPathNumber; + UINTN PciPathIndex; + EFI_ACPI_DMAR_PCI_PATH *PciPath; + + if (DmarDeviceScopeEntry =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *****************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * DMA-Remapping Device Scope Entry Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *****************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " DMAR Device Scope Entry address ...................... 0x%016lx\n= " : + " DMAR Device Scope Entry address ...................... 0x%08x\n", + DmarDeviceScopeEntry + )); + DEBUG ((DEBUG_INFO, + " Device Scope Entry Type ............................ 0x%02x\n", + DmarDeviceScopeEntry->Type + )); + switch (DmarDeviceScopeEntry->Type) { + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT: + DEBUG ((DEBUG_INFO, + " PCI Endpoint Device\n" + )); + break; + case EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_BRIDGE: + DEBUG ((DEBUG_INFO, + " PCI Sub-hierachy\n" + )); + break; + default: + break; + } + DEBUG ((DEBUG_INFO, + " Length ............................................. 0x%02x\n", + DmarDeviceScopeEntry->Length + )); + DEBUG ((DEBUG_INFO, + " Enumeration ID ..................................... 0x%02x\n", + DmarDeviceScopeEntry->EnumerationId + )); + DEBUG ((DEBUG_INFO, + " Starting Bus Number ................................ 0x%02x\n", + DmarDeviceScopeEntry->StartBusNumber + )); + + PciPathNumber =3D (DmarDeviceScopeEntry->Length - sizeof(EFI_ACPI_DMAR_D= EVICE_SCOPE_STRUCTURE_HEADER)) / sizeof(EFI_ACPI_DMAR_PCI_PATH); + PciPath =3D (EFI_ACPI_DMAR_PCI_PATH *)(DmarDeviceScopeEntry + 1); + for (PciPathIndex =3D 0; PciPathIndex < PciPathNumber; PciPathIndex++) { + DEBUG ((DEBUG_INFO, + " Device ............................................. 0x%02x\n= ", + PciPath[PciPathIndex].Device + )); + DEBUG ((DEBUG_INFO, + " Function ........................................... 0x%02x\n= ", + PciPath[PciPathIndex].Function + )); + } + + DEBUG ((DEBUG_INFO, + " *****************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR RMRR table. + + @param[in] Rmrr DMAR RMRR table +**/ +VOID +DumpDmarRmrr ( + IN EFI_ACPI_DMAR_RMRR_HEADER *Rmrr + ) +{ + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry; + INTN RmrrLen; + + if (Rmrr =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * Reserved Memory Region Reporting Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " RMRR address ........................................... 0x%016lx\n= " : + " RMRR address ........................................... 0x%08x\n", + Rmrr + )); + DEBUG ((DEBUG_INFO, + " Type ................................................. 0x%04x\n", + Rmrr->Header.Type + )); + DEBUG ((DEBUG_INFO, + " Length ............................................... 0x%04x\n", + Rmrr->Header.Length + )); + DEBUG ((DEBUG_INFO, + " Segment Number ....................................... 0x%04x\n", + Rmrr->SegmentNumber + )); + DEBUG ((DEBUG_INFO, + " Reserved Memory Region Base Address .................. 0x%016lx\n= ", + Rmrr->ReservedMemoryRegionBaseAddress + )); + DEBUG ((DEBUG_INFO, + " Reserved Memory Region Limit Address ................. 0x%016lx\n= ", + Rmrr->ReservedMemoryRegionLimitAddress + )); + + RmrrLen =3D Rmrr->Header.Length - sizeof(EFI_ACPI_DMAR_RMRR_HEADER); + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)= (Rmrr + 1); + while (RmrrLen > 0) { + DumpDmarDeviceScopeEntry (DmarDeviceScopeEntry); + RmrrLen -=3D DmarDeviceScopeEntry->Length; + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER = *)((UINTN)DmarDeviceScopeEntry + DmarDeviceScopeEntry->Length); + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR DRHD table. + + @param[in] Drhd DMAR DRHD table +**/ +VOID +DumpDmarDrhd ( + IN EFI_ACPI_DMAR_DRHD_HEADER *Drhd + ) +{ + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDeviceScopeEntry; + INTN DrhdLen; + + if (Drhd =3D=3D NULL) { + return; + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + " * DMA-Remapping Hardware Definition Structure = *\n" + )); + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + " DRHD address ........................................... 0x%016lx\n= " : + " DRHD address ........................................... 0x%08x\n", + Drhd + )); + DEBUG ((DEBUG_INFO, + " Type ................................................. 0x%04x\n", + Drhd->Header.Type + )); + DEBUG ((DEBUG_INFO, + " Length ............................................... 0x%04x\n", + Drhd->Header.Length + )); + DEBUG ((DEBUG_INFO, + " Flags ................................................ 0x%02x\n", + Drhd->Flags + )); + DEBUG ((DEBUG_INFO, + " INCLUDE_PCI_ALL .................................... 0x%02x\n", + Drhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL + )); + DEBUG ((DEBUG_INFO, + " Segment Number ....................................... 0x%04x\n", + Drhd->SegmentNumber + )); + DEBUG ((DEBUG_INFO, + " Register Base Address ................................ 0x%016lx\n= ", + Drhd->RegisterBaseAddress + )); + + DrhdLen =3D Drhd->Header.Length - sizeof(EFI_ACPI_DMAR_DRHD_HEADER); + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)= (Drhd + 1); + while (DrhdLen > 0) { + DumpDmarDeviceScopeEntry (DmarDeviceScopeEntry); + DrhdLen -=3D DmarDeviceScopeEntry->Length; + DmarDeviceScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER = *)((UINTN)DmarDeviceScopeEntry + DmarDeviceScopeEntry->Length); + } + + DEBUG ((DEBUG_INFO, + " *******************************************************************= ********\n\n" + )); + + return; +} + +/** + Dump DMAR ACPI table. + + @param[in] Dmar DMAR ACPI table +**/ +VOID +DumpAcpiDMAR ( + IN EFI_ACPI_DMAR_HEADER *Dmar + ) +{ + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + INTN DmarLen; + + if (Dmar =3D=3D NULL) { + return; + } + + // + // Dump Dmar table + // + DEBUG ((DEBUG_INFO, + "*********************************************************************= ********\n" + )); + DEBUG ((DEBUG_INFO, + "* DMAR Table = *\n" + )); + DEBUG ((DEBUG_INFO, + "*********************************************************************= ********\n" + )); + + DEBUG ((DEBUG_INFO, + (sizeof(UINTN) =3D=3D sizeof(UINT64)) ? + "DMAR address ............................................. 0x%016lx\n= " : + "DMAR address ............................................. 0x%08x\n", + Dmar + )); + + DEBUG ((DEBUG_INFO, + " Table Contents:\n" + )); + DEBUG ((DEBUG_INFO, + " Host Address Width ................................... 0x%02x\n", + Dmar->HostAddressWidth + )); + DEBUG ((DEBUG_INFO, + " Flags ................................................ 0x%02x\n", + Dmar->Flags + )); + DEBUG ((DEBUG_INFO, + " INTR_REMAP ......................................... 0x%02x\n", + Dmar->Flags & EFI_ACPI_DMAR_FLAGS_INTR_REMAP + )); + DEBUG ((DEBUG_INFO, + " X2APIC_OPT_OUT_SET ................................. 0x%02x\n", + Dmar->Flags & EFI_ACPI_DMAR_FLAGS_X2APIC_OPT_OUT + )); + DEBUG ((DEBUG_INFO, + " DMA_CTRL_PLATFORM_OPT_IN_FLAG ...................... 0x%02x\n", + Dmar->Flags & EFI_ACPI_DMAR_FLAGS_DMA_CTRL_PLATFORM_OPT_IN_FLAG + )); + + DmarLen =3D Dmar->Header.Length - sizeof(EFI_ACPI_DMAR_HEADER); + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)(Dmar + 1); + while (DmarLen > 0) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + DumpDmarDrhd ((EFI_ACPI_DMAR_DRHD_HEADER *)DmarHeader); + break; + case EFI_ACPI_DMAR_TYPE_RMRR: + DumpDmarRmrr ((EFI_ACPI_DMAR_RMRR_HEADER *)DmarHeader); + break; + default: + break; + } + DmarLen -=3D DmarHeader->Length; + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } + + DEBUG ((DEBUG_INFO, + "*********************************************************************= ********\n\n" + )); + + return; +} + +/** + Get VTd engine number. + + @param[in] AcpiDmarTable DMAR ACPI table + + @return the VTd engine number. +**/ +UINTN +GetVtdEngineNumber ( + IN EFI_ACPI_DMAR_HEADER *AcpiDmarTable + ) +{ + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + UINTN VtdIndex; + + VtdIndex =3D 0; + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTable = + 1)); + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Header.= Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + VtdIndex++; + break; + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } + return VtdIndex ; +} + +/** + Process DMAR DHRD table. + + @param[in] VTdInfo The VTd engine context information. + @param[in] VtdIndex The index of VTd engine. + @param[in] DmarDrhd The DRHD table. +**/ +VOID +ProcessDhrd ( + IN VTD_INFO *VTdInfo, + IN UINTN VtdIndex, + IN EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd + ) +{ + DEBUG ((DEBUG_INFO," VTD (%d) BaseAddress - 0x%016lx\n", VtdIndex, Dma= rDrhd->RegisterBaseAddress)); + VTdInfo->VTdEngineAddress[VtdIndex] =3D DmarDrhd->RegisterBaseAddress; +} + +/** + Parse DMAR DRHD table. + + @param[in] AcpiDmarTable DMAR ACPI table + + @return EFI_SUCCESS The DMAR DRHD table is parsed. +**/ +EFI_STATUS +ParseDmarAcpiTableDrhd ( + IN EFI_ACPI_DMAR_HEADER *AcpiDmarTable + ) +{ + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + UINTN VtdUnitNumber; + UINTN VtdIndex; + VTD_INFO *VTdInfo; + + VtdUnitNumber =3D GetVtdEngineNumber (AcpiDmarTable); + if (VtdUnitNumber =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + VTdInfo =3D BuildGuidHob (&mVTdInfoGuid, sizeof(VTD_INFO) + (VtdUnitNumb= er - 1) * sizeof(UINT64)); + ASSERT(VTdInfo !=3D NULL); + if (VTdInfo =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Initialize the engine mask to all. + // + VTdInfo->AcpiDmarTable =3D AcpiDmarTable; + VTdInfo->EngineMask =3D LShiftU64 (1, VtdUnitNumber) - 1; + VTdInfo->HostAddressWidth =3D AcpiDmarTable->HostAddressWidth; + VTdInfo->VTdEngineCount =3D VtdUnitNumber; + + VtdIndex =3D 0; + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTable = + 1)); + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Header.= Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + ASSERT (VtdIndex < VtdUnitNumber); + ProcessDhrd (VTdInfo, VtdIndex, (EFI_ACPI_DMAR_DRHD_HEADER *)DmarHea= der); + VtdIndex++; + + break; + + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } + ASSERT (VtdIndex =3D=3D VtdUnitNumber); + + return EFI_SUCCESS; +} + +/** + Return the VTd engine index according to the Segment and DevScopeEntry. + + @param AcpiDmarTable DMAR ACPI table + @param Segment The segment of the VTd engine + @param DevScopeEntry The DevScopeEntry of the VTd engine + + @return The VTd engine index according to the Segment and DevScopeEntry. + @retval -1 The VTd engine is not found. +**/ +UINTN +GetVTdEngineFromDevScopeEntry ( + IN EFI_ACPI_DMAR_HEADER *AcpiDmarTable, + IN UINT16 Segment, + IN EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DevScopeEntry + ) +{ + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + UINTN VtdIndex; + EFI_ACPI_DMAR_DRHD_HEADER *DmarDrhd; + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *ThisDevScopeEntry; + + VtdIndex =3D 0; + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTable = + 1)); + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Header.= Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_DRHD: + DmarDrhd =3D (EFI_ACPI_DMAR_DRHD_HEADER *)DmarHeader; + if (DmarDrhd->SegmentNumber !=3D Segment) { + // Mismatch + break; + } + if ((DmarDrhd->Header.Length =3D=3D sizeof(EFI_ACPI_DMAR_DRHD_HEADER= )) || + ((DmarDrhd->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) != =3D 0)) { + // No DevScopeEntry + // Do not handle PCI_ALL + break; + } + ThisDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *= )((UINTN)(DmarDrhd + 1)); + while ((UINTN)ThisDevScopeEntry < (UINTN)DmarDrhd + DmarDrhd->Header= .Length) { + if ((ThisDevScopeEntry->Length =3D=3D DevScopeEntry->Length) && + (CompareMem (ThisDevScopeEntry, DevScopeEntry, DevScopeEntry->= Length) =3D=3D 0)) { + return VtdIndex; + } + ThisDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER= *)((UINTN)ThisDevScopeEntry + ThisDevScopeEntry->Length); + } + break; + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } + return (UINTN)-1; +} + +/** + Process DMAR RMRR table. + + @param[in] VTdInfo The VTd engine context information. + @param[in] DmarRmrr The RMRR table. +**/ +VOID +ProcessRmrr ( + IN VTD_INFO *VTdInfo, + IN EFI_ACPI_DMAR_RMRR_HEADER *DmarRmrr + ) +{ + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDevScopeEntry; + UINTN VTdIndex; + UINT64 RmrrMask; + UINTN LowBottom; + UINTN LowTop; + UINTN HighBottom; + UINT64 HighTop; + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; + + AcpiDmarTable =3D VTdInfo->AcpiDmarTable; + + DEBUG ((DEBUG_INFO," RMRR (Base 0x%016lx, Limit 0x%016lx)\n", DmarRmrr-= >ReservedMemoryRegionBaseAddress, DmarRmrr->ReservedMemoryRegionLimitAddres= s)); + + if ((DmarRmrr->ReservedMemoryRegionBaseAddress =3D=3D 0) || + (DmarRmrr->ReservedMemoryRegionLimitAddress =3D=3D 0)) { + return ; + } + + DmarDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)((U= INTN)(DmarRmrr + 1)); + while ((UINTN)DmarDevScopeEntry < (UINTN)DmarRmrr + DmarRmrr->Header.Len= gth) { + ASSERT (DmarDevScopeEntry->Type =3D=3D EFI_ACPI_DEVICE_SCOPE_ENTRY_TYP= E_PCI_ENDPOINT); + + VTdIndex =3D GetVTdEngineFromDevScopeEntry (AcpiDmarTable, DmarRmrr->S= egmentNumber, DmarDevScopeEntry); + if (VTdIndex !=3D (UINTN)-1) { + RmrrMask =3D LShiftU64 (1, VTdIndex); + + LowBottom =3D 0; + LowTop =3D (UINTN)DmarRmrr->ReservedMemoryRegionBaseAddress; + HighBottom =3D (UINTN)DmarRmrr->ReservedMemoryRegionLimitAddress + 1; + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); + + SetDmaProtectedRange ( + VTdInfo, + RmrrMask, + 0, + (UINT32)(LowTop - LowBottom), + HighBottom, + HighTop - HighBottom + ); + + // + // Remove the engine from the engine mask. + // The assumption is that any other PEI driver does not access + // the device covered by this engine. + // + VTdInfo->EngineMask =3D VTdInfo->EngineMask & (~RmrrMask); + } + + DmarDevScopeEntry =3D (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *)(= (UINTN)DmarDevScopeEntry + DmarDevScopeEntry->Length); + } +} + +/** + Parse DMAR DRHD table. + + @param[in] VTdInfo The VTd engine context information. +**/ +VOID +ParseDmarAcpiTableRmrr ( + IN VTD_INFO *VTdInfo + ) +{ + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; + EFI_ACPI_DMAR_STRUCTURE_HEADER *DmarHeader; + + AcpiDmarTable =3D VTdInfo->AcpiDmarTable; + + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)(AcpiDmarTable = + 1)); + while ((UINTN)DmarHeader < (UINTN)AcpiDmarTable + AcpiDmarTable->Header.= Length) { + switch (DmarHeader->Type) { + case EFI_ACPI_DMAR_TYPE_RMRR: + ProcessRmrr (VTdInfo, (EFI_ACPI_DMAR_RMRR_HEADER *)DmarHeader); + break; + default: + break; + } + DmarHeader =3D (EFI_ACPI_DMAR_STRUCTURE_HEADER *)((UINTN)DmarHeader + = DmarHeader->Length); + } +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmr.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVT= dPmr.c new file mode 100644 index 0000000000..37283f0fab --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmr.c @@ -0,0 +1,420 @@ +/** @file + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +#include "IntelVTdPmrPei.h" + +/** + Get protected low memory alignment. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected low memory alignment. +**/ +UINT32 +GetPlmrAlignment ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Data32; + + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, 0xFFFFFFFF); + Data32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG); + Data32 =3D ~Data32 + 1; + + return Data32; +} + +/** + Get protected high memory alignment. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + + @return protected high memory alignment. +**/ +UINT64 +GetPhmrAlignment ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress + ) +{ + UINT64 Data64; + + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, 0xFFFFFFFFFFFFFF= FF); + Data64 =3D MmioRead64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG); + Data64 =3D ~Data64 + 1; + Data64 =3D Data64 & (LShiftU64 (1, HostAddressWidth) - 1); + + return Data64; +} + +/** + Get protected low memory alignment. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + + @return protected low memory alignment. +**/ +UINT32 +GetLowMemoryAlignment ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ) +{ + UINTN Index; + UINT32 Alignment; + UINT32 FinalAlignment; + + FinalAlignment =3D 0; + for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { + if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { + continue; + } + Alignment =3D GetPlmrAlignment (VTdInfo->HostAddressWidth, (UINTN)VTdI= nfo->VTdEngineAddress[Index]); + if (FinalAlignment < Alignment) { + FinalAlignment =3D Alignment; + } + } + return FinalAlignment; +} + +/** + Get protected high memory alignment. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + + @return protected high memory alignment. +**/ +UINT64 +GetHighMemoryAlignment ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ) +{ + UINTN Index; + UINT64 Alignment; + UINT64 FinalAlignment; + + FinalAlignment =3D 0; + for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { + if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { + continue; + } + Alignment =3D GetPhmrAlignment (VTdInfo->HostAddressWidth, (UINTN)VTdI= nfo->VTdEngineAddress[Index]); + if (FinalAlignment < Alignment) { + FinalAlignment =3D Alignment; + } + } + return FinalAlignment; +} + +/** + Enable PMR in the VTd engine. + + @param VtdUnitBaseAddress The base address of the VTd engine. + + @retval EFI_SUCCESS The PMR is enabled. + @retval EFI_UNSUPPORTED The PMR is not supported. +**/ +EFI_STATUS +EnablePmr ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + + DEBUG ((DEBUG_INFO, "EnablePmr - %x\n", VtdUnitBaseAddress)); + + CapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + if (Reg32 =3D=3D 0xFFFFFFFF) { + DEBUG ((DEBUG_ERROR, "R_PMEN_ENABLE_REG - 0x%x\n", Reg32)); + ASSERT(FALSE); + } + + if ((Reg32 & BIT0) =3D=3D 0) { + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG, BIT31); + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + } while((Reg32 & BIT0) =3D=3D 0); + } + + DEBUG ((DEBUG_INFO, "EnablePmr - Done\n")); + + return EFI_SUCCESS; +} + +/** + Disable PMR in the VTd engine. + + @param VtdUnitBaseAddress The base address of the VTd engine. + + @retval EFI_SUCCESS The PMR is disabled. + @retval EFI_UNSUPPORTED The PMR is not supported. +**/ +EFI_STATUS +DisablePmr ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + + CapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + if (Reg32 =3D=3D 0xFFFFFFFF) { + DEBUG ((DEBUG_ERROR, "R_PMEN_ENABLE_REG - 0x%x\n", Reg32)); + ASSERT(FALSE); + } + + if ((Reg32 & BIT0) !=3D 0) { + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG, 0x0); + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + } while((Reg32 & BIT0) !=3D 0); + } + + return EFI_SUCCESS; +} + +/** + Set PMR region in the VTd engine. + + @param HostAddressWidth The host address width. + @param VtdUnitBaseAddress The base address of the VTd engine. + @param LowMemoryBase The protected low memory region base. + @param LowMemoryLength The protected low memory region length. + @param HighMemoryBase The protected high memory region base. + @param HighMemoryLength The protected high memory region length. + + @retval EFI_SUCCESS The PMR is set to protected region. + @retval EFI_UNSUPPORTED The PMR is not supported. +**/ +EFI_STATUS +SetPmrRegion ( + IN UINT8 HostAddressWidth, + IN UINTN VtdUnitBaseAddress, + IN UINT32 LowMemoryBase, + IN UINT32 LowMemoryLength, + IN UINT64 HighMemoryBase, + IN UINT64 HighMemoryLength + ) +{ + VTD_CAP_REG CapReg; + UINT32 PlmrAlignment; + UINT64 PhmrAlignment; + + DEBUG ((DEBUG_INFO, "VtdUnitBaseAddress - 0x%x\n", VtdUnitBaseAddress)); + + CapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "PLMR/PHMR unsupported\n")); + return EFI_UNSUPPORTED; + } + + PlmrAlignment =3D GetPlmrAlignment (HostAddressWidth, VtdUnitBaseAddress= ); + DEBUG ((DEBUG_INFO, "PlmrAlignment - 0x%x\n", PlmrAlignment)); + PhmrAlignment =3D GetPhmrAlignment (HostAddressWidth, VtdUnitBaseAddress= ); + DEBUG ((DEBUG_INFO, "PhmrAlignment - 0x%lx\n", PhmrAlignment)); + + if ((LowMemoryBase !=3D ALIGN_VALUE(LowMemoryBase, PlmrAlignment)) || + (LowMemoryLength !=3D ALIGN_VALUE(LowMemoryLength, PlmrAlignment)) = || + (HighMemoryBase !=3D ALIGN_VALUE(HighMemoryBase, PhmrAlignment)) || + (HighMemoryLength !=3D ALIGN_VALUE(HighMemoryLength, PhmrAlignment))= ) { + DEBUG ((DEBUG_ERROR, "PLMR/PHMR alignment issue\n")); + return EFI_UNSUPPORTED; + } + + if (LowMemoryBase =3D=3D 0 && LowMemoryLength =3D=3D 0) { + LowMemoryBase =3D 0xFFFFFFFF; + } + if (HighMemoryBase =3D=3D 0 && HighMemoryLength =3D=3D 0) { + HighMemoryBase =3D 0xFFFFFFFFFFFFFFFF; + } + + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_BASE_REG, LowMemoryBase); + MmioWrite32 (VtdUnitBaseAddress + R_PMEN_LOW_LIMITE_REG, LowMemoryBase = + LowMemoryLength - 1); + DEBUG ((DEBUG_INFO, "PLMR set done\n")); + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_BASE_REG, HighMemoryBase= ); + MmioWrite64 (VtdUnitBaseAddress + R_PMEN_HIGH_LIMITE_REG, HighMemoryBase= + HighMemoryLength - 1); + DEBUG ((DEBUG_INFO, "PHMR set done\n")); + + return EFI_SUCCESS; +} + +/** + Set DMA protected region. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + @param LowMemoryBase The protected low memory region base. + @param LowMemoryLength The protected low memory region length. + @param HighMemoryBase The protected high memory region base. + @param HighMemoryLength The protected high memory region length. + + @retval EFI_SUCCESS The DMA protection is set. + @retval EFI_UNSUPPORTED The DMA protection is not set. +**/ +EFI_STATUS +SetDmaProtectedRange ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask, + IN UINT32 LowMemoryBase, + IN UINT32 LowMemoryLength, + IN UINT64 HighMemoryBase, + IN UINT64 HighMemoryLength + ) +{ + UINTN Index; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SetDmaProtectedRange(0x%lx) - [0x%x, 0x%x] [0x%lx, = 0x%lx]\n", EngineMask, LowMemoryBase, LowMemoryLength, HighMemoryBase, High= MemoryLength)); + + for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { + if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { + continue; + } + DisablePmr ((UINTN)VTdInfo->VTdEngineAddress[Index]); + Status =3D SetPmrRegion ( + VTdInfo->HostAddressWidth, + (UINTN)VTdInfo->VTdEngineAddress[Index], + LowMemoryBase, + LowMemoryLength, + HighMemoryBase, + HighMemoryLength + ); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D EnablePmr ((UINTN)VTdInfo->VTdEngineAddress[Index]); + if (EFI_ERROR(Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} + +/** + Diable DMA protection. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + + @retval EFI_SUCCESS DMA protection is disabled. +**/ +EFI_STATUS +DisableDmaProtection ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ) +{ + UINTN Index; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "DisableDmaProtection - 0x%lx\n", EngineMask)); + + for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { + DEBUG ((DEBUG_INFO, "Disabling...%d\n", Index)); + + if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { + continue; + } + Status =3D DisablePmr ((UINTN)VTdInfo->VTdEngineAddress[Index]); + if (EFI_ERROR(Status)) { + return Status; + } + } + + return EFI_SUCCESS; +} + +/** + Return if the PMR is enabled. + + @param VtdUnitBaseAddress The base address of the VTd engine. + + @retval TRUE PMR is enabled. + @retval FALSE PMR is disabled or unsupported. +**/ +BOOLEAN +IsPmrEnabled ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + + CapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_CAP_REG); + if (CapReg.Bits.PLMR =3D=3D 0 || CapReg.Bits.PHMR =3D=3D 0) { + return FALSE; + } + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_PMEN_ENABLE_REG); + if ((Reg32 & BIT0) =3D=3D 0) { + return FALSE; + } + + return TRUE; +} + +/** + Return the mask of the VTd engine which is enabled. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + + @return the mask of the VTd engine which is enabled. +**/ +UINT64 +GetDmaProtectionEnabledEngineMask ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ) +{ + UINTN Index; + BOOLEAN Result; + UINT64 EnabledEngineMask; + + DEBUG ((DEBUG_INFO, "GetDmaProtectionEnabledEngineMask - 0x%lx\n", Engin= eMask)); + + EnabledEngineMask =3D 0; + for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { + if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { + continue; + } + Result =3D IsPmrEnabled ((UINTN)VTdInfo->VTdEngineAddress[Index]); + if (Result) { + EnabledEngineMask |=3D LShiftU64(1, Index); + } + } + + DEBUG ((DEBUG_INFO, "EnabledEngineMask - 0x%lx\n", EnabledEngineMask)); + return EnabledEngineMask; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmrPei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Inte= lVTdPmrPei.c new file mode 100644 index 0000000000..ca099ed71d --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.c @@ -0,0 +1,810 @@ +/** @file + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "IntelVTdPmrPei.h" + +EFI_GUID mVTdInfoGuid =3D { + 0x222f5e30, 0x5cd, 0x49c6, { 0x8a, 0xc, 0x36, 0xd6, 0x58, 0x41, 0xe0, 0x= 82 } +}; + +EFI_GUID mDmaBufferInfoGuid =3D { + 0x7b624ec7, 0xfb67, 0x4f9c, { 0xb6, 0xb0, 0x4d, 0xfa, 0x9c, 0x88, 0x20, = 0x39 } +}; + +typedef struct { + UINTN DmaBufferBase; + UINTN DmaBufferSize; + UINTN DmaBufferCurrentTop; + UINTN DmaBufferCurrentBottom; +} DMA_BUFFER_INFO; + +#define MAP_INFO_SIGNATURE SIGNATURE_32 ('D', 'M', 'A', 'P') +typedef struct { + UINT32 Signature; + EDKII_IOMMU_OPERATION Operation; + UINTN NumberOfBytes; + EFI_PHYSICAL_ADDRESS HostAddress; + EFI_PHYSICAL_ADDRESS DeviceAddress; +} MAP_INFO; + +/** + + PEI Memory Layout: + + +------------------+ <=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D PHMR.Limit (+ alignment) (1 << (HostAddressWidth + 1)) + | Mem Resource | + | | + + +------------------+ <------- EfiMemoryTop + | PEI allocated | + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ <=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PHMR.Base + ^ | Commom Buf | + | | -------------- | + DMA Buffer | * DMA FREE * | + | | -------------- | + V | Read/Write Buf | + =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D+ <=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D PLMR.Lim= it (+ alignment) + | PEI allocated | + | -------------- | <------- EfiFreeMemoryTop + | * PEI FREE * | + | -------------- | <------- EfiFreeMemoryBottom + | hob | + | -------------- | + | Stack | + +------------------+ <------- EfiMemoryBottom / Stack Bottom + + +------------------+ + | Mem Alloc Hob | + +------------------+ + + | | + | Mem Resource | + +------------------+ <=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D PLMR.Base (0) +**/ + +/** + Set IOMMU attribute for a system memory. + + If the IOMMU PPI exists, the system memory cannot be used + for DMA by default. + + When a device requests a DMA access for a system memory, + the device driver need use SetAttribute() to update the IOMMU + attribute to request DMA access (read and/or write). + + @param[in] This The PPI instance pointer. + @param[in] Mapping The mapping value returned from Map(). + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by DeviceAddress and Length. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by Map(). + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by Mapping. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. + @retval EFI_NOT_AVAILABLE_YET DMA protection has been enabled, but DMA = buffer are + not available to be allocated yet. + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuSetAttribute ( + IN EDKII_IOMMU_PPI *This, + IN VOID *Mapping, + IN UINT64 IoMmuAccess + ) +{ + VOID *Hob; + DMA_BUFFER_INFO *DmaBufferInfo; + + Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); + DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); + + if (DmaBufferInfo->DmaBufferCurrentTop =3D=3D 0) { + return EFI_NOT_AVAILABLE_YET; + } + + return EFI_SUCCESS; +} + +/** + Provides the controller-specific addresses required to access system mem= ory from a + DMA bus master. + + @param This The PPI instance pointer. + @param Operation Indicates if the bus master is going to re= ad or write to system memory. + @param HostAddress The system memory address to map to the PC= I controller. + @param NumberOfBytes On input the number of bytes to map. On ou= tput the number of bytes + that were mapped. + @param DeviceAddress The resulting map address for the bus mast= er PCI controller to use to + access the hosts HostAddress. + @param Mapping A resulting value to pass to Unmap(). + + @retval EFI_SUCCESS The range was mapped for the returned Numb= erOfBytes. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a comm= on buffer. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to = a lack of resources. + @retval EFI_DEVICE_ERROR The system hardware could not map the requ= ested address. + @retval EFI_NOT_AVAILABLE_YET DMA protection has been enabled, but DMA b= uffer are + not available to be allocated yet. + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuMap ( + IN EDKII_IOMMU_PPI *This, + IN EDKII_IOMMU_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + MAP_INFO *MapInfo; + UINTN Length; + VOID *Hob; + DMA_BUFFER_INFO *DmaBufferInfo; + + Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); + DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuMap - HostAddress - 0x%x, NumberOfBytes = - %x\n", HostAddress, *NumberOfBytes)); + DEBUG ((DEBUG_VERBOSE, " DmaBufferCurrentTop - %x\n", DmaBufferInfo->Dm= aBufferCurrentTop)); + DEBUG ((DEBUG_VERBOSE, " DmaBufferCurrentBottom - %x\n", DmaBufferInfo-= >DmaBufferCurrentBottom)); + + if (DmaBufferInfo->DmaBufferCurrentTop =3D=3D 0) { + return EFI_NOT_AVAILABLE_YET; + } + + if (Operation =3D=3D EdkiiIoMmuOperationBusMasterCommonBuffer || + Operation =3D=3D EdkiiIoMmuOperationBusMasterCommonBuffer64) { + *DeviceAddress =3D (UINTN)HostAddress; + *Mapping =3D NULL; + return EFI_SUCCESS; + } + + Length =3D *NumberOfBytes + sizeof(MAP_INFO); + if (Length > DmaBufferInfo->DmaBufferCurrentTop - DmaBufferInfo->DmaBuff= erCurrentBottom) { + DEBUG ((DEBUG_ERROR, "PeiIoMmuMap - OUT_OF_RESOURCE\n")); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + + *DeviceAddress =3D DmaBufferInfo->DmaBufferCurrentBottom; + DmaBufferInfo->DmaBufferCurrentBottom +=3D Length; + + MapInfo =3D (VOID *)(UINTN)(*DeviceAddress + *NumberOfBytes); + MapInfo->Signature =3D MAP_INFO_SIGNATURE; + MapInfo->Operation =3D Operation; + MapInfo->NumberOfBytes =3D *NumberOfBytes; + MapInfo->HostAddress =3D (UINTN)HostAddress; + MapInfo->DeviceAddress =3D *DeviceAddress; + *Mapping =3D MapInfo; + DEBUG ((DEBUG_VERBOSE, " Op(%x):DeviceAddress - %x, Mapping - %x\n", Op= eration, (UINTN)*DeviceAddress, MapInfo)); + + // + // If this is a read operation from the Bus Master's point of view, + // then copy the contents of the real buffer into the mapped buffer + // so the Bus Master can read the contents of the real buffer. + // + if (Operation =3D=3D EdkiiIoMmuOperationBusMasterRead || + Operation =3D=3D EdkiiIoMmuOperationBusMasterRead64) { + CopyMem ( + (VOID *) (UINTN) MapInfo->DeviceAddress, + (VOID *) (UINTN) MapInfo->HostAddress, + MapInfo->NumberOfBytes + ); + } + + return EFI_SUCCESS; +} + +/** + Completes the Map() operation and releases any corresponding resources. + + @param This The PPI instance pointer. + @param Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned b= y Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target s= ystem memory. + @retval EFI_NOT_AVAILABLE_YET DMA protection has been enabled, but DMA b= uffer are + not available to be allocated yet. + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuUnmap ( + IN EDKII_IOMMU_PPI *This, + IN VOID *Mapping + ) +{ + MAP_INFO *MapInfo; + UINTN Length; + VOID *Hob; + DMA_BUFFER_INFO *DmaBufferInfo; + + Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); + DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuUnmap - Mapping - %x\n", Mapping)); + DEBUG ((DEBUG_VERBOSE, " DmaBufferCurrentTop - %x\n", DmaBufferInfo->Dm= aBufferCurrentTop)); + DEBUG ((DEBUG_VERBOSE, " DmaBufferCurrentBottom - %x\n", DmaBufferInfo-= >DmaBufferCurrentBottom)); + + if (DmaBufferInfo->DmaBufferCurrentTop =3D=3D 0) { + return EFI_NOT_AVAILABLE_YET; + } + + if (Mapping =3D=3D NULL) { + return EFI_SUCCESS; + } + + MapInfo =3D Mapping; + ASSERT (MapInfo->Signature =3D=3D MAP_INFO_SIGNATURE); + DEBUG ((DEBUG_VERBOSE, " Op(%x):DeviceAddress - %x, NumberOfBytes - %x\= n", MapInfo->Operation, (UINTN)MapInfo->DeviceAddress, MapInfo->NumberOfByt= es)); + + // + // If this is a write operation from the Bus Master's point of view, + // then copy the contents of the mapped buffer into the real buffer + // so the processor can read the contents of the real buffer. + // + if (MapInfo->Operation =3D=3D EdkiiIoMmuOperationBusMasterWrite || + MapInfo->Operation =3D=3D EdkiiIoMmuOperationBusMasterWrite64) { + CopyMem ( + (VOID *) (UINTN) MapInfo->HostAddress, + (VOID *) (UINTN) MapInfo->DeviceAddress, + MapInfo->NumberOfBytes + ); + } + + Length =3D MapInfo->NumberOfBytes + sizeof(MAP_INFO); + if (DmaBufferInfo->DmaBufferCurrentBottom =3D=3D MapInfo->DeviceAddress = + Length) { + DmaBufferInfo->DmaBufferCurrentBottom -=3D Length; + } + + return EFI_SUCCESS; +} + +/** + Allocates pages that are suitable for an OperationBusMasterCommonBuffer = or + OperationBusMasterCommonBuffer64 mapping. + + @param This The PPI instance pointer. + @param MemoryType The type of memory to allocate, EfiBootSer= vicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory = address of the + allocated range. + @param Attributes The requested bit mask of attributes for t= he allocated range. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal = attribute bits are + MEMORY_WRITE_COMBINE, MEMORY_CACHED and DU= AL_ADDRESS_CYCLE. + @retval EFI_INVALID_PARAMETER One or more parameters are invalid. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. + @retval EFI_NOT_AVAILABLE_YET DMA protection has been enabled, but DMA b= uffer are + not available to be allocated yet. + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuAllocateBuffer ( + IN EDKII_IOMMU_PPI *This, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + IN OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + UINTN Length; + VOID *Hob; + DMA_BUFFER_INFO *DmaBufferInfo; + + Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); + DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuAllocateBuffer - page - %x\n", Pages)); + DEBUG ((DEBUG_VERBOSE, " DmaBufferCurrentTop - %x\n", DmaBufferInfo->Dm= aBufferCurrentTop)); + DEBUG ((DEBUG_VERBOSE, " DmaBufferCurrentBottom - %x\n", DmaBufferInfo-= >DmaBufferCurrentBottom)); + + if (DmaBufferInfo->DmaBufferCurrentTop =3D=3D 0) { + return EFI_NOT_AVAILABLE_YET; + } + + Length =3D EFI_PAGES_TO_SIZE(Pages); + if (Length > DmaBufferInfo->DmaBufferCurrentTop - DmaBufferInfo->DmaBuff= erCurrentBottom) { + DEBUG ((DEBUG_ERROR, "PeiIoMmuAllocateBuffer - OUT_OF_RESOURCE\n")); + ASSERT (FALSE); + return EFI_OUT_OF_RESOURCES; + } + *HostAddress =3D (VOID *)(UINTN)(DmaBufferInfo->DmaBufferCurrentTop - Le= ngth); + DmaBufferInfo->DmaBufferCurrentTop -=3D Length; + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuAllocateBuffer - allocate - %x\n", *Host= Address)); + return EFI_SUCCESS; +} + +/** + Frees memory that was allocated with AllocateBuffer(). + + @param This The PPI instance pointer. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allo= cated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress = and Pages + was not allocated with AllocateBuffer(). + @retval EFI_NOT_AVAILABLE_YET DMA protection has been enabled, but DMA b= uffer are + not available to be allocated yet. + +**/ +EFI_STATUS +EFIAPI +PeiIoMmuFreeBuffer ( + IN EDKII_IOMMU_PPI *This, + IN UINTN Pages, + IN VOID *HostAddress + ) +{ + UINTN Length; + VOID *Hob; + DMA_BUFFER_INFO *DmaBufferInfo; + + Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); + DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); + + DEBUG ((DEBUG_VERBOSE, "PeiIoMmuFreeBuffer - page - %x, HostAddr - %x\n"= , Pages, HostAddress)); + DEBUG ((DEBUG_VERBOSE, " DmaBufferCurrentTop - %x\n", DmaBufferInfo->Dm= aBufferCurrentTop)); + DEBUG ((DEBUG_VERBOSE, " DmaBufferCurrentBottom - %x\n", DmaBufferInfo-= >DmaBufferCurrentBottom)); + + if (DmaBufferInfo->DmaBufferCurrentTop =3D=3D 0) { + return EFI_NOT_AVAILABLE_YET; + } + + Length =3D EFI_PAGES_TO_SIZE(Pages); + if ((UINTN)HostAddress =3D=3D DmaBufferInfo->DmaBufferCurrentTop) { + DmaBufferInfo->DmaBufferCurrentTop +=3D Length; + } + + return EFI_SUCCESS; +} + +EDKII_IOMMU_PPI mIoMmuPpi =3D { + EDKII_IOMMU_PPI_REVISION, + PeiIoMmuSetAttribute, + PeiIoMmuMap, + PeiIoMmuUnmap, + PeiIoMmuAllocateBuffer, + PeiIoMmuFreeBuffer, +}; + +CONST EFI_PEI_PPI_DESCRIPTOR mIoMmuPpiList =3D { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEdkiiIoMmuPpiGuid, + (VOID *) &mIoMmuPpi +}; + +/** + Initialize DMA protection. + + @param VTdInfo The VTd engine context information. + + @retval EFI_SUCCESS the DMA protection is initialized. + @retval EFI_OUT_OF_RESOURCES no enough resource to initialize DMA prote= ction. +**/ +EFI_STATUS +InitDmaProtection ( + IN VTD_INFO *VTdInfo + ) +{ + EFI_STATUS Status; + UINT32 LowMemoryAlignment; + UINT64 HighMemoryAlignment; + UINTN MemoryAlignment; + UINTN LowBottom; + UINTN LowTop; + UINTN HighBottom; + UINT64 HighTop; + DMA_BUFFER_INFO *DmaBufferInfo; + VOID *Hob; + EFI_PEI_PPI_DESCRIPTOR *OldDescriptor; + EDKII_IOMMU_PPI *OldIoMmuPpi; + + Hob =3D GetFirstGuidHob (&mDmaBufferInfoGuid); + DmaBufferInfo =3D GET_GUID_HOB_DATA(Hob); + + DEBUG ((DEBUG_INFO, " DmaBufferSize : 0x%x\n", DmaBufferInfo->DmaBufferS= ize)); + + LowMemoryAlignment =3D GetLowMemoryAlignment (VTdInfo, VTdInfo->EngineMa= sk); + HighMemoryAlignment =3D GetHighMemoryAlignment (VTdInfo, VTdInfo->Engine= Mask); + if (LowMemoryAlignment < HighMemoryAlignment) { + MemoryAlignment =3D (UINTN)HighMemoryAlignment; + } else { + MemoryAlignment =3D LowMemoryAlignment; + } + ASSERT (DmaBufferInfo->DmaBufferSize =3D=3D ALIGN_VALUE(DmaBufferInfo->D= maBufferSize, MemoryAlignment)); + DmaBufferInfo->DmaBufferBase =3D (UINTN)AllocateAlignedPages (EFI_SIZE_T= O_PAGES(DmaBufferInfo->DmaBufferSize), MemoryAlignment); + ASSERT (DmaBufferInfo->DmaBufferBase !=3D 0); + if (DmaBufferInfo->DmaBufferBase =3D=3D 0) { + DEBUG ((DEBUG_INFO, " InitDmaProtection : OutOfResource\n")); + return EFI_OUT_OF_RESOURCES; + } + + DEBUG ((DEBUG_INFO, " DmaBufferBase : 0x%x\n", DmaBufferInfo->DmaBufferB= ase)); + + DmaBufferInfo->DmaBufferCurrentTop =3D DmaBufferInfo->DmaBufferBase + Dm= aBufferInfo->DmaBufferSize; + DmaBufferInfo->DmaBufferCurrentBottom =3D DmaBufferInfo->DmaBufferBase; + + // + // (Re)Install PPI. + // + Status =3D PeiServicesLocatePpi ( + &gEdkiiIoMmuPpiGuid, + 0, + &OldDescriptor, + (VOID **) &OldIoMmuPpi + ); + if (!EFI_ERROR (Status)) { + Status =3D PeiServicesReInstallPpi (OldDescriptor, &mIoMmuPpiList); + } else { + Status =3D PeiServicesInstallPpi (&mIoMmuPpiList); + } + ASSERT_EFI_ERROR (Status); + + LowBottom =3D 0; + LowTop =3D DmaBufferInfo->DmaBufferBase; + HighBottom =3D DmaBufferInfo->DmaBufferBase + DmaBufferInfo->DmaBufferSi= ze; + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); + + Status =3D SetDmaProtectedRange ( + VTdInfo, + VTdInfo->EngineMask, + (UINT32)LowBottom, + (UINT32)(LowTop - LowBottom), + HighBottom, + HighTop - HighBottom + ); + + if (EFI_ERROR(Status)) { + FreePages ((VOID *)DmaBufferInfo->DmaBufferBase, EFI_SIZE_TO_PAGES(Dma= BufferInfo->DmaBufferSize)); + } + + return Status; +} + +/** + Initializes the Intel VTd Info. + + @retval EFI_SUCCESS Usb bot driver is successfully initialize= d. + @retval EFI_OUT_OF_RESOURCES Can't initialize the driver. + +**/ +EFI_STATUS +InitVTdInfo ( + VOID + ) +{ + EFI_STATUS Status; + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; + VOID *Hob; + + Status =3D PeiServicesLocatePpi ( + &gEdkiiVTdInfoPpiGuid, + 0, + NULL, + (VOID **)&AcpiDmarTable + ); + ASSERT_EFI_ERROR(Status); + + DumpAcpiDMAR (AcpiDmarTable); + + // + // Clear old VTdInfo Hob. + // + Hob =3D GetFirstGuidHob (&mVTdInfoGuid); + if (Hob !=3D NULL) { + ZeroMem (&((EFI_HOB_GUID_TYPE *)Hob)->Name, sizeof(EFI_GUID)); + } + + // + // Get DMAR information to local VTdInfo + // + Status =3D ParseDmarAcpiTableDrhd (AcpiDmarTable); + if (EFI_ERROR(Status)) { + return Status; + } + + // + // NOTE: Do not parse RMRR here, because RMRR may cause PMR programming. + // + + return EFI_SUCCESS; +} + +/** + Initializes the Intel VTd PMR for all memory. + + @retval EFI_SUCCESS Usb bot driver is successfully initialize= d. + @retval EFI_OUT_OF_RESOURCES Can't initialize the driver. + +**/ +EFI_STATUS +InitVTdPmrForAll ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Hob; + VTD_INFO *VTdInfo; + UINTN LowBottom; + UINTN LowTop; + UINTN HighBottom; + UINT64 HighTop; + + Hob =3D GetFirstGuidHob (&mVTdInfoGuid); + VTdInfo =3D GET_GUID_HOB_DATA(Hob); + + LowBottom =3D 0; + LowTop =3D 0; + HighBottom =3D 0; + HighTop =3D LShiftU64 (1, VTdInfo->HostAddressWidth + 1); + + Status =3D SetDmaProtectedRange ( + VTdInfo, + VTdInfo->EngineMask, + (UINT32)LowBottom, + (UINT32)(LowTop - LowBottom), + HighBottom, + HighTop - HighBottom + ); + + return Status; +} + +/** + Initializes the Intel VTd PMR for DMA buffer. + + @retval EFI_SUCCESS Usb bot driver is successfully initialize= d. + @retval EFI_OUT_OF_RESOURCES Can't initialize the driver. + +**/ +EFI_STATUS +InitVTdPmrForDma ( + VOID + ) +{ + EFI_STATUS Status; + VOID *Hob; + VTD_INFO *VTdInfo; + + Hob =3D GetFirstGuidHob (&mVTdInfoGuid); + VTdInfo =3D GET_GUID_HOB_DATA(Hob); + + // + // If there is RMRR memory, parse it here. + // + ParseDmarAcpiTableRmrr (VTdInfo); + + // + // Allocate a range in PEI memory as DMA buffer + // Mark others to be DMA protected. + // + Status =3D InitDmaProtection (VTdInfo); + + return Status; +} + +/** + This function handles S3 resume task at the end of PEI + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_STATUS Always return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +S3EndOfPeiNotify( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + VOID *Hob; + VTD_INFO *VTdInfo; + UINT64 EngineMask; + + DEBUG((DEBUG_INFO, "VTdPmr S3EndOfPeiNotify\n")); + + if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT1) =3D=3D 0) { + Hob =3D GetFirstGuidHob (&mVTdInfoGuid); + if (Hob =3D=3D NULL) { + return EFI_SUCCESS; + } + VTdInfo =3D GET_GUID_HOB_DATA(Hob); + + EngineMask =3D LShiftU64 (1, VTdInfo->VTdEngineCount) - 1; + DisableDmaProtection (VTdInfo, EngineMask); + } + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mS3EndOfPeiNotifyDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEfiEndOfPeiSignalPpiGuid, + S3EndOfPeiNotify +}; + +/** + This function handles VTd engine setup + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_STATUS Always return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +VTdInfoNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + VOID *MemoryDiscovered; + UINT64 EnabledEngineMask; + VOID *Hob; + VTD_INFO *VTdInfo; + BOOLEAN MemoryInitialized; + + DEBUG ((DEBUG_INFO, "VTdInfoNotify\n")); + + // + // Check if memory is initialized. + // + MemoryInitialized =3D FALSE; + Status =3D PeiServicesLocatePpi ( + &gEfiPeiMemoryDiscoveredPpiGuid, + 0, + NULL, + &MemoryDiscovered + ); + if (!EFI_ERROR(Status)) { + MemoryInitialized =3D TRUE; + } + + DEBUG ((DEBUG_INFO, "MemoryInitialized - %x\n", MemoryInitialized)); + + if (!MemoryInitialized) { + // + // If the memory is not initialized, + // Protect all system memory + // + InitVTdInfo (); + InitVTdPmrForAll (); + + // + // Install PPI. + // + Status =3D PeiServicesInstallPpi (&mIoMmuPpiList); + ASSERT_EFI_ERROR(Status); + } else { + // + // If the memory is initialized, + // Allocate DMA buffer and protect rest system memory + // + + // + // NOTE: We need reinit VTdInfo because previous information might be = overriden. + // + InitVTdInfo (); + + Hob =3D GetFirstGuidHob (&mVTdInfoGuid); + VTdInfo =3D GET_GUID_HOB_DATA(Hob); + + // + // NOTE: We need check if PMR is enabled or not. + // + EnabledEngineMask =3D GetDmaProtectionEnabledEngineMask (VTdInfo, VTdI= nfo->EngineMask); + if (EnabledEngineMask !=3D 0) { + EnableVTdTranslationProtection (VTdInfo, EnabledEngineMask); + DisableDmaProtection (VTdInfo, EnabledEngineMask); + } + InitVTdPmrForDma (); + if (EnabledEngineMask !=3D 0) { + DisableVTdTranslationProtection (VTdInfo, EnabledEngineMask); + } + + } + + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mVTdInfoNotifyDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEdkiiVTdInfoPpiGuid, + VTdInfoNotify +}; + +/** + Initializes the Intel VTd PMR PEIM. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Usb bot driver is successfully initialize= d. + @retval EFI_OUT_OF_RESOURCES Can't initialize the driver. + +**/ +EFI_STATUS +EFIAPI +IntelVTdPmrInitialize ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + DMA_BUFFER_INFO *DmaBufferInfo; + + DEBUG ((DEBUG_INFO, "IntelVTdPmrInitialize\n")); + + if ((PcdGet8(PcdVTdPolicyPropertyMask) & BIT0) =3D=3D 0) { + return EFI_UNSUPPORTED; + } + + DmaBufferInfo =3D BuildGuidHob (&mDmaBufferInfoGuid, sizeof(DMA_BUFFER_I= NFO)); + ASSERT(DmaBufferInfo !=3D NULL); + if (DmaBufferInfo =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + ZeroMem (DmaBufferInfo, sizeof(DMA_BUFFER_INFO)); + + PeiServicesGetBootMode (&BootMode); + + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + DmaBufferInfo->DmaBufferSize =3D PcdGet32 (PcdVTdPeiDmaBufferSizeS3); + } else { + DmaBufferInfo->DmaBufferSize =3D PcdGet32 (PcdVTdPeiDmaBufferSize); + } + + Status =3D PeiServicesNotifyPpi (&mVTdInfoNotifyDesc); + ASSERT_EFI_ERROR (Status); + + // + // Register EndOfPei Notify for S3 + // + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + Status =3D PeiServicesNotifyPpi (&mS3EndOfPeiNotifyDesc); + ASSERT_EFI_ERROR (Status); + } + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdRe= g.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c new file mode 100644 index 0000000000..4774a2ae5b --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/VtdReg.c @@ -0,0 +1,287 @@ +/** @file + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "IntelVTdPmrPei.h" + +/** + Flush VTD page table and context table memory. + + This action is to make sure the IOMMU engine can get final data in memor= y. + + @param[in] Base The base address of memory to be flushed. + @param[in] Size The size of memory in bytes to be flushed. +**/ +VOID +FlushPageTableMemory ( + IN UINTN Base, + IN UINTN Size + ) +{ + WriteBackDataCacheRange ((VOID *)Base, Size); +} + +/** + Flush VTd engine write buffer. + + @param VtdUnitBaseAddress The base address of the VTd engine. +**/ +VOID +FlushWriteBuffer ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Reg32; + VTD_CAP_REG CapReg; + + CapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_CAP_REG); + + if (CapReg.Bits.RWBF !=3D 0) { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, Reg32 | B_GMCD_REG_WBF); + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_WBF) !=3D 0); + } +} + +/** + Invalidate VTd context cache. + + @param VtdUnitBaseAddress The base address of the VTd engine. +**/ +EFI_STATUS +InvalidateContextCache ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT64 Reg64; + + Reg64 =3D MmioRead64 (VtdUnitBaseAddress + R_CCMD_REG); + if ((Reg64 & B_CCMD_REG_ICC) !=3D 0) { + DEBUG ((DEBUG_ERROR,"ERROR: InvalidateContextCache: B_CCMD_REG_ICC is = set for VTD(%x)\n",VtdUnitBaseAddress)); + return EFI_DEVICE_ERROR; + } + + Reg64 &=3D ((~B_CCMD_REG_ICC) & (~B_CCMD_REG_CIRG_MASK)); + Reg64 |=3D (B_CCMD_REG_ICC | V_CCMD_REG_CIRG_GLOBAL); + MmioWrite64 (VtdUnitBaseAddress + R_CCMD_REG, Reg64); + + do { + Reg64 =3D MmioRead64 (VtdUnitBaseAddress + R_CCMD_REG); + } while ((Reg64 & B_CCMD_REG_ICC) !=3D 0); + + return EFI_SUCCESS; +} + +/** + Invalidate VTd IOTLB. + + @param VtdUnitBaseAddress The base address of the VTd engine. +**/ +EFI_STATUS +InvalidateIOTLB ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT64 Reg64; + VTD_ECAP_REG ECapReg; + + ECapReg.Uint64 =3D MmioRead64 (VtdUnitBaseAddress + R_ECAP_REG); + + Reg64 =3D MmioRead64 (VtdUnitBaseAddress + (ECapReg.Bits.IRO * 16) + R_I= OTLB_REG); + if ((Reg64 & B_IOTLB_REG_IVT) !=3D 0) { + DEBUG ((DEBUG_ERROR,"ERROR: InvalidateIOTLB: B_IOTLB_REG_IVT is set fo= r VTD(%x)\n", VtdUnitBaseAddress)); + return EFI_DEVICE_ERROR; + } + + Reg64 &=3D ((~B_IOTLB_REG_IVT) & (~B_IOTLB_REG_IIRG_MASK)); + Reg64 |=3D (B_IOTLB_REG_IVT | V_IOTLB_REG_IIRG_GLOBAL); + MmioWrite64 (VtdUnitBaseAddress + (ECapReg.Bits.IRO * 16) + R_IOTLB_REG,= Reg64); + + do { + Reg64 =3D MmioRead64 (VtdUnitBaseAddress + (ECapReg.Bits.IRO * 16) + R= _IOTLB_REG); + } while ((Reg64 & B_IOTLB_REG_IVT) !=3D 0); + + return EFI_SUCCESS; +} + +/** + Enable DMAR translation. + + @param VtdUnitBaseAddress The base address of the VTd engine. + @param RootEntryTable The address of the VTd RootEntryTable. + + @retval EFI_SUCCESS DMAR translation is enabled. + @retval EFI_DEVICE_ERROR DMAR translation is not enabled. +**/ +EFI_STATUS +EnableDmar ( + IN UINTN VtdUnitBaseAddress, + IN UINTN RootEntryTable + ) +{ + UINT32 Reg32; + + DEBUG((DEBUG_INFO, ">>>>>>EnableDmar() for engine [%x] \n", VtdUnitBaseA= ddress)); + + DEBUG((DEBUG_INFO, "RootEntryTable 0x%x \n", RootEntryTable)); + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, (UINT64)(UINTN)RootEntry= Table); + + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP); + + DEBUG((DEBUG_INFO, "EnableDmar: waiting for RTPS bit to be set... \n")); + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + + // + // Init DMAr Fault Event and Data registers + // + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_FEDATA_REG); + + // + // Write Buffer Flush before invalidation + // + FlushWriteBuffer (VtdUnitBaseAddress); + + // + // Invalidate the context cache + // + InvalidateContextCache (VtdUnitBaseAddress); + + // + // Invalidate the IOTLB cache + // + InvalidateIOTLB (VtdUnitBaseAddress); + + // + // Enable VTd + // + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_TE); + DEBUG((DEBUG_INFO, "EnableDmar: Waiting B_GSTS_REG_TE ...\n")); + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while ((Reg32 & B_GSTS_REG_TE) =3D=3D 0); + + DEBUG ((DEBUG_INFO,"VTD () enabled!<<<<<<\n")); + + return EFI_SUCCESS; +} + +/** + Disable DMAR translation. + + @param VtdUnitBaseAddress The base address of the VTd engine. + + @retval EFI_SUCCESS DMAR translation is disabled. + @retval EFI_DEVICE_ERROR DMAR translation is not disabled. +**/ +EFI_STATUS +DisableDmar ( + IN UINTN VtdUnitBaseAddress + ) +{ + UINT32 Reg32; + + DEBUG((DEBUG_INFO, ">>>>>>DisableDmar() for engine [%x] \n", VtdUnitBase= Address)); + + // + // Write Buffer Flush before invalidation + // + FlushWriteBuffer (VtdUnitBaseAddress); + + // + // Disable VTd + // + MmioWrite32 (VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP); + do { + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); + + Reg32 =3D MmioRead32 (VtdUnitBaseAddress + R_GSTS_REG); + DEBUG((DEBUG_INFO, "DisableDmar: GSTS_REG - 0x%08x\n", Reg32)); + + MmioWrite64 (VtdUnitBaseAddress + R_RTADDR_REG, 0); + + DEBUG ((DEBUG_INFO,"VTD () Disabled!<<<<<<\n")); + + return EFI_SUCCESS; +} + +/** + Enable VTd translation table protection. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. +**/ +VOID +EnableVTdTranslationProtection ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ) +{ + UINTN Index; + VOID *RootEntryTable; + + DEBUG ((DEBUG_INFO, "EnableVTdTranslationProtection - 0x%lx\n", EngineMa= sk)); + + RootEntryTable =3D AllocatePages (1); + ASSERT (RootEntryTable !=3D NULL); + if (RootEntryTable =3D=3D NULL) { + DEBUG ((DEBUG_INFO, " EnableVTdTranslationProtection : OutOfResource\n= ")); + return ; + } + + ZeroMem (RootEntryTable, EFI_PAGES_TO_SIZE(1)); + FlushPageTableMemory ((UINTN)RootEntryTable, EFI_PAGES_TO_SIZE(1)); + + for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { + if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { + continue; + } + EnableDmar ((UINTN)VTdInfo->VTdEngineAddress[Index], (UINTN)RootEntryT= able); + } + + return ; +} + +/** + Disable VTd translation table protection. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. +**/ +VOID +DisableVTdTranslationProtection ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ) +{ + UINTN Index; + + DEBUG ((DEBUG_INFO, "DisableVTdTranslationProtection - 0x%lx\n", EngineM= ask)); + + for (Index =3D 0; Index < VTdInfo->VTdEngineCount; Index++) { + if ((EngineMask & LShiftU64(1, Index)) =3D=3D 0) { + continue; + } + DisableDmar ((UINTN)VTdInfo->VTdEngineAddress[Index]); + } + + return ; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSampl= ePei/PlatformVTdInfoSamplePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd= /PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.c new file mode 100644 index 0000000000..3698c3d3f1 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePei.c @@ -0,0 +1,361 @@ +/** @file + Platform VTd Info Sample PEI driver. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include + +#include +#include +#include +#include +#include + +#define R_SA_MCHBAR (0x48) +#define R_SA_GGC (0x50) +#define N_SKL_SA_GGC_GGMS_OFFSET (0x6) +#define B_SKL_SA_GGC_GGMS_MASK (0xc0) +#define N_SKL_SA_GGC_GMS_OFFSET (0x8) +#define B_SKL_SA_GGC_GMS_MASK (0xff00) +#define V_SKL_SA_GGC_GGMS_8MB 3 +#define R_SA_TOLUD (0xbc) + +#define R_SA_MCHBAR_VTD1_OFFSET 0x5400 ///< HW UNIT for IGD +#define R_SA_MCHBAR_VTD2_OFFSET 0x5410 ///< HW UNIT for all other - PEG,= USB, SATA etc + +EFI_GUID gEdkiiSiliconInitializedPpiGuid =3D {0x82a72dc8, 0x61ec, 0x403e, = {0xb1, 0x5a, 0x8d, 0x7a, 0x3a, 0x71, 0x84, 0x98}}; + +typedef struct { + EFI_ACPI_DMAR_HEADER DmarHeader; + // + // VTd engine 1 - integrated graphic + // + EFI_ACPI_DMAR_DRHD_HEADER Drhd1; + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER Drhd11; + EFI_ACPI_DMAR_PCI_PATH Drhd111; + // + // VTd engine 2 - all rest + // + EFI_ACPI_DMAR_DRHD_HEADER Drhd2; + // + // RMRR 1 - integrated graphic + // + EFI_ACPI_DMAR_RMRR_HEADER Rmrr1; + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER Rmrr11; + EFI_ACPI_DMAR_PCI_PATH Rmrr111; +} MY_VTD_INFO_PPI; + +MY_VTD_INFO_PPI mPlatformVTdSample =3D { + { // DmarHeader + { // Header + EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE, + sizeof(MY_VTD_INFO_PPI), + EFI_ACPI_DMAR_REVISION, + }, + 0x26, // HostAddressWidth + }, + + { // Drhd1 + { // Header + EFI_ACPI_DMAR_TYPE_DRHD, + sizeof(EFI_ACPI_DMAR_DRHD_HEADER) + + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + sizeof(EFI_ACPI_DMAR_PCI_PATH) + }, + 0, // Flags + 0, // Reserved + 0, // SegmentNumber + 0xFED90000 // RegisterBaseAddress -- TO BE PATCHED + }, + { // Drhd11 + EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT, + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + sizeof(EFI_ACPI_DMAR_PCI_PATH), + 0, // Reserved2 + 0, // EnumerationId + 0 // StartBusNumber + }, + { // Drhd111 + 2, // Device + 0 // Function + }, + + { // Drhd2 + { // Header + EFI_ACPI_DMAR_TYPE_DRHD, + sizeof(EFI_ACPI_DMAR_DRHD_HEADER) + }, + EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags + 0, // Reserved + 0, // SegmentNumber + 0xFED91000 // RegisterBaseAddress -- TO BE PATCHED + }, + + { // Rmrr1 + { // Header + EFI_ACPI_DMAR_TYPE_RMRR, + sizeof(EFI_ACPI_DMAR_RMRR_HEADER) + + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + sizeof(EFI_ACPI_DMAR_PCI_PATH) + }, + {0}, // Reserved + 0, // SegmentNumber + 0x0, // ReservedMemoryRegionBaseAddress -- TO BE PATCHED + 0x0 // ReservedMemoryRegionLimitAddress -- TO BE PATCHED + }, + { // Rmrr11 + EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT, + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + sizeof(EFI_ACPI_DMAR_PCI_PATH), + 0, // Reserved2 + 0, // EnumerationId + 0 // StartBusNumber + }, + { // Rmrr111 + 2, // Device + 0 // Function + }, +}; + +EFI_PEI_PPI_DESCRIPTOR mPlatformVTdInfoSampleDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEdkiiVTdInfoPpiGuid, + &mPlatformVTdSample +}; + +typedef struct { + EFI_ACPI_DMAR_HEADER DmarHeader; + // + // VTd engine 2 - all rest + // + EFI_ACPI_DMAR_DRHD_HEADER Drhd2; +} MY_VTD_INFO_NO_IGD_PPI; + +MY_VTD_INFO_NO_IGD_PPI mPlatformVTdNoIgdSample =3D { + { // DmarHeader + { // Header + EFI_ACPI_4_0_DMA_REMAPPING_TABLE_SIGNATURE, + sizeof(MY_VTD_INFO_NO_IGD_PPI), + EFI_ACPI_DMAR_REVISION, + }, + 0x26, // HostAddressWidth + }, + + { // Drhd2 + { // Header + EFI_ACPI_DMAR_TYPE_DRHD, + sizeof(EFI_ACPI_DMAR_DRHD_HEADER) + }, + EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL, // Flags + 0, // Reserved + 0, // SegmentNumber + 0xFED91000 // RegisterBaseAddress -- TO BE PATCHED + }, +}; + +EFI_PEI_PPI_DESCRIPTOR mPlatformVTdNoIgdInfoSampleDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEdkiiVTdInfoPpiGuid, + &mPlatformVTdNoIgdSample +}; + +/** + Initialize VTd register. +**/ +VOID +InitDmar ( + VOID + ) +{ + UINT32 MchBar; + + DEBUG ((DEBUG_INFO, "InitDmar\n")); + + MchBar =3D PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0; + PciWrite32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR), 0xFED10000 | BIT0); + DEBUG ((DEBUG_INFO, "MchBar - %x\n", MchBar)); + + MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)mPlatformVTdSampl= e.Drhd2.RegisterBaseAddress | 1); + DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_VTD= 2_OFFSET)))); +} + +/** + Patch Graphic UMA address in RMRR and base address. +**/ +EFI_PEI_PPI_DESCRIPTOR * +PatchDmar ( + VOID + ) +{ + UINT32 MchBar; + UINT16 IgdMode; + UINT16 GttMode; + UINT32 IgdMemSize; + UINT32 GttMemSize; + MY_VTD_INFO_PPI *PlatformVTdSample; + EFI_PEI_PPI_DESCRIPTOR *PlatformVTdInfoSampleDesc; + MY_VTD_INFO_NO_IGD_PPI *PlatformVTdNoIgdSample; + EFI_PEI_PPI_DESCRIPTOR *PlatformVTdNoIgdInfoSampleDesc; + + DEBUG ((DEBUG_INFO, "PatchDmar\n")); + + if (PciRead16 (PCI_LIB_ADDRESS(0, 2, 0, 0)) !=3D 0xFFFF) { + PlatformVTdSample =3D AllocateCopyPool (sizeof(MY_VTD_INFO_PPI), &mPla= tformVTdSample); + ASSERT(PlatformVTdSample !=3D NULL); + PlatformVTdInfoSampleDesc =3D AllocateCopyPool (sizeof(EFI_PEI_PPI_DES= CRIPTOR), &mPlatformVTdInfoSampleDesc); + ASSERT(PlatformVTdInfoSampleDesc !=3D NULL); + PlatformVTdInfoSampleDesc->Ppi =3D PlatformVTdSample; + + /// + /// Calculate IGD memsize + /// + IgdMode =3D ((PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_S= A_GGC_GMS_MASK) >> N_SKL_SA_GGC_GMS_OFFSET) & 0xFF; + if (IgdMode < 0xF0) { + IgdMemSize =3D IgdMode * 32 * (1024) * (1024); + } else { + IgdMemSize =3D 4 * (IgdMode - 0xF0 + 1) * (1024) * (1024); + } + + /// + /// Calculate GTT mem size + /// + GttMemSize =3D 0; + GttMode =3D (PciRead16 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_GGC)) & B_SKL_SA= _GGC_GGMS_MASK) >> N_SKL_SA_GGC_GGMS_OFFSET; + if (GttMode <=3D V_SKL_SA_GGC_GGMS_8MB) { + GttMemSize =3D (1 << GttMode) * (1024) * (1024); + } + + PlatformVTdSample->Rmrr1.ReservedMemoryRegionBaseAddress =3D (PciRead= 32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_TOLUD)) & ~(0x01)) - IgdMemSize - GttMemS= ize; + PlatformVTdSample->Rmrr1.ReservedMemoryRegionLimitAddress =3D Platform= VTdSample->Rmrr1.ReservedMemoryRegionBaseAddress + IgdMemSize + GttMemSize = - 1; + + /// + /// Update DRHD structures of DmarTable + /// + MchBar =3D PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0; + + if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET) &~1) !=3D 0) { + PlatformVTdSample->Drhd1.RegisterBaseAddress =3D (MmioRead32 (MchBar= + R_SA_MCHBAR_VTD1_OFFSET) &~1); + } else { + MmioWrite32 (MchBar + R_SA_MCHBAR_VTD1_OFFSET, (UINT32)PlatformVTdSa= mple->Drhd1.RegisterBaseAddress | 1); + } + DEBUG ((DEBUG_INFO, "VTd1 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_V= TD1_OFFSET)))); + + if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1) !=3D 0) { + PlatformVTdSample->Drhd2.RegisterBaseAddress =3D (MmioRead32 (MchBar= + R_SA_MCHBAR_VTD2_OFFSET) &~1); + } else { + MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)PlatformVTdSa= mple->Drhd2.RegisterBaseAddress | 1); + } + DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_V= TD2_OFFSET)))); + + return PlatformVTdInfoSampleDesc; + } else { + PlatformVTdNoIgdSample =3D AllocateCopyPool (sizeof(MY_VTD_INFO_NO_IGD= _PPI), &mPlatformVTdNoIgdSample); + ASSERT(PlatformVTdNoIgdSample !=3D NULL); + PlatformVTdNoIgdInfoSampleDesc =3D AllocateCopyPool (sizeof(EFI_PEI_PP= I_DESCRIPTOR), &mPlatformVTdNoIgdInfoSampleDesc); + ASSERT(PlatformVTdNoIgdInfoSampleDesc !=3D NULL); + PlatformVTdNoIgdInfoSampleDesc->Ppi =3D PlatformVTdNoIgdSample; + + /// + /// Update DRHD structures of DmarTable + /// + MchBar =3D PciRead32 (PCI_LIB_ADDRESS(0, 0, 0, R_SA_MCHBAR)) & ~BIT0; + + if ((MmioRead32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET) &~1) !=3D 0) { + PlatformVTdNoIgdSample->Drhd2.RegisterBaseAddress =3D (MmioRead32 (M= chBar + R_SA_MCHBAR_VTD2_OFFSET) &~1); + } else { + MmioWrite32 (MchBar + R_SA_MCHBAR_VTD2_OFFSET, (UINT32)PlatformVTdNo= IgdSample->Drhd2.RegisterBaseAddress | 1); + } + DEBUG ((DEBUG_INFO, "VTd2 - %x\n", (MmioRead32 (MchBar + R_SA_MCHBAR_V= TD2_OFFSET)))); + + return PlatformVTdNoIgdInfoSampleDesc; + } +} + +/** + The callback function for SiliconInitializedPpi. + It reinstalls VTD_INFO_PPI. + + @param[in] PeiServices General purpose services available to ever= y PEIM. + @param[in] NotifyDescriptor Notify that this module published. + @param[in] Ppi PPI that was installed. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +SiliconInitializedPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PpiDesc; + + PpiDesc =3D PatchDmar (); + + Status =3D PeiServicesReInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc, Pp= iDesc); + ASSERT_EFI_ERROR (Status); + return EFI_SUCCESS; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mSiliconInitializedNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEdkiiSiliconInitializedPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT) SiliconInitializedPpiNotifyCallback +}; + +/** + Platform VTd Info sample driver. + + @param[in] FileHandle Handle of the file being invoked. + @param[in] PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS if it completed successfully. +**/ +EFI_STATUS +EFIAPI +PlatformVTdInfoSampleInitialize ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + BOOLEAN SiliconInitialized; + VOID *SiliconInitializedPpi; + EFI_PEI_PPI_DESCRIPTOR *PpiDesc; + + SiliconInitialized =3D FALSE; + // + // Check if silicon is initialized. + // + Status =3D PeiServicesLocatePpi ( + &gEdkiiSiliconInitializedPpiGuid, + 0, + NULL, + &SiliconInitializedPpi + ); + if (!EFI_ERROR(Status)) { + SiliconInitialized =3D TRUE; + } + DEBUG ((DEBUG_INFO, "SiliconInitialized - %x\n", SiliconInitialized)); + if (!SiliconInitialized) { + Status =3D PeiServicesNotifyPpi (&mSiliconInitializedNotifyList); + InitDmar (); + + Status =3D PeiServicesInstallPpi (&mPlatformVTdNoIgdInfoSampleDesc); + ASSERT_EFI_ERROR (Status); + } else { + PpiDesc =3D PatchDmar (); + + Status =3D PeiServicesInstallPpi (PpiDesc); + ASSERT_EFI_ERROR (Status); + } + + return Status; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe= /PlatformVTdSampleDxe.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Platfor= mVTdSampleDxe/PlatformVTdSampleDxe.c new file mode 100644 index 0000000000..fb77e6aa3f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/Platfo= rmVTdSampleDxe.c @@ -0,0 +1,407 @@ +/** @file + Platform VTd Sample driver. + + Note: This module should only be used for dev/debug purposes. + It MUST never be used for production builds. + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +typedef struct { + ACPI_EXTENDED_HID_DEVICE_PATH I2cController; + UINT8 HidStr[8]; + UINT8 UidStr[1]; + UINT8 CidStr[8]; +} PLATFORM_I2C_CONTROLLER_DEVICE_PATH; + +typedef struct { + ACPI_EXTENDED_HID_DEVICE_PATH I2cDevice; + UINT8 HidStr[13]; + UINT8 UidStr[1]; + UINT8 CidStr[13]; +} PLATFORM_I2C_DEVICE_DEVICE_PATH; + +typedef struct { + PLATFORM_I2C_CONTROLLER_DEVICE_PATH I2cController; + PLATFORM_I2C_DEVICE_DEVICE_PATH I2cDevice; + EFI_DEVICE_PATH_PROTOCOL End; +} PLATFORM_I2C_DEVICE_PATH; + +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH PciDevice; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} PLATFORM_PCI_DEVICE_PATH; + +typedef struct { + ACPI_HID_DEVICE_PATH PciRootBridge; + PCI_DEVICE_PATH PciBridge; + PCI_DEVICE_PATH PciDevice; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} PLATFORM_PCI_BRIDGE_DEVICE_PATH; + +typedef struct { + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + UINT16 Segment; + VTD_SOURCE_ID SourceId; +} PLATFORM_ACPI_DEVICE_MAPPING; + +#define PLATFORM_PCI_ROOT_BRIDGE \ + { \ + { \ + ACPI_DEVICE_PATH, \ + ACPI_DP, \ + { \ + (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \ + (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \ + }, \ + }, \ + EISA_PNP_ID (0x0A03), \ + 0 \ + } + +#define PLATFORM_END_ENTIRE \ + { \ + END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PAT= H_LENGTH, 0 } \ + } + +#define PLATFORM_PCI(Device, Function) \ + { \ + { \ + HARDWARE_DEVICE_PATH, \ + HW_PCI_DP, \ + { \ + (UINT8) (sizeof (PCI_DEVICE_PATH)), \ + (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8) \ + } \ + }, \ + (Function), \ + (Device) \ + } + +#define PLATFORM_I2C(Hid, Uid, Cid, HidStr, UidStr, CidStr) \ + { \ + { \ + { \ + ACPI_DEVICE_PATH, \ + ACPI_EXTENDED_DP, \ + {sizeof(ACPI_EXTENDED_HID_DEVICE_PATH) + sizeof(HidStr) + sizeof(U= idStr) + sizeof(CidStr), 0} \ + }, \ + Hid, \ + Uid, \ + Cid \ + }, \ + HidStr, \ + UidStr, \ + CidStr \ + } + +PLATFORM_I2C_DEVICE_PATH mPlatformI2CDevicePath =3D { + PLATFORM_I2C(0, 2, 0, "INT33C3", "", "INT33C3"), + PLATFORM_I2C(0, 1, 0, "I2C01\\TPANEL", "", "I2C01\\TPANEL"), + PLATFORM_END_ENTIRE +}; + +PLATFORM_ACPI_DEVICE_MAPPING mAcpiDeviceMapping[] =3D { + { + (EFI_DEVICE_PATH_PROTOCOL *)&mPlatformI2CDevicePath, + 0x0, // Segment + {{0x01, 0x15, 0x00}} // Function, Device, Bus + } +}; + +PLATFORM_PCI_BRIDGE_DEVICE_PATH mPlatformPciBridgeDevicePath =3D { + PLATFORM_PCI_ROOT_BRIDGE, + PLATFORM_PCI(0x1C, 1), + PLATFORM_PCI(0, 0), + PLATFORM_END_ENTIRE +}; + +#pragma pack(1) + +typedef struct { + EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO ExceptionDeviceInfo; + EDKII_PLATFORM_VTD_DEVICE_SCOPE DeviceScope; + EFI_ACPI_DMAR_PCI_PATH PciBridge; + EFI_ACPI_DMAR_PCI_PATH PciDevice; +} PLATFORM_EXCEPTION_DEVICE_SCOPE_STRUCT; + +typedef struct { + EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO ExceptionDeviceInfo; + EDKII_PLATFORM_VTD_PCI_DEVICE_ID PciDeviceId; +} PLATFORM_EXCEPTION_PCI_DEVICE_ID_STRUCT; + +#pragma pack() + +PLATFORM_EXCEPTION_DEVICE_SCOPE_STRUCT mExceptionDeviceScopeList[] =3D { + { + { + EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_DEVICE_SCOPE, + sizeof(PLATFORM_EXCEPTION_DEVICE_SCOPE_STRUCT) + }, // ExceptionDeviceInfo + { + 0, // SegmentNumb= er + { + EFI_ACPI_DEVICE_SCOPE_ENTRY_TYPE_PCI_ENDPOINT, // Type + sizeof(EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + + 2 * sizeof(EFI_ACPI_DMAR_PCI_PATH), // Length + 0, // Reserved2 + 0, // Enumeration= Id + 0, // StartBusNum= ber + }, + }, // DeviceScope + { 0x1C, 1 }, // PciBridge + { 0x0, 0 }, // PciDevice + }, +}; + +PLATFORM_EXCEPTION_PCI_DEVICE_ID_STRUCT mExceptionPciDeviceIdList[] =3D { + { + { + EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_PCI_DEVICE_ID, + sizeof(PLATFORM_EXCEPTION_PCI_DEVICE_ID_STRUCT) + }, // ExceptionDeviceInfo + { + 0x8086, // VendorId + 0x9D2F, // DeviceId + 0x21, // RevisionId + 0x8086, // SubsystemVe= ndorId + 0x7270, // SubsystemDe= viceId + }, + }, +}; + +/** + Compares 2 device path. + + @param[in] DevicePath1 A device path with EndDevicePath node. + @param[in] DevicePath2 A device path with EndDevicePath node. + + @retval TRUE 2 device path are identical. + @retval FALSE 2 device path are not identical. +**/ +BOOLEAN +CompareDevicePath ( + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath1, + IN CONST EFI_DEVICE_PATH_PROTOCOL *DevicePath2 + ) +{ + UINTN Size1; + UINTN Size2; + + Size1 =3D GetDevicePathSize (DevicePath1); + Size2 =3D GetDevicePathSize (DevicePath2); + if (Size1 !=3D Size2) { + return FALSE; + } + if (CompareMem (DevicePath1, DevicePath2, Size1) !=3D 0) { + return FALSE; + } + return TRUE; +} + +/** + Get the VTD SourceId from the device handler. + This function is required for non PCI device handler. + + Pseudo-algo in Intel VTd driver: + Status =3D PlatformGetVTdDeviceId (); + if (EFI_ERROR(Status)) { + if (DeviceHandle is PCI) { + Get SourceId from Bus/Device/Function + } else { + return EFI_UNSUPPORTED + } + } + Get VTd engine by Segment/Bus/Device/Function. + + @param[in] This The protocol instance pointer. + @param[in] DeviceHandle Device Identifier in UEFI. + @param[out] DeviceInfo DeviceInfo for indentify the VTd engin= e in ACPI Table + and the VTd page entry. + + @retval EFI_SUCCESS The VtdIndex and SourceId are returned. + @retval EFI_INVALID_PARAMETER DeviceHandle is not a valid handler. + @retval EFI_INVALID_PARAMETER DeviceInfo is NULL. + @retval EFI_NOT_FOUND The Segment or SourceId information is NOT= found. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +PlatformVTdGetDeviceId ( + IN EDKII_PLATFORM_VTD_POLICY_PROTOCOL *This, + IN EFI_HANDLE DeviceHandle, + OUT EDKII_PLATFORM_VTD_DEVICE_INFO *DeviceInfo + ) +{ + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN Seg; + UINTN Bus; + UINTN Dev; + UINTN Func; + EFI_STATUS Status; + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + UINTN Index; + + DEBUG ((DEBUG_VERBOSE, "PlatformVTdGetDeviceId\n")); + + if (DeviceInfo =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if (DeviceHandle =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Handle PCI device + // + Status =3D gBS->HandleProtocol (DeviceHandle, &gEfiPciIoProtocolGuid, (V= OID **)&PciIo); + if (!EFI_ERROR(Status)) { + Status =3D PciIo->GetLocation (PciIo, &Seg, &Bus, &Dev, &Func); + if (EFI_ERROR(Status)) { + return EFI_UNSUPPORTED; + } + DeviceInfo->Segment =3D (UINT16)Seg; + DeviceInfo->SourceId.Bits.Bus =3D (UINT8)Bus; + DeviceInfo->SourceId.Bits.Device =3D (UINT8)Dev; + DeviceInfo->SourceId.Bits.Function =3D (UINT8)Func; + + return EFI_SUCCESS; + } + + // + // Handle ACPI device + // + Status =3D gBS->HandleProtocol (DeviceHandle, &gEfiDevicePathProtocolGui= d, (VOID **)&DevicePath); + if (!EFI_ERROR(Status)) { + for (Index =3D 0; Index < ARRAY_SIZE(mAcpiDeviceMapping); Index++) { + if (CompareDevicePath (mAcpiDeviceMapping[Index].DevicePath, DeviceP= ath)) { + DeviceInfo->Segment =3D mAcpiDeviceMapping[Index].Segment; + DeviceInfo->SourceId =3D mAcpiDeviceMapping[Index].SourceId; + return EFI_SUCCESS; + } + } + } + + return EFI_NOT_FOUND; +} + +/** + Get a list of the exception devices. + + The VTd driver should always set ALLOW for the device in this list. + + @param[in] This The protocol instance pointer. + @param[out] DeviceInfoCount The count of the list of DeviceInfo. + @param[out] DeviceInfo A callee allocated buffer to hold a li= st of DeviceInfo. + Each DeviceInfo pointer points to EDKI= I_PLATFORM_VTD_EXCEPTION_DEVICE_INFO. + + @retval EFI_SUCCESS The DeviceInfoCount and DeviceInfo are ret= urned. + @retval EFI_INVALID_PARAMETER DeviceInfoCount is NULL, or DeviceInfo is = NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +EFI_STATUS +EFIAPI +PlatformVTdGetExceptionDeviceList ( + IN EDKII_PLATFORM_VTD_POLICY_PROTOCOL *This, + OUT UINTN *DeviceInfoCount, + OUT VOID **DeviceInfo + ) +{ + DEBUG ((DEBUG_VERBOSE, "PlatformVTdGetExceptionDeviceList\n")); + + if (DeviceInfoCount =3D=3D NULL || DeviceInfo =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Sample codes for device scope based exception list. + // Uncomment to take affect and comment the sample codes for PCI vendor = id + // based exception list. + // + /* + *DeviceInfo =3D AllocateZeroPool (sizeof(mExceptionDeviceScopeList)); + if (*DeviceInfo =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (*DeviceInfo, mExceptionDeviceScopeList, sizeof(mExceptionDevice= ScopeList)); + + *DeviceInfoCount =3D ARRAY_SIZE(mExceptionDeviceScopeList); + */ + + // + // Sample codes for PCI vendor id based exception list. + // Uncomment to take affect and comment the sample codes for device scope + // based exception list. + // + /* + *DeviceInfo =3D AllocateZeroPool (sizeof(mExceptionPciDeviceIdList)); + if (*DeviceInfo =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (*DeviceInfo, mExceptionPciDeviceIdList, sizeof(mExceptionPciDev= iceIdList)); + + *DeviceInfoCount =3D ARRAY_SIZE(mExceptionPciDeviceIdList); + */ + return EFI_UNSUPPORTED; +} + +EDKII_PLATFORM_VTD_POLICY_PROTOCOL mPlatformVTdSample =3D { + EDKII_PLATFORM_VTD_POLICY_PROTOCOL_REVISION, + PlatformVTdGetDeviceId, + PlatformVTdGetExceptionDeviceList, +}; + +/** + Platform VTd sample driver. + + @param[in] ImageHandle ImageHandle of the loaded driver + @param[in] SystemTable Pointer to the System Table + + @retval EFI_SUCCESS The Protocol is installed. + @retval EFI_OUT_OF_RESOURCES Not enough resources available to initial= ize driver. + @retval EFI_DEVICE_ERROR A device error occurred attempting to ini= tialize the driver. + +**/ +EFI_STATUS +EFIAPI +PlatformVTdSampleInitialize ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_HANDLE Handle; + + Handle =3D NULL; + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &Handle, + &gEdkiiPlatformVTdPolicyProtocolGuid, &mPlatformVTdSampl= e, + NULL + ); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeS= mbiosDataHobLib.c b/Silicon/Intel/IntelSiliconPkg/Library/DxeSmbiosDataHobL= ib/DxeSmbiosDataHobLib.c new file mode 100644 index 0000000000..bcb77eb122 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeSmbiosDa= taHobLib.c @@ -0,0 +1,81 @@ +/** @file + Library to add SMBIOS data records from HOB to SMBIOS table. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 + dated 2015-Feb-12 (DSP0134) + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.= 0.pdf + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include + + +/** + Adds SMBIOS records to tables + + @param[in] ImageHandle Image handle of this driver. + @param[in] SystemTable Global system service table. + + @retval EFI_UNSUPPORTED - Could not locate SMBIOS protocol + @retval EFI_OUT_OF_RESOURCES - Failed to allocate memory for SMBIOS HOB= type. + @retval EFI_SUCCESS - Successfully added SMBIOS records based = on HOB. +**/ +EFI_STATUS +EFIAPI +DxeSmbiosDataHobLibConstructor ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_SMBIOS_HANDLE SmbiosHandle; + EFI_SMBIOS_PROTOCOL *Smbios; + EFI_STATUS Status; + UINT8 *RecordPtr; + UINT16 RecordCount; + + RecordCount =3D 0; + + DEBUG ((DEBUG_INFO, "Adding SMBIOS records from HOB..\n")); + + Status =3D gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID **)= &Smbios); + if (Smbios =3D=3D NULL) { + DEBUG ((DEBUG_WARN, "Can't locate SMBIOS protocol\n")); + return EFI_UNSUPPORTED; + } + + /// + /// Get SMBIOS HOB data (each hob contains one SMBIOS record) + /// + for (Hob.Raw =3D GetHobList (); !END_OF_HOB_LIST(Hob); Hob.Raw =3D GET_N= EXT_HOB (Hob)) { + if ((GET_HOB_TYPE (Hob) =3D=3D EFI_HOB_TYPE_GUID_EXTENSION) && (Compar= eGuid (&Hob.Guid->Name, &gIntelSmbiosDataHobGuid))) { + RecordPtr =3D GET_GUID_HOB_DATA (Hob.Raw); + + /// + /// Add generic SMBIOS HOB to SMBIOS table + /// + DEBUG ((DEBUG_VERBOSE, "Add SMBIOS record type: %x\n", ((EFI_SMBIOS_= TABLE_HEADER *) RecordPtr)->Type)); + SmbiosHandle =3D SMBIOS_HANDLE_PI_RESERVED; + Status =3D Smbios->Add (Smbios, NULL, &SmbiosHandle, (EFI_SMBIOS_TAB= LE_HEADER *) RecordPtr); + if (!EFI_ERROR (Status)) { + RecordCount++; + } + } + } + DEBUG ((DEBUG_INFO, "Found %d Records and added to SMBIOS table.\n", Rec= ordCount)); + + return EFI_SUCCESS; +} + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/Microcod= eFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf b/Silicon/Intel/IntelSi= liconPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/MicrocodeFlash= AccessLibNull.inf new file mode 100644 index 0000000000..5ade90fe31 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashA= ccessLibNull/MicrocodeFlashAccessLibNull.inf @@ -0,0 +1,34 @@ +## @file +# Microcode flash device access library. +# +# Microcode flash device access library NULL instance. +# +# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D MicrocodeFlashAccessLibNull + MODULE_UNI_FILE =3D MicrocodeFlashAccessLibNull.uni + FILE_GUID =3D 6F871ADD-9D86-4676-8BAD-68E2E451FC5B + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D MicrocodeFlashAccessLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + MicrocodeFlashAccessLibNull.c + +[Packages] + MdePkg/MdePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[LibraryClasses] + BaseMemoryLib diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/Microcod= eFlashAccessLibNull/MicrocodeFlashAccessLibNull.uni b/Silicon/Intel/IntelSi= liconPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/MicrocodeFlash= AccessLibNull.uni new file mode 100644 index 0000000000..79918daf2b --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashA= ccessLibNull/MicrocodeFlashAccessLibNull.uni @@ -0,0 +1,16 @@ +// /** @file +// Microcode flash device access library. +// +// Microcode flash device access library NULL instance. +// +// Copyright (c) 2016, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Microcode flash d= evice access library." + +#string STR_MODULE_DESCRIPTION #language en-US "Microcode flash d= evice access library NULL instance." + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsule= Pdb/MicrocodeCapsulePdb.dsc b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule= /MicrocodeCapsulePdb/MicrocodeCapsulePdb.dsc new file mode 100644 index 0000000000..b4cf1d2638 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsulePdb/Mic= rocodeCapsulePdb.dsc @@ -0,0 +1,27 @@ +## @file +# MicrocodeCapsulePdb +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +# +# Uncomment the following line and update with your platform pkg name +# +# PLATFORM_NAME =3D + PLATFORM_GUID =3D 6875FD33-602E-4EF9-9DF2-8BA7D8B7A7AF + PLATFORM_VERSION =3D 0.1 +# +# Uncomment the following line and update with your platform pkg name +# +# FLASH_DEFINITION =3D /MicrocodeCapsulePdb/Mi= crocodeCapsulePdb.fdf +# +# Uncomment the following line and update with your platform pkg name +# +# OUTPUT_DIRECTORY =3D Build/ + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsule= Pdb/MicrocodeCapsulePdb.fdf b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule= /MicrocodeCapsulePdb/MicrocodeCapsulePdb.fdf new file mode 100644 index 0000000000..bba1a2b583 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsulePdb/Mic= rocodeCapsulePdb.fdf @@ -0,0 +1,26 @@ +## @file +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[FmpPayload.FmpPayloadMicrocode1] +IMAGE_HEADER_INIT_VERSION =3D 0x02 +IMAGE_TYPE_ID =3D 96d4fdcd-1502-424d-9d4c-9b12d2dcae5c # Micro= code GUID (do not change it) +IMAGE_INDEX =3D 0x1 +HARDWARE_INSTANCE =3D 0x0 + +# +# Uncomment the following line and update with path to Microcode PDB file +# +#FILE DATA =3D $(WORKSPACE)//Microcode/Microcode.pdb + +[Capsule.MicrocodeCapsule] +CAPSULE_GUID =3D 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # FMP= special Guid (do not change it) +CAPSULE_FLAGS =3D PersistAcrossReset,InitiateReset +CAPSULE_HEADER_SIZE =3D 0x20 +CAPSULE_HEADER_INIT_VERSION =3D 0x1 + +FMP_PAYLOAD =3D FmpPayloadMicrocode1 diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsule= Pdb/Readme.md b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCaps= ulePdb/Readme.md new file mode 100644 index 0000000000..9f81373fda --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsulePdb/Rea= dme.md @@ -0,0 +1,20 @@ +# How to generate Microcode FMP from Microcode PDB file + +1) Copy directory `UefiCpuPkg/Feature/Capsule/MicrocodeUpdatePdb` to `/MicrocodeUpdatePdb`. + +2) Uncomment and update `FILE DATA` statement in `/= MicrocodeUpdatePdb/MicrocodeCapsulePdb.fdf` with path to a Microcode PDB fi= le. The PDB file can placed in `/MicrocodeUpdatePdb= ` or any other path. + +`FILE DATA =3D ` + +Uncomment and update `PLATFORM_NAME`, `FLASH_DEFINITION`, `OUTPUT_DIRECTOR= Y` section in `/MicrocodeUpdatePdb/MicrocodeCapsuleP= db.dsc` with . + + PLATFORM_NAME =3D + FLASH_DEFINITION =3D /MicrocodeCa= psulePdb/MicrocodeCapsulePdb.fdf + OUTPUT_DIRECTORY =3D Build/ + +3) Use EDK II build tools to generate the Microcode FMP Capsule + +`build -p /MicrocodeCapsulePdb/MicrocodeCapsulePdb.= dsc` + +4) The Microcode FMP Capsule is generated at `$(WORKSPACE)/$(OUTPUT_DIRECT= ORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/MicrocodeCapsule.Cap` + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsule= Txt/Microcode/Microcode.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule= /MicrocodeCapsuleTxt/Microcode/Microcode.inf new file mode 100644 index 0000000000..7a4f2491ff --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsuleTxt/Mic= rocode/Microcode.inf @@ -0,0 +1,21 @@ +## @file +# Microcode text file to binary +# +# Convert text format microcode to binary format. +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +BASE_NAME =3D Microcode +FILE_GUID =3D ABC36AAC-2031-4422-896E-0A3B899AD0B4 +COMPONENT_TYPE =3D Microcode +FFS_EXT =3D .ffs + +[Sources] +# +# Uncomment the following line and update with name of Microcode TXT file +# +#Microcode.txt diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsule= Txt/MicrocodeCapsuleTxt.dsc b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule= /MicrocodeCapsuleTxt/MicrocodeCapsuleTxt.dsc new file mode 100644 index 0000000000..0dffe20f4e --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsuleTxt/Mic= rocodeCapsuleTxt.dsc @@ -0,0 +1,33 @@ +## @file +# MicrocodeCapsuleTxt +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +# +# Uncomment the following line and update with your platform pkg name +# +# PLATFORM_NAME =3D + PLATFORM_GUID =3D 6875FD33-602E-4EF9-9DF2-8BA7D8B7A7AF + PLATFORM_VERSION =3D 0.1 +# +# Uncomment the following line and update with your platform pkg name +# +# FLASH_DEFINITION =3D /MicrocodeCapsuleTxt/Mi= crocodeCapsuleTxt.fdf +# +# Uncomment the following line and update with your platform pkg name +# +# OUTPUT_DIRECTORY =3D Build/ + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + SKUID_IDENTIFIER =3D DEFAULT + +[Components] +# +# Uncomment the following line and update with path to Microcode INF file +# +# /MicrocodeCapsuleTxt/Microcode/Microcode.inf diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsule= Txt/MicrocodeCapsuleTxt.fdf b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule= /MicrocodeCapsuleTxt/MicrocodeCapsuleTxt.fdf new file mode 100644 index 0000000000..8366405501 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsuleTxt/Mic= rocodeCapsuleTxt.fdf @@ -0,0 +1,26 @@ +## @file +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[FmpPayload.FmpPayloadMicrocode1] +IMAGE_HEADER_INIT_VERSION =3D 0x02 +IMAGE_TYPE_ID =3D 96d4fdcd-1502-424d-9d4c-9b12d2dcae5c # Micro= code GUID (do not change it) +IMAGE_INDEX =3D 0x1 +HARDWARE_INSTANCE =3D 0x0 + +# +# Uncomment the following line and update with path to Microcode MCB file +# +#FILE DATA =3D $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/IA32/Platfo= rmPkg/MicrocodeCapsuleTxt/Microcode/Microcode/OUTPUT/Microcode.mcb + +[Capsule.MicrocodeCapsule] +CAPSULE_GUID =3D 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # FMP= special Guid (do not change it) +CAPSULE_FLAGS =3D PersistAcrossReset,InitiateReset +CAPSULE_HEADER_SIZE =3D 0x20 +CAPSULE_HEADER_INIT_VERSION =3D 0x1 + +FMP_PAYLOAD =3D FmpPayloadMicrocode1 diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsule= Txt/Readme.md b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCaps= uleTxt/Readme.md new file mode 100644 index 0000000000..f7d7040fcb --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeCapsuleTxt/Rea= dme.md @@ -0,0 +1,33 @@ +# How to generate Microcode FMP from Microcode TXT file + +1) Copy directory `UefiCpuPkg/Feature/Capsule/MicrocodeUpdateTxt` to `/MicrocodeUpdateTxt` + +2) Copy microcode TXT file to`/MicrocodeUpdateTxt/M= icrocode` + +3) Uncomment and update statement in `[Sources]` section of `/MicrocodeUpdateTxt/Microcode/Microcode.inf` with name of Microco= de TXT file copied in previous step. + + [Sources] + + +Uncomment and update `FILE DATA` statement in `/Mic= rocodeUpdateTxt/MicrocodeCapsuleTxt.fdf` with path to a Microcode MCB file.= The MCB file is placed in `$(WORKSPACE)/$(OUTPUT_DIRECTORY)/$(TARGET)_$(T= OOL_CHAIN_TAG)/IA32//MicrocodeUpdateTxt/Microcode/Mi= crocode/OUTPUT/`. + +`FILE DATA =3D ` + +Uncomment and update `PLATFORM_NAME`, `FLASH_DEFINITION`, `OUTPUT_DIRECTOR= Y` section in `/MicrocodeUpdateTxt/MicrocodeCapsuleT= xt.dsc` with . + + PLATFORM_NAME =3D + FLASH_DEFINITION =3D /MicrocodeCa= psuleTxt/MicrocodeCapsuleTxt.fdf + OUTPUT_DIRECTORY =3D Build/ + +Uncomment and update statement in `Components` section of `/MicrocodeUpdateTxt/MicrocodeCapsuleTxt.dsc` with path to a Microco= de INF file. + + [Components] + + +4) Use EDK II build tools to generate the Microcode FMP Capsule + +`build -p /MicrocodeCapsuleTxt/MicrocodeCapsuleTxt.= dsc` + +5) The generated Microcode FMP Capsule is found at `$(WORKSPACE)/$(OUTPUT_= DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/MicrocodeCapsule.Cap` + + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateD= xe/MicrocodeUpdate.h b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/Microc= odeUpdateDxe/MicrocodeUpdate.h new file mode 100644 index 0000000000..ecbe8b4994 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/Micr= ocodeUpdate.h @@ -0,0 +1,499 @@ +/** @file + Microcode update header file. + + Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _MICROCODE_FMP_H_ +#define _MICROCODE_FMP_H_ + +#include + +#include +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define MICROCODE_FMP_PRIVATE_DATA_SIGNATURE SIGNATURE_32('M', 'C', 'U', = 'F') + +// +// Microcode FMP private data structure. +// + +typedef struct { + UINT32 LastAttemptVersion; + UINT32 LastAttemptStatus; +} MICROCODE_FMP_LAST_ATTEMPT_VARIABLE; + +typedef struct { + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN TotalSize; + BOOLEAN InUse; +} MICROCODE_INFO; + +typedef struct { + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN TotalSize; + BOOLEAN InUse; + BOOLEAN Empty; +} FIT_MICROCODE_INFO; + +typedef struct { + UINTN CpuIndex; + UINT32 ProcessorSignature; + UINT8 PlatformId; + UINT32 MicrocodeRevision; + UINTN MicrocodeIndex; +} PROCESSOR_INFO; + +typedef struct { + UINT64 Address; + UINT32 Revision; +} MICROCODE_LOAD_BUFFER; + +struct _MICROCODE_FMP_PRIVATE_DATA { + UINT32 Signature; + EFI_FIRMWARE_MANAGEMENT_PROTOCOL Fmp; + EFI_HANDLE Handle; + VOID *MicrocodePatchAddress; + UINTN MicrocodePatchRegionSize; + UINT8 DescriptorCount; + EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageDescriptor; + MICROCODE_INFO *MicrocodeInfo; + UINT32 PackageVersion; + CHAR16 *PackageVersionName; + MICROCODE_FMP_LAST_ATTEMPT_VARIABLE LastAttempt; + EFI_MP_SERVICES_PROTOCOL *MpService; + UINTN BspIndex; + UINTN ProcessorCount; + PROCESSOR_INFO *ProcessorInfo; + UINT32 FitMicrocodeEntryCount; + FIT_MICROCODE_INFO *FitMicrocodeInfo; +}; + +typedef struct _MICROCODE_FMP_PRIVATE_DATA MICROCODE_FMP_PRIVATE_DATA; + +#define MICROCODE_FMP_LAST_ATTEMPT_VARIABLE_NAME L"MicrocodeLastAttemptVa= r" + +/** + Returns a pointer to the MICROCODE_FMP_PRIVATE_DATA structure from the i= nput a as Fmp. + + If the signatures matches, then a pointer to the data structure that con= tains + a specified field of that data structure is returned. + + @param a Pointer to the field specified by ServiceBinding = within + a data structure of type MICROCODE_FMP_PRIVATE_DA= TA. + +**/ +#define MICROCODE_FMP_PRIVATE_DATA_FROM_FMP(a) \ + CR ( \ + (a), \ + MICROCODE_FMP_PRIVATE_DATA, \ + Fmp, \ + MICROCODE_FMP_PRIVATE_DATA_SIGNATURE \ + ) + +/** + Get Microcode Region. + + @param[out] MicrocodePatchAddress The address of Microcode + @param[out] MicrocodePatchRegionSize The region size of Microcode + + @retval TRUE The Microcode region is returned. + @retval FALSE No Microcode region. +**/ +BOOLEAN +GetMicrocodeRegion ( + OUT VOID **MicrocodePatchAddress, + OUT UINTN *MicrocodePatchRegionSize + ); + +/** + Collect processor information. + The function prototype for invoking a function on an Application Process= or. + + @param[in,out] Buffer The pointer to private data buffer. +**/ +VOID +EFIAPI +CollectProcessorInfo ( + IN OUT VOID *Buffer + ); + +/** + Get current Microcode information. + + The ProcessorInformation (BspIndex/ProcessorCount/ProcessorInfo) + in MicrocodeFmpPrivate must be initialized. + + The MicrocodeInformation (DescriptorCount/ImageDescriptor/MicrocodeInfo) + in MicrocodeFmpPrivate may not be avaiable in this function. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] DescriptorCount The count of Microcode ImageDesc= riptor allocated. + @param[out] ImageDescriptor Microcode ImageDescriptor + @param[out] MicrocodeInfo Microcode information + + @return Microcode count +**/ +UINTN +GetMicrocodeInfo ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN UINTN DescriptorCount, OPTIONAL + OUT EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageDescriptor, OPTIONAL + OUT MICROCODE_INFO *MicrocodeInfo OPTIONAL + ); + +/** + Verify Microcode. + + Caution: This function may receive untrusted input. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] Image The Microcode image buffer. + @param[in] ImageSize The size of Microcode image buffe= r in bytes. + @param[in] TryLoad Try to load Microcode or not. + @param[out] LastAttemptStatus The last attempt status, which wi= ll be recorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + @param[out] AbortReason A pointer to a pointer to a null-= terminated string providing more + details for the aborted operation= . The buffer is allocated by this function + with AllocatePool(), and it is th= e caller's responsibility to free it with a + call to FreePool(). + @param[in, out] TargetCpuIndex On input, the index of target CPU= which tries to match the Microcode. (UINTN)-1 means to try all. + On output, the index of target CP= U which matches the Microcode. + + @retval EFI_SUCCESS The Microcode image passes verificatio= n. + @retval EFI_VOLUME_CORRUPTED The Microcode image is corrupt. + @retval EFI_INCOMPATIBLE_VERSION The Microcode image version is incorre= ct. + @retval EFI_UNSUPPORTED The Microcode ProcessorSignature or Pr= ocessorFlags is incorrect. + @retval EFI_SECURITY_VIOLATION The Microcode image fails to load. +**/ +EFI_STATUS +VerifyMicrocode ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN VOID *Image, + IN UINTN ImageSize, + IN BOOLEAN TryLoad, + OUT UINT32 *LastAttemptStatus, + OUT CHAR16 **AbortReason, OPTIONAL + IN OUT UINTN *TargetCpuIndex OPTIONAL + ); + +/** + Write Microcode. + + @param[in] MicrocodeFmpPrivate The Microcode driver private data + @param[in] Image The Microcode image buffer. + @param[in] ImageSize The size of Microcode image buffer in b= ytes. + @param[out] LastAttemptVersion The last attempt version, which will be= recorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + @param[out] LastAttemptStatus The last attempt status, which will be = recorded in ESRT and FMP EFI_FIRMWARE_IMAGE_DESCRIPTOR. + @param[out] AbortReason A pointer to a pointer to a null-termin= ated string providing more + details for the aborted operation. The = buffer is allocated by this function + with AllocatePool(), and it is the call= er's responsibility to free it with a + call to FreePool(). + + @retval EFI_SUCCESS The Microcode image is written. + @retval EFI_VOLUME_CORRUPTED The Microcode image is corrupt. + @retval EFI_INCOMPATIBLE_VERSION The Microcode image version is incorre= ct. + @retval EFI_SECURITY_VIOLATION The Microcode image fails to load. + @retval EFI_WRITE_PROTECTED The flash device is read only. +**/ +EFI_STATUS +MicrocodeWrite ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate, + IN VOID *Image, + IN UINTN ImageSize, + OUT UINT32 *LastAttemptVersion, + OUT UINT32 *LastAttemptStatus, + OUT CHAR16 **AbortReason + ); + +/** + Dump private information. + + @param[in] MicrocodeFmpPrivate private data structure. +**/ +VOID +DumpPrivateInfo ( + IN MICROCODE_FMP_PRIVATE_DATA *MicrocodeFmpPrivate + ); + +/** + Returns information about the current firmware image(s) of the device. + + This function allows a copy of the current firmware image to be created = and saved. + The saved copy could later been used, for example, in firmware image rec= overy or rollback. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEM= ENT_PROTOCOL instance. + @param[in, out] ImageInfoSize A pointer to the size, in bytes, of t= he ImageInfo buffer. + On input, this is the size of the buf= fer allocated by the caller. + On output, it is the size of the buff= er returned by the firmware + if the buffer was large enough, or th= e size of the buffer needed + to contain the image(s) information i= f the buffer was too small. + @param[in, out] ImageInfo A pointer to the buffer in which firm= ware places the current image(s) + information. The information is an ar= ray of EFI_FIRMWARE_IMAGE_DESCRIPTORs. + @param[out] DescriptorVersion A pointer to the location in which fi= rmware returns the version number + associated with the EFI_FIRMWARE_IMAG= E_DESCRIPTOR. + @param[out] DescriptorCount A pointer to the location in which fi= rmware returns the number of + descriptors or firmware images within= this device. + @param[out] DescriptorSize A pointer to the location in which fi= rmware returns the size, in bytes, + of an individual EFI_FIRMWARE_IMAGE_D= ESCRIPTOR. + @param[out] PackageVersion A version number that represents all = the firmware images in the device. + The format is vendor specific and new= version must have a greater value + than the old version. If PackageVersi= on is not supported, the value is + 0xFFFFFFFF. A value of 0xFFFFFFFE ind= icates that package version comparison + is to be performed using PackageVersi= onName. A value of 0xFFFFFFFD indicates + that package version update is in pro= gress. + @param[out] PackageVersionName A pointer to a pointer to a null-term= inated string representing the + package version name. The buffer is a= llocated by this function with + AllocatePool(), and it is the caller'= s responsibility to free it with a call + to FreePool(). + + @retval EFI_SUCCESS The device was successfully updated w= ith the new image. + @retval EFI_BUFFER_TOO_SMALL The ImageInfo buffer was too small. T= he current buffer size + needed to hold the image(s) informati= on is returned in ImageInfoSize. + @retval EFI_INVALID_PARAMETER ImageInfoSize is NULL. + @retval EFI_DEVICE_ERROR Valid information could not be return= ed. Possible corrupted image. + +**/ +EFI_STATUS +EFIAPI +FmpGetImageInfo ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN OUT UINTN *ImageInfoSize, + IN OUT EFI_FIRMWARE_IMAGE_DESCRIPTOR *ImageInfo, + OUT UINT32 *DescriptorVersion, + OUT UINT8 *DescriptorCount, + OUT UINTN *DescriptorSize, + OUT UINT32 *PackageVersion, + OUT CHAR16 **PackageVersionName + ); + +/** + Retrieves a copy of the current firmware image of the device. + + This function allows a copy of the current firmware image to be created = and saved. + The saved copy could later been used, for example, in firmware image rec= overy or rollback. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_= PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware = image(s) within the device. + The number is between 1 and DescriptorCou= nt. + @param[in,out] Image Points to the buffer where the current im= age is copied to. + @param[in,out] ImageSize On entry, points to the size of the buffe= r pointed to by Image, in bytes. + On return, points to the length of the im= age, in bytes. + + @retval EFI_SUCCESS The device was successfully updated with = the new image. + @retval EFI_BUFFER_TOO_SMALL The buffer specified by ImageSize is too = small to hold the + image. The current buffer size needed to = hold the image is returned + in ImageSize. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_NOT_FOUND The current image is not copied to the bu= ffer. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due = to an authentication failure. + +**/ +EFI_STATUS +EFIAPI +FmpGetImage ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + IN OUT VOID *Image, + IN OUT UINTN *ImageSize + ); + +/** + Updates the firmware image of the device. + + This function updates the hardware with the new firmware image. + This function returns EFI_UNSUPPORTED if the firmware image is not updat= able. + If the firmware image is updatable, the function should perform the foll= owing minimal validations + before proceeding to do the firmware image update. + - Validate the image authentication if image has attribute + IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED. The function returns + EFI_SECURITY_VIOLATION if the validation fails. + - Validate the image is a supported image for this device. The function = returns EFI_ABORTED if + the image is unsupported. The function can optionally provide more det= ailed information on + why the image is not a supported image. + - Validate the data from VendorCode if not null. Image validation must b= e performed before + VendorCode data validation. VendorCode data is ignored or considered i= nvalid if image + validation failed. The function returns EFI_ABORTED if the data is inv= alid. + + VendorCode enables vendor to implement vendor-specific firmware image up= date policy. Null if + the caller did not specify the policy or use the default policy. As an e= xample, vendor can implement + a policy to allow an option to force a firmware image update when the ab= ort reason is due to the new + firmware image version is older than the current firmware image version = or bad image checksum. + Sensitive operations such as those wiping the entire firmware image and = render the device to be + non-functional should be encoded in the image itself rather than passed = with the VendorCode. + AbortReason enables vendor to have the option to provide a more detailed= description of the abort + reason to the caller. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_= PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware = image(s) within the device. + The number is between 1 and DescriptorCou= nt. + @param[in] Image Points to the new image. + @param[in] ImageSize Size of the new image in bytes. + @param[in] VendorCode This enables vendor to implement vendor-s= pecific firmware image update policy. + Null indicates the caller did not specify= the policy or use the default policy. + @param[in] Progress A function used by the driver to report t= he progress of the firmware update. + @param[out] AbortReason A pointer to a pointer to a null-terminat= ed string providing more + details for the aborted operation. The bu= ffer is allocated by this function + with AllocatePool(), and it is the caller= 's responsibility to free it with a + call to FreePool(). + + @retval EFI_SUCCESS The device was successfully updated with = the new image. + @retval EFI_ABORTED The operation is aborted. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due = to an authentication failure. + +**/ +EFI_STATUS +EFIAPI +FmpSetImage ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + IN CONST VOID *Image, + IN UINTN ImageSize, + IN CONST VOID *VendorCode, + IN EFI_FIRMWARE_MANAGEMENT_UPDATE_IMAGE_PROGRESS Progress, + OUT CHAR16 **AbortReason + ); + +/** + Checks if the firmware image is valid for the device. + + This function allows firmware update application to validate the firmwar= e image without + invoking the SetImage() first. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_= PROTOCOL instance. + @param[in] ImageIndex A unique number identifying the firmware = image(s) within the device. + The number is between 1 and DescriptorCou= nt. + @param[in] Image Points to the new image. + @param[in] ImageSize Size of the new image in bytes. + @param[out] ImageUpdatable Indicates if the new image is valid for u= pdate. It also provides, + if available, additional information if t= he image is invalid. + + @retval EFI_SUCCESS The image was successfully checked. + @retval EFI_INVALID_PARAMETER The Image was NULL. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due = to an authentication failure. + +**/ +EFI_STATUS +EFIAPI +FmpCheckImage ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN UINT8 ImageIndex, + IN CONST VOID *Image, + IN UINTN ImageSize, + OUT UINT32 *ImageUpdatable + ); + +/** + Returns information about the firmware package. + + This function returns package information. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAG= EMENT_PROTOCOL instance. + @param[out] PackageVersion A version number that represents al= l the firmware images in the device. + The format is vendor specific and n= ew version must have a greater value + than the old version. If PackageVer= sion is not supported, the value is + 0xFFFFFFFF. A value of 0xFFFFFFFE i= ndicates that package version + comparison is to be performed using= PackageVersionName. A value of + 0xFFFFFFFD indicates that package v= ersion update is in progress. + @param[out] PackageVersionName A pointer to a pointer to a null-te= rminated string representing + the package version name. The buffe= r is allocated by this function with + AllocatePool(), and it is the calle= r's responsibility to free it with a + call to FreePool(). + @param[out] PackageVersionNameMaxLen The maximum length of package versi= on name if device supports update of + package version name. A value of 0 = indicates the device does not support + update of package version name. Len= gth is the number of Unicode characters, + including the terminating null char= acter. + @param[out] AttributesSupported Package attributes that are support= ed by this device. See 'Package Attribute + Definitions' for possible returned = values of this parameter. A value of 1 + indicates the attribute is supporte= d and the current setting value is + indicated in AttributesSetting. A v= alue of 0 indicates the attribute is not + supported and the current setting v= alue in AttributesSetting is meaningless. + @param[out] AttributesSetting Package attributes. See 'Package At= tribute Definitions' for possible returned + values of this parameter + + @retval EFI_SUCCESS The package information was success= fully returned. + @retval EFI_UNSUPPORTED The operation is not supported. + +**/ +EFI_STATUS +EFIAPI +FmpGetPackageInfo ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + OUT UINT32 *PackageVersion, + OUT CHAR16 **PackageVersionName, + OUT UINT32 *PackageVersionNameMaxLen, + OUT UINT64 *AttributesSupported, + OUT UINT64 *AttributesSetting + ); + +/** + Updates information about the firmware package. + + This function updates package information. + This function returns EFI_UNSUPPORTED if the package information is not = updatable. + VendorCode enables vendor to implement vendor-specific package informati= on update policy. + Null if the caller did not specify this policy or use the default policy. + + @param[in] This A pointer to the EFI_FIRMWARE_MANAGEMENT_= PROTOCOL instance. + @param[in] Image Points to the authentication image. + Null if authentication is not required. + @param[in] ImageSize Size of the authentication image in bytes. + 0 if authentication is not required. + @param[in] VendorCode This enables vendor to implement vendor-s= pecific firmware + image update policy. + Null indicates the caller did not specify= this policy or use + the default policy. + @param[in] PackageVersion The new package version. + @param[in] PackageVersionName A pointer to the new null-terminated Unic= ode string representing + the package version name. + The string length is equal to or less tha= n the value returned in + PackageVersionNameMaxLen. + + @retval EFI_SUCCESS The device was successfully updated with = the new package + information. + @retval EFI_INVALID_PARAMETER The PackageVersionName length is longer t= han the value + returned in PackageVersionNameMaxLen. + @retval EFI_UNSUPPORTED The operation is not supported. + @retval EFI_SECURITY_VIOLATION The operation could not be performed due = to an authentication failure. + +**/ +EFI_STATUS +EFIAPI +FmpSetPackageInfo ( + IN EFI_FIRMWARE_MANAGEMENT_PROTOCOL *This, + IN CONST VOID *Image, + IN UINTN ImageSize, + IN CONST VOID *VendorCode, + IN UINT32 PackageVersion, + IN CONST CHAR16 *PackageVersionName + ); + +#endif + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateD= xe/MicrocodeUpdateDxe.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/M= icrocodeUpdateDxe/MicrocodeUpdateDxe.inf new file mode 100644 index 0000000000..8e9fa440f0 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/Micr= ocodeUpdateDxe.inf @@ -0,0 +1,67 @@ +## @file +# Microcode FMP update driver. +# +# Produce FMP instance to update Microcode. +# +# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D MicrocodeUpdateDxe + MODULE_UNI_FILE =3D MicrocodeUpdateDxe.uni + FILE_GUID =3D 0565365C-2FE1-4F88-B3BE-624C04623A20 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D MicrocodeFmpMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D X64 +# + +[Sources] + MicrocodeUpdate.h + MicrocodeFmp.c + MicrocodeUpdate.c + +[Packages] + MdePkg/MdePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + UefiLib + BaseMemoryLib + DebugLib + PcdLib + MemoryAllocationLib + UefiBootServicesTableLib + HobLib + UefiRuntimeServicesTableLib + UefiDriverEntryPoint + MicrocodeFlashAccessLib + +[Guids] + gMicrocodeFmpImageTypeIdGuid ## CONSUMES ## GUID + +[Protocols] + gEfiFirmwareManagementProtocolGuid ## PRODUCES + gEfiMpServiceProtocolGuid ## CONSUMES + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONS= UMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONS= UMES + +[Depex] + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid AND + gEfiMpServiceProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + MicrocodeUpdateDxeExtra.uni + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateD= xe/MicrocodeUpdateDxe.uni b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/M= icrocodeUpdateDxe/MicrocodeUpdateDxe.uni new file mode 100644 index 0000000000..a793631c10 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/Micr= ocodeUpdateDxe.uni @@ -0,0 +1,15 @@ +// /** @file +// Microcode FMP update driver. +// +// Produce FMP instance to update Microcode. +// +// Copyright (c) 2016, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Microcode FMP upd= ate driver." + +#string STR_MODULE_DESCRIPTION #language en-US "Produce FMP insta= nce to update Microcode." diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateD= xe/MicrocodeUpdateDxeExtra.uni b/Silicon/Intel/IntelSiliconPkg/Feature/Caps= ule/MicrocodeUpdateDxe/MicrocodeUpdateDxeExtra.uni new file mode 100644 index 0000000000..cf9853d02c --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/Micr= ocodeUpdateDxeExtra.uni @@ -0,0 +1,14 @@ +// /** @file +// MicrocodeUpdateDxe Localized Strings and Content +// +// Copyright (c) 2016, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"MicrocodeUpdate DXE Driver" + + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProte= ction.h b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtecti= on.h new file mode 100644 index 0000000000..a3331db8f7 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.h @@ -0,0 +1,632 @@ +/** @file + + Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _DMAR_PROTECTION_H_ +#define _DMAR_PROTECTION_H_ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#define VTD_64BITS_ADDRESS(Lo, Hi) (LShiftU64 (Lo, 12) | LShiftU64 (Hi, 32= )) + +#define ALIGN_VALUE_UP(Value, Alignment) (((Value) + (Alignment) - 1) & (= ~((Alignment) - 1))) +#define ALIGN_VALUE_LOW(Value, Alignment) ((Value) & (~((Alignment) - 1))) + +#define VTD_TPL_LEVEL TPL_NOTIFY + +// +// This is the initial max PCI DATA number. +// The number may be enlarged later. +// +#define MAX_VTD_PCI_DATA_NUMBER 0x100 + +typedef struct { + UINT8 DeviceType; + VTD_SOURCE_ID PciSourceId; + EDKII_PLATFORM_VTD_PCI_DEVICE_ID PciDeviceId; + // for statistic analysis + UINTN AccessCount; +} PCI_DEVICE_DATA; + +typedef struct { + BOOLEAN IncludeAllFlag; + UINTN PciDeviceDataNumber; + UINTN PciDeviceDataMaxNumber; + PCI_DEVICE_DATA *PciDeviceData; +} PCI_DEVICE_INFORMATION; + +typedef struct { + UINTN VtdUnitBaseAddress; + UINT16 Segment; + VTD_CAP_REG CapReg; + VTD_ECAP_REG ECapReg; + VTD_ROOT_ENTRY *RootEntryTable; + VTD_EXT_ROOT_ENTRY *ExtRootEntryTable; + VTD_SECOND_LEVEL_PAGING_ENTRY *FixedSecondLevelPagingEntry; + BOOLEAN HasDirtyContext; + BOOLEAN HasDirtyPages; + PCI_DEVICE_INFORMATION PciDeviceInfo; +} VTD_UNIT_INFORMATION; + +// +// This is the initial max ACCESS request. +// The number may be enlarged later. +// +#define MAX_VTD_ACCESS_REQUEST 0x100 + +typedef struct { + UINT16 Segment; + VTD_SOURCE_ID SourceId; + UINT64 BaseAddress; + UINT64 Length; + UINT64 IoMmuAccess; +} VTD_ACCESS_REQUEST; + + +/** + The scan bus callback function. + + It is called in PCI bus scan for each PCI device under the bus. + + @param[in] Context The context of the callback. + @param[in] Segment The segment of the source. + @param[in] Bus The bus of the source. + @param[in] Device The device of the source. + @param[in] Function The function of the source. + + @retval EFI_SUCCESS The specific PCI device is processed in th= e callback. +**/ +typedef +EFI_STATUS +(EFIAPI *SCAN_BUS_FUNC_CALLBACK_FUNC) ( + IN VOID *Context, + IN UINT16 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function + ); + +extern EFI_ACPI_DMAR_HEADER *mAcpiDmarTable; + +extern UINTN mVtdUnitNumber; +extern VTD_UNIT_INFORMATION *mVtdUnitInformation; + +extern UINT64 mBelow4GMemoryLimit; +extern UINT64 mAbove4GMemoryLimit; + +extern EDKII_PLATFORM_VTD_POLICY_PROTOCOL *mPlatformVTdPolicy; + +/** + Prepare VTD configuration. +**/ +VOID +PrepareVtdConfig ( + VOID + ); + +/** + Setup VTd translation table. + + @retval EFI_SUCCESS Setup translation table successfully. + @retval EFI_OUT_OF_RESOURCE Setup translation table fail. +**/ +EFI_STATUS +SetupTranslationTable ( + VOID + ); + +/** + Enable DMAR translation. + + @retval EFI_SUCCESS DMAR translation is enabled. + @retval EFI_DEVICE_ERROR DMAR translation is not enabled. +**/ +EFI_STATUS +EnableDmar ( + VOID + ); + +/** + Disable DMAR translation. + + @retval EFI_SUCCESS DMAR translation is disabled. + @retval EFI_DEVICE_ERROR DMAR translation is not disabled. +**/ +EFI_STATUS +DisableDmar ( + VOID + ); + +/** + Flush VTd engine write buffer. + + @param[in] VtdIndex The index used to identify a VTd engine. +**/ +VOID +FlushWriteBuffer ( + IN UINTN VtdIndex + ); + +/** + Invalidate VTd context cache. + + @param[in] VtdIndex The index used to identify a VTd engine. +**/ +EFI_STATUS +InvalidateContextCache ( + IN UINTN VtdIndex + ); + +/** + Invalidate VTd IOTLB. + + @param[in] VtdIndex The index used to identify a VTd engine. +**/ +EFI_STATUS +InvalidateIOTLB ( + IN UINTN VtdIndex + ); + +/** + Invalid VTd global IOTLB. + + @param[in] VtdIndex The index of VTd engine. + + @retval EFI_SUCCESS VTd global IOTLB is invalidated. + @retval EFI_DEVICE_ERROR VTd global IOTLB is not invalidated. +**/ +EFI_STATUS +InvalidateVtdIOTLBGlobal ( + IN UINTN VtdIndex + ); + +/** + Dump VTd registers. + + @param[in] VtdIndex The index of VTd engine. +**/ +VOID +DumpVtdRegs ( + IN UINTN VtdIndex + ); + +/** + Dump VTd registers for all VTd engine. +**/ +VOID +DumpVtdRegsAll ( + VOID + ); + +/** + Dump VTd capability registers. + + @param[in] CapReg The capability register. +**/ +VOID +DumpVtdCapRegs ( + IN VTD_CAP_REG *CapReg + ); + +/** + Dump VTd extended capability registers. + + @param[in] ECapReg The extended capability register. +**/ +VOID +DumpVtdECapRegs ( + IN VTD_ECAP_REG *ECapReg + ); + +/** + Register PCI device to VTd engine. + + @param[in] VtdIndex The index of VTd engine. + @param[in] Segment The segment of the source. + @param[in] SourceId The SourceId of the source. + @param[in] DeviceType The DMAR device scope type. + @param[in] CheckExist TRUE: ERROR will be returned if the PC= I device is already registered. + FALSE: SUCCESS will be returned if the= PCI device is registered. + + @retval EFI_SUCCESS The PCI device is registered. + @retval EFI_OUT_OF_RESOURCES No enough resource to register a new PCI d= evice. + @retval EFI_ALREADY_STARTED The device is already registered. +**/ +EFI_STATUS +RegisterPciDevice ( + IN UINTN VtdIndex, + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId, + IN UINT8 DeviceType, + IN BOOLEAN CheckExist + ); + +/** + The scan bus callback function to always enable page attribute. + + @param[in] Context The context of the callback. + @param[in] Segment The segment of the source. + @param[in] Bus The bus of the source. + @param[in] Device The device of the source. + @param[in] Function The function of the source. + + @retval EFI_SUCCESS The VTd entry is updated to always enable = all DMA access for the specific device. +**/ +EFI_STATUS +EFIAPI +ScanBusCallbackRegisterPciDevice ( + IN VOID *Context, + IN UINT16 Segment, + IN UINT8 Bus, + IN UINT8 Device, + IN UINT8 Function + ); + +/** + Scan PCI bus and invoke callback function for each PCI devices under the= bus. + + @param[in] Context The context of the callback function. + @param[in] Segment The segment of the source. + @param[in] Bus The bus of the source. + @param[in] Callback The callback function in PCI scan. + + @retval EFI_SUCCESS The PCI devices under the bus are scaned. +**/ +EFI_STATUS +ScanPciBus ( + IN VOID *Context, + IN UINT16 Segment, + IN UINT8 Bus, + IN SCAN_BUS_FUNC_CALLBACK_FUNC Callback + ); + +/** + Dump the PCI device information managed by this VTd engine. + + @param[in] VtdIndex The index of VTd engine. +**/ +VOID +DumpPciDeviceInfo ( + IN UINTN VtdIndex + ); + +/** + Find the VTd index by the Segment and SourceId. + + @param[in] Segment The segment of the source. + @param[in] SourceId The SourceId of the source. + @param[out] ExtContextEntry The ExtContextEntry of the source. + @param[out] ContextEntry The ContextEntry of the source. + + @return The index of the VTd engine. + @retval (UINTN)-1 The VTd engine is not found. +**/ +UINTN +FindVtdIndexByPciDevice ( + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId, + OUT VTD_EXT_CONTEXT_ENTRY **ExtContextEntry, + OUT VTD_CONTEXT_ENTRY **ContextEntry + ); + +/** + Get the DMAR ACPI table. + + @retval EFI_SUCCESS The DMAR ACPI table is got. + @retval EFI_ALREADY_STARTED The DMAR ACPI table has been got previousl= y. + @retval EFI_NOT_FOUND The DMAR ACPI table is not found. +**/ +EFI_STATUS +GetDmarAcpiTable ( + VOID + ); + +/** + Parse DMAR DRHD table. + + @return EFI_SUCCESS The DMAR DRHD table is parsed. +**/ +EFI_STATUS +ParseDmarAcpiTableDrhd ( + VOID + ); + +/** + Parse DMAR RMRR table. + + @return EFI_SUCCESS The DMAR RMRR table is parsed. +**/ +EFI_STATUS +ParseDmarAcpiTableRmrr ( + VOID + ); + +/** + Dump DMAR context entry table. + + @param[in] RootEntry DMAR root entry. +**/ +VOID +DumpDmarContextEntryTable ( + IN VTD_ROOT_ENTRY *RootEntry + ); + +/** + Dump DMAR extended context entry table. + + @param[in] ExtRootEntry DMAR extended root entry. +**/ +VOID +DumpDmarExtContextEntryTable ( + IN VTD_EXT_ROOT_ENTRY *ExtRootEntry + ); + +/** + Dump DMAR second level paging entry. + + @param[in] SecondLevelPagingEntry The second level paging entry. +**/ +VOID +DumpSecondLevelPagingEntry ( + IN VOID *SecondLevelPagingEntry + ); + +/** + Set VTd attribute for a system memory. + + @param[in] VtdIndex The index used to identify a VTd eng= ine. + @param[in] DomainIdentifier The domain ID of the source. + @param[in] SecondLevelPagingEntry The second level paging entry in VTd= table for the device. + @param[in] BaseAddress The base of device memory address to= be used as the DMA memory. + @param[in] Length The length of device memory address = to be used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by BaseAddress and Length. + @retval EFI_INVALID_PARAMETER BaseAddress is not IoMmu Page size aligne= d. + @retval EFI_INVALID_PARAMETER Length is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is 0. + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by BaseAddress and Length. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. +**/ +EFI_STATUS +SetPageAttribute ( + IN UINTN VtdIndex, + IN UINT16 DomainIdentifier, + IN VTD_SECOND_LEVEL_PAGING_ENTRY *SecondLevelPagingEntry, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ); + +/** + Set VTd attribute for a system memory. + + @param[in] Segment The Segment used to identify a VTd engine. + @param[in] SourceId The SourceId used to identify a VTd engine= and table entry. + @param[in] BaseAddress The base of device memory address to be us= ed as the DMA memory. + @param[in] Length The length of device memory address to be = used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory ran= ge specified by BaseAddress and Length. + @retval EFI_INVALID_PARAMETER BaseAddress is not IoMmu Page size aligne= d. + @retval EFI_INVALID_PARAMETER Length is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is 0. + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinat= ion of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not suppor= ted by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory ran= ge specified by BaseAddress and Length. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while = attempting the operation. +**/ +EFI_STATUS +SetAccessAttribute ( + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ); + +/** + Return the index of PCI data. + + @param[in] VtdIndex The index used to identify a VTd engine. + @param[in] Segment The Segment used to identify a VTd engine. + @param[in] SourceId The SourceId used to identify a VTd engine= and table entry. + + @return The index of the PCI data. + @retval (UINTN)-1 The PCI data is not found. +**/ +UINTN +GetPciDataIndex ( + IN UINTN VtdIndex, + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId + ); + +/** + Dump VTd registers if there is error. +**/ +VOID +DumpVtdIfError ( + VOID + ); + +/** + Initialize platform VTd policy. +**/ +VOID +InitializePlatformVTdPolicy ( + VOID + ); + +/** + Always enable the VTd page attribute for the device. + + @param[in] Segment The Segment used to identify a VTd engine. + @param[in] SourceId The SourceId used to identify a VTd engine= and table entry. + + @retval EFI_SUCCESS The VTd entry is updated to always enable = all DMA access for the specific device. +**/ +EFI_STATUS +AlwaysEnablePageAttribute ( + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId + ); + +/** + Convert the DeviceHandle to SourceId and Segment. + + @param[in] DeviceHandle The device who initiates the DMA access re= quest. + @param[out] Segment The Segment used to identify a VTd engine. + @param[out] SourceId The SourceId used to identify a VTd engine= and table entry. + + @retval EFI_SUCCESS The Segment and SourceId are returned. + @retval EFI_INVALID_PARAMETER DeviceHandle is an invalid handle. + @retval EFI_UNSUPPORTED DeviceHandle is unknown by the IOMMU. +**/ +EFI_STATUS +DeviceHandleToSourceId ( + IN EFI_HANDLE DeviceHandle, + OUT UINT16 *Segment, + OUT VTD_SOURCE_ID *SourceId + ); + +/** + Get device information from mapping. + + @param[in] Mapping The mapping. + @param[out] DeviceAddress The device address of the mapping. + @param[out] NumberOfPages The number of pages of the mapping. + + @retval EFI_SUCCESS The device information is returned. + @retval EFI_INVALID_PARAMETER The mapping is invalid. +**/ +EFI_STATUS +GetDeviceInfoFromMapping ( + IN VOID *Mapping, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT UINTN *NumberOfPages + ); + +/** + Initialize DMA protection. +**/ +VOID +InitializeDmaProtection ( + VOID + ); + +/** + Allocate zero pages. + + @param[in] Pages the number of pages. + + @return the page address. + @retval NULL No resource to allocate pages. +**/ +VOID * +EFIAPI +AllocateZeroPages ( + IN UINTN Pages + ); + +/** + Flush VTD page table and context table memory. + + This action is to make sure the IOMMU engine can get final data in memor= y. + + @param[in] VtdIndex The index used to identify a VTd engine. + @param[in] Base The base address of memory to be flushed. + @param[in] Size The size of memory in bytes to be flushed. +**/ +VOID +FlushPageTableMemory ( + IN UINTN VtdIndex, + IN UINTN Base, + IN UINTN Size + ); + +/** + Get PCI device information from DMAR DevScopeEntry. + + @param[in] Segment The segment number. + @param[in] DmarDevScopeEntry DMAR DevScopeEntry + @param[out] Bus The bus number. + @param[out] Device The device number. + @param[out] Function The function number. + + @retval EFI_SUCCESS The PCI device information is returned. +**/ +EFI_STATUS +GetPciBusDeviceFunction ( + IN UINT16 Segment, + IN EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DmarDevScopeEntry, + OUT UINT8 *Bus, + OUT UINT8 *Device, + OUT UINT8 *Function + ); + +/** + Append VTd Access Request to global. + + @param[in] Segment The Segment used to identify a VTd engine. + @param[in] SourceId The SourceId used to identify a VTd engine= and table entry. + @param[in] BaseAddress The base of device memory address to be us= ed as the DMA memory. + @param[in] Length The length of device memory address to be = used as the DMA memory. + @param[in] IoMmuAccess The IOMMU access. + + @retval EFI_SUCCESS The IoMmuAccess is set for the memory rang= e specified by BaseAddress and Length. + @retval EFI_INVALID_PARAMETER BaseAddress is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is not IoMmu Page size aligned. + @retval EFI_INVALID_PARAMETER Length is 0. + @retval EFI_INVALID_PARAMETER IoMmuAccess specified an illegal combinati= on of access. + @retval EFI_UNSUPPORTED The bit mask of IoMmuAccess is not support= ed by the IOMMU. + @retval EFI_UNSUPPORTED The IOMMU does not support the memory rang= e specified by BaseAddress and Length. + @retval EFI_OUT_OF_RESOURCES There are not enough resources available t= o modify the IOMMU access. + @retval EFI_DEVICE_ERROR The IOMMU device reported an error while a= ttempting the operation. + +**/ +EFI_STATUS +RequestAccessAttribute ( + IN UINT16 Segment, + IN VTD_SOURCE_ID SourceId, + IN UINT64 BaseAddress, + IN UINT64 Length, + IN UINT64 IoMmuAccess + ); + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTd= Dxe.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe= .inf new file mode 100644 index 0000000000..220636adab --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf @@ -0,0 +1,83 @@ +## @file +# Intel VTd DXE Driver. +# +# This driver initializes VTd engine based upon DMAR ACPI tables +# and provide DMA protection to PCI or ACPI device. +# +# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IntelVTdDxe + MODULE_UNI_FILE =3D IntelVTdDxe.uni + FILE_GUID =3D 987555D6-595D-4CFA-B895-59B89368BD4D + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IntelVTdInitialize + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# +# + +[Sources] + IntelVTdDxe.c + BmDma.c + DmaProtection.c + DmaProtection.h + DmarAcpiTable.c + PciInfo.c + TranslationTable.c + TranslationTableEx.c + VtdReg.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[LibraryClasses] + DebugLib + UefiDriverEntryPoint + UefiBootServicesTableLib + BaseLib + IoLib + PciSegmentLib + BaseMemoryLib + MemoryAllocationLib + UefiLib + CacheMaintenanceLib + PerformanceLib + PrintLib + ReportStatusCodeLib + +[Guids] + gEfiEventExitBootServicesGuid ## CONSUMES ## Event + ## CONSUMES ## SystemTable + ## CONSUMES ## Event + gEfiAcpi20TableGuid + ## CONSUMES ## SystemTable + ## CONSUMES ## Event + gEfiAcpi10TableGuid + +[Protocols] + gEdkiiIoMmuProtocolGuid ## PRODUCES + gEfiPciIoProtocolGuid ## CONSUMES + gEfiPciEnumerationCompleteProtocolGuid ## CONSUMES + gEdkiiPlatformVTdPolicyProtocolGuid ## SOMETIMES_CONSUMES + +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError ## CONSUMES + +[Depex] + gEfiPciRootBridgeIoProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + IntelVTdDxeExtra.uni + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTd= Dxe.uni b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe= .uni new file mode 100644 index 0000000000..e41fcff0e9 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.uni @@ -0,0 +1,14 @@ +// /** @file +// IntelVTdDxe Module Localized Abstract and Description Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Intel VTd DXE Dri= ver." + +#string STR_MODULE_DESCRIPTION #language en-US "This driver initi= alizes VTd engine based upon DMAR ACPI tables and provide DMA protection to= PCI or ACPI device." + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTd= DxeExtra.uni b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelV= TdDxeExtra.uni new file mode 100644 index 0000000000..cd08ff3eda --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxeExtr= a.uni @@ -0,0 +1,14 @@ +// /** @file +// IntelVTdDxe Localized Strings and Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Intel VTd DXE Driver" + + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmrPei.h b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Inte= lVTdPmrPei.h new file mode 100644 index 0000000000..58e6afad08 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.h @@ -0,0 +1,159 @@ +/** @file + The definition for DMA access Library. + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DMA_ACCESS_LIB_H__ +#define __DMA_ACCESS_LIB_H__ + +typedef struct { + EFI_ACPI_DMAR_HEADER *AcpiDmarTable; + UINT64 EngineMask; + UINT8 HostAddressWidth; + UINTN VTdEngineCount; + UINT64 VTdEngineAddress[1]; +} VTD_INFO; + +/** + Set DMA protected region. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + @param LowMemoryBase The protected low memory region base. + @param LowMemoryLength The protected low memory region length. + @param HighMemoryBase The protected high memory region base. + @param HighMemoryLength The protected high memory region length. + + @retval EFI_SUCCESS The DMA protection is set. + @retval EFI_UNSUPPORTED The DMA protection is not set. +**/ +EFI_STATUS +SetDmaProtectedRange ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask, + IN UINT32 LowMemoryBase, + IN UINT32 LowMemoryLength, + IN UINT64 HighMemoryBase, + IN UINT64 HighMemoryLength + ); + +/** + Diable DMA protection. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + + @retval DMA protection is disabled. +**/ +EFI_STATUS +DisableDmaProtection ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ); + +/** + Return if the DMA protection is enabled. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + + @retval TRUE DMA protection is enabled in at least one VTd engine. + @retval FALSE DMA protection is disabled in all VTd engines. +**/ +UINT64 +GetDmaProtectionEnabledEngineMask ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ); + +/** + Get protected low memory alignment. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + + @return protected low memory alignment. +**/ +UINT32 +GetLowMemoryAlignment ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ); + +/** + Get protected high memory alignment. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. + + @return protected high memory alignment. +**/ +UINT64 +GetHighMemoryAlignment ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ); + +/** + Enable VTd translation table protection. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. +**/ +VOID +EnableVTdTranslationProtection ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ); + +/** + Disable VTd translation table protection. + + @param VTdInfo The VTd engine context information. + @param EngineMask The mask of the VTd engine to be accessed. +**/ +VOID +DisableVTdTranslationProtection ( + IN VTD_INFO *VTdInfo, + IN UINT64 EngineMask + ); + +/** + Parse DMAR DRHD table. + + @param[in] AcpiDmarTable DMAR ACPI table + + @return EFI_SUCCESS The DMAR DRHD table is parsed. +**/ +EFI_STATUS +ParseDmarAcpiTableDrhd ( + IN EFI_ACPI_DMAR_HEADER *AcpiDmarTable + ); + +/** + Parse DMAR DRHD table. + + @param VTdInfo The VTd engine context information. +**/ +VOID +ParseDmarAcpiTableRmrr ( + IN VTD_INFO *VTdInfo + ); + +/** + Dump DMAR ACPI table. + + @param[in] Dmar DMAR ACPI table +**/ +VOID +DumpAcpiDMAR ( + IN EFI_ACPI_DMAR_HEADER *Dmar + ); + +extern EFI_GUID mVTdInfoGuid; + +#endif + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmrPei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/In= telVTdPmrPei.inf new file mode 100644 index 0000000000..39b914cd00 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.inf @@ -0,0 +1,60 @@ +## @file +# Component INF file for the Intel VTd PMR PEIM. +# +# This driver initializes VTd engine based upon EDKII_VTD_INFO_PPI +# and provide DMA protection in PEI. +# +# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D IntelVTdPmrPei + MODULE_UNI_FILE =3D IntelVTdPmrPei.uni + FILE_GUID =3D F906769F-4AED-4A0D-8C7C-FF21B9D1051A + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IntelVTdPmrInitialize + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + IntelVTdPmrPei.c + IntelVTdPmrPei.h + IntelVTdPmr.c + DmarTable.c + VtdReg.c + +[LibraryClasses] + DebugLib + BaseMemoryLib + BaseLib + PeimEntryPoint + PeiServicesLib + HobLib + IoLib + CacheMaintenanceLib + +[Ppis] + gEdkiiIoMmuPpiGuid ## PRODUCES + gEdkiiVTdInfoPpiGuid ## CONSUMES + gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES + gEfiEndOfPeiSignalPpiGuid ## CONSUMES + +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize ## CONSUMES + gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3 ## CONSUMES + +[Depex] + gEfiPeiMasterBootModePpiGuid AND + gEdkiiVTdInfoPpiGuid + +[UserExtensions.TianoCore."ExtraFiles"] + IntelVTdPmrPeiExtra.uni + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmrPei.uni b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/In= telVTdPmrPei.uni new file mode 100644 index 0000000000..1aecacdc4f --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= ei.uni @@ -0,0 +1,14 @@ +// /** @file +// IntelVTdPmrPei Module Localized Abstract and Description Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Intel VTd PMR PEI= Driver." + +#string STR_MODULE_DESCRIPTION #language en-US "This driver initi= alizes VTd engine based upon EDKII_VTD_INFO_PPI and provide DMA protection = to device in PEI." + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/Intel= VTdPmrPeiExtra.uni b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrP= ei/IntelVTdPmrPeiExtra.uni new file mode 100644 index 0000000000..080842f4c3 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrP= eiExtra.uni @@ -0,0 +1,14 @@ +// /** @file +// IntelVTdPmrPei Localized Strings and Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Intel VTd PMR PEI Driver" + + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSampl= ePei/PlatformVTdInfoSamplePei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/V= Td/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf new file mode 100644 index 0000000000..dacfdf5e10 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePei.inf @@ -0,0 +1,48 @@ +## @file +# Platform VTd Info Sample PEI driver. +# +# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformVTdInfoSamplePei + MODULE_UNI_FILE =3D PlatformVTdInfoSamplePei.uni + FILE_GUID =3D 839EB770-5C64-4EED-A6D5-EC515B2B2B23 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformVTdInfoSampleInitialize + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# +# + +[Sources] + PlatformVTdInfoSamplePei.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[LibraryClasses] + PeimEntryPoint + PeiServicesLib + DebugLib + PciLib + IoLib + +[Ppis] + gEdkiiVTdInfoPpiGuid ## PRODUCES + +[Depex] + gEfiPeiMasterBootModePpiGuid + +[UserExtensions.TianoCore."ExtraFiles"] + PlatformVTdInfoSamplePeiExtra.uni + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSampl= ePei/PlatformVTdInfoSamplePei.uni b/Silicon/Intel/IntelSiliconPkg/Feature/V= Td/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.uni new file mode 100644 index 0000000000..3662fe5bfb --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePei.uni @@ -0,0 +1,14 @@ +// /** @file +// PlatformVTdInfoSamplePei Module Localized Abstract and Description Cont= ent +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Platform VTd Info= PEI Driver." + +#string STR_MODULE_DESCRIPTION #language en-US "This driver provi= des sample on how to produce Platform VTd Info PPI." + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSampl= ePei/PlatformVTdInfoSamplePeiExtra.uni b/Silicon/Intel/IntelSiliconPkg/Feat= ure/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePeiExtra.uni new file mode 100644 index 0000000000..ddfa629169 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/Pl= atformVTdInfoSamplePeiExtra.uni @@ -0,0 +1,14 @@ +// /** @file +// PlatformVTdInfoSamplePei Localized Strings and Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Platform VTd Info Sample PEI Driver" + + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe= /PlatformVTdSampleDxe.inf b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Platf= ormVTdSampleDxe/PlatformVTdSampleDxe.inf new file mode 100644 index 0000000000..be18284ed4 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/Platfo= rmVTdSampleDxe.inf @@ -0,0 +1,56 @@ +## @file +# Platform VTd Sample driver. +# +# Note: This module should only be used for dev/debug purposes. +# It MUST never be used for production builds. +# +# Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PlatformVTdSampleDxe + MODULE_UNI_FILE =3D PlatformVTdSampleDxe.uni + FILE_GUID =3D 5DFAE03E-9C19-4996-85BF-65297BD4137F + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PlatformVTdSampleInitialize + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 EBC +# +# + +[Sources] + PlatformVTdSampleDxe.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[LibraryClasses] + DebugLib + UefiDriverEntryPoint + UefiBootServicesTableLib + BaseLib + IoLib + PciSegmentLib + BaseMemoryLib + MemoryAllocationLib + DevicePathLib + +[Protocols] + gEdkiiPlatformVTdPolicyProtocolGuid ## PRODUCES + gEfiPciIoProtocolGuid ## CONSUMES + +[Depex] + gEfiPciRootBridgeIoProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + PlatformVTdSampleDxeExtra.uni + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe= /PlatformVTdSampleDxe.uni b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Platf= ormVTdSampleDxe/PlatformVTdSampleDxe.uni new file mode 100644 index 0000000000..7e9963d696 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/Platfo= rmVTdSampleDxe.uni @@ -0,0 +1,14 @@ +// /** @file +// PlatformVTdSampleDxe Module Localized Abstract and Description Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "Platform VTd Samp= le DXE Driver." + +#string STR_MODULE_DESCRIPTION #language en-US "This driver provi= des sample on how to produce Platform VTd policy protocol." + diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe= /PlatformVTdSampleDxeExtra.uni b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/= PlatformVTdSampleDxe/PlatformVTdSampleDxeExtra.uni new file mode 100644 index 0000000000..e2726f4a68 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/Platfo= rmVTdSampleDxeExtra.uni @@ -0,0 +1,14 @@ +// /** @file +// PlatformVTdSampleDxe Localized Strings and Content +// +// Copyright (c) 2017, Intel Corporation. All rights reserved.
+// +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + +#string STR_PROPERTIES_MODULE_NAME +#language en-US +"Platform VTd Sample DXE Driver" + + diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeFmp.h b/Si= licon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeFmp.h new file mode 100644 index 0000000000..b6ee34d65d --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeFmp.h @@ -0,0 +1,15 @@ +/** @file + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __MICROCODE_FMP_GUID_H__ +#define __MICROCODE_FMP_GUID_H__ + +#define MICROCODE_FMP_IMAGE_TYPE_ID_GUID { 0x96d4fdcd, 0x1502, 0x424d, { 0= x9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } } + +extern EFI_GUID gMicrocodeFmpImageTypeIdGuid; + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Firmwar= eInterfaceTable.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/= FirmwareInterfaceTable.h new file mode 100644 index 0000000000..3a8dd24dea --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareInterf= aceTable.h @@ -0,0 +1,69 @@ +/** @file + FirmwareInterfaceTable (FIT) related definitions. + + @todo update document/spec reference + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FIRMWARE_INTERFACE_TABLE_H__ +#define __FIRMWARE_INTERFACE_TABLE_H__ + +// +// FIT Entry type definitions +// +#define FIT_TYPE_00_HEADER 0x00 +#define FIT_TYPE_01_MICROCODE 0x01 +#define FIT_TYPE_02_STARTUP_ACM 0x02 +#define FIT_TYPE_07_BIOS_STARTUP_MODULE 0x07 +#define FIT_TYPE_08_TPM_POLICY 0x08 +#define FIT_TYPE_09_BIOS_POLICY 0x09 +#define FIT_TYPE_0A_TXT_POLICY 0x0A +#define FIT_TYPE_0B_KEY_MANIFEST 0x0B +#define FIT_TYPE_0C_BOOT_POLICY_MANIFEST 0x0C +#define FIT_TYPE_10_CSE_SECURE_BOOT 0x10 +#define FIT_TYPE_2D_TXTSX_POLICY 0x2D +#define FIT_TYPE_2F_JMP_DEBUG_POLICY 0x2F +#define FIT_TYPE_7F_SKIP 0x7F + +#define FIT_POINTER_ADDRESS 0xFFFFFFC0 ///< Fixed address = at 4G - 40h + +#define FIT_TYPE_VERSION 0x0100 + +#define FIT_TYPE_00_SIGNATURE SIGNATURE_64 ('_', 'F', 'I', 'T', '_', ' ',= ' ', ' ') + +#pragma pack(1) + +typedef struct { + /** + Address is the base address of the firmware component + must be aligned on 16 byte boundary + **/ + UINT64 Address; + UINT8 Size[3]; ///< Size is the span of the component in multiple of = 16 bytes + UINT8 Reserved; ///< Reserved must be set to 0 + /** + Component's version number in binary coded decimal (BCD) format. + For the FIT header entry, the value in this field will indicate the re= vision + number of the FIT data structure. The upper byte of the revision field + indicates the major revision and the lower byte indicates the minor re= vision. + **/ + UINT16 Version; + UINT8 Type : 7; ///< FIT types 0x00 to 0x7F + /// + /// Checksum Valid indicates whether component has valid checksum. + /// + UINT8 C_V : 1; + /** + Component's checksum. The modulo sum of all the bytes in the component= and + the value in this field (Chksum) must add up to zero. This field is on= ly + valid if the C_V flag is non-zero. + **/ + UINT8 Chksum; +} FIRMWARE_INTERFACE_TABLE_ENTRY; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Firmwar= eVersionInfo.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Fir= mwareVersionInfo.h new file mode 100644 index 0000000000..b30bc3f9e7 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareVersio= nInfo.h @@ -0,0 +1,54 @@ +/** @file + Intel Firmware Version Info (FVI) related definitions. + + @todo update document/spec reference + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +@par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 201= 5-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.= 0.pdf + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Compone= nt Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version= String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries i= n this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRe= gion.h b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion= .h new file mode 100644 index 0000000000..f512535803 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion.h @@ -0,0 +1,149 @@ +/** @file + IGD OpRegion definition from Intel Integrated Graphics Device OpRegion + Specification. + + https://01.org/sites/default/files/documentation/skl_opregion_rev0p5.pdf + + Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _IGD_OPREGION_H_ +#define _IGD_OPREGION_H_ + +#define IGD_OPREGION_HEADER_SIGN "IntelGraphicsMem" +#define IGD_OPREGION_HEADER_MBOX1 BIT0 +#define IGD_OPREGION_HEADER_MBOX2 BIT1 +#define IGD_OPREGION_HEADER_MBOX3 BIT2 +#define IGD_OPREGION_HEADER_MBOX4 BIT3 +#define IGD_OPREGION_HEADER_MBOX5 BIT4 + +/** + OpRegion structures: + Sub-structures define the different parts of the OpRegion followed by the + main structure representing the entire OpRegion. + + @note These structures are packed to 1 byte offsets because the exact + data location is required by the supporting design specification due to + the fact that the data is used by ASL and Graphics driver code compiled + separately. +**/ +#pragma pack(1) +/// +/// OpRegion Mailbox 0 Header structure. The OpRegion Header is used to +/// identify a block of memory as the graphics driver OpRegion. +/// Offset 0x0, Size 0x100 +/// +typedef struct { + CHAR8 SIGN[0x10]; ///< Offset 0x00 OpRegion Signature + UINT32 SIZE; ///< Offset 0x10 OpRegion Size + UINT32 OVER; ///< Offset 0x14 OpRegion Structure Version + UINT8 SVER[0x20]; ///< Offset 0x18 System BIOS Build Version + UINT8 VVER[0x10]; ///< Offset 0x38 Video BIOS Build Version + UINT8 GVER[0x10]; ///< Offset 0x48 Graphic Driver Build Version + UINT32 MBOX; ///< Offset 0x58 Supported Mailboxes + UINT32 DMOD; ///< Offset 0x5C Driver Model + UINT32 PCON; ///< Offset 0x60 Platform Configuration + CHAR16 DVER[0x10]; ///< Offset 0x64 GOP Version + UINT8 RM01[0x7C]; ///< Offset 0x84 Reserved Must be zero +} IGD_OPREGION_HEADER; + +/// +/// OpRegion Mailbox 1 - Public ACPI Methods +/// Offset 0x100, Size 0x100 +/// +typedef struct { + UINT32 DRDY; ///< Offset 0x100 Driver Readiness + UINT32 CSTS; ///< Offset 0x104 Status + UINT32 CEVT; ///< Offset 0x108 Current Event + UINT8 RM11[0x14]; ///< Offset 0x10C Reserved Must be Zero + UINT32 DIDL[8]; ///< Offset 0x120 Supported Display Devices ID List + UINT32 CPDL[8]; ///< Offset 0x140 Currently Attached Display Devic= es List + UINT32 CADL[8]; ///< Offset 0x160 Currently Active Display Devices= List + UINT32 NADL[8]; ///< Offset 0x180 Next Active Devices List + UINT32 ASLP; ///< Offset 0x1A0 ASL Sleep Time Out + UINT32 TIDX; ///< Offset 0x1A4 Toggle Table Index + UINT32 CHPD; ///< Offset 0x1A8 Current Hotplug Enable Indicator + UINT32 CLID; ///< Offset 0x1AC Current Lid State Indicator + UINT32 CDCK; ///< Offset 0x1B0 Current Docking State Indicator + UINT32 SXSW; ///< Offset 0x1B4 Display Switch Notification on S= x State Resume + UINT32 EVTS; ///< Offset 0x1B8 Events supported by ASL + UINT32 CNOT; ///< Offset 0x1BC Current OS Notification + UINT32 NRDY; ///< Offset 0x1C0 Driver Status + UINT8 DID2[0x1C]; ///< Offset 0x1C4 Extended Supported Devices ID Li= st (DOD) + UINT8 CPD2[0x1C]; ///< Offset 0x1E0 Extended Attached Display Device= s List + UINT8 RM12[4]; ///< Offset 0x1FC - 0x1FF Reserved Must be zero +} IGD_OPREGION_MBOX1; + +/// +/// OpRegion Mailbox 2 - Software SCI Interface +/// Offset 0x200, Size 0x100 +/// +typedef struct { + UINT32 SCIC; ///< Offset 0x200 Software SCI Command / Status / = Data + UINT32 PARM; ///< Offset 0x204 Software SCI Parameters + UINT32 DSLP; ///< Offset 0x208 Driver Sleep Time Out + UINT8 RM21[0xF4]; ///< Offset 0x20C - 0x2FF Reserved Must be zero +} IGD_OPREGION_MBOX2; + +/// +/// OpRegion Mailbox 3 - BIOS/Driver Notification - ASLE Support +/// Offset 0x300, Size 0x100 +/// +typedef struct { + UINT32 ARDY; ///< Offset 0x300 Driver Readiness + UINT32 ASLC; ///< Offset 0x304 ASLE Interrupt Command / Status + UINT32 TCHE; ///< Offset 0x308 Technology Enabled Indicator + UINT32 ALSI; ///< Offset 0x30C Current ALS Luminance Reading + UINT32 BCLP; ///< Offset 0x310 Requested Backlight Brightness + UINT32 PFIT; ///< Offset 0x314 Panel Fitting State or Request + UINT32 CBLV; ///< Offset 0x318 Current Brightness Level + UINT16 BCLM[0x14]; ///< Offset 0x31C Backlight Brightness Levels Duty= Cycle Mapping Table + UINT32 CPFM; ///< Offset 0x344 Current Panel Fitting Mode + UINT32 EPFM; ///< Offset 0x348 Enabled Panel Fitting Modes + UINT8 PLUT[0x4A]; ///< Offset 0x34C Panel Look Up Table & Identifier + UINT32 PFMB; ///< Offset 0x396 PWM Frequency and Minimum Bright= ness + UINT32 CCDV; ///< Offset 0x39A Color Correction Default Values + UINT32 PCFT; ///< Offset 0x39E Power Conservation Features + UINT32 SROT; ///< Offset 0x3A2 Supported Rotation Angles + UINT32 IUER; ///< Offset 0x3A6 Intel Ultrabook(TM) Event Regist= er + UINT64 FDSS; ///< Offset 0x3AA DSS Buffer address allocated for= IFFS feature + UINT32 FDSP; ///< Offset 0x3B2 Size of DSS buffer + UINT32 STAT; ///< Offset 0x3B6 State Indicator + UINT64 RVDA; ///< Offset 0x3BA Physical address of Raw VBT data= . Added from Spec Version 0.90 to support VBT greater than 6KB. + UINT32 RVDS; ///< Offset 0x3C2 Size of Raw VBT data. Added from= Spec Version 0.90 to support VBT greater than 6KB. + UINT8 RM32[0x3A]; ///< Offset 0x3C6 - 0x3FF Reserved Must be zero. +} IGD_OPREGION_MBOX3; + +/// +/// OpRegion Mailbox 4 - VBT Video BIOS Table +/// Offset 0x400, Size 0x1800 +/// +typedef struct { + UINT8 RVBT[0x1800]; ///< Offset 0x400 - 0x1BFF Raw VBT Data +} IGD_OPREGION_MBOX4; + +/// +/// OpRegion Mailbox 5 - BIOS/Driver Notification - Data storage BIOS to D= river data sync +/// Offset 0x1C00, Size 0x400 +/// +typedef struct { + UINT32 PHED; ///< Offset 0x1C00 Panel Header + UINT8 BDDC[0x100]; ///< Offset 0x1C04 Panel EDID (DDC data) + UINT8 RM51[0x2FC]; ///< Offset 0x1D04 - 0x1FFF Reserved Must be zero +} IGD_OPREGION_MBOX5; + +/// +/// IGD OpRegion Structure +/// +typedef struct { + IGD_OPREGION_HEADER Header; ///< OpRegion header (Offset 0x0, Size 0x100) + IGD_OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods (Offset = 0x100, Size 0x100) + IGD_OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Interface (Offs= et 0x200, Size 0x100) + IGD_OPREGION_MBOX3 MBox3; ///< Mailbox 3: BIOS to Driver Notification = (Offset 0x300, Size 0x100) + IGD_OPREGION_MBOX4 MBox4; ///< Mailbox 4: Video BIOS Table (VBT) (Offs= et 0x400, Size 0x1800) + IGD_OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification = Extension (Offset 0x1C00, Size 0x400) +} IGD_OPREGION_STRUCTURE; +#pragma pack() + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h b= /Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h new file mode 100644 index 0000000000..b2f745bd47 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/Vtd.h @@ -0,0 +1,355 @@ +/** @file + The definition for VTD register. + It is defined in "Intel VT for Direct IO Architecture Specification". + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __VTD_REG_H__ +#define __VTD_REG_H__ + +#pragma pack(1) + +// +// Translation Structure Formats +// +#define VTD_ROOT_ENTRY_NUMBER 256 +#define VTD_CONTEXT_ENTRY_NUMBER 256 + +typedef union { + struct { + UINT32 Present:1; + UINT32 Reserved_1:11; + UINT32 ContextTablePointerLo:20; + UINT32 ContextTablePointerHi:32; + + UINT64 Reserved_64; + } Bits; + struct { + UINT64 Uint64Lo; + UINT64 Uint64Hi; + } Uint128; +} VTD_ROOT_ENTRY; + +typedef union { + struct { + UINT32 LowerPresent:1; + UINT32 Reserved_1:11; + UINT32 LowerContextTablePointerLo:20; + UINT32 LowerContextTablePointerHi:32; + + UINT32 UpperPresent:1; + UINT32 Reserved_65:11; + UINT32 UpperContextTablePointerLo:20; + UINT32 UpperContextTablePointerHi:32; + } Bits; + struct { + UINT64 Uint64Lo; + UINT64 Uint64Hi; + } Uint128; +} VTD_EXT_ROOT_ENTRY; + +typedef union { + struct { + UINT32 Present:1; + UINT32 FaultProcessingDisable:1; + UINT32 TranslationType:2; + UINT32 Reserved_4:8; + UINT32 SecondLevelPageTranslationPointerLo:20; + UINT32 SecondLevelPageTranslationPointerHi:32; + + UINT32 AddressWidth:3; + UINT32 Ignored_67:4; + UINT32 Reserved_71:1; + UINT32 DomainIdentifier:16; + UINT32 Reserved_88:8; + UINT32 Reserved_96:32; + } Bits; + struct { + UINT64 Uint64Lo; + UINT64 Uint64Hi; + } Uint128; +} VTD_CONTEXT_ENTRY; + +typedef union { + struct { + UINT32 Present:1; + UINT32 FaultProcessingDisable:1; + UINT32 TranslationType:3; + UINT32 ExtendedMemoryType:3; + UINT32 DeferredInvalidateEnable:1; + UINT32 PageRequestEnable:1; + UINT32 NestedTranslationEnable:1; + UINT32 PASIDEnable:1; + UINT32 SecondLevelPageTranslationPointerLo:20; + UINT32 SecondLevelPageTranslationPointerHi:32; + + UINT32 AddressWidth:3; + UINT32 PageGlobalEnable:1; + UINT32 NoExecuteEnable:1; + UINT32 WriteProtectEnable:1; + UINT32 CacheDisable:1; + UINT32 ExtendedMemoryTypeEnable:1; + UINT32 DomainIdentifier:16; + UINT32 SupervisorModeExecuteProtection:1; + UINT32 ExtendedAccessedFlagEnable:1; + UINT32 ExecuteRequestsEnable:1; + UINT32 SecondLevelExecuteEnable:1; + UINT32 Reserved_92:4; + UINT32 PageAttributeTable0:3; + UINT32 Reserved_Pat0:1; + UINT32 PageAttributeTable1:3; + UINT32 Reserved_Pat1:1; + UINT32 PageAttributeTable2:3; + UINT32 Reserved_Pat2:1; + UINT32 PageAttributeTable3:3; + UINT32 Reserved_Pat3:1; + UINT32 PageAttributeTable4:3; + UINT32 Reserved_Pat4:1; + UINT32 PageAttributeTable5:3; + UINT32 Reserved_Pat5:1; + UINT32 PageAttributeTable6:3; + UINT32 Reserved_Pat6:1; + UINT32 PageAttributeTable7:3; + UINT32 Reserved_Pat7:1; + + UINT32 PASIDTableSize:4; + UINT32 Reserved_132:8; + UINT32 PASIDTablePointerLo:20; + UINT32 PASIDTablePointerHi:32; + + UINT32 Reserved_192:12; + UINT32 PASIDStateTablePointerLo:20; + UINT32 PASIDStateTablePointerHi:32; + } Bits; + struct { + UINT64 Uint64_1; + UINT64 Uint64_2; + UINT64 Uint64_3; + UINT64 Uint64_4; + } Uint256; +} VTD_EXT_CONTEXT_ENTRY; + +typedef union { + struct { + UINT32 Present:1; + UINT32 Reserved_1:2; + UINT32 PageLevelCacheDisable:1; + UINT32 PageLevelWriteThrough:1; + UINT32 Reserved_5:6; + UINT32 SupervisorRequestsEnable:1; + UINT32 FirstLevelPageTranslationPointerLo:20; + UINT32 FirstLevelPageTranslationPointerHi:32; + } Bits; + UINT64 Uint64; +} VTD_PASID_ENTRY; + +typedef union { + struct { + UINT32 Reserved_0:32; + UINT32 ActiveReferenceCount:16; + UINT32 Reserved_48:15; + UINT32 DeferredInvalidate:1; + } Bits; + UINT64 Uint64; +} VTD_PASID_STATE_ENTRY; + +typedef union { + struct { + UINT32 Present:1; + UINT32 ReadWrite:1; + UINT32 UserSupervisor:1; + UINT32 PageLevelWriteThrough:1; + UINT32 PageLevelCacheDisable:1; + UINT32 Accessed:1; + UINT32 Dirty:1; + UINT32 PageSize:1; // It is PageAttribute:1 for 4K page entry + UINT32 Global:1; + UINT32 Ignored_9:1; + UINT32 ExtendedAccessed:1; + UINT32 Ignored_11:1; + // NOTE: There is PageAttribute:1 as bit12 for 1G page entry and 2M pa= ge entry + UINT32 AddressLo:20; + UINT32 AddressHi:20; + UINT32 Ignored_52:11; + UINT32 ExecuteDisable:1; + } Bits; + UINT64 Uint64; +} VTD_FIRST_LEVEL_PAGING_ENTRY; + +typedef union { + struct { + UINT32 Read:1; + UINT32 Write:1; + UINT32 Execute:1; + UINT32 ExtendedMemoryType:3; + UINT32 IgnorePAT:1; + UINT32 PageSize:1; + UINT32 Ignored_8:3; + UINT32 Snoop:1; + UINT32 AddressLo:20; + UINT32 AddressHi:20; + UINT32 Ignored_52:10; + UINT32 TransientMapping:1; + UINT32 Ignored_63:1; + } Bits; + UINT64 Uint64; +} VTD_SECOND_LEVEL_PAGING_ENTRY; + +// +// Register Descriptions +// +#define R_VER_REG 0x00 +#define R_CAP_REG 0x08 +#define B_CAP_REG_RWBF BIT4 +#define R_ECAP_REG 0x10 +#define R_GCMD_REG 0x18 +#define B_GMCD_REG_WBF BIT27 +#define B_GMCD_REG_SRTP BIT30 +#define B_GMCD_REG_TE BIT31 +#define R_GSTS_REG 0x1C +#define B_GSTS_REG_WBF BIT27 +#define B_GSTS_REG_RTPS BIT30 +#define B_GSTS_REG_TE BIT31 +#define R_RTADDR_REG 0x20 +#define R_CCMD_REG 0x28 +#define B_CCMD_REG_CIRG_MASK (BIT62|BIT61) +#define V_CCMD_REG_CIRG_GLOBAL BIT61 +#define V_CCMD_REG_CIRG_DOMAIN BIT62 +#define V_CCMD_REG_CIRG_DEVICE (BIT62|BIT61) +#define B_CCMD_REG_ICC BIT63 +#define R_FSTS_REG 0x34 +#define R_FECTL_REG 0x38 +#define R_FEDATA_REG 0x3C +#define R_FEADDR_REG 0x40 +#define R_FEUADDR_REG 0x44 +#define R_AFLOG_REG 0x58 + +#define R_IVA_REG 0x00 // + IRO +#define B_IVA_REG_AM_MASK (BIT0|BIT1|BIT2|BIT3|BIT4|BIT5) +#define B_IVA_REG_AM_4K 0 // 1 page +#define B_IVA_REG_AM_2M 9 // 2M page +#define B_IVA_REG_IH BIT6 +#define R_IOTLB_REG 0x08 // + IRO +#define B_IOTLB_REG_IIRG_MASK (BIT61|BIT60) +#define V_IOTLB_REG_IIRG_GLOBAL BIT60 +#define V_IOTLB_REG_IIRG_DOMAIN BIT61 +#define V_IOTLB_REG_IIRG_PAGE (BIT61|BIT60) +#define B_IOTLB_REG_IVT BIT63 + +#define R_FRCD_REG 0x00 // + FRO + +#define R_PMEN_ENABLE_REG 0x64 +#define R_PMEN_LOW_BASE_REG 0x68 +#define R_PMEN_LOW_LIMITE_REG 0x6C +#define R_PMEN_HIGH_BASE_REG 0x70 +#define R_PMEN_HIGH_LIMITE_REG 0x78 + +typedef union { + struct { + UINT8 ND:3; // Number of domains supported + UINT8 AFL:1; // Advanced Fault Logging + UINT8 RWBF:1; // Required Write-Buffer Flushing + UINT8 PLMR:1; // Protected Low-Memory Region + UINT8 PHMR:1; // Protected High-Memory Region + UINT8 CM:1; // Caching Mode + + UINT8 SAGAW:5; // Supported Adjusted Guest Address Widths + UINT8 Rsvd_13:3; + + UINT8 MGAW:6; // Maximum Guest Address Width + UINT8 ZLR:1; // Zero Length Read + UINT8 Rsvd_23:1; + + UINT16 FRO:10; // Fault-recording Register offset + UINT16 SLLPS:4; // Second Level Large Page Support + UINT16 Rsvd_38:1; + UINT16 PSI:1; // Page Selective Invalidation + + UINT8 NFR:8; // Number of Fault-recording Registers + + UINT8 MAMV:6; // Maximum Address Mask Value + UINT8 DWD:1; // Write Draining + UINT8 DRD:1; // Read Draining + + UINT8 FL1GP:1; // First Level 1-GByte Page Support + UINT8 Rsvd_57:2; + UINT8 PI:1; // Posted Interrupts Support + UINT8 Rsvd_60:4; + } Bits; + UINT64 Uint64; +} VTD_CAP_REG; + +typedef union { + struct { + UINT8 C:1; // Page-walk Coherency + UINT8 QI:1; // Queued Invalidation support + UINT8 DT:1; // Device-TLB support + UINT8 IR:1; // Interrupt Remapping support + UINT8 EIM:1; // Extended Interrupt Mode + UINT8 Rsvd_5:1; + UINT8 PT:1; // Pass Through + UINT8 SC:1; // Snoop Control + + UINT16 IRO:10; // IOTLB Register Offset + UINT16 Rsvd_18:2; + UINT16 MHMV:4; // Maximum Handle Mask Value + + UINT8 ECS:1; // Extended Context Support + UINT8 MTS:1; // Memory Type Support + UINT8 NEST:1; // Nested Translation Support + UINT8 DIS:1; // Deferred Invalidate Support + UINT8 PASID:1; // Process Address Space ID Support + UINT8 PRS:1; // Page Request Support + UINT8 ERS:1; // Execute Request Support + UINT8 SRS:1; // Supervisor Request Support + + UINT32 Rsvd_32:1; + UINT32 NWFS:1; // No Write Flag Support + UINT32 EAFS:1; // Extended Accessed Flag Support + UINT32 PSS:5; // PASID Size Supported + UINT32 Rsvd_40:24; + } Bits; + UINT64 Uint64; +} VTD_ECAP_REG; + +typedef union { + struct { + UINT32 Rsvd_0:12; + UINT32 FILo:20; // FaultInfo + UINT32 FIHi:32; // FaultInfo + + UINT32 SID:16; // Source Identifier + UINT32 Rsvd_80:13; + UINT32 PRIV:1; // Privilege Mode Requested + UINT32 EXE:1; // Execute Permission Requested + UINT32 PP:1; // PASID Present + + UINT32 FR:8; // Fault Reason + UINT32 PV:20; // PASID Value + UINT32 AT:2; // Address Type + UINT32 T:1; // Type (0: Write, 1: Read) + UINT32 F:1; // Fault + } Bits; + UINT64 Uint64[2]; +} VTD_FRCD_REG; + +typedef union { + struct { + UINT8 Function:3; + UINT8 Device:5; + UINT8 Bus; + } Bits; + struct { + UINT8 ContextIndex; + UINT8 RootIndex; + } Index; + UINT16 Uint16; +} VTD_SOURCE_ID; + +#pragma pack() + +#endif + diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/MicrocodeFlashAc= cessLib.h b/Silicon/Intel/IntelSiliconPkg/Include/Library/MicrocodeFlashAcc= essLib.h new file mode 100644 index 0000000000..f991945c23 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/MicrocodeFlashAccessLib= .h @@ -0,0 +1,33 @@ +/** @file + Microcode flash device access library. + + Copyright (c) 2016, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#ifndef __MICROCODE_FLASH_ACCESS_LIB_H__ +#define __MICROCODE_FLASH_ACCESS_LIB_H__ + +/** + Perform microcode write opreation. + + @param[in] FlashAddress The address of flash device to be accessed. + @param[in] Buffer The pointer to the data buffer. + @param[in] Length The length of data buffer in bytes. + + @retval EFI_SUCCESS The operation returns successfully. + @retval EFI_WRITE_PROTECTED The flash device is read only. + @retval EFI_UNSUPPORTED The flash device access is unsupported. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. +**/ +EFI_STATUS +EFIAPI +MicrocodeFlashWrite ( + IN EFI_PHYSICAL_ADDRESS FlashAddress, + IN VOID *Buffer, + IN UINTN Length + ); + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Ppi/VtdInfo.h b/Silicon/= Intel/IntelSiliconPkg/Include/Ppi/VtdInfo.h new file mode 100644 index 0000000000..f91dbc0381 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Ppi/VtdInfo.h @@ -0,0 +1,37 @@ +/** @file + The definition for VTD information PPI. + + This is a lightweight VTd information report in PEI phase. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __VTD_INFO_PPI_H__ +#define __VTD_INFO_PPI_H__ + +#include + +#define EDKII_VTD_INFO_PPI_GUID \ + { \ + 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x67, 0xaf, 0x2b, 0x25, 0x= 68, 0x4a } \ + } + +// +// VTD info PPI just use same data structure as DMAR table. +// +// The reported information must include what is needed in PEI phase, e.g. +// the VTd engine (such as DRHD) +// the reserved DMA address in PEI for eary graphic (such as RMRR for gr= aphic UMA) +// +// The reported information can be and might be a subset of full DMAR tabl= e, e.g. +// if some data is not avaiable (such as ANDD), +// if some data is not needed (such as RMRR for legacy USB). +// +typedef EFI_ACPI_DMAR_HEADER EDKII_VTD_INFO_PPI; + +extern EFI_GUID gEdkiiVTdInfoPpiGuid; + +#endif + diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Protocol/PlatformVtdPoli= cy.h b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h new file mode 100644 index 0000000000..acab432ede --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Protocol/PlatformVtdPolicy.h @@ -0,0 +1,143 @@ +/** @file + The definition for platform VTD policy. + + Copyright (c) 2017, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __PLATFORM_VTD_POLICY_PROTOCOL_H__ +#define __PLATFORM_VTD_POLICY_PROTOCOL_H__ + +#include +#include + +#define EDKII_PLATFORM_VTD_POLICY_PROTOCOL_GUID \ + { \ + 0x3d17e448, 0x466, 0x4e20, { 0x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xe= e, 0x22 } \ + } + +typedef struct _EDKII_PLATFORM_VTD_POLICY_PROTOCOL EDKII_PLATFORM_VTD_POL= ICY_PROTOCOL; + +#define EDKII_PLATFORM_VTD_POLICY_PROTOCOL_REVISION 0x00010000 + +typedef struct { + UINT16 Segment; + VTD_SOURCE_ID SourceId; +} EDKII_PLATFORM_VTD_DEVICE_INFO; + +/** + Get the VTD SourceId from the device handler. + This function is required for non PCI device handler. + + Pseudo-algo in Intel VTd driver: + Status =3D PlatformGetVTdDeviceId (); + if (EFI_ERROR(Status)) { + if (DeviceHandle is PCI) { + Get SourceId from Bus/Device/Function + } else { + return EFI_UNSUPPORTED + } + } + Get VTd engine by Segment/Bus/Device/Function. + + @param[in] This The protocol instance pointer. + @param[in] DeviceHandle Device Identifier in UEFI. + @param[out] DeviceInfo DeviceInfo for indentify the VTd engin= e in ACPI Table + and the VTd page entry. + + @retval EFI_SUCCESS The VtdIndex and SourceId are returned. + @retval EFI_INVALID_PARAMETER DeviceHandle is not a valid handler. + @retval EFI_INVALID_PARAMETER DeviceInfo is NULL. + @retval EFI_NOT_FOUND The Segment or SourceId information is NOT= found. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PLATFORM_VTD_POLICY_GET_DEVICE_ID) ( + IN EDKII_PLATFORM_VTD_POLICY_PROTOCOL *This, + IN EFI_HANDLE DeviceHandle, + OUT EDKII_PLATFORM_VTD_DEVICE_INFO *DeviceInfo + ); + +#pragma pack(1) + +typedef struct { + // + // The segment number of the device + // + UINT16 SegmentNumber; + // + // Device scope definition in DMAR table + // + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER DeviceScope; + // + // Pci path definition in DMAR table + // +//EFI_ACPI_DMAR_PCI_PATH PciPath[]; +} EDKII_PLATFORM_VTD_DEVICE_SCOPE; + +typedef struct { + UINT16 VendorId; + UINT16 DeviceId; + UINT8 RevisionId; + UINT16 SubsystemVendorId; + UINT16 SubsystemDeviceId; +} EDKII_PLATFORM_VTD_PCI_DEVICE_ID; + +#define EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_END 0 +#define EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_DEVICE_SCOPE 1 +#define EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_PCI_DEVICE_ID 2 + +typedef struct { + // + // EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO_TYPE_xxx defined above. + // + UINT8 Type; + // + // The length of the full data structure including EDKII_PLATFORM_VTD_EX= CEPTION_DEVICE_INFO and Data. + // + UINT8 Length; + // + // Data can be EDKII_PLATFORM_VTD_DEVICE_SCOPE or EDKII_PLATFORM_VTD_PCI= _DEVICE_ID + // +//UINT8 Data[Length - sizeof(EDKII_PLATFORM_VTD_EXCEPTION_DEVI= CE_INFO)]; +} EDKII_PLATFORM_VTD_EXCEPTION_DEVICE_INFO; + +#pragma pack() + + +/** + Get a list of the exception devices. + + The VTd driver should always set ALLOW for the device in this list. + + @param[in] This The protocol instance pointer. + @param[out] DeviceInfoCount The count of the list of DeviceInfo. + @param[out] DeviceInfo A callee allocated buffer to hold a li= st of DeviceInfo. + Each DeviceInfo pointer points to EDKI= I_PLATFORM_VTD_EXCEPTION_DEVICE_INFO. + + @retval EFI_SUCCESS The DeviceInfoCount and DeviceInfo are ret= urned. + @retval EFI_INVALID_PARAMETER DeviceInfoCount is NULL, or DeviceInfo is = NULL. + @retval EFI_UNSUPPORTED This function is not supported. + +**/ +typedef +EFI_STATUS +(EFIAPI *EDKII_PLATFORM_VTD_POLICY_GET_EXCEPTION_DEVICE_LIST) ( + IN EDKII_PLATFORM_VTD_POLICY_PROTOCOL *This, + OUT UINTN *DeviceInfoCount, + OUT VOID **DeviceInfo + ); + +struct _EDKII_PLATFORM_VTD_POLICY_PROTOCOL { + UINT64 Revision; + EDKII_PLATFORM_VTD_POLICY_GET_DEVICE_ID GetDeviceId; + EDKII_PLATFORM_VTD_POLICY_GET_EXCEPTION_DEVICE_LIST GetExceptionDeviceL= ist; +}; + +extern EFI_GUID gEdkiiPlatformVTdPolicyProtocolGuid; + +#endif + diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec new file mode 100644 index 0000000000..fe5bfa0dc6 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -0,0 +1,80 @@ +## @file +# IntelSilicon Package +# +# This package provides common open source Intel silicon modules. +# +# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x00010005 + PACKAGE_NAME =3D IntelSiliconPkg + PACKAGE_GUID =3D F7A58914-FA0E-4F71-BD6A-220FDF824A49 + PACKAGE_VERSION =3D 0.1 + +[Includes] + Include + +[LibraryClasses.IA32, LibraryClasses.X64] + ## @libraryclass Provides services to access Microcode region on flash = device. + # + MicrocodeFlashAccessLib|Include/Library/MicrocodeFlashAccessLib.h + +[Guids] + ## GUID for Package token space + # {A9F8D54E-1107-4F0A-ADD0-4587E7A4A735} + gIntelSiliconPkgTokenSpaceGuid =3D { 0xa9f8d54e, 0x1107, 0x4f0a, { 0xad= , 0xd0, 0x45, 0x87, 0xe7, 0xa4, 0xa7, 0x35 } } + + ## HOB GUID to publish SMBIOS data records from PEI phase + # HOB data format is same as SMBIOS records defined in SMBIOS spec or OE= M defined types + # Generic DXE Library / Driver can locate HOB(s) and add SMBIOS records = into SMBIOS table + gIntelSmbiosDataHobGuid =3D { 0x798e722e, 0x15b2, 0x4e13, { 0x8a= , 0xe9, 0x6b, 0xa3, 0x0f, 0xf7, 0xf1, 0x67 }} + + ## Include/Guid/MicrocodeFmp.h + gMicrocodeFmpImageTypeIdGuid =3D { 0x96d4fdcd, 0x1502, 0x424d, { 0x= 9d, 0x4c, 0x9b, 0x12, 0xd2, 0xdc, 0xae, 0x5c } } + +[Ppis] + gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } + +[Protocols] + gEdkiiPlatformVTdPolicyProtocolGuid =3D { 0x3d17e448, 0x466, 0x4e20, { 0= x99, 0x9f, 0xb2, 0xe1, 0x34, 0x88, 0xee, 0x22 }} + +[PcdsFixedAtBuild, PcdsPatchableInModule] + ## Error code for VTd error.

+ # EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPE= CIFIC | 0x00000000)) =3D 0x02008000
+ # @Prompt Error code for VTd error. + gIntelSiliconPkgTokenSpaceGuid.PcdErrorCodeVTdError|0x02008000|UINT32|0x= 00000005 + +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] + ## This is the GUID of the FFS which contains the Graphics Video BIOS Ta= ble (VBT) + # The VBT content is stored as a RAW section which is consumed by GOP PE= I/UEFI driver. + # The default GUID can be updated by patching or runtime if platform sup= port multiple VBT configurations. + # @Prompt GUID of the FFS which contains the Graphics Video BIOS Table (= VBT) + # { 0x56752da9, 0xde6b, 0x4895, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x6c= , 0x22 } + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid|{ 0xa9, 0x2d,= 0x75, 0x56, 0x6b, 0xde, 0x95, 0x48, 0x88, 0x19, 0x19, 0x45, 0xb6, 0xb7, 0x= 6c, 0x22 }|VOID*|0x00000001 + + ## The mask is used to control VTd behavior.

+ # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If= VTD_INFO_PPI is installed in PEI.) + # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in no= rmal boot. EndOfPEI in S3) + # BIT2: Force no IOMMU access attribute request recording before DMAR t= able is installed. + # @Prompt The policy for VTd driver behavior. + gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x000000= 02 + + ## Declares VTd PEI DMA buffer size.

+ # When this PCD value is referred by platform to calculate the required + # memory size for PEI (InstallPeiMemory), the PMR alignment requirement + # needs be considered to be added with this PCD value for alignment + # adjustment need by AllocateAlignedPages. + # @Prompt The VTd PEI DMA buffer size. + gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSize|0x00400000|UINT32|= 0x00000003 + + ## Declares VTd PEI DMA buffer size for S3.

+ # When this PCD value is referred by platform to calculate the required + # memory size for PEI S3 (InstallPeiMemory), the PMR alignment requirem= ent + # needs be considered to be added with this PCD value for alignment + # adjustment need by AllocateAlignedPages. + # @Prompt The VTd PEI DMA buffer size for S3. + gIntelSiliconPkgTokenSpaceGuid.PcdVTdPeiDmaBufferSizeS3|0x00200000|UINT3= 2|0x00000004 + diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dsc new file mode 100644 index 0000000000..58b5b656ef --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -0,0 +1,86 @@ +## @file +# This package provides common open source Intel silicon modules. +# +# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + PLATFORM_NAME =3D IntelSiliconPkg + PLATFORM_GUID =3D 9B96228E-1155-4967-8E16-D0ED8E1B4297 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/IntelSiliconPkg + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT + SKUID_IDENTIFIER =3D DEFAULT + +[LibraryClasses] + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf + PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.i= nf + PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf + UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompres= sLib.inf + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf + MicrocodeFlashAccessLib|IntelSiliconPkg/Feature/Capsule/Library/Microcod= eFlashAccessLibNull/MicrocodeFlashAccessLibNull.inf + +[LibraryClasses.common.PEIM] + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLib/Pei= ServicesTablePointerLib.inf + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf + + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf + +[LibraryClasses.common.DXE_DRIVER] + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf + + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf + +##########################################################################= ######################### +# +# Components Section - list of the modules and components that will be pro= cessed by compilation +# tools and the EDK II tools to generate PE32/PE32+/C= off image files. +# +# Note: The EDK II DSC file is not used to specify how compiled binary ima= ges get placed +# into firmware volume images. This section is just a list of module= s to compile from +# source into UEFI-compliant binaries. +# It is the FDF file that contains information on combining binary f= iles into firmware +# volume images, whose concept is beyond UEFI and is described in PI= specification. +# Binary modules do not need to be listed in this section, as they s= hould be +# specified in the FDF file. For example: Shell binary (Shell_Full.e= fi), FAT binary (Fat.efi), +# Logo (Logo.bmp), and etc. +# There may also be modules listed in this section that are not requ= ired in the FDF file, +# When a module listed here is excluded from FDF file, then UEFI-com= pliant binary will be +# generated for it, but the binary will not be put into any firmware= volume. +# +##########################################################################= ######################### + +[Components] + IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.inf + IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf + IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdSampleDxe/PlatformVTdSampleDxe.inf + IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf + IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDxe.inf + IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/Micr= ocodeFlashAccessLibNull.inf + +[BuildOptions] + *_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES + diff --git a/Silicon/Intel/IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeS= mbiosDataHobLib.inf b/Silicon/Intel/IntelSiliconPkg/Library/DxeSmbiosDataHo= bLib/DxeSmbiosDataHobLib.inf new file mode 100644 index 0000000000..df3c751f37 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Library/DxeSmbiosDataHobLib/DxeSmbiosDa= taHobLib.inf @@ -0,0 +1,38 @@ +## @file +# Component INF file for the DxeSmbiosDataHob library. +# +# Copyright (c) 2016, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010017 +BASE_NAME =3D DxeSmbiosDataHobLib +FILE_GUID =3D AF55A9B6-2AE6-4B08-8CF7-750B7CBF49D7 +MODULE_TYPE =3D DXE_DRIVER +LIBRARY_CLASS =3D NULL|DXE_DRIVER +CONSTRUCTOR =3D DxeSmbiosDataHobLibConstructor + +[Packages] +MdePkg/MdePkg.dec +IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] +DxeSmbiosDataHobLib.c + +[LibraryClasses] +DebugLib +BaseMemoryLib +MemoryAllocationLib +BaseLib +HobLib +UefiLib + +[Guids] +gIntelSmbiosDataHobGuid ## CONSUMES ## GUID + +[Depex] +gEfiSmbiosProtocolGuid + --=20 2.13.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42116): https://edk2.groups.io/g/devel/message/42116 Mute This Topic: https://groups.io/mt/32005625/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Thu Apr 25 07:30:38 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+42117+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42117+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1560181015; cv=none; d=zoho.com; s=zohoarc; b=TJG27DKniOXkG+1oEnhLMlxMbJFX/ijW+vUOTzmGKps0i+ceBH7CIxh5U7evx8OyJg02gGPX/wX2jKV59Urh0Gl+8WwMSmlsjxXBSrg9znqxymhhUNwloaaR0pM1ch0b/fvqivfBDSIaKJH0y7UdApMcHB6CqrB7bC0hOX84hOU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1560181015; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=pzV1TULBsNxD5FQSS5ctEhrbwNWnz3EjKfkkvK4KVpk=; b=gQEpQz5rqzCyUwRfCHNtbhsQXKTU/HFwKMwP5WFxdfmdbDlRbkDOGKNJXr9iQuMV/NVjhhW98ERwsBL8n8ewDRP3xxMJfn0vhlbH7JFIMkU/lGeFcB0QIVLuFuZj8Metfox1q4QfgQl5kvqn/XkHm+I1EE9WpANg0k1krL/WGWk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+42117+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1560181015537794.2815414640546; Mon, 10 Jun 2019 08:36:55 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by groups.io with SMTP; Mon, 10 Jun 2019 08:36:54 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jun 2019 08:36:54 -0700 X-ExtLoop1: 1 X-Received: from lgao4-mobl1.ccr.corp.intel.com ([10.255.29.227]) by FMSMGA003.fm.intel.com with ESMTP; 10 Jun 2019 08:36:53 -0700 From: "Liming Gao" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty Subject: [edk2-devel] [edk2-platform patch 2/2] Maintainers.txt: Add Maintainers for new added IntelSiliconPkg Date: Mon, 10 Jun 2019 23:36:27 +0800 Message-Id: <20190610153627.16864-3-liming.gao@intel.com> In-Reply-To: <20190610153627.16864-1-liming.gao@intel.com> References: <20190610153627.16864-1-liming.gao@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,liming.gao@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1560181015; bh=YkfAmQbRtq6euMS1qjQDKhgowdrv1NK7NA4zCpGKA8c=; h=Cc:Date:From:Reply-To:Subject:To; b=G4LPDOCcaZnlHNnjKrEAgOWLDIjJJ7CW6O4zCt8Dxi1otCE1mF/nx5PTrh7LuYsdRod AwubG6xSbfTdsOdcB+rdl9h4Rz5Q2NaHT7NY0paxa94w6RWi7eow9qFRmoYdXQyQUaAHb pH+OdRvdaafFdKe6v5DS2bMY8tyJJwRmzfs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1890 Signed-off-by: Liming Gao Cc: Ray Ni Cc: Rangasai V Chaganty Reviewed-by: Ray Ni Reviewed-by: Sai Chaganty =20 --- Maintainers.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index f47fd71025..cb9e15e880 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -105,6 +105,10 @@ M: Ard Biesheuvel M: Leif Lindholm M: Michael D Kinney =20 +Silicon/Intel/IntelSiliconPkg +M: Ray Ni +M: Rangasai V Chaganty + Silicon/Intel/QuarkSocPkg M: Michael D Kinney M: Kelly Steele --=20 2.13.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42117): https://edk2.groups.io/g/devel/message/42117 Mute This Topic: https://groups.io/mt/32005626/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-