From nobody Mon Apr 29 20:11:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41730+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41730+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1559302934; cv=none; d=zoho.com; s=zohoarc; b=W0rjdW61V2oU6mdwC/Lsmsp8GZCejLulnhSnGzf/PveOlxrU/d58rIk20+BVWw6OzHpBXcCxlgWM6N8bYHCLHlyiSKVwNVKhCcuH7K5WWkC4pPoxZ7LDpRjrpW1KYxqPetRyLBa9frcPXcjz0Upd5h5qbnIo6to4Uus+CUG7EAA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559302934; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=MMr3WUBygaROMIqL3/a8jgrThDyOodQR1zqoZxVOGRs=; b=aYieuAw5qTaP+T6wBGAHIUlmwEiUMVLVe7RhZz+UxaXgf9r8YAE/1xWITi9f8vDiSIQ2Xg+6Mg3ijtz6QV+eBfYQBBVuzzFGLMLRNx76qRIJrfc9ypu9a8k7iHE55jsu3m2K3vi+7hSs5gdIVblZ39YecYvjJaEP4ZNq3bOwGHA= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41730+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1559302934631876.5591505214427; Fri, 31 May 2019 04:42:14 -0700 (PDT) Return-Path: X-Received: from mga18.intel.com (mga18.intel.com []) by groups.io with SMTP; Fri, 31 May 2019 04:42:13 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 May 2019 04:42:13 -0700 X-ExtLoop1: 1 X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.240.72]) by fmsmga008.fm.intel.com with ESMTP; 31 May 2019 04:42:11 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: "Chasel, Chiu" , Michael A Kubacki , Sai Chaganty , Nate DeSimone Subject: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Support DynamicExPCD from FSP. Date: Fri, 31 May 2019 19:42:06 +0800 Message-Id: <20190531114207.21112-2-chasel.chiu@intel.com> In-Reply-To: <20190531114207.21112-1-chasel.chiu@intel.com> References: <20190531114207.21112-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559302934; bh=D5TfiU3ssj3JbvgnIxe5krnMWjD8Cmuy95TsvkxJ/QU=; h=Cc:Date:From:Reply-To:Subject:To; b=AYJ5XzL1aNTvCvDEzF06mqUjEPy4UJQm4/Kd/bdXcw8pkrNiyRMQLCr8uNV+7YPFZru yqMdSTAiKFsSsEh/boEjiaTPwCW6KNFZ1yyqn5SxiI+Yt3O5p2gxuXc6GBeD79Qqt7Hap QeO4ujCn0euPxJrScIR93K4r2Aer5Toi59o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1864 FSP Dispatch mode can consume DynamicEx PCD from boot loader so it must include those PCD in PCD database for FSP to consume. PeiPostMemSiliconPolicyInitLib.inf (this is for FSP Dispatch mode) has all PCDs included to ensure they can be built into PCD database. Also cleaned up unused PciExpress related PCD from INFs. Cc: Michael A Kubacki Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciL= ib.c | 8 ++++++-- Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/PeiDx= eSmmCpuPlatformLib.inf | 7 +------ Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc = | 6 +++++- Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciL= ib.inf | 5 +++-- Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLib.inf= | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec = | 8 ++++++-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformLi= b/PeiDxeSmmSaPlatformLib.inf | 7 +------ Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/PeiSaP= olicyLib.inf | 3 +-- Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf = | 3 +-- 9 files changed, 25 insertions(+), 25 deletions(-) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/Pei= DxeSmmMmPciLib.c b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciL= ib/PeiDxeSmmMmPciLib.c index 51a06528e0..d99ee8e644 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmM= mPciLib.c +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmM= mPciLib.c @@ -1,7 +1,7 @@ /** @file This file contains routines that get PCI Express Address =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -27,5 +27,9 @@ MmPciBase ( { ASSERT ((Bus <=3D 0xFF) && (Device <=3D 0x1F) && (Function <=3D 0x7)); =20 - return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << 20= ) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#ifdef FSP_FLAG + return ((UINTN) PcdGet64 (PcdSiPciExpressBaseAddress) + (UINTN) (Bus << = 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#else + return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << = 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12)); +#endif } diff --git a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatf= ormLib/PeiDxeSmmCpuPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Cpu/L= ibrary/PeiDxeSmmCpuPlatformLib/PeiDxeSmmCpuPlatformLib.inf index 21d441a577..d2e813fea3 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/= PeiDxeSmmCpuPlatformLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Cpu/Library/PeiDxeSmmCpuPlatformLib/= PeiDxeSmmCpuPlatformLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for CPU Platform Lib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -34,11 +34,6 @@ MdePkg/MdePkg.dec UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec =20 - -[Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Sources] CpuPlatformLibrary.h CpuPlatformLibrary.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc b/Sili= con/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc index 5b114ae99e..aa481d0307 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc +++ b/Silicon/Intel/KabylakeSiliconPkg/KabylakeSiliconPkg.dsc @@ -47,7 +47,11 @@ gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FA= LSE =20 [PcdsFixedAtBuild.common] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xE0000000 -gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000 +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength |0x10000000 +# +# This DSC mainly for GreenH Silicon code build so PciExpressBaseAddress c= an be FixedAtBuild +# +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid.P= cdPciExpressBaseAddress =20 [Defines] PLATFORM_NAME =3D KabylakeSiliconPkg diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/Pei= DxeSmmMmPciLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPc= iLib/PeiDxeSmmMmPciLib.inf index 8ae40a0c9e..02495953a7 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmM= mPciLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmM= mPciLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiDxeSmmMmPciLib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -31,11 +31,12 @@ DebugLib =20 [Packages] MdePkg/MdePkg.dec +KabylakeSiliconPkg/SiPkg.dec =20 =20 [Pcd] +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress =20 - [Sources] PeiDxeSmmMmPciLib.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/Silico= nInitLib.inf b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/Sili= conInitLib.inf index 9007f299bb..132080e876 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLi= b.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/SiliconInitLib/SiliconInitLi= b.inf @@ -1,6 +1,6 @@ ### @file # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ SiliconInitPreMem.c =20 [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdTcoBaseAddress ## CONSUMES =20 diff --git a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec b/Silicon/Intel/Kab= ylakeSiliconPkg/SiPkg.dec index a613079dd4..baee73038b 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec +++ b/Silicon/Intel/KabylakeSiliconPkg/SiPkg.dec @@ -573,8 +573,12 @@ gSiPkgTokenSpaceGuid.PcdSerialIoUartInputClock |18432= 00|UINT32|0x00100003 ## PCI Express MMIO region length ## Valid settings: 0x10000000/256MB, 0x8000000/128MB, 0x4000000/64MB ## -gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0010004 - +gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000|UINT32|0x00100= 04 +## +## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciE= xpressBaseAddress. +## This PCD is added for supporting different PCD type in different phases. +## +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0xE0000000|UINT64|0x00100= 08 =20 [PcdsFeatureFlag] ## diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmm= SaPlatformLib/PeiDxeSmmSaPlatformLib.inf b/Silicon/Intel/KabylakeSiliconPkg= /SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf index 9fe71e5bac..5b034c2e9d 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf= ormLib/PeiDxeSmmSaPlatformLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatf= ormLib/PeiDxeSmmSaPlatformLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for SA Platform Lib # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,11 +28,6 @@ IoLib MdePkg/MdePkg.dec KabylakeSiliconPkg/SiPkg.dec =20 - -[Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress - - [Sources] SaPlatformLibrary.h SaPlatformLibrary.c diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPoli= cyLib/PeiSaPolicyLib.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Lib= rary/PeiSaPolicyLib/PeiSaPolicyLib.inf index 8fae4cee61..2adfc28d6c 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/P= eiSaPolicyLib.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/Library/PeiSaPolicyLib/P= eiSaPolicyLib.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the PeiSaPolicy library. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -35,7 +35,6 @@ UefiCpuPkg/UefiCpuPkg.dec KabylakeSiliconPkg/SiPkg.dec =20 [Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdTsegSize gSiPkgTokenSpaceGuid.PcdMchBaseAddress gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress diff --git a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInit= Dxe.inf b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe= .inf index cc05f336b3..3c4c79affb 100644 --- a/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf +++ b/Silicon/Intel/KabylakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.inf @@ -1,7 +1,7 @@ ## @file # Component description file for SystemAgent Initialization driver # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -53,7 +53,6 @@ KabylakeSiliconPkg/KabylakeSiliconPrivate.dec =20 =20 [Pcd] -gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId gSiPkgTokenSpaceGuid.PcdMchBaseAddress =20 --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41730): https://edk2.groups.io/g/devel/message/41730 Mute This Topic: https://groups.io/mt/31879157/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Apr 29 20:11:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41731+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41731+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1559302936; cv=none; d=zoho.com; s=zohoarc; b=ChqHqFrCjXApAIKSIDTT7X7ZtQVIKKsS755Wp045oQMUd5hB5rya77RNijsEekadv5Dzc5BCt9cuAGirU22FSHK1o31Fuo9orJyeVjRyOjblQ6Hcxdmsi+hzCn8k7iHDCRfiUZqUcruXUm0bPbcnfYw4sgwWdOpMd19Q1g8PQWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559302936; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=cvk+4VCQp0uptkS/ue5UfXN2rEuGGP0Va8gJnmWEyXI=; b=Vai0FAsb96aT5t2AD+Da0R6dRGLcH+sYHZ5fB2e2cP+p12bxVmPafYMcHOAMoaUNe7ukIu+/O9SJ3nJodTDfHSVPlCcH9jJnXUJ2aKNKNLeTjRGglBkMgYmHFdwxxB/aJ3ghI1lJR0eMxB+oi5fCPO/ItW9sLV+rfI5D0rNJeZ4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41731+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1559302936118841.8674587321491; Fri, 31 May 2019 04:42:16 -0700 (PDT) Return-Path: X-Received: from mga18.intel.com (mga18.intel.com []) by groups.io with SMTP; Fri, 31 May 2019 04:42:15 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 May 2019 04:42:15 -0700 X-ExtLoop1: 1 X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.240.72]) by fmsmga008.fm.intel.com with ESMTP; 31 May 2019 04:42:13 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: "Chasel, Chiu" , Michael A Kubacki , Sai Chaganty , Nate DeSimone Subject: [edk2-devel] [PATCH 2/2] KabylakeOpenBoardPkg: Support DynamicExPCD from FSP. Date: Fri, 31 May 2019 19:42:07 +0800 Message-Id: <20190531114207.21112-3-chasel.chiu@intel.com> In-Reply-To: <20190531114207.21112-1-chasel.chiu@intel.com> References: <20190531114207.21112-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559302935; bh=KCyZOkc7q8yzpSs5sRp55lxvfoqANWS5uCCVIXdjbfA=; h=Cc:Date:From:Reply-To:Subject:To; b=taEfWfo23kHXRaw6AKXljT5eAxwW9FUy8LdxC8mRJveTjUfPOAi02kU9LsIbaubZI1r 70gMBgInyo6EITTHpQDdvZVcWFmaLN0WgL4JckFhV9mGJui6QGxKrSpM1NsXSCJ01QPG3 7JcnXMeRiLcbI6zE5S6ve+35R4SisexqPuQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1864 Cleaned up unused PciExpress related PCD from INF and remove unnecessary DEFINE from DSC. Defines some PCDs as different types per API mode or Dispatch mode, also enlarge PeiMemory for Dispatch mode as both FSP and boot loader shares the same PeiMemory. Test: Boot with FSP API mode successfully. Cc: Michael A Kubacki Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf | = 3 +-- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | = 17 ++++++++++++++++- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | = 25 +++++++++++++++++++------ 3 files changed, 36 insertions(+), 9 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/T= btSmm.inf b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/Tb= tSmm.inf index 9218c8fe67..8bc2f8729f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.i= nf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.i= nf @@ -1,7 +1,7 @@ ### @file # Component information file for the ThunderBolt Smm module. # -# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2018 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -44,7 +44,6 @@ =20 [Pcd] gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES =20 [FixedPcd] gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 1dfe49a7ad..8dbdf25787 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -15,7 +15,6 @@ DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE =3D AmberLakeFspBinPkg DEFINE PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg DEFINE BOARD =3D KabylakeRvp3 DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE= )/$(BOARD) @@ -40,6 +39,22 @@ DEFINE PLATFORM_FSP_BIN_PACKAGE =3D AmberLakeFspBinPkg !endif =20 +[PcdsDynamicExDefault.common.DEFAULT] +!if gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D TRUE +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 0 + # + # Include FSP DynamicEx PCD settings in Dispatch mode + # + !include $(PLATFORM_FSP_BIN_PACKAGE)/FspPcds.dsc + + # + # Override some FSP consumed PCD default value to match platform require= ment. + # + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSpaceGui= d.PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength +!endif +!endif + ##########################################################################= ###### # # Defines Section - statements that will be processed to create a Makefile. diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index 63d0c4c2e6..fbd43a6947 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -48,7 +48,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 =20 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 @@ -147,6 +147,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0xFFEBC000 gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0xFFE00000 =20 + ## Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. + # @Prompt Timeout for the BSP to detect all APs for the first time. + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 + +!if (gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode =3D=3D FALSE) || = (gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1) + # + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBui= ld + # (They will be DynamicEx in FSP Dispatch mode) + # ## Specifies max supported number of Logical Processors. # @Prompt Configure max supported number of Logical Processorss gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|12 @@ -155,10 +164,6 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt Microcode Region size. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0 =20 - ## Specifies timeout value in microseconds for the BSP to detect all APs= for the first time. - # @Prompt Timeout for the BSP to detect all APs for the first time. - gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|1000 - ## Specifies the AP wait loop state during POST phase. # The value is defined as below. # 1: Place AP in the Hlt-Loop state. @@ -167,6 +172,15 @@ gSiPkgTokenSpaceGuid.PcdTsegSize|0x800000 # @Prompt The AP wait loop state. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2 =20 + gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress|gEfiMdePkgTokenSpaceGuid= .PcdPciExpressBaseAddress + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|gMinPlatformPkgTokenSpa= ceGuid.PcdPciExpressRegionLength +!else + # + # FSP Dispatch mode requires more platform memory as boot loader and FSP= sharing the same + # platform memory. + # + gSiPkgTokenSpaceGuid.PcdPeiMinMemorySize|0x5500000 +!endif =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -294,4 +308,3 @@ gBoardModuleTokenSpaceGuid.PcdDTbtPcieMemAddrRngMax | 26 gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemRsvd | 100 gBoardModuleTokenSpaceGuid.PcdDTbtPciePMemAddrRngMax | 28 gBoardModuleTokenSpaceGuid.PcdPchPcieRootPortHpe| 0x00000001 - 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