From nobody Wed Nov 27 04:53:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41627+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41627+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1559142756; cv=none; d=zoho.com; s=zohoarc; b=g02jwZGx1HwVdUmLz52zVnkURRKyJDquvbqiDyq582z2/1bXK84U9FUEEm7S6pW/E0LaB2M7vP12gfMFeduBofNy663Og9bpbOS5x0ZKGZI2nbL9Z0Mp3zKV6EA6mguffvG7l1tW8vbYFO52iZTAjehWjB6ILtLDBVxWVjeJmxQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559142756; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=qCU7ptQ72mbrJYZRZxq41MJYJ78tascsIIIEZnAg+vg=; b=h2M3AJFHpwOqQUCa0JVjjIe9Zwgr68Bm8n7wNuxAXukusHxOdoDQq8dvqmOlfrRATIgM0Q8+XUyGOAtdneZu85tFTUaJm06XO3dHqkwGcXM7/Df8Q0RvWXZouacvZfsUrMvOk6CRteVhbJBn7QZOYlq0ChZhf6zkRjZjzvRuLpk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41627+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1559142756467648.3084621980179; Wed, 29 May 2019 08:12:36 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:34 -0700 X-Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C0D0230C62A8; Wed, 29 May 2019 15:12:28 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2A78A4DA; Wed, 29 May 2019 15:12:24 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH for-edk2-stable201905 2/6] Revert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35" Date: Wed, 29 May 2019 17:12:05 +0200 Message-Id: <20190529151209.17503-3-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.46]); Wed, 29 May 2019 15:12:28 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559142755; bh=/yoUb+P6NuFVrgXG/A2vhm2X+o0FSWUU4JrRQYZ3vcY=; h=Cc:Date:From:Reply-To:Subject:To; b=LYuGceKpeYNNvUVP75yNWKhGMWFBmtx/SUrBtb929jNApungbVRskHzaaxv10OxvUNI b8rrOZtNBErC/u571+ovNpfWwn0820XFEN2CQqSEWWC0hdL4mOAywFXpvCEPCgChjafOl V/787neHCc+clilTCRiXnARJgfA9y4mHHoA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This reverts commit 75136b29541b0e093a51d2e2c2af8d19855c2b60. The original fix for triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/OvmfPkgIa32.dsc | 5 ++++- OvmfPkg/OvmfPkgIa32X64.dsc | 5 ++++- OvmfPkg/OvmfPkgX64.dsc | 5 ++++- OvmfPkg/PlatformPei/Platform.c | 9 +++++---- 4 files changed, 17 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index b3446ece311a..578fc6c98ec8 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -490,7 +490,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, QE= MU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 679d4eb8dd36..eade8f62d3de 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, QE= MU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 56a9560262aa..733a4c9d8a43 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, QE= MU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index fd8eccaf3e50..9c013613a1a0 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -184,13 +184,14 @@ MemMapInitialization ( PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // - // The 32-bit PCI host aperture is expected to fall between the top = of - // low RAM and the base of the MMCONFIG area. + // The MMCONFIG area is expected to fall between the top of low RAM = and + // the base of the 32-bit PCI host aperture. // PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT (PciBase < PciExBarBase); + ASSERT (TopOfLowRam <=3D PciExBarBase); ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); - PciSize =3D (UINT32)(PciExBarBase - PciBase); + PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); + PciSize =3D 0xFC000000 - PciBase; } else { PciSize =3D 0xFC000000 - PciBase; } --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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