From nobody Sun May 5 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41625+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41625+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1559142744; cv=none; d=zoho.com; s=zohoarc; b=P3MGJVCprtP3VoQQdDbfWHSlxsrCzUvYH4nkL7n5S/zZAuTJm6bA+aNHRRrK/bc8rIysQ+00ijv6dD990If1ExFE3GD/y9G/BlRHSNzU46bu1GpYnZ8SrA2/WxGzoSFZrJNeBeKlB95MuPoicn2Kdwd7AnnxvlTDUnZQUrPSzp8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559142744; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=mFNCgXkuqG31521PB+7poeUYgOPhcLFrcuQKvZdRhI4=; b=AyRPxrK4Cp/ZY5C9gcb4ExzY5/Zjhm2/k4dLEiWAz7ypaFMTY4Aiz4noQuo5lDBTgcpNxqQUvJffVb0+cKtyJI1tkhabSJF81w2aQNS1oxMtweM8Bxn7xz2XlswP5KKcJlMz07Sl1dqWRGB0Jl6JfdguWPFQTO9v0+fz8405eDo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41625+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 155914274425772.6954082372971; Wed, 29 May 2019 08:12:24 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:23 -0700 X-Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F215B30B96FC; Wed, 29 May 2019 15:12:22 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id AF2F54DA; Wed, 29 May 2019 15:12:16 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH for-edk2-stable201905 1/6] Revert "OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear" Date: Wed, 29 May 2019 17:12:04 +0200 Message-Id: <20190529151209.17503-2-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Wed, 29 May 2019 15:12:23 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559142743; bh=H01IgLGc6Qup/Dh9+UAldaUJxs4DNL0cXlyl16N9vFE=; h=Cc:Date:From:Reply-To:Subject:To; b=S3i9SqYnQceCsbnfpkxiKLwNDEz+qWVguctK5jV+H5c2oJvNy86ZPc9gWR23wXLGwMJ 2QsjqrZ1nvM187F1qWPHMFLwkYso4MO5TvbOjKeMl0qbH/TxGefI6IB3+La4VrRbmXKuB C2diN8cd+xzgoOcLbrmzyeYJCoyy/86AYaw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This reverts commit 39b9a5ffe6618b7870be2a54fe7725000249c33a. The original fix for triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek Acked-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/PlatformPei/Platform.h | 2 -- OvmfPkg/PlatformPei/MemDetect.c | 23 +++----------------- OvmfPkg/PlatformPei/Platform.c | 4 +++- 3 files changed, 6 insertions(+), 23 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 4476ddd871cd..81af8b71480f 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -114,6 +114,4 @@ extern UINT32 mMaxCpuCount; =20 extern UINT16 mHostBridgeDevId; =20 -extern UINT32 mQemuUc32Base; - #endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index ae73c63d27d5..e890e36408a6 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -42,8 +42,6 @@ STATIC UINT32 mS3AcpiReservedMemorySize; =20 STATIC UINT16 mQ35TsegMbytes; =20 -UINT32 mQemuUc32Base; - VOID Q35TsegMbytesInitialization ( VOID @@ -665,8 +663,6 @@ QemuInitializeRam ( // cover it exactly. // if (IsMtrrSupported ()) { - UINT32 Uc32Size; - MtrrGetAllMtrrs (&MtrrSettings); =20 // @@ -693,24 +689,11 @@ QemuInitializeRam ( =20 // // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB= as - // uncacheable. Make sure one variable MTRR suffices by truncating the= size - // to a whole power of two. This will round the base *up*, and a gap (= not - // used for either RAM or MMIO) may stay in the middle, marked as - // cacheable-by-default. + // uncacheable // - Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize)); - mQemuUc32Base =3D (UINT32)(SIZE_4GB - Uc32Size); - if (mQemuUc32Base !=3D LowerMemorySize) { - DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, = for " - "an UC32 size of 0x%x\n", __FUNCTION__, (UINT32)LowerMemorySize, - mQemuUc32Base, Uc32Size)); - } - - Status =3D MtrrSetMemoryAttribute (mQemuUc32Base, Uc32Size, - CacheUncacheable); + Status =3D MtrrSetMemoryAttribute (LowerMemorySize, + SIZE_4GB - LowerMemorySize, CacheUncacheable); ASSERT_EFI_ERROR (Status); - } else { - mQemuUc32Base =3D (UINT32)LowerMemorySize; } } =20 diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index c064b4ed9b8f..fd8eccaf3e50 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -174,12 +174,14 @@ MemMapInitialization ( AddIoMemoryRangeHob (0x0A0000, BASE_1MB); =20 if (!mXen) { + UINT32 TopOfLowRam; UINT64 PciExBarBase; UINT32 PciBase; UINT32 PciSize; =20 + TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); PciExBarBase =3D 0; - PciBase =3D (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base; + PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // // The 32-bit PCI host aperture is expected to fall between the top = of --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41625): https://edk2.groups.io/g/devel/message/41625 Mute This Topic: https://groups.io/mt/31834711/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41627+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41627+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1559142756; cv=none; d=zoho.com; s=zohoarc; b=g02jwZGx1HwVdUmLz52zVnkURRKyJDquvbqiDyq582z2/1bXK84U9FUEEm7S6pW/E0LaB2M7vP12gfMFeduBofNy663Og9bpbOS5x0ZKGZI2nbL9Z0Mp3zKV6EA6mguffvG7l1tW8vbYFO52iZTAjehWjB6ILtLDBVxWVjeJmxQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559142756; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=qCU7ptQ72mbrJYZRZxq41MJYJ78tascsIIIEZnAg+vg=; b=h2M3AJFHpwOqQUCa0JVjjIe9Zwgr68Bm8n7wNuxAXukusHxOdoDQq8dvqmOlfrRATIgM0Q8+XUyGOAtdneZu85tFTUaJm06XO3dHqkwGcXM7/Df8Q0RvWXZouacvZfsUrMvOk6CRteVhbJBn7QZOYlq0ChZhf6zkRjZjzvRuLpk= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41627+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1559142756467648.3084621980179; Wed, 29 May 2019 08:12:36 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:34 -0700 X-Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id C0D0230C62A8; Wed, 29 May 2019 15:12:28 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 2A78A4DA; Wed, 29 May 2019 15:12:24 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH for-edk2-stable201905 2/6] Revert "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35" Date: Wed, 29 May 2019 17:12:05 +0200 Message-Id: <20190529151209.17503-3-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.46]); Wed, 29 May 2019 15:12:28 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559142755; bh=/yoUb+P6NuFVrgXG/A2vhm2X+o0FSWUU4JrRQYZ3vcY=; h=Cc:Date:From:Reply-To:Subject:To; b=LYuGceKpeYNNvUVP75yNWKhGMWFBmtx/SUrBtb929jNApungbVRskHzaaxv10OxvUNI b8rrOZtNBErC/u571+ovNpfWwn0820XFEN2CQqSEWWC0hdL4mOAywFXpvCEPCgChjafOl V/787neHCc+clilTCRiXnARJgfA9y4mHHoA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This reverts commit 75136b29541b0e093a51d2e2c2af8d19855c2b60. The original fix for triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek Acked-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/OvmfPkgIa32.dsc | 5 ++++- OvmfPkg/OvmfPkgIa32X64.dsc | 5 ++++- OvmfPkg/OvmfPkgX64.dsc | 5 ++++- OvmfPkg/PlatformPei/Platform.c | 9 +++++---- 4 files changed, 17 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index b3446ece311a..578fc6c98ec8 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -490,7 +490,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, QE= MU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 679d4eb8dd36..eade8f62d3de 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, QE= MU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 56a9560262aa..733a4c9d8a43 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -495,7 +495,10 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 + # + # On Q35 machine types that QEMU intends to support in the long term, QE= MU + # never lets the RAM below 4 GB exceed 2 GB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index fd8eccaf3e50..9c013613a1a0 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -184,13 +184,14 @@ MemMapInitialization ( PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // - // The 32-bit PCI host aperture is expected to fall between the top = of - // low RAM and the base of the MMCONFIG area. + // The MMCONFIG area is expected to fall between the top of low RAM = and + // the base of the 32-bit PCI host aperture. // PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT (PciBase < PciExBarBase); + ASSERT (TopOfLowRam <=3D PciExBarBase); ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); - PciSize =3D (UINT32)(PciExBarBase - PciBase); + PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); + PciSize =3D 0xFC000000 - PciBase; } else { PciSize =3D 0xFC000000 - PciBase; } --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41627): https://edk2.groups.io/g/devel/message/41627 Mute This Topic: https://groups.io/mt/31834716/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41626+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41626+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1559142752; cv=none; d=zoho.com; s=zohoarc; b=MG7wlyZEKpvHHzekCGwa79GgECDpC25xkHmFeVY1ZN/7sPROJXxI00naeQ0UHMtpv93vNAPhIif3GQ4LqHYb2O1Wq5sEUBDmAHCfogewKlj5BixXUG4mQ1GLaUfrFNzQdEjB/6Fnj+XcRQBSt1xQWXf1DDl6NhmkrNeQlkNu8vs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559142752; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=jbeVx+o/wwMU1tOtRXPOscq2js2UT/E8Wz5bu2KiEpw=; b=mi+k0g1vVJLzn1rVHNRlzJSVUfSxU8+kGwWqeL/YvvIr5EjAKZwF1GeiPLeOZ/0ie4TRM4RtzLe8eVqesk18dh0kr+gsbbCe2HR/dU2FO5rZIxJql6Nz8zMazwO84ysOy6m7pkqUfbvOebMZf37PXXStbaXrETGPHOo2XhK3xIc= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41626+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1559142752925354.4250691124266; Wed, 29 May 2019 08:12:32 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:32 -0700 X-Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id DC33930C0DED; Wed, 29 May 2019 15:12:30 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 28F0D4DA; Wed, 29 May 2019 15:12:28 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH for-edk2-stable201905 3/6] Revert "OvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching" Date: Wed, 29 May 2019 17:12:06 +0200 Message-Id: <20190529151209.17503-4-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.45]); Wed, 29 May 2019 15:12:30 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559142752; bh=NF8qDB5MckhLjdoLmX3n0+Cq5eMxDAAjUueUu3EDgfE=; h=Cc:Date:From:Reply-To:Subject:To; b=cQx0132xaR98Ju5m6QjujDaTQ9QWamu7wu+4NYX2m2o8Ee8P5RojKc7WOX4dbNVqk42 rFL08d0adkljDUf3bFbQd7+P9EulwNi2lMm1f+SaqZD4dPNFCi2QszavkfMTY9mmfVRly P/fczOkVAxCyhWFFuKqcmIekf23g6e518v0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This reverts commit 9a2e8d7c65ef7f39c6754d27e52954b616bc6628. The original fix for triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek Acked-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/PlatformPei/Platform.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 9c013613a1a0..5e0a15484230 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -181,7 +181,6 @@ MemMapInitialization ( =20 TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); PciExBarBase =3D 0; - PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // // The MMCONFIG area is expected to fall between the top of low RAM = and @@ -193,6 +192,7 @@ MemMapInitialization ( PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); PciSize =3D 0xFC000000 - PciBase; } else { + PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; PciSize =3D 0xFC000000 - PciBase; } =20 --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41626): https://edk2.groups.io/g/devel/message/41626 Mute This Topic: https://groups.io/mt/31834715/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41628+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41628+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1559142758; cv=none; d=zoho.com; s=zohoarc; b=EbXXO4+i4Mr4LWJdj0CSlNFgDMB8YUPcGT1mokdu+sNcqQuWcF5nCvzsMNTHxpn8NmBAI/0Wcl4F4V4IrJ7MMXEyPPBN91MTBNKf3Rx6NmTVk2aEkFPC0BtXd7JeZX8HBMnDzkRTQ55URdHsRA6pDNppuCq5vebyeqpdGEqtfBI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559142758; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=KLWedqKShzANveqdXHgx8m2os51yufVnap+lIaYQMQk=; b=P1CsbYnjEgzQOueE70BmQMkBD1kcFbkZw2oS2nMNQMYxMjtLSus1wtshbOaGeylb9M3MURmcDgBRWanOY7DHa9DEtw0KHfNi1kFAhueE/IgFwj1MFALwwCKqe7aBDNz1UivRBTco8JCVg7TC4fsIFNmno9P81Gv67K7bFuuusoU= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41628+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1559142758888979.7016200852611; Wed, 29 May 2019 08:12:38 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:38 -0700 X-Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id B011B7F7C8; Wed, 29 May 2019 15:12:37 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 41BB879423; Wed, 29 May 2019 15:12:31 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH for-edk2-stable201905 4/6] Revert "OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly" Date: Wed, 29 May 2019 17:12:07 +0200 Message-Id: <20190529151209.17503-5-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.28]); Wed, 29 May 2019 15:12:37 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559142758; bh=qBCGs/S6/Tn3A5UN+RWiIyxNQuZ00M/do0sq3Clswnw=; h=Cc:Date:From:Reply-To:Subject:To; b=PbJO2K6mqOfzMVdtKY5ybBaK/8iMDqSBzzrTpEknmLii3yqW7breIsLup4ce0a2nvb5 jJBpKDTQYIFqxV3UlHtzLRNN/eOi5+lDZqUo+nkqO5dYdnxbUrVt8PGzvEmBS0FWi40Bs dcPVvzSseCSWcTGRX7XxF0Se9UKsALKkuas= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This reverts commit 60e95bf5094fbb9b728729ccfaf32184b3662317. The original fix for triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek Acked-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/PlatformPei/Platform.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 5e0a15484230..0876316eefbc 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -190,10 +190,8 @@ MemMapInitialization ( ASSERT (TopOfLowRam <=3D PciExBarBase); ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); - PciSize =3D 0xFC000000 - PciBase; } else { PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; - PciSize =3D 0xFC000000 - PciBase; } =20 // @@ -209,6 +207,7 @@ MemMapInitialization ( // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // + PciSize =3D 0xFC000000 - PciBase; AddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41628): https://edk2.groups.io/g/devel/message/41628 Mute This Topic: https://groups.io/mt/31834717/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41629+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41629+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1559142764; cv=none; d=zoho.com; s=zohoarc; b=BkLD6HT4R2vh0i4MeLKipG5lHnB3Q7l2uvH+HcFg6tHOAyM5UHF4FdDYfwo4qqNwlmkqMRabHoXzdgRrYtvuQvvBnRMX2gZCtCRmcMXOCBgsbXRNGXJ9jfV4zRYgZopqDIu4dioR0tMHTgsFmq0kR7FtDr+q2C3i3k1u121aEGI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559142764; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=4s/8nSiTzQSMxlRSCQmgK+ueiZnLYW/BIVuMkcPatYc=; b=hOvvFvmfRzf7w31uGUQ5tDS1X8AW8BFyLfh9PET+mEVpfxCPLs4Yl/PmGg0fD/GF9mHC6RdmrWFHHMF8kc2zwVV1CYKfnIils83uti6zfZSzP5ax2N3KdsugSO5dGC6jfe514PjDhUQWyy4PF2uFNqyfcuqFpOTeOEoYNsNpyQo= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41629+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1559142764594531.4142617622986; Wed, 29 May 2019 08:12:44 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:41 -0700 X-Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id D4EAEC05FF80; Wed, 29 May 2019 15:12:40 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 172201715C; Wed, 29 May 2019 15:12:37 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH for-edk2-stable201905 5/6] OvmfPkg: raise the PCIEXBAR base to 2816 MB on Q35 Date: Wed, 29 May 2019 17:12:08 +0200 Message-Id: <20190529151209.17503-6-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.31]); Wed, 29 May 2019 15:12:40 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559142764; bh=g/cwNGPl+7d9XvMYCrefX0lFNdV0RO4FpTffIup9ZNM=; h=Cc:Date:From:Reply-To:Subject:To; b=h6FRcr35Kj46+dzmGg7BB0w6qZ1YdvbQL9zCXSX7njyPHsxBh4SGzjNmQxLB85hoIa0 DnSNHJfetEGB1q+rQPXtnrBM28uzPx8XzAGuf6MLEBEg9ZmTpHeEjFvRBNORIPE+hAKh/ B3vrNI8Ogw77y/KYgQSOqtCjbAg12h1cEOE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" (This is a replacement for commit 75136b29541b, "OvmfPkg/PlatformPei: reorder the 32-bit PCI window vs. the PCIEXBAR on q35", 2019-05-16). Commit 7b8fe63561b4 ("OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35", 2016-03-10) claimed that, On Q35 machine types that QEMU intends to support in the long term, QEMU never lets the RAM below 4 GB exceed 2 GB. Alas, this statement came from a misunderstanding that occurred while we worked out the interface contract. In fact QEMU does allow the 32-bit RAM extend up to 0xB000_0000 (exclusive), in case the RAM size falls in the range (0x8000_0000, 0xB000_0000) (i.e., the RAM size is greater than 2048MB and smaller than 2816MB). In turn, such a RAM size (justifiedly) triggers ASSERT (TopOfLowRam <=3D PciExBarBase); in MemMapInitialization(), because we placed the 256MB PCIEXBAR at 0x8000_0000 (2GB) exactly, relying on the interface contract. (And, the 32-bit PCI window would follow the PCIEXBAR, covering the [0x9000_0000, 0xFC00_0000) range.) In order to fix this, place the PCIEXBAR at 2816MB (0xB000_0000), and start the 32-bit PCI window at 3 GB (0xC000_0000). This shrinks the 32-bit PCI window to 0xFC00_0000 - 0xC000_0000 =3D 0x3C00_0000 =3D 960 MB. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek Acked-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/OvmfPkgIa32.dsc | 4 ++-- OvmfPkg/OvmfPkgIa32X64.dsc | 4 ++-- OvmfPkg/OvmfPkgX64.dsc | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 578fc6c98ec8..e74a9d5a5149 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -492,8 +492,8 @@ [PcdsFixedAtBuild] # the PCIEXBAR register. # # On Q35 machine types that QEMU intends to support in the long term, QE= MU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + # never lets the RAM below 4 GB exceed 2816 MB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index eade8f62d3de..67ac015991fd 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -497,8 +497,8 @@ [PcdsFixedAtBuild] # the PCIEXBAR register. # # On Q35 machine types that QEMU intends to support in the long term, QE= MU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + # never lets the RAM below 4 GB exceed 2816 MB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 733a4c9d8a43..68073ef55b4d 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -497,8 +497,8 @@ [PcdsFixedAtBuild] # the PCIEXBAR register. # # On Q35 machine types that QEMU intends to support in the long term, QE= MU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + # never lets the RAM below 4 GB exceed 2816 MB. + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xB0000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41629): https://edk2.groups.io/g/devel/message/41629 Mute This Topic: https://groups.io/mt/31834720/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 14:33:12 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41630+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41630+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1559142765; cv=none; d=zoho.com; s=zohoarc; b=i1azk2TrgT1u7uZiRinbzE6+wEYLoO8atK3uwgTYogrFKWPunUwH7DPwuilyxfBBhQznSIt6WXYo28gKZtWgg+n3XIXkLMldgICYaaO2F+EEXhLJjEJlyRZIk+GOYmJ6d71KREFTSA+tk0Mmspue71xJHMtR/qIQhA2ZAISyuQQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1559142765; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=88P8P8g/aT8F40rwYv/2tDwjzt5eukSyNS6n+RL5vsg=; b=XaViIsE3GI1kKdxgM5IXm2BCYpv1qCQ2iAm8oV1ZxIQ1Pd+5GLjLIj9GcbMelNUC7diyGL54F/ABwgu1r73zZociwKHDCKxxOZq9lrcTLn8x40+DqwifyPJmPXRTb4sp0f/KXDCaFCMfZqGyQ6RyIcgY60EYYu3oPk/mJmY285w= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41630+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1559142765004964.4583582065417; Wed, 29 May 2019 08:12:45 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Wed, 29 May 2019 08:12:43 -0700 X-Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.phx2.redhat.com [10.5.11.16]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 425E5309B15E; Wed, 29 May 2019 15:12:43 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-120-170.rdu2.redhat.com [10.10.120.170]) by smtp.corp.redhat.com (Postfix) with ESMTP id 9C8531715C; Wed, 29 May 2019 15:12:41 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH for-edk2-stable201905 6/6] OvmfPkg/PlatformPei: set 32-bit UC area at PciBase / PciExBarBase (pc/q35) Date: Wed, 29 May 2019 17:12:09 +0200 Message-Id: <20190529151209.17503-7-lersek@redhat.com> In-Reply-To: <20190529151209.17503-1-lersek@redhat.com> References: <20190529151209.17503-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.49]); Wed, 29 May 2019 15:12:43 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1559142764; bh=v7QH/cjgEZJb/t6Fn7AHB6vsyWgWEB/BVUtXk/K8r80=; h=Cc:Date:From:Reply-To:Subject:To; b=F+KjAHHlxZpamMIDkg12dlrxUyfXUN0/eqti6ptNdYthrOOru08Jh09YZib8BsOzpYj QX5C7PKB+uJaGCXaqQAJKA4uqU3gfbyRdQLPnJ5V8JAeGSf5LAlCAuLdriTkyqtjy7+2B 0ZvOtnD1dZZoJiAciV4/lavlGfa4Chto1c0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" (This is a replacement for commit 39b9a5ffe661 ("OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear", 2019-05-16).) Reintroduce the same logic as seen in commit 39b9a5ffe661 for the pc (i440fx) board type. For q35, the same approach doesn't work any longer, given that (a) we'd like to keep the PCIEXBAR in the platform DSC a fixed-at-build PCD, and (b) QEMU expects the PCIEXBAR to reside at a lower address than the 32-bit PCI MMIO aperture. Therefore, introduce a helper function for determining the 32-bit "uncacheable" (MMIO) area base address: - On q35, this function behaves statically. Furthermore, the MTRR setup exploits that the range [0xB000_0000, 0xFFFF_FFFF] can be marked UC with just two variable MTRRs (one at 0xB000_0000 (size 256MB), another at 0xC000_0000 (size 1GB)). - On pc (i440fx), the function behaves dynamically, implementing the same logic as commit 39b9a5ffe661 did. The PciBase value is adjusted to the value calculated, similarly to commit 39b9a5ffe661. A further simplification is that we show that the UC32 area size truncation to a whole power of two automatically guarantees a >=3D2GB base address. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1859 Signed-off-by: Laszlo Ersek Acked-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/PlatformPei/Platform.h | 7 +++ OvmfPkg/PlatformPei/MemDetect.c | 59 ++++++++++++++++++-- OvmfPkg/PlatformPei/Platform.c | 5 +- 3 files changed, 66 insertions(+), 5 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 81af8b71480f..2f3cebcd3a6a 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -62,6 +62,11 @@ GetSystemMemorySizeBelow4gb ( VOID ); =20 +VOID +QemuUc32BaseInitialization ( + VOID + ); + VOID InitializeRamRegions ( VOID @@ -114,4 +119,6 @@ extern UINT32 mMaxCpuCount; =20 extern UINT16 mHostBridgeDevId; =20 +extern UINT32 mQemuUc32Base; + #endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index e890e36408a6..d451989f31c9 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -14,6 +14,7 @@ Module Name: // The package level header files this module uses // #include +#include #include #include =20 @@ -42,6 +43,8 @@ STATIC UINT32 mS3AcpiReservedMemorySize; =20 STATIC UINT16 mQ35TsegMbytes; =20 +UINT32 mQemuUc32Base; + VOID Q35TsegMbytesInitialization ( VOID @@ -98,6 +101,54 @@ Q35TsegMbytesInitialization ( } =20 =20 +VOID +QemuUc32BaseInitialization ( + VOID + ) +{ + UINT32 LowerMemorySize; + UINT32 Uc32Size; + + if (mXen) { + return; + } + + if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { + // + // On q35, the 32-bit area that we'll mark as UC, through variable MTR= Rs, + // starts at PcdPciExpressBaseAddress. The platform DSC is responsible= for + // setting PcdPciExpressBaseAddress such that describing the + // [PcdPciExpressBaseAddress, 4GB) range require a very small number of + // variable MTRRs (preferably 1 or 2). + // + ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); + mQemuUc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); + return; + } + + ASSERT (mHostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); + // + // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one + // variable MTRR suffices by truncating the size to a whole power of two, + // while keeping the end affixed to 4GB. This will round the base up. + // + LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); + Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize)); + mQemuUc32Base =3D (UINT32)(SIZE_4GB - Uc32Size); + // + // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most= 2GB. + // Therefore mQemuUc32Base is at least 2GB. + // + ASSERT (mQemuUc32Base >=3D BASE_2GB); + + if (mQemuUc32Base !=3D LowerMemorySize) { + DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, fo= r " + "an UC32 size of 0x%x\n", __FUNCTION__, LowerMemorySize, mQemuUc32Ba= se, + Uc32Size)); + } +} + + /** Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start ou= tside of the 32-bit address range. @@ -688,11 +739,11 @@ QemuInitializeRam ( ASSERT_EFI_ERROR (Status); =20 // - // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB= as - // uncacheable + // Set the memory range from the start of the 32-bit MMIO area (32-bit= PCI + // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. // - Status =3D MtrrSetMemoryAttribute (LowerMemorySize, - SIZE_4GB - LowerMemorySize, CacheUncacheable); + Status =3D MtrrSetMemoryAttribute (mQemuUc32Base, SIZE_4GB - mQemuUc32= Base, + CacheUncacheable); ASSERT_EFI_ERROR (Status); } } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 0876316eefbc..3ba2459872d9 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -191,7 +191,8 @@ MemMapInitialization ( ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); } else { - PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; + ASSERT (TopOfLowRam <=3D mQemuUc32Base); + PciBase =3D mQemuUc32Base; } =20 // @@ -650,6 +651,8 @@ InitializePlatform ( =20 PublishPeiMemory (); =20 + QemuUc32BaseInitialization (); + InitializeRamRegions (); =20 if (mXen) { --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41630): https://edk2.groups.io/g/devel/message/41630 Mute This Topic: https://groups.io/mt/31834722/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-