From nobody Tue May 7 09:15:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41208+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41208+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1558514122; cv=none; d=zoho.com; s=zohoarc; b=KtE2bRRBWBFcZBqoHEMxTU1uO3IQWqUSakgdqTxaElonMvWlQDdi8gqQzkkfMGE4y9Uj9ntdruU07Nu/N35okvPWoWya7RkRjGwH5HnCxXfZwM621k13i7M7KWXm9cOG3EHyp/FTYLDfs/+7MF09E92NrdOqnoeBQiSn/ER9soc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558514122; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=n9k5TBdH/8T2g+8GshtOdhw+7GbPKnz+v6zhUTIW/xk=; b=YbyfDtQUrV/P4JxrcJnZn0pAuMuwePnTp0m7dhQsxpHf8SaLC7RsSiUClNcelcgxeZNuloO79jlXxFPamMhrQ20LiuxmACnrabkErbpTiEn95YTi1IHL0o1L6JhwKHCRmIXprMY/5bCUaWJr2pb+2q6+bgjl6YBzCYvaAR6V+jI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41208+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1558514122440201.1922239646267; Wed, 22 May 2019 01:35:22 -0700 (PDT) Return-Path: X-Received: from mga17.intel.com (mga17.intel.com []) by groups.io with SMTP; Wed, 22 May 2019 01:35:21 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 May 2019 01:35:21 -0700 X-ExtLoop1: 1 X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.240.31]) by fmsmga007.fm.intel.com with ESMTP; 22 May 2019 01:35:20 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: "Chasel, Chiu" , Nate DeSimone , Michael Kubacki Subject: [edk2-devel] [PATCH 1/2] KabylakeSiliconPkg: Add FSP Dispatch switch. Date: Wed, 22 May 2019 16:35:09 +0800 Message-Id: <20190522083510.17476-2-chasel.chiu@intel.com> In-Reply-To: <20190522083510.17476-1-chasel.chiu@intel.com> References: <20190522083510.17476-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1558514122; bh=qCl6NgdyD91OCSXSDfVcXjW/vYkPa0S72hHeHIJpv84=; h=Cc:Date:From:Reply-To:Subject:To; b=U7yabNDcfH59umn+TnYQvvHsWjSXBiZRUXCHvacJ1w/re4K1i4HPBzfCWx1jFBar3nG H/MEHfWvYg/z85dm+doBLUylpRnbD6Jm3gYpGyNxxoe2fedm5qgwr0SZ+K5i27CQfIC2c HG6pw9jfxV9/iO5d2P4aBSSolhfgYsejPPU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1832 PcdFspModeSelection is used as switch for boot loader to consume FSP in API mode or Dispatch mode. For backward compatibility, if boot loader running in FSP API mode the KabylakeFspBinPkg will be used which does not have FSP 2.1 changes. For FSP Dispatch mode AmberLakeFspBinPkg will be used with FSP 2.1 support. One INF was duplicate to include different DEC file in each build type. Test: Booted Kabylake RVP3 to Windows successfully. Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/PeiSil= iconPolicyInitLibFspAml.inf | 146 +++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitL= ibFsp/PeiSiliconPolicyInitLibFspAml.inf b/Silicon/Intel/KabylakeSiliconPkg/= Library/PeiSiliconPolicyInitLibFsp/PeiSiliconPolicyInitLibFspAml.inf new file mode 100644 index 0000000000..aebd3583bc --- /dev/null +++ b/Silicon/Intel/KabylakeSiliconPkg/Library/PeiSiliconPolicyInitLibFsp/P= eiSiliconPolicyInitLibFspAml.inf @@ -0,0 +1,146 @@ +### @file +# Library functions for Fsp Policy Initialization Library. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSiliconPolicyInitLibFspAml + FILE_GUID =3D 930816C4-D182-4A23-BF21-9AED635AF06C + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SiliconPolicyInitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + PeiFspPolicyInitLib.c + PeiFspSiPolicyInitLib.c + PeiFspPchPolicyInitLib.c + PeiFspCpuPolicyInitLib.c + PeiFspMePolicyInitLib.c + PeiFspSaPolicyInitLib.c + PeiFspMiscUpdInitLib.c + + PeiPolicyInitPreMem.c + PeiPolicyInit.c + PeiPolicyInit.h + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + KabylakeSiliconPkg/SiPkg.dec + AmberLakeFspBinPkg/AmberLakeFspBinPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + IoLib + PeiServicesLib + PcdLib + SmbusLib + MmPciLib + ConfigBlockLib + MemoryAllocationLib + DebugPrintErrorLevelLib + FspWrapperApiLib + +[Pcd] + gSiPkgTokenSpaceGuid.PcdTsegSize ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CONSUMES + +[Ppis] + gSiPolicyPpiGuid ## CONSUMES + gSiPreMemPolicyPpiGuid ## CONSUMES + +[Guids] + gTraceHubPreMemConfigGuid ## CONSUMES + gSmbusPreMemConfigGuid ## CONSUMES + gDciPreMemConfigGuid ## CONSUMES + gHpetPreMemConfigGuid ## CONSUMES + gHsioPciePreMemConfigGuid ## CONSUMES + gHsioSataPreMemConfigGuid ## CONSUMES + gHsioPreMemConfigGuid ## CONSUMES + gPcieRpPreMemConfigGuid ## CONSUMES + gLpcPreMemConfigGuid ## CONSUMES + gPchGeneralPreMemConfigGuid ## CONSUMES + gWatchDogPreMemConfigGuid ## CONSUMES + gLanConfigGuid ## CONSUMES + gPcieRpConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gHdAudioConfigGuid ## CONSUMES + gCio2ConfigGuid ## CONSUMES + gScsConfigGuid ## CONSUMES + gIshConfigGuid ## CONSUMES + gSpiConfigGuid ## CONSUMES + gSataConfigGuid ## CONSUMES + gUsbConfigGuid ## CONSUMES + gSerialIoConfigGuid ## CONSUMES + gInterruptConfigGuid ## CONSUMES + gLockDownConfigGuid ## CONSUMES + gSaMiscPeiPreMemConfigGuid ## PRODUCES + gMemoryConfigGuid ## CONSUMES + gMemoryConfigNoCrcGuid ## CONSUMES + gGraphicsPeiConfigGuid ## CONSUMES + gMePeiPreMemConfigGuid ## CONSUMES + gMePeiConfigGuid ## CONSUMES + gAmtPeiConfigGuid ## CONSUMES + gDmiConfigGuid ## CONSUMES + gFlashProtectionConfigGuid ## CONSUMES + gIoApicConfigGuid ## CONSUMES + gPmConfigGuid ## CONSUMES + gP2sbConfigGuid ## CONSUMES + gPchGeneralConfigGuid ## CONSUMES + gPort61ConfigGuid ## CONSUMES + gSerialIrqConfigGuid ## CONSUMES + gThermalConfigGuid ## CONSUMES + gCpuSecurityPreMemConfigGuid ## CONSUMES + gCpuTxtPreMemConfigGuid ## CONSUMES + gCpuConfigGuid ## CONSUMES + gBiosGuardConfigGuid ## CONSUMES + gCpuOverclockingPreMemConfigGuid ## CONSUMES + gCpuConfigLibPreMemConfigGuid ## CONSUMES + gCpuSgxConfigGuid ## CONSUMES + gCpuPowerMgmtBasicConfigGuid ## CONSUMES + gCpuPowerMgmtCustomConfigGuid ## CONSUMES + gCpuTestConfigGuid ## CONSUMES + gCpuPidTestConfigGuid ## CONSUMES + gCpuPowerMgmtTestConfigGuid ## CONSUMES + gSmramCpuDataHeaderGuid ## CONSUMES + gFspReservedMemoryResourceHobTsegGuid ## CONSUMES --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41208): https://edk2.groups.io/g/devel/message/41208 Mute This Topic: https://groups.io/mt/31717895/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 09:15:43 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+41209+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41209+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1558514123; cv=none; d=zoho.com; s=zohoarc; b=ndYwTqgJpEI9BgYSybg2ZsTwuC3VhAVtNSQZrwpW3cpjVy2KSjVjRy2bxkaUYWCOt1KpQ7xvQcxt6YnypqRYXyWDAAsALUed4WNRJ6+UH+pzrUfMi0UeNSCDmsMJbqC0DGoYyLTysJaVJdVgFO2A/lDY8BOFNIE7u3kT0O3G0tM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558514123; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=n9alDwoz7dk14acWseQA+nZnXKH4JN4swe1A8rOzevY=; b=fwDjQIo4bZMvCfaCLsHZOSNQeBwEBui/uJMpQ5KM+f5OJYYr2aCBX6FYsViBHX2VyTndXQh2x9ovHbvRfk4JGQ8rfAj/6LYlnEonTUg8TjHQycyvfk40Re84t/PNOVlmVsaF5bGQ0UmRmTPKTtGfF6S6fxKpUbXZoybyO6xWv0g= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+41209+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1558514123281132.9816954656303; Wed, 22 May 2019 01:35:23 -0700 (PDT) Return-Path: X-Received: from mga17.intel.com (mga17.intel.com []) by groups.io with SMTP; Wed, 22 May 2019 01:35:22 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 May 2019 01:35:22 -0700 X-ExtLoop1: 1 X-Received: from cchiu4-mobl1.gar.corp.intel.com ([10.5.240.31]) by fmsmga007.fm.intel.com with ESMTP; 22 May 2019 01:35:21 -0700 From: "Chiu, Chasel" To: devel@edk2.groups.io Cc: "Chasel, Chiu" , Nate DeSimone , Michael Kubacki Subject: [edk2-devel] [PATCH 2/2] KabylakeOpenBoardPkg: Add FSP Dispatch switch. Date: Wed, 22 May 2019 16:35:10 +0800 Message-Id: <20190522083510.17476-3-chasel.chiu@intel.com> In-Reply-To: <20190522083510.17476-1-chasel.chiu@intel.com> References: <20190522083510.17476-1-chasel.chiu@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chasel.chiu@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1558514122; bh=/9T9seIXnymcB2T1AnABB7RvYZxWhQwhlxFG5aF+278=; h=Cc:Date:From:Reply-To:Subject:To; b=KQ1eX5NeqXMyFQy/VHhyPH9iZfzFW1QeZU4ttOb7GZsbCTKbxJlk8Q4AjB22msI1sxY FLN4unPFCgDqDoDfxu336cNDOoB1iTqPqghmjYTBVGBevoiCVy4OHfNJFJU6nsO90GzSK 3xIn4GKBRFAFtflVjnkC2Oi5PsgPBHTc1vg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Chasel, Chiu" REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1832 Basing on PcdFspModeSelection setting either KabylakeFspBinPkg or AmberLakeFspBinPkg will be used and temporary memory arrangement will be different as AmberLakeFspBinPkg will share the same stack with boot loader. Also enlarged FSP-T size to support future larger FSP binary. Test: Booted Kabylake RVP3 to Windows successfully. Cc: Nate DeSimone Cc: Michael Kubacki Signed-off-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf | 8 = ++++---- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc | 33 = +++++++++++++++++++++++++++++---- Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc | 29 = +++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 8 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclud= e.fdf b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf index 3a28bd4109..6cb49c941c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf +++ b/Platform/Intel/KabylakeOpenBoardPkg/Include/Fdf/FlashMapInclude.fdf @@ -1,7 +1,7 @@ ## @file # FDF file of Platform. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -41,6 +41,6 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = =3D 0x00060000 SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D 0x= 00600000 # Flash addr (0xFFE00000) SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x= 000BC000 # SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D 0x= 006BC000 # Flash addr (0xFFEBC000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00004000 # -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006C0000 # Flash addr (0xFFEC0000) -SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00140000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x= 00014000 # +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D 0x= 006D0000 # Flash addr (0xFFED0000) +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D 0x= 00130000 # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 7f19ad1eed..1dfe49a7ad 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -15,7 +15,7 @@ DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg DEFINE PLATFORM_SI_PACKAGE =3D KabylakeSiliconPkg DEFINE PLATFORM_SI_BIN_PACKAGE =3D KabylakeSiliconBinPkg - DEFINE PLATFORM_FSP_BIN_PACKAGE =3D KabylakeFspBinPkg + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D AmberLakeFspBinPkg DEFINE PLATFORM_BOARD_PACKAGE =3D KabylakeOpenBoardPkg DEFINE BOARD =3D KabylakeRvp3 DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE= )/$(BOARD) @@ -24,6 +24,21 @@ # Platform On/Off features are defined here # !include OpenBoardPkgConfig.dsc + !include OpenBoardPkgPcd.dsc + +[Defines] +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # For backward compatibility API mode will use KabylakeFspBinPkg. + # KabylakeFspBinPkg only supports API mode. + # + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D KabylakeFspBinPkg +!else + # + # AmberLakeFspBinPkg supports both API and Dispatch modes + # + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D AmberLakeFspBinPkg +!endif =20 ##########################################################################= ###### # @@ -92,8 +107,20 @@ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf =20 FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf - SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf + +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # Below library are used by FSP API mode + # SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiS= iliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf +!else + # + # Below library are used by FSP Dispatch mode and non-FSP build (EDK2 bu= ild) + # + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/PeiSilic= onPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf + SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFspAml.inf +!endif =20 ConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseConfigBlockLib/BaseCon= figBlockLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/SiliconInitLib/SiliconInit= Lib.inf @@ -173,8 +200,6 @@ [LibraryClasses.X64.DXE_RUNTIME_DRIVER] ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxeRuntimeResetSystemL= ib/DxeRuntimeResetSystemLib.inf =20 -!include OpenBoardPkgPcd.dsc - [Components.IA32] =20 # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index 9774acb5eb..63d0c4c2e6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -28,6 +28,11 @@ =20 [PcdsFixedAtBuild.common] gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE + # + # 0: FSP Wrapper is running in Dispatch mode. + # 1: FSP Wrapper is running in API mode. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 =20 !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1 @@ -49,9 +54,33 @@ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 =20 +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 + # + # FSP API mode is backward compatible with earlier FSP which + # does not share stack with boot loader, so FSP needs more + # temporary memory for FSP heap + stack size. + # gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00026000 =20 + # + # In FSP API mode, FSP and boot loader runnig on different stack + # so no need to enlarge boot loader stack size. + # gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 +!else + # + # FSP Dispatch mode will share the same stack with boot loader, + # here temporary ram size is used by FSP heap and can be smaller + # + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize | 0x00010000 + + # + # In FSP Dispatch mode boot loader stack size must be big enough for exe= cuting + # both boot loader and FSP. + # + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x40000 +!endif + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x5000 gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800 gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400 --=20 2.13.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#41209): https://edk2.groups.io/g/devel/message/41209 Mute This Topic: https://groups.io/mt/31717896/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-