From nobody Thu Apr 25 12:11:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40576+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40576+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1557815100; cv=none; d=zoho.com; s=zohoarc; b=mqK99Eh6AHriuH9gu6KbNDCq6K9MLq710ZPbhI9Z+C/0nA0Nln9mLlzEaGpbE1N+me04pQwNwRVT0JM/irv6u7aAV4jV4hzqV1+n3plAg4Nk7vvm0eE3akzFJO0SoA8hb2Y91fqTD92cYo/J+G09+hfWUk4siv+dGC/IAr7yboM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557815100; h=Cc:Date:From:List-Id:List-Unsubscribe:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=1oddWOhq6wobLK0yvYHD6j48pvygwl57ZnV13KUutZk=; b=is0bwuWJrap7dzsFM5d4Y60XAJQQ6FIx0J1/TeMkDeM2ESgSF2o904C/JeFKre4/MGB2ndVam1G3AOLHYGejHirIT5FVSDwFQm8lFTsTD1qMX3Ini4tUf9IYBy3WEW7t98jehppfx/bPp5KlaiQB5d3U+w9QtaamzVa46j1UL4c= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40576+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1557815100484533.6920855573378; Mon, 13 May 2019 23:25:00 -0700 (PDT) Return-Path: X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by groups.io with SMTP; Mon, 13 May 2019 23:24:59 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 May 2019 23:24:58 -0700 X-ExtLoop1: 1 X-Received: from chenmarc-mobl.gar.corp.intel.com ([10.5.245.93]) by fmsmga008.fm.intel.com with ESMTP; 13 May 2019 23:24:57 -0700 From: "Marc W Chen" To: devel@edk2.groups.io Cc: Marc Chen , Michael Kubacki , Sai Chaganty Subject: [edk2-devel] [edk2-platform] MinPlatformPkg: Add multiple segment support for PciHostBridgeLib Date: Tue, 14 May 2019 14:24:20 +0800 Message-Id: <20190514062420.43312-1-marc.w.chen@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,marc.w.chen@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557815099; bh=tOjMBtAJ8N9m/zUTECd5LF0UD7bfV3E4Syb4TzpP0XY=; h=Cc:Date:From:Reply-To:Subject:To; b=W6fSefbGe4ktH8FwnGdc+EMEJfzzmKGzblREjfpnr6bu7C1yEbldGCvKdqddNs90z0P I5kHyN8I1OeWmhHzNIV4Oc/dsjIvd2gvVFvrW98C2W97gKlte5ytwoBAk2N5Js2fBLLPC zGiLJAiPOEY7dfZbhSNkNlGCLNo7LPkYC8I= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D1799 1. Add PcdPciSegmentCount PCD in MinPlatformPkg.dec and set default to 1 2. Base on PciHostBridge related PCDs to Initialize RootBridges. Signed-off-by: Marc Chen Cc: Michael Kubacki Cc: Sai Chaganty --- Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec | 3 +- .../PciHostBridgeLibSimple.c | 83 ++++++++++++++----= ---- .../PciHostBridgeLibSimple.inf | 4 +- 3 files changed, 59 insertions(+), 31 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index 3185776ac3..e1ae8004cb 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -6,7 +6,7 @@ # INF files to generate AutoGen.c and AutoGen.h files # for the build infrastructure. # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # This program and the accompanying materials are licensed and made availa= ble under # the terms and conditions of the BSD License which accompanies this distr= ibution. @@ -223,6 +223,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0|UIN= T32|0x90000019 gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G |FALSE|BOOL= EAN|0x4001004B gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace |FALSE|BOOL= EAN|0x4001004C gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned |FALSE|BOOL= EAN|0x4001004D + gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount |0x1 |UI= NT8|0x4001004E =20 gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x1800|UINT16= |0x00010035 gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0x0000|UINT16= |0x00010036 diff --git a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimp= le/PciHostBridgeLibSimple.c b/Platform/Intel/MinPlatformPkg/Pci/Library/Pci= HostBridgeLibSimple/PciHostBridgeLibSimple.c index 557ac2a5b3..25259e2f2d 100644 --- a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciH= ostBridgeLibSimple.c +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciH= ostBridgeLibSimple.c @@ -1,7 +1,7 @@ /** @file - SA PciHostBridge Library + PciHostBridge Library =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made availabl= e under the terms and conditions of the BSD License that accompanies this distribu= tion. The full text of the license may be found at @@ -15,6 +15,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. #include #include #include +#include #include #include #include @@ -28,7 +29,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER= EXPRESS OR IMPLIED. GLOBAL_REMOVE_IF_UNREFERENCED CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTyp= eStr[] =3D { L"Mem", L"I/O", L"Bus" }; -ACPI_HID_DEVICE_PATH mRootBridgeDeviceNode =3D { +ACPI_HID_DEVICE_PATH mRootBridgeDeviceNodeTemplate =3D { { ACPI_DEVICE_PATH, ACPI_DP, @@ -41,7 +42,7 @@ ACPI_HID_DEVICE_PATH mRootBridgeDeviceNode =3D { 0 }; =20 -PCI_ROOT_BRIDGE mRootBridge =3D { +PCI_ROOT_BRIDGE mRootBridgeTemplate =3D { 0, EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | @@ -66,41 +67,67 @@ PCI_ROOT_BRIDGE mRootBridge =3D { NULL // DevicePath; }; =20 +/** + Return all the root bridge instances. + + @param Count Return the count of root bridge instances. + + @return All the root bridge instances, it will be NULL if system has ins= ufficient memory + resources available and count will be zero. +**/ + PCI_ROOT_BRIDGE * EFIAPI PciHostBridgeGetRootBridges ( UINTN *Count ) { - mRootBridge.Mem.Base =3D PcdGet32 (PcdPciReservedMemBase); + UINT8 Index; + PCI_ROOT_BRIDGE *RootBridge; + + RootBridge =3D AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE) * PcdGet8 (Pcd= PciSegmentCount)); + if (RootBridge =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "PciHostBridge: Out of resource\n")); + *Count =3D 0; + return RootBridge; + } + + mRootBridgeTemplate.Mem.Base =3D PcdGet32 (PcdPciReservedMemBase); if (PcdGet32(PcdPciReservedMemLimit) !=3D 0) { - mRootBridge.Mem.Limit =3D PcdGet32 (PcdPciReservedMemLimit); + mRootBridgeTemplate.Mem.Limit =3D PcdGet32 (PcdPciReservedMemLimit); } else { - mRootBridge.Mem.Limit =3D (UINT32)PcdGet64 (PcdPciExpressBaseAddress); + mRootBridgeTemplate.Mem.Limit =3D (UINT32) PcdGet64 (PcdPciExpressBase= Address); } =20 - mRootBridge.MemAbove4G.Base =3D PcdGet64 (PcdPciReservedMemAbove4GBBase); - mRootBridge.MemAbove4G.Limit =3D PcdGet64 (PcdPciReservedMemAbove4GBLimi= t); + mRootBridgeTemplate.MemAbove4G.Base =3D PcdGet64 (PcdPciReservedMemAbove= 4GBBase); + mRootBridgeTemplate.MemAbove4G.Limit =3D PcdGet64 (PcdPciReservedMemAbov= e4GBLimit); =20 - mRootBridge.PMem.Base =3D PcdGet32 (PcdPciReservedPMemBase); - mRootBridge.PMem.Limit =3D PcdGet32 (PcdPciReservedPMemLimit); - mRootBridge.PMemAbove4G.Base =3D PcdGet64 (PcdPciReservedPMemAbove4GBBas= e); - mRootBridge.PMemAbove4G.Limit =3D PcdGet64 (PcdPciReservedPMemAbove4GBLi= mit); + mRootBridgeTemplate.PMem.Base =3D PcdGet32 (PcdPciReservedPMemBase); + mRootBridgeTemplate.PMem.Limit =3D PcdGet32 (PcdPciReservedPMemLimit); + mRootBridgeTemplate.PMemAbove4G.Base =3D PcdGet64 (PcdPciReservedPMemAbo= ve4GBBase); + mRootBridgeTemplate.PMemAbove4G.Limit =3D PcdGet64 (PcdPciReservedPMemAb= ove4GBLimit); =20 - if (mRootBridge.MemAbove4G.Base < mRootBridge.MemAbove4G.Limit) { - mRootBridge.AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM64_DECODE; + if (mRootBridgeTemplate.MemAbove4G.Base < mRootBridgeTemplate.MemAbove4G= .Limit) { + mRootBridgeTemplate.AllocationAttributes |=3D EFI_PCI_HOST_BRIDGE_MEM6= 4_DECODE; } =20 - mRootBridge.Io.Base =3D PcdGet16 (PcdPciReservedIobase); - mRootBridge.Io.Limit =3D PcdGet16 (PcdPciReservedIoLimit); + mRootBridgeTemplate.Io.Base =3D PcdGet16 (PcdPciReservedIobase); + mRootBridgeTemplate.Io.Limit =3D PcdGet16 (PcdPciReservedIoLimit); =20 - mRootBridge.DmaAbove4G =3D PcdGetBool (PcdPciDmaAbove4G); - mRootBridge.NoExtendedConfigSpace =3D PcdGetBool (PcdPciNoExtendedConfig= Space); - mRootBridge.ResourceAssigned =3D PcdGetBool (PcdPciResourceAssigned); + mRootBridgeTemplate.DmaAbove4G =3D PcdGetBool (PcdPciDmaAbove4G); + mRootBridgeTemplate.NoExtendedConfigSpace =3D PcdGetBool (PcdPciNoExtend= edConfigSpace); + mRootBridgeTemplate.ResourceAssigned =3D PcdGetBool (PcdPciResourceAssig= ned); + + for (Index =3D 0; Index < PcdGet8 (PcdPciSegmentCount); Index ++) { + mRootBridgeDeviceNodeTemplate.UID =3D Index; + mRootBridgeTemplate.Segment =3D Index; + mRootBridgeTemplate.DevicePath =3D NULL; + mRootBridgeTemplate.DevicePath =3D AppendDevicePathNode (NULL, &mRootB= ridgeDeviceNodeTemplate.Header); + CopyMem (RootBridge + Index, &mRootBridgeTemplate, sizeof (PCI_ROOT_BR= IDGE)); + } =20 - mRootBridge.DevicePath =3D AppendDevicePathNode (NULL, &mRootBridgeDevic= eNode.Header); - *Count =3D 1; - return &mRootBridge; + *Count =3D PcdGet8 (PcdPciSegmentCount); + return RootBridge; } =20 VOID @@ -110,7 +137,7 @@ PciHostBridgeFreeRootBridges ( UINTN Count ) { - ASSERT (Count =3D=3D 1); + ASSERT (Count <=3D PcdGet8 (PcdPciSegmentCount)); FreePool (Bridges->DevicePath); } =20 @@ -136,20 +163,20 @@ PciHostBridgeResourceConflict ( { EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; UINTN RootBridgeIndex; - DEBUG ((EFI_D_ERROR, "PciHostBridge: Resource conflict happens!\n")); + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); =20 RootBridgeIndex =3D 0; Descriptor =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; while (Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { - DEBUG ((EFI_D_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); for (; Descriptor->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR; Descript= or++) { ASSERT (Descriptor->ResType < sizeof (mPciHostBridgeLibAcpiAddressSpaceTypeStr) / sizeof (= mPciHostBridgeLibAcpiAddressSpaceTypeStr[0]) ); - DEBUG ((EFI_D_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment =3D 0x%lx / 0x%lx\n", mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType= ], Descriptor->AddrLen, Descriptor->AddrRangeMax)); if (Descriptor->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_MEM) { - DEBUG ((EFI_D_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag =3D %ld / %02x= %s\n", Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, ((Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPEC= IFIC_FLAG_CACHEABLE_PREFETCHABLE) !=3D 0) ? L" (Prefetchable)" : L"" )); diff --git a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimp= le/PciHostBridgeLibSimple.inf b/Platform/Intel/MinPlatformPkg/Pci/Library/P= ciHostBridgeLibSimple/PciHostBridgeLibSimple.inf index f9a769155b..b37488e512 100644 --- a/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciH= ostBridgeLibSimple.inf +++ b/Platform/Intel/MinPlatformPkg/Pci/Library/PciHostBridgeLibSimple/PciH= ostBridgeLibSimple.inf @@ -1,7 +1,7 @@ ## @file # Component description file for the SA PciHostBridge library # -# Copyright (c) 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
# # This program and the accompanying materials are licensed and made availa= ble under # the terms and conditions of the BSD License which accompanies this distr= ibution. @@ -56,4 +56,4 @@ gMinPlatformPkgTokenSpaceGuid.PcdPciDmaAbove4G gMinPlatformPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace gMinPlatformPkgTokenSpaceGuid.PcdPciResourceAssigned - + gMinPlatformPkgTokenSpaceGuid.PcdPciSegmentCount --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40576): https://edk2.groups.io/g/devel/message/40576 Mute This Topic: https://groups.io/mt/31615801/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-