From nobody Sun May 5 03:25:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39966+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39966+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1556928446; cv=none; d=zoho.com; s=zohoarc; b=N1i+uTfkF8JSLznic3ks+hlL7V1n8cus4OqRnGamgWPp/rGVj+P6zHK9A/HmlTV572KwdTA8UkM2i9tUgIewRpZKMPCTE7+/HmHmhBTCdnZKOZUGfT25OtCKhmpCmN1zJ3KYx4Uuw7qSO2e+PKCcv7T7KoWOP4IrPtwb6DUzgoY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556928446; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=EKPeyvpZ9dGQggcONVnp4Nwz0lWJen7ZXANvLyWMEdI=; b=fSlqmnniC/CJ6aBMbewJSp4slVEfYXvM/t3ql+tau4sWu+X5uj34KOlekP47bV8uVxY7S7GrSp7Qe6eShQCNoqhfqswnplwlnbpSGHMJHWGGIH96Scup7Yr4AxwLzxHgvm8CL/OdhjmaQglLGqwQYoIfRhfEf1SHFsy8SGX5nh0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39966+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556928446853660.6646102420926; Fri, 3 May 2019 17:07:26 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Fri, 03 May 2019 17:07:26 -0700 X-Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 9E08820277; Sat, 4 May 2019 00:07:25 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-107.rdu2.redhat.com [10.10.121.107]) by smtp.corp.redhat.com (Postfix) with ESMTP id BD2895D9C4; Sat, 4 May 2019 00:07:23 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH 1/4] OvmfPkg/PlatformPei: assign PciSize on both i440fx/q35 branches explicitly Date: Sat, 4 May 2019 02:07:12 +0200 Message-Id: <20190504000716.7525-2-lersek@redhat.com> In-Reply-To: <20190504000716.7525-1-lersek@redhat.com> References: <20190504000716.7525-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.29]); Sat, 04 May 2019 00:07:25 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556928446; bh=GeS6XTG0lo+R9X9oztkKeUNpDBT0kU9R05UDJOjq/Aw=; h=Cc:Date:From:Reply-To:Subject:To; b=cxqAQsXXFT1q6wtHBW5gDPR5O58vASdmmvwn9/hNhJVwCh2507xz5eCVhGR64i5QAWd boN5SFGaDrcmGJKOgHRwWVMsGcSAYm+yJjtRrjLW3mQIHQkMtynvMwemVOyJ8QwZ/4h9f F9NT9gTyiov3q4sEoEzep8MoX8BF0DMLLIc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" In the MemMapInitialization() function, we currently have a common PciSize assignment, shared between i440fx and q35. In order to simplify the rest of this series, lift and duplicate the assignment identically to both board-specific branches. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1666941 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1701710 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- OvmfPkg/PlatformPei/Platform.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 0876316eefbc..5e0a15484230 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -190,8 +190,10 @@ MemMapInitialization ( ASSERT (TopOfLowRam <=3D PciExBarBase); ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); + PciSize =3D 0xFC000000 - PciBase; } else { PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; + PciSize =3D 0xFC000000 - PciBase; } =20 // @@ -207,7 +209,6 @@ MemMapInitialization ( // 0xFED20000 gap 896 KB // 0xFEE00000 LAPIC 1 MB // - PciSize =3D 0xFC000000 - PciBase; AddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39966): https://edk2.groups.io/g/devel/message/39966 Mute This Topic: https://groups.io/mt/31489696/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 03:25:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39967+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39967+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1556928449; cv=none; d=zoho.com; s=zohoarc; b=bZjqpjlKoNeieHiQQ79m1D9w+tEHs4y4zqy+E69K4QKSs4Y83oDJqmQCtZa06VIhH0DQj5EyG6vL0+TIyB4k1AdIlvylBb0jZqW5cdrIwlufW7FLYiucU8xnVRu3qh0XLk+YFwO/DxHgQLnIjLGkjZv0djKeu6NwFrhfmb60OQY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556928449; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=jjNX4mSPbdH26tQRsPgjWPQhbAKH+COxHKRRflAaCqs=; b=mf02tzYmMpCo6gvzuhCTRuVO9PnTHe2FjVGZPLT15N6iRaKy7wuhHHgeQ37tG2OSn3OjeHwROwJ00URfLxWAMcqgJR9bLNA1f4Bmk+p5/g6CDmw9hX/fEsEZi/LjgCrZKQm3ash8DZNypYcfBX13u5zQAzJPHk7CQzaL30Ht5H4= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39967+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556928449106512.8439520150213; Fri, 3 May 2019 17:07:29 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Fri, 03 May 2019 17:07:28 -0700 X-Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id F3E67307D911; Sat, 4 May 2019 00:07:27 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-107.rdu2.redhat.com [10.10.121.107]) by smtp.corp.redhat.com (Postfix) with ESMTP id 38B855DA35; Sat, 4 May 2019 00:07:25 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH 2/4] OvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching Date: Sat, 4 May 2019 02:07:13 +0200 Message-Id: <20190504000716.7525-3-lersek@redhat.com> In-Reply-To: <20190504000716.7525-1-lersek@redhat.com> References: <20190504000716.7525-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.48]); Sat, 04 May 2019 00:07:28 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556928448; bh=mCflQCBJkgyDK1gXZ/n7w/4trYW0oIC7QEIZSwfNzYs=; h=Cc:Date:From:Reply-To:Subject:To; b=PLd0ADu09cOS7M25sNvfWbnNQMDIbXi3J55U/QsVFUXT0F9djr/7g2bce+J7dg2bGEN VFimjp08+i1GRtHluLFwDNlFaBIkmJXsxoyfJ2rPXYmEpYSl/c47GhLaQ6cPeOhVj9JHt asy6WC2aYP3trT+JyQFrhdkQeM+t+zjvWkM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" In the MemMapInitialization() function, we currently assign PciBase different values, on both branches of the board type check. Hoist the PciBase assignment from the i440fx branch in front of the "if". This is a no-op for the i440fx branch. On the q35 branch, we overwrite this value, hence the change is a no-op on q35 as well. This is another refactoring for simplifying the rest of this series. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1666941 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1701710 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- OvmfPkg/PlatformPei/Platform.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 5e0a15484230..9c013613a1a0 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -181,6 +181,7 @@ MemMapInitialization ( =20 TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); PciExBarBase =3D 0; + PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // // The MMCONFIG area is expected to fall between the top of low RAM = and @@ -192,7 +193,6 @@ MemMapInitialization ( PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); PciSize =3D 0xFC000000 - PciBase; } else { - PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; PciSize =3D 0xFC000000 - PciBase; } =20 --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39967): https://edk2.groups.io/g/devel/message/39967 Mute This Topic: https://groups.io/mt/31489697/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 03:25:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39968+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39968+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1556928451; cv=none; d=zoho.com; s=zohoarc; b=XELCL19up7rM6WFCYezq4PJz0lyiJD4W15xoE8u8hH8MBkhLQvAQhPeg4xTbv80iyVUYgFLzXEX0p8TC2iVX16DXTb/jp/HwarX/fHivdy5r4Idq8xshITTx8+aMWjmcfQa41T6PXLyCTtu0q7WCpKlfDKEyoxrUnfY69hvqb4E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556928451; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=SZA5UocOMV4qeyvJKCpcRnveq/7eCZ8y3f0U4UJpZjw=; b=fAdEQ1zniwumfX/pnBUpZbVXunA7xo3HBENI1bCrQ0rsPQcVvn6f/0OBaZkZdACxfNXAhJaEdiq8da5+wWMvX5PqavekJxXC/qYQbr80v8nfNQeOvhIezizPPw9/2Btx5Sy+GMsTQvz36XgijA91jXPIX45keCU92I3K1ST5JX0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39968+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556928451677364.46811552789495; Fri, 3 May 2019 17:07:31 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Fri, 03 May 2019 17:07:30 -0700 X-Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 709BD309265B; Sat, 4 May 2019 00:07:30 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-107.rdu2.redhat.com [10.10.121.107]) by smtp.corp.redhat.com (Postfix) with ESMTP id 8FFFC5D9C4; Sat, 4 May 2019 00:07:28 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH 3/4] OvmfPkg/PlatformPei: reorder the 32-bit PCI hole vs. the PCIEXBAR on q35 Date: Sat, 4 May 2019 02:07:14 +0200 Message-Id: <20190504000716.7525-4-lersek@redhat.com> In-Reply-To: <20190504000716.7525-1-lersek@redhat.com> References: <20190504000716.7525-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.43]); Sat, 04 May 2019 00:07:30 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556928451; bh=3BoN0IBjxp98kjx9S0eIhk+/GERX5JKWQzCRNTWahPU=; h=Cc:Date:From:Reply-To:Subject:To; b=Ln2DaykTAJZhBOyVwMfkWiuP+xtfc9xwQG3r4Y4RThNQWDhDm4Gu0IUyTM7M2RHi59b qtMpEVNiFLataqexDot2SC2Nb9tza2tAXcPY6bh52pFIJTvdvxHX8LJmv4ge+NssdA6po +9CF0UpA0Bc2FraD43hwACCuhEl5l3amDWo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Commit 7b8fe63561b4 ("OvmfPkg: PlatformPei: enable PCIEXBAR (aka MMCONFIG / ECAM) on Q35", 2016-03-10) claimed that, On Q35 machine types that QEMU intends to support in the long term, QEMU never lets the RAM below 4 GB exceed 2 GB. Alas, this statement came from a misunderstanding that occurred while we worked out the interface contract. In fact QEMU does allow the 32-bit RAM extend up to 0xB000_0000 (exclusive), in case the RAM size falls in the range (0x8000_0000, 0xB000_0000) (i.e., the RAM size is greater than 2048MB and smaller than 2816MB). In turn, such a RAM size (justifiedly) triggers ASSERT (TopOfLowRam <=3D PciExBarBase); in MemMapInitialization(), because we placed the 256MB PCIEXBAR at 0x8000_0000 (2GB) exactly, relying on the interface contract. (And, the 32-bit PCI hole would follow the PCIEXBAR, covering the [0x9000_0000, 0xFC00_0000) range.) In order to fix this, reorder the 32-bit PCI hole against the PCIEXBAR, as follows: - start the 32-bit PCI hole where it starts on i440fx as well, that is, at 2GB or TopOfLowRam, whichever is higher; - unlike on i440fx, where the 32-bit PCI hole extends up to 0xFC00_0000, stop it at 0xE000_0000 on q35, - place the PCIEXBAR at 0xE000_0000. (We cannot place the PCIEXBAR at 0xF000_0000 because the 256MB MMIO area that starts there is not entirely free.) Before this patch, the 32-bit PCI hole used to only *end* at the same spot (namely, 0xFC00_0000) between i440fx and q35; now it will only *start* at the same spot (namely, 2GB or TopOfLowRam, whichever is higher) between both boards. On q35, the maximal hole shrinks from 0xFC00_0000 - 0x9000_0000 =3D 0x6C00_0000 =3D=3D 1728 MB to 0xE000_0000 - 0x8000_0000 =3D=3D 1536 MB. We lose 192 MB of the aperture; however, the aperture is now aligned at 1GB, rather than 256 MB, and so it could fit a 1GB BAR even. Regarding the minimal hole (triggered by RAM size 2815MB), its size is 0xE000_0000 - 0xAFF0_0000 =3D 769 MB which is not great, but probably better than a failed ASSERT. Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1666941 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1701710 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/OvmfPkgIa32.dsc | 5 +---- OvmfPkg/OvmfPkgIa32X64.dsc | 5 +---- OvmfPkg/OvmfPkgX64.dsc | 5 +---- OvmfPkg/PlatformPei/Platform.c | 9 ++++----- 4 files changed, 7 insertions(+), 17 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 36a0f87258dd..bb55b6fa58e1 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -491,10 +491,7 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - # - # On Q35 machine types that QEMU intends to support in the long term, QE= MU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 9b341e17d7ff..06c394a6fb1f 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -496,10 +496,7 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - # - # On Q35 machine types that QEMU intends to support in the long term, QE= MU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index a0f87f74dab9..5e0eb043fab9 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -496,10 +496,7 @@ [PcdsFixedAtBuild] # This PCD is used to set the base address of the PCI express hierarchy.= It # is only consulted when OVMF runs on Q35. In that case it is programmed= into # the PCIEXBAR register. - # - # On Q35 machine types that QEMU intends to support in the long term, QE= MU - # never lets the RAM below 4 GB exceed 2 GB. - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000 + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 =20 !ifdef $(SOURCE_DEBUG_ENABLE) gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 9c013613a1a0..fd8eccaf3e50 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -184,14 +184,13 @@ MemMapInitialization ( PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // - // The MMCONFIG area is expected to fall between the top of low RAM = and - // the base of the 32-bit PCI host aperture. + // The 32-bit PCI host aperture is expected to fall between the top = of + // low RAM and the base of the MMCONFIG area. // PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT (TopOfLowRam <=3D PciExBarBase); + ASSERT (PciBase < PciExBarBase); ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); - PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); - PciSize =3D 0xFC000000 - PciBase; + PciSize =3D (UINT32)(PciExBarBase - PciBase); } else { PciSize =3D 0xFC000000 - PciBase; } --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39968): https://edk2.groups.io/g/devel/message/39968 Mute This Topic: https://groups.io/mt/31489698/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 03:25:30 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39969+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39969+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1556928454; cv=none; d=zoho.com; s=zohoarc; b=HR9fY3pZ9ddpUYm1crpegtU76XNcIzg/sa+dDybSV+NPUFVwDwUL79mg6t8wTzU5ELJOnyvFXp+0FaBtb4voSXjrPAtZFZcEqOEdp8FS8F2Mt5DCcm1X/4nUi2zGZhqZFI+5EWtGjfdquF3rGHT2bL/r05OlRAylRzYTuzrcUL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556928454; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=csxLNdwtblfi+J5lE56Hh0WKeceya4B6uEDUfVugXKI=; b=A3Z6XeJFHR6O2n5C2MKTHIPIZnKBTNSV3f4h5ZuwRtGLA72v/N1TgS2L0xxOis4/oDAhVPeHB+3VKmjQxrUQVhWQPvTVf4O39F1E7GcGrtjeVZ1IX4kXLSNTgCEb2bzWV7EPWUZHCw/CxJRrgEk0SckPpdroGYWIgcLM5jMpN5M= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39969+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556928454097374.80682799625083; Fri, 3 May 2019 17:07:34 -0700 (PDT) Return-Path: X-Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by groups.io with SMTP; Fri, 03 May 2019 17:07:33 -0700 X-Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E3CFD3091749; Sat, 4 May 2019 00:07:32 +0000 (UTC) X-Received: from lacos-laptop-7.usersys.redhat.com (ovpn-121-107.rdu2.redhat.com [10.10.121.107]) by smtp.corp.redhat.com (Postfix) with ESMTP id 0AC245D9C4; Sat, 4 May 2019 00:07:30 +0000 (UTC) From: "Laszlo Ersek" To: edk2-devel-groups-io Cc: Ard Biesheuvel , Gerd Hoffmann , Jordan Justen Subject: [edk2-devel] [PATCH 4/4] OvmfPkg/PlatformPei: fix MTRR for low-RAM sizes that have many bits clear Date: Sat, 4 May 2019 02:07:15 +0200 Message-Id: <20190504000716.7525-5-lersek@redhat.com> In-Reply-To: <20190504000716.7525-1-lersek@redhat.com> References: <20190504000716.7525-1-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.41]); Sat, 04 May 2019 00:07:32 +0000 (UTC) Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lersek@redhat.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556928453; bh=9UibNHrMKCw2qUMVjf1g1S22w1sYdQXQG5JGb79NCv0=; h=Cc:Date:From:Reply-To:Subject:To; b=wUb3CzNQ7nH87+DJdPXps7GvhfHIV9S1Ex0enYFOyg8Vi8zZlq52wH0Trjkwwka7DMD Wpfno/UPixg6PUaJBUWhLs9RNPlqR4yrBVntVXAY5IoP3NsYxG8dq1vFJ1LBfOFQHQ9eN RRotNNFeCC9jmB1xXH52Vtf/gEskZA8Nt9A= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Assume that we boot OVMF in a QEMU guest with 1025 MB of RAM. The following assertion will fire: > ASSERT_EFI_ERROR (Status =3D Out of Resources) > ASSERT OvmfPkg/PlatformPei/MemDetect.c(696): !EFI_ERROR (Status) That's because the range [1025 MB, 4 GB) that we try to mark as uncacheable with MTRRs has size 3071 MB: 0x1_0000_0000 -0x0_4010_0000 -------------- 0x0_BFF0_0000 The integer that stands for the uncacheable area size has 11 (eleven) bits set to 1. As a result, covering this size requires 11 variable MTRRs (each MTRR must cover a naturally aligned, power-of-two sized area). But, if we need more variable MTRRs than the CPU can muster (such as 8), then MtrrSetMemoryAttribute() fails, and we refuse to continue booting (which is justified, in itself). Unfortunately, this is not difficult to trigger, and the error message is well-hidden from end-users, in the OVMF debug log. The following mitigation is inspired by SeaBIOS: Truncate the uncacheable area size to a power-of-two, while keeping the end fixed at 4 GB. Such an interval can be covered by just one variable MTRR. This may leave such an MMIO gap, between the end of low-RAM and the start of the uncacheable area, that is marked as WB (through the MTRR default). Raise the base of the 32-bit PCI MMIO aperture accordingly -- the gap will not be used for anything. On Q35, the minimal 32-bit PCI MMIO aperture (triggered by RAM size 2815 MB) shrinks from 0xE000_0000 - 0xAFF0_0000 =3D 769 MB to 0xE000_0000 - 0xC000_0000 =3D 512 MB On i440fx, the minimal 32-bit PCI MMIO aperture (triggered by RAM size 3583 MB) shrinks from 0xFC00_0000 - 0xDFF0_0000 =3D 449 MB to 0xFC00_0000 - 0xE000_0000 =3D 448 MB Cc: Ard Biesheuvel Cc: Gerd Hoffmann Cc: Jordan Justen Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1666941 Ref: https://bugzilla.redhat.com/show_bug.cgi?id=3D1701710 Signed-off-by: Laszlo Ersek Reviewed-by: Ard Biesheuvel Reviewed-by: Philippe Mathieu-Daude --- OvmfPkg/PlatformPei/Platform.h | 2 ++ OvmfPkg/PlatformPei/MemDetect.c | 23 +++++++++++++++++--- OvmfPkg/PlatformPei/Platform.c | 4 +--- 3 files changed, 23 insertions(+), 6 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 81af8b71480f..4476ddd871cd 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -114,4 +114,6 @@ extern UINT32 mMaxCpuCount; =20 extern UINT16 mHostBridgeDevId; =20 +extern UINT32 mQemuUc32Base; + #endif // _PLATFORM_PEI_H_INCLUDED_ diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index e890e36408a6..ae73c63d27d5 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -42,6 +42,8 @@ STATIC UINT32 mS3AcpiReservedMemorySize; =20 STATIC UINT16 mQ35TsegMbytes; =20 +UINT32 mQemuUc32Base; + VOID Q35TsegMbytesInitialization ( VOID @@ -663,6 +665,8 @@ QemuInitializeRam ( // cover it exactly. // if (IsMtrrSupported ()) { + UINT32 Uc32Size; + MtrrGetAllMtrrs (&MtrrSettings); =20 // @@ -689,11 +693,24 @@ QemuInitializeRam ( =20 // // Set memory range from the "top of lower RAM" (RAM below 4GB) to 4GB= as - // uncacheable + // uncacheable. Make sure one variable MTRR suffices by truncating the= size + // to a whole power of two. This will round the base *up*, and a gap (= not + // used for either RAM or MMIO) may stay in the middle, marked as + // cacheable-by-default. // - Status =3D MtrrSetMemoryAttribute (LowerMemorySize, - SIZE_4GB - LowerMemorySize, CacheUncacheable); + Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize)); + mQemuUc32Base =3D (UINT32)(SIZE_4GB - Uc32Size); + if (mQemuUc32Base !=3D LowerMemorySize) { + DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, = for " + "an UC32 size of 0x%x\n", __FUNCTION__, (UINT32)LowerMemorySize, + mQemuUc32Base, Uc32Size)); + } + + Status =3D MtrrSetMemoryAttribute (mQemuUc32Base, Uc32Size, + CacheUncacheable); ASSERT_EFI_ERROR (Status); + } else { + mQemuUc32Base =3D (UINT32)LowerMemorySize; } } =20 diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index fd8eccaf3e50..c064b4ed9b8f 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -174,14 +174,12 @@ MemMapInitialization ( AddIoMemoryRangeHob (0x0A0000, BASE_1MB); =20 if (!mXen) { - UINT32 TopOfLowRam; UINT64 PciExBarBase; UINT32 PciBase; UINT32 PciSize; =20 - TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); PciExBarBase =3D 0; - PciBase =3D (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam; + PciBase =3D (mQemuUc32Base < BASE_2GB) ? BASE_2GB : mQemuUc32Base; if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { // // The 32-bit PCI host aperture is expected to fall between the top = of --=20 2.19.1.3.g30247aa5d201 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39969): https://edk2.groups.io/g/devel/message/39969 Mute This Topic: https://groups.io/mt/31489699/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-