From nobody Fri May 10 00:23:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39905+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39905+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1556790516; cv=none; d=zoho.com; s=zohoarc; b=G7JmPOGpGA3ax9LBOKF5Sr2XBTvo9aqHAqJtGaS9w0PlFHy5RlDkkehHJg4Je+XvSVnqdgO9ITHqyfhuCFGqcd2HOU0Kl6HWs8zIlC3cdsPKlaMhfvEzPNfTMpa6bSmcK6PfTiMC2FEr2yQAWTVJfA9K9mMswRKnRTAWWk5p2w0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556790516; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=5zgRHqi/Mw7IHw+14akJuPgAzlGFUJQcaKMyvsb9w4E=; b=d1vQNoymAMLHdBuLFI/5AFP/BeyPVgqNfNHeZcpHLigPjhWYMqJsIrje0jSzj7FwirLcaS2jJ2paUgtu8Axnp1fY1mj4AIzHm4YX2uYeTirv+3qcEbrdlO/160ps6F0nKE2hDem2yD9igFqAtmbn+w11F5oviKnAohl7CDGGLwQ= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39905+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556790516256653.0281107238627; Thu, 2 May 2019 02:48:36 -0700 (PDT) Return-Path: X-Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) by groups.io with SMTP; Thu, 02 May 2019 02:48:34 -0700 X-Received: by mail-wm1-f65.google.com with SMTP id n25so1738580wmk.4 for ; Thu, 02 May 2019 02:48:33 -0700 (PDT) X-Gm-Message-State: APjAAAUfGcG1iUfeckV/vJbEaNvW7p5qC315dEuj8Orf1deIZu6+tklO 17UDKn2tbWlQGPZPIL2rVYtNjPWLJK/J9A== X-Google-Smtp-Source: APXvYqxy92d6HRhKu85ZNUXiXnpOCaMDmGTPBijsiZF0nFFC/nO/PGEpJY0qlmw4RJ73vz80neCAgA== X-Received: by 2002:a7b:c954:: with SMTP id i20mr1629970wml.59.1556790511932; Thu, 02 May 2019 02:48:31 -0700 (PDT) X-Received: from sudo.home ([2a01:cb1d:112:6f00:2dc9:bac0:dc74:9979]) by smtp.gmail.com with ESMTPSA id h123sm9819231wme.6.2019.05.02.02.48.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 02 May 2019 02:48:30 -0700 (PDT) From: "Ard Biesheuvel" To: devel@edk2.groups.io Cc: leif.lindholm@linaro.org, graeme.gregory@linaro.org, Ard Biesheuvel Subject: [edk2-devel] [PATCH edk2-platforms v2] Silicon/SynQuacer: add ACPI description of GPIO controller and power button Date: Thu, 2 May 2019 11:48:26 +0200 Message-Id: <20190502094826.6550-1-ard.biesheuvel@linaro.org> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ard.biesheuvel@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556790515; bh=6OOOaPDNLHALpza+v5djVZx5lukuA4kTW8h0QOh0JbE=; h=Cc:Date:From:Reply-To:Subject:To; b=p899FCUJGto4DDxEJFAJ0nG9/Q7D+Cj6oOpOQz34DMLWd4p3VFCMjT67jyizFVucg4W UxvHg9TPrkkxDvAm6btsA+YGf2r2twhxTRrVXOK09EA8HMPZqt4qUY3wQqRumgXs+pHT7 a5u9hnp29eSVqq8ehGx82aXK8Pqf76XDNBc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Add ACPI descriptions of the GPIO and external interrupt (EXIU) controllers as well as the power button. Note that on rev 0.3 boards, the power button appears to reset the system (this was not the case on rev 0.1 boards), so it is included for reference primarily. The same GPIO event mechanism will be used in the future for reporting hardware errors to the OS. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Acked-by: Leif Lindholm --- v2: split EXIU interrupt controller and GPIO controller into separate devic= es, and mirror the incoming GPIO interrupt with a interrupt resource pointi= ng to the EXIU - this is a more accurate depiction of the situation, given that not all EXIU interrupt lines are connected to GPIO lines Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl | 56 ++++++++++++= ++++++++ Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 4 ++ 2 files changed, 60 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl b/Silicon/Soci= onext/SynQuacer/AcpiTables/Dsdt.asl index aab4fbf0e6b4..44cdf6568991 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/Dsdt.asl @@ -201,5 +201,61 @@ DefinitionBlock ("DsdtTable.aml", "DSDT", 1, "SNI", "S= YNQUACR", } }) } + + Device (EXIU) { + Name (_HID, "SCX0008") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_EXIU_BASE, SYNQUACER_EXIU_SIZE) + }) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "socionext,spi-base", 112 }, + } + }) + } + + Device (GPIO) { + Name (_HID, "SCX0007") + Name (_UID, Zero) + Name (_CRS, ResourceTemplate () { + Memory32Fixed (ReadWrite, SYNQUACER_GPIO_BASE, SYNQUACER_GPIO_SIZE) + Interrupt (ResourceConsumer, Edge, ActiveLow, ExclusiveAndWake, 0,= "\\_SB.EXIU") { + 8, + } + }) + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { + "gpio-line-names", + Package () { + "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4", + "DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8", + "PSIN#", "PWROFF#", "GPIO-A", "GPIO-B", + "GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT", + "PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F", + "GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J", + "GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27", + "PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31" + }, + } + } + }) + Name (_AEI, ResourceTemplate () { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullDefault, 0, "\\_SB= .GPIO") + { + 8 + } + }) + Method (_E08) { + Notify (\_SB.PWRB, 0x80) + } + } + + Device (PWRB) { + Name (_HID, "PNP0C0C") + } } // Scope (_SB) } diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h b/Sil= icon/Socionext/SynQuacer/Include/Platform/MemoryMap.h index b0fcc306c1ae..cff981c4f8ae 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h @@ -42,6 +42,10 @@ #define SYNQUACER_GPIO_BASE 0x51000000 #define SYNQUACER_GPIO_SIZE SIZE_4KB =20 +// EXIU interrupt controller +#define SYNQUACER_EXIU_BASE 0x510c0000 +#define SYNQUACER_EXIU_SIZE 0x20 + // I2C0 block #define SYNQUACER_I2C0_BASE 0x51200000 #define SYNQUACER_I2C0_SIZE SIZE_4KB --=20 2.20.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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