From nobody Mon May 13 15:58:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39612+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39612+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1556247708; cv=none; d=zoho.com; s=zohoarc; b=aP0AldtDMoWw6NVgn6x1OwD1m30JKdv3MqFhMevmSTCFHR8y9PWGQGlntkjjudu7RAWqWKpP9QVU9T9ZoUlNne45zRAiELsREYp9VyNvsBf+b7REfe6t0ZY4L5dNsaQ5p8vUGh9lGmImiITUIpBz1ip2mbPPWLaVTOErCK6ISGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556247708; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=GAo+oYzbuNnqfQ/SrXHQkCrx1hCAsyxJzd45/xavyCQ=; b=Me//RbHgN7RiNsy+QZYiE/DPX3KJakTCdZlAgIyrVEafFBl0peqM8WNubIGAge/qM+rH0MRyMg34AiXHaxTPpdqKFtx9J0vQ2RHsUpoIJUeMPgBNxPzq0CMVrP4VYMfMBpg6h1iMe8oVadMMHExbHuuynwMxDLgz3l3vPqrDpyE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39612+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556247708667510.12152025407147; Thu, 25 Apr 2019 20:01:48 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Thu, 25 Apr 2019 20:01:48 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Apr 2019 20:01:47 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,395,1549958400"; d="scan'208";a="340896370" X-Received: from shenglei-dev.ccr.corp.intel.com ([10.239.158.52]) by fmsmga005.fm.intel.com with ESMTP; 25 Apr 2019 20:01:46 -0700 From: "Zhang, Shenglei" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel Subject: [edk2-devel] [PATCH v2 1/4] OvmfPkg/PlatformBootManagerLib: Remove dependency on Mps.h Date: Fri, 26 Apr 2019 11:01:39 +0800 Message-Id: <20190426030142.7880-2-shenglei.zhang@intel.com> In-Reply-To: <20190426030142.7880-1-shenglei.zhang@intel.com> References: <20190426030142.7880-1-shenglei.zhang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,shenglei.zhang@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556247708; bh=6Sbe1XIHQziRZV0cZ2aTZ6RG0ggufmLjc4ztBQBadHk=; h=Cc:Date:From:Reply-To:Subject:To; b=VFd9507Tpexuyj2Z1k0DKMlTJx/wZWGvLyY61PPmhfvHqBBJdOifShxk99ScJrzAyEE 0jYPNxFbCsf/1g3RqWIUEejhwzjBpJQtf3HIGUndNUGNEexX1UnbUZuVXg0BzRhP+dHQr MxJFOlOqqsPIqqg62KBbWL0m4eEZzexPH/Q= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Mps.h is included in BdsPlatform.h but not actually used. So remove it. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang Reviewed-by: Laszlo Ersek --- OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h | 1 - 1 file changed, 1 deletion(-) diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h b/OvmfPkg= /Library/PlatformBootManagerLib/BdsPlatform.h index da6dd86616..49a072b400 100644 --- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h +++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.h @@ -57,7 +57,6 @@ Abstract: =20 #include #include -#include #include #include #include --=20 2.18.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39612): https://edk2.groups.io/g/devel/message/39612 Mute This Topic: https://groups.io/mt/31349516/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 13 15:58:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39613+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39613+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1556247710; cv=none; d=zoho.com; s=zohoarc; b=WMQeBncDIn2mAU5AMeRqh8c5sSv9TC6HqhOT3KRXPJ3cCOL3bKyhwIVYdJqaPAo2FQXp8EOn0rIP12j5gZN6JHsiSL2jcFqqf2rJBMTN6k9wR0Ldjf8JvQtJ8T4i/hhc4ofVTO8bRAW+74HyCemMYNZuUAzz5Qa15aAWd02qDfA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556247710; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=0F+J4Lwx1mrqUBBQeHm9Ar0Vxk5W9a1gOEVSMenficU=; b=bFX0Cqfcxhui4FYcocQcGF9wT/EARHQP5EF7T0bwaiaCaLK/CKN+6LNi0QKEVeqev7JxzXeBwaZnEHXKG5gmtvH9Lz8GXwIObSxbdDyXWUUNY0tRkEHyhy1d+lRvE7Bsfqs+QRfo8Z60365sYVALV3q0S38R82g+p/Ys80Jrpq0= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39613+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556247710135362.98987893402045; Thu, 25 Apr 2019 20:01:50 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Thu, 25 Apr 2019 20:01:49 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Apr 2019 20:01:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,395,1549958400"; d="scan'208";a="340896386" X-Received: from shenglei-dev.ccr.corp.intel.com ([10.239.158.52]) by fmsmga005.fm.intel.com with ESMTP; 25 Apr 2019 20:01:48 -0700 From: "Zhang, Shenglei" To: devel@edk2.groups.io Cc: Jaben Carsey , Ray Ni Subject: [edk2-devel] [PATCH v2 2/4] ShellPkg/UefiShellDebug1CommandsLib Date: Fri, 26 Apr 2019 11:01:40 +0800 Message-Id: <20190426030142.7880-3-shenglei.zhang@intel.com> In-Reply-To: <20190426030142.7880-1-shenglei.zhang@intel.com> References: <20190426030142.7880-1-shenglei.zhang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,shenglei.zhang@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556247709; bh=22l/cknsM/eLzlN2MTE+IKbVS1UJpoy6MzmSaxdgymY=; h=Cc:Date:From:Reply-To:Subject:To; b=ILAqmQgvubFqVOmmYcCIPlTzrQdS9hX93eqFnLWbnxBgxaNUug8eV8EV+8qhxGpCWH/ VWEgOscDXoaZchnU17y+w/Uedy6WfLhHjK4HJmGKHqhoc1as/W+XD56wvSGhsqPsxYYjV Z9NRO448x8i3+3DNBhhEevcEFoFYJbT8+4k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" With Itanium architecture unsupported, gEfiSalSystemTableGuid and gEfiMpsTableGuid will be no longer used. https://bugzilla.tianocore.org/show_bug.cgi?id=3D1560 v2:Withdraw the removal of #include and gEfiMpsTableGuid. Cc: Jaben Carsey Cc: Ray Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang Reviewed-by: Ray Ni --- ShellPkg/Library/UefiShellDebug1CommandsLib/Dmem.c | 5 ----- .../UefiShellDebug1CommandsLib.inf | 1 - 2 files changed, 6 deletions(-) diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/Dmem.c b/ShellPkg/= Library/UefiShellDebug1CommandsLib/Dmem.c index 59eee3082a..e6aec2e37c 100644 --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/Dmem.c +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/Dmem.c @@ -13,7 +13,6 @@ #include #include #include -#include =20 /** Make a printable character. @@ -180,10 +179,6 @@ ShellCommandRunDmem ( AcpiTableAddress =3D (UINT64)(UINTN)gST->ConfigurationTable[= TableWalker].VendorTable; continue; } - if (CompareGuid(&gST->ConfigurationTable[TableWalker].VendorGu= id, &gEfiSalSystemTableGuid)) { - SalTableAddress =3D (UINT64)(UINTN)gST->ConfigurationTable[T= ableWalker].VendorTable; - continue; - } if (CompareGuid(&gST->ConfigurationTable[TableWalker].VendorGu= id, &gEfiSmbiosTableGuid)) { SmbiosTableAddress =3D (UINT64)(UINTN)gST->ConfigurationTabl= e[TableWalker].VendorTable; continue; diff --git a/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Com= mandsLib.inf b/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1C= ommandsLib.inf index 2c8894a2cd..ed94477a06 100644 --- a/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLi= b.inf +++ b/ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLi= b.inf @@ -126,7 +126,6 @@ gEfiSmbiosTableGuid ## SOMETIMES_CONSUMES ## SystemTable gEfiSmbios3TableGuid ## SOMETIMES_CONSUMES ## SystemTable gEfiMpsTableGuid ## SOMETIMES_CONSUMES ## SystemTable - gEfiSalSystemTableGuid ## SOMETIMES_CONSUMES ## SystemTable gEfiAcpi10TableGuid ## SOMETIMES_CONSUMES ## SystemTable gEfiAcpi20TableGuid ## SOMETIMES_CONSUMES ## SystemTable gShellDebug1HiiGuid ## SOMETIMES_CONSUMES ## HII --=20 2.18.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39613): https://edk2.groups.io/g/devel/message/39613 Mute This Topic: https://groups.io/mt/31349517/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 13 15:58:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39614+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39614+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1556247711; cv=none; d=zoho.com; s=zohoarc; b=P7RMAdLGmKiq4maBQjyX0jizw+qKwQ2CC9w7E1kY3BDIsMLudPsruZ23TouzV7StXvd9m4ZK+A9CWIHiCI8FwhlqzsW9Puk+jFNVsBsbHFtbn/1q5oiHJNiaeFXCskkz67aqija5RYFOLcS5y+TjzGmY8LWY/6YwcX+IeW7Pauc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556247711; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=q8if5UeuaKYVEDEKvTG2UyrBJMS6GwqsHv218vYcWuE=; b=QRBAcUHDRXouxQkuw7Wr5sBWHi16XuuyoYjN0HHd3jf+6nwG0L6w2j62/i0xk5XVzZ+Hc5s34s0q28CLl6auvz4a1kMJKjimz3GBpkEBqmQmpMwOGdL28LLkcu76jg1YUtXgyBzgFDTnMNva7WyNgBnom66Sh0TIaDnjR3E8J/w= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39614+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556247711874579.7558936763112; Thu, 25 Apr 2019 20:01:51 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Thu, 25 Apr 2019 20:01:51 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Apr 2019 20:01:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,395,1549958400"; d="scan'208";a="340896394" X-Received: from shenglei-dev.ccr.corp.intel.com ([10.239.158.52]) by fmsmga005.fm.intel.com with ESMTP; 25 Apr 2019 20:01:49 -0700 From: "Zhang, Shenglei" To: devel@edk2.groups.io Cc: Jaben Carsey , Ray Ni Subject: [edk2-devel] [PATCH v2 3/4] ShellPkg/UefiHandleParsingLib: Remove some unused Guids Date: Fri, 26 Apr 2019 11:01:41 +0800 Message-Id: <20190426030142.7880-4-shenglei.zhang@intel.com> In-Reply-To: <20190426030142.7880-1-shenglei.zhang@intel.com> References: <20190426030142.7880-1-shenglei.zhang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,shenglei.zhang@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556247711; bh=zBWndsUW8YFH8jfUZen7e9RgVpwb8Kg/WhP5ASfMaQU=; h=Cc:Date:From:Reply-To:Subject:To; b=CBI+/HTwOp2yLp/ob03fE3iM6+Fj0vu4Vdk4X+AuV/6DeIrR03HHihj68OxDzMBVAB9 NZEWQSO9GH7PEG+yb1z0GoKqeuxyn39q2c1FjhYoNdTNRITd0ZNqxgPxW4H5slOzdhBtf w1WfC1+USZhtiA/AlN444dsgNZiN4NXGhvE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ExtendedSalBootService.h, ExtendedSalServiceClasses.h and McaInitPmi.h will be deleted. So remove the Guids defined in these Protocols. And also remove strings in uni file. https://bugzilla.tianocore.org/show_bug.cgi?id=3D1560 Cc: Jaben Carsey Cc: Ray Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang Reviewed-by: Jaben Carsey Reviewed-by: Ray Ni --- .../UefiHandleParsingLib/UefiHandleParsingLib.c | 17 ----------------- .../UefiHandleParsingLib.inf | 17 ----------------- .../UefiHandleParsingLib.uni | 17 ----------------- 3 files changed, 51 deletions(-) diff --git a/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.c b= /ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.c index 8e8fa13285..f179c41092 100644 --- a/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.c +++ b/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.c @@ -2315,23 +2315,6 @@ STATIC CONST GUID_INFO_BLOCK mGuidStringList[] =3D { {STRING_TOKEN(STR_FVB2), &gEfiFirmwareVolumeBlock2Proto= colGuid, NULL}, {STRING_TOKEN(STR_CPUIO2), &gEfiCpuIo2ProtocolGuid, = NULL}, {STRING_TOKEN(STR_LEGACY_R2), &gEfiLegacyRegion2ProtocolGuid= , NULL}, - {STRING_TOKEN(STR_SAL_MIP), &gEfiSalMcaInitPmiProtocolGuid= , NULL}, - {STRING_TOKEN(STR_ES_BS), &gEfiExtendedSalBootServicePro= tocolGuid, NULL}, - {STRING_TOKEN(STR_ES_BIO), &gEfiExtendedSalBaseIoServices= ProtocolGuid, NULL}, - {STRING_TOKEN(STR_ES_STALL), &gEfiExtendedSalStallServicesP= rotocolGuid, NULL}, - {STRING_TOKEN(STR_ES_RTC), &gEfiExtendedSalRtcServicesPro= tocolGuid, NULL}, - {STRING_TOKEN(STR_ES_VS), &gEfiExtendedSalVariableServic= esProtocolGuid, NULL}, - {STRING_TOKEN(STR_ES_MTC), &gEfiExtendedSalMtcServicesPro= tocolGuid, NULL}, - {STRING_TOKEN(STR_ES_RESET), &gEfiExtendedSalResetServicesP= rotocolGuid, NULL}, - {STRING_TOKEN(STR_ES_SC), &gEfiExtendedSalStatusCodeServ= icesProtocolGuid, NULL}, - {STRING_TOKEN(STR_ES_FBS), &gEfiExtendedSalFvBlockService= sProtocolGuid, NULL}, - {STRING_TOKEN(STR_ES_MP), &gEfiExtendedSalMpServicesProt= ocolGuid, NULL}, - {STRING_TOKEN(STR_ES_PAL), &gEfiExtendedSalPalServicesPro= tocolGuid, NULL}, - {STRING_TOKEN(STR_ES_BASE), &gEfiExtendedSalBaseServicesPr= otocolGuid, NULL}, - {STRING_TOKEN(STR_ES_MCA), &gEfiExtendedSalMcaServicesPro= tocolGuid, NULL}, - {STRING_TOKEN(STR_ES_PCI), &gEfiExtendedSalPciServicesPro= tocolGuid, NULL}, - {STRING_TOKEN(STR_ES_CACHE), &gEfiExtendedSalCacheServicesP= rotocolGuid, NULL}, - {STRING_TOKEN(STR_ES_MCA_LOG), &gEfiExtendedSalMcaLogServices= ProtocolGuid, NULL}, {STRING_TOKEN(STR_S2ARCH), &gEfiSecurity2ArchProtocolGuid= , NULL}, {STRING_TOKEN(STR_EODXE), &gEfiSmmEndOfDxeProtocolGuid, = NULL}, {STRING_TOKEN(STR_ISAHC), &gEfiIsaHcProtocolGuid, = NULL}, diff --git a/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf= b/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf index 2a54529901..93b69cd8e9 100644 --- a/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf +++ b/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf @@ -229,23 +229,6 @@ gEfiFirmwareVolumeBlock2ProtocolGuid ## UNDEFINED gEfiCpuIo2ProtocolGuid ## UNDEFINED gEfiLegacyRegion2ProtocolGuid ## UNDEFINED - gEfiSalMcaInitPmiProtocolGuid ## UNDEFINED - gEfiExtendedSalBootServiceProtocolGuid ## UNDEFINED - gEfiExtendedSalBaseIoServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalStallServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalRtcServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalVariableServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalMtcServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalResetServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalStatusCodeServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalFvBlockServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalMpServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalPalServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalBaseServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalMcaServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalPciServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalCacheServicesProtocolGuid ## UNDEFINED - gEfiExtendedSalMcaLogServicesProtocolGuid ## UNDEFINED gEfiSecurity2ArchProtocolGuid ## UNDEFINED gEfiSmmEndOfDxeProtocolGuid ## UNDEFINED gEfiIsaHcProtocolGuid ## UNDEFINED diff --git a/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.uni= b/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.uni index 15a270620f..9c8028d0d5 100644 --- a/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.uni +++ b/ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.uni @@ -268,23 +268,6 @@ #string STR_FVB2 #language en-US "FirmwareVolumeBlock2" #string STR_CPUIO2 #language en-US "CpuIo2" #string STR_LEGACY_R2 #language en-US "LegacyRegion2" -#string STR_SAL_MIP #language en-US "SalMcaInitPmi" -#string STR_ES_BS #language en-US "ExtendedSalBootService" -#string STR_ES_BIO #language en-US "ExtendedSalBaseIoServic= es" -#string STR_ES_STALL #language en-US "ExtendedSalStallService= s" -#string STR_ES_RTC #language en-US "ExtendedSalRtcServices" -#string STR_ES_VS #language en-US "ExtendedSalVariableServ= ices" -#string STR_ES_MTC #language en-US "ExtendedSalMtcServices" -#string STR_ES_RESET #language en-US "ExtendedSalResetService= s" -#string STR_ES_SC #language en-US "ExtendedSalStatusCodeSe= rvices" -#string STR_ES_FBS #language en-US "ExtendedSalFvBlockServi= ces" -#string STR_ES_MP #language en-US "ExtendedSalMpServices" -#string STR_ES_PAL #language en-US "ExtendedSalPalServices" -#string STR_ES_BASE #language en-US "ExtendedSalBaseServices" -#string STR_ES_MCA #language en-US "ExtendedSalMcaServices" -#string STR_ES_PCI #language en-US "ExtendedSalPciServices" -#string STR_ES_CACHE #language en-US "ExtendedSalCacheService= s" -#string STR_ES_MCA_LOG #language en-US "ExtendedSalMcaLogServic= es" #string STR_S2ARCH #language en-US "Security2Arch" #string STR_EODXE #language en-US "SmmEndOfDxe" #string STR_ISAHC #language en-US "IsaHc" --=20 2.18.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#39614): https://edk2.groups.io/g/devel/message/39614 Mute This Topic: https://groups.io/mt/31349518/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 13 15:58:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+39615+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39615+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1556247715; cv=none; d=zoho.com; s=zohoarc; b=BAGU/tok2NJB3VmsCnk3rsdCO6Pb9DwHkVVYAiikyoi/cuUqlfkpU9RT7xV3klso6C/d7WUFz2OSS6oJLlid3MvkbvocQ29SHng5otco6ztqQo6iKfIWWwAc2N3MEvKXXY0ZyAFpzfWbKF9kt1eniwNfbDKTJuQ8ZBtqlGtBEcU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1556247715; h=Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=B1EpV5db8lWqcwIwS6hfFH6Dn9hoYaIfhAaZTPsKk9U=; b=aYBSOQyL6+da4UNS10yY15EB0ugAm/SQ/ywc15bPjIKwUjQXXdF7W0StcTXTpMsqfJRCke9bwKDAxF34Aypc3aeVVWpvWVLEhYUegKHLp5ka4fJgK3WZcxoXLinZQyVNuYfgdW53Q7UDMdb5rxROJ2KExhP9u+QvxlpP3MY9270= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+39615+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1556247715757202.75210171893775; Thu, 25 Apr 2019 20:01:55 -0700 (PDT) Return-Path: X-Received: from mga03.intel.com (mga03.intel.com []) by groups.io with SMTP; Thu, 25 Apr 2019 20:01:54 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 25 Apr 2019 20:01:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.60,395,1549958400"; d="scan'208";a="340896424" X-Received: from shenglei-dev.ccr.corp.intel.com ([10.239.158.52]) by fmsmga005.fm.intel.com with ESMTP; 25 Apr 2019 20:01:51 -0700 From: "Zhang, Shenglei" To: devel@edk2.groups.io Cc: Michael D Kinney , Liming Gao Subject: [edk2-devel] [PATCH v2 4/4] MdePkg: Removed IPF related code Date: Fri, 26 Apr 2019 11:01:42 +0800 Message-Id: <20190426030142.7880-5-shenglei.zhang@intel.com> In-Reply-To: <20190426030142.7880-1-shenglei.zhang@intel.com> References: <20190426030142.7880-1-shenglei.zhang@intel.com> Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,shenglei.zhang@intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1556247715; bh=XE2VpGeDoYQ0B41heOXY7fZ5LXxJY3/FmL9/fqKPxk0=; h=Cc:Date:From:Reply-To:Subject:To; b=ZYbQhossjWCL6nYMFQkSi2VDnd8nZzl3dfKr6sEwY1FVX2RoqjAlUcm4eBZslhjn2Pp SLHKSkfx8R2Oq6yXAo+vT7ZQjjwVXV3HYzb9wdW4VP1BmrfLjWDO2Dyxy7CYUdn9Y1rn0 5fnBYXw/TtlthufnIOT03Dgsyf5bRBhx/jk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A previous commit(3cb0a311cb7e747d7be5c5076d0fff76ad256d2b) didn't clean all IPF contents. So this change removes the rest contents. https://bugzilla.tianocore.org/show_bug.cgi?id=3D1560 v2: Withdraw the removal of Mps.h. It is written in Mps.h that MPS only was included to support Itanium-based platform power on. But we found MPS is not so relevant to Itanium architecture. Cc: Michael D Kinney Cc: Liming Gao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Shenglei Zhang --- MdePkg/Include/Guid/SalSystemTable.h | 25 - MdePkg/Include/IndustryStandard/Pal.h | 3296 ----------------- MdePkg/Include/IndustryStandard/Sal.h | 909 ----- MdePkg/Include/Library/ExtendedSalLib.h | 488 --- MdePkg/Include/Library/PalLib.h | 57 - MdePkg/Include/Library/SalLib.h | 53 - .../Include/Protocol/ExtendedSalBootService.h | 211 -- .../Protocol/ExtendedSalServiceClasses.h | 272 -- MdePkg/Include/Protocol/McaInitPmi.h | 201 - MdePkg/MdePkg.dec | 26 - 10 files changed, 5538 deletions(-) delete mode 100644 MdePkg/Include/Guid/SalSystemTable.h delete mode 100644 MdePkg/Include/IndustryStandard/Pal.h delete mode 100644 MdePkg/Include/IndustryStandard/Sal.h delete mode 100644 MdePkg/Include/Library/ExtendedSalLib.h delete mode 100644 MdePkg/Include/Library/PalLib.h delete mode 100644 MdePkg/Include/Library/SalLib.h delete mode 100644 MdePkg/Include/Protocol/ExtendedSalBootService.h delete mode 100644 MdePkg/Include/Protocol/ExtendedSalServiceClasses.h delete mode 100644 MdePkg/Include/Protocol/McaInitPmi.h diff --git a/MdePkg/Include/Guid/SalSystemTable.h b/MdePkg/Include/Guid/Sal= SystemTable.h deleted file mode 100644 index daa7c0a42f..0000000000 --- a/MdePkg/Include/Guid/SalSystemTable.h +++ /dev/null @@ -1,25 +0,0 @@ -/** @file - GUIDs used for SAL system table entries in the EFI system table. - - SAL System Table contains Itanium-based processor centric information ab= out - the system. - - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - @par Revision Reference: - GUIDs defined in UEFI 2.0 spec. - -**/ - -#ifndef __SAL_SYSTEM_TABLE_GUID_H__ -#define __SAL_SYSTEM_TABLE_GUID_H__ - -#define SAL_SYSTEM_TABLE_GUID \ - { \ - 0xeb9d2d32, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, = 0x4d } \ - } - -extern EFI_GUID gEfiSalSystemTableGuid; - -#endif diff --git a/MdePkg/Include/IndustryStandard/Pal.h b/MdePkg/Include/Industr= yStandard/Pal.h deleted file mode 100644 index 393798ecf9..0000000000 --- a/MdePkg/Include/IndustryStandard/Pal.h +++ /dev/null @@ -1,3296 +0,0 @@ -/** @file - Main PAL API's defined in Intel Itanium Architecture Software Developer'= s Manual. - - Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __PAL_API_H__ -#define __PAL_API_H__ - -#define PAL_SUCCESS 0x0 - -/// -/// CacheType of PAL_CACHE_FLUSH. -/// -#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1 -#define PAL_CACHE_FLUSH_DATA_ALL 2 -#define PAL_CACHE_FLUSH_ALL 3 -#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4 - - -/// -/// Bitmask of Opearation of PAL_CACHE_FLUSH. -/// -#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0 -#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0 -#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1 -#define PAL_CACHE_FLUSH_NO_INTERRUPT 0 - -/** - PAL Procedure - PAL_CACHE_FLUSH. - - Flush the instruction or data caches. It is required by Itanium processo= rs. - The PAL procedure supports the Static Registers calling - convention. It could be called at virtual mode and physical - mode. - - @param Index Index of PAL_CACHE_FLUSH within the - list of PAL procedures. - @param CacheType Unsigned 64-bit integer indicating - which cache to flush. - @param Operation Formatted bit vector indicating the - operation of this call. - @param ProgressIndicator Unsigned 64-bit integer specifying - the starting position of the flush - operation. - - @retval 2 Call completed without error, but a PMI - was taken during the execution of this - procedure. - @retval 1 Call has not completed flushing due to - a pending interrupt. - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error - - @return R9 Unsigned 64-bit integer specifying the vector - number of the pending interrupt. - @return R10 Unsigned 64-bit integer specifying the - starting position of the flush operation. - @return R11 Unsigned 64-bit integer specifying the vector - number of the pending interrupt. - -**/ -#define PAL_CACHE_FLUSH 1 - - -/// -/// Attributes of PAL_CACHE_CONFIG_INFO1 -/// -#define PAL_CACHE_ATTR_WT 0 -#define PAL_CACHE_ATTR_WB 1 - -/// -/// PAL_CACHE_CONFIG_INFO1.StoreHint -/// -#define PAL_CACHE_STORE_TEMPORAL 0 -#define PAL_CACHE_STORE_NONE_TEMPORAL 3 - -/// -/// PAL_CACHE_CONFIG_INFO1.StoreHint -/// -#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0 -#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3 - -/// -/// PAL_CACHE_CONFIG_INFO1.StoreHint -/// -#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0 -#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1 -#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3 - -/// -/// Detail the characteristics of a given processor controlled -/// cache in the cache hierarchy. -/// -typedef struct { - UINT64 IsUnified : 1; - UINT64 Attributes : 2; - UINT64 Associativity:8; - UINT64 LineSize:8; - UINT64 Stride:8; - UINT64 StoreLatency:8; - UINT64 StoreHint:8; - UINT64 LoadHint:8; -} PAL_CACHE_INFO_RETURN1; - -/// -/// Detail the characteristics of a given processor controlled -/// cache in the cache hierarchy. -/// -typedef struct { - UINT64 CacheSize:32; - UINT64 AliasBoundary:8; - UINT64 TagLsBits:8; - UINT64 TagMsBits:8; -} PAL_CACHE_INFO_RETURN2; - -/** - PAL Procedure - PAL_CACHE_INFO. - - Return detailed instruction or data cache information. It is - required by Itanium processors. The PAL procedure supports the Static - Registers calling convention. It could be called at virtual - mode and physical mode. - - @param Index Index of PAL_CACHE_INFO within the list of - PAL procedures. - @param CacheLevel Unsigned 64-bit integer specifying the - level in the cache hierarchy for which - information is requested. This value must - be between 0 and one less than the value - returned in the cache_levels return value - from PAL_CACHE_SUMMARY. - @param CacheType Unsigned 64-bit integer with a value of 1 - for instruction cache and 2 for data or - unified cache. All other values are - reserved. - @param Reserved Should be 0. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error - - @return R9 Detail the characteristics of a given - processor controlled cache in the cache - hierarchy. See PAL_CACHE_INFO_RETURN1. - @return R10 Detail the characteristics of a given - processor controlled cache in the cache - hierarchy. See PAL_CACHE_INFO_RETURN2. - @return R11 Reserved with 0. - -**/ -#define PAL_CACHE_INFO 2 - - - -/// -/// Level of PAL_CACHE_INIT. -/// -#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL - -/// -/// CacheType -/// -#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1 -#define PAL_CACHE_INIT_TYPE_DATA 0x2 -#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3 - -/// -/// Restrict of PAL_CACHE_INIT. -/// -#define PAL_CACHE_INIT_NO_RESTRICT 0 -#define PAL_CACHE_INIT_RESTRICTED 1 - -/** - PAL Procedure - PAL_CACHE_INIT. - - Initialize the instruction or data caches. It is required by - Itanium processors. The PAL procedure supports the Static Registers call= ing - convention. It could be called at physical mode. - - @param Index Index of PAL_CACHE_INIT within the list of PAL - procedures. - @param Level Unsigned 64-bit integer containing the level of - cache to initialize. If the cache level can be - initialized independently, only that level will - be initialized. Otherwise - implementation-dependent side-effects will - occur. - @param CacheType Unsigned 64-bit integer with a value of 1 to - initialize the instruction cache, 2 to - initialize the data cache, or 3 to - initialize both. All other values are - reserved. - @param Restrict Unsigned 64-bit integer with a value of 0 or - 1. All other values are reserved. If - restrict is 1 and initializing the specified - level and cache_type of the cache would - cause side-effects, PAL_CACHE_INIT will - return -4 instead of initializing the cache. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -4 Call could not initialize the specified - level and cache_type of the cache without - side-effects and restrict was 1. - -**/ -#define PAL_CACHE_INIT 3 - - -/// -/// PAL_CACHE_PROTECTION.Method. -/// -#define PAL_CACHE_PROTECTION_NONE_PROTECT 0 -#define PAL_CACHE_PROTECTION_ODD_PROTECT 1 -#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2 -#define PAL_CACHE_PROTECTION_ECC_PROTECT 3 - - - -/// -/// PAL_CACHE_PROTECTION.TagOrData. -/// -#define PAL_CACHE_PROTECTION_PROTECT_DATA 0 -#define PAL_CACHE_PROTECTION_PROTECT_TAG 1 -#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2 -#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3 - -/// -/// 32-bit protection information structures. -/// -typedef struct { - UINT32 DataBits:8; - UINT32 TagProtLsb:6; - UINT32 TagProtMsb:6; - UINT32 ProtBits:6; - UINT32 Method:4; - UINT32 TagOrData:2; -} PAL_CACHE_PROTECTION; - -/** - PAL Procedure - PAL_CACHE_PROT_INFO. - - Return instruction or data cache protection information. It is - required by Itanium processors. The PAL procedure supports the Static - Registers calling convention. It could be called at physical - mode and Virtual mode. - - @param Index Index of PAL_CACHE_PROT_INFO within the list of - PAL procedures. - @param CacheLevel Unsigned 64-bit integer specifying the level - in the cache hierarchy for which information - is requested. This value must be between 0 - and one less than the value returned in the - cache_levels return value from - PAL_CACHE_SUMMARY. - @param CacheType Unsigned 64-bit integer with a value of 1 - for instruction cache and 2 for data or - unified cache. All other values are - reserved. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Detail the characteristics of a given - processor controlled cache in the cache - hierarchy. See PAL_CACHE_PROTECTION[0..1]. - @return R10 Detail the characteristics of a given - processor controlled cache in the cache - hierarchy. See PAL_CACHE_PROTECTION[2..3]. - @return R11 Detail the characteristics of a given - processor controlled cache in the cache - hierarchy. See PAL_CACHE_PROTECTION[4..5]. - -**/ -#define PAL_CACHE_PROT_INFO 38 - -typedef struct { - UINT64 ThreadId : 16; ///< The thread identifier of the logical - ///< processor for which information is being - ///< returned. This value will be unique on a = per core basis. - UINT64 Reserved1: 16; - UINT64 CoreId: 16; ///< The core identifier of the logical proces= sor - ///< for which information is being returned. - ///< This value will be unique on a per physic= al - ///< processor package basis. - UINT64 Reserved2: 16; -} PAL_PCOC_N_CACHE_INFO1; - - -typedef struct { - UINT64 LogicalAddress : 16; ///< Logical address: geographical address - ///< of the logical processor for which - ///< information is being returned. This is - ///< the same value that is returned by the - ///< PAL_FIXED_ADDR procedure when it is - ///< called on the logical processor. - UINT64 Reserved1: 16; - UINT64 Reserved2: 32; -} PAL_PCOC_N_CACHE_INFO2; - -/** - PAL Procedure - PAL_CACHE_SHARED_INFO. - - Returns information on which logical processors share caches. - It is optional. The PAL procedure supports the Static - Registers calling convention. It could be called at physical - mode and Virtual mode. - - @param Index Index of PAL_CACHE_SHARED_INFO within the list - of PAL procedures. - @param CacheLevel Unsigned 64-bit integer specifying the - level in the cache hierarchy for which - information is requested. This value must - be between 0 and one less than the value - returned in the cache_levels return value - from PAL_CACHE_SUMMARY. - @param CacheType Unsigned 64-bit integer with a value of 1 - for instruction cache and 2 for data or - unified cache. All other values are - reserved. - @param ProcNumber Unsigned 64-bit integer that specifies for - which logical processor information is - being requested. This input argument must - be zero for the first call to this - procedure and can be a maximum value of - one less than the number of logical - processors sharing this cache, which is - returned by the num_shared return value. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned integer that returns the number of - logical processors that share the processor - cache level and type, for which information was - requested. - @return R10 The format of PAL_PCOC_N_CACHE_INFO1. - @return R11 The format of PAL_PCOC_N_CACHE_INFO2. - -**/ -#define PAL_CACHE_SHARED_INFO 43 - - -/** - PAL Procedure - PAL_CACHE_SUMMARY. - - Return a summary of the cache hierarchy. It is required by - Itanium processors. The PAL procedure supports the Static Registers call= ing - convention. It could be called at physical mode and Virtual - mode. - - @param Index Index of PAL_CACHE_SUMMARY within the list of - PAL procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 CacheLevels Unsigned 64-bit integer denoting the - number of levels of cache - implemented by the processor. - Strictly, this is the number of - levels for which the cache - controller is integrated into the - processor (the cache SRAMs may be - external to the processor). - @return R10 UniqueCaches Unsigned 64-bit integer denoting the - number of unique caches implemented - by the processor. This has a maximum - of 2*cache_levels, but may be less - if any of the levels in the cache - hierarchy are unified caches or do - not have both instruction and data - caches. - -**/ -#define PAL_CACHE_SUMMARY 4 - - -// -// Virtual Memory Attributes implemented by processor. -// -#define PAL_MEMORY_ATTR_WB 0 -#define PAL_MEMORY_ATTR_WC 6 -#define PAL_MEMORY_ATTR_UC 4 -#define PAL_MEMORY_ATTR_UCE 5 -#define PAL_MEMORY_ATTR_NATPAGE 7 - -/** - PAL Procedure - PAL_MEM_ATTRIB. - - Return a list of supported memory attributes.. It is required - by Itanium processors. The PAL procedure supports the Static Registers c= alling - convention. It could be called at physical mode and Virtual - mode. - - @param Index Index of PAL_MEM_ATTRIB within the list of PAL - procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Attributes 8-bit vector of memory attributes - implemented by processor. See Virtual - Memory Attributes above. - -**/ - -#define PAL_MEM_ATTRIB 5 - -/** - PAL Procedure - PAL_PREFETCH_VISIBILITY. - - Used in architected sequence to transition pages from a - cacheable, speculative attribute to an uncacheable attribute. - It is required by Itanium processors. The PAL procedure supports the Sta= tic - Registers calling convention. It could be called at physical - mode and Virtual mode. - - @param Index Index of PAL_PREFETCH_VISIBILITY within the list - of PAL procedures. - @param TransitionType Unsigned integer specifying the type - of memory attribute transition that is - being performed. - - @retval 1 Call completed without error; this - call is not necessary on remote - processors. - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_PREFETCH_VISIBILITY 41 - -/** - PAL Procedure - PAL_PTCE_INFO. - - Return information needed for ptc.e instruction to purge - entire TC. It is required by Itanium processors. The PAL procedure suppo= rts - the Static Registers calling convention. It could be called at - physical mode and Virtual mode. - - @param Index Index of PAL_PTCE_INFO within the list - of PAL procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned 64-bit integer denoting the beginning - address to be used by the first PTCE instruction - in the purge loop. - @return R10 Two unsigned 32-bit integers denoting the loop - counts of the outer (loop 1) and inner (loop 2) - purge loops. count1 (loop 1) is contained in bits - 63:32 of the parameter, and count2 (loop 2) is - contained in bits 31:0 of the parameter. - @return R11 Two unsigned 32-bit integers denoting the loop - strides of the outer (loop 1) and inner (loop 2) - purge loops. stride1 (loop 1) is contained in bits - 63:32 of the parameter, and stride2 (loop 2) is - contained in bits 31:0 of the parameter. - -**/ -#define PAL_PTCE_INFO 6 - -typedef struct { - UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting t= he number - ///< of hash sets for the specified le= vel - ///< (1=3Dfully associative) - UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting t= he - ///< associativity of the specified le= vel - ///< (1=3Ddirect). - UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting = the - ///< number of entries in the specifie= d TC. - UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the - ///< specified level is optimized for - ///< the region's preferred page size - ///< (1=3Doptimized) tc_pages indicates - ///< which page sizes are usable by - ///< this translation cache. - UINT64 TcIsUnified:1; ///< Flag denoting whether the specifi= ed TC is - ///< unified (1=3Dunified). - UINT64 EntriesReduction:1; ///< Flag denoting whether installed - ///< translation registers will reduce - ///< the number of entries within the - ///< specified TC. -} PAL_TC_INFO; - -/** - PAL Procedure - PAL_VM_INFO. - - Return detailed information about virtual memory features - supported in the processor. It is required by Itanium processors. The PAL - procedure supports the Static Registers calling convention. It - could be called at physical mode and Virtual mode. - - @param Index Index of PAL_VM_INFO within the list - of PAL procedures. - @param TcLevel Unsigned 64-bit integer specifying the level - in the TLB hierarchy for which information is - required. This value must be between 0 and one - less than the value returned in the - vm_info_1.num_tc_levels return value from - PAL_VM_SUMMARY. - @param TcType Unsigned 64-bit integer with a value of 1 for - instruction translation cache and 2 for data - or unified translation cache. All other values - are reserved. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 8-byte formatted value returning information - about the specified TC. See PAL_TC_INFO above. - @return R10 64-bit vector containing a bit for each page - size supported in the specified TC, where bit - position n indicates a page size of 2**n. - -**/ -#define PAL_VM_INFO 7 - - -/** - PAL Procedure - PAL_VM_PAGE_SIZE. - - Return virtual memory TC and hardware walker page sizes - supported in the processor. It is required by Itanium processors. The PAL - procedure supports the Static Registers calling convention. It - could be called at physical mode and Virtual mode. - - @param Index Index of PAL_VM_PAGE_SIZE within the list - of PAL procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 64-bit vector containing a bit for each - architected page size that is supported for - TLB insertions and region registers. - @return R10 64-bit vector containing a bit for each - architected page size supported for TLB purge - operations. - -**/ -#define PAL_VM_PAGE_SIZE 34 - -typedef struct { - UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether= a hardware - ///< TLB walker is implemented (1 = =3D walker - ///< present). - UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer - ///< denoting the number of bits of - ///< physical address implemented. - UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoti= ng the number - ///< of bits mplemented in the PKR= .key field. - UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoti= ng the - ///< maximum PKR index (number of = PKRs-1). - UINT64 HashTagId:8; ///< Unsigned 8-bit integer which = uniquely - ///< identifies the processor hash= and tag - ///< algorithm. - UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoti= ng the - ///< maximum data translation regi= ster index - ///< (number of dtr entries - 1). - UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoti= ng the - ///< maximum instruction translati= on register - ///< index (number of itr entries = - 1). - UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoti= ng the - ///< number of unique TCs implemen= ted. - ///< This is a maximum of - ///< 2*num_tc_levels. - UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoti= ng the - ///< number of TC levels. -} PAL_VM_INFO1; - -typedef struct { - UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting - ///< is the total number of virtual - ///< address bits - 1. - UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting t= he number - ///< of bits implemented in the RR.rid= field. - UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting = the - ///< maximum number of concurrent outs= tanding - ///< TLB purges allowed by the process= or. A - ///< value of 0 indicates one outstand= ing - ///< purge allowed. A value of 216-1 - ///< indicates no limit on outstanding - ///< purges. All other values indicate= the - ///< actual number of concurrent outst= anding - ///< purges allowed. - UINT64 Reserved:32; -} PAL_VM_INFO2; - -/** - PAL Procedure - PAL_VM_SUMMARY. - - Return summary information about virtual memory features - supported in the processor. It is required by Itanium processors. The PAL - procedure supports the Static Registers calling convention. It - could be called at physical mode and Virtual mode. - - @param Index Index of PAL_VM_SUMMARY within the list - of PAL procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 8-byte formatted value returning global virtual - memory information. See PAL_VM_INFO1 above. - @return R10 8-byte formatted value returning global virtual - memory information. See PAL_VM_INFO2 above. - -**/ -#define PAL_VM_SUMMARY 8 - - -// -// Bit mask of TR_valid flag. -// -#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0 -#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1 -#define PAL_TR_DIRTY_IS_VALID BIT2 -#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3 - - -/** - PAL Procedure - PAL_VM_TR_READ. - - Read contents of a translation register. It is required by - Itanium processors. The PAL procedure supports the Stacked Register call= ing - convention. It could be called at physical mode. - - @param Index Index of PAL_VM_TR_READ within the list - of PAL procedures. - @param RegNumber Unsigned 64-bit number denoting which TR to - read. - @param TrType Unsigned 64-bit number denoting whether to - read an ITR (0) or DTR (1). All other values - are reserved. - @param TrBuffer 64-bit pointer to the 32-byte memory buffer in - which translation data is returned. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Formatted bit vector denoting which fields are - valid. See TR_valid above. - -**/ -#define PAL_VM_TR_READ 261 - - - - -// -// Bit Mask of Processor Bus Fesatures . -// - -/** - - When 0, bus data errors are detected and single bit errors are - corrected. When 1, no error detection or correction is done. - -**/ -#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63 - - -/** - - When 0, bus address errors are signalled on the bus. When 1, - no bus errors are signalled on the bus. If Disable Bus Address - Error Checking is 1, this bit is ignored. - -**/ -#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62 - - - - -/** - - When 0, bus errors are detected, single bit errors are - corrected., and a CMCI or MCA is generated internally to the - processor. When 1, no bus address errors are detected or - corrected. - -**/ -#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61 - - -/** - - When 0, bus protocol errors (BINIT#) are signaled by the - processor on the bus. When 1, bus protocol errors (BINIT#) are - not signaled on the bus. If Disable Bus Initialization Event - Checking is 1, this bit is ignored. - -**/ -#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60 - - -/** - - When 0, bus protocol errors (BINIT#) are detected and sampled - and an MCA is generated internally to the processor. When 1, - the processor will ignore bus protocol error conditions - (BINIT#). - -**/ -#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59 - - - -/** - - When 0, BERR# is signalled if a bus error is detected. When 1, - bus errors are not signalled on the bus. - -**/ -#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58 - - - - -/** - - When 0, BERR# is signalled when internal processor requestor - initiated bus errors are detected. When 1, internal requester - bus errors are not signalled on the bus. - -**/ -#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57 - - -/** - - When 0, the processor takes an MCA if BERR# is asserted. When - 1, the processor ignores the BERR# signal. - -**/ -#define PAL_BUS_DISABLE_ERROR_CHECK BIT56 - - -/** - - When 0, the processor asserts BINIT# if it detects a parity - error on the signals which identify the transactions to which - this is a response. When 1, the processor ignores parity on - these signals. - -**/ -#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55 - - -/** - - When 0, the in-order transaction queue is limited only by the - number of hardware entries. When 1, the processor's in-order - transactions queue is limited to one entry. - -**/ -#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54 - -/** - - Enable a bus cache line replacement transaction when a cache - line in the exclusive state is replaced from the highest level - processor cache and is not present in the lower level processor - caches. When 0, no bus cache line replacement transaction will - be seen on the bus. When 1, bus cache line replacement - transactions will be seen on the bus when the above condition is - detected. - -**/ -#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53 - - -/** - - Enable a bus cache line replacement transaction when a cache - line in the shared or exclusive state is replaced from the - highest level processor cache and is not present in the lower - level processor caches. - When 0, no bus cache line replacement transaction will be seen - on the bus. When 1, bus cache line replacement transactions - will be seen on the bus when the above condition is detected. - -**/ -#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52 - - - -/** - - When 0, the data bus is configured at the 2x data transfer - rate.When 1, the data bus is configured at the 1x data - transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the - processor executes locked transactions atomically. When 1, the - processor masks the bus lock signal and executes locked - transactions as a non-atomic series of transactions. - -**/ -#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30 - -/** - - When 0, the processor will deassert bus request when finished - with each transaction. When 1, the processor will continue to - assert bus request after it has finished, if it was the last - agent to own the bus and if there are no other pending - requests. - -**/ -#define PAL_BUS_REQUEST_BUS_PARKING BIT29 - - -/** - PAL Procedure - PAL_BUS_GET_FEATURES. - - Return configurable processor bus interface features and their - current settings. It is required by Itanium processors. The PAL procedure - supports the Stacked Register calling convention. It could be - called at physical mode. - - @param Index Index of PAL_BUS_GET_FEATURES within the list - of PAL procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 64-bit vector of features implemented. - (1=3Dimplemented, 0=3Dnot implemented) - @return R10 64-bit vector of current feature settings. - @return R11 64-bit vector of features controllable by - software. (1=3Dcontrollable, 0=3D not controllable) - -**/ -#define PAL_BUS_GET_FEATURES 9 - -/** - PAL Procedure - PAL_BUS_SET_FEATURES. - - Enable or disable configurable features in processor bus - interface. It is required by Itanium processors. The PAL procedure - supports the Static Registers calling convention. It could be - called at physical mode. - - @param Index Index of PAL_BUS_SET_FEATURES within the list - of PAL procedures. - @param FeatureSelect 64-bit vector denoting desired state of - each feature (1=3Dselect, 0=3Dnon-select). - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_BUS_SET_FEATURES 10 - - -/** - PAL Procedure - PAL_DEBUG_INFO. - - Return the number of instruction and data breakpoint - registers. It is required by Itanium processors. The - PAL procedure supports the Static Registers calling - convention. It could be called at physical mode and virtual - mode. - - @param Index Index of PAL_DEBUG_INFO within the list of PAL - procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned 64-bit integer denoting the number of - pairs of instruction debug registers implemented - by the processor. - @return R10 Unsigned 64-bit integer denoting the number of - pairs of data debug registers implemented by the - processor. - -**/ -#define PAL_DEBUG_INFO 11 - -/** - PAL Procedure - PAL_FIXED_ADDR. - - Return the fixed component of a processor's directed address. - It is required by Itanium processors. The PAL - procedure supports the Static Registers calling convention. It - could be called at physical mode and virtual mode. - - @param Index Index of PAL_FIXED_ADDR within the list of PAL - procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Fixed geographical address of this processor. - -**/ -#define PAL_FIXED_ADDR 12 - -/** - PAL Procedure - PAL_FREQ_BASE. - - Return the frequency of the output clock for use by the - platform, if generated by the processor. It is optinal. The - PAL procedure supports the Static Registers calling - convention. It could be called at physical mode and virtual - mode. - - @param Index Index of PAL_FREQ_BASE within the list of PAL - procedures. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Base frequency of the platform if generated by the - processor chip. - -**/ -#define PAL_FREQ_BASE 13 - - -/** - PAL Procedure - PAL_FREQ_RATIOS. - - Return ratio of processor, bus, and interval time counter to - processor input clock or output clock for platform use, if - generated by the processor. It is required by Itanium processors. The PAL - procedure supports the Static Registers calling convention. It - could be called at physical mode and virtual mode. - - @param Index Index of PAL_FREQ_RATIOS within the list of PAL - procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Ratio of the processor frequency to the input - clock of the processor, if the platform clock is - generated externally or to the output clock to the - platform, if the platform clock is generated by - the processor. - @return R10 Ratio of the bus frequency to the input clock of - the processor, if the platform clock is generated - externally or to the output clock to the platform, - if the platform clock is generated by the - processor. - @return R11 Ratio of the interval timer counter rate to input - clock of the processor, if the platform clock is - generated externally or to the output clock to the - platform, if the platform clock is generated by - the processor. - -**/ -#define PAL_FREQ_RATIOS 14 - -typedef struct { - UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical - ///< processors on this physic= al - ///< processor package that are - ///< enabled. - UINT64 ThreadsPerCore:8; ///< Number of threads per cor= e. - UINT64 Reserved1:8; - UINT64 CoresPerProcessor:8; ///< Total number of cores on = this - ///< physical processor packag= e. - UINT64 Reserved2:8; - UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package - ///< identifier which was - ///< assigned at reset by the - ///< platform or bus - ///< controller. This value may - ///< or may not be unique - ///< across the entire platform - ///< since it depends on the - ///< platform vendor's policy. - UINT64 Reserved3:8; -} PAL_LOGICAL_PROCESSPR_OVERVIEW; - -typedef struct { - UINT64 ThreadId:16; ///< The thread identifier of the logical - ///< processor for which information is being - ///< returned. This value will be unique on a = per - ///< core basis. - UINT64 Reserved1:16; - UINT64 CoreId:16; ///< The core identifier of the logical proces= sor - ///< for which information is being returned. - ///< This value will be unique on a per physic= al - ///< processor package basis. - UINT64 Reserved2:16; -} PAL_LOGICAL_PROCESSORN_INFO1; - -typedef struct { - UINT64 LogicalAddress:16; ///< Geographical address of the logical - ///< processor for which information is be= ing - ///< returned. This is the same value that= is - ///< returned by the PAL_FIXED_ADDR proced= ure - ///< when it is called on the logical proc= essor. - UINT64 Reserved:48; -} PAL_LOGICAL_PROCESSORN_INFO2; - -/** - PAL Procedure - PAL_LOGICAL_TO_PHYSICAL. - - Return information on which logical processors map to a - physical processor die. It is optinal. The PAL procedure - supports the Static Registers calling convention. It could be - called at physical mode and virtual mode. - - @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list= of PAL - procedures. - @param ProcessorNumber Signed 64-bit integer that specifies - for which logical processor - information is being requested. When - this input argument is -1, information - is returned about the logical - processor on which the procedure call - is made. This input argument must be - in the range of 1 up to one less than - the number of logical processors - returned by num_log in the - log_overview return value. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW. - @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1. - @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2. - -**/ -#define PAL_LOGICAL_TO_PHYSICAL 42 - -typedef struct { - UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number def= ining the - ///< number of generic PMC/PMD= pairs. - UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in = the range - ///< 0:60 defining the number = of - ///< implemented counter bits. - UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number def= ining the - ///< event type for counting p= rocessor cycles. - UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit - ///< number defining the - ///< event type for retired - ///< instruction bundles. - UINT64 Reserved:32; -} PAL_PERFORMANCE_INFO; - -/** - PAL Procedure - PAL_PERF_MON_INFO. - - Return the number and type of performance monitors. It is - required by Itanium processors. The PAL procedure supports the Static - Registers calling convention. It could be called at physical - mode and virtual mode. - - @param Index Index of PAL_PERF_MON_INFO within the list of - PAL procedures. - @param PerformanceBuffer An address to an 8-byte aligned - 128-byte memory buffer. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Information about the performance monitors - implemented. See PAL_PERFORMANCE_INFO; - -**/ -#define PAL_PERF_MON_INFO 15 - -#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0 -#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1 - -/** - PAL Procedure - PAL_PLATFORM_ADDR. - - Specify processor interrupt block address and I/O port space - address. It is required by Itanium processors. The PAL procedure support= s the - Static Registers calling convention. It could be called at - physical mode and virtual mode. - - @param Index Index of PAL_PLATFORM_ADDR within the list of - PAL procedures. - @param Type Unsigned 64-bit integer specifying the type of - block. 0 indicates that the processor interrupt - block pointer should be initialized. 1 indicates - that the processor I/O block pointer should be - initialized. - @param Address Unsigned 64-bit integer specifying the address - to which the processor I/O block or interrupt - block shall be set. The address must specify - an implemented physical address on the - processor model, bit 63 is ignored. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure. - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_PLATFORM_ADDR 16 - -typedef struct { - UINT64 Reserved1:36; - UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplement= ed - ///< instruction address r= eported as - ///< fault. Denotes how th= e processor - ///< reports the detection= of - ///< unimplemented instruc= tion - ///< addresses. When 1, th= e processor - ///< reports an Unimplemen= ted - ///< Instruction Address f= ault on the - ///< unimplemented address= ; when 0, it - ///< reports an Unimplemen= ted - ///< Instruction Address t= rap on the - ///< previous instruction = in program - ///< order. This feature m= ay only be - ///< interrogated by - ///< PAL_PROC_GET_FEATURES= . It may not - ///< be enabled or disable= d by - ///< PAL_PROC_SET_FEATURES= . The - ///< corresponding argumen= t is ignored. - - UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, = and LINT pins - ///< present. Denotes the = absence of INIT, - ///< PMI, LINT0 and LINT1 = pins on the - ///< processor. When 1, th= e pins are absent. - ///< When 0, the pins are = present. This - ///< feature may only be i= nterrogated by - ///< PAL_PROC_GET_FEATURES= . It may not be - ///< enabled or disabled by - ///< PAL_PROC_SET_FEATURES= . The corresponding - ///< argument is ignored. - - UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple - ///< implementation of - ///< unimplemented instruc= tion - ///< addresses. Denotes ho= w an - ///< unimplemented instruc= tion - ///< address is recorded i= n IIP - ///< on an Unimplemented - ///< Instruction Address t= rap or - ///< fault. When 1, the fu= ll - ///< unimplemented address= is - ///< recorded in IIP; when= 0, the - ///< address is sign exten= ded - ///< (virtual addresses) o= r zero - ///< extended (physical - ///< addresses). This feat= ure may - ///< only be interrogated = by - ///< PAL_PROC_GET_FEATURES= . It - ///< may not be enabled or - ///< disabled by - ///< PAL_PROC_SET_FEATURES= . The - ///< corresponding argumen= t is - ///< ignored. - - UINT64 NoVariablePState:1; ///< Bit39, No Variable P-= state - ///< performance: A value = of 1, indicates - ///< that a processor impl= ements - ///< techniques to optimiz= e performance - ///< for the given P-state= power budget - ///< by dynamically varyin= g the - ///< frequency, such that = maximum - ///< performance is achiev= ed for the - ///< power budget. A value= of 0, - ///< indicates that P-stat= es have no - ///< frequency variation o= r very small - ///< frequency variations = for their given - ///< power budget. This fe= ature may only - ///< be interrogated by - ///< PAL_PROC_GET_FEATURES= . it may not be - ///< enabled or disabled by - ///< PAL_PROC_SET_FEATURES= . The - ///< corresponding argumen= t is ignored. - - UINT64 NoVM:1; ///< Bit40, No Virtual Mac= hine features implemented. - ///< Denotes whether PSR.v= m is implemented. This - ///< feature may only be i= nterrogated by - ///< PAL_PROC_GET_FEATURES= . It may not be enabled or - ///< disabled by PAL_PROC_= SET_FEATURES. The - ///< corresponding argumen= t is ignored. - - UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, = and XFS - ///< implemented. Denotes = whether XIP, XPSR, - ///< and XFS are implement= ed for machine - ///< check recovery. This = feature may only be - ///< interrogated by PAL_P= ROC_GET_FEATURES. - ///< It may not be enabled= or disabled by - ///< PAL_PROC_SET_FEATURES= . The corresponding - ///< argument is ignored. - - UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through= XR3 implemented. - ///< Denotes whether XR1= XR3 are - ///< implemented for mac= hine check - ///< recovery. This feat= ure may only be - ///< interrogated by PAL= _PROC_GET_FEATURES. - ///< It may not be enabl= ed or disabled by - ///< PAL_PROC_SET_FEATUR= ES. The - ///< corresponding argum= ent is ignored. - - UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic - ///< Predicate Prediction.= When - ///< 0, the processor may = predict - ///< predicate results and - ///< execute speculatively= , but - ///< may not commit result= s until - ///< the actual predicates= are - ///< known. When 1, the pr= ocessor - ///< shall not execute pre= dicated - ///< instructions until the - ///< actual predicates are= known. - - UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Sponta= neous - ///< Deferral. When 1, t= he - ///< processor may optio= nally - ///< defer speculative l= oads - ///< that do not encount= er any - ///< exception condition= s, but - ///< that trigger other - ///< implementation-depe= ndent - ///< conditions (e.g., c= ache - ///< miss). When 0, spon= taneous - ///< deferral is disable= d. - - UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic - ///< Data Cache Prefetch. - ///< When 0, the process= or - ///< may prefetch into t= he - ///< caches any data whi= ch - ///< has not been access= ed - ///< by instruction - ///< execution, but which - ///< is likely to be - ///< accessed. When 1, no - ///< data may be fetched - ///< until it is needed = for - ///< instruction executi= on - ///< or is fetched by an - ///< lfetch instruction. - - UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable - ///< DynamicInstruction Ca= che - ///< Prefetch. When 0, the - ///< processor may prefetch - ///< into the caches any - ///< instruction which has - ///< not been executed, but - ///< whose execution is - ///< likely. When 1, - ///< instructions may not = be - ///< fetched until needed = or - ///< hinted for execution. - ///< (Prefetch for a hinted - ///< branch is allowed even - ///< when dynamic instruct= ion - ///< cache prefetch is - ///< disabled.) - - UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynami= c branch - ///< prediction. When 0,= the - ///< processor may predi= ct branch - ///< targets and specula= tively - ///< execute, but may no= t commit - ///< results. When 1, th= e processor - ///< must wait until bra= nch targets - ///< are known to execut= e. - UINT64 Reserved2:4; - UINT64 DisablePState:1; ///< Bit52, Disable P-stat= es. When 1, the PAL - ///< P-state procedures (P= AL_PSTATE_INFO, - ///< PAL_SET_PSTATE, PAL_G= ET_PSTATE) will - ///< return with a status = of -1 - ///< (Unimplemented proced= ure). - - UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA sig= naling - ///< on data-poisoning eve= nt - ///< detection. When 0, a = CMCI - ///< will be signaled on e= rror - ///< detection. When 1, an= MCA - ///< will be signaled on e= rror - ///< detection. If this fe= ature - ///< is not supported, the= n the - ///< corresponding argumen= t is - ///< ignored when calling - ///< PAL_PROC_SET_FEATURES= . Note - ///< that the functionalit= y of - ///< this bit is independe= nt of - ///< the setting in bit 60 - ///< (Enable CMCI promotio= n), and - ///< that the bit 60 setti= ng does - ///< not affect CMCI signa= ling - ///< for data-poisoning re= lated - ///< events. Volume 2: Pro= cessor - ///< Abstraction Layer 2:4= 31 - ///< PAL_PROC_GET_FEATURES - - UINT64 EnableVmsw:1; ///< Bit54, Enable the use= of the vmsw - ///< instruction. When 0= , the vmsw instruction - ///< causes a Virtualiza= tion fault when - ///< executed at the mos= t privileged level. - ///< When 1, this bit wi= ll enable normal - ///< operation of the vm= sw instruction. - - UINT64 EnableEnvNotification:1; ///< Bit55, Enable external - ///< notification when the= processor - ///< detects hardware erro= rs caused - ///< by environmental fact= ors that - ///< could cause loss of - ///< deterministic behavio= r of the - ///< processor. When 1, th= is bit will - ///< enable external notif= ication, - ///< when 0 external notif= ication is - ///< not provided. The typ= e of - ///< external notification= of these - ///< errors is processor-d= ependent. A - ///< loss of processor det= erministic - ///< behavior is considere= d to have - ///< occurred if these - ///< environmentally induc= ed errors - ///< cause the processor t= o deviate - ///< from its normal execu= tion and - ///< eventually causes dif= ferent - ///< behavior which can be= observed - ///< at the processor bus= pins. - ///< Processor errors that= do not - ///< have this effects (i.= e., - ///< software induced mach= ine checks) - ///< may or may not be pro= moted - ///< depending on the proc= essor - ///< implementation. - - UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINI= T on - ///< internal processor = time-out. - ///< When 0, the process= or may - ///< generate a BINIT on= an - ///< internal processor = time-out. - ///< When 1, the process= or will not - ///< generate a BINIT on= an - ///< internal processor = time-out. - ///< The event is silent= ly ignored. - - UINT64 DisableDPM:1; ///< Bit57, Disable Dynami= c Power Management - ///< (DPM). When 0, the = hardware may reduce - ///< power consumption b= y removing the clock - ///< input from idle fun= ctional units. When 1, - ///< all functional unit= s will receive clock - ///< input, even when id= le. - - UINT64 DisableCoherency:1; ///< Bit58, Disable Cohere= ncy. When 0, - ///< the processor uses no= rmal coherency - ///< requests and response= s. When 1, the - ///< processor answers all= requests as if - ///< the line were not pre= sent. - - UINT64 DisableCache:1; ///< Bit59, Disable Cache.= When 0, the - ///< processor performs ca= st outs on - ///< cacheable pages and i= ssues and responds - ///< to coherency requests= normally. When 1, - ///< the processor perform= s a memory access - ///< for each reference re= gardless of cache - ///< contents and issues n= o coherence - ///< requests and responds= as if the line - ///< were not present. Cac= he contents cannot - ///< be relied upon when t= he cache is - ///< disabled. WARNING: Se= maphore - ///< instructions may not = be atomic or may - ///< cause Unsupported Dat= a Reference faults - ///< if caches are disable= d. - - UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI pr= omotion When - ///< 1, Corrected Machin= e Check - ///< Interrupts (CMCI) a= re promoted to - ///< MCAs. They are also= further - ///< promoted to BERR if= bit 39, Enable - ///< MCA promotion, is a= lso set and - ///< they are promoted t= o BINIT if bit - ///< 38, Enable MCA to B= INIT promotion, - ///< is also set. This b= it has no - ///< effect if MCA signa= lling is - ///< disabled (see - ///< PAL_BUS_GET/SET_FEA= TURES) - - UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to = BINIT - ///< promotion. When 1, ma= chine - ///< check aborts (MCAs) a= re - ///< promoted to the Bus - ///< Initialization signal= , and - ///< the BINIT pin is asse= rt on - ///< each occurrence of an= MCA. - ///< Setting this bit has = no - ///< effect if BINIT signa= lling - ///< is disabled. (See - ///< PAL_BUS_GET/SET_FEATU= RES) - - UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA pro= motion. When - ///< 1, machine check ab= orts (MCAs) are - ///< promoted to the Bus= Error signal, - ///< and the BERR pin is= assert on each - ///< occurrence of an MC= A. Setting this - ///< bit has no effect i= f BERR - ///< signalling is disab= led. (See - ///< PAL_BUS_GET/SET_FEA= TURES) - - UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR pr= omotion. When - ///< 1, the Bus Error (B= ERR) signal is - ///< promoted to the Bus= Initialization - ///< (BINIT) signal, and= the BINIT pin - ///< is asserted on the = occurrence of - ///< each Bus Error. Set= ting this bit - ///< has no effect if BI= NIT signalling - ///< is disabled. (See - ///< PAL_BUS_GET/SET_FEA= TURES) -} PAL_PROCESSOR_FEATURES; - -/** - PAL Procedure - PAL_PROC_GET_FEATURES. - - Return configurable processor features and their current - setting. It is required by Itanium processors. The PAL procedure support= s the - Static Registers calling convention. It could be called at - physical mode and virtual mode. - - @param Index Index of PAL_PROC_GET_FEATURES within the list of - PAL procedures. - @param Reserved Reserved parameter. - @param FeatureSet Feature set information is being requested - for. - - @retval 1 Call completed without error; The - feature_set passed is not supported but a - feature_set of a larger value is supported. - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -8 feature_set passed is beyond the maximum - feature_set supported - - @return R9 64-bit vector of features implemented. See - PAL_PROCESSOR_FEATURES. - @return R10 64-bit vector of current feature settings. See - PAL_PROCESSOR_FEATURES. - @return R11 64-bit vector of features controllable by - software. - -**/ -#define PAL_PROC_GET_FEATURES 17 - - -/** - PAL Procedure - PAL_PROC_SET_FEATURES. - - Enable or disable configurable processor features. It is - required by Itanium processors. The PAL procedure supports the Static - Registers calling convention. It could be called at physical - mode. - - @param Index Index of PAL_PROC_SET_FEATURES within the list of - PAL procedures. - @param FeatureSelect 64-bit vector denoting desired state of - each feature (1=3Dselect, 0=3Dnon-select). - @param FeatureSet Feature set to apply changes to. See - PAL_PROC_GET_FEATURES for more information - on feature sets. - - @retval 1 Call completed without error; The - feature_set passed is not supported but a - feature_set of a larger value is supported - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -8 feature_set passed is beyond the maximum - feature_set supported - -**/ -#define PAL_PROC_SET_FEATURES 18 - - -// -// Value of PAL_REGISTER_INFO.InfoRequest. -// -#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0 -#define PAL_APPLICATION_REGISTER_READABLE 1 -#define PAL_CONTROL_REGISTER_IMPLEMENTED 2 -#define PAL_CONTROL_REGISTER_READABLE 3 - - -/** - PAL Procedure - PAL_REGISTER_INFO. - - Return AR and CR register information. It is required by Itanium process= ors. - The PAL procedure supports the Static Registers calling - convention. It could be called at physical mode and virtual - mode. - - @param Index Index of PAL_REGISTER_INFO within the list of - PAL procedures. - @param InfoRequest Unsigned 64-bit integer denoting what - register information is requested. See - PAL_REGISTER_INFO.InfoRequest above. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 64-bit vector denoting information for registers - 0-63. Bit 0 is register 0, bit 63 is register 63. - @return R10 64-bit vector denoting information for registers - 64-127. Bit 0 is register 64, bit 63 is register - 127. - -**/ -#define PAL_REGISTER_INFO 39 - -/** - PAL Procedure - PAL_RSE_INFO. - - Return RSE information. It is required by Itanium processors. The PAL - procedure supports the Static Registers calling convention. It - could be called at physical mode and virtual mode. - - @param Index Index of PAL_RSE_INFO within the list of - PAL procedures. - @param InfoRequest Unsigned 64-bit integer denoting what - register information is requested. See - PAL_REGISTER_INFO.InfoRequest above. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Number of physical stacked general registers. - @return R10 RSE hints supported by processor. - -**/ -#define PAL_RSE_INFO 19 - -typedef struct { - UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD) - ///< number that provides identification - ///< information about the PAL_B firmware. - UINT64 Reserved1:8; - UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicati= ng the - ///< vendor of the PAL code. - UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD) - ///< number that provides identification - ///< information about the PAL_A firmware.= In - ///< the split PAL_A model, this return va= lue - ///< is the version number of the - ///< processor-specific PAL_A. The generic - ///< PAL_A version is not returned by this - ///< procedure in the split PAL_A model. - UINT64 Reserved2:16; -} PAL_VERSION_INFO; - -/** - PAL Procedure - PAL_VERSION. - - Return version of PAL code. It is required by Itanium processors. The PAL - procedure supports the Static Registers calling convention. It - could be called at physical mode and virtual mode. - - @param Index Index of PAL_VERSION within the list of - PAL procedures. - @param InfoRequest Unsigned 64-bit integer denoting what - register information is requested. See - PAL_REGISTER_INFO.InfoRequest above. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 8-byte formatted value returning the minimum PAL - version needed for proper operation of the - processor. See PAL_VERSION_INFO above. - @return R10 8-byte formatted value returning the current PAL - version running on the processor. See - PAL_VERSION_INFO above. - -**/ -#define PAL_VERSION 20 - - - -// -// Vectors of PAL_MC_CLEAR_LOG.pending -// -#define PAL_MC_PENDING BIT0 -#define PAL_INIT_PENDING BIT1 - -/** - PAL Procedure - PAL_MC_CLEAR_LOG. - - Clear all error information from processor error logging - registers. It is required by Itanium processors. The PAL procedure suppo= rts - the Static Registers calling convention. It could be called at - physical mode and virtual mode. - - @param Index Index of PAL_MC_CLEAR_LOG within the list of - PAL procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 64-bit vector denoting whether an event is - pending. See PAL_MC_CLEAR_LOG.pending above. - -**/ -#define PAL_MC_CLEAR_LOG 21 - -/** - PAL Procedure - PAL_MC_DRAIN. - - Ensure that all operations that could cause an MCA have - completed. It is required by Itanium processors. The PAL procedure suppo= rts - the Static Registers calling convention. It could be called at - physical mode and virtual mode. - - @param Index Index of PAL_MC_DRAIN within the list of PAL - procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_MC_DRAIN 22 - - -/** - PAL Procedure - PAL_MC_DYNAMIC_STATE. - - Return Processor Dynamic State for logging by SAL. It is - optional. The PAL procedure supports the Static Registers - calling convention. It could be called at physical mode. - - @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL - procedures. - @param Offset Offset of the next 8 bytes of Dynamic Processor - State to return. (multiple of 8). - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure. - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned 64-bit integer denoting bytes of Dynamic - Processor State returned. - @return R10 Next 8 bytes of Dynamic Processor State. - -**/ -#define PAL_MC_DYNAMIC_STATE 24 - - - -// -// Values of PAL_MC_ERROR_INFO.InfoIndex. -// -#define PAL_PROCESSOR_ERROR_MAP 0 -#define PAL_PROCESSOR_STATE_PARAM 1 -#define PAL_STRUCTURE_SPECIFIC_ERROR 2 - -typedef struct { - UINT64 CoreId:4; ///< Bit3:0, Processor core ID (defau= lt is 0 for - ///< processors with a single core) - - UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (defaul= t is 0 for - ///< processors that execute a single = thread) - - UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is - ///< available for 1st, 2nd, 3rd, and = 4th - ///< level instruction caches. - - UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is - ///< available for 1st, 2nd, 3rd, an= d 4th - ///< level data/unified caches. - - UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is ava= ilable - ///< for 1st, 2nd, 3rd, and 4th level - ///< instruction TLB. - - UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is av= ailable - ///< for 1st, 2nd, 3rd, and 4th level - ///< data/unified TLB - - UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is - ///< available for the 1st, 2nd, 3rd, - ///< and 4th level processor bus - ///< hierarchy. - UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is - ///< available on register file - ///< structures. - UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is - ///< available on micro-architectural - ///< structures. - UINT64 Reserved:16; -} PAL_MC_ERROR_INFO_LEVEL_INDEX; - -// -// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex -// -#define PAL_ERR_INFO_BY_LEVEL_INDEX 0 -#define PAL_ERR_INFO_TARGET_ADDRESS 1 -#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2 -#define PAL_ERR_INFO_REPONSER_INDENTIFIER 3 -#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4 - -typedef struct { - UINT64 Operation:4; ///< Bit3:0, Type of cache operati= on that caused - ///< the machine check: 0 - unknow= n or internal - ///< error 1 - load 2 - store 3 - = instruction - ///< fetch or instruction prefetch= 4 - data - ///< prefetch (both hardware and s= oftware) 5 - - ///< snoop (coherency check) 6 - c= ast out - ///< (explicit or implicit write-b= ack of a cache - ///< line) 7 - move in (cache line= fill) - - UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where t= he - ///< error occurred. A value of 0 - ///< indicates the first level of = cache. - UINT64 Reserved1:2; - UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the = data part of the cache line. - UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the = tag part of the cache line. - UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the= data cache - - UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the - ///< instruction cache. - - UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is = invalid. 1 - cache - ///< line is held shared. 2 - cach= e line is held - ///< exclusive. 3 - cache line is = modified. All other - ///< values are reserved. - - UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the = cache_check - ///< parameter is valid. - - UINT64 FailedWay:5; ///< Bit20:16, Failure located in = the way of - ///< the cache indicated by this v= alue. - - UINT64 WayIndexIsValid:1; ///< Bit21, The way and index fiel= d in the - ///< cache_check parameter is vali= d. - - UINT64 Reserved2:1; - UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error w= as - ///< detected, and data was poison= ed for - ///< the corresponding cache line = during - ///< castout. - UINT64 Reserved3:8; - UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache - ///< line where the error occurred. - UINT64 Reserved4:2; - - UINT64 InstructionSet:1; ///< Bit54, Instruction set. If th= is value - ///< is set to zero, the instruc= tion that - ///< generated the machine check= was an - ///< Intel Itanium instruction. = If this bit - ///< is set to one, the instruct= ion that - ///< generated the machine check= was IA-32 - ///< instruction. - - UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the - ///< cache_check parameter is vali= d. - - UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The - ///< privilege level of the inst= ruction - ///< bundle responsible for gene= rating the - ///< machine check. - - UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the - ///< cache_check parameter is - ///< valid. - - UINT64 McCorrected:1; ///< Bit59, Machine check correcte= d: This bit - ///< is set to one to indicate t= hat the machine - ///< check has been corrected. - - UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is vali= d: - ///< This bit is set to one to - ///< indicate that a valid target - ///< address has been logged. - - UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: = This - ///< bit is set to one to indica= te that - ///< a valid requester identifie= r has - ///< been logged. - - UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: = This - ///< bit is set to one to indica= te that - ///< a valid responder identifie= r has - ///< been logged. - - UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction p= ointer. - ///< This bit is set to one to ind= icate - ///< that a valid precise instruct= ion - ///< pointer has been logged. - -} PAL_CACHE_CHECK_INFO; - - -typedef struct { - UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the tr= anslation - ///< register where the failure oc= curred. - UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the - ///< TLB_check parameter is valid. - UINT64 Reserved1 :1; - UINT64 TlbLevel:2; ///< Bit11:10, The level of the T= LB where the - ///< error occurred. A value of 0 = indicates the - ///< first level of TLB - UINT64 Reserved2 :4; - - UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the = data - ///< translation registers. - - UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the = instruction - ///< translation registers - - UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data - ///< translation cache. - - UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the = instruction - ///< translation cache. - - UINT64 FailedOperation:4; ///< Bit23:20, Type of cache opera= tion that - ///< caused the machine check: 0= - unknown - ///< 1 - TLB access due to load = instruction - ///< 2 - TLB access due to store - ///< instruction 3 - TLB access = due to - ///< instruction fetch or instru= ction - ///< prefetch 4 - TLB access due= to data - ///< prefetch (both hardware and= software) - ///< 5 - TLB shoot down access 6= - TLB - ///< probe instruction (probe, t= pa) 7 - - ///< move in (VHPT fill) 8 - pur= ge (insert - ///< operation that purges entri= es or a TLB - ///< purge instruction) All othe= r values - ///< are reserved. - - UINT64 Reserved3:30; - UINT64 InstructionSet:1; ///< Bit54, Instruction set. If th= is value - ///< is set to zero, the instruc= tion that - ///< generated the machine check= was an - ///< Intel Itanium instruction. = If this bit - ///< is set to one, the instruct= ion that - ///< generated the machine check= was IA-32 - ///< instruction. - - UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the - ///< TLB_check parameter is valid. - - UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The - ///< privilege level of the inst= ruction - ///< bundle responsible for gene= rating the - ///< machine check. - - UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the - ///< TLB_check parameter is valid. - - UINT64 McCorrected:1; ///< Bit59, Machine check correcte= d: This bit - ///< is set to one to indicate t= hat the machine - ///< check has been corrected. - - UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is vali= d: - ///< This bit is set to one to - ///< indicate that a valid target - ///< address has been logged. - - UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: T= his - ///< bit is set to one to indica= te that - ///< a valid requester identifie= r has - ///< been logged. - - UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: = This - ///< bit is set to one to indica= te that - ///< a valid responder identifie= r has - ///< been logged. - - UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction poi= nter. - ///< This bit is set to one to i= ndicate - ///< that a valid precise instru= ction - ///< pointer has been logged. -} PAL_TLB_CHECK_INFO; - -/** - PAL Procedure - PAL_MC_ERROR_INFO. - - Return Processor Machine Check Information and Processor - Static State for logging by SAL. It is required by Itanium processors. T= he - PAL procedure supports the Static Registers calling - convention. It could be called at physical and virtual mode. - - @param Index Index of PAL_MC_ERROR_INFO within the list of PAL - procedures. - @param InfoIndex Unsigned 64-bit integer identifying the - error information that is being requested. - See PAL_MC_ERROR_INFO.InfoIndex. - @param LevelIndex 8-byte formatted value identifying the - structure to return error information - on. See PAL_MC_ERROR_INFO_LEVEL_INDEX. - @param ErrorTypeIndex Unsigned 64-bit integer denoting the - type of error information that is - being requested for the structure - identified in LevelIndex. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -6 Argument was valid, but no error - information was available - - @return R9 Error information returned. The format of this - value is dependant on the input values passed. - @return R10 If this value is zero, all the error information - specified by err_type_index has been returned. If - this value is one, more structure-specific error - information is available and the caller needs to - make this procedure call again with level_index - unchanged and err_type_index, incremented. - -**/ -#define PAL_MC_ERROR_INFO 25 - -/** - PAL Procedure - PAL_MC_EXPECTED. - - Set/Reset Expected Machine Check Indicator. It is required by - Itanium processors. The PAL procedure supports the Static Registers call= ing - convention. It could be called at physical mode. - - @param Index Index of PAL_MC_EXPECTED within the list of PAL - procedures. - @param Expected Unsigned integer with a value of 0 or 1 to - set or reset the hardware resource - PALE_CHECK examines for expected machine - checks. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned integer denoting whether a machine check - was previously expected. - -**/ -#define PAL_MC_EXPECTED 23 - -/** - PAL Procedure - PAL_MC_REGISTER_MEM. - - Register min-state save area with PAL for machine checks and - inits. It is required by Itanium processors. The PAL procedure supports = the - Static Registers calling convention. It could be called at - physical mode. - - @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL - procedures. - @param Address Physical address of the buffer to be - registered with PAL. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_MC_REGISTER_MEM 27 - -/** - PAL Procedure - PAL_MC_RESUME. - - Restore minimal architected state and return to interrupted - process. It is required by Itanium processors. The PAL procedure support= s the - Static Registers calling convention. It could be called at - physical mode. - - @param Index Index of PAL_MC_RESUME within the list of PAL - procedures. - @param SetCmci Unsigned 64 bit integer denoting whether to - set the CMC interrupt. A value of 0 indicates - not to set the interrupt, a value of 1 - indicated to set the interrupt, and all other - values are reserved. - @param SavePtr Physical address of min-state save area used - to used to restore processor state. - @param NewContext Unsigned 64-bit integer denoting whether - the caller is returning to a new context. - A value of 0 indicates the caller is - returning to the interrupted context, a - value of 1 indicates that the caller is - returning to a new context. - - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_MC_RESUME 26 - -/** - PAL Procedure - PAL_HALT. - - Enter the low-power HALT state or an implementation-dependent - low-power state. It is optinal. The PAL procedure supports the - Static Registers calling convention. It could be called at - physical mode. - - @param Index Index of PAL_HALT within the list of PAL - procedures. - @param HaltState Unsigned 64-bit integer denoting low power - state requested. - @param IoDetailPtr 8-byte aligned physical address pointer to - information on the type of I/O - (load/store) requested. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Value returned if a load instruction is requested - in the io_detail_ptr - -**/ -#define PAL_HALT 28 - - -/** - PAL Procedure - PAL_HALT_INFO. - - Return the low power capabilities of the processor. It is - required by Itanium processors. The PAL procedure supports the - Stacked Registers calling convention. It could be called at - physical and virtual mode. - - @param Index Index of PAL_HALT_INFO within the list of PAL - procedures. - @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned - on an 8-byte boundary. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_HALT_INFO 257 - - -/** - PAL Procedure - PAL_HALT_LIGHT. - - Enter the low power LIGHT HALT state. It is required by - Itanium processors. The PAL procedure supports the Static Registers call= ing - convention. It could be called at physical and virtual mode. - - @param Index Index of PAL_HALT_LIGHT within the list of PAL - procedures. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_HALT_LIGHT 29 - -/** - PAL Procedure - PAL_CACHE_LINE_INIT. - - Initialize tags and data of a cache line for processor - testing. It is required by Itanium processors. The PAL procedure support= s the - Static Registers calling convention. It could be called at - physical and virtual mode. - - @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL - procedures. - @param Address Unsigned 64-bit integer value denoting the - physical address from which the physical page - number is to be generated. The address must be - an implemented physical address, bit 63 must - be zero. - @param DataValue 64-bit data value which is used to - initialize the cache line. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_CACHE_LINE_INIT 31 - -/** - PAL Procedure - PAL_CACHE_READ. - - Read tag and data of a cache line for diagnostic testing. It - is optional. The PAL procedure supports the - Satcked Registers calling convention. It could be called at - physical mode. - - @param Index Index of PAL_CACHE_READ within the list of PAL - procedures. - @param LineId 8-byte formatted value describing where in the - cache to read the data. - @param Address 64-bit 8-byte aligned physical address from - which to read the data. The address must be an - implemented physical address on the processor - model with bit 63 set to zero. - - @retval 1 The word at address was found in the - cache, but the line was invalid. - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -5 The word at address was not found in the - cache. - @retval -7 The operation requested is not supported - for this cache_type and level. - - @return R9 Right-justified value returned from the cache - line. - @return R10 The number of bits returned in data. - @return R11 The status of the cache line. - -**/ -#define PAL_CACHE_READ 259 - - -/** - PAL Procedure - PAL_CACHE_WRITE. - - Write tag and data of a cache for diagnostic testing. It is - optional. The PAL procedure supports the Satcked Registers - calling convention. It could be called at physical mode. - - @param Index Index of PAL_CACHE_WRITE within the list of PAL - procedures. - @param LineId 8-byte formatted value describing where in the - cache to write the data. - @param Address 64-bit 8-byte aligned physical address at - which the data should be written. The address - must be an implemented physical address on the - processor model with bit 63 set to 0. - @param Data Unsigned 64-bit integer value to write into - the specified part of the cache. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -7 The operation requested is not supported - for this cache_type and level. - -**/ -#define PAL_CACHE_WRITE 260 - -/** - PAL Procedure - PAL_TEST_INFO. - - Returns alignment and size requirements needed for the memory - buffer passed to the PAL_TEST_PROC procedure as well as - information on self-test control words for the processor self - tests. It is required by Itanium processors. The PAL procedure supports = the - Static Registers calling convention. It could be called at - physical mode. - - @param Index Index of PAL_TEST_INFO within the list of PAL - procedures. - @param TestPhase Unsigned integer that specifies which phase - of the processor self-test information is - being requested on. A value of 0 indicates - the phase two of the processor self-test and - a value of 1 indicates phase one of the - processor self-test. All other values are - reserved. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned 64-bit integer denoting the number of - bytes of main memory needed to perform the second - phase of processor self-test. - @return R10 Unsigned 64-bit integer denoting the alignment - required for the memory buffer. - @return R11 48-bit wide bit-field indicating if control of - the processor self-tests is supported and which - bits of the test_control field are defined for - use. - -**/ -#define PAL_TEST_INFO 37 - -typedef struct { - UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory - ///< buffer that is passed to this procedure. - ///< BufferSize must be greater than or equal = in - ///< size to the bytes_needed return value from - ///< PAL_TEST_INFO, otherwise this procedure w= ill - ///< return with an invalid argument return - ///< value. - - UINT64 TestPhase:8; ///< Defines which phase of the processor - ///< self-tests are requested to be run. A val= ue - ///< of zero indicates to run phase two of the - ///< processor self-tests. Phase two of the - ///< processor self-tests are ones that require - ///< external memory to execute correctly. A - ///< value of one indicates to run phase one of - ///< the processor self-tests. Phase one of the - ///< processor self-tests are tests run during - ///< PALE_RESET and do not depend on external - ///< memory to run correctly. When the caller - ///< requests to have phase one of the process= or - ///< self-test run via this procedure call, a - ///< memory buffer may be needed to save and - ///< restore state as required by the PAL call= ing - ///< conventions. The procedure PAL_TEST_INFO - ///< informs the caller about the requirements= of - ///< the memory buffer. -} PAL_TEST_INFO_INFO; - -typedef struct { - UINT64 TestControl:47; ///< This is an ordered implementation-spe= cific - ///< control word that allows the user c= ontrol - ///< over the length and runtime of the - ///< processor self-tests. This control = word is - ///< ordered from the longest running te= sts up - ///< to the shortest running tests with = bit 0 - ///< controlling the longest running tes= t. PAL - ///< may not implement all 47-bits of the - ///< test_control word. PAL communicates= if a - ///< bit provides control by placing a z= ero in - ///< that bit. If a bit provides no cont= rol, - ///< PAL will place a one in it. PAL wil= l have - ///< two sets of test_control bits for t= he two - ///< phases of the processor self-test. = PAL - ///< provides information about implemen= ted - ///< test_control bits at the hand-off f= rom PAL - ///< to SAL for the firmware recovery ch= eck. - ///< These test_control bits provide con= trol - ///< for phase one of processor self-tes= t. It - ///< also provides this information via = the PAL - ///< procedure call PAL_TEST_INFO for bo= th the - ///< phase one and phase two processor t= ests - ///< depending on which information the = caller - ///< is requesting. PAL interprets these= bits - ///< as input parameters on two occasion= s. The - ///< first time is when SAL passes contr= ol back - ///< to PAL after the firmware recovery = check. - ///< The second time is when a call to - ///< PAL_TEST_PROC is made. When PAL int= erprets - ///< these bits it will only interpret - ///< implemented test_control bits and w= ill - ///< ignore the values located in the - ///< unimplemented test_control bits. PAL - ///< interprets the implemented bits suc= h that - ///< if a bit contains a zero, this indi= cates - ///< to run the test. If a bit contains = a one, - ///< this indicates to PAL to skip the t= est. If - ///< the cs bit indicates that control i= s not - ///< available, the test_control bits w= ill be - ///< ignored or generate an illegal argu= ment in - ///< procedure calls if the caller sets = these - ///< bits. - - UINT64 ControlSupport:1; ///< This bit defines if an implementation - ///< supports control of the PAL self-tes= ts - ///< via the self-test control word. If - ///< this bit is 0, the implementation do= es - ///< not support control of the processor - ///< self-tests via the self-test control - ///< word. If this bit is 1, the - ///< implementation does support control = of - ///< the processor self-tests via the - ///< self-test control word. If control is - ///< not supported, GR37 will be ignored = at - ///< the hand-off between SAL and PAL aft= er - ///< the firmware recovery check and the - ///< PAL procedures related to the - ///< processor self-tests may return - ///< illegal arguments if a user tries to - ///< use the self-test control features. - UINT64 Reserved:16; -} PAL_SELF_TEST_CONTROL; - -typedef struct { - UINT64 Attributes:8; ///< Specifies the memory attributes that = are - ///< allowed to be used with the memory b= uffer - ///< passed to this procedure. The attrib= utes - ///< parameter is a vector where each bit - ///< represents one of the virtual memory - ///< attributes defined by the architectu= re.See - ///< MEMORY_AATRIBUTES. The caller is req= uired - ///< to support the cacheable attribute f= or the - ///< memory buffer, otherwise an invalid - ///< argument will be returned. - UINT64 Reserved:8; - UINT64 TestControl:48; ///< Is the self-test control word - ///< corresponding to the test_phase pass= ed. - ///< This test_control directs the covera= ge and - ///< runtime of the processor self-tests - ///< specified by the test_phase input - ///< argument. Information on if this - ///< feature is implemented and the numbe= r of - ///< bits supported can be obtained by the - ///< PAL_TEST_INFO procedure call. If this - ///< feature is implemented by the proces= sor, - ///< the caller can selectively skip part= s of - ///< the processor self-test by setting - ///< test_control bits to a one. If a bit= has a - ///< zero, this test will be run. The val= ues in - ///< the unimplemented bits are ignored. = If - ///< PAL_TEST_INFO indicated that the sel= f-test - ///< control word is not implemented, this - ///< procedure will return with an invalid - ///< argument status if the caller sets a= ny of - ///< the test_control bits. See - ///< PAL_SELF_TEST_CONTROL. -} PAL_TEST_CONTROL; - -/** - PAL Procedure - PAL_TEST_PROC. - - Perform late processor self test. It is required by Itanium processors. = The - PAL procedure supports the Static Registers calling - convention. It could be called at physical mode. - - @param Index Index of PAL_TEST_PROC within the list of PAL - procedures. - @param TestAddress 64-bit physical address of main memory - area to be used by processor self-test. - The memory region passed must be - cacheable, bit 63 must be zero. - @param TestInfo Input argument specifying the size of the - memory buffer passed and the phase of the - processor self-test that should be run. See - PAL_TEST_INFO. - @param TestParam Input argument specifying the self-test - control word and the allowable memory - attributes that can be used with the memory - buffer. See PAL_TEST_CONTROL. - - @retval 1 Call completed without error, but hardware - failures occurred during self-test. - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Formatted 8-byte value denoting the state of the - processor after self-test - -**/ -#define PAL_TEST_PROC 258 - -typedef struct { - UINT32 NumberOfInterruptControllers; ///< Number of interrupt - ///< controllers currently - ///< enabled on the system. - - UINT32 NumberOfProcessors; ///< Number of processors curr= ently - ///< enabled on the system. -} PAL_PLATFORM_INFO; - -/** - PAL Procedure - PAL_COPY_INFO. - - Return information needed to relocate PAL procedures and PAL - PMI code to memory. It is required by Itanium processors. The PAL proced= ure - supports the Static Registers calling convention. It could be - called at physical mode. - - @param Index Index of PAL_COPY_INFO within the list of PAL - procedures. - @param CopyType Unsigned integer denoting type of procedures - for which copy information is requested. - @param PlatformInfo 8-byte formatted value describing the - number of processors and the number of - interrupt controllers currently enabled - on the system. See PAL_PLATFORM_INFO. - @param McaProcStateInfo Unsigned integer denoting the number - of bytes that SAL needs for the - min-state save area for each - processor. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned integer denoting the number of bytes = of - PAL information that must be copied to main - memory. - @return R10 Unsigned integer denoting the starting alignme= nt - of the data to be copied. - -**/ -#define PAL_COPY_INFO 30 - -/** - PAL Procedure - PAL_COPY_PAL. - - Relocate PAL procedures and PAL PMI code to memory. It is - required by Itanium processors. The PAL procedure supports the Stacked - Registers calling convention. It could be called at physical - mode. - - @param Index Index of PAL_COPY_PAL within the list of PAL - procedures. - @param TargetAddress Physical address of a memory buffer to - copy relocatable PAL procedures and PAL - PMI code. - @param AllocSize Unsigned integer denoting the size of the - buffer passed by SAL for the copy operation. - @param CopyOption Unsigned integer indicating whether - relocatable PAL code and PAL PMI code - should be copied from firmware address - space to main memory. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned integer denoting the offset of PAL_PROC - in the relocatable segment copied. - -**/ -#define PAL_COPY_PAL 256 - -/** - PAL Procedure - PAL_ENTER_IA_32_ENV. - - Enter IA-32 System environment. It is optional. The PAL - procedure supports the Static Registers calling convention. - It could be called at physical mode. - - Note: Since this is a special call, it does not follow the PAL - static register calling convention. GR28 contains the index of - PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other - input arguments including GR29-GR31 are setup by SAL to values - as required by the IA-32 operating system defined in Table - 11-67. The registers that are designated as preserved, scratch, - input arguments and procedure return values by the static - procedure calling convention are not followed by this call. For - instance, GR5 and GR6 need not be preserved since these are - regarded as scratch by the IA-32 operating system. Note: In an - MP system, this call must be COMPLETED on the first CPU to enter - the IA-32 System Environment (may or may not be the BSP) prior - to being called on the remaining processors in the MP system. - - @param Index GR28 contains the index of the - PAL_ENTER_IA_32_ENV call within the list of PAL - procedures. - - - @retval The status is returned in GR4. - -1 - Un-implemented procedure 0 JMPE detected - at privilege level - - 0 - 1 SAL allocated buffer for IA-32 System - Environment operation is too small - - 2 - IA-32 Firmware Checksum Error - - 3 - SAL allocated buffer for IA-32 System - Environment operation is not properly aligned - - 4 - Error in SAL MP Info Table - - 5 - Error in SAL Memory Descriptor Table - - 6 - Error in SAL System Table - - 7 - Inconsistent IA-32 state - - 8 - IA-32 Firmware Internal Error - - 9 - IA-32 Soft Reset (Note: remaining register - state is undefined for this termination - reason) - - 10 - Machine Check Error - - 11 - Error in SAL I/O Intercept Table - - 12 - Processor exit due to other processor in - MP system terminating the IA32 system - environment. (Note: remaining register state - is undefined for this termination reason.) - - 13 - Itanium architecture-based state - corruption by either SAL PMI handler or I/O - Intercept callback function. - - -**/ -#define PAL_ENTER_IA_32_ENV 33 - -/** - PAL Procedure - PAL_PMI_ENTRYPOINT. - - Register PMI memory entrypoints with processor. It is required - by Itanium processors. The PAL procedure supports the Stacked Registers - calling convention. It could be called at physical mode. - - @param Index Index of PAL_PMI_ENTRYPOINT within the list of - PAL procedures. - @param SalPmiEntry 256-byte aligned physical address of SAL - PMI entrypoint in memory. - - @retval 0 Call completed without error - @retval -2 Invalid argument - @retval -3 Call completed with error. - -**/ -#define PAL_PMI_ENTRYPOINT 32 - - -/** - - The ASCII brand identification string will be copied to the - address specified in the address input argument. The processor - brand identification string is defined to be a maximum of 128 - characters long; 127 bytes will contain characters and the 128th - byte is defined to be NULL (0). A processor may return less than - the 127 ASCII characters as long as the string is null - terminated. The string length will be placed in the brand_info - return argument. - -**/ -#define PAL_BRAND_INFO_ID_REQUEST 0 - -/** - PAL Procedure - PAL_BRAND_INFO. - - Provides processor branding information. It is optional by - Itanium processors. The PAL procedure supports the Stacked Registers cal= ling - convention. It could be called at physical and Virtual mode. - - @param Index Index of PAL_BRAND_INFO within the list of PAL - procedures. - @param InfoRequest Unsigned 64-bit integer specifying the - information that is being requested. (See - PAL_BRAND_INFO_ID_REQUEST) - @param Address Unsigned 64-bit integer specifying the - address of the 128-byte block to which the - processor brand string shall be written. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -6 Input argument is not implemented. - - @return R9 Brand information returned. The format of this - value is dependent on the input values passed. - -**/ -#define PAL_BRAND_INFO 274 - -/** - PAL Procedure - PAL_GET_HW_POLICY. - - Returns the current hardware resource sharing policy of the - processor. It is optional by Itanium processors. The PAL procedure suppo= rts - the Static Registers calling convention. It could be called at - physical and Virtual mode. - - - @param Index Index of PAL_GET_HW_POLICY within the list of PAL - procedures. - @param ProcessorNumber Unsigned 64-bit integer that specifies - for which logical processor - information is being requested. This - input argument must be zero for the - first call to this procedure and can - be a maximum value of one less than - the number of logical processors - impacted by the hardware resource - sharing policy, which is returned by - the R10 return value. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - - @return R9 Unsigned 64-bit integer representing the current - hardware resource sharing policy. - @return R10 Unsigned 64-bit integer that returns the number - of logical processors impacted by the policy - input argument. - @return R11 Unsigned 64-bit integer containing the logical - address of one of the logical processors - impacted by policy modification. - -**/ -#define PAL_GET_HW_POLICY 48 - - -// -// Value of PAL_SET_HW_POLICY.Policy -// -#define PAL_SET_HW_POLICY_PERFORMANCE 0 -#define PAL_SET_HW_POLICY_FAIRNESS 1 -#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2 -#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3 - -/** - PAL Procedure - PAL_SET_HW_POLICY. - - Sets the current hardware resource sharing policy of the - processor. It is optional by Itanium processors. The PAL procedure suppo= rts - the Static Registers calling convention. It could be called at - physical and Virtual mode. - - @param Index Index of PAL_SET_HW_POLICY within the list of PAL - procedures. - @param Policy Unsigned 64-bit integer specifying the hardware - resource sharing policy the caller is setting. - See Value of PAL_SET_HW_POLICY.Policy above. - - @retval 1 Call completed successfully but could not - change the hardware policy since a - competing logical processor is set in - exclusive high priority. - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_SET_HW_POLICY 49 - -typedef struct { - UINT64 Mode:3; ///< Bit2:0, Indicates the mode of ope= ration for this - ///< procedure: 0 - Query mode 1 - = Error inject mode - ///< (err_inj should also be specif= ied) 2 - Cancel - ///< outstanding trigger. All other= fields in - ///< PAL_MC_ERROR_TYPE_INFO, - ///< PAL_MC_ERROR_STRUCTURE_INFO and - ///< PAL_MC_ERROR_DATA_BUFFER are i= gnored. All other - ///< values are reserved. - - UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of err= or - ///< injection: 0 - Error inject only= (no - ///< error consumption) 1 - Error inj= ect - ///< and consume All other values are - ///< reserved. - - UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity de= sired - ///< for error injection/query. Defin= itions - ///< of the different error severity = types - ///< 0 - Corrected error 1 - Recovera= ble - ///< error 2 - Fatal error 3 - Reserv= ed - - UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure - ///< identification for error - ///< injection/query: 0 - Any structu= re - ///< (cannot be used during query mod= e). - ///< When selected, the structure typ= e used - ///< for error injection is determine= d by - ///< PAL. 1 - Cache 2 - TLB 3 - Regis= ter - ///< file 4 - Bus/System interconnect= 5-15 - ///< - Reserved 16-31 - Processor - ///< specific error injection - ///< capabilities.ErrorDataBuffer is = used - ///< to specify error types. Please r= efer - ///< to the processor specific - ///< documentation for additional det= ails. - - UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure - ///< hierarchy for error - ///< injection/query: 0 - Any level of - ///< hierarchy (cannot be used during - ///< query mode). When selected, the - ///< structure hierarchy used for err= or - ///< injection is determined by PAL. 1 - ///< - Error structure hierarchy - ///< level-1 2 - Error structure - ///< hierarchy level-2 3 - Error - ///< structure hierarchy level-3 4 - - ///< Error structure hierarchy level-4 - ///< All other values are reserved. - - UINT64 Reserved:32; ///< Reserved 47:16 Reserved - - UINT64 ImplSpec:16; ///< Bit63:48, Processor specific erro= r injection capabilities. -} PAL_MC_ERROR_TYPE_INFO; - -typedef struct { - UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates th= at the - ///< structure information fie= lds - ///< (c_t,cl_p,cl_id) are vali= d and - ///< should be used for error = injection. - ///< When 0, the structure inf= ormation - ///< fields are ignored, and t= he values - ///< of these fields used for = error - ///< injection are - ///< implementation-specific. - - UINT64 CacheType:2; ///< Bit2:1 Indicates which c= ache should be used - ///< for error injection: 0 - = Reserved 1 - - ///< Instruction cache 2 - Dat= a or unified cache - ///< 3 - Reserved - - UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the port= ion of the - ///< cache line where the er= ror should - ///< be injected: 0 - Reserv= ed 1 - Tag - ///< 2 - Data 3 - mesi All o= ther - ///< values are reserved. - - UINT64 Mechanism:3; ///< Bit8:6 Indicates which me= chanism is used to - ///< identify the cache line t= o be used for error - ///< injection: 0 - Reserved 1= - Virtual address - ///< provided in the inj_addr = field of the buffer - ///< pointed to by err_data_bu= ffer should be used - ///< to identify the cache lin= e for error - ///< injection. 2 - Physical a= ddress provided in - ///< the inj_addr field of the= buffer pointed to - ///< by err_data_buffershould = be used to identify - ///< the cache line for error = injection. 3 - way - ///< and index fields provided= in err_data_buffer - ///< should be used to identif= y the cache line - ///< for error injection. All = other values are - ///< reserved. - - UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates th= at a - ///< multiple bit, non-correct= able - ///< error should be injected = in the - ///< cache line specified by c= l_id. - ///< If this injected error is= not - ///< consumed, it may eventual= ly - ///< cause a data-poisoning ev= ent - ///< resulting in a corrected = error - ///< signal, when the associat= ed - ///< cache line is cast out (i= mplicit - ///< or explicit write-back of= the - ///< cache line). The error se= verity - ///< specified by err_sev in - ///< err_type_info must be set= to 0 - ///< (corrected error) when th= is bit - ///< is set. - - UINT64 Reserved1:22; - - UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates t= hat the - ///< trigger information field= s (trigger, - ///< trigger_pl) are valid and= should be - ///< used for error injection.= When 0, - ///< the trigger information f= ields are - ///< ignored and error injecti= on is - ///< performed immediately. - - UINT64 Triger:4; ///< Bit36:33 Indicates the op= eration type to be - ///< used as the error trigg= er condition. The - ///< address corresponding t= o the trigger is - ///< specified in the trigge= r_addr field of the - ///< buffer pointed to by er= r_data_buffer: 0 - - ///< Instruction memory acce= ss. The trigger match - ///< conditions for this ope= ration type are similar - ///< to the IBR address brea= kpoint match conditions - ///< 1 - Data memory access.= The trigger match - ///< conditions for this ope= ration type are similar - ///< to the DBR address brea= kpoint match conditions - ///< All other values are re= served. - - UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the p= rivilege - ///< level of the context duri= ng which - ///< the error should be injec= ted: 0 - - ///< privilege level 0 1 - pri= vilege - ///< level 1 2 - privilege lev= el 2 3 - - ///< privilege level 3 All oth= er values - ///< are reserved. If the impl= ementation - ///< does not support privileg= e level - ///< qualifier for triggers (i= .e. if - ///< trigger_pl is 0 in the ca= pabilities - ///< vector), this field is ig= nored and - ///< triggers can be taken at = any - ///< privilege level. - - UINT64 Reserved2:24; -} PAL_MC_ERROR_STRUCT_INFO; - -/** - - Buffer Pointed to by err_data_buffer - TLB - -**/ -typedef struct { - UINT64 TrigerAddress; - UINT64 VirtualPageNumber:52; - UINT64 Reserved1:8; - UINT64 RegionId:24; - UINT64 Reserved2:40; -} PAL_MC_ERROR_DATA_BUFFER_TLB; - -/** - PAL Procedure - PAL_MC_ERROR_INJECT. - - Injects the requested processor error or returns information - on the supported injection capabilities for this particular - processor implementation. It is optional by Itanium processors. The PAL - procedure supports the Stacked Registers calling convention. - It could be called at physical and Virtual mode. - - @param Index Index of PAL_MC_ERROR_INJECT within the list of = PAL - procedures. - @param ErrorTypeInfo Unsigned 64-bit integer specifying the - first level error information which - identifies the error structure and - corresponding structure hierarchy, and - the error severity. - @param ErrorStructInfo Unsigned 64-bit integer identifying - the optional structure specific - information that provides the second - level details for the requested error. - @param ErrorDataBuffer 64-bit physical address of a buffer - providing additional parameters for - the requested error. The address of - this buffer must be 8-byte aligned. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -4 Call completed with error; the requested - error could not be injected due to failure in - locating the target location in the specified - structure. - @retval -5 Argument was valid, but requested error - injection capability is not supported. - @retval -9 Call requires PAL memory buffer. - - @return R9 64-bit vector specifying the supported error - injection capabilities for the input argument - combination of struct_hier, err_struct and - err_sev fields in ErrorTypeInfo. - @return R10 64-bit vector specifying the architectural - resources that are used by the procedure. - -**/ -#define PAL_MC_ERROR_INJECT 276 - - -// -// Types of PAL_GET_PSTATE.Type -// -#define PAL_GET_PSTATE_RECENT 0 -#define PAL_GET_PSTATE_AVERAGE_NEW_START 1 -#define PAL_GET_PSTATE_AVERAGE 2 -#define PAL_GET_PSTATE_NOW 3 - -/** - PAL Procedure - PAL_GET_PSTATE. - - Returns the performance index of the processor. It is optional - by Itanium processors. The PAL procedure supports the Stacked Registers - calling convention. It could be called at physical and Virtual - mode. - - @param Index Index of PAL_GET_PSTATE within the list of PAL - procedures. - @param Type Type of performance_index value to be returned - by this procedure.See PAL_GET_PSTATE.Type above. - - @retval 1 Call completed without error, but accuracy - of performance index has been impacted by a - thermal throttling event, or a - hardware-initiated event. - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - - @return R9 Unsigned integer denoting the processor - performance for the time duration since the last - PAL_GET_PSTATE procedure call was made. The - value returned is between 0 and 100, and is - relative to the performance index of the highest - available P-state. - -**/ -#define PAL_GET_PSTATE 262 - -/** - - Layout of PAL_PSTATE_INFO.PStateBuffer - -**/ -typedef struct { - UINT32 PerformanceIndex:7; - UINT32 Reserved1:5; - UINT32 TypicalPowerDissipation:20; - UINT32 TransitionLatency1; - UINT32 TransitionLatency2; - UINT32 Reserved2; -} PAL_PSTATE_INFO_BUFFER; - - -/** - PAL Procedure - PAL_PSTATE_INFO. - - Returns information about the P-states supported by the - processor. It is optional by Itanium processors. The PAL procedure suppo= rts - the Static Registers calling convention. It could be called - at physical and Virtual mode. - - @param Index Index of PAL_PSTATE_INFO within the list of PAL - procedures. - @param PStateBuffer 64-bit pointer to a 256-byte buffer - aligned on an 8-byte boundary. See - PAL_PSTATE_INFO_BUFFER above. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - - @return R9 Unsigned integer denoting the number of P-states - supported. The maximum value of this field is 16. - @return R10 Dependency domain information - -**/ -#define PAL_PSTATE_INFO 44 - - -/** - PAL Procedure - PAL_SET_PSTATE. - - To request a processor transition to a given P-state. It is - optional by Itanium processors. The PAL procedure supports the Stacked - Registers calling convention. It could be called at physical - and Virtual mode. - - @param Index Index of PAL_SET_PSTATE within the list of PAL - procedures. - @param PState Unsigned integer denoting the processor - P-state being requested. - @param ForcePState Unsigned integer denoting whether the - P-state change should be forced for the - logical processor. - - @retval 1 Call completed without error, but - transition request was not accepted - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_SET_PSTATE 263 - -/** - PAL Procedure - PAL_SHUTDOWN. - - Put the logical processor into a low power state which can be - exited only by a reset event. It is optional by Itanium processors. The = PAL - procedure supports the Static Registers calling convention. It - could be called at physical mode. - - @param Index Index of PAL_SHUTDOWN within the list of PAL - procedures. - @param NotifyPlatform 8-byte aligned physical address - pointer providing details on how to - optionally notify the platform that - the processor is entering a shutdown - state. - - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_SHUTDOWN 45 - -/** - - Layout of PAL_MEMORY_BUFFER.ControlWord - -**/ -typedef struct { - UINT64 Registration:1; - UINT64 ProbeInterrupt:1; - UINT64 Reserved:62; -} PAL_MEMORY_CONTROL_WORD; - -/** - PAL Procedure - PAL_MEMORY_BUFFER. - - Provides cacheable memory to PAL for exclusive use during - runtime. It is optional by Itanium processors. The PAL procedure support= s the - Static Registers calling convention. It could be called at - physical mode. - - @param Index Index of PAL_MEMORY_BUFFER within the list of PAL - procedures. - @param BaseAddress Physical address of the memory buffer - allocated for PAL use. - @param AllocSize Unsigned integer denoting the size of the - memory buffer. - @param ControlWord Formatted bit vector that provides control - options for this procedure. See - PAL_MEMORY_CONTROL_WORD above. - - @retval 1 Call has not completed a buffer relocation - due to a pending interrupt - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - - @return R9 Returns the minimum size of the memory buffer - required if the alloc_size input argument was - not large enough. - -**/ -#define PAL_MEMORY_BUFFER 277 - - -/** - PAL Procedure - PAL_VP_CREATE. - - Initializes a new vpd for the operation of a new virtual - processor in the virtual environment. It is optional by Itanium processo= rs. - The PAL procedure supports the Stacked Registers calling - convention. It could be called at Virtual mode. - - @param Index Index of PAL_VP_CREATE within the list of PAL - procedures. - @param Vpd 64-bit host virtual pointer to the Virtual - Processor Descriptor (VPD). - @param HostIva 64-bit host virtual pointer to the host IVT - for the virtual processor - @param OptionalHandler 64-bit non-zero host-virtual pointer - to an optional handler for - virtualization intercepts. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_VP_CREATE 265 - -/** - - Virtual Environment Information Parameter - -**/ -typedef struct { - UINT64 Reserved1:8; - UINT64 Opcode:1; - UINT64 Reserved:53; -} PAL_VP_ENV_INFO_RETURN; - -/** - PAL Procedure - PAL_VP_ENV_INFO. - - Returns the parameters needed to enter a virtual environment. - It is optional by Itanium processors. The PAL procedure supports the Sta= cked - Registers calling convention. It could be called at Virtual - mode. - - @param Index Index of PAL_VP_ENV_INFO within the list of PAL - procedures. - @param Vpd 64-bit host virtual pointer to the Virtual - Processor Descriptor (VPD). - @param HostIva 64-bit host virtual pointer to the host IVT - for the virtual processor - @param OptionalHandler 64-bit non-zero host-virtual pointer - to an optional handler for - virtualization intercepts. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - - @return R9 Unsigned integer denoting the number of bytes - required by the PAL virtual environment buffer - during PAL_VP_INIT_ENV - @return R10 64-bit vector of virtual environment - information. See PAL_VP_ENV_INFO_RETURN. - - -**/ -#define PAL_VP_ENV_INFO 266 - -/** - PAL Procedure - PAL_VP_EXIT_ENV. - - Allows a logical processor to exit a virtual environment. - It is optional by Itanium processors. The PAL procedure supports the Sta= cked - Registers calling convention. It could be called at Virtual - mode. - - @param Index Index of PAL_VP_EXIT_ENV within the list of PAL - procedures. - @param Iva Optional 64-bit host virtual pointer to the IVT - when this procedure is done - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_VP_EXIT_ENV 267 - - - -/** - PAL Procedure - PAL_VP_INIT_ENV. - - Allows a logical processor to enter a virtual environment. It - is optional by Itanium processors. The PAL procedure supports the Stacked - Registers calling convention. It could be called at Virtual - mode. - - @param Index Index of PAL_VP_INIT_ENV within the list of PAL - procedures. - @param ConfigOptions 64-bit vector of global configuration - settings. - @param PhysicalBase Host physical base address of a block of - contiguous physical memory for the PAL - virtual environment buffer 1) This - memory area must be allocated by the VMM - and be 4K aligned. The first logical - processor to enter the environment will - initialize the physical block for - virtualization operations. - @param VirtualBase Host virtual base address of the - corresponding physical memory block for - the PAL virtual environment buffer : The - VMM must maintain the host virtual to host - physical data and instruction translations - in TRs for addresses within the allocated - address space. Logical processors in this - virtual environment will use this address - when transitioning to virtual mode - operations. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - - @return R9 Virtualization Service Address - VSA specifies - the virtual base address of the PAL - virtualization services in this virtual - environment. - - -**/ -#define PAL_VP_INIT_ENV 268 - - -/** - PAL Procedure - PAL_VP_REGISTER. - - Register a different host IVT and/or a different optional - virtualization intercept handler for the virtual processor - specified by vpd. It is optional by Itanium processors. The PAL procedure - supports the Stacked Registers calling convention. It could be - called at Virtual mode. - - @param Index Index of PAL_VP_REGISTER within the list of PAL - procedures. - @param Vpd 64-bit host virtual pointer to the Virtual - Processor Descriptor (VPD) host_iva 64-bit host - virtual pointer to the host IVT for the virtual - processor - @param OptionalHandler 64-bit non-zero host-virtual pointer - to an optional handler for - virtualization intercepts. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_VP_REGISTER 269 - - -/** - PAL Procedure - PAL_VP_RESTORE. - - Restores virtual processor state for the specified vpd on the - logical processor. It is optional by Itanium processors. The PAL procedu= re - supports the Stacked Registers calling convention. It could be - called at Virtual mode. - - @param Index Index of PAL_VP_RESTORE within the list of PAL - procedures. - @param Vpd 64-bit host virtual pointer to the Virtual - Processor Descriptor (VPD) host_iva 64-bit host - virtual pointer to the host IVT for the virtual - processor - @param PalVector Vector specifies PAL procedure - implementation-specific state to be - restored. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_VP_RESTORE 270 - -/** - PAL Procedure - PAL_VP_SAVE. - - Saves virtual processor state for the specified vpd on the - logical processor. It is optional by Itanium processors. The PAL procedu= re - supports the Stacked Registers calling convention. It could be - called at Virtual mode. - - @param Index Index of PAL_VP_SAVE within the list of PAL - procedures. - @param Vpd 64-bit host virtual pointer to the Virtual - Processor Descriptor (VPD) host_iva 64-bit host - virtual pointer to the host IVT for the virtual - processor - @param PalVector Vector specifies PAL procedure - implementation-specific state to be - restored. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_VP_SAVE 271 - - -/** - PAL Procedure - PAL_VP_TERMINATE. - - Terminates operation for the specified virtual processor. It - is optional by Itanium processors. The PAL procedure supports the Stacked - Registers calling convention. It could be called at Virtual - mode. - - @param Index Index of PAL_VP_TERMINATE within the list of PAL - procedures. - @param Vpd 64-bit host virtual pointer to the Virtual - Processor Descriptor (VPD) - @param Iva Optional 64-bit host virtual pointer to the IVT - when this procedure is done. - - @retval 0 Call completed without error - @retval -1 Unimplemented procedure - @retval -2 Invalid argument - @retval -3 Call completed with error. - @retval -9 Call requires PAL memory buffer. - -**/ -#define PAL_VP_TERMINATE 272 - -#endif diff --git a/MdePkg/Include/IndustryStandard/Sal.h b/MdePkg/Include/Industr= yStandard/Sal.h deleted file mode 100644 index ae9c4c5263..0000000000 --- a/MdePkg/Include/IndustryStandard/Sal.h +++ /dev/null @@ -1,909 +0,0 @@ -/** @file - Main SAL API's defined in Intel Itanium Processor Family System Abstract= ion - Layer Specification Revision 3.2 (December 2003) - -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __SAL_API_H__ -#define __SAL_API_H__ - -/// -/// SAL return status type -/// -typedef INTN EFI_SAL_STATUS; - -/// -/// Call completed without error. -/// -#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0) -/// -/// Call completed without error, but some information was lost due to ove= rflow. -/// -#define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1) -/// -/// Call completed without error; effect a warm boot of the system to comp= lete the update. -/// -#define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2) -/// -/// More information is available for retrieval. -/// -#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3) -/// -/// Not implemented. -/// -#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1) -/// -/// Invalid Argument. -/// -#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2) -/// -/// Call completed without error. -/// -#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3) -/// -/// Virtual address not registered. -/// -#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4) -/// -/// No information available. -/// -#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5) -/// -/// Scratch buffer required. -/// -#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9) - -/// -/// Return registers from SAL. -/// -typedef struct { - /// - /// SAL return status value in r8. - /// - EFI_SAL_STATUS Status; - /// - /// SAL returned value in r9. - /// - UINTN r9; - /// - /// SAL returned value in r10. - /// - UINTN r10; - /// - /// SAL returned value in r11. - /// - UINTN r11; -} SAL_RETURN_REGS; - -/** - Prototype of SAL procedures. - - @param FunctionId Functional identifier. - The upper 32 bits are ignored and only the lo= wer 32 bits - are used. The following functional identifier= s are defined: - 0x01XXXXXX - Architected SAL functional group. - 0x02XXXXXX to 0x03XXXXXX - OEM SAL functional= group. Each OEM is - allowed to use the entire range in the 0x02XX= XXXX to 0x03XXXXXX range. - 0x04XXXXXX to 0xFFFFFFFF - Reserved. - @param Arg1 The first parameter of the architected/OEM sp= ecific SAL functions. - @param Arg2 The second parameter of the architected/OEM s= pecific SAL functions. - @param Arg3 The third parameter passed to the ESAL functi= on based. - @param Arg4 The fourth parameter passed to the ESAL funct= ion based. - @param Arg5 The fifth parameter passed to the ESAL functi= on based. - @param Arg6 The sixth parameter passed to the ESAL functi= on. - @param Arg7 The seventh parameter passed to the ESAL func= tion based. - - @return r8 Return status: positive number indicates succ= essful, - negative number indicates failure. - r9 Other return parameter in r9. - r10 Other return parameter in r10. - r11 Other return parameter in r11. - -**/ -typedef -SAL_RETURN_REGS -(EFIAPI *SAL_PROC)( - IN UINT64 FunctionId, - IN UINT64 Arg1, - IN UINT64 Arg2, - IN UINT64 Arg3, - IN UINT64 Arg4, - IN UINT64 Arg5, - IN UINT64 Arg6, - IN UINT64 Arg7 - ); - -// -// SAL Procedure FunctionId definition -// - -/// -/// Register software code locations with SAL. -/// -#define EFI_SAL_SET_VECTORS 0x01000000 -/// -/// Return Machine State information obtained by SAL. -/// -#define EFI_SAL_GET_STATE_INFO 0x01000001 -/// -/// Obtain size of Machine State information. -/// -#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002 -/// -/// Clear Machine State information. -/// -#define EFI_SAL_CLEAR_STATE_INFO 0x01000003 -/// -/// Cause the processor to go into a spin loop within SAL. -/// -#define EFI_SAL_MC_RENDEZ 0x01000004 -/// -/// Register the machine check interface layer with SAL. -/// -#define EFI_SAL_MC_SET_PARAMS 0x01000005 -/// -/// Register the physical addresses of locations needed by SAL. -/// -#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006 -/// -/// Flush the instruction or data caches. -/// -#define EFI_SAL_CACHE_FLUSH 0x01000008 -/// -/// Initialize the instruction and data caches. -/// -#define EFI_SAL_CACHE_INIT 0x01000009 -/// -/// Read from the PCI configuration space. -/// -#define EFI_SAL_PCI_CONFIG_READ 0x01000010 -/// -/// Write to the PCI configuration space. -/// -#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011 -/// -/// Return the base frequency of the platform. -/// -#define EFI_SAL_FREQ_BASE 0x01000012 -/// -/// Returns information on the physical processor mapping within the platf= orm. -/// -#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013 -/// -/// Update the contents of firmware blocks. -/// -#define EFI_SAL_UPDATE_PAL 0x01000020 - -#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff -#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021 - -// -// SAL Procedure parameter definitions -// Not much point in using typedefs or enums because all params -// are UINT64 and the entry point is common -// - -// -// Parameter of EFI_SAL_SET_VECTORS -// -// Vector type -// -#define EFI_SAL_SET_MCA_VECTOR 0x0 -#define EFI_SAL_SET_INIT_VECTOR 0x1 -#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2 -/// -/// The format of a length_cs_n argument. -/// -typedef struct { - UINT64 Length : 32; - UINT64 ChecksumValid : 1; - UINT64 Reserved1 : 7; - UINT64 ByteChecksum : 8; - UINT64 Reserved2 : 16; -} SAL_SET_VECTORS_CS_N; - -// -// Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and E= FI_SAL_CLEAR_STATE_INFO -// -// Type of information -// -#define EFI_SAL_MCA_STATE_INFO 0x0 -#define EFI_SAL_INIT_STATE_INFO 0x1 -#define EFI_SAL_CMC_STATE_INFO 0x2 -#define EFI_SAL_CP_STATE_INFO 0x3 - -// -// Parameter of EFI_SAL_MC_SET_PARAMS -// -// Unsigned 64-bit integer value for the parameter type of the machine che= ck interface -// -#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1 -#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2 -#define EFI_SAL_MC_SET_CPE_PARAM 0x3 -// -// Unsigned 64-bit integer value indicating whether interrupt vector or -// memory address is specified -// -#define EFI_SAL_MC_SET_INTR_PARAM 0x1 -#define EFI_SAL_MC_SET_MEM_PARAM 0x2 - -// -// Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR -// -// The encoded value of the entity whose physical address is registered -// -#define EFI_SAL_REGISTER_PAL_ADDR 0x0 - -// -// Parameter of EFI_SAL_CACHE_FLUSH -// -// Unsigned 64-bit integer denoting type of cache flush operation -// -#define EFI_SAL_FLUSH_I_CACHE 0x01 -#define EFI_SAL_FLUSH_D_CACHE 0x02 -#define EFI_SAL_FLUSH_BOTH_CACHE 0x03 -#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04 - -// -// Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE -// -// PCI config size -// -#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1 -#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2 -#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4 -// -// The type of PCI configuration address -// -#define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0 -#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1 -/// -/// The format of PCI Compatible Address. -/// -typedef struct { - UINT64 Register : 8; - UINT64 Function : 3; - UINT64 Device : 5; - UINT64 Bus : 8; - UINT64 Segment : 8; - UINT64 Reserved : 32; -} SAL_PCI_ADDRESS; -/// -/// The format of Extended Register Address. -/// -typedef struct { - UINT64 Register : 8; - UINT64 ExtendedRegister : 4; - UINT64 Function : 3; - UINT64 Device : 5; - UINT64 Bus : 8; - UINT64 Segment : 16; - UINT64 Reserved : 20; -} SAL_PCI_EXTENDED_REGISTER_ADDRESS; - -// -// Parameter of EFI_SAL_FREQ_BASE -// -// Unsigned 64-bit integer specifying the type of clock source -// -#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0 -#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1 -#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2 - -// -// Parameter and return value of EFI_SAL_UPDATE_PAL -// -// Return parameter provides additional information on the -// failure when the status field contains a value of -3, -// returned in r9. -// -#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1) -#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2) -#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3) -#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4) -#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10) -#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11) -#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12) -#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13) -/// -/// 64-byte header of update data block. -/// -typedef struct { - UINT32 Size; - UINT32 MmddyyyyDate; - UINT16 Version; - UINT8 Type; - UINT8 Reserved[5]; - UINT64 FwVendorId; - UINT8 Reserved2[40]; -} SAL_UPDATE_PAL_DATA_BLOCK; -/// -/// Data structure pointed by the parameter param_buf. -/// It is a 16-byte aligned data structure in memory with a length of 32 b= ytes -/// that describes the new firmware. This information is organized in the = form -/// of a linked list with each element describing one firmware component. -/// -typedef struct _SAL_UPDATE_PAL_INFO_BLOCK { - struct _SAL_UPDATE_PAL_INFO_BLOCK *Next; - struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock; - UINT8 StoreChecksum; - UINT8 Reserved[15]; -} SAL_UPDATE_PAL_INFO_BLOCK; - -/// -/// SAL System Table Definitions. -/// -#pragma pack(1) -typedef struct { - /// - /// The ASCII string representation of "SST_" that confirms the presence= of the table. - /// - UINT32 Signature; - /// - /// The length of the entire table in bytes, starting from offset zero a= nd including the - /// header and all entries indicated by the EntryCount field. - /// - UINT32 Length; - /// - /// The revision number of the Itanium Processor Family System Abstracti= on Layer - /// Specification supported by the SAL implementation, in binary coded d= ecimal (BCD) format. - /// - UINT16 SalRevision; - /// - /// The number of entries in the variable portion of the table. - /// - UINT16 EntryCount; - /// - /// A modulo checksum of the entire table and the entries following this= table. - /// - UINT8 CheckSum; - /// - /// Unused, must be zero. - /// - UINT8 Reserved[7]; - /// - /// Version Number of the SAL_A firmware implementation in BCD format. - /// - UINT16 SalAVersion; - /// - /// Version Number of the SAL_B firmware implementation in BCD format. - /// - UINT16 SalBVersion; - /// - /// An ASCII identification string which uniquely identifies the manufac= turer - /// of the system hardware. - /// - UINT8 OemId[32]; - /// - /// An ASCII identification string which uniquely identifies a family of - /// compatible products from the manufacturer. - /// - UINT8 ProductId[32]; - /// - /// Unused, must be zero. - /// - UINT8 Reserved2[8]; -} SAL_SYSTEM_TABLE_HEADER; - -#define EFI_SAL_ST_HEADER_SIGNATURE "SST_" -#define EFI_SAL_REVISION 0x0320 -// -// SAL System Types -// -#define EFI_SAL_ST_ENTRY_POINT 0 -#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1 -#define EFI_SAL_ST_PLATFORM_FEATURES 2 -#define EFI_SAL_ST_TR_USAGE 3 -#define EFI_SAL_ST_PTC 4 -#define EFI_SAL_ST_AP_WAKEUP 5 - -// -// SAL System Type Sizes -// -#define EFI_SAL_ST_ENTRY_POINT_SIZE 48 -#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32 -#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16 -#define EFI_SAL_ST_TR_USAGE_SIZE 32 -#define EFI_SAL_ST_PTC_SIZE 16 -#define EFI_SAL_ST_AP_WAKEUP_SIZE 16 - -/// -/// Format of Entrypoint Descriptor Entry. -/// -typedef struct { - UINT8 Type; ///< Type here should be 0. - UINT8 Reserved[7]; - UINT64 PalProcEntry; - UINT64 SalProcEntry; - UINT64 SalGlobalDataPointer; - UINT64 Reserved2[2]; -} SAL_ST_ENTRY_POINT_DESCRIPTOR; - -/// -/// Format of Platform Features Descriptor Entry. -/// -typedef struct { - UINT8 Type; ///< Type here should be 2. - UINT8 PlatformFeatures; - UINT8 Reserved[14]; -} SAL_ST_PLATFORM_FEATURES; - -// -// Value of Platform Feature List -// -#define SAL_PLAT_FEAT_BUS_LOCK 0x01 -#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02 -#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04 - -/// -/// Format of Translation Register Descriptor Entry. -/// -typedef struct { - UINT8 Type; ///< Type here should be 3. - UINT8 TRType; - UINT8 TRNumber; - UINT8 Reserved[5]; - UINT64 VirtualAddress; - UINT64 EncodedPageSize; - UINT64 Reserved1; -} SAL_ST_TR_DECRIPTOR; - -// -// Type of Translation Register -// -#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00 -#define EFI_SAL_ST_TR_USAGE_DATA 01 - -/// -/// Definition of Coherence Domain Information. -/// -typedef struct { - UINT64 NumberOfProcessors; - UINT64 LocalIDRegister; -} SAL_COHERENCE_DOMAIN_INFO; - -/// -/// Format of Purge Translation Cache Coherence Domain Entry. -/// -typedef struct { - UINT8 Type; ///< Type here should be 4. - UINT8 Reserved[3]; - UINT32 NumberOfDomains; - SAL_COHERENCE_DOMAIN_INFO *DomainInformation; -} SAL_ST_CACHE_COHERENCE_DECRIPTOR; - -/// -/// Format of Application Processor Wake-Up Descriptor Entry. -/// -typedef struct { - UINT8 Type; ///< Type here should be 5. - UINT8 WakeUpType; - UINT8 Reserved[6]; - UINT64 ExternalInterruptVector; -} SAL_ST_AP_WAKEUP_DECRIPTOR; - -/// -/// Format of Firmware Interface Table (FIT) Entry. -/// -typedef struct { - UINT64 Address; - UINT8 Size[3]; - UINT8 Reserved; - UINT16 Revision; - UINT8 Type : 7; - UINT8 CheckSumValid : 1; - UINT8 CheckSum; -} EFI_SAL_FIT_ENTRY; -// -// FIT Types -// -#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00 -#define EFI_SAL_FIT_PAL_B_TYPE 0x01 -// -// Type from 0x02 to 0x0D is reserved. -// -#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E -#define EFI_SAL_FIT_PAL_A_TYPE 0x0F -// -// OEM-defined type range is from 0x10 to 0x7E. -// Here we defined the PEI_CORE type as 0x10 -// -#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10 -#define EFI_SAL_FIT_UNUSED_TYPE 0x7F - -// -// FIT Entry -// -#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24 -#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32 -#define EFI_SAL_FIT_PALB_TYPE 01 - -// -// Following definitions are for Error Record Structure -// - -/// -/// Format of TimeStamp field in Record Header. -/// -typedef struct { - UINT8 Seconds; - UINT8 Minutes; - UINT8 Hours; - UINT8 Reserved; - UINT8 Day; - UINT8 Month; - UINT8 Year; - UINT8 Century; -} SAL_TIME_STAMP; -/// -/// Definition of Record Header. -/// -typedef struct { - UINT64 RecordId; - UINT16 Revision; - UINT8 ErrorSeverity; - UINT8 ValidationBits; - UINT32 RecordLength; - SAL_TIME_STAMP TimeStamp; - UINT8 OemPlatformId[16]; -} SAL_RECORD_HEADER; -/// -/// Definition of Section Header. -/// -typedef struct { - GUID Guid; - UINT16 Revision; - UINT8 ErrorRecoveryInfo; - UINT8 Reserved; - UINT32 SectionLength; -} SAL_SEC_HEADER; - -/// -/// GUID of Processor Machine Check Errors. -/// -#define SAL_PROCESSOR_ERROR_RECORD_INFO \ - { \ - 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, = 0x81 } \ - } -// -// Bit masks for valid bits of MOD_ERROR_INFO -// -#define CHECK_INFO_VALID_BIT_MASK 0x1 -#define REQUESTOR_ID_VALID_BIT_MASK 0x2 -#define RESPONDER_ID_VALID_BIT_MASK 0x4 -#define TARGER_ID_VALID_BIT_MASK 0x8 -#define PRECISE_IP_VALID_BIT_MASK 0x10 -/// -/// Definition of MOD_ERROR_INFO_STRUCT. -/// -typedef struct { - UINT64 InfoValid : 1; - UINT64 ReqValid : 1; - UINT64 RespValid : 1; - UINT64 TargetValid : 1; - UINT64 IpValid : 1; - UINT64 Reserved : 59; - UINT64 Info; - UINT64 Req; - UINT64 Resp; - UINT64 Target; - UINT64 Ip; -} MOD_ERROR_INFO; -/// -/// Definition of CPUID_INFO_STRUCT. -/// -typedef struct { - UINT8 CpuidInfo[40]; - UINT8 Reserved; -} CPUID_INFO; - -typedef struct { - UINT64 FrLow; - UINT64 FrHigh; -} FR_STRUCT; -// -// Bit masks for PSI_STATIC_STRUCT.ValidFieldBits -// -#define MIN_STATE_VALID_BIT_MASK 0x1 -#define BR_VALID_BIT_MASK 0x2 -#define CR_VALID_BIT_MASK 0x4 -#define AR_VALID_BIT_MASK 0x8 -#define RR_VALID_BIT_MASK 0x10 -#define FR_VALID_BIT_MASK 0x20 -/// -/// Definition of PSI_STATIC_STRUCT. -/// -typedef struct { - UINT64 ValidFieldBits; - UINT8 MinStateInfo[1024]; - UINT64 Br[8]; - UINT64 Cr[128]; - UINT64 Ar[128]; - UINT64 Rr[8]; - FR_STRUCT Fr[128]; -} PSI_STATIC_STRUCT; -// -// Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits -// -#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1 -#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2 -#define PROC_CR_LID_VALID_BIT_MASK 0x4 -#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8 -#define CPU_INFO_VALID_BIT_MASK 0x1000000 -/// -/// Definition of Processor Machine Check Error Record. -/// -typedef struct { - SAL_SEC_HEADER SectionHeader; - UINT64 ValidationBits; - UINT64 ProcErrorMap; - UINT64 ProcStateParameter; - UINT64 ProcCrLid; - MOD_ERROR_INFO CacheError[15]; - MOD_ERROR_INFO TlbError[15]; - MOD_ERROR_INFO BusError[15]; - MOD_ERROR_INFO RegFileCheck[15]; - MOD_ERROR_INFO MsCheck[15]; - CPUID_INFO CpuInfo; - PSI_STATIC_STRUCT PsiValidData; -} SAL_PROCESSOR_ERROR_RECORD; - -/// -/// GUID of Platform Memory Device Error Info. -/// -#define SAL_MEMORY_ERROR_RECORD_INFO \ - { \ - 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, = 0x81 } \ - } -// -// Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits -// -#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1 -#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2 -#define MEMORY_ADDR_BIT_MASK 0x4 -#define MEMORY_NODE_VALID_BIT_MASK 0x8 -#define MEMORY_CARD_VALID_BIT_MASK 0x10 -#define MEMORY_MODULE_VALID_BIT_MASK 0x20 -#define MEMORY_BANK_VALID_BIT_MASK 0x40 -#define MEMORY_DEVICE_VALID_BIT_MASK 0x80 -#define MEMORY_ROW_VALID_BIT_MASK 0x100 -#define MEMORY_COLUMN_VALID_BIT_MASK 0x200 -#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400 -#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800 -#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000 -#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000 -#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000 -#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000 -#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000 -/// -/// Definition of Platform Memory Device Error Info Record. -/// -typedef struct { - SAL_SEC_HEADER SectionHeader; - UINT64 ValidationBits; - UINT64 MemErrorStatus; - UINT64 MemPhysicalAddress; - UINT64 MemPhysicalAddressMask; - UINT16 MemNode; - UINT16 MemCard; - UINT16 MemModule; - UINT16 MemBank; - UINT16 MemDevice; - UINT16 MemRow; - UINT16 MemColumn; - UINT16 MemBitPosition; - UINT64 ModRequestorId; - UINT64 ModResponderId; - UINT64 ModTargetId; - UINT64 BusSpecificData; - UINT8 MemPlatformOemId[16]; -} SAL_MEMORY_ERROR_RECORD; - -/// -/// GUID of Platform PCI Bus Error Info. -/// -#define SAL_PCI_BUS_ERROR_RECORD_INFO \ - { \ - 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, = 0x81 } \ - } -// -// Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits -// -#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1 -#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2 -#define PCI_BUS_ID_VALID_BIT_MASK 0x4 -#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8 -#define PCI_BUS_DATA_VALID_BIT_MASK 0x10 -#define PCI_BUS_CMD_VALID_BIT_MASK 0x20 -#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40 -#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80 -#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100 -#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200 -#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400 - -/// -/// Designated PCI Bus identifier. -/// -typedef struct { - UINT8 BusNumber; - UINT8 SegmentNumber; -} PCI_BUS_ID; - -/// -/// Definition of Platform PCI Bus Error Info Record. -/// -typedef struct { - SAL_SEC_HEADER SectionHeader; - UINT64 ValidationBits; - UINT64 PciBusErrorStatus; - UINT16 PciBusErrorType; - PCI_BUS_ID PciBusId; - UINT32 Reserved; - UINT64 PciBusAddress; - UINT64 PciBusData; - UINT64 PciBusCommand; - UINT64 PciBusRequestorId; - UINT64 PciBusResponderId; - UINT64 PciBusTargetId; - UINT8 PciBusOemId[16]; -} SAL_PCI_BUS_ERROR_RECORD; - -/// -/// GUID of Platform PCI Component Error Info. -/// -#define SAL_PCI_COMP_ERROR_RECORD_INFO \ - { \ - 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, = 0x81 } \ - } -// -// Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits -// -#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1 -#define PCI_COMP_INFO_VALID_BIT_MASK 0x2 -#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4 -#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8 -#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10 -#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20 -/// -/// Format of PCI Component Information to identify the device. -/// -typedef struct { - UINT16 VendorId; - UINT16 DeviceId; - UINT8 ClassCode[3]; - UINT8 FunctionNumber; - UINT8 DeviceNumber; - UINT8 BusNumber; - UINT8 SegmentNumber; - UINT8 Reserved[5]; -} PCI_COMP_INFO; -/// -/// Definition of Platform PCI Component Error Info. -/// -typedef struct { - SAL_SEC_HEADER SectionHeader; - UINT64 ValidationBits; - UINT64 PciComponentErrorStatus; - PCI_COMP_INFO PciComponentInfo; - UINT32 PciComponentMemNum; - UINT32 PciComponentIoNum; - UINT8 PciBusOemId[16]; -} SAL_PCI_COMPONENT_ERROR_RECORD; - -/// -/// Platform SEL Device Error Info. -/// -#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \ - { \ - 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, = 0x81 } \ - } -// -// Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits -// -#define SEL_RECORD_ID_VALID_BIT_MASK 0x1; -#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2; -#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4; -#define SEL_EVM_REV_VALID_BIT_MASK 0x8; -#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10; -#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20; -#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40; -#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80; -#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100; -#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200; -/// -/// Definition of Platform SEL Device Error Info Record. -/// -typedef struct { - SAL_SEC_HEADER SectionHeader; - UINT64 ValidationBits; - UINT16 SelRecordId; - UINT8 SelRecordType; - UINT32 TimeStamp; - UINT16 GeneratorId; - UINT8 EvmRevision; - UINT8 SensorType; - UINT8 SensorNum; - UINT8 EventDirType; - UINT8 Data1; - UINT8 Data2; - UINT8 Data3; -} SAL_SEL_DEVICE_ERROR_RECORD; - -/// -/// GUID of Platform SMBIOS Device Error Info. -/// -#define SAL_SMBIOS_ERROR_RECORD_INFO \ - { \ - 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, = 0x81 } \ - } -// -// Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits -// -#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1 -#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2 -#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4 -#define SMBIOS_DATA_VALID_BIT_MASK 0x8 -/// -/// Definition of Platform SMBIOS Device Error Info Record. -/// -typedef struct { - SAL_SEC_HEADER SectionHeader; - UINT64 ValidationBits; - UINT8 SmbiosEventType; - UINT8 SmbiosLength; - UINT8 SmbiosBcdTimeStamp[6]; -} SAL_SMBIOS_DEVICE_ERROR_RECORD; - -/// -/// GUID of Platform Specific Error Info. -/// -#define SAL_PLATFORM_ERROR_RECORD_INFO \ - { \ - 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, = 0x81 } \ - } -// -// Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits -// -#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1 -#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2 -#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4 -#define PLATFORM_TARGET_VALID_BIT_MASK 0x8 -#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10 -#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20 -#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40 -#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80 -/// -/// Definition of Platform Specific Error Info Record. -/// -typedef struct { - SAL_SEC_HEADER SectionHeader; - UINT64 ValidationBits; - UINT64 PlatformErrorStatus; - UINT64 PlatformRequestorId; - UINT64 PlatformResponderId; - UINT64 PlatformTargetId; - UINT64 PlatformBusSpecificData; - UINT8 OemComponentId[16]; -} SAL_PLATFORM_SPECIFIC_ERROR_RECORD; - -/// -/// Union of all the possible SAL Error Record Types. -/// -typedef union { - SAL_RECORD_HEADER *RecordHeader; - SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord; - SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord; - SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord; - SAL_SEL_DEVICE_ERROR_RECORD *ImpiRecord; - SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord; - SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord; - SAL_MEMORY_ERROR_RECORD *MemoryRecord; - UINT8 *Raw; -} SAL_ERROR_RECORDS_POINTERS; - -#pragma pack() - -#endif diff --git a/MdePkg/Include/Library/ExtendedSalLib.h b/MdePkg/Include/Libra= ry/ExtendedSalLib.h deleted file mode 100644 index 85cfe5a34c..0000000000 --- a/MdePkg/Include/Library/ExtendedSalLib.h +++ /dev/null @@ -1,488 +0,0 @@ -/** @file - Library class definition of Extended SAL Library. - -Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef _EXTENDED_SAL_LIB_H__ -#define _EXTENDED_SAL_LIB_H__ - -#include - -/** - Register ESAL Class and its associated global. - - This function Registers one or more Extended SAL services in a given - class along with the associated global context. - This function is only available prior to ExitBootServices(). - - @param ClassGuidLo GUID of function class, lower 64-bits - @param ClassGuidHi GUID of function class, upper 64-bits - @param ModuleGlobal Module global for Function. - @param ... List of Function/FunctionId pairs, ended by= NULL - - @retval EFI_SUCCESS The Extended SAL services were registered. - @retval EFI_UNSUPPORTED This function was called after ExitBootServ= ices(). - @retval EFI_OUT_OF_RESOURCES There are not enough resources available to= register one or more of the specified services. - @retval Other ClassGuid could not be installed onto a new= handle. - -**/ -EFI_STATUS -EFIAPI -RegisterEsalClass ( - IN CONST UINT64 ClassGuidLo, - IN CONST UINT64 ClassGuidHi, - IN VOID *ModuleGlobal, OPTIONAL - ... - ); - -/** - Calls an Extended SAL Class service that was previously registered with = RegisterEsalClass(). - - This function calls an Extended SAL Class service that was previously re= gistered with RegisterEsalClass(). - - @param ClassGuidLo GUID of function, lower 64-bits - @param ClassGuidHi GUID of function, upper 64-bits - @param FunctionId Function in ClassGuid to call - @param Arg2 Argument 2 ClassGuid/FunctionId defined - @param Arg3 Argument 3 ClassGuid/FunctionId defined - @param Arg4 Argument 4 ClassGuid/FunctionId defined - @param Arg5 Argument 5 ClassGuid/FunctionId defined - @param Arg6 Argument 6 ClassGuid/FunctionId defined - @param Arg7 Argument 7 ClassGuid/FunctionId defined - @param Arg8 Argument 8 ClassGuid/FunctionId defined - - @retval EFI_SAL_ERROR The address of ExtendedSalProc() can not be deter= mined - for the current CPU execution mode. - @retval Other See the return status from ExtendedSalProc() in t= he - EXTENDED_SAL_BOOT_SERVICE_PROTOCOL. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalCall ( - IN UINT64 ClassGuidLo, - IN UINT64 ClassGuidHi, - IN UINT64 FunctionId, - IN UINT64 Arg2, - IN UINT64 Arg3, - IN UINT64 Arg4, - IN UINT64 Arg5, - IN UINT64 Arg6, - IN UINT64 Arg7, - IN UINT64 Arg8 - ); - -/** - Wrapper for the EsalStallFunctionId service of Extended SAL Stall Servic= es Class. - - This function is a wrapper for the EsalStallFunctionId service of Extend= ed SAL - Stall Services Class. See EsalStallFunctionId of Extended SAL Specificat= ion. - - @param Microseconds The number of microseconds to dela= y. - - @retval EFI_SAL_SUCCESS Call completed without error. - @retval EFI_SAL_INVALID_ARGUMENT Invalid argument. - @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR Virtual address not registered - -**/ -SAL_RETURN_REGS -EFIAPI -EsalStall ( - IN UINTN Microseconds - ); - -/** - Wrapper for the EsalSetNewPalEntryFunctionId service of Extended SAL PAL= Services Services Class. - - This function is a wrapper for the EsalSetNewPalEntryFunctionId service = of Extended SAL - PAL Services Services Class. See EsalSetNewPalEntryFunctionId of Extende= d SAL Specification. - - @param PhysicalAddress If TRUE, then PalEntryPoint is a = physical address. - If FALSE, then PalEntryPoint is a= virtual address. - @param PalEntryPoint The PAL Entry Point being set. - - @retval EFI_SAL_SUCCESS The PAL Entry Point was set. - @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtu= al mode before - virtual mappings for the specifie= d Extended SAL - Procedure are available. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalSetNewPalEntry ( - IN BOOLEAN PhysicalAddress, - IN UINT64 PalEntryPoint - ); - -/** - Wrapper for the EsalGetNewPalEntryFunctionId service of Extended SAL PAL= Services Services Class. - - This function is a wrapper for the EsalGetNewPalEntryFunctionId service = of Extended SAL - PAL Services Services Class. See EsalGetNewPalEntryFunctionId of Extende= d SAL Specification. - - @param PhysicalAddress If TRUE, then PalEntryPoint is a = physical address. - If FALSE, then PalEntryPoint is a= virtual address. - - @retval EFI_SAL_SUCCESS The PAL Entry Point was retrieved= and returned in - SAL_RETURN_REGS.r9. - @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtu= al mode before - virtual mappings for the specifie= d Extended SAL - Procedure are available. - @return r9 PAL entry point retrieved. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalGetNewPalEntry ( - IN BOOLEAN PhysicalAddress - ); - -/** - Wrapper for the EsalGetStateBufferFunctionId service of Extended SAL MCA= Log Services Class. - - This function is a wrapper for the EsalGetStateBufferFunctionId service = of Extended SAL - MCA Log Services Class. See EsalGetStateBufferFunctionId of Extended SAL= Specification. - - @param McaType See type parameter of SAL Procedure SAL_GE= T_STATE_INFO. - @param McaBuffer A pointer to the base address of the retur= ned buffer. - Copied from SAL_RETURN_REGS.r9. - @param BufferSize A pointer to the size, in bytes, of the re= turned buffer. - Copied from SAL_RETURN_REGS.r10. - - @retval EFI_SAL_SUCCESS The memory buffer to store error records w= as returned in r9 and r10. - @retval EFI_OUT_OF_RESOURCES A memory buffer for string error records i= n not available - @return r9 Base address of the returned buffer - @return r10 Size of the returned buffer in bytes - -**/ -SAL_RETURN_REGS -EFIAPI -EsalGetStateBuffer ( - IN UINT64 McaType, - OUT UINT8 **McaBuffer, - OUT UINTN *BufferSize - ); - -/** - Wrapper for the EsalSaveStateBufferFunctionId service of Extended SAL MC= A Log Services Class. - - This function is a wrapper for the EsalSaveStateBufferFunctionId service= of Extended SAL - MCA Log Services Class. See EsalSaveStateBufferFunctionId of Extended SA= L Specification. - - @param McaType See type parameter of SAL Procedure SAL_GET_STATE_I= NFO. - - @retval EFI_SUCCESS The memory buffer containing the error record was w= ritten to nonvolatile storage. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalSaveStateBuffer ( - IN UINT64 McaType - ); - -/** - Wrapper for the EsalGetVectorsFunctionId service of Extended SAL Base Se= rvices Class. - - This function is a wrapper for the EsalGetVectorsFunctionId service of E= xtended SAL - Base Services Class. See EsalGetVectorsFunctionId of Extended SAL Specif= ication. - - @param VectorType The vector type to retrieve. - 0 - MCA, 1 - BSP INIT, 2 - BOOT_RENDEZ,= 3 - AP INIT. - - @retval EFI_SAL_SUCCESS Call completed without error. - @retval EFI_SAL_INVALID_ARGUMENT Invalid argument. - @retval EFI_SAL_NO_INFORMATION The requested vector has not been regis= tered - with the SAL Procedure SAL_SET_VECTORS. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalGetVectors ( - IN UINT64 VectorType - ); - -/** - Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base S= ervices Class. - - This function is a wrapper for the EsalMcGetParamsFunctionId service of = Extended SAL - Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Speci= fication. - - @param ParamInfoType The parameter type to retrieve. - 1 - rendezvous interrupt - 2 - wake up - 3 - Corrected Platform Error Vector. - - @retval EFI_SAL_SUCCESS Call completed without error. - @retval EFI_SAL_INVALID_ARGUMENT Invalid argument. - @retval EFI_SAL_NO_INFORMATION The requested vector has not been regis= tered - with the SAL Procedure SAL_MC_SET_PARAM= S. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalMcGetParams ( - IN UINT64 ParamInfoType - ); - -/** - Wrapper for the EsalMcGetParamsFunctionId service of Extended SAL Base S= ervices Class. - - This function is a wrapper for the EsalMcGetParamsFunctionId service of = Extended SAL - Base Services Class. See EsalMcGetParamsFunctionId of Extended SAL Speci= fication. - - @retval EFI_SAL_SUCCESS Call completed without error. - @retval EFI_SAL_NO_INFORMATION The requested vector has not been regis= tered - with the SAL Procedure SAL_MC_SET_PARAM= S. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalMcGetMcParams ( - VOID - ); - -/** - Wrapper for the EsalGetMcCheckinFlagsFunctionId service of Extended SAL = Base Services Class. - - This function is a wrapper for the EsalGetMcCheckinFlagsFunctionId servi= ce of Extended SAL - Base Services Class. See EsalGetMcCheckinFlagsFunctionId of Extended SAL= Specification. - - @param CpuIndex The index of the CPU of set of enabled CPUs to = check. - - @retval EFI_SAL_SUCCESS The checkin status of the requested CPU was ret= urned. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalGetMcCheckinFlags ( - IN UINT64 CpuIndex - ); - -/** - Wrapper for the EsalAddCpuDataFunctionId service of Extended SAL MP Serv= ices Class. - - This function is a wrapper for the EsalAddCpuDataFunctionId service of E= xtended SAL - MP Services Class. See EsalAddCpuDataFunctionId of Extended SAL Specific= ation. - - @param CpuGlobalId The Global ID for the CPU being adde= d. - @param Enabled The enable flag for the CPU being ad= ded. - TRUE means the CPU is enabled. - FALSE means the CPU is disabled. - @param PalCompatibility The PAL Compatibility value for the = CPU being added. - - @retval EFI_SAL_SUCCESS The CPU was added to the database. - @retval EFI_SAL_NOT_ENOUGH_SCRATCH There are not enough resource availa= ble to add the CPU. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalAddCpuData ( - IN UINT64 CpuGlobalId, - IN BOOLEAN Enabled, - IN UINT64 PalCompatibility - ); - -/** - Wrapper for the EsalRemoveCpuDataFunctionId service of Extended SAL MP S= ervices Class. - - This function is a wrapper for the EsalRemoveCpuDataFunctionId service o= f Extended SAL - MP Services Class. See EsalRemoveCpuDataFunctionId of Extended SAL Speci= fication. - - @param CpuGlobalId The Global ID for the CPU being removed. - - @retval EFI_SAL_SUCCESS The CPU was removed from the database. - @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalRemoveCpuData ( - IN UINT64 CpuGlobalId - ); - -/** - Wrapper for the EsalModifyCpuDataFunctionId service of Extended SAL MP S= ervices Class. - - This function is a wrapper for the EsalModifyCpuDataFunctionId service o= f Extended SAL - MP Services Class. See EsalModifyCpuDataFunctionId of Extended SAL Speci= fication. - - @param CpuGlobalId The Global ID for the CPU being modified. - @param Enabled The enable flag for the CPU being modifi= ed. - TRUE means the CPU is enabled. - FALSE means the CPU is disabled. - @param PalCompatibility The PAL Compatibility value for the CPU = being modified. - - @retval EFI_SAL_SUCCESS The CPU database was updated. - @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalModifyCpuData ( - IN UINT64 CpuGlobalId, - IN BOOLEAN Enabled, - IN UINT64 PalCompatibility - ); - -/** - Wrapper for the EsalGetCpuDataByIdFunctionId service of Extended SAL MP = Services Class. - - This function is a wrapper for the EsalGetCpuDataByIdFunctionId service = of Extended SAL - MP Services Class. See EsalGetCpuDataByIdFunctionId of Extended SAL Spec= ification. - - @param CpuGlobalId The Global ID for the CPU being looked u= p. - @param IndexByEnabledCpu If TRUE, then the index of set of enable= d CPUs of database is returned. - If FALSE, then the index of set of all C= PUs of database is returned. - - @retval EFI_SAL_SUCCESS The information on the specified CPU was= returned. - @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalGetCpuDataById ( - IN UINT64 CpuGlobalId, - IN BOOLEAN IndexByEnabledCpu - ); - -/** - Wrapper for the EsalGetCpuDataByIndexFunctionId service of Extended SAL = MP Services Class. - - This function is a wrapper for the EsalGetCpuDataByIndexFunctionId servi= ce of Extended SAL - MP Services Class. See EsalGetCpuDataByIndexFunctionId of Extended SAL S= pecification. - - @param Index The Global ID for the CPU being modified. - @param IndexByEnabledCpu If TRUE, then the index of set of enable= d CPUs of database is returned. - If FALSE, then the index of set of all C= PUs of database is returned. - - @retval EFI_SAL_SUCCESS The information on the specified CPU was= returned. - @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalGetCpuDataByIndex ( - IN UINT64 Index, - IN BOOLEAN IndexByEnabledCpu - ); - -/** - Wrapper for the EsalWhoAmIFunctionId service of Extended SAL MP Services= Class. - - This function is a wrapper for the EsalWhoAmIFunctionId service of Exten= ded SAL - MP Services Class. See EsalWhoAmIFunctionId of Extended SAL Specificatio= n. - - @param IndexByEnabledCpu If TRUE, then the index of set of enable= d CPUs of database is returned. - If FALSE, then the index of set of all C= PUs of database is returned. - - @retval EFI_SAL_SUCCESS The Global ID for the calling CPU was re= turned. - @retval EFI_SAL_NO_INFORMATION The calling CPU is not in the database. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalWhoAmI ( - IN BOOLEAN IndexByEnabledCpu - ); - -/** - Wrapper for the EsalNumProcessors service of Extended SAL MP Services Cl= ass. - - This function is a wrapper for the EsalNumProcessors service of Extended= SAL - MP Services Class. See EsalNumProcessors of Extended SAL Specification. - - @retval EFI_SAL_SUCCESS The information on the number of CPUs in the = platform - was returned. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalNumProcessors ( - VOID - ); - -/** - Wrapper for the EsalSetMinStateFnctionId service of Extended SAL MP Serv= ices Class. - - This function is a wrapper for the EsalSetMinStateFnctionId service of E= xtended SAL - MP Services Class. See EsalSetMinStateFnctionId of Extended SAL Specific= ation. - - @param CpuGlobalId The Global ID for the CPU whose MINSTAT= E pointer is being set. - @param MinStatePointer The physical address of the MINSTATE bu= ffer for the CPU - specified by CpuGlobalId. - - @retval EFI_SAL_SUCCESS The MINSTATE pointer was set for the sp= ecified CPU. - @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the databas= e. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalSetMinState ( - IN UINT64 CpuGlobalId, - IN EFI_PHYSICAL_ADDRESS MinStatePointer - ); - -/** - Wrapper for the EsalGetMinStateFunctionId service of Extended SAL MP Ser= vices Class. - - This function is a wrapper for the EsalGetMinStateFunctionId service of = Extended SAL - MP Services Class. See EsalGetMinStateFunctionId of Extended SAL Specifi= cation. - - @param CpuGlobalId The Global ID for the CPU whose MINSTATE = pointer is being retrieved. - - @retval EFI_SAL_SUCCESS The MINSTATE pointer for the specified CP= U was retrieved. - @retval EFI_SAL_NO_INFORMATION The specified CPU is not in the database. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalGetMinState ( - IN UINT64 CpuGlobalId - ); - -/** - Wrapper for the EsalMcsGetStateInfoFunctionId service of Extended SAL MC= A Services Class. - - This function is a wrapper for the EsalMcsGetStateInfoFunctionId service= of Extended SAL - MCA Services Class. See EsalMcsGetStateInfoFunctionId of Extended SAL Sp= ecification. - - @param CpuGlobalId The Global ID for the CPU whose MCA st= ate buffer is being retrieved. - @param StateBufferPointer A pointer to the returned MCA state bu= ffer. - @param RequiredStateBufferSize A pointer to the size, in bytes, of th= e returned MCA state buffer. - - @retval EFI_SUCCESS MINSTATE successfully got and size cal= culated. - @retval EFI_SAL_NO_INFORMATION Fail to get MINSTATE. - -**/ -SAL_RETURN_REGS -EFIAPI -EsalMcaGetStateInfo ( - IN UINT64 CpuGlobalId, - OUT EFI_PHYSICAL_ADDRESS *StateBufferPointer, - OUT UINT64 *RequiredStateBufferSize - ); - -/** - Wrapper for the EsalMcaRegisterCpuFunctionId service of Extended SAL MCA= Services Class. - - This function is a wrapper for the EsalMcaRegisterCpuFunctionId service = of Extended SAL - MCA Services Class. See EsalMcaRegisterCpuFunctionId of Extended SAL Spe= cification. - - @param CpuGlobalId The Global ID for the CPU whose MCA sta= te buffer is being set. - @param StateBufferPointer A pointer to the MCA state buffer. - - @retval EFI_SAL_NO_INFORMATION Cannot get the processor info with the = CpuId - @retval EFI_SUCCESS Save the processor's state info success= fully - -**/ -SAL_RETURN_REGS -EFIAPI -EsalMcaRegisterCpu ( - IN UINT64 CpuGlobalId, - IN EFI_PHYSICAL_ADDRESS StateBufferPointer - ); - -#endif diff --git a/MdePkg/Include/Library/PalLib.h b/MdePkg/Include/Library/PalLi= b.h deleted file mode 100644 index 85be2b32ad..0000000000 --- a/MdePkg/Include/Library/PalLib.h +++ /dev/null @@ -1,57 +0,0 @@ -/** @file - Provides library services to make PAL Calls. - - The PAL Library provides a service to make a PAL CALL. This service is = identical - in functionality to AsmPalCall() in the functions of the Base Library sp= ecific to Intel Itanium architecture. - The only difference is that the PAL Entry Point is not passed in. Imple= mentations - of this library class must manage PAL Entry Point on their own. For exa= mple, a PEI - implementation can use a PPI to lookup the PAL Entry Point, and a DXE im= plementation - can contain a constructor to look up the PAL Entry Point from a HOB. Th= is library class - is only available on Intel Itanium-based platforms. - -Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __PAL_CALL_LIB_H__ -#define __PAL_CALL_LIB_H__ - -#include - -/** - Makes a PAL procedure call. - - This is a wrapper function to make a PAL procedure call. Based on the I= ndex value, - this API will make static or stacked PAL call. Architected procedures ma= y be designated - as required or optional. If a PAL procedure is specified as optional, a= unique return - code of 0xFFFFFFFFFFFFFFFF is returned in the Status field of the PAL_CA= LL_RETURN structure. - This indicates that the procedure is not present in this PAL implementat= ion. It is the - caller's responsibility to check for this return code after calling any = optional PAL - procedure. No parameter checking is performed on the 4 input parameters,= but there are - some common rules that the caller should follow when making a PAL call. = Any address - passed to PAL as buffers for return parameters must be 8-byte aligned. = Unaligned addresses - may cause undefined results. For those parameters defined as reserved o= r some fields - defined as reserved must be zero filled or the invalid argument return v= alue may be - returned or undefined result may occur during the execution of the proce= dure. - This function is only available on Intel Itanium-based platforms. - - @param Index The PAL procedure Index number. - @param Arg2 The 2nd parameter for PAL procedure calls. - @param Arg3 The 3rd parameter for PAL procedure calls. - @param Arg4 The 4th parameter for PAL procedure calls. - - @return Structure returned from the PAL Call procedure, including the st= atus and return value. - -**/ -PAL_CALL_RETURN -EFIAPI -PalCall ( - IN UINT64 Index, - IN UINT64 Arg2, - IN UINT64 Arg3, - IN UINT64 Arg4 - ); - -#endif - diff --git a/MdePkg/Include/Library/SalLib.h b/MdePkg/Include/Library/SalLi= b.h deleted file mode 100644 index 73d0952755..0000000000 --- a/MdePkg/Include/Library/SalLib.h +++ /dev/null @@ -1,53 +0,0 @@ -/** @file - Provides library services to make SAL Calls. - -Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.
-SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __SAL_LIB__ -#define __SAL_LIB__ - -#include - -/** - Makes a SAL procedure call. - - This is a wrapper function to make a SAL procedure call. - No parameter checking is performed on the 8 input parameters, - but there are some common rules that the caller should follow - when making a SAL call. Any address passed to SAL as buffers - for return parameters must be 8-byte aligned. Unaligned - addresses may cause undefined results. For those parameters - defined as reserved or some fields defined as reserved must be - zero filled or the invalid argument return value may be returned - or undefined result may occur during the execution of the procedure. - This function is only available on Intel Itanium-based platforms. - - @param Index The SAL procedure Index number - @param Arg2 The 2nd parameter for SAL procedure calls - @param Arg3 The 3rd parameter for SAL procedure calls - @param Arg4 The 4th parameter for SAL procedure calls - @param Arg5 The 5th parameter for SAL procedure calls - @param Arg6 The 6th parameter for SAL procedure calls - @param Arg7 The 7th parameter for SAL procedure calls - @param Arg8 The 8th parameter for SAL procedure calls - - @return SAL returned registers. - -**/ -SAL_RETURN_REGS -EFIAPI -SalCall ( - IN UINT64 Index, - IN UINT64 Arg2, - IN UINT64 Arg3, - IN UINT64 Arg4, - IN UINT64 Arg5, - IN UINT64 Arg6, - IN UINT64 Arg7, - IN UINT64 Arg8 - ); - -#endif diff --git a/MdePkg/Include/Protocol/ExtendedSalBootService.h b/MdePkg/Incl= ude/Protocol/ExtendedSalBootService.h deleted file mode 100644 index fd76532be6..0000000000 --- a/MdePkg/Include/Protocol/ExtendedSalBootService.h +++ /dev/null @@ -1,211 +0,0 @@ -/** @file - Definition of Extended SAL Boot Service Protocol - - The Extended SAL Boot Service Protocol provides a mechanisms for platfor= m specific - drivers to update the SAL System Table and register Extended SAL Procedu= res that are - callable in physical or virtual mode using the SAL calling convention. - - Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - @par Revision Reference: - This Protocol was introduced in PI Specification 1.2. - -**/ - -#ifndef _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL_H_ -#define _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL_H_ - -#include - -#define EXTENDED_SAL_BOOT_SERVICE_PROTOCOL_GUID \ - { 0xde0ee9a4, 0x3c7a, 0x44f2, {0xb7, 0x8b, 0xe3, 0xcc, 0xd6, 0x9c, 0x3a,= 0xf7 } } - -typedef struct _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL EXTENDED_SAL_BOOT_SERVI= CE_PROTOCOL; - -/** - Adds platform specific information to the to the header of the SAL Syste= m Table. - - @param This A pointer to the EXTENDED_SAL_BOOT_SERVICE= _PROTOCOL instance. - @param SalAVersion Version of recovery SAL PEIM(s) in BCD for= mat. Higher byte contains - the major revision and the lower byte cont= ains the minor revision. - @param SalBVersion Version of DXE SAL Driver in BCD format. H= igher byte contains - the major revision and the lower byte cont= ains the minor revision. - @param OemId A pointer to a Null-terminated ASCII strin= g that contains OEM unique string. - The string cannot be longer than 32 bytes = in total length - @param ProductId A pointer to a Null-terminated ASCII strin= g that uniquely identifies a family of - compatible products. The string cannot be = longer than 32 bytes in total length. - - @retval EFI_SUCCESS The SAL System Table header was updated su= ccessfully. - @retval EFI_INVALID_PARAMETER OemId is NULL. - @retval EFI_INVALID_PARAMETER ProductId is NULL. - @retval EFI_INVALID_PARAMETER The length of OemId is greater than 32 cha= racters. - @retval EFI_INVALID_PARAMETER The length of ProductId is greater than 32= characters. - -**/ -typedef -EFI_STATUS -(EFIAPI *EXTENDED_SAL_ADD_SST_INFO)( - IN EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *This, - IN UINT16 SalAVersion, - IN UINT16 SalBVersion, - IN CHAR8 *OemId, - IN CHAR8 *ProductId - ); - -/** - Adds an entry to the SAL System Table. - - This function adds the SAL System Table Entry specified by TableEntry an= d EntrySize - to the SAL System Table. - - @param This A pointer to the EXTENDED_SAL_BOOT_SERVICE_PROTOCOL= instance. - @param TableEntry Pointer to a buffer containing a SAL System Table e= ntry that is EntrySize bytes - in length. The first byte of the TableEntry describ= es the type of entry. - @param EntrySize The size, in bytes, of TableEntry. - - @retval EFI_SUCCESSThe SAL System Table was updated successfully. - @retval EFI_INVALID_PARAMETER TableEntry is NULL. - @retval EFI_INVALID_PARAMETER TableEntry specifies an invalid entry type. - @retval EFI_INVALID_PARAMETER EntrySize is not valid for this type of en= try. - -**/ -typedef -EFI_STATUS -(EFIAPI *EXTENDED_SAL_ADD_SST_ENTRY)( - IN EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *This, - IN UINT8 *TableEntry, - IN UINTN EntrySize - ); - -/** - Internal ESAL procedures. - - This is prototype of internal Extended SAL procedures, which is register= d by - EXTENDED_SAL_REGISTER_INTERNAL_PROC service. - - @param FunctionId The Function ID associated with this Extended= SAL Procedure. - @param Arg2 Second argument to the Extended SAL procedure. - @param Arg3 Third argument to the Extended SAL procedure. - @param Arg4 Fourth argument to the Extended SAL procedure. - @param Arg5 Fifth argument to the Extended SAL procedure. - @param Arg6 Sixth argument to the Extended SAL procedure. - @param Arg7 Seventh argument to the Extended SAL procedur= e. - @param Arg8 Eighth argument to the Extended SAL procedure. - @param VirtualMode TRUE if the Extended SAL Procedure is being i= nvoked in virtual mode. - FALSE if the Extended SAL Procedure is being = invoked in physical mode. - @param ModuleGlobal A pointer to the global context associated wi= th this Extended SAL Procedure. - - @return The result returned from the specified Extended SAL Procedure - -**/ -typedef -SAL_RETURN_REGS -(EFIAPI *SAL_INTERNAL_EXTENDED_SAL_PROC)( - IN UINT64 FunctionId, - IN UINT64 Arg2, - IN UINT64 Arg3, - IN UINT64 Arg4, - IN UINT64 Arg5, - IN UINT64 Arg6, - IN UINT64 Arg7, - IN UINT64 Arg8, - IN BOOLEAN VirtualMode, - IN VOID *ModuleGlobal OPTIONAL - ); - -/** - Registers an Extended SAL Procedure. - - The Extended SAL Procedure specified by InternalSalProc and named by Cla= ssGuidLo, - ClassGuidHi, and FunctionId is added to the set of available Extended SA= L Procedures. - - @param This A pointer to the EXTENDED_SAL_BOOT_SERVIC= E_PROTOCOL instance. - @param ClassGuidLo The lower 64-bits of the class GUID for = the Extended SAL Procedure being added. - Each class GUID contains one or more func= tions specified by a Function ID. - @param ClassGuidHi The upper 64-bits of the class GUID for = the Extended SAL Procedure being added. - Each class GUID contains one or more func= tions specified by a Function ID. - @param FunctionId The Function ID for the Extended SAL Proc= edure that is being added. This Function - ID is a member of the Extended SAL Proced= ure class specified by ClassGuidLo - and ClassGuidHi. - @param InternalSalProc A pointer to the Extended SAL Procedure b= eing added. - @param PhysicalModuleGlobal Pointer to a module global structure. Th= is is a physical mode pointer. - This pointer is passed to the Extended SA= L Procedure specified by ClassGuidLo, - ClassGuidHi, FunctionId, and InternalSalP= roc. If the system is in physical mode, - then this pointer is passed unmodified to= InternalSalProc. If the system is in - virtual mode, then the virtual address as= sociated with this pointer is passed to - InternalSalProc. - - @retval EFI_SUCCESS The Extended SAL Procedure was added. - @retval EFI_OUT_OF_RESOURCES There are not enough resources available = to add the Extended SAL Procedure. - -**/ -typedef -EFI_STATUS -(EFIAPI *EXTENDED_SAL_REGISTER_INTERNAL_PROC)( - IN EXTENDED_SAL_BOOT_SERVICE_PROTOCOL *This, - IN UINT64 ClassGuidLo, - IN UINT64 ClassGuidHi, - IN UINT64 FunctionId, - IN SAL_INTERNAL_EXTENDED_SAL_PROC InternalSalProc, - IN VOID *PhysicalModuleGlobal OPTIONAL - ); - -/** - Calls a previously registered Extended SAL Procedure. - - This function calls the Extended SAL Procedure specified by ClassGuidLo,= ClassGuidHi, - and FunctionId. The set of previously registered Extended SAL Procedure= s is searched for a - matching ClassGuidLo, ClassGuidHi, and FunctionId. If a match is not fo= und, then - EFI_SAL_NOT_IMPLEMENTED is returned. - - @param ClassGuidLo The lower 64-bits of the class GUID for the E= xtended SAL Procedure - that is being called. - @param ClassGuidHi The upper 64-bits of the class GUID for the E= xtended SAL Procedure - that is being called. - @param FunctionId Function ID for the Extended SAL Procedure be= ing called. - @param Arg2 Second argument to the Extended SAL procedure. - @param Arg3 Third argument to the Extended SAL procedure. - @param Arg4 Fourth argument to the Extended SAL procedure. - @param Arg5 Fifth argument to the Extended SAL procedure. - @param Arg6 Sixth argument to the Extended SAL procedure. - @param Arg7 Seventh argument to the Extended SAL procedur= e. - @param Arg8 Eighth argument to the Extended SAL procedure. - - @retval EFI_SAL_NOT_IMPLEMENTED The Extended SAL Procedure specif= ied by ClassGuidLo, - ClassGuidHi, and FunctionId has n= ot been registered. - @retval EFI_SAL_VIRTUAL_ADDRESS_ERROR This function was called in virtu= al mode before virtual mappings - for the specified Extended SAL Pr= ocedure are available. - @retval Other The result returned from the spec= ified Extended SAL Procedure - -**/ -typedef -SAL_RETURN_REGS -(EFIAPI *EXTENDED_SAL_PROC)( - IN UINT64 ClassGuidLo, - IN UINT64 ClassGuidHi, - IN UINT64 FunctionId, - IN UINT64 Arg2, - IN UINT64 Arg3, - IN UINT64 Arg4, - IN UINT64 Arg5, - IN UINT64 Arg6, - IN UINT64 Arg7, - IN UINT64 Arg8 - ); - -/// -/// The EXTENDED_SAL_BOOT_SERVICE_PROTOCOL provides a mechanisms for platf= orm specific -/// drivers to update the SAL System Table and register Extended SAL Proce= dures that are -/// callable in physical or virtual mode using the SAL calling convention. -/// -struct _EXTENDED_SAL_BOOT_SERVICE_PROTOCOL { - EXTENDED_SAL_ADD_SST_INFO AddSalSystemTableInfo; - EXTENDED_SAL_ADD_SST_ENTRY AddSalSystemTableEntry; - EXTENDED_SAL_REGISTER_INTERNAL_PROC RegisterExtendedSalProc; - EXTENDED_SAL_PROC ExtendedSalProc; -}; - -extern EFI_GUID gEfiExtendedSalBootServiceProtocolGuid; - -#endif diff --git a/MdePkg/Include/Protocol/ExtendedSalServiceClasses.h b/MdePkg/I= nclude/Protocol/ExtendedSalServiceClasses.h deleted file mode 100644 index 847a149b69..0000000000 --- a/MdePkg/Include/Protocol/ExtendedSalServiceClasses.h +++ /dev/null @@ -1,272 +0,0 @@ -/** @file - The standard set of Extended SAL service classes. - - Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - - @par Revision Reference: - This Protocol was introduced in PI Specification 1.2. - -**/ - -#ifndef _EXTENDED_SAL_SERVICE_CLASSES_H_ -#define _EXTENDED_SAL_SERVICE_CLASSES_H_ - -/// -/// Extended SAL Base I/O Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_LO 0x451531e15aea4= 2b5 -#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID_HI 0xa6657525d5b83= 1bc -#define EFI_EXTENDED_SAL_BASE_IO_SERVICES_PROTOCOL_GUID \ - { 0x5aea42b5, 0x31e1, 0x4515, {0xbc, 0x31, 0xb8, 0xd5, 0x25, 0x75, 0x65,= 0xa6 } } - -typedef enum { - IoReadFunctionId, - IoWriteFunctionId, - MemReadFunctionId, - MemWriteFunctionId -} EFI_EXTENDED_SAL_BASE_IO_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL Stall Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_LO 0x4d8cac2753a58d06 -#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID_HI 0x704165808af0e9b5 -#define EFI_EXTENDED_SAL_STALL_SERVICES_PROTOCOL_GUID \ - { 0x53a58d06, 0xac27, 0x4d8c, {0xb5, 0xe9, 0xf0, 0x8a, 0x80, 0x65, 0x41,= 0x70 } } - -typedef enum { - StallFunctionId -} EFI_EXTENDED_SAL_STALL_FUNC_ID; -///@} - -/// -/// Extended SAL Real Time Clock Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID_LO 0x4d02efdb7e97a470 -#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID_HI 0x96a27bd29061ce8f -#define EFI_EXTENDED_SAL_RTC_SERVICES_PROTOCOL_GUID \ - { 0x7e97a470, 0xefdb, 0x4d02, {0x8f, 0xce, 0x61, 0x90, 0xd2, 0x7b, 0xa2,= 0x96 } } - -typedef enum { - GetTimeFunctionId, - SetTimeFunctionId, - GetWakeupTimeFunctionId, - SetWakeupTimeFunctionId, - GetRtcFreqFunctionId, - InitializeThresholdFunctionId, - BumpThresholdCountFunctionId, - GetThresholdCountFunctionId -} EFI_EXTENDED_SAL_RTC_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL Variable Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID_LO 0x4370c6414ecb= 6c53 -#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID_HI 0x78836e490e3b= b28c -#define EFI_EXTENDED_SAL_VARIABLE_SERVICES_PROTOCOL_GUID \ - { 0x4ecb6c53, 0xc641, 0x4370, {0x8c, 0xb2, 0x3b, 0x0e, 0x49, 0x6e, 0x83,= 0x78 } } - -typedef enum { - EsalGetVariableFunctionId, - EsalGetNextVariableNameFunctionId, - EsalSetVariableFunctionId, - EsalQueryVariableInfoFunctionId -} EFI_EXTENDED_SAL_VARIABLE_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL Monotonic Counter Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID_LO 0x408b75e8899afd18 -#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID_HI 0x54f4cd7e2e6e1aa4 -#define EFI_EXTENDED_SAL_MTC_SERVICES_PROTOCOL_GUID \ - { 0x899afd18, 0x75e8, 0x408b, {0xa4, 0x1a, 0x6e, 0x2e, 0x7e, 0xcd, 0xf4,= 0x54 } } - -typedef enum { - GetNextHighMonotonicCountFunctionId -} EFI_EXTENDED_SAL_MTC_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL Reset Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID_LO 0x46f58ce17d0199= 90 -#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID_HI 0xa06a6798513c76= a7 -#define EFI_EXTENDED_SAL_RESET_SERVICES_PROTOCOL_GUID \ - { 0x7d019990, 0x8ce1, 0x46f5, {0xa7, 0x76, 0x3c, 0x51, 0x98, 0x67, 0x6a,= 0xa0 } } - -typedef enum { - ResetSystemFunctionId -} EFI_EXTENDED_SAL_RESET_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL Status Code Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID_LO 0x420f55e9d= bd91d -#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID_HI 0x4fb437849= f5e3996 -#define EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_PROTOCOL_GUID \ - { 0xdbd91d, 0x55e9, 0x420f, {0x96, 0x39, 0x5e, 0x9f, 0x84, 0x37, 0xb4, 0= x4f } } - -typedef enum { - ReportStatusCodeServiceFunctionId -} EFI_EXTENDED_SAL_STATUS_CODE_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL Firmware Volume Block Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_PROTOCOL_GUID_LO 0x4f1dbcbba227= 1df1 -#define EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_PROTOCOL_GUID_HI 0x1a072f17bc06= a998 -#define EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_PROTOCOL_GUID \ - { 0xa2271df1, 0xbcbb, 0x4f1d, {0x98, 0xa9, 0x06, 0xbc, 0x17, 0x2f, 0x07,= 0x1a } } - -typedef enum { - ReadFunctionId, - WriteFunctionId, - EraseBlockFunctionId, - GetVolumeAttributesFunctionId, - SetVolumeAttributesFunctionId, - GetPhysicalAddressFunctionId, - GetBlockSizeFunctionId, -} EFI_EXTENDED_SAL_FV_BLOCK_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL MP Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_LO 0x4dc0cf18697d81a2 -#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID_HI 0x3f8a613b11060d9e -#define EFI_EXTENDED_SAL_MP_SERVICES_PROTOCOL_GUID \ - { 0x697d81a2, 0xcf18, 0x4dc0, {0x9e, 0x0d, 0x06, 0x11, 0x3b, 0x61, 0x8a,= 0x3f } } - -typedef enum { - AddCpuDataFunctionId, - RemoveCpuDataFunctionId, - ModifyCpuDataFunctionId, - GetCpuDataByIDFunctionId, - GetCpuDataByIndexFunctionId, - SendIpiFunctionId, - CurrentProcInfoFunctionId, - NumProcessorsFunctionId, - SetMinStateFunctionId, - GetMinStateFunctionId -} EFI_EXTENDED_SAL_MP_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL PAL Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_LO 0x438d0fc2e1cd9d21 -#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID_HI 0x571e966de6040397 -#define EFI_EXTENDED_SAL_PAL_SERVICES_PROTOCOL_GUID \ - { 0xe1cd9d21, 0x0fc2, 0x438d, {0x97, 0x03, 0x04, 0xe6, 0x6d, 0x96, 0x1e,= 0x57 } } - -typedef enum { - PalProcFunctionId, - SetNewPalEntryFunctionId, - GetNewPalEntryFunctionId, - EsalUpdatePalFunctionId -} EFI_EXTENDED_SAL_PAL_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL Base Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_LO 0x41c30fe0d9e9fa06 -#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID_HI 0xf894335a4283fb96 -#define EFI_EXTENDED_SAL_BASE_SERVICES_PROTOCOL_GUID \ - { 0xd9e9fa06, 0x0fe0, 0x41c3, {0x96, 0xfb, 0x83, 0x42, 0x5a, 0x33, 0x94,= 0xf8 } } - -typedef enum { - SalSetVectorsFunctionId, - SalMcRendezFunctionId, - SalMcSetParamsFunctionId, - EsalGetVectorsFunctionId, - EsalMcGetParamsFunctionId, - EsalMcGetMcParamsFunctionId, - EsalGetMcCheckinFlagsFunctionId, - EsalGetPlatformBaseFreqFunctionId, - EsalPhysicalIdInfoFunctionId, - EsalRegisterPhysicalAddrFunctionId -} EFI_EXTENDED_SAL_BASE_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL MCA Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_LO 0x42b16cc72a591128 -#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID_HI 0xbb2d683b9358f08a -#define EFI_EXTENDED_SAL_MCA_SERVICES_PROTOCOL_GUID \ - { 0x2a591128, 0x6cc7, 0x42b1, {0x8a, 0xf0, 0x58, 0x93, 0x3b, 0x68, 0x2d,= 0xbb } } - -typedef enum { - McaGetStateInfoFunctionId, - McaRegisterCpuFunctionId -} EFI_EXTENDED_SAL_MCA_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL PCI Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_LO 0x4905ad66a46b1a31 -#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID_HI 0x6330dc59462bf692 -#define EFI_EXTENDED_SAL_PCI_SERVICES_PROTOCOL_GUID \ - { 0xa46b1a31, 0xad66, 0x4905, {0x92, 0xf6, 0x2b, 0x46, 0x59, 0xdc, 0x30,= 0x63 } } - -typedef enum { - SalPciConfigReadFunctionId, - SalPciConfigWriteFunctionId -} EFI_EXTENDED_SAL_PCI_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL Cache Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_LO 0x4ba52743edc9494 -#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID_HI 0x88f11352ef0a1888 -#define EFI_EXTENDED_SAL_CACHE_SERVICES_PROTOCOL_GUID \ - { 0xedc9494, 0x2743, 0x4ba5, { 0x88, 0x18, 0x0a, 0xef, 0x52, 0x13, 0xf1,= 0x88 } } - -typedef enum { - SalCacheInitFunctionId, - SalCacheFlushFunctionId -} EFI_EXTENDED_SAL_CACHE_SERVICES_FUNC_ID; -///@} - -/// -/// Extended SAL MCA Log Services Class -/// -///@{ -#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_LO 0x4c0338a3cb3fd= 86e -#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID_HI 0x7aaba2a3cf905= c9a -#define EFI_EXTENDED_SAL_MCA_LOG_SERVICES_PROTOCOL_GUID \ - { 0xcb3fd86e, 0x38a3, 0x4c03, {0x9a, 0x5c, 0x90, 0xcf, 0xa3, 0xa2, 0xab,= 0x7a } } - -typedef enum { - SalGetStateInfoFunctionId, - SalGetStateInfoSizeFunctionId, - SalClearStateInfoFunctionId, - EsalGetStateBufferFunctionId, - EsalSaveStateBufferFunctionId -} EFI_EXTENDED_SAL_MCA_LOG_SERVICES_FUNC_ID; -///@} - -#endif diff --git a/MdePkg/Include/Protocol/McaInitPmi.h b/MdePkg/Include/Protocol= /McaInitPmi.h deleted file mode 100644 index 617154d19b..0000000000 --- a/MdePkg/Include/Protocol/McaInitPmi.h +++ /dev/null @@ -1,201 +0,0 @@ -/** @file - MCA/PMI/INIT Protocol as defined in PI Specification VOLUME 4. - - This protocol provides services to handle Machine Checks (MCA), - Initialization (INIT) events, and Platform Management Interrupt (PMI) ev= ents - on an Intel Itanium Processor Family based system. - - Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __MCA_INIT_PMI_PROTOCOL_H__ -#define __MCA_INIT_PMI_PROTOCOL_H__ - -/// -/// Global ID for the MCA/PMI/INIT Protocol. -/// -#define EFI_SAL_MCA_INIT_PMI_PROTOCOL_GUID \ - { 0xb60dc6e8, 0x3b6f, 0x11d5, {0xaf, 0x9, 0x0, 0xa0, 0xc9, 0x44, 0xa0, 0= x5b} } - - -/// -/// Declare forward reference for the Timer Architectural Protocol -/// -typedef struct _EFI_SAL_MCA_INIT_PMI_PROTOCOL EFI_SAL_MCA_INIT_PMI_PROTOC= OL; - -#pragma pack(1) -/// -/// MCA Records Structure -/// -typedef struct { - UINT64 First : 1; - UINT64 Last : 1; - UINT64 EntryCount : 16; - UINT64 DispatchedCount : 16; - UINT64 Reserved : 30; -} SAL_MCA_COUNT_STRUCTURE; - -#pragma pack() - -/** - Prototype of MCA handler. - - @param ModuleGlobal The context of MCA Handler - @param ProcessorStateParameters The processor state parameters (PSP) - @param MinstateBase Base address of the min-state - @param RendezvouseStateInformation Rendezvous state information to be p= assed to - the OS on OS MCA entry - @param CpuIndex Index of the logical processor - @param McaCountStructure Pointer to the MCA records structure - @param CorrectedMachineCheck This flag is set to TRUE is the MCA = has been - corrected by the handler or by a pre= vious handler - - @retval EFI_SUCCESS Handler successfully returned - -**/ -typedef -EFI_STATUS -(EFIAPI *EFI_SAL_MCA_HANDLER)( - IN VOID *ModuleGlobal, - IN UINT64 ProcessorStateParameters, - IN EFI_PHYSICAL_ADDRESS MinstateBase, - IN UINT64 RendezvouseStateInformation, - IN UINT64 CpuIndex, - IN SAL_MCA_COUNT_STRUCTURE *McaCountStructure, - OUT BOOLEAN *CorrectedMachineCheck - ); - -/** - Prototype of INIT handler. - - @param ModuleGlobal The context of INIT Handler - @param ProcessorStateParameters The processor state parameters (PSP) - @param MinstateBase Base address of the min-state - @param McaInProgress This flag indicates if an MCA is in = progress - @param CpuIndex Index of the logical processor - @param McaCountStructure Pointer to the MCA records structure - @param DumpSwitchPressed This flag indicates the crash dump s= witch has been pressed - - @retval EFI_SUCCESS Handler successfully returned - -**/ -typedef -EFI_STATUS -(EFIAPI *EFI_SAL_INIT_HANDLER)( - IN VOID *ModuleGlobal, - IN UINT64 ProcessorStateParameters, - IN EFI_PHYSICAL_ADDRESS MinstateBase, - IN BOOLEAN McaInProgress, - IN UINT64 CpuIndex, - IN SAL_MCA_COUNT_STRUCTURE *McaCountStructure, - OUT BOOLEAN *DumpSwitchPressed - ); - -/** - Prototype of PMI handler - - @param ModuleGlobal The context of PMI Handler - @param CpuIndex Index of the logical processor - @param PmiVector The PMI vector number as received fr= om the PALE_PMI exit state (GR24) - - @retval EFI_SUCCESS Handler successfully returned - -**/ -typedef -EFI_STATUS -(EFIAPI *EFI_SAL_PMI_HANDLER)( - IN VOID *ModuleGlobal, - IN UINT64 CpuIndex, - IN UINT64 PmiVector - ); - -/** - Register a MCA handler with the MCA dispatcher. - - @param This The EFI_SAL_MCA_INIT_PMI_PROTOCOL in= stance - @param McaHandler The MCA handler to register - @param ModuleGlobal The context of MCA Handler - @param MakeFirst This flag specifies the handler shou= ld be made first in the list - @param MakeLast This flag specifies the handler shou= ld be made last in the list - - @retval EFI_SUCCESS MCA Handle was registered - @retval EFI_OUT_OF_RESOURCES No more resources to register an MCA= handler - @retval EFI_INVALID_PARAMETER Invalid parameters were passed - -**/ -typedef -EFI_STATUS -(EFIAPI *EFI_SAL_REGISTER_MCA_HANDLER)( - IN EFI_SAL_MCA_INIT_PMI_PROTOCOL *This, - IN EFI_SAL_MCA_HANDLER McaHandler, - IN VOID *ModuleGlobal, - IN BOOLEAN MakeFirst, - IN BOOLEAN MakeLast - ); - -/** - Register an INIT handler with the INIT dispatcher. - - @param This The EFI_SAL_MCA_INIT_PMI_PROTOCOL in= stance - @param InitHandler The INIT handler to register - @param ModuleGlobal The context of INIT Handler - @param MakeFirst This flag specifies the handler shou= ld be made first in the list - @param MakeLast This flag specifies the handler shou= ld be made last in the list - - @retval EFI_SUCCESS INIT Handle was registered - @retval EFI_OUT_OF_RESOURCES No more resources to register an INI= T handler - @retval EFI_INVALID_PARAMETER Invalid parameters were passed - -**/ -typedef -EFI_STATUS -(EFIAPI *EFI_SAL_REGISTER_INIT_HANDLER)( - IN EFI_SAL_MCA_INIT_PMI_PROTOCOL *This, - IN EFI_SAL_INIT_HANDLER InitHandler, - IN VOID *ModuleGlobal, - IN BOOLEAN MakeFirst, - IN BOOLEAN MakeLast - ); - -/** - Register a PMI handler with the PMI dispatcher. - - @param This The EFI_SAL_MCA_INIT_PMI_PROTOCOL in= stance - @param PmiHandler The PMI handler to register - @param ModuleGlobal The context of PMI Handler - @param MakeFirst This flag specifies the handler shou= ld be made first in the list - @param MakeLast This flag specifies the handler shou= ld be made last in the list - - @retval EFI_SUCCESS PMI Handle was registered - @retval EFI_OUT_OF_RESOURCES No more resources to register an PMI= handler - @retval EFI_INVALID_PARAMETER Invalid parameters were passed - -**/ -typedef -EFI_STATUS -(EFIAPI *EFI_SAL_REGISTER_PMI_HANDLER)( - IN EFI_SAL_MCA_INIT_PMI_PROTOCOL *This, - IN EFI_SAL_PMI_HANDLER PmiHandler, - IN VOID *ModuleGlobal, - IN BOOLEAN MakeFirst, - IN BOOLEAN MakeLast - ); - -/// -/// This protocol is used to register MCA, INIT and PMI handlers with thei= r respective dispatcher -/// -struct _EFI_SAL_MCA_INIT_PMI_PROTOCOL { - EFI_SAL_REGISTER_MCA_HANDLER RegisterMcaHandler; - EFI_SAL_REGISTER_INIT_HANDLER RegisterInitHandler; - EFI_SAL_REGISTER_PMI_HANDLER RegisterPmiHandler; - BOOLEAN McaInProgress; ///< Whether MCA hand= ler is in progress - BOOLEAN InitInProgress; ///< Whether Init han= dler is in progress - BOOLEAN PmiInProgress; ///< Whether Pmi hand= ler is in progress -}; - -extern EFI_GUID gEfiSalMcaInitPmiProtocolGuid; - -#endif - diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 382319dfd7..e2ea8fff66 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -324,9 +324,6 @@ ## Include/Guid/Mps.h gEfiMpsTableGuid =3D { 0xEB9D2D2F, 0x2D88, 0x11D3, { 0x9A,= 0x16, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} =20 - ## Include/Guid/SalSystemTable.h - gEfiSalSystemTableGuid =3D { 0xEB9D2D32, 0x2D88, 0x11D3, { 0x9A,= 0x16, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D }} - ## Include/Protocol/AuthenticationInfo.h gEfiAuthenticationChapLocalGuid =3D { 0xC280C73E, 0x15CA, 0x11DA, { 0xB0= , 0xCA, 0x00, 0x10, 0x83, 0xFF, 0xCA, 0x4D }} =20 @@ -1122,29 +1119,6 @@ ## Include/Protocol/LegacyRegion2.h gEfiLegacyRegion2ProtocolGuid =3D {0x70101eaf, 0x85, 0x440c, {0xb3, 0x56= , 0x8e, 0xe3, 0x6f, 0xef, 0x24, 0xf0 } } =20 - ## Include/Protocol/McaInitPmi.h - gEfiSalMcaInitPmiProtocolGuid =3D { 0xb60dc6e8, 0x3b6f, 0x11d5, {0xaf, 0= x9, 0x0, 0xa0, 0xc9, 0x44, 0xa0, 0x5b } } - - ## Include/Protocol/ExtendedSalBootService.h - gEfiExtendedSalBootServiceProtocolGuid =3D { 0xde0ee9a4, 0x3c7a, 0x44f2= , {0xb7, 0x8b, 0xe3, 0xcc, 0xd6, 0x9c, 0x3a, 0xf7 } } - - ## Include/Protocol/ExtendedSalServiceClasses.h - gEfiExtendedSalBaseIoServicesProtocolGuid =3D { 0x5aea42b5, 0x31e1, 0x45= 15, {0xbc, 0x31, 0xb8, 0xd5, 0x25, 0x75, 0x65, 0xa6 } } - gEfiExtendedSalStallServicesProtocolGuid =3D { 0x53a58d06, 0xac27, 0x4d8= c, {0xb5, 0xe9, 0xf0, 0x8a, 0x80, 0x65, 0x41, 0x70 } } - gEfiExtendedSalRtcServicesProtocolGuid =3D { 0x7e97a470, 0xefdb, 0x4d02,= {0x8f, 0xce, 0x61, 0x90, 0xd2, 0x7b, 0xa2, 0x96 } } - gEfiExtendedSalVariableServicesProtocolGuid =3D { 0x4ecb6c53, 0xc641, 0x= 4370, {0x8c, 0xb2, 0x3b, 0x0e, 0x49, 0x6e, 0x83, 0x78 } } - gEfiExtendedSalMtcServicesProtocolGuid =3D { 0x899afd18, 0x75e8, 0x408b,= {0xa4, 0x1a, 0x6e, 0x2e, 0x7e, 0xcd, 0xf4, 0x54 } } - gEfiExtendedSalResetServicesProtocolGuid =3D { 0x7d019990, 0x8ce1, 0x46f= 5, {0xa7, 0x76, 0x3c, 0x51, 0x98, 0x67, 0x6a, 0xa0 } } - gEfiExtendedSalStatusCodeServicesProtocolGuid =3D { 0xdbd91d, 0x55e9, 0x= 420f, {0x96, 0x39, 0x5e, 0x9f, 0x84, 0x37, 0xb4, 0x4f } } - gEfiExtendedSalFvBlockServicesProtocolGuid =3D { 0xa2271df1, 0xbcbb, 0x4= f1d, {0x98, 0xa9, 0x06, 0xbc, 0x17, 0x2f, 0x07, 0x1a } } - gEfiExtendedSalMpServicesProtocolGuid =3D { 0x697d81a2, 0xcf18, 0x4dc0, = {0x9e, 0x0d, 0x06, 0x11, 0x3b, 0x61, 0x8a, 0x3f } } - gEfiExtendedSalPalServicesProtocolGuid =3D { 0xe1cd9d21, 0x0fc2, 0x438d,= {0x97, 0x03, 0x04, 0xe6, 0x6d, 0x96, 0x1e, 0x57 } } - gEfiExtendedSalBaseServicesProtocolGuid =3D { 0xd9e9fa06, 0x0fe0, 0x41c3= , {0x96, 0xfb, 0x83, 0x42, 0x5a, 0x33, 0x94, 0xf8 } } - gEfiExtendedSalMcaServicesProtocolGuid =3D { 0x2a591128, 0x6cc7, 0x42b1,= {0x8a, 0xf0, 0x58, 0x93, 0x3b, 0x68, 0x2d, 0xbb } } - gEfiExtendedSalPciServicesProtocolGuid =3D { 0xa46b1a31, 0xad66, 0x4905,= {0x92, 0xf6, 0x2b, 0x46, 0x59, 0xdc, 0x30, 0x63 } } - gEfiExtendedSalCacheServicesProtocolGuid =3D { 0xedc9494, 0x2743, 0x4ba5= , { 0x88, 0x18, 0x0a, 0xef, 0x52, 0x13, 0xf1, 0x88 } } - gEfiExtendedSalMcaLogServicesProtocolGuid =3D { 0xcb3fd86e, 0x38a3, 0x4c= 03, {0x9a, 0x5c, 0x90, 0xcf, 0xa3, 0xa2, 0xab, 0x7a } } - # # Protocols defined in PI 1.2.1 # --=20 2.18.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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