From nobody Mon Feb 9 17:57:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1532416898352361.83397387663456; Tue, 24 Jul 2018 00:21:38 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 212E5210C125E; Tue, 24 Jul 2018 00:21:38 -0700 (PDT) Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 56466210C1255 for ; Tue, 24 Jul 2018 00:21:37 -0700 (PDT) Received: by mail-pg1-x543.google.com with SMTP id v13-v6so2227579pgr.10 for ; Tue, 24 Jul 2018 00:21:37 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id t14-v6sm11449788pgu.0.2018.07.24.00.21.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Jul 2018 00:21:36 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::543; helo=mail-pg1-x543.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kaOx92Szxqxkvg65TfUr2tb0OdWIUAH1aKDaha1G+Aw=; b=jxMptXrq1/ABnytMano2Wd+aByWnDxdZx3G6ZS+oguHelT3Zu34imnZooU8akgAlYb qnmpTRCtAFFtULVMRqtMUj2OBd3vFMlMgM47gwIjAoMzf6C5KxqhM0IgAZq5IVX9ToBV rnqib1ysrPE3DGycY+kY4FHo/nBJySgKEcMho= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kaOx92Szxqxkvg65TfUr2tb0OdWIUAH1aKDaha1G+Aw=; b=qUXLU2vh0Nv+IMHoS1RRsn04JHVk5anwt1ptxJh8z2jfo0FoFcbh3LJfmHNgiQ8GcE cTZb/LuUokODvCICMSOzafZgeDuTwCf2XOvXf92Y2XGdQ45SHZQh2F12Cut4nWFgVJbC 0ygNCcRoO7/jLnHrSnhV+W83IyUVyucG59mOAwt5tGIUCUOMYfWLBY1juRSlRk2QFRKH W92vjHB61R5UQrAu0zPoRJbQuBxwQYMMEWTQHKbYXTCW7/AtEbAvRaSjwmDcoksjXxmU NuRaptqwLUIbcqLjq0KlxUnO9MpLDUz7lSjwGq6XXn0VWuRyrhp1IB6TU1Hw7hwZF3cR dAJQ== X-Gm-Message-State: AOUpUlE9sxUVmc30J0Nc0w3SLDefBZ5FJc88TTxUsfbchfa+SlGhbyTI pIhTbwQ8b4heVE4BXGGCYJZsDg== X-Google-Smtp-Source: AAOMgpftGVDD8GfOvFL7R7x03n/UrENNox178TAy0vJ+0O7w0+Y9r2JwWIvwg64av5C8x6l1sLoyQg== X-Received: by 2002:a62:990f:: with SMTP id d15-v6mr16488530pfe.162.1532416897009; Tue, 24 Jul 2018 00:21:37 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 15:09:12 +0800 Message-Id: <20180724070922.63362-29-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724070922.63362-1-ming.huang@linaro.org> References: <20180724070922.63362-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v1 28/38] Hisilicon/D0x: Unify FlashFvbDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, shaochangliang , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: shaochangliang Add PcdSFCMEM0BaseAddress to D06 and switch three 32-bit macro PcdFlashNvStorage to 64-bit for D05/D03. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: shaochangliang Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D03/D03.fdf | 6 +++--- Platform/Hisilicon/D05/D05.fdf | 6 +++--- Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 22 ++++++++++-----= ----- Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 7 ++++--- 4 files changed, 21 insertions(+), 20 deletions(-) diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf index cf11aeccc8..5c68846a06 100644 --- a/Platform/Hisilicon/D03/D03.fdf +++ b/Platform/Hisilicon/D03/D03.fdf @@ -69,7 +69,7 @@ FILE =3D Platform/Hisilicon/D03/bl1.bin FILE =3D Platform/Hisilicon/D03/fip.bin =20 0x002D0000|0x0000E000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize DATA =3D { ## This is the EFI_FIRMWARE_VOLUME_HEADER 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -97,7 +97,7 @@ DATA =3D { } =20 0x002DE000|0x00002000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize #NV_FTW_WORKING DATA =3D { # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D @@ -110,7 +110,7 @@ DATA =3D { } =20 0x002E0000|0x00010000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =20 0x002F0000|0x00010000 FILE =3D Platform/Hisilicon/D03/CustomData.Fv diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 701804360e..989e05dfcd 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -69,7 +69,7 @@ FILE =3D Platform/Hisilicon/D05/bl1.bin FILE =3D Platform/Hisilicon/D05/fip.bin =20 0x002D0000|0x0000E000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize DATA =3D { ## This is the EFI_FIRMWARE_VOLUME_HEADER 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -97,7 +97,7 @@ DATA =3D { } =20 0x002DE000|0x00002000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize #NV_FTW_WORKING DATA =3D { # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D @@ -110,7 +110,7 @@ DATA =3D { } =20 0x002E0000|0x00010000 -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =20 0x002F0000|0x00010000 FILE =3D Platform/Hisilicon/D03/CustomData.Fv diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Silicon/= Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c index 7c6b64c33e..e18cc9e06e 100644 --- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c +++ b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c @@ -28,8 +28,8 @@ FLASH_DESCRIPTION mFlashDevices[FLASH_DEVICE_COUNT] =3D { { // UEFI Variable Services non-volatile storage - 0xa4000000, - FixedPcdGet32(PcdFlashNvStorageVariableBase), + FixedPcdGet64 (PcdSFCMEM0BaseAddress), + FixedPcdGet64 (PcdFlashNvStorageVariableBase64), 0x20000, SIZE_64KB, {0xCC2CBF29, 0x1498, 0x4CDD, {0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, = 0x09, 0x09}} @@ -145,8 +145,8 @@ InitializeFvAndVariableStoreHeaders ( Headers =3D AllocateZeroPool(HeadersLength); =20 // FirmwareVolumeHeader->FvLength is declared to have the Variable are= a AND the FTW working area AND the FTW Spare contiguous. - ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvSt= orageVariableSize) =3D=3D PcdGet32(PcdFlashNvStorageFtwWorkingBase)); - ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNv= StorageFtwWorkingSize) =3D=3D PcdGet32(PcdFlashNvStorageFtwSpareBase)); + ASSERT(PcdGet64(PcdFlashNvStorageVariableBase64) + PcdGet32(PcdFlashNv= StorageVariableSize) =3D=3D PcdGet64(PcdFlashNvStorageFtwWorkingBase64)); + ASSERT(PcdGet64(PcdFlashNvStorageFtwWorkingBase64) + PcdGet32(PcdFlash= NvStorageFtwWorkingSize) =3D=3D PcdGet64(PcdFlashNvStorageFtwSpareBase64)); =20 // Check if the size of the area is at least one block size ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && ((UINT32)PcdGe= t32(PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0)); @@ -154,9 +154,9 @@ InitializeFvAndVariableStoreHeaders ( ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && ((UINT32)PcdGe= t32(PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0)); =20 // Ensure the Variable area Base Addresses are aligned on a block size= boundaries - ASSERT((UINT32)PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Med= ia.BlockSize =3D=3D 0); - ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->M= edia.BlockSize =3D=3D 0); - ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Med= ia.BlockSize =3D=3D 0); + ASSERT((UINT32)PcdGet64(PcdFlashNvStorageVariableBase64) % Instance->M= edia.BlockSize =3D=3D 0); + ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwWorkingBase64) % Instance-= >Media.BlockSize =3D=3D 0); + ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwSpareBase64) % Instance->M= edia.BlockSize =3D=3D 0); =20 // // EFI_FIRMWARE_VOLUME_HEADER @@ -855,10 +855,10 @@ FvbInitialize ( UINT32 FvbNumLba; =20 Instance->Initialized =3D TRUE; - mFlashNvStorageVariableBase =3D FixedPcdGet32 (PcdFlashNvStorageVariab= leBase); + mFlashNvStorageVariableBase =3D FixedPcdGet64 (PcdFlashNvStorageVariab= leBase64); =20 // Set the index of the first LBA for the FVB - Instance->StartLba =3D (PcdGet32 (PcdFlashNvStorageVariableBase) - Ins= tance->RegionBaseAddress) / Instance->Media.BlockSize; + Instance->StartLba =3D (PcdGet64 (PcdFlashNvStorageVariableBase64) - I= nstance->RegionBaseAddress) / Instance->Media.BlockSize; =20 // Determine if there is a valid header at the beginning of the Flash Status =3D ValidateFvHeader (Instance); @@ -1208,8 +1208,8 @@ FlashFvbInitialize ( { // Check if this Flash device contain the variable storage region ContainVariableStorage =3D - (FlashDevices[Index].RegionBaseAddress <=3D (UINT32)PcdGet32 (= PcdFlashNvStorageVariableBase)) && - ((UINT32)(PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 = (PcdFlashNvStorageVariableSize)) <=3D FlashDevices[Index].RegionBaseAddress= + FlashDevices[Index].Size); + (FlashDevices[Index].RegionBaseAddress <=3D PcdGet64 (PcdFlas= hNvStorageVariableBase64)) && + ((PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdF= lashNvStorageVariableSize)) <=3D FlashDevices[Index].RegionBaseAddress + Fl= ashDevices[Index].Size); =20 Status =3D FlashCreateInstance ( FlashDevices[Index].DeviceBaseAddress, diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf b/Silico= n/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf index 09ec7ce08b..f8be4741ef 100644 --- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf +++ b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf @@ -54,14 +54,15 @@ gHisiSpiFlashProtocolGuid =20 [Pcd.common] - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =20 gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress =20 [Depex] gHisiSpiFlashProtocolGuid --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel