From nobody Mon Feb 9 19:52:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1532413972656489.1946254599977; Mon, 23 Jul 2018 23:32:52 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id E54DB210C1235; Mon, 23 Jul 2018 23:32:49 -0700 (PDT) Received: from mail-pg1-x541.google.com (mail-pg1-x541.google.com [IPv6:2607:f8b0:4864:20::541]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DDF3A210C1231 for ; Mon, 23 Jul 2018 23:32:48 -0700 (PDT) Received: by mail-pg1-x541.google.com with SMTP id s7-v6so2142410pgv.3 for ; Mon, 23 Jul 2018 23:32:48 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id e2-v6sm12086575pgo.92.2018.07.23.23.32.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 23:32:47 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::541; helo=mail-pg1-x541.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RdSQ6jFwLbLUW7Y0utDwChKzUVWFUVOazC9FNcqya9U=; b=CqttHS4dYolaNkqR+XVbsvqNdWuKR8bye0nU46/GRkBkBroqQiJ7DUrPBV0DYXGIUv lvkhg6l6u6sihRY+o1QV+lAKU+vULcdpRKb5N7Hx5t/wG7KzQ+qIf80Lp9dK/sGLwuP/ ZNk159MsTd5uqJR9WwIBdOhasurZ9hviwPelc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RdSQ6jFwLbLUW7Y0utDwChKzUVWFUVOazC9FNcqya9U=; b=YJ+jxGYVunIRd48f9Z8D9xoACgW58P/o8Fw966jSVlPMweaLnez0lZ0y2RAgPhPKAr XXXUHxORlmUCxxdo3BwFizTLtNc5mgQ+12de6lfH1W6gPAAnodWmFVKU2tOWZvch7IqC kf28c39cCEhSQy8cfxDTTxMtr2setJWVRq5wMbvE3AXWLbgKBi9+pkZ1WQRTC9/NsPDE Co5JvtsiGw4+Jvs5pmqwBZ+P9u2tqm1I86DxBEAOFHn8o+W3EmmXgYFutr2zdi2hI3QN Ck+2uN274gKrYruoQsLTti8P19q+CELw3SLntz/6Rq/4epXYjBjKn4+92X+uu2p6e8sH vsyA== X-Gm-Message-State: AOUpUlHTUxLoo3ZGwjHmbwOU/6x5gi1mQYMhYe1855JnbQTMVcmf/6gs to3/mK7aARaWlZjiI1jpXw0f+Q== X-Google-Smtp-Source: AAOMgpcbiV72dpZbjRT2iUcpGGeLRU0A43sexZ9KM0e48dI46/t6De/unQEyIbklif4V7nGaTCCmug== X-Received: by 2002:a63:686:: with SMTP id 128-v6mr14928015pgg.338.1532413968486; Mon, 23 Jul 2018 23:32:48 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 14:32:14 +0800 Message-Id: <20180724063220.61679-7-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724063220.61679-1-ming.huang@linaro.org> References: <20180724063220.61679-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 06/12] Hisilicon/Pci: move EnlargeAtuConfig0() to PciPlatformLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Michael D Kinney , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" we move all platform specific code to platform specific module, not in PciHostBridge driver. This is to prepare for switching to generic PciHostBridge driver, so This patch is to move EnlargeAtuConfig0() into PcieInitDxe, in PlatformNotify() of EFI_PCI_PLATFORM_PROTOCOL and implement api PhaseNotifyPlatform for PciPlatform driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Ming Huang Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c = | 1 - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h = | 8 - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c = | 78 -------- Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib= .c | 199 ++++++++++++++++++++ 4 files changed, 199 insertions(+), 87 deletions(-) diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/S= ilicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c index 9fa3f84098..e3d3988a64 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c @@ -839,7 +839,6 @@ NotifyPhase( =20 case EfiPciHostBridgeEndEnumeration: PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); - EnlargeAtuConfig0 (This); break; =20 case EfiPciHostBridgeBeginBusAllocation: diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/S= ilicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h index c04361fcee..435385491a 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h @@ -401,10 +401,6 @@ PreprocessController ( #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL =20 -#define INVALID_CAPABILITY_00 0x00 -#define INVALID_CAPABILITY_FF 0xFF -#define PCI_CAPABILITY_POINTER_MASK 0xFC - // // Driver Instance Data Prototypes // @@ -521,8 +517,4 @@ RootBridgeConstructor ( IN UINT32 Seg ); =20 -VOID -EnlargeAtuConfig0 ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This - ); #endif diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b= /Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c index 273a322ee4..3c265ea433 100644 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c @@ -2218,81 +2218,3 @@ RootBridgeIoConfiguration ( return EFI_SUCCESS; } =20 -BOOLEAN -PcieCheckAriFwdEn ( - UINTN PciBaseAddr - ) -{ - UINT8 PciPrimaryStatus; - UINT8 CapabilityOffset; - UINT8 CapId; - UINT8 TempData; - - PciPrimaryStatus =3D MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET= ); - - if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { - CapabilityOffset =3D MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OF= FSET); - CapabilityOffset &=3D PCI_CAPABILITY_POINTER_MASK; - - while ((CapabilityOffset !=3D INVALID_CAPABILITY_00) && (CapabilityOff= set !=3D INVALID_CAPABILITY_FF)) { - CapId =3D MmioRead8 (PciBaseAddr + CapabilityOffset); - if (CapId =3D=3D EFI_PCI_CAPABILITY_ID_PCIEXP) { - break; - } - CapabilityOffset =3D MmioRead8 (PciBaseAddr + CapabilityOffset + 1); - CapabilityOffset &=3D PCI_CAPABILITY_POINTER_MASK; - } - } else { - PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); - return FALSE; - } - - if ((CapabilityOffset =3D=3D INVALID_CAPABILITY_FF) || (CapabilityOffset= =3D=3D INVALID_CAPABILITY_00)) { - PCIE_DEBUG ("[%a:%d] - No PCIE Capability.\n", __FUNCTION__, __LINE__); - return FALSE; - } - - TempData =3D MmioRead16 (PciBaseAddr + CapabilityOffset + - EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); - TempData &=3D EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; - - if (TempData =3D=3D EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWAR= DING) { - return TRUE; - } else { - return FALSE; - } -} - -VOID -EnlargeAtuConfig0 ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This - ) -{ - UINTN RbPciBase; - UINT64 MemLimit; - LIST_ENTRY *List; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - - PCIE_DEBUG ("In Enlarge RP iatu Config 0.\n"); - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List =3D HostBridgeInstance->Head.ForwardLink; - - while (List !=3D &HostBridgeInstance->Head) { - PCIE_DEBUG ("HostBridge has data.\n"); - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - - RbPciBase =3D RootBridgeInstance->RbPciBar; - - // Those ARI FWD Enable Root Bridge, need enlarge iatu window. - if (PcieCheckAriFwdEn (RbPciBase)) { - MemLimit =3D GetPcieCfgAddress (RootBridgeInstance->Ecam, - RootBridgeInstance->BusBase + 2, 0, 0,= 0) - - 1; - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); - MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT= 32) MemLimit); - } - List =3D List->ForwardLink; - } -} diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPc= iPlatformLib.c b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi16= 1xPciPlatformLib.c index de26259778..dad848e714 100644 --- a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatfo= rmLib.c +++ b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatfo= rmLib.c @@ -14,6 +14,7 @@ **/ =20 #include +#include #include #include #include @@ -21,8 +22,14 @@ #include #include #include +#include +#include +#include #include =20 +#define INVALID_CAPABILITY_00 0x00 +#define INVALID_CAPABILITY_FF 0xFF +#define PCI_CAPABILITY_POINTER_MASK 0xFC =20 STATIC UINT64 @@ -37,6 +44,53 @@ GetPcieCfgAddress ( return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg); } =20 +STATIC +PCI_ROOT_BRIDGE_RESOURCE_APPETURE * +GetAppetureByRootBridgeIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridge + ) +{ + EFI_STATUS Status; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration =3D NULL; + UINTN Hb; + UINTN Rb; + + Status =3D RootBridge->Configuration ( + RootBridge, + (VOID **)&Configuration + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a:%d] RootBridgeIo->Configuration failed %r\n", + __FUNCTION__, __LINE__, Status)); + return NULL; + }; + + while (Configuration->Desc =3D=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + if (Configuration->ResType =3D=3D ACPI_ADDRESS_SPACE_TYPE_BUS) { + break; + } + Configuration++; + } + + if (Configuration->Desc !=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + DEBUG ((DEBUG_ERROR, "[%a:%d] Can't find bus descriptor\n", __FUNCTION= __, __LINE__)); + return NULL; + } + + for (Hb =3D 0; Hb < PCIE_MAX_HOSTBRIDGE; Hb++) { + for (Rb =3D 0; Rb < PCIE_MAX_ROOTBRIDGE; Rb++) { + if (RootBridge->SegmentNumber =3D=3D mResAppeture[Hb][Rb].Segment && + Configuration->AddrRangeMin >=3D mResAppeture[Hb][Rb].BusBase && + Configuration->AddrRangeMax <=3D mResAppeture[Hb][Rb].BusLimit) { + return &mResAppeture[Hb][Rb]; + } + } + } + + DEBUG ((DEBUG_ERROR, "[%a:%d] Can't find PCI appeture\n", __FUNCTION__, = __LINE__)); + return NULL; +} + STATIC VOID SetAtuConfig0RW ( @@ -183,3 +237,148 @@ PciInitPlatform ( return; } =20 +STATIC +BOOLEAN +PcieCheckAriFwdEn ( + UINTN PciBaseAddr + ) +{ + UINT8 PciPrimaryStatus; + UINT8 CapabilityOffset; + UINT8 CapId; + UINT8 TempData; + + PciPrimaryStatus =3D MmioRead16 (PciBaseAddr + PCI_PRIMARY_STATUS_OFFSET= ); + + if (PciPrimaryStatus & EFI_PCI_STATUS_CAPABILITY) { + CapabilityOffset =3D MmioRead8 (PciBaseAddr + PCI_CAPBILITY_POINTER_OF= FSET); + CapabilityOffset &=3D PCI_CAPABILITY_POINTER_MASK; + + while ((CapabilityOffset !=3D INVALID_CAPABILITY_00) && (CapabilityOff= set !=3D INVALID_CAPABILITY_FF)) { + CapId =3D MmioRead8 (PciBaseAddr + CapabilityOffset); + if (CapId =3D=3D EFI_PCI_CAPABILITY_ID_PCIEXP) { + break; + } + CapabilityOffset =3D MmioRead8 (PciBaseAddr + CapabilityOffset + 1); + CapabilityOffset &=3D PCI_CAPABILITY_POINTER_MASK; + } + } else { + return FALSE; + } + + if ((CapabilityOffset =3D=3D INVALID_CAPABILITY_FF) || (CapabilityOffset= =3D=3D INVALID_CAPABILITY_00)) { + return FALSE; + } + + TempData =3D MmioRead16 (PciBaseAddr + CapabilityOffset + + EFI_PCIE_CAPABILITY_DEVICE_CONTROL_2_OFFSET); + TempData &=3D EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWARDING; + + if (TempData =3D=3D EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_2_ARI_FORWAR= DING) { + return TRUE; + } else { + return FALSE; + } +} + +VOID +EnlargeAtuConfig0 ( + IN EFI_HANDLE HostBridge + ) +{ + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *ResAlloc =3D NULL; + EFI_STATUS Status; + EFI_HANDLE RootBridgeHandle =3D NULL; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *RootBridgeIo =3D NULL; + PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Appeture; + UINTN RbPciBase; + UINT64 MemLimit; + + DEBUG ((DEBUG_INFO, "In Enlarge RP iATU Config 0.\n")); + + Status =3D gBS->HandleProtocol ( + HostBridge, + &gEfiPciHostBridgeResourceAllocationProtocolGuid, + (VOID **)&ResAlloc + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - HandleProtocol failed %r\n", __FUNCTIO= N__, + __LINE__, Status)); + return; + } + + while (TRUE) { + Status =3D ResAlloc->GetNextRootBridge ( + ResAlloc, + &RootBridgeHandle + ); + if (EFI_ERROR (Status)) { + break; + } + Status =3D gBS->HandleProtocol ( + RootBridgeHandle, + &gEfiPciRootBridgeIoProtocolGuid, + (VOID **)&RootBridgeIo + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "[%a:%d] - HandleProtocol failed %r\n", __FUNCT= ION__, __LINE__, Status)); + // This should never happen so that it is a fatal error and we don't= try + // to continue + break; + } + + Appeture =3D GetAppetureByRootBridgeIo (RootBridgeIo); + if (Appeture =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "[%a:%d] Get appeture failed\n", __FUNCTION__, + __LINE__)); + continue; + } + + RbPciBase =3D Appeture->RbPciBar; + // Those ARI FWD Enable Root Bridge, need enlarge iATU window. + if (PcieCheckAriFwdEn (RbPciBase)) { + MemLimit =3D GetPcieCfgAddress (Appeture->Ecam, Appeture->BusBase + = 2, 0, 0, 0) - 1; + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, 1); + MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT= 32) MemLimit); + } + } +} + +/*++ + +Routine Description: + + Perform Platform initialization by the phase indicated. + +Arguments: + + HostBridge - The associated PCI host bridge handle. + Phase - The phase of the PCI controller enumeration. + ChipsetPhase - Defines the execution phase of the PCI chipset driver. + +Returns: + +--*/ +VOID +EFIAPI +PhaseNotifyPlatform ( + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + switch (Phase) { + case EfiPciHostBridgeEndEnumeration: + // Only do once + if (ChipsetPhase =3D=3D ChipsetEntry) { + DEBUG ((DEBUG_INFO, "PCI end enumeration platform hook\n")); + EnlargeAtuConfig0 (HostBridge); + } + break; + default: + break; + } + + return ; +} + --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel