From nobody Mon Feb 9 18:19:25 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1532413991829280.01467746331366; Mon, 23 Jul 2018 23:33:11 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id CF1FC210C124C; Mon, 23 Jul 2018 23:33:10 -0700 (PDT) Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 577BC210C1243 for ; Mon, 23 Jul 2018 23:33:09 -0700 (PDT) Received: by mail-pg1-x543.google.com with SMTP id y5-v6so2148842pgv.1 for ; Mon, 23 Jul 2018 23:33:09 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id e2-v6sm12086575pgo.92.2018.07.23.23.33.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 23 Jul 2018 23:33:07 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::543; helo=mail-pg1-x543.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u3KgeujAS0IspEAY9duzVLcOb8K4pFvkXDLuJZuwswQ=; b=A5w7jK7vH3N9MJFUzalwm+Uz5I93pBU3RqCFGR638hsIS/l60ZhcbzUmnCn4YuSzb2 ylsNh5VTL0Jq1US6IiQNbylkpHEhDJPmFw5qyfR44YEtFPRYtEz8vkRCk5bRflW0UP5g GnMVKHmylhbb1RKt12CTVE9ttx+mkIwLYibK0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u3KgeujAS0IspEAY9duzVLcOb8K4pFvkXDLuJZuwswQ=; b=WiL5PTiwt/HbsALH5uoLR8o3E3fysIReikozQRtzjQxcDpg43G7wKfPOTGHO5D5e+2 2opGD8RjfqTI9SSx/ehbbT4gXW5TZLPOdMzRIBblL2Y0LNOqzVF4+TyxBl9mO22OeEaz CZ8sUuRqs//0wMPdYxJsFc+Sf/UwUtRK3D0CNXQP7h7+ZsxvNRgvv5DLwbVR1MZ6kCyK y/XWhwBnbUMEZcYL1GkXwXH1pkkS36PrEh9N6uee3D8Yz92iMXB4F+2qngXpeHfjsgMB PLYM8OPl/m7I+D+SfNtbDPHI/gNBjSVJtCVENINVp6H2dcEiB836QwCPRiSlycC3ftJ8 hplw== X-Gm-Message-State: AOUpUlElobkhFLHgeZfxcByRAho1DqbcUOFjTZ37mYEman1PdJrpopdn Q9VdotXwRBsHY0SqxHtEig/lgw== X-Google-Smtp-Source: AAOMgpdGuHWSxWnn/FO0ThS1FMq9gKQmrOqf0DOuOTVwNxST9tNU/Cs+W1Bk7qjO+32Of3FYLlPyZQ== X-Received: by 2002:a62:3001:: with SMTP id w1-v6mr16327540pfw.19.1532413988484; Mon, 23 Jul 2018 23:33:08 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Date: Tue, 24 Jul 2018 14:32:19 +0800 Message-Id: <20180724063220.61679-12-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724063220.61679-1-ming.huang@linaro.org> References: <20180724063220.61679-1-ming.huang@linaro.org> Subject: [edk2] [PATCH edk2-platforms v2 11/12] Hisilicon: remove platform specific PciHostBridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: huangming23@huawei.com, xinliang.liu@linaro.org, john.garry@huawei.com, zhangjinsong2@huawei.com, Michael D Kinney , Yi Li , huangdaode@hisilicon.com, guoheyi@huawei.com, wanghuiqiang@huawei.com MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" From: Heyi Guo PciHostBridge in Silicon/Hisilicon is specific for D03/D05. After we switch to generic PciHostBridge in MdeModulePkg, this driver is useless and can be removed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Signed-off-by: Yi Li Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c | 1658 ---= ------------ Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h | 520 ---= -- Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf | 74 - Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2220 ---= ----------------- 4 files changed, 4472 deletions(-) diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c b/S= ilicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c deleted file mode 100644 index e3d3988a64..0000000000 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.c +++ /dev/null @@ -1,1658 +0,0 @@ -/** - * Copyright (c) 2014, AppliedMicro Corp. All rights reserved. - * Copyright (c) 2016, Hisilicon Limited. All rights reserved. - * Copyright (c) 2016, Linaro Limited. All rights reserved. - * - * This program and the accompanying materials - * are licensed and made available under the terms and conditions of the B= SD License - * which accompanies this distribution. The full text of the license may = be found at - * http://opensource.org/licenses/bsd-license.php - * - * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. - * - **/ - -#include -#include -#include -#include -#include -#include - -#include "PciHostBridge.h" - -UINTN RootBridgeNumber[PCIE_MAX_HOSTBRIDGE] =3D { PCIE_MAX_ROOTBRIDGE,PCIE= _MAX_ROOTBRIDGE }; - -UINT64 RootBridgeAttribute[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] =3D { - { //Host Bridge0 - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - }, - { //Host Bridge1 - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - EFI_PCI_HOST_BRIDGE_MEM64_DECODE, - } - }; - -EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTB= RIDGE][PCIE_MAX_ROOTBRIDGE] =3D { - { //Host Bridge0 - /* Port 0 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A03), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 1 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A04), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 2 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A05), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 3 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A06), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 4 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A07), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 5 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A08), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 6 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A09), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 7 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A0A), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - } -}, -{ // Host Bridge1 - /* Port 0 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A0B), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 1 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A0C), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 2 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A0D), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 3 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A0E), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 4 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A0F), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 5 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A10), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 6 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A11), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - }, - /* Port 7 */ - { - { - { - ACPI_DEVICE_PATH, - ACPI_DP, - { - (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), - (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) - } - }, - EISA_PNP_ID(0x0A12), - 0 - }, - - { - END_DEVICE_PATH_TYPE, - END_ENTIRE_DEVICE_PATH_SUBTYPE, - { - END_DEVICE_PATH_LENGTH, - 0 - } - } - } - } -}; - -EFI_HANDLE mDriverImageHandle; - -PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate =3D { - PCI_HOST_BRIDGE_SIGNATURE, // Signature - NULL, // HostBridgeHandle - 0, // RootBridgeNumber - {NULL, NULL}, // Head - FALSE, // ResourceSubiteed - TRUE, // CanRestarted - { - NotifyPhase, - GetNextRootBridge, - GetAttributes, - StartBusEnumeration, - SetBusNumbers, - SubmitResources, - GetProposedResources, - PreprocessController - } -}; - -/** - Entry point of this driver - - @param ImageHandle Handle of driver image - @param SystemTable Point to EFI_SYSTEM_TABLE - - @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource - @retval EFI_DEVICE_ERROR Can not install the protocol instance - @retval EFI_SUCCESS Success to initialize the Pci host bridge. -**/ -EFI_STATUS -EFIAPI -InitializePciHostBridge ( - IN EFI_HANDLE ImageHandle, - IN EFI_SYSTEM_TABLE *SystemTable - ) -{ - EFI_STATUS Status; - UINTN Loop1; - UINTN Loop2; - PCI_HOST_BRIDGE_INSTANCE *HostBridge =3D NULL; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - UINT32 PcieRootBridgeMask; - - if (!OemIsMpBoot()) - { - PcieRootBridgeMask =3D PcdGet32(PcdPcieRootBridgeMask); - } - else - { - PcieRootBridgeMask =3D PcdGet32(PcdPcieRootBridgeMask2P); - } - - mDriverImageHandle =3D ImageHandle; - // - // Create Host Bridge Device Handle - // - //Each Host Bridge have 8 Root Bridges max, every bits of 0xFF(8 bit) st= ands for the according PCIe Port - //is enable or not - for (Loop1 =3D 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) { - if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) = =3D=3D 0) { - continue; - } - - - HostBridge =3D AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mP= ciHostBridgeInstanceTemplate); - if (HostBridge =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - HostBridge->RootBridgeNumber =3D RootBridgeNumber[Loop1]; - InitializeListHead (&HostBridge->Head); - - Status =3D gBS->InstallMultipleProtocolInterfaces ( - &HostBridge->HostBridgeHandle, - &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostB= ridge->ResAlloc, - NULL - ); - if (EFI_ERROR (Status)) { - FreePool (HostBridge); - return EFI_DEVICE_ERROR; - } - - // - // Create Root Bridge Device Handle in this Host Bridge - // - for (Loop2 =3D 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) { - if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop= 2 ) & 0x01)) { - continue; - } - - PrivateData =3D AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE)); - if (PrivateData =3D=3D NULL) { - FreePool (HostBridge); - return EFI_OUT_OF_RESOURCES; - } - PrivateData->Port =3D Loop2; - PrivateData->SocType =3D PcdGet32(Pcdsoctype); - PrivateData->Signature =3D PCI_ROOT_BRIDGE_SIGNATURE; - PrivateData->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRoot= BridgeDevicePath[Loop1][Loop2]; - - (VOID)RootBridgeConstructor ( - &PrivateData->Io, - HostBridge->HostBridgeHandle, - RootBridgeAttribute[Loop1][Loop2], - &mResAppeture[Loop1][Loop2], - Loop1 - ); - - Status =3D gBS->InstallMultipleProtocolInterfaces( - &PrivateData->Handle, - &gEfiDevicePathProtocolGuid, PrivateData->Devic= ePath, - &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io, - NULL - ); - if (EFI_ERROR (Status)) { - (VOID)gBS->UninstallMultipleProtocolInterfaces ( - HostBridge->HostBridgeHandle, - &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBri= dge->ResAlloc, - NULL - ); - FreePool(PrivateData); - FreePool (HostBridge); - return EFI_DEVICE_ERROR; - } - // PCI Memory Space - Status =3D gDS->AddMemorySpace ( - EfiGcdMemoryTypeMemoryMappedIo, - mResAppeture[Loop1][Loop2] .MemBase, - mResAppeture[Loop1][Loop2] .MemLimit -mResAppeture[Loop1][Loo= p2] .MemBase + 1, - 0 - ); - if (EFI_ERROR (Status)) { - DEBUG((EFI_D_ERROR,"PCIE AddMemorySpace Error\n")); - } - InsertTailList (&HostBridge->Head, &PrivateData->Link); - } - } - - return EFI_SUCCESS; -} - -EFI_STATUS -EFIAPI -NotifyAllocateMemResources( - IN PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance, - IN PCI_RESOURCE_TYPE Index, - IN OUT UINT64 *AllocatedLenMem -) -{ - EFI_PHYSICAL_ADDRESS BaseAddress; - EFI_STATUS ReturnStatus; - UINT64 AddrLen; - UINTN BitsOfAlignment; - - AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; - PCIE_DEBUG("Addrlen:%llx\n", AddrLen); - // Get the number of '1' in Alignment. - BitsOfAlignment =3D (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocN= ode[Index].Alignment) + 1); - - BaseAddress =3D (RootBridgeInstance->MemBase + *AllocatedLenMem + - RootBridgeInstance->ResAllocNode[Index].Alignment) - & ~(RootBridgeInstance->ResAllocNode[Index].Alignm= ent); - if ((BaseAddress + AddrLen - 1) > RootBridgeInstance->MemLimit) { - ReturnStatus =3D EFI_OUT_OF_RESOURCES; - RootBridgeInstance->ResAllocNode[Index].Length =3D 0; - return ReturnStatus; - } - - PCIE_DEBUG("(P)Mem32/64 request memory at:%llx\n", BaseAddress); - ReturnStatus =3D gDS->AllocateMemorySpace ( - EfiGcdAllocateAddress, - EfiGcdMemoryTypeMemoryMappedIo, - BitsOfAlignment, - AddrLen, - &BaseAddress, - mDriverImageHandle, - NULL - ); - - if (!EFI_ERROR (ReturnStatus)) { - // We were able to allocate the PCI memory - RootBridgeInstance->ResAllocNode[Index].Base =3D (UINTN)BaseAddress; - RootBridgeInstance->ResAllocNode[Index].Status =3D ResAllocated; - *AllocatedLenMem +=3D AddrLen; - PCIE_DEBUG("(P)Mem32/64 resource allocated:%llx\n", BaseAddress); - - } else { - // Not able to allocate enough PCI memory - if (ReturnStatus !=3D EFI_OUT_OF_RESOURCES) { - RootBridgeInstance->ResAllocNode[Index].Length =3D 0; - } - } - return ReturnStatus; -} - -EFI_STATUS -EFIAPI -NotifyAllocateResources( - IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance -) -{ - EFI_STATUS ReturnStatus; - LIST_ENTRY *List; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - PCI_RESOURCE_TYPE Index; - - ReturnStatus =3D EFI_SUCCESS; - List =3D HostBridgeInstance->Head.ForwardLink; - - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - - UINT64 AllocatedLenMem =3D 0; - for (Index =3D TypeIo; Index < TypeBus; Index++) { - if (RootBridgeInstance->ResAllocNode[Index].Status !=3D ResNone) { - if(Index =3D=3D TypeIo) { - PCIE_DEBUG("NOT SUPPOER IO RESOURCES ON THIS PLATFORM\n"); - } else if ((Index >=3D TypeMem32) && (Index <=3D TypePMem64)) { - ReturnStatus =3D NotifyAllocateMemResources(RootBridgeInstance,I= ndex,&AllocatedLenMem); - } else { - ASSERT (FALSE); - } - } - } - - List =3D List->ForwardLink; - } - - return ReturnStatus; -} - -EFI_STATUS -EFIAPI -NotifyFreeResources( - IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance -) -{ - EFI_STATUS ReturnStatus; - LIST_ENTRY *List; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - PCI_RESOURCE_TYPE Index; - UINT64 AddrLen; - EFI_PHYSICAL_ADDRESS BaseAddress; - - ReturnStatus =3D EFI_SUCCESS; - List =3D HostBridgeInstance->Head.ForwardLink; - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - for (Index =3D TypeIo; Index < TypeBus; Index++) { - if (RootBridgeInstance->ResAllocNode[Index].Status =3D=3D ResAllocat= ed) { - AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; - BaseAddress =3D RootBridgeInstance->ResAllocNode[Index].Base; - - if(Index <=3D TypePMem64){ - ReturnStatus =3D gDS->FreeMemorySpace (BaseAddress, AddrLen); - }else{ - ASSERT (FALSE); - } - - RootBridgeInstance->ResAllocNode[Index].Type =3D Index; - RootBridgeInstance->ResAllocNode[Index].Base =3D 0; - RootBridgeInstance->ResAllocNode[Index].Length =3D 0; - RootBridgeInstance->ResAllocNode[Index].Status =3D ResNone; - } - } - - List =3D List->ForwardLink; - } - - HostBridgeInstance->ResourceSubmited =3D FALSE; - HostBridgeInstance->CanRestarted =3D TRUE; - return ReturnStatus; - -} - -VOID -EFIAPI -NotifyBeginEnumeration( - IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance -) -{ - LIST_ENTRY *List; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - PCI_RESOURCE_TYPE Index; - - // - // Reset the Each Root Bridge - // - List =3D HostBridgeInstance->Head.ForwardLink; - - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - for (Index =3D TypeIo; Index < TypeMax; Index++) { - RootBridgeInstance->ResAllocNode[Index].Type =3D Index; - RootBridgeInstance->ResAllocNode[Index].Base =3D 0; - RootBridgeInstance->ResAllocNode[Index].Length =3D 0; - RootBridgeInstance->ResAllocNode[Index].Status =3D ResNone; - } - - List =3D List->ForwardLink; - } - - HostBridgeInstance->ResourceSubmited =3D FALSE; - HostBridgeInstance->CanRestarted =3D TRUE; -} - -/** - These are the notifications from the PCI bus driver that it is about to= enter a certain - phase of the PCI enumeration process. - - This member function can be used to notify the host bridge driver to pe= rform specific actions, - including any chipset-specific initialization, so that the chipset is r= eady to enter the next phase. - Eight notification points are defined at this time. See belows: - EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apert= ures and internal data - structures. The PCI enumerator s= hould issue this notification - before starting a fresh enumerat= ion process. Enumeration cannot - be restarted after sending any o= ther notification such as - EfiPciHostBridgeBeginBusAllocati= on. - EfiPciHostBridgeBeginBusAllocation The bus allocation phase is abou= t to begin. No specific action is - required here. This notification= can be used to perform any - chipset-specific programming. - EfiPciHostBridgeEndBusAllocation The bus allocation and bus progr= amming phase is complete. No - specific action is required here= . This notification can be used to - perform any chipset-specific pro= gramming. - EfiPciHostBridgeBeginResourceAllocation - The resource allocation phase is= about to begin. No specific - action is required here. This no= tification can be used to perform - any chipset-specific programming. - EfiPciHostBridgeAllocateResources Allocates resources per previous= ly submitted requests for all the PCI - root bridges. These resource set= tings are returned on the next call to - GetProposedResources(). Before c= alling NotifyPhase() with a Phase of - EfiPciHostBridgeAllocateResource= , the PCI bus enumerator is responsible - for gathering I/O and memory req= uests for - all the PCI root bridges and sub= mitting these requests using - SubmitResources(). This function= pads the resource amount - to suit the root bridge hardware= , takes care of dependencies between - the PCI root bridges, and calls = the Global Coherency Domain (GCD) - with the allocation request. In = the case of padding, the allocated range - could be bigger than what was re= quested. - EfiPciHostBridgeSetResources Programs the host bridge hardwar= e to decode previously allocated - resources (proposed resources) f= or all the PCI root bridges. After the - hardware is programmed, reassign= ing resources will not be supported. - The bus settings are not affecte= d. - EfiPciHostBridgeFreeResources Deallocates resources that were = previously allocated for all the PCI - root bridges and resets the I/O = and memory apertures to their initial - state. The bus settings are not = affected. If the request to allocate - resources fails, the PCI enumera= tor can use this notification to - deallocate previous resources, a= djust the requests, and retry - allocation. - EfiPciHostBridgeEndResourceAllocation The resource allocation phase is= completed. No specific action is - required here. This notification= can be used to perform any chipsetspecific - programming. - - @param[in] This The instance pointer of EFI_PCI_HOST_BRI= DGE_RESOURCE_ALLOCATION_PROTOCOL - @param[in] Phase The phase during enumeration - - @retval EFI_NOT_READY This phase cannot be entered at this tim= e. For example, this error - is valid for a Phase of EfiPciHostBridge= AllocateResources if - SubmitResources() has not been called fo= r one or more - PCI root bridges before this call - @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. This error is valid - for a Phase of EfiPciHostBridgeSetResour= ces. - @retval EFI_INVALID_PARAMETER Invalid phase parameter - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - This error is valid for a Phase of EfiPc= iHostBridgeAllocateResources if the - previously submitted resource requests c= annot be fulfilled or - were only partially fulfilled. - @retval EFI_SUCCESS The notification was accepted without an= y errors. - -**/ -EFI_STATUS -EFIAPI -NotifyPhase( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - EFI_STATUS ReturnStatus; - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - ReturnStatus =3D EFI_SUCCESS; - - switch (Phase) { - - case EfiPciHostBridgeBeginEnumeration: - PCIE_DEBUG("Case EfiPciHostBridgeBeginEnumeration\n"); - if (HostBridgeInstance->CanRestarted) { - NotifyBeginEnumeration(HostBridgeInstance); - } else { - // - // Can not restart - // - return EFI_NOT_READY; - } - break; - - case EfiPciHostBridgeEndEnumeration: - PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n"); - break; - - case EfiPciHostBridgeBeginBusAllocation: - PCIE_DEBUG("Case EfiPciHostBridgeBeginBusAllocation\n"); - // - // No specific action is required here, can perform any chipset specif= ic programing - // - - HostBridgeInstance->CanRestarted =3D FALSE; - break; - - case EfiPciHostBridgeEndBusAllocation: - PCIE_DEBUG("Case EfiPciHostBridgeEndBusAllocation\n"); - // - // No specific action is required here, can perform any chipset specif= ic programing - // - break; - - case EfiPciHostBridgeBeginResourceAllocation: - PCIE_DEBUG("Case EfiPciHostBridgeBeginResourceAllocation\n"); - // - // No specific action is required here, can perform any chipset specif= ic programing - // - break; - - case EfiPciHostBridgeAllocateResources: - PCIE_DEBUG("Case EfiPciHostBridgeAllocateResources\n"); - - if (HostBridgeInstance->ResourceSubmited) { - // - // Take care of the resource dependencies between the root bridges - // - ReturnStatus =3D NotifyAllocateResources(HostBridgeInstance); - } else { - return EFI_NOT_READY; - } - //break; - - case EfiPciHostBridgeSetResources: - PCIE_DEBUG("Case EfiPciHostBridgeSetResources\n"); - break; - - case EfiPciHostBridgeFreeResources: - PCIE_DEBUG("Case EfiPciHostBridgeFreeResources\n"); - - ReturnStatus =3D NotifyFreeResources(HostBridgeInstance); - break; - - case EfiPciHostBridgeEndResourceAllocation: - PCIE_DEBUG("Case EfiPciHostBridgeEndResourceAllocation\n"); - HostBridgeInstance->CanRestarted =3D FALSE; - break; - - default: - return EFI_INVALID_PARAMETER; - } - - return ReturnStatus; -} - -/** - Return the device handle of the next PCI root bridge that is associated= with this Host Bridge. - - This function is called multiple times to retrieve the device handles o= f all the PCI root bridges that - are associated with this PCI host bridge. Each PCI host bridge is assoc= iated with one or more PCI - root bridges. On each call, the handle that was returned by the previou= s call is passed into the - interface, and on output the interface returns the device handle of the= next PCI root bridge. The - caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BR= IDGE_IO_PROTOCOL - for that root bridge. When there are no more PCI root bridges to report= , the interface returns - EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in = the order that they - are returned by this function. - For D945 implementation, there is only one root bridge in PCI host brid= ge. - - @param[in] This The instance pointer of EFI_PCI_HOST= _BRIDGE_RESOURCE_ALLOCATION_PROTOCOL - @param[in, out] RootBridgeHandle Returns the device handle of the nex= t PCI root bridge. - - @retval EFI_SUCCESS If parameter RootBridgeHandle =3D NULL, = then return the first Rootbridge handle of the - specific Host bridge and return EFI_SUCC= ESS. - @retval EFI_NOT_FOUND Can not find the any more root bridge in= specific host bridge. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE th= at was - returned on a previous call to GetNextRo= otBridge(). -**/ -EFI_STATUS -EFIAPI -GetNextRootBridge( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN OUT EFI_HANDLE *RootBridgeHan= dle - ) -{ - BOOLEAN NoRootBridge; - LIST_ENTRY *List; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - - NoRootBridge =3D TRUE; - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List =3D HostBridgeInstance->Head.ForwardLink; - - - while (List !=3D &HostBridgeInstance->Head) { - NoRootBridge =3D FALSE; - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - if (*RootBridgeHandle =3D=3D NULL) { - // - // Return the first Root Bridge Handle of the Host Bridge - // - *RootBridgeHandle =3D RootBridgeInstance->Handle; - return EFI_SUCCESS; - } else { - if (*RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { - // - // Get next if have - // - List =3D List->ForwardLink; - if (List!=3D&HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - *RootBridgeHandle =3D RootBridgeInstance->Handle; - return EFI_SUCCESS; - } else { - return EFI_NOT_FOUND; - } - } - } - - List =3D List->ForwardLink; - } //end while - - if (NoRootBridge) { - return EFI_NOT_FOUND; - } else { - return EFI_INVALID_PARAMETER; - } -} - -/** - Returns the allocation attributes of a PCI root bridge. - - The function returns the allocation attributes of a specific PCI root b= ridge. The attributes can vary - from one PCI root bridge to another. These attributes are different fro= m the decode-related - attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Get= Attributes() member function. The - RootBridgeHandle parameter is used to specify the instance of the PCI r= oot bridge. The device - handles of all the root bridges that are associated with this host brid= ge must be obtained by calling - GetNextRootBridge(). The attributes are static in the sense that they d= o not change during or - after the enumeration process. The hardware may provide mechanisms to c= hange the attributes on - the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_= RESOURCE_ALLOCATION_PROTOCOL is - installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCAT= ION_ATTRIBUTES are defined in - "Related Definitions" below. The caller uses these attributes to combin= e multiple resource requests. - For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, t= he PCI bus enumerator needs to - include requests for the prefetchable memory in the nonprefetchable mem= ory pool and not request any - prefetchable memory. - Attribute Description - ------------------------------------ --------------------------= -------------------------------------------- - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then t= he PCI root bridge does not support separate - windows for nonprefetchabl= e and prefetchable memory. A PCI bus - driver needs to include re= quests for prefetchable memory in the - nonprefetchable memory poo= l. - - EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then t= he PCI root bridge supports 64-bit memory - windows. If this bit is no= t set, the PCI bus driver needs to include - requests for a 64-bit memo= ry address in the corresponding 32-bit - memory pool. - - @param[in] This The instance pointer of EFI_PCI_HOST_BR= IDGE_RESOURCE_ALLOCATION_PROTOCOL - @param[in] RootBridgeHandle The device handle of the PCI root bridg= e in which the caller is interested. Type - EFI_HANDLE is defined in InstallProtoco= lInterface() in the UEFI 2.0 Specification. - @param[out] Attributes The pointer to attribte of root bridge,= it is output parameter - - @retval EFI_INVALID_PARAMETER Attribute pointer is NULL - @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid. - @retval EFI_SUCCESS Success to get attribute of interested = root bridge. - -**/ -EFI_STATUS -EFIAPI -GetAttributes( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT UINT64 *Attributes - ) -{ - LIST_ENTRY *List; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - - if (Attributes =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List =3D HostBridgeInstance->Head.ForwardLink; - - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { - *Attributes =3D RootBridgeInstance->RootBridgeAttrib; - return EFI_SUCCESS; - } - - List =3D List->ForwardLink; - } - - // - // RootBridgeHandle is not an EFI_HANDLE - // that was returned on a previous call to GetNextRootBridge() - // - return EFI_INVALID_PARAMETER; -} - -/** - Sets up the specified PCI root bridge for the bus enumeration process. - - This member function sets up the root bridge for bus enumeration and re= turns the PCI bus range - over which the search should be performed in ACPI 2.0 resource descript= or format. - - @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCAT= ION_ PROTOCOL instance. - @param[in] RootBridgeHandle The PCI Root Bridge to be set up. - @param[out] Configuration Pointer to the pointer to the PCI bus re= source descriptor. - - @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle - @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor= tag. - @retval EFI_SUCCESS Sucess to allocate ACPI resource descript= or. - -**/ -EFI_STATUS -EFIAPI -StartBusEnumeration( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ) -{ - LIST_ENTRY *List; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - VOID *Buffer; - UINT8 *Temp; - UINT64 BusStart; - UINT64 BusEnd; - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List =3D HostBridgeInstance->Head.ForwardLink; - - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { - // - // Set up the Root Bridge for Bus Enumeration - // - BusStart =3D RootBridgeInstance->BusBase; - BusEnd =3D RootBridgeInstance->BusLimit; - // - // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR - // - - Buffer =3D AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) += sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)); - if (Buffer =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - Temp =3D (UINT8 *)Buffer; - - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc =3D 0x8A; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len =3D 0x2B; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType =3D 2; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin =3D BusSta= rt; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = =3D 0; - ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen =3D BusEnd - Bu= sStart + 1; - - Temp =3D Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc =3D 0x79; - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum =3D 0x0; - - *Configuration =3D Buffer; - return EFI_SUCCESS; - } - List =3D List->ForwardLink; - } - - return EFI_INVALID_PARAMETER; -} - -/** - Programs the PCI root bridge hardware so that it decodes the specified = PCI bus range. - - This member function programs the specified PCI root bridge to decode t= he bus range that is - specified by the input parameter Configuration. - The bus range information is specified in terms of the ACPI 2.0 resourc= e descriptor format. - - @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATIO= N_ PROTOCOL instance - @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to = be programmed - @param[in] Configuration The pointer to the PCI bus resource descri= ptor - - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge handle. - @retval EFI_INVALID_PARAMETER Configuration is NULL. - @retval EFI_INVALID_PARAMETER Configuration does not point to a valid = ACPI 2.0 resource descriptor. - @retval EFI_INVALID_PARAMETER Configuration does not include a valid A= CPI 2.0 bus resource descriptor. - @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 re= source descriptors other than - bus descriptors. - @retval EFI_INVALID_PARAMETER Configuration contains one or more inval= id ACPI resource descriptors. - @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for t= his root bridge. - @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for th= is root bridge. - @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. - @retval EFI_SUCCESS The bus range for the PCI root bridge wa= s programmed. - -**/ -EFI_STATUS -EFIAPI -SetBusNumbers( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ) -{ - LIST_ENTRY *List; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - UINT8 *Ptr; - UINTN BusStart; - UINTN BusEnd; - UINTN BusLen; - - if (Configuration =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - Ptr =3D Configuration; - - // - // Check the Configuration is valid - // - if(*Ptr !=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { - return EFI_INVALID_PARAMETER; - } - - if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType !=3D 2) { - return EFI_INVALID_PARAMETER; - } - - Ptr +=3D sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - if (*Ptr !=3D ACPI_END_TAG_DESCRIPTOR) { - return EFI_INVALID_PARAMETER; - } - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List =3D HostBridgeInstance->Head.ForwardLink; - - Ptr =3D Configuration; - - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { - BusStart =3D (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->Addr= RangeMin; - BusLen =3D (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLe= n; - BusEnd =3D BusStart + BusLen - 1; - - if (BusStart > BusEnd) { - return EFI_INVALID_PARAMETER; - } - - if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridge= Instance->BusLimit)) { - return EFI_INVALID_PARAMETER; - } - - // - // Update the Bus Range - // - RootBridgeInstance->ResAllocNode[TypeBus].Base =3D BusStart; - RootBridgeInstance->ResAllocNode[TypeBus].Length =3D BusLen; - RootBridgeInstance->ResAllocNode[TypeBus].Status =3D ResAllocated; - - // - // Program the Root Bridge Hardware - // - - return EFI_SUCCESS; - } - - List =3D List->ForwardLink; - } - - return EFI_INVALID_PARAMETER; -} - -VOID -EFIAPI -SubmitGetResourceType( - IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr, - OUT UINT64* Index -) -{ - switch (Ptr->ResType) { - case 0: - if (Ptr->AddrSpaceGranularity =3D=3D 32) { - if (Ptr->SpecificFlag =3D=3D 0x06) - *Index =3D TypePMem32; - else - *Index =3D TypeMem32; - } - - if (Ptr->AddrSpaceGranularity =3D=3D 64) { - if (Ptr->SpecificFlag =3D=3D 0x06) - *Index =3D TypePMem64; - else - *Index =3D TypeMem64; - } - break; - - case 1: - *Index =3D TypeIo; - break; - - default: - break; - }; - -} - -/** - Submits the I/O and memory resource requirements for the specified PCI = root bridge. - - This function is used to submit all the I/O and memory resources that a= re required by the specified - PCI root bridge. The input parameter Configuration is used to specify t= he following: - - The various types of resources that are required - - The associated lengths in terms of ACPI 2.0 resource descriptor format - - @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURC= E_ALLOCATION_PROTOCOL instance. - @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory r= esource requirements are being submitted. - @param[in] Configuration The pointer to the PCI I/O and PCI memory = resource descriptor. - - @retval EFI_SUCCESS The I/O and memory resource requests for= a PCI root bridge were accepted. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge handle. - @retval EFI_INVALID_PARAMETER Configuration is NULL. - @retval EFI_INVALID_PARAMETER Configuration does not point to a valid = ACPI 2.0 resource descriptor. - @retval EFI_INVALID_PARAMETER Configuration includes requests for one = or more resource types that are - not supported by this PCI root bridge. T= his error will happen if the caller - did not combine resources according to A= ttributes that were returned by - GetAllocAttributes(). - @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid. - @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for th= is PCI root bridge. - @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid f= or this PCI root bridge. - -**/ -EFI_STATUS -EFIAPI -SubmitResources( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ) -{ - LIST_ENTRY *List; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - UINT8 *Temp; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr; - UINT64 AddrLen; - UINT64 Alignment; - UINTN Index; - - PCIE_DEBUG("In SubmitResources\n"); - // - // Check the input parameter: Configuration - // - if (Configuration =3D=3D NULL) - return EFI_INVALID_PARAMETER; - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List =3D HostBridgeInstance->Head.ForwardLink; - - Temp =3D (UINT8 *)Configuration; - while ( *Temp =3D=3D 0x8A) - Temp +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ; - - if (*Temp !=3D 0x79) - return EFI_INVALID_PARAMETER; - - Temp =3D (UINT8 *)Configuration; - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { - while ( *Temp =3D=3D 0x8A) { - Ptr =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ; - PCIE_DEBUG("Ptr->ResType:%d\n", Ptr->ResType); - PCIE_DEBUG("Ptr->Addrlen:%llx\n", Ptr->AddrLen); - PCIE_DEBUG("Ptr->AddrRangeMax:%llx\n", Ptr->AddrRangeMax); - PCIE_DEBUG("Ptr->AddrRangeMin:%llx\n", Ptr->AddrRangeMin); - PCIE_DEBUG("Ptr->SpecificFlag:%llx\n", Ptr->SpecificFlag); - PCIE_DEBUG("Ptr->AddrSpaceGranularity:%d\n", Ptr->AddrSpaceGranula= rity); - PCIE_DEBUG("RootBridgeInstance->RootBridgeAttrib:%llx\n", RootBrid= geInstance->RootBridgeAttrib); - // - // Check address range alignment - // - if (Ptr->AddrRangeMax !=3D (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1= ) - 1)) { - return EFI_INVALID_PARAMETER; - } - Index =3D 0; - SubmitGetResourceType(Ptr,&Index); - AddrLen =3D (UINTN) Ptr->AddrLen; - Alignment =3D (UINTN) Ptr->AddrRangeMax; - RootBridgeInstance->ResAllocNode[Index].Length =3D AddrLen; - RootBridgeInstance->ResAllocNode[Index].Alignment =3D Alignment; - RootBridgeInstance->ResAllocNode[Index].Status =3D ResRequested; - HostBridgeInstance->ResourceSubmited =3D TRUE; - - Temp +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ; - } - - return EFI_SUCCESS; - } - - List =3D List->ForwardLink; - } - return EFI_INVALID_PARAMETER; -} - -/** - Returns the proposed resource settings for the specified PCI root bridg= e. - - This member function returns the proposed resource settings for the spe= cified PCI root bridge. The - proposed resource settings are prepared when NotifyPhase() is called wi= th a Phase of - EfiPciHostBridgeAllocateResources. The output parameter Configuration - specifies the following: - - The various types of resources, excluding bus resources, that are all= ocated - - The associated lengths in terms of ACPI 2.0 resource descriptor format - - @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOUR= CE_ALLOCATION_PROTOCOL instance. - @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HAND= LE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. - @param[out] Configuration The pointer to the pointer to the PCI I/O= and memory resource descriptor. - - @retval EFI_SUCCESS The requested parameters were returned. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge handle. - @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -SetResource( - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance, - VOID *Buffer - -) -{ - UINTN Index; - UINT8 *Temp; - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr; - UINT64 ResStatus; - - Temp =3D Buffer; - - for (Index =3D 0; Index < TypeBus; Index ++) - { - if (RootBridgeInstance->ResAllocNode[Index].Status !=3D ResNone) { - Ptr =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ; - ResStatus =3D RootBridgeInstance->ResAllocNode[Index].Status; - - switch (Index) { - - case TypeIo: - // - // Io - // - Ptr->Desc =3D 0x8A; - Ptr->Len =3D 0x2B; - Ptr->ResType =3D 1; - Ptr->GenFlag =3D 0; - Ptr->SpecificFlag =3D 0; - /* PCIE Device Iobar address should be based on IoBase */ - Ptr->AddrRangeMin =3D RootBridgeInstance->IoBase; - Ptr->AddrRangeMax =3D 0; - Ptr->AddrTranslationOffset =3D \ - (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; - Ptr->AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; - break; - - case TypeMem32: - // - // Memory 32 - // - Ptr->Desc =3D 0x8A; - Ptr->Len =3D 0x2B; - Ptr->ResType =3D 0; - Ptr->GenFlag =3D 0; - Ptr->SpecificFlag =3D 0; - Ptr->AddrSpaceGranularity =3D 32; - /* PCIE device Bar should be based on PciRegionBase */ - if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { - DEBUG((DEBUG_ERROR, "PCIE Res(TypeMem32) unsupported.\n")); - return EFI_UNSUPPORTED; - } - Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocNode[Index].Base= - RootBridgeInstance->MemBase + - RootBridgeInstance->PciRegionBase; - Ptr->AddrRangeMax =3D 0; - Ptr->AddrTranslationOffset =3D \ - (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; - Ptr->AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; - break; - - case TypePMem32: - // - // Prefetch memory 32 - // - Ptr->Desc =3D 0x8A; - Ptr->Len =3D 0x2B; - Ptr->ResType =3D 0; - Ptr->GenFlag =3D 0; - Ptr->SpecificFlag =3D 6; - Ptr->AddrSpaceGranularity =3D 32; - /* PCIE device Bar should be based on PciRegionBase */ - if (RootBridgeInstance->PciRegionBase > MAX_UINT32) { - DEBUG((DEBUG_ERROR, "PCIE Res(TypePMem32) unsupported.\n")); - return EFI_UNSUPPORTED; - } - Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocNode[Index].Base= - RootBridgeInstance->MemBase + - RootBridgeInstance->PciRegionBase; - Ptr->AddrRangeMax =3D 0; - Ptr->AddrTranslationOffset =3D \ - (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; - Ptr->AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; - break; - - case TypeMem64: - // - // Memory 64 - // - Ptr->Desc =3D 0x8A; - Ptr->Len =3D 0x2B; - Ptr->ResType =3D 0; - Ptr->GenFlag =3D 0; - Ptr->SpecificFlag =3D 0; - Ptr->AddrSpaceGranularity =3D 64; - /* PCIE device Bar should be based on PciRegionBase */ - Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocNode[Index].Base= - RootBridgeInstance->MemBase + - RootBridgeInstance->PciRegionBase; - Ptr->AddrRangeMax =3D 0; - Ptr->AddrTranslationOffset =3D \ - (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; - Ptr->AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; - break; - - case TypePMem64: - // - // Prefetch memory 64 - // - Ptr->Desc =3D 0x8A; - Ptr->Len =3D 0x2B; - Ptr->ResType =3D 0; - Ptr->GenFlag =3D 0; - Ptr->SpecificFlag =3D 6; - Ptr->AddrSpaceGranularity =3D 64; - /* PCIE device Bar should be based on PciRegionBase */ - Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocNode[Index].Base= - RootBridgeInstance->MemBase + - RootBridgeInstance->PciRegionBase; - Ptr->AddrRangeMax =3D 0; - Ptr->AddrTranslationOffset =3D \ - (ResStatus =3D=3D ResAllocated) ? EFI_RESOURCE_SATISFIED : EF= I_RESOURCE_LESS; - Ptr->AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; - break; - }; - PCIE_DEBUG("Ptr->ResType:%d\n", Ptr->ResType); - PCIE_DEBUG("Ptr->Addrlen:%llx\n", Ptr->AddrLen); - PCIE_DEBUG("Ptr->AddrRangeMax:%llx\n", Ptr->AddrRangeMax); - PCIE_DEBUG("Ptr->AddrRangeMin:%llx\n", Ptr->AddrRangeMin); - PCIE_DEBUG("Ptr->SpecificFlag:%llx\n", Ptr->SpecificFlag); - PCIE_DEBUG("Ptr->AddrTranslationOffset:%d\n", Ptr->AddrTranslationOf= fset); - PCIE_DEBUG("Ptr->AddrSpaceGranularity:%d\n", Ptr->AddrSpaceGranulari= ty); - - Temp +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); - } - } - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc =3D 0x79; - ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum =3D 0x0; - - return EFI_SUCCESS; -} -/** - Returns the proposed resource settings for the specified PCI root bridg= e. - - This member function returns the proposed resource settings for the spe= cified PCI root bridge. The - proposed resource settings are prepared when NotifyPhase() is called wi= th a Phase of - EfiPciHostBridgeAllocateResources. The output parameter Configuration - specifies the following: - - The various types of resources, excluding bus resources, that are all= ocated - - The associated lengths in terms of ACPI 2.0 resource descriptor format - - @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOUR= CE_ALLOCATION_PROTOCOL instance. - @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HAND= LE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. - @param[out] Configuration The pointer to the pointer to the PCI I/O= and memory resource descriptor. - - @retval EFI_SUCCESS The requested parameters were returned. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge handle. - @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -GetProposedResources( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ) -{ - LIST_ENTRY *List; - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - UINTN Index; - UINTN Number; - VOID *Buffer; - - Buffer =3D NULL; - Number =3D 0; - - PCIE_DEBUG("In GetProposedResources\n"); - // - // Get the Host Bridge Instance from the resource allocation protocol - // - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List =3D HostBridgeInstance->Head.ForwardLink; - - // - // Enumerate the root bridges in this host bridge - // - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { - for (Index =3D 0; Index < TypeBus; Index ++) { - if (RootBridgeInstance->ResAllocNode[Index].Status !=3D ResNone) { - Number ++; - } - } - - Buffer =3D AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_= DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR)); - if (Buffer =3D=3D NULL) { - return EFI_OUT_OF_RESOURCES; - } - - (VOID)SetResource(RootBridgeInstance,Buffer); - - *Configuration =3D Buffer; - - return EFI_SUCCESS; - } - - List =3D List->ForwardLink; - } - - return EFI_INVALID_PARAMETER; -} - -/** - Provides the hooks from the PCI bus driver to every PCI controller (dev= ice/function) at various - stages of the PCI enumeration process that allow the host bridge driver= to preinitialize individual - PCI controllers before enumeration. - - This function is called during the PCI enumeration process. No specific= action is expected from this - member function. It allows the host bridge driver to preinitialize indi= vidual PCI controllers before - enumeration. - - @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_AL= LOCATION_PROTOCOL instance. - @param RootBridgeHandle The associated PCI root bridge handle. Type EF= I_HANDLE is defined in - InstallProtocolInterface() in the UEFI 2.0 Spe= cification. - @param PciAddress The address of the PCI device on the PCI bus. = This address can be passed to the - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functio= ns to access the PCI - configuration space of the device. See Table 1= 2-1 in the UEFI 2.0 Specification for - the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTO= COL_PCI_ADDRESS. - @param Phase The phase of the PCI device enumeration. - - @retval EFI_SUCCESS The requested parameters were returned. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root b= ridge handle. - @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is def= ined in - EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION= _PHASE. - @retval EFI_DEVICE_ERROR Programming failed due to a hardware e= rror. The PCI enumerator should - not enumerate this device, including i= ts child devices if it is a PCI-to-PCI - bridge. - -**/ -EFI_STATUS -EFIAPI -PreprocessController ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridge= Handle, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, - IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase - ) -{ - PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; - PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; - LIST_ENTRY *List; - - HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); - List =3D HostBridgeInstance->Head.ForwardLink; - - // - // Enumerate the root bridges in this host bridge - // - while (List !=3D &HostBridgeInstance->Head) { - RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); - if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { - break; - } - List =3D List->ForwardLink; - } - if (List =3D=3D &HostBridgeInstance->Head) { - return EFI_INVALID_PARAMETER; - } - - if ((UINT32)Phase > EfiPciBeforeResourceCollection) { - return EFI_INVALID_PARAMETER; - } - - return EFI_SUCCESS; -} diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h b/S= ilicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h deleted file mode 100644 index 435385491a..0000000000 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridge.h +++ /dev/null @@ -1,520 +0,0 @@ -/** - * Copyright (c) 2014, AppliedMicro Corp. All rights reserved. - * Copyright (c) 2016, Hisilicon Limited. All rights reserved. - * Copyright (c) 2016, Linaro Limited. All rights reserved. - * - * This program and the accompanying materials - * are licensed and made available under the terms and conditions of the B= SD License - * which accompanies this distribution. The full text of the license may = be found at - * http://opensource.org/licenses/bsd-license.php - * - * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. - * - **/ - -#ifndef _PCI_HOST_BRIDGE_H_ -#define _PCI_HOST_BRIDGE_H_ - -#include - -#include -#include - -#include -#include -#include -#include -#include -#include - - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -// Enable below statments to enable PCIE debug -//#define PCIE_DEBUG_ENABLE -//#define PCIE_VDEBUG_ENABLE -//#define PCIE_CDEBUG_ENABLE - -#ifdef PCIE_CDEBUG_ENABLE -# define PCIE_CSR_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg)) -#else -# define PCIE_CSR_DEBUG(arg...) -#endif - -#ifdef PCIE_VDEBUG_ENABLE -# define PCIE_VDEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg)) -#else -# define PCIE_VDEBUG(arg...) -#endif - -#ifdef PCIE_DEBUG_ENABLE -# define PCIE_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg)) -#else -# define PCIE_DEBUG(arg...) -#endif -#define PCIE_WARN(arg...) DEBUG((EFI_D_WARN,## arg)) -#define PCIE_ERR(arg...) DEBUG((EFI_D_ERROR,## arg)) -#define PCIE_INFO(arg...) DEBUG((EFI_D_INFO,## arg)) - -#define MAX_PCI_DEVICE_NUMBER 31 -#define MAX_PCI_FUNCTION_NUMBER 7 -#define MAX_PCI_REG_ADDRESS 0xFFFF - -typedef enum { - IoOperation, - MemOperation, - PciOperation -} OPERATION_TYPE; - -#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't') -typedef struct { - UINTN Signature; - EFI_HANDLE HostBridgeHandle; - UINTN RootBridgeNumber; - LIST_ENTRY Head; - BOOLEAN ResourceSubmited; - BOOLEAN CanRestarted; - EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; -} PCI_HOST_BRIDGE_INSTANCE; - -#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \ - CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) - -// -// HostBridge Resource Allocation interface -// - -/** - These are the notifications from the PCI bus driver that it is about to= enter a certain - phase of the PCI enumeration process. - - This member function can be used to notify the host bridge driver to pe= rform specific actions, - including any chipset-specific initialization, so that the chipset is r= eady to enter the next phase. - Eight notification points are defined at this time. See belows: - EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apert= ures and internal data - structures. The PCI enumerator s= hould issue this notification - before starting a fresh enumerat= ion process. Enumeration cannot - be restarted after sending any o= ther notification such as - EfiPciHostBridgeBeginBusAllocati= on. - EfiPciHostBridgeBeginBusAllocation The bus allocation phase is abou= t to begin. No specific action is - required here. This notification= can be used to perform any - chipset-specific programming. - EfiPciHostBridgeEndBusAllocation The bus allocation and bus progr= amming phase is complete. No - specific action is required here= . This notification can be used to - perform any chipset-specific pro= gramming. - EfiPciHostBridgeBeginResourceAllocation - The resource allocation phase is= about to begin. No specific - action is required here. This no= tification can be used to perform - any chipset-specific programming. - EfiPciHostBridgeAllocateResources Allocates resources per previous= ly submitted requests for all the PCI - root bridges. These resource set= tings are returned on the next call to - GetProposedResources(). Before c= alling NotifyPhase() with a Phase of - EfiPciHostBridgeAllocateResource= , the PCI bus enumerator is responsible - for gathering I/O and memory req= uests for - all the PCI root bridges and sub= mitting these requests using - SubmitResources(). This function= pads the resource amount - to suit the root bridge hardware= , takes care of dependencies between - the PCI root bridges, and calls = the Global Coherency Domain (GCD) - with the allocation request. In = the case of padding, the allocated range - could be bigger than what was re= quested. - EfiPciHostBridgeSetResources Programs the host bridge hardwar= e to decode previously allocated - resources (proposed resources) f= or all the PCI root bridges. After the - hardware is programmed, reassign= ing resources will not be supported. - The bus settings are not affecte= d. - EfiPciHostBridgeFreeResources Deallocates resources that were = previously allocated for all the PCI - root bridges and resets the I/O = and memory apertures to their initial - state. The bus settings are not = affected. If the request to allocate - resources fails, the PCI enumera= tor can use this notification to - deallocate previous resources, a= djust the requests, and retry - allocation. - EfiPciHostBridgeEndResourceAllocation The resource allocation phase is= completed. No specific action is - required here. This notification= can be used to perform any chipsetspecific - programming. - - @param[in] This The instance pointer of EFI_PCI_HOST_BRI= DGE_RESOURCE_ALLOCATION_PROTOCOL - @param[in] Phase The phase during enumeration - - @retval EFI_NOT_READY This phase cannot be entered at this tim= e. For example, this error - is valid for a Phase of EfiPciHostBridge= AllocateResources if - SubmitResources() has not been called fo= r one or more - PCI root bridges before this call - @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. This error is valid - for a Phase of EfiPciHostBridgeSetResour= ces. - @retval EFI_INVALID_PARAMETER Invalid phase parameter - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - This error is valid for a Phase of EfiPc= iHostBridgeAllocateResources if the - previously submitted resource requests c= annot be fulfilled or - were only partially fulfilled. - @retval EFI_SUCCESS The notification was accepted without an= y errors. - -**/ -EFI_STATUS -EFIAPI -NotifyPhase( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase - ); - -/** - Return the device handle of the next PCI root bridge that is associated= with this Host Bridge. - - This function is called multiple times to retrieve the device handles o= f all the PCI root bridges that - are associated with this PCI host bridge. Each PCI host bridge is assoc= iated with one or more PCI - root bridges. On each call, the handle that was returned by the previou= s call is passed into the - interface, and on output the interface returns the device handle of the= next PCI root bridge. The - caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BR= IDGE_IO_PROTOCOL - for that root bridge. When there are no more PCI root bridges to report= , the interface returns - EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in = the order that they - are returned by this function. - For D945 implementation, there is only one root bridge in PCI host brid= ge. - - @param[in] This The instance pointer of EFI_PCI_HOST= _BRIDGE_RESOURCE_ALLOCATION_PROTOCOL - @param[in, out] RootBridgeHandle Returns the device handle of the nex= t PCI root bridge. - - @retval EFI_SUCCESS If parameter RootBridgeHandle =3D NULL, = then return the first Rootbridge handle of the - specific Host bridge and return EFI_SUCC= ESS. - @retval EFI_NOT_FOUND Can not find the any more root bridge in= specific host bridge. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE th= at was - returned on a previous call to GetNextRo= otBridge(). -**/ -EFI_STATUS -EFIAPI -GetNextRootBridge( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN OUT EFI_HANDLE *RootBridgeHan= dle - ); - -/** - Returns the allocation attributes of a PCI root bridge. - - The function returns the allocation attributes of a specific PCI root b= ridge. The attributes can vary - from one PCI root bridge to another. These attributes are different fro= m the decode-related - attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Get= Attributes() member function. The - RootBridgeHandle parameter is used to specify the instance of the PCI r= oot bridge. The device - handles of all the root bridges that are associated with this host brid= ge must be obtained by calling - GetNextRootBridge(). The attributes are static in the sense that they d= o not change during or - after the enumeration process. The hardware may provide mechanisms to c= hange the attributes on - the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_= RESOURCE_ALLOCATION_PROTOCOL is - installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCAT= ION_ATTRIBUTES are defined in - "Related Definitions" below. The caller uses these attributes to combin= e multiple resource requests. - For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, t= he PCI bus enumerator needs to - include requests for the prefetchable memory in the nonprefetchable mem= ory pool and not request any - prefetchable memory. - Attribute Description - ------------------------------------ --------------------------= -------------------------------------------- - EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then t= he PCI root bridge does not support separate - windows for nonprefetchabl= e and prefetchable memory. A PCI bus - driver needs to include re= quests for prefetchable memory in the - nonprefetchable memory poo= l. - - EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then t= he PCI root bridge supports 64-bit memory - windows. If this bit is no= t set, the PCI bus driver needs to include - requests for a 64-bit memo= ry address in the corresponding 32-bit - memory pool. - - @param[in] This The instance pointer of EFI_PCI_HOST_BR= IDGE_RESOURCE_ALLOCATION_PROTOCOL - @param[in] RootBridgeHandle The device handle of the PCI root bridg= e in which the caller is interested. Type - EFI_HANDLE is defined in InstallProtoco= lInterface() in the UEFI 2.0 Specification. - @param[out] Attributes The pointer to attribte of root bridge,= it is output parameter - - @retval EFI_INVALID_PARAMETER Attribute pointer is NULL - @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid. - @retval EFI_SUCCESS Success to get attribute of interested = root bridge. - -**/ -EFI_STATUS -EFIAPI -GetAttributes( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT UINT64 *Attributes - ); - -/** - Sets up the specified PCI root bridge for the bus enumeration process. - - This member function sets up the root bridge for bus enumeration and re= turns the PCI bus range - over which the search should be performed in ACPI 2.0 resource descript= or format. - - @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCAT= ION_ PROTOCOL instance. - @param[in] RootBridgeHandle The PCI Root Bridge to be set up. - @param[out] Configuration Pointer to the pointer to the PCI bus re= source descriptor. - - @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle - @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor= tag. - @retval EFI_SUCCESS Sucess to allocate ACPI resource descript= or. - -**/ -EFI_STATUS -EFIAPI -StartBusEnumeration( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ); - -/** - Programs the PCI root bridge hardware so that it decodes the specified = PCI bus range. - - This member function programs the specified PCI root bridge to decode t= he bus range that is - specified by the input parameter Configuration. - The bus range information is specified in terms of the ACPI 2.0 resourc= e descriptor format. - - @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATIO= N_ PROTOCOL instance - @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to = be programmed - @param[in] Configuration The pointer to the PCI bus resource descri= ptor - - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge handle. - @retval EFI_INVALID_PARAMETER Configuration is NULL. - @retval EFI_INVALID_PARAMETER Configuration does not point to a valid = ACPI 2.0 resource descriptor. - @retval EFI_INVALID_PARAMETER Configuration does not include a valid A= CPI 2.0 bus resource descriptor. - @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 re= source descriptors other than - bus descriptors. - @retval EFI_INVALID_PARAMETER Configuration contains one or more inval= id ACPI resource descriptors. - @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for t= his root bridge. - @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for th= is root bridge. - @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. - @retval EFI_SUCCESS The bus range for the PCI root bridge wa= s programmed. - -**/ -EFI_STATUS -EFIAPI -SetBusNumbers( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ); - -/** - Submits the I/O and memory resource requirements for the specified PCI = root bridge. - - This function is used to submit all the I/O and memory resources that a= re required by the specified - PCI root bridge. The input parameter Configuration is used to specify t= he following: - - The various types of resources that are required - - The associated lengths in terms of ACPI 2.0 resource descriptor format - - @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURC= E_ALLOCATION_PROTOCOL instance. - @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory r= esource requirements are being submitted. - @param[in] Configuration The pointer to the PCI I/O and PCI memory = resource descriptor. - - @retval EFI_SUCCESS The I/O and memory resource requests for= a PCI root bridge were accepted. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge handle. - @retval EFI_INVALID_PARAMETER Configuration is NULL. - @retval EFI_INVALID_PARAMETER Configuration does not point to a valid = ACPI 2.0 resource descriptor. - @retval EFI_INVALID_PARAMETER Configuration includes requests for one = or more resource types that are - not supported by this PCI root bridge. T= his error will happen if the caller - did not combine resources according to A= ttributes that were returned by - GetAllocAttributes(). - @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid. - @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for th= is PCI root bridge. - @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid f= or this PCI root bridge. - -**/ -EFI_STATUS -EFIAPI -SubmitResources( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN VOID *Configuration - ); - -/** - Returns the proposed resource settings for the specified PCI root bridg= e. - - This member function returns the proposed resource settings for the spe= cified PCI root bridge. The - proposed resource settings are prepared when NotifyPhase() is called wi= th a Phase of - EfiPciHostBridgeAllocateResources. The output parameter Configuration - specifies the following: - - The various types of resources, excluding bus resources, that are all= ocated - - The associated lengths in terms of ACPI 2.0 resource descriptor format - - @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOUR= CE_ALLOCATION_PROTOCOL instance. - @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HAND= LE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification. - @param[out] Configuration The pointer to the pointer to the PCI I/O= and memory resource descriptor. - - @retval EFI_SUCCESS The requested parameters were returned. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge handle. - @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -GetProposedResources( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - OUT VOID **Configuration - ); - -/** - Provides the hooks from the PCI bus driver to every PCI controller (dev= ice/function) at various - stages of the PCI enumeration process that allow the host bridge driver= to preinitialize individual - PCI controllers before enumeration. - - This function is called during the PCI enumeration process. No specific= action is expected from this - member function. It allows the host bridge driver to preinitialize indi= vidual PCI controllers before - enumeration. - - @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_AL= LOCATION_PROTOCOL instance. - @param RootBridgeHandle The associated PCI root bridge handle. Type EF= I_HANDLE is defined in - InstallProtocolInterface() in the UEFI 2.0 Spe= cification. - @param PciAddress The address of the PCI device on the PCI bus. = This address can be passed to the - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functio= ns to access the PCI - configuration space of the device. See Table 1= 2-1 in the UEFI 2.0 Specification for - the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTO= COL_PCI_ADDRESS. - @param Phase The phase of the PCI device enumeration. - - @retval EFI_SUCCESS The requested parameters were returned. - @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root b= ridge handle. - @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is def= ined in - EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION= _PHASE. - @retval EFI_DEVICE_ERROR Programming failed due to a hardware e= rror. The PCI enumerator should - not enumerate this device, including i= ts child devices if it is a PCI-to-PCI - bridge. - -**/ -EFI_STATUS -EFIAPI -PreprocessController ( - IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, - IN EFI_HANDLE RootBridgeHandle, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, - IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase - ); - - -// -// Define resource status constant -// -#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL -#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL - -// -// Driver Instance Data Prototypes -// - -typedef struct { - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation; - UINTN NumberOfBytes; - UINTN NumberOfPages; - EFI_PHYSICAL_ADDRESS HostAddress; - EFI_PHYSICAL_ADDRESS MappedHostAddress; -} MAP_INFO; - -typedef struct { - ACPI_HID_DEVICE_PATH AcpiDevicePath; - EFI_DEVICE_PATH_PROTOCOL EndDevicePath; -} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; - -typedef enum { - TypeIo =3D 0, - TypeMem32, - TypePMem32, - TypeMem64, - TypePMem64, - TypeBus, - TypeMax -} PCI_RESOURCE_TYPE; - -typedef enum { - ResNone =3D 0, - ResSubmitted, - ResRequested, - ResAllocated, - ResStatusMax -} RES_STATUS; - -typedef struct { - PCI_RESOURCE_TYPE Type; - UINT64 Base; - UINT64 Length; - UINT64 Alignment; - RES_STATUS Status; -} PCI_RES_NODE; - -#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b') - -typedef struct { - UINT32 Signature; - LIST_ENTRY Link; - EFI_HANDLE Handle; - UINT64 RootBridgeAttrib; - UINT64 Attributes; - UINT64 Supports; - - // - // Specific for this memory controller: Bus, I/O, Mem - // - PCI_RES_NODE ResAllocNode[6]; - - // - // Addressing for Memory and I/O and Bus arrange - // - UINT64 BusBase; - UINT64 MemBase; - UINT64 IoBase; - UINT64 BusLimit; - UINT64 MemLimit; - UINT64 IoLimit; - UINT64 RbPciBar; - UINT64 Ecam; - - UINTN PciAddress; - UINTN PciData; - UINTN Port; - UINT32 SocType; - UINT64 CpuMemRegionBase; - UINT64 CpuIoRegionBase; - UINT64 PciRegionBase; - UINT64 PciRegionLimit; - - EFI_DEVICE_PATH_PROTOCOL *DevicePath; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; - -} PCI_ROOT_BRIDGE_INSTANCE; - - -// -// Driver Instance Data Macros -// -#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \ - CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE) - - -#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \ - CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE) - -/** - - Construct the Pci Root Bridge Io protocol - - @param Protocol Point to protocol instance - @param HostBridgeHandle Handle of host bridge - @param Attri Attribute of host bridge - @param ResAppeture ResourceAppeture for host bridge - - @retval EFI_SUCCESS Success to initialize the Pci Root Bridge. - -**/ -EFI_STATUS -RootBridgeConstructor ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, - IN EFI_HANDLE HostBridgeHandle, - IN UINT64 Attri, - IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture, - IN UINT32 Seg - ); - -#endif diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.in= f b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf deleted file mode 100644 index 7f5e1751ec..0000000000 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf +++ /dev/null @@ -1,74 +0,0 @@ -## @file -# -# Component description file PCI Host Bridge driver. -# Copyright (c) 2014, AppliedMicro Corp. All rights reserved. -# Copyright (c) 2016, Hisilicon Limited. All rights reserved. -# Copyright (c) 2016, Linaro Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may = be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D PciHostBridge - FILE_GUID =3D B0E61270-263F-11E3-8224-0800200C9A66 - MODULE_TYPE =3D DXE_DRIVER - VERSION_STRING =3D 1.0 - - ENTRY_POINT =3D InitializePciHostBridge - -[Packages] - MdePkg/MdePkg.dec - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - EmbeddedPkg/EmbeddedPkg.dec - Silicon/Hisilicon/HisiPkg.dec - -[LibraryClasses] - UefiDriverEntryPoint - UefiBootServicesTableLib - MemoryAllocationLib - DxeServicesTableLib - CacheMaintenanceLib - DmaLib - BaseMemoryLib - BaseLib - DebugLib - TimerLib - ArmLib - DevicePathLib - PcdLib - OemMiscLib - -[Sources] - PciHostBridge.c - PciRootBridgeIo.c - PciHostBridge.h - -[Protocols] - gEfiPciHostBridgeResourceAllocationProtocolGuid - gEfiPciRootBridgeIoProtocolGuid - gEfiMetronomeArchProtocolGuid - gEfiDevicePathProtocolGuid - gEmbeddedGpioProtocolGuid - -[depex] - gEfiMetronomeArchProtocolGuid - -[FeaturePcd] - -[Pcd] - -[FixedPcd] - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask - gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P - gHisiTokenSpaceGuid.Pcdsoctype - -[Guids] - gEfiEventExitBootServicesGuid ## PRODUCES ## Event diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b= /Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c deleted file mode 100644 index 3c265ea433..0000000000 --- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c +++ /dev/null @@ -1,2220 +0,0 @@ -/** - * Copyright (c) 2014, AppliedMicro Corp. All rights reserved. - * Copyright (c) 2016, Hisilicon Limited. All rights reserved. - * Copyright (c) 2016, Linaro Limited. All rights reserved. - * - * This program and the accompanying materials - * are licensed and made available under the terms and conditions of the B= SD License - * which accompanies this distribution. The full text of the license may = be found at - * http://opensource.org/licenses/bsd-license.php - * - * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. - * - **/ - -#include "PciHostBridge.h" -#include -#include -#include -#include -#include - - -typedef struct { - EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax]; - EFI_ACPI_END_TAG_DESCRIPTOR EndDesp; -} RESOURCE_CONFIGURATION; - -RESOURCE_CONFIGURATION Configuration =3D { - {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0}, - {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0}, - {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0}, - {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0}, - {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0}, - {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}}, - {0x79, 0} -}; - -// -// Protocol Member Function Prototypes -// - -/** - Polls an address in memory mapped I/O space until an exit condition is = met, or - a timeout occurs. - - This function provides a standard way to poll a PCI memory location. A = PCI memory read - operation is performed at the PCI memory address specified by Address f= or the width specified - by Width. The result of this PCI memory read operation is stored in Res= ult. This PCI memory - read operation is repeated until either a timeout of Delay 100 ns units= has expired, or (Result & - Mask) is equal to Value. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operations. - @param[in] Address The base address of the memory operations. The c= aller is - responsible for aligning Address if required. - @param[in] Mask Mask used for the polling criteria. Bytes above = Width in Mask - are ignored. The bits in the bytes below Width w= hich are zero in - Mask are ignored when polling the memory address. - @param[in] Value The comparison value used for the polling exit c= riteria. - @param[in] Delay The number of 100 ns units to poll. Note that ti= mer available may - be of poorer granularity. - @param[out] Result Pointer to the last value read from the memory l= ocation. - - @retval EFI_SUCCESS The last data returned from the access m= atched the poll exit criteria. - @retval EFI_INVALID_PARAMETER Width is invalid. - @retval EFI_INVALID_PARAMETER Result is NULL. - @retval EFI_TIMEOUT Delay expired before a match occurred. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoPollMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -/** - Reads from the I/O space of a PCI Root Bridge. Returns when either the = polling exit criteria is - satisfied or after a defined duration. - - This function provides a standard way to poll a PCI I/O location. A PCI= I/O read operation is - performed at the PCI I/O address specified by Address for the width spe= cified by Width. - The result of this PCI I/O read operation is stored in Result. This PCI= I/O read operation is - repeated until either a timeout of Delay 100 ns units has expired, or (= Result & Mask) is equal - to Value. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the I/O operations. - @param[in] Address The base address of the I/O operations. The caller= is responsible - for aligning Address if required. - @param[in] Mask Mask used for the polling criteria. Bytes above Wi= dth in Mask - are ignored. The bits in the bytes below Width whi= ch are zero in - Mask are ignored when polling the I/O address. - @param[in] Value The comparison value used for the polling exit cri= teria. - @param[in] Delay The number of 100 ns units to poll. Note that time= r available may - be of poorer granularity. - @param[out] Result Pointer to the last value read from the memory loc= ation. - - @retval EFI_SUCCESS The last data returned from the access m= atched the poll exit criteria. - @retval EFI_INVALID_PARAMETER Width is invalid. - @retval EFI_INVALID_PARAMETER Result is NULL. - @retval EFI_TIMEOUT Delay expired before a match occurred. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoPollIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ); - -/** - Enables a PCI driver to access PCI controller registers in the PCI root= bridge memory space. - - The Mem.Read(), and Mem.Write() functions enable a driver to access PCI= controller - registers in the PCI root bridge memory space. - The memory operations are carried out exactly as requested. The caller = is responsible for satisfying - any alignment and memory width restrictions that a PCI Root Bridge on a= platform might require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operation. - @param[in] Address The base address of the memory operation. The ca= ller is - responsible for aligning the Address if required. - @param[in] Count The number of memory operations to perform. Byte= s moved is - Width size * Count, starting at Address. - @param[out] Buffer For read operations, the destination buffer to s= tore the results. For - write operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - OUT VOID *Buffer - ); - -/** - Enables a PCI driver to access PCI controller registers in the PCI root= bridge memory space. - - The Mem.Read(), and Mem.Write() functions enable a driver to access PCI= controller - registers in the PCI root bridge memory space. - The memory operations are carried out exactly as requested. The caller = is responsible for satisfying - any alignment and memory width restrictions that a PCI Root Bridge on a= platform might require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operation. - @param[in] Address The base address of the memory operation. The ca= ller is - responsible for aligning the Address if required. - @param[in] Count The number of memory operations to perform. Byte= s moved is - Width size * Count, starting at Address. - @param[in] Buffer For read operations, the destination buffer to s= tore the results. For - write operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. -**/ -EFI_STATUS -EFIAPI -RootBridgeIoMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ); - -/** - Enables a PCI driver to access PCI controller registers in the PCI root= bridge I/O space. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOC= OL. - @param[in] Width Signifies the width of the memory operations. - @param[in] UserAddress The base address of the I/O operation. The cal= ler is responsible for - aligning the Address if required. - @param[in] Count The number of I/O operations to perform. Bytes= moved is Width - size * Count, starting at Address. - @param[out] UserBuffer For read operations, the destination buffer to= store the results. For - write operations, the source buffer to write d= ata from. - - @retval EFI_SUCCESS The data was read from or written to t= he PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bri= dge. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due= to a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - OUT VOID *UserBuffer - ); - -/** - Enables a PCI driver to access PCI controller registers in the PCI root= bridge I/O space. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOC= OL. - @param[in] Width Signifies the width of the memory operations. - @param[in] UserAddress The base address of the I/O operation. The cal= ler is responsible for - aligning the Address if required. - @param[in] Count The number of I/O operations to perform. Bytes= moved is Width - size * Count, starting at Address. - @param[in] UserBuffer For read operations, the destination buffer to= store the results. For - write operations, the source buffer to write d= ata from. - - @retval EFI_SUCCESS The data was read from or written to t= he PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bri= dge. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due= to a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 UserAddress, - IN UINTN Count, - IN VOID *UserBuffer - ); - -/** - Enables a PCI driver to copy one region of PCI root bridge memory space= to another region of PCI - root bridge memory space. - - The CopyMem() function enables a PCI driver to copy one region of PCI r= oot bridge memory - space to another region of PCI root bridge memory space. This is especi= ally useful for video scroll - operation on a memory mapped video buffer. - The memory operations are carried out exactly as requested. The caller = is responsible for satisfying - any alignment and memory width restrictions that a PCI root bridge on a= platform might require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL= instance. - @param[in] Width Signifies the width of the memory operations. - @param[in] DestAddress The destination address of the memory operation.= The caller is - responsible for aligning the DestAddress if requ= ired. - @param[in] SrcAddress The source address of the memory operation. The = caller is - responsible for aligning the SrcAddress if requi= red. - @param[in] Count The number of memory operations to perform. Byte= s moved is - Width size * Count, starting at DestAddress and = SrcAddress. - - @retval EFI_SUCCESS The data was copied from one memory re= gion to another memory region. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bri= dge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due= to a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoCopyMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 DestAddress, - IN UINT64 SrcAddress, - IN UINTN Count - ); - -/** - Enables a PCI driver to access PCI controller registers in a PCI root b= ridge's configuration space. - - The Pci.Read() and Pci.Write() functions enable a driver to access PCI = configuration - registers for a PCI controller. - The PCI Configuration operations are carried out exactly as requested. = The caller is responsible for - any alignment and PCI configuration width issues that a PCI Root Bridge= on a platform might - require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operations. - @param[in] Address The address within the PCI configuration space f= or the PCI controller. - @param[in] Count The number of PCI configuration operations to pe= rform. Bytes - moved is Width size * Count, starting at Address. - @param[out] Buffer For read operations, the destination buffer to s= tore the results. For - write operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - OUT VOID *Buffer - ); - -/** - Enables a PCI driver to access PCI controller registers in a PCI root b= ridge's configuration space. - - The Pci.Read() and Pci.Write() functions enable a driver to access PCI = configuration - registers for a PCI controller. - The PCI Configuration operations are carried out exactly as requested. = The caller is responsible for - any alignment and PCI configuration width issues that a PCI Root Bridge= on a platform might - require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operations. - @param[in] Address The address within the PCI configuration space f= or the PCI controller. - @param[in] Count The number of PCI configuration operations to pe= rform. Bytes - moved is Width size * Count, starting at Address. - @param[in] Buffer For read operations, the destination buffer to s= tore the results. For - write operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ); - -/** - Provides the PCI controller-specific addresses required to access syste= m memory from a - DMA bus master. - - The Map() function provides the PCI controller specific addresses neede= d to access system - memory. This function is used to map system memory for PCI bus master D= MA accesses. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_I= O_PROTOCOL. - @param[in] Operation Indicates if the bus master is going t= o read or write to system memory. - @param[in] HostAddress The system memory address to map to th= e PCI controller. - @param[in, out] NumberOfBytes On input the number of bytes to map. O= n output the number of bytes that were mapped. - @param[out] DeviceAddress The resulting map address for the bus = master PCI controller to use - to access the system memory's HostAddr= ess. - @param[out] Mapping The value to pass to Unmap() when the = bus master DMA operation is complete. - - @retval EFI_SUCCESS The range was mapped for the returned Nu= mberOfBytes. - @retval EFI_INVALID_PARAMETER Operation is invalid. - @retval EFI_INVALID_PARAMETER HostAddress is NULL. - @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL. - @retval EFI_INVALID_PARAMETER DeviceAddress is NULL. - @retval EFI_INVALID_PARAMETER Mapping is NULL. - @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a co= mmon buffer. - @retval EFI_DEVICE_ERROR The system hardware could not map the re= quested address. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ); - -/** - Completes the Map() operation and releases any corresponding resources. - - The Unmap() function completes the Map() operation and releases any cor= responding resources. - If the operation was an EfiPciOperationBusMasterWrite or - EfiPciOperationBusMasterWrite64, the data is committed to the target sy= stem memory. - Any resources used for the mapping are freed. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Mapping The mapping value returned from Map(). - - @retval EFI_SUCCESS The range was unmapped. - @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned= by Map(). - @retval EFI_DEVICE_ERROR The data was not committed to the target= system memory. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoUnmap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN VOID *Mapping - ); - -/** - Allocates pages that are suitable for an EfiPciOperationBusMasterCommon= Buffer or - EfiPciOperationBusMasterCommonBuffer64 mapping. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Type This parameter is not used and must be ignored. - @param MemoryType The type of memory to allocate, EfiBootServicesData = or EfiRuntimeServicesData. - @param Pages The number of pages to allocate. - @param HostAddress A pointer to store the base system memory address of= the allocated range. - @param Attributes The requested bit mask of attributes for the allocat= ed range. Only - the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBIN= E, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, - and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used= with this function. - - @retval EFI_SUCCESS The requested memory pages were allocate= d. - @retval EFI_INVALID_PARAMETER MemoryType is invalid. - @retval EFI_INVALID_PARAMETER HostAddress is NULL. - @retval EFI_UNSUPPORTED Attributes is unsupported. The only lega= l attribute bits are - MEMORY_WRITE_COMBINE, MEMORY_CACHED, and= DUAL_ADDRESS_CYCLE. - @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoAllocateBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - OUT VOID **HostAddress, - IN UINT64 Attributes - ); - -/** - Frees memory that was allocated with AllocateBuffer(). - - The FreeBuffer() function frees memory that was allocated with Allocate= Buffer(). - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Pages The number of pages to free. - @param HostAddress The base system memory address of the allocated rang= e. - - @retval EFI_SUCCESS The requested memory pages were freed. - @retval EFI_INVALID_PARAMETER The memory range specified by HostAddres= s and Pages - was not allocated with AllocateBuffer(). - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoFreeBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINTN Pages, - OUT VOID *HostAddress - ); - -/** - Flushes all PCI posted write transactions from a PCI host bridge to sys= tem memory. - - The Flush() function flushes any PCI posted write transactions from a P= CI host bridge to system - memory. Posted write transactions are generated by PCI bus masters when= they perform write - transactions to target addresses in system memory. - This function does not flush posted write transactions from any PCI bri= dges. A PCI controller - specific action must be taken to guarantee that the posted write transa= ctions have been flushed from - the PCI controller and from all the PCI bridges into the PCI host bridg= e. This is typically done with - a PCI read transaction from the PCI controller prior to calling Flush(). - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - - @retval EFI_SUCCESS The PCI posted write transactions were flush= ed from the PCI host - bridge to system memory. - @retval EFI_DEVICE_ERROR The PCI posted write transactions were not f= lushed from the PCI - host bridge due to a hardware error. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoFlush ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This - ); - -/** - Gets the attributes that a PCI root bridge supports setting with SetAtt= ributes(), and the - attributes that a PCI root bridge is currently using. - - The GetAttributes() function returns the mask of attributes that this P= CI root bridge supports - and the mask of attributes that the PCI root bridge is currently using. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Supported A pointer to the mask of attributes that this PCI ro= ot bridge - supports setting with SetAttributes(). - @param Attributes A pointer to the mask of attributes that this PCI ro= ot bridge is - currently using. - - @retval EFI_SUCCESS If Supports is not NULL, then the attrib= utes that the PCI root - bridge supports is returned in Supports.= If Attributes is - not NULL, then the attributes that the P= CI root bridge is currently - using is returned in Attributes. - @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoGetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT UINT64 *Supported, - OUT UINT64 *Attributes - ); - -/** - Sets attributes for a resource range on a PCI root bridge. - - The SetAttributes() function sets the attributes specified in Attribute= s for the PCI root - bridge on the resource range specified by ResourceBase and ResourceLeng= th. Since the - granularity of setting these attributes may vary from resource type to = resource type, and from - platform to platform, the actual resource range and the one passed in b= y the caller may differ. As a - result, this function may set the attributes specified by Attributes on= a larger resource range - than the caller requested. The actual range is returned in ResourceBase= and - ResourceLength. The caller is responsible for verifying that the actual= range for which the - attributes were set is acceptable. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_I= O_PROTOCOL. - @param[in] Attributes The mask of attributes to set. If the = attribute bit - MEMORY_WRITE_COMBINE, MEMORY_CACHED, or - MEMORY_DISABLE is set, then the resour= ce range is specified by - ResourceBase and ResourceLength. If - MEMORY_WRITE_COMBINE, MEMORY_CACHED, a= nd - MEMORY_DISABLE are not set, then Resou= rceBase and - ResourceLength are ignored, and may be= NULL. - @param[in, out] ResourceBase A pointer to the base address of the r= esource range to be modified - by the attributes specified by Attribu= tes. - @param[in, out] ResourceLength A pointer to the length of the resourc= e range to be modified by the - attributes specified by Attributes. - - @retval EFI_SUCCESS The current configuration of this PCI root bri= dge was returned in Resources. - @retval EFI_UNSUPPORTED The current configuration of this PCI root bri= dge could not be retrieved. - @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_I= O_PROTOCOL - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoSetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN OUT UINT64 *ResourceBase, - IN OUT UINT64 *ResourceLength - ); - -/** - Retrieves the current resource settings of this PCI root bridge in the = form of a set of ACPI 2.0 - resource descriptors. - - There are only two resource descriptor types from the ACPI Specificatio= n that may be used to - describe the current resources allocated to a PCI root bridge. These ar= e the QWORD Address - Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.= 0 Section 6.4.2.8). The - QWORD Address Space Descriptor can describe memory, I/O, and bus number= ranges for dynamic - or fixed resources. The configuration of a PCI root bridge is described= with one or more QWORD - Address Space Descriptors followed by an End Tag. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOC= OL. - @param[out] Resources A pointer to the ACPI 2.0 resource descriptors= that describe the - current configuration of this PCI root bridge.= The storage for the - ACPI 2.0 resource descriptors is allocated by = this function. The - caller must treat the return buffer as read-on= ly data, and the buffer - must not be freed by the caller. - - @retval EFI_SUCCESS The current configuration of this PCI root bri= dge was returned in Resources. - @retval EFI_UNSUPPORTED The current configuration of this PCI root bri= dge could not be retrieved. - @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_I= O_PROTOCOL - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoConfiguration ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT VOID **Resources - ); - -// -// Memory Controller Pci Root Bridge Io Module Variables -// -EFI_METRONOME_ARCH_PROTOCOL *mMetronome; - -// -// Lookup table for increment values based on transfer widths -// -UINT8 mInStride[] =3D { - 1, // EfiPciWidthUint8 - 2, // EfiPciWidthUint16 - 4, // EfiPciWidthUint32 - 8, // EfiPciWidthUint64 - 0, // EfiPciWidthFifoUint8 - 0, // EfiPciWidthFifoUint16 - 0, // EfiPciWidthFifoUint32 - 0, // EfiPciWidthFifoUint64 - 1, // EfiPciWidthFillUint8 - 2, // EfiPciWidthFillUint16 - 4, // EfiPciWidthFillUint32 - 8 // EfiPciWidthFillUint64 -}; - -// -// Lookup table for increment values based on transfer widths -// -UINT8 mOutStride[] =3D { - 1, // EfiPciWidthUint8 - 2, // EfiPciWidthUint16 - 4, // EfiPciWidthUint32 - 8, // EfiPciWidthUint64 - 1, // EfiPciWidthFifoUint8 - 2, // EfiPciWidthFifoUint16 - 4, // EfiPciWidthFifoUint32 - 8, // EfiPciWidthFifoUint64 - 0, // EfiPciWidthFillUint8 - 0, // EfiPciWidthFillUint16 - 0, // EfiPciWidthFillUint32 - 0 // EfiPciWidthFillUint64 -}; - - -UINT64 GetPcieCfgAddress ( - UINT64 Ecam, - UINTN Bus, - UINTN Device, - UINTN Function, - UINTN Reg - ) -{ - return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg); -} - - -BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port) -{ - UINT32 Value =3D 0; - - if (0x1610 =3D=3D SocType) - { - Value =3D MmioRead32(RbPciBar + 0x131C); - if ((Value & 0x3F) =3D=3D 0x11) - { - return TRUE; - } - return FALSE; - } - else - { - Value =3D MmioRead32 (0xb0000000 + 0x6818 + 0x100 * Port); - if ((Value & 0x3F) =3D=3D 0x11) - { - return TRUE; - } - return FALSE; - } -} - -/** - - Construct the Pci Root Bridge Io protocol - - @param Protocol Point to protocol instance - @param HostBridgeHandle Handle of host bridge - @param Attri Attribute of host bridge - @param ResAppeture ResourceAppeture for host bridge - - @retval EFI_SUCCESS Success to initialize the Pci Root Bridge. - -**/ -EFI_STATUS -RootBridgeConstructor ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, - IN EFI_HANDLE HostBridgeHandle, - IN UINT64 Attri, - IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture, - IN UINT32 Seg - ) -{ - EFI_STATUS Status; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - PCI_RESOURCE_TYPE Index; - - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol); - - // - // The host to pci bridge, the host memory and io addresses are - // direct mapped to pci addresses, so no need translate, set bases to 0. - // - PrivateData->MemBase =3D ResAppeture->MemBase; - PrivateData->IoBase =3D ResAppeture->IoBase; - PrivateData->RbPciBar =3D ResAppeture->RbPciBar; - PrivateData->MemLimit =3D ResAppeture->MemLimit; - PrivateData->IoLimit =3D ResAppeture->IoLimit; - PrivateData->Ecam =3D ResAppeture->Ecam; - PrivateData->CpuMemRegionBase =3D ResAppeture->CpuMemRegionBase; - PrivateData->CpuIoRegionBase =3D ResAppeture->CpuIoRegionBase; - PrivateData->PciRegionBase =3D ResAppeture->PciRegionBase; - PrivateData->PciRegionLimit =3D ResAppeture->PciRegionLimit; - - // - // Bus Appeture for this Root Bridge (Possible Range) - // - PrivateData->BusBase =3D ResAppeture->BusBase; - PrivateData->BusLimit =3D ResAppeture->BusLimit; - - // - // Specific for this chipset - // - for (Index =3D TypeIo; Index < TypeMax; Index++) { - PrivateData->ResAllocNode[Index].Type =3D Index; - PrivateData->ResAllocNode[Index].Base =3D 0; - PrivateData->ResAllocNode[Index].Length =3D 0; - PrivateData->ResAllocNode[Index].Status =3D ResNone; - } - - PrivateData->RootBridgeAttrib =3D Attri; - - PrivateData->Supports =3D EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_= ATTRIBUTE_IDE_SECONDARY_IO | \ - EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBU= TE_ISA_MOTHERBOARD_IO | \ - EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ - EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIB= UTE_VGA_PALETTE_IO_16 | \ - EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER; - PrivateData->Attributes =3D PrivateData->Supports; - - Protocol->ParentHandle =3D HostBridgeHandle; - - Protocol->PollMem =3D RootBridgeIoPollMem; - Protocol->PollIo =3D RootBridgeIoPollIo; - - Protocol->Mem.Read =3D RootBridgeIoMemRead; - Protocol->Mem.Write =3D RootBridgeIoMemWrite; - - Protocol->Io.Read =3D RootBridgeIoIoRead; - Protocol->Io.Write =3D RootBridgeIoIoWrite; - - Protocol->CopyMem =3D RootBridgeIoCopyMem; - - Protocol->Pci.Read =3D RootBridgeIoPciRead; - Protocol->Pci.Write =3D RootBridgeIoPciWrite; - - Protocol->Map =3D RootBridgeIoMap; - Protocol->Unmap =3D RootBridgeIoUnmap; - - Protocol->AllocateBuffer =3D RootBridgeIoAllocateBuffer; - Protocol->FreeBuffer =3D RootBridgeIoFreeBuffer; - - Protocol->Flush =3D RootBridgeIoFlush; - - Protocol->GetAttributes =3D RootBridgeIoGetAttributes; - Protocol->SetAttributes =3D RootBridgeIoSetAttributes; - - Protocol->Configuration =3D RootBridgeIoConfiguration; - - Protocol->SegmentNumber =3D Seg; - - - Status =3D gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (V= OID **)&mMetronome); - if (EFI_ERROR(Status)) - { - DEBUG((EFI_D_ERROR,"LocateProtocol MetronomeArchProtocol Error\n")); - } - - return EFI_SUCCESS; -} - -/** - Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge = IO. - - The I/O operations are carried out exactly as requested. The caller is r= esponsible - for satisfying any alignment and I/O width restrictions that a PI System= on a - platform might require. For example on some platforms, width requests of - EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, = will - be handled by the driver. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOC= OL. - @param[in] OperationType I/O operation type: IO/MMIO/PCI. - @param[in] Width Signifies the width of the I/O or Memory opera= tion. - @param[in] Address The base address of the I/O operation. - @param[in] Count The number of I/O operations to perform. The n= umber of - bytes moved is Width size * Count, starting at= Address. - @param[in] Buffer For read operations, the destination buffer to= store the results. - For write operations, the source buffer from w= hich to write data. - - @retval EFI_SUCCESS The parameters for this request pass the = checks. - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. - @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, - and Count is not valid for this PI system. - -**/ -EFI_STATUS -RootBridgeIoCheckParameter ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN OPERATION_TYPE OperationType, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr; - UINT64 MaxCount; - UINT64 Base; - UINT64 Limit; - - // - // Check to see if Buffer is NULL - // - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - // - // Check to see if Width is in the valid range - // - if ((UINT32)Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - // - // For FIFO type, the target address won't increase during the access, - // so treat Count as 1 - // - if (Width >=3D EfiPciWidthFifoUint8 && Width <=3D EfiPciWidthFifoUint64)= { - Count =3D 1; - } - - // - // Check to see if Width is in the valid range for I/O Port operations - // - Width =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03); - if ((OperationType !=3D MemOperation) && (Width =3D=3D EfiPciWidthUint64= )) { - ASSERT (FALSE); - return EFI_INVALID_PARAMETER; - } - - // - // Check to see if Address is aligned - // - if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { - return EFI_UNSUPPORTED; - } - - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); - - // - // Check to see if any address associated with this transfer exceeds the= maximum - // allowed address. The maximum address implied by the parameters passe= d in is - // Address + Size * Count. If the following condition is met, then the = transfer - // is not supported. - // - // Address + Size * Count > Limit + 1 - // - // Since Limit can be the maximum integer value supported by the CPU and= Count - // can also be the maximum integer value supported by the CPU, this range - // check must be adjusted to avoid all oveflow conditions. - // - // The following form of the range check is equivalent but assumes that - // Limit is of the form (2^n - 1). - // - if (OperationType =3D=3D IoOperation) { - Base =3D PrivateData->IoBase; - Limit =3D PrivateData->IoLimit; - } else if (OperationType =3D=3D MemOperation) { - Base =3D PrivateData->MemBase; - Limit =3D PrivateData->MemLimit; - } else { - PciRbAddr =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address; - if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateD= ata->BusLimit) { - return EFI_INVALID_PARAMETER; - } - - /* The root complex has only one device / function */ - if (PciRbAddr->Bus =3D=3D PrivateData->BusBase && PciRbAddr->Device != =3D 0) { - return EFI_INVALID_PARAMETER; - } - - /* The other side of the RC has only one device as well */ - if (PciRbAddr->Bus =3D=3D (PrivateData->BusBase + 1 ) && PciRbAddr->De= vice !=3D 0) { - return EFI_INVALID_PARAMETER; - } - - if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function >= MAX_PCI_FUNCTION_NUMBER) { - return EFI_INVALID_PARAMETER; - } - - if (PciRbAddr->ExtendedRegister !=3D 0) { - Address =3D PciRbAddr->ExtendedRegister; - } else { - Address =3D PciRbAddr->Register; - } - Base =3D 0; - Limit =3D MAX_PCI_REG_ADDRESS; - } - - if (Address < Base) { - return EFI_INVALID_PARAMETER; - } - - if (Count =3D=3D 0) { - if (Address > Limit) { - return EFI_UNSUPPORTED; - } - } else { - MaxCount =3D RShiftU64 (Limit, Width); - if (MaxCount < (Count - 1)) { - return EFI_UNSUPPORTED; - } - if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { - return EFI_UNSUPPORTED; - } - } - - return EFI_SUCCESS; -} - -/** - Internal help function for read and write memory space. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROT= OCOL. - @param[in] Write Switch value for Read or Write. - @param[in] Width Signifies the width of the memory operations. - @param[in] UserAddress The address within the PCI configuration spa= ce for the PCI controller. - @param[in] Count The number of PCI configuration operations t= o perform. Bytes - moved is Width size * Count, starting at Add= ress. - @param[in, out] UserBuffer For read operations, the destination buffer = to store the results. For - write operations, the source buffer to write= data from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -RootBridgeIoMemRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN BOOLEAN Write, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - UINT8 InStride; - UINT8 OutStride; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; - UINT8 *Uint8Buffer; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); - /* Address is bus resource */ - Address -=3D PrivateData->PciRegionBase; - Address +=3D PrivateData->CpuMemRegionBase; - - PCIE_DEBUG("RootBridgeIoMemRW Address:0x%llx\n", Address); - PCIE_DEBUG("RootBridgeIoMemRW Count:0x%llx\n", Count); - PCIE_DEBUG("RootBridgeIoMemRW Write:0x%llx\n", Write); - PCIE_DEBUG("RootBridgeIoMemRW Width:0x%llx\n", Width); - - Status =3D RootBridgeIoCheckParameter (This, MemOperation, Width, Addres= s, Count, Buffer); - if (EFI_ERROR (Status)) { - return Status; - } - - InStride =3D mInStride[Width]; - OutStride =3D mOutStride[Width]; - OperationWidth =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03= ); - for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { - if (Write) { - switch (OperationWidth) { - case EfiPciWidthUint8: - MmioWrite8 ((UINTN)Address, *Uint8Buffer); - break; - case EfiPciWidthUint16: - MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); - break; - case EfiPciWidthUint32: - MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); - break; - case EfiPciWidthUint64: - MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); - break; - default: - // - // The RootBridgeIoCheckParameter call above will ensure that th= is - // path is not taken. - // - ASSERT (FALSE); - break; - } - } else { - switch (OperationWidth) { - case EfiPciWidthUint8: - *Uint8Buffer =3D MmioRead8 ((UINTN)Address); - break; - case EfiPciWidthUint16: - *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); - break; - case EfiPciWidthUint32: - *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); - break; - case EfiPciWidthUint64: - *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); - break; - default: - // - // The RootBridgeIoCheckParameter call above will ensure that th= is - // path is not taken. - // - ASSERT (FALSE); - break; - } - } - } - return EFI_SUCCESS; -} - -/** - Internal help function for read and write IO space. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROT= OCOL. - @param[in] Write Switch value for Read or Write. - @param[in] Width Signifies the width of the memory operations. - @param[in] UserAddress The address within the PCI configuration spa= ce for the PCI controller. - @param[in] Count The number of PCI configuration operations t= o perform. Bytes - moved is Width size * Count, starting at Add= ress. - @param[in, out] UserBuffer For read operations, the destination buffer = to store the results. For - write operations, the source buffer to write= data from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -RootBridgeIoIoRW ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN BOOLEAN Write, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN OUT VOID *Buffer - ) -{ - EFI_STATUS Status; - UINT8 InStride; - UINT8 OutStride; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; - UINT8 *Uint8Buffer; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); - /* Address is bus resource */ - Address -=3D PrivateData->IoBase; - Address +=3D PrivateData->CpuIoRegionBase; - - Status =3D RootBridgeIoCheckParameter (This, IoOperation, Width, Address= , Count, Buffer); - if (EFI_ERROR (Status)) { - return Status; - } - - InStride =3D mInStride[Width]; - OutStride =3D mOutStride[Width]; - OperationWidth =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03= ); - - for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { - if (Write) { - switch (OperationWidth) { - case EfiPciWidthUint8: - MmioWrite8 ((UINTN)Address, *Uint8Buffer); - break; - case EfiPciWidthUint16: - MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); - break; - case EfiPciWidthUint32: - MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); - break; - case EfiPciWidthUint64: - MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); - break; - default: - // - // The RootBridgeIoCheckParameter call above will ensure that th= is - // path is not taken. - // - ASSERT (FALSE); - break; - } - } else { - switch (OperationWidth) { - case EfiPciWidthUint8: - *Uint8Buffer =3D MmioRead8 ((UINTN)Address); - break; - case EfiPciWidthUint16: - *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); - break; - case EfiPciWidthUint32: - *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); - break; - case EfiPciWidthUint64: - *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); - break; - default: - // - // The RootBridgeIoCheckParameter call above will ensure that th= is - // path is not taken. - // - ASSERT (FALSE); - break; - } - } - } - return EFI_SUCCESS; -} - - -/** - Polls an address in memory mapped I/O space until an exit condition is = met, or - a timeout occurs. - - This function provides a standard way to poll a PCI memory location. A = PCI memory read - operation is performed at the PCI memory address specified by Address f= or the width specified - by Width. The result of this PCI memory read operation is stored in Res= ult. This PCI memory - read operation is repeated until either a timeout of Delay 100 ns units= has expired, or (Result & - Mask) is equal to Value. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operations. - @param[in] Address The base address of the memory operations. The c= aller is - responsible for aligning Address if required. - @param[in] Mask Mask used for the polling criteria. Bytes above = Width in Mask - are ignored. The bits in the bytes below Width w= hich are zero in - Mask are ignored when polling the memory address. - @param[in] Value The comparison value used for the polling exit c= riteria. - @param[in] Delay The number of 100 ns units to poll. Note that ti= mer available may - be of poorer granularity. - @param[out] Result Pointer to the last value read from the memory l= ocation. - - @retval EFI_SUCCESS The last data returned from the access m= atched the poll exit criteria. - @retval EFI_INVALID_PARAMETER Width is invalid. - @retval EFI_INVALID_PARAMETER Result is NULL. - @retval EFI_TIMEOUT Delay expired before a match occurred. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoPollMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - EFI_STATUS Status; - UINT64 NumberOfTicks; - UINT32 Remainder; - - if (Result =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - // - // No matter what, always do a single poll. - // - Status =3D This->Mem.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - if ((*Result & Mask) =3D=3D Value) { - return EFI_SUCCESS; - } - - if (Delay =3D=3D 0) { - return EFI_TIMEOUT; - - } else { - - // - // Determine the proper # of metronome ticks to wait for polling the - // location. The nuber of ticks is Roundup (Delay / mMetronome->TickP= eriod)+1 - // The "+1" to account for the possibility of the first tick being sho= rt - // because we started in the middle of a tick. - // - // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metrono= me - // protocol definition is updated. - // - NumberOfTicks =3D DivU64x32Remainder (Delay, (UINT32) mMetronome->Tick= Period, &Remainder); - if (Remainder !=3D 0) { - NumberOfTicks +=3D 1; - } - NumberOfTicks +=3D 1; - - while (NumberOfTicks !=3D 0) { - - mMetronome->WaitForTick (mMetronome, 1); - - Status =3D This->Mem.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - - if ((*Result & Mask) =3D=3D Value) { - return EFI_SUCCESS; - } - - NumberOfTicks -=3D 1; - } - } - return EFI_TIMEOUT; -} - -/** - Reads from the I/O space of a PCI Root Bridge. Returns when either the = polling exit criteria is - satisfied or after a defined duration. - - This function provides a standard way to poll a PCI I/O location. A PCI= I/O read operation is - performed at the PCI I/O address specified by Address for the width spe= cified by Width. - The result of this PCI I/O read operation is stored in Result. This PCI= I/O read operation is - repeated until either a timeout of Delay 100 ns units has expired, or (= Result & Mask) is equal - to Value. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the I/O operations. - @param[in] Address The base address of the I/O operations. The caller= is responsible - for aligning Address if required. - @param[in] Mask Mask used for the polling criteria. Bytes above Wi= dth in Mask - are ignored. The bits in the bytes below Width whi= ch are zero in - Mask are ignored when polling the I/O address. - @param[in] Value The comparison value used for the polling exit cri= teria. - @param[in] Delay The number of 100 ns units to poll. Note that time= r available may - be of poorer granularity. - @param[out] Result Pointer to the last value read from the memory loc= ation. - - @retval EFI_SUCCESS The last data returned from the access m= atched the poll exit criteria. - @retval EFI_INVALID_PARAMETER Width is invalid. - @retval EFI_INVALID_PARAMETER Result is NULL. - @retval EFI_TIMEOUT Delay expired before a match occurred. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoPollIo ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINT64 Mask, - IN UINT64 Value, - IN UINT64 Delay, - OUT UINT64 *Result - ) -{ - EFI_STATUS Status; - UINT64 NumberOfTicks; - UINT32 Remainder; - - // - // No matter what, always do a single poll. - // - - if (Result =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - Status =3D This->Io.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - if ((*Result & Mask) =3D=3D Value) { - return EFI_SUCCESS; - } - - if (Delay =3D=3D 0) { - return EFI_SUCCESS; - - } else { - - // - // Determine the proper # of metronome ticks to wait for polling the - // location. The number of ticks is Roundup (Delay / mMetronome->Tick= Period)+1 - // The "+1" to account for the possibility of the first tick being sho= rt - // because we started in the middle of a tick. - // - NumberOfTicks =3D DivU64x32Remainder (Delay, (UINT32)mMetronome->TickP= eriod, &Remainder); - if (Remainder !=3D 0) { - NumberOfTicks +=3D 1; - } - NumberOfTicks +=3D 1; - - while (NumberOfTicks !=3D 0) { - - mMetronome->WaitForTick (mMetronome, 1); - - Status =3D This->Io.Read (This, Width, Address, 1, Result); - if (EFI_ERROR (Status)) { - return Status; - } - - if ((*Result & Mask) =3D=3D Value) { - return EFI_SUCCESS; - } - - NumberOfTicks -=3D 1; - } - } - return EFI_TIMEOUT; -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root= bridge memory space. - - The Mem.Read(), and Mem.Write() functions enable a driver to access PCI= controller - registers in the PCI root bridge memory space. - The memory operations are carried out exactly as requested. The caller = is responsible for satisfying - any alignment and memory width restrictions that a PCI Root Bridge on a= platform might require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operation. - @param[in] Address The base address of the memory operation. The ca= ller is - responsible for aligning the Address if required. - @param[in] Count The number of memory operations to perform. Byte= s moved is - Width size * Count, starting at Address. - @param[out] Buffer For read operations, the destination buffer to s= tore the results. For - write operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoMemRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - OUT VOID *Buffer - ) -{ - return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer); -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root= bridge memory space. - - The Mem.Read(), and Mem.Write() functions enable a driver to access PCI= controller - registers in the PCI root bridge memory space. - The memory operations are carried out exactly as requested. The caller = is responsible for satisfying - any alignment and memory width restrictions that a PCI Root Bridge on a= platform might require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operation. - @param[in] Address The base address of the memory operation. The ca= ller is - responsible for aligning the Address if required. - @param[in] Count The number of memory operations to perform. Byte= s moved is - Width size * Count, starting at Address. - @param[in] Buffer For read operations, the destination buffer to s= tore the results. For - write operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. -**/ -EFI_STATUS -EFIAPI -RootBridgeIoMemWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ) -{ - return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer); -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root= bridge I/O space. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOC= OL. - @param[in] Width Signifies the width of the memory operations. - @param[in] Address The base address of the I/O operation. The cal= ler is responsible for - aligning the Address if required. - @param[in] Count The number of I/O operations to perform. Bytes= moved is Width - size * Count, starting at Address. - @param[out] Buffer For read operations, the destination buffer to= store the results. For - write operations, the source buffer to write d= ata from. - - @retval EFI_SUCCESS The data was read from or written to t= he PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bri= dge. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due= to a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoIoRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - OUT VOID *Buffer - ) -{ - return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer); -} - -/** - Enables a PCI driver to access PCI controller registers in the PCI root= bridge I/O space. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOC= OL. - @param[in] Width Signifies the width of the memory operations. - @param[in] Address The base address of the I/O operation. The cal= ler is responsible for - aligning the Address if required. - @param[in] Count The number of I/O operations to perform. Bytes= moved is Width - size * Count, starting at Address. - @param[in] Buffer For read operations, the destination buffer t= o store the results. For - write operations, the source buffer to write d= ata from. - - @retval EFI_SUCCESS The data was read from or written to t= he PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bri= dge. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due= to a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoIoWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ) -{ - return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer); -} - -/** - Enables a PCI driver to copy one region of PCI root bridge memory space= to another region of PCI - root bridge memory space. - - The CopyMem() function enables a PCI driver to copy one region of PCI r= oot bridge memory - space to another region of PCI root bridge memory space. This is especi= ally useful for video scroll - operation on a memory mapped video buffer. - The memory operations are carried out exactly as requested. The caller = is responsible for satisfying - any alignment and memory width restrictions that a PCI root bridge on a= platform might require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL= instance. - @param[in] Width Signifies the width of the memory operations. - @param[in] DestAddress The destination address of the memory operation.= The caller is - responsible for aligning the DestAddress if requ= ired. - @param[in] SrcAddress The source address of the memory operation. The = caller is - responsible for aligning the SrcAddress if requi= red. - @param[in] Count The number of memory operations to perform. Byte= s moved is - Width size * Count, starting at DestAddress and = SrcAddress. - - @retval EFI_SUCCESS The data was copied from one memory re= gion to another memory region. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bri= dge. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due= to a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoCopyMem ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 DestAddress, - IN UINT64 SrcAddress, - IN UINTN Count - ) -{ - EFI_STATUS Status; - BOOLEAN Direction; - UINTN Stride; - UINTN Index; - UINT64 Result; - - if ((UINT32)Width > EfiPciWidthUint64) { - return EFI_INVALID_PARAMETER; - } - - if (DestAddress =3D=3D SrcAddress) { - return EFI_SUCCESS; - } - - Stride =3D (UINTN)((UINTN)1 << Width); - - Direction =3D TRUE; - if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * S= tride))) { - Direction =3D FALSE; - SrcAddress =3D SrcAddress + (Count-1) * Stride; - DestAddress =3D DestAddress + (Count-1) * Stride; - } - - for (Index =3D 0;Index < Count;Index++) { - Status =3D RootBridgeIoMemRead ( - This, - Width, - SrcAddress, - 1, - &Result - ); - if (EFI_ERROR (Status)) { - return Status; - } - Status =3D RootBridgeIoMemWrite ( - This, - Width, - DestAddress, - 1, - &Result - ); - if (EFI_ERROR (Status)) { - return Status; - } - if (Direction) { - SrcAddress +=3D Stride; - DestAddress +=3D Stride; - } else { - SrcAddress -=3D Stride; - DestAddress -=3D Stride; - } - } - return EFI_SUCCESS; -} - -/** - Reads memory-mapped registers. - @param[in] Width Signifies the width of the I/O or Memory operation. - @param[in] Address The base address of the I/O operation. - @param[in] Count The number of I/O operations to perform. The number= of - bytes moved is Width size * Count, starting at Addr= ess. - @param[out] Buffer For read operations, the destination buffer to stor= e the results. - For write operations, the source buffer from which = to write data. - - @retval EFI_SUCCESS The data was read from or written to the = PI system. - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. - @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, - and Count is not valid for this PI system. - -**/ -EFI_STATUS -CpuMemoryServiceRead ( - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - OUT VOID *Buffer - ) -{ - - UINT8 InStride; - UINT8 OutStride; - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; - UINT8 *Uint8Buffer; - UINT32 Uint32Buffer =3D 0; - - // - // Select loop based on the width of the transfer - // - InStride =3D mInStride[Width]; - OutStride =3D mOutStride[Width]; - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); - for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { - if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { - Uint32Buffer =3D MmioRead32((UINTN)(Address & (~0x3))); - Uint32Buffer &=3D (0xFF << ((Address & 0x3) * 8)); - *((UINT8*)Uint8Buffer) =3D (UINT8)(Uint32Buffer >> (((Address & 0x3)= * 8))); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { - if (((Address & 0x3) =3D=3D 1) || ((Address & 0x3) =3D=3D 3)) { - return EFI_INVALID_PARAMETER; - } - Uint32Buffer =3D MmioRead32((UINTN)(Address & (~0x3))); - Uint32Buffer &=3D (0xFFFF << ((Address & 0x3) * 8)); - *(UINT16 *)Uint8Buffer =3D (UINT16)(Uint32Buffer >> (((Address & 0x3= ) * 8))); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { - *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { - *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); - } - } - return EFI_SUCCESS; -} - -/** - Enables a PCI driver to access PCI controller registers in a PCI root b= ridge's configuration space. - - The Pci.Read() and Pci.Write() functions enable a driver to access PCI = configuration - registers for a PCI controller. - The PCI Configuration operations are carried out exactly as requested. = The caller is responsible for - any alignment and PCI configuration width issues that a PCI Root Bridge= on a platform might - require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operations. - @param[in] Address The address within the PCI configuration space f= or the PCI controller. - @param[in] Count The number of PCI configuration operations to pe= rform. Bytes - moved is Width size * Count, starting at Address. - @param[out] Buffer For read operations, the destination buffer to s= tore the results. For - write operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoPciRead ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 EfiAddress, - IN UINTN Count, - OUT VOID *Buffer - ) -{ - UINT32 Offset; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress; - UINT64 Address; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - - EfiPciAddress =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAd= dress; - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (EfiPciAddress->ExtendedRegister) { - Offset =3D EfiPciAddress->ExtendedRegister; - } else { - Offset =3D EfiPciAddress->Register; - } - - PCIE_DEBUG ("[%a:%d] - bus %x dev %x func %x Off %x\n", __FUNCTION__, __= LINE__, - EfiPciAddress->Bus, - EfiPciAddress->Device, - EfiPciAddress->Function, - Offset - ); - if (EfiPciAddress->Bus < PrivateData->BusBase || EfiPciAddress->Bus > Pr= ivateData->BusLimit) { - PCIE_DEBUG ("[%a:%d] - Bus number out of range %d\n", __FUNCTION__, __= LINE__, EfiPciAddress->Bus); - SetMem (Buffer, mOutStride[Width] * Count, 0xFF); - return EFI_INVALID_PARAMETER; - } - - // The UEFI PCI enumerator scans for devices at all possible addresses, - // and ignores some PCI rules - this results in some hardware being - // detected multiple times. We work around this by faking absent - // devices - if(EfiPciAddress->Bus =3D=3D PrivateData->BusBase) - { - if((EfiPciAddress->Device !=3D 0x0) || (EfiPciAddress->Function !=3D 0= )) { - SetMem (Buffer, mOutStride[Width] * Count, 0xFF); - return EFI_UNSUPPORTED; - } - } - - if (EfiPciAddress->Bus =3D=3D PrivateData->BusBase){ - Address =3D PrivateData->RbPciBar + Offset; - } - else if(EfiPciAddress->Bus =3D=3D PrivateData->BusBase + 1) - { - if (!PcieIsLinkUp(PrivateData->SocType,PrivateData->RbPciBar, PrivateD= ata->Port)) - { - SetMem (Buffer, mOutStride[Width] * Count, 0xFF); - return EFI_NOT_READY; - } - Address =3D GetPcieCfgAddress ( - PrivateData->Ecam, - EfiPciAddress->Bus, - EfiPciAddress->Device, - EfiPciAddress->Function, - Offset - ); - } - else - { - Address =3D GetPcieCfgAddress ( - PrivateData->Ecam, - EfiPciAddress->Bus, - EfiPciAddress->Device, - EfiPciAddress->Function, - Offset - ); - } - - (VOID)CpuMemoryServiceRead((EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Co= unt, Buffer); - PCIE_DEBUG ("[%a:%d] - %x\n", __FUNCTION__, __LINE__, *(UINT32 *)Buffer); - - return EFI_SUCCESS; -} - -/** - Writes memory-mapped registers. - @param[in] Width Signifies the width of the I/O or Memory operation. - @param[in] Address The base address of the I/O operation. - @param[in] Count The number of I/O operations to perform. The number= of - bytes moved is Width size * Count, starting at Addr= ess. - @param[in] Buffer For read operations, the destination buffer to stor= e the results. - For write operations, the source buffer from which = to write data. - - @retval EFI_SUCCESS The data was read from or written to the = PI system. - @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. - @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, - and Count is not valid for this PI system. - -**/ -EFI_STATUS -CpuMemoryServiceWrite ( - IN EFI_CPU_IO_PROTOCOL_WIDTH Width, - IN UINT64 Address, - IN UINTN Count, - IN VOID *Buffer - ) -{ - UINT8 InStride; - UINT8 OutStride; - EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth; - UINT8 *Uint8Buffer; - UINT32 Uint32Buffer; - - // - // Select loop based on the width of the transfer - // - InStride =3D mInStride[Width]; - OutStride =3D mOutStride[Width]; - OperationWidth =3D (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03); - for (Uint8Buffer =3D Buffer; Count > 0; Address +=3D InStride, Uint8Buff= er +=3D OutStride, Count--) { - if (OperationWidth =3D=3D EfiCpuIoWidthUint8) { - Uint32Buffer =3D MmioRead32 ((UINTN)(Address & (~0x03))); - Uint32Buffer &=3D ~(UINT32)(0xFF << ((Address & 0x3) * 8)); - Uint32Buffer |=3D (UINT32)(*(UINT8 *)Uint8Buffer) << ((Address & 0x3= ) * 8); - MmioWrite32 ((UINTN)(Address & (~0x03)), Uint32Buffer); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint16) { - if (((Address & 0x3) =3D=3D 1) || ((Address & 0x3) =3D=3D 3)) { - return EFI_INVALID_PARAMETER; - } - Uint32Buffer =3D MmioRead32 ((UINTN)(Address & (~0x03))); - Uint32Buffer &=3D ~(UINT32)(0xFFFF << ((Address & 0x3) * 8)); - Uint32Buffer |=3D (UINT32)(*(UINT16 *)Uint8Buffer) << ((Address & 0x= 3) * 8); - MmioWrite32 ((UINTN)(Address & (~0x03)), Uint32Buffer); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint32) { - MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); - } else if (OperationWidth =3D=3D EfiCpuIoWidthUint64) { - MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); - } - } - return EFI_SUCCESS; -} - -/** - Enables a PCI driver to access PCI controller registers in a PCI root b= ridge's configuration space. - - The Pci.Read() and Pci.Write() functions enable a driver to access PCI = configuration - registers for a PCI controller. - The PCI Configuration operations are carried out exactly as requested. = The caller is responsible for - any alignment and PCI configuration width issues that a PCI Root Bridge= on a platform might - require. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Width Signifies the width of the memory operations. - @param[in] Address The address within the PCI configuration space f= or the PCI controller. - @param[in] Count The number of PCI configuration operations to pe= rform. Bytes - moved is Width size * Count, starting at Address. - @param[in] Buffer For read operations, the destination buffer to s= tore the results. For - write operations, the source buffer to write dat= a from. - - @retval EFI_SUCCESS The data was read from or written to the= PCI root bridge. - @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridg= e. - @retval EFI_INVALID_PARAMETER Buffer is NULL. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoPciWrite ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, - IN UINT64 EfiAddress, - IN UINTN Count, - IN VOID *Buffer - ) -{ - UINT32 Offset; - EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress; - UINT64 Address; - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - - EfiPciAddress =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAd= dress; - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - if (Buffer =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - if (Width >=3D EfiPciWidthMaximum) { - return EFI_INVALID_PARAMETER; - } - - if (EfiPciAddress->ExtendedRegister) - Offset =3D EfiPciAddress->ExtendedRegister; - else - Offset =3D EfiPciAddress->Register; - - PCIE_DEBUG ("[%a:%d] - bus %x dev %x func %x Off %x\n", __FUNCTION__, __= LINE__, - EfiPciAddress->Bus, - EfiPciAddress->Device, - EfiPciAddress->Function, - Offset - ); - if (((EfiPciAddress->Bus =3D=3D PrivateData->BusBase) && (EfiPciAddress-= >Device =3D=3D 0x00) && (EfiPciAddress->Function =3D=3D 0))){ - Address =3D PrivateData->RbPciBar + Offset; - if ((Offset =3D=3D 0x14) || (Offset =3D=3D 0x10)) { - return EFI_SUCCESS; - } - } - else if (EfiPciAddress->Bus =3D=3D PrivateData->BusBase + 1) - { - if (!PcieIsLinkUp(PrivateData->SocType,PrivateData->RbPciBar, Private= Data->Port)) { - return EFI_NOT_READY; - } - Address =3D GetPcieCfgAddress ( - PrivateData->Ecam, - EfiPciAddress->Bus, - EfiPciAddress->Device, - EfiPciAddress->Function, - Offset - ); - } - else - { - Address =3D GetPcieCfgAddress ( - PrivateData->Ecam, - EfiPciAddress->Bus, - EfiPciAddress->Device, - EfiPciAddress->Function, - Offset - ); - } - - (VOID)CpuMemoryServiceWrite ((EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, = Count, Buffer); - PCIE_DEBUG ("[%a:%d] - 0x%08x\n", __FUNCTION__, __LINE__, *(UINT32 *)Buf= fer); - return EFI_SUCCESS; -} - -/** - Provides the PCI controller-specific addresses required to access syste= m memory from a - DMA bus master. - - The Map() function provides the PCI controller specific addresses neede= d to access system - memory. This function is used to map system memory for PCI bus master D= MA accesses. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_I= O_PROTOCOL. - @param[in] Operation Indicates if the bus master is going t= o read or write to system memory. - @param[in] HostAddress The system memory address to map to th= e PCI controller. - @param[in, out] NumberOfBytes On input the number of bytes to map. O= n output the number of bytes that were mapped. - @param[out] DeviceAddress The resulting map address for the bus = master PCI controller to use - to access the system memory's HostAddr= ess. - @param[out] Mapping The value to pass to Unmap() when the = bus master DMA operation is complete. - - @retval EFI_SUCCESS The range was mapped for the returned Nu= mberOfBytes. - @retval EFI_INVALID_PARAMETER Operation is invalid. - @retval EFI_INVALID_PARAMETER HostAddress is NULL. - @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL. - @retval EFI_INVALID_PARAMETER DeviceAddress is NULL. - @retval EFI_INVALID_PARAMETER Mapping is NULL. - @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a co= mmon buffer. - @retval EFI_DEVICE_ERROR The system hardware could not map the re= quested address. - @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a lack of resources. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoMap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, - IN VOID *HostAddress, - IN OUT UINTN *NumberOfBytes, - OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, - OUT VOID **Mapping - ) -{ - DMA_MAP_OPERATION DmaOperation; - - if (Operation =3D=3D EfiPciOperationBusMasterRead) { - DmaOperation =3D MapOperationBusMasterRead; - } else if (Operation =3D=3D EfiPciOperationBusMasterWrite) { - DmaOperation =3D MapOperationBusMasterWrite; - } else if (Operation =3D=3D EfiPciOperationBusMasterCommonBuffer) { - DmaOperation =3D MapOperationBusMasterCommonBuffer; - } else if (Operation =3D=3D EfiPciOperationBusMasterRead64) { - DmaOperation =3D MapOperationBusMasterRead; - } else if (Operation =3D=3D EfiPciOperationBusMasterWrite64) { - DmaOperation =3D MapOperationBusMasterWrite; - } else if (Operation =3D=3D EfiPciOperationBusMasterCommonBuffer64) { - DmaOperation =3D MapOperationBusMasterCommonBuffer; - } else { - return EFI_INVALID_PARAMETER; - } - (VOID)DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, M= apping); - return EFI_SUCCESS; -} - -/** - Completes the Map() operation and releases any corresponding resources. - - The Unmap() function completes the Map() operation and releases any cor= responding resources. - If the operation was an EfiPciOperationBusMasterWrite or - EfiPciOperationBusMasterWrite64, the data is committed to the target sy= stem memory. - Any resources used for the mapping are freed. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param[in] Mapping The mapping value returned from Map(). - - @retval EFI_SUCCESS The range was unmapped. - @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned= by Map(). - @retval EFI_DEVICE_ERROR The data was not committed to the target= system memory. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoUnmap ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN VOID *Mapping - ) -{ - return DmaUnmap (Mapping); -} - -/** - Allocates pages that are suitable for an EfiPciOperationBusMasterCommon= Buffer or - EfiPciOperationBusMasterCommonBuffer64 mapping. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Type This parameter is not used and must be ignored. - @param MemoryType The type of memory to allocate, EfiBootServicesData = or EfiRuntimeServicesData. - @param Pages The number of pages to allocate. - @param HostAddress A pointer to store the base system memory address of= the allocated range. - @param Attributes The requested bit mask of attributes for the allocat= ed range. Only - the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBIN= E, EFI_PCI_ATTRIBUTE_MEMORY_CACHED, - and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used= with this function. - - @retval EFI_SUCCESS The requested memory pages were allocate= d. - @retval EFI_INVALID_PARAMETER MemoryType is invalid. - @retval EFI_INVALID_PARAMETER HostAddress is NULL. - @retval EFI_UNSUPPORTED Attributes is unsupported. The only lega= l attribute bits are - MEMORY_WRITE_COMBINE, MEMORY_CACHED, and= DUAL_ADDRESS_CYCLE. - @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoAllocateBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN EFI_ALLOCATE_TYPE Type, - IN EFI_MEMORY_TYPE MemoryType, - IN UINTN Pages, - OUT VOID **HostAddress, - IN UINT64 Attributes - ) -{ - if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) { - return EFI_UNSUPPORTED; - } - - return DmaAllocateBuffer (MemoryType, Pages, HostAddress); - -} - -/** - Frees memory that was allocated with AllocateBuffer(). - - The FreeBuffer() function frees memory that was allocated with Allocate= Buffer(). - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Pages The number of pages to free. - @param HostAddress The base system memory address of the allocated rang= e. - - @retval EFI_SUCCESS The requested memory pages were freed. - @retval EFI_INVALID_PARAMETER The memory range specified by HostAddres= s and Pages - was not allocated with AllocateBuffer(). - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoFreeBuffer ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINTN Pages, - OUT VOID *HostAddress - ) -{ - return DmaFreeBuffer (Pages, HostAddress); -} - -/** - Flushes all PCI posted write transactions from a PCI host bridge to sys= tem memory. - - The Flush() function flushes any PCI posted write transactions from a P= CI host bridge to system - memory. Posted write transactions are generated by PCI bus masters when= they perform write - transactions to target addresses in system memory. - This function does not flush posted write transactions from any PCI bri= dges. A PCI controller - specific action must be taken to guarantee that the posted write transa= ctions have been flushed from - the PCI controller and from all the PCI bridges into the PCI host bridg= e. This is typically done with - a PCI read transaction from the PCI controller prior to calling Flush(). - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - - @retval EFI_SUCCESS The PCI posted write transactions were flush= ed from the PCI host - bridge to system memory. - @retval EFI_DEVICE_ERROR The PCI posted write transactions were not f= lushed from the PCI - host bridge due to a hardware error. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoFlush ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This - ) -{ - // - // not supported yet - // - return EFI_SUCCESS; -} - -/** - Gets the attributes that a PCI root bridge supports setting with SetAtt= ributes(), and the - attributes that a PCI root bridge is currently using. - - The GetAttributes() function returns the mask of attributes that this P= CI root bridge supports - and the mask of attributes that the PCI root bridge is currently using. - - @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. - @param Supported A pointer to the mask of attributes that this PCI ro= ot bridge - supports setting with SetAttributes(). - @param Attributes A pointer to the mask of attributes that this PCI ro= ot bridge is - currently using. - - @retval EFI_SUCCESS If Supports is not NULL, then the attrib= utes that the PCI root - bridge supports is returned in Supports.= If Attributes is - not NULL, then the attributes that the P= CI root bridge is currently - using is returned in Attributes. - @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoGetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT UINT64 *Supported, - OUT UINT64 *Attributes - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - if (Attributes =3D=3D NULL && Supported =3D=3D NULL) { - return EFI_INVALID_PARAMETER; - } - - // - // Set the return value for Supported and Attributes - // - if (Supported !=3D NULL) { - *Supported =3D PrivateData->Supports; - } - - if (Attributes !=3D NULL) { - *Attributes =3D PrivateData->Attributes; - } - - return EFI_SUCCESS; -} - -/** - Sets attributes for a resource range on a PCI root bridge. - - The SetAttributes() function sets the attributes specified in Attribute= s for the PCI root - bridge on the resource range specified by ResourceBase and ResourceLeng= th. Since the - granularity of setting these attributes may vary from resource type to = resource type, and from - platform to platform, the actual resource range and the one passed in b= y the caller may differ. As a - result, this function may set the attributes specified by Attributes on= a larger resource range - than the caller requested. The actual range is returned in ResourceBase= and - ResourceLength. The caller is responsible for verifying that the actual= range for which the - attributes were set is acceptable. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_I= O_PROTOCOL. - @param[in] Attributes The mask of attributes to set. If the = attribute bit - MEMORY_WRITE_COMBINE, MEMORY_CACHED, or - MEMORY_DISABLE is set, then the resour= ce range is specified by - ResourceBase and ResourceLength. If - MEMORY_WRITE_COMBINE, MEMORY_CACHED, a= nd - MEMORY_DISABLE are not set, then Resou= rceBase and - ResourceLength are ignored, and may be= NULL. - @param[in, out] ResourceBase A pointer to the base address of the r= esource range to be modified - by the attributes specified by Attribu= tes. - @param[in, out] ResourceLength A pointer to the length of the resourc= e range to be modified by the - attributes specified by Attributes. - - @retval EFI_SUCCESS The current configuration of this PCI root bri= dge was returned in Resources. - @retval EFI_UNSUPPORTED The current configuration of this PCI root bri= dge could not be retrieved. - @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_I= O_PROTOCOL - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoSetAttributes ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - IN UINT64 Attributes, - IN OUT UINT64 *ResourceBase, - IN OUT UINT64 *ResourceLength - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This); - - if (Attributes !=3D 0) { - if ((Attributes & (~(PrivateData->Supports))) !=3D 0) { - return EFI_UNSUPPORTED; - } - } - - // - // This is a generic driver for a PC-AT class system. It does not have = any - // chipset specific knowlegde, so none of the attributes can be set or - // cleared. Any attempt to set attribute that are already set will succ= eed, - // and any attempt to set an attribute that is not supported will fail. - // - if (Attributes & (~PrivateData->Attributes)) { - /* FIXME: */ - return EFI_UNSUPPORTED; - } - - return EFI_SUCCESS; -} - -/** - Retrieves the current resource settings of this PCI root bridge in the = form of a set of ACPI 2.0 - resource descriptors. - - There are only two resource descriptor types from the ACPI Specificatio= n that may be used to - describe the current resources allocated to a PCI root bridge. These ar= e the QWORD Address - Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.= 0 Section 6.4.2.8). The - QWORD Address Space Descriptor can describe memory, I/O, and bus number= ranges for dynamic - or fixed resources. The configuration of a PCI root bridge is described= with one or more QWORD - Address Space Descriptors followed by an End Tag. - - @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOC= OL. - @param[out] Resources A pointer to the ACPI 2.0 resource descriptors= that describe the - current configuration of this PCI root bridge.= The storage for the - ACPI 2.0 resource descriptors is allocated by = this function. The - caller must treat the return buffer as read-on= ly data, and the buffer - must not be freed by the caller. - - @retval EFI_SUCCESS The current configuration of this PCI root bri= dge was returned in Resources. - @retval EFI_UNSUPPORTED The current configuration of this PCI root bri= dge could not be retrieved. - @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_I= O_PROTOCOL - -**/ -EFI_STATUS -EFIAPI -RootBridgeIoConfiguration ( - IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, - OUT VOID **Resources - ) -{ - PCI_ROOT_BRIDGE_INSTANCE *PrivateData; - UINTN Index; - - PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); - for (Index =3D 0; Index < TypeMax; Index++) { - if (PrivateData->ResAllocNode[Index].Status =3D=3D ResAllocated) { - switch (Index) { - case TypeIo: - Configuration.SpaceDesp[Index].AddrRangeMin =3D PrivateData->IoBas= e; - break; - case TypeBus: - Configuration.SpaceDesp[Index].AddrRangeMin =3D PrivateData->ResAl= locNode[Index].Base; - break; - default: - /* PCIE Device bar address should be base on PciRegionBase */ - Configuration.SpaceDesp[Index].AddrRangeMin =3D PrivateData->ResAllo= cNode[Index].Base - PrivateData->MemBase + - PrivateData->PciRegion= Base; - } - Configuration.SpaceDesp[Index].AddrRangeMax =3D Configuration.SpaceD= esp[Index].AddrRangeMin + PrivateData->ResAllocNode[Index].Length - 1; - Configuration.SpaceDesp[Index].AddrLen =3D PrivateData->ResAllo= cNode[Index].Length; - Configuration.SpaceDesp[Index].AddrTranslationOffset =3D PrivateData= ->MemBase - PrivateData->PciRegionBase; - } - } - - *Resources =3D &Configuration; - return EFI_SUCCESS; -} - --=20 2.17.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel