From nobody Sun Apr 28 09:19:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518715274147767.7002835225264; Thu, 15 Feb 2018 09:21:14 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 59E0021CF1CF9; Thu, 15 Feb 2018 09:15:19 -0800 (PST) Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D39C220F33DE for ; Thu, 15 Feb 2018 09:15:17 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id v71so2233053wmv.2 for ; Thu, 15 Feb 2018 09:21:10 -0800 (PST) Received: from localhost.localdomain ([154.145.114.50]) by smtp.gmail.com with ESMTPSA id j125sm14142363wmd.19.2018.02.15.09.21.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 09:21:07 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nCmKX7R3Xdev4YDatrRU+tbfhCl/A+i6fDJ5rTqKs34=; b=JcW74saZcS2bIItmmDqNLS+IRPrDSkgQ4QENPrea5AmzYTiq3wzkBRlVCWX0D/fXDn lZhfl3qtxkLlGhoJbeq9Am4POCqdKWiHpCDXsVOjRBZaMQoVIejQBmPWPNIW0LyPABVK 8BxaDnDkdB95qjfHTA22cdB2BuWxZVcDga9Lg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nCmKX7R3Xdev4YDatrRU+tbfhCl/A+i6fDJ5rTqKs34=; b=D6ijt9lzRxV2qsjH8hpQ94x38FZ5bhgnuNs+c1ICRamFixag7JAevX+0PlLteOqAgA Ji3ACEr/odfmLS7VVD6L5MwamOZ2ThELdz50LqI6GlODEkFVm0BUtFVm9+5oODojNeti Rx6y6QLv2uR//jFji7Ld484BM3hFS21ZgKMGwZEhOAYaTdq7yvB1bfKDAVnvg15d8jIG Agf8v6ZKJrHPH6TB2e6Wzq5dwA4Hv8FIYu8ZasSw1Del1H0zXMr+TDdtozVk0rSt4n3J IhX0F84d+S6WApBSTGTtzoLQ27DB+dArIJgaoXmnU9AStSO6HDis54ZL+eLBn8nFIOgW R7OQ== X-Gm-Message-State: APf1xPAJc2X4k4uYwNc4BcXXRtoDi73/lhfIK6vEUMBBNW+t06dHBPOu kCTMJ9HG/g1y2RICG89QZKdsvletpJo= X-Google-Smtp-Source: AH8x2245XMA5fa90sPdM4aVyxzN0HZbbFcYrA/LFX78qGskVlfObZ5Gi9tWfCOVIeai2QbiL7TG83A== X-Received: by 10.28.45.151 with SMTP id t145mr2674175wmt.129.1518715268078; Thu, 15 Feb 2018 09:21:08 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 15 Feb 2018 17:20:50 +0000 Message-Id: <20180215172054.27452-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215172054.27452-1-ard.biesheuvel@linaro.org> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 1/5] Silicon/SynQuaver/DeviceTree: add node for SPI controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: joakim.bech@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a node for the SPI controller to the device tree so the OS may attach to it. This is the SPI controller that is attached to the 96boards mezzanine connector on Developer Box. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 +++++++++++++++= +++ 1 file changed, 18 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index 9085adb326ab..ba445a50f16f 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -538,4 +538,22 @@ clock-names =3D "core", "iface"; dma-coherent; }; + + clk_alw_1_8: spi_ihclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <125000000>; + clock-output-names =3D "iHCLK"; + }; + + spi: spi@54810000 { + compatible =3D "socionext,synquacer-spi"; + reg =3D <0x0 0x54810000 0x0 0x1000>; + clocks =3D <&clk_alw_1_8>; + clock-names =3D "iHCLK"; + socionext,use-rtm; + socionext,set-aces; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; }; --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 09:19:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518715277141555.8600239073564; Thu, 15 Feb 2018 09:21:17 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id D276321CF1D1C; Thu, 15 Feb 2018 09:15:22 -0800 (PST) Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AC7AD220F33C5 for ; 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Thu, 15 Feb 2018 09:21:09 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 15 Feb 2018 17:20:51 +0000 Message-Id: <20180215172054.27452-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215172054.27452-1-ard.biesheuvel@linaro.org> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 2/5] Silicon/SynQuaver/DeviceTree: add node for I2C controller X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: joakim.bech@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add a node for the I2C controller #1 to the device tree so the OS may attach to it. This is the I2C controller that is attached to the 96boards mezzanine connector on Developer Box. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 18 +++++++++++++++= +++ 1 file changed, 18 insertions(+) diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silico= n/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi index ba445a50f16f..9ec752956d05 100644 --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi @@ -556,4 +556,22 @@ #address-cells =3D <1>; #size-cells =3D <0>; }; + + clk_i2c: i2c_pclk { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <62500000>; + clock-output-names =3D "pclk"; + }; + + i2c: i2c@51210000 { + compatible =3D "socionext,synquacer-i2c"; + reg =3D <0x0 0x51210000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&clk_i2c>; + clock-names =3D "pclk"; + clock-frequency =3D <400>; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; }; --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 09:19:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518715279330630.568390474246; Thu, 15 Feb 2018 09:21:19 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3EB2C21E0B9FA; Thu, 15 Feb 2018 09:15:23 -0800 (PST) Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CE0442095C73C for ; Thu, 15 Feb 2018 09:15:20 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id m5so437271wrg.1 for ; Thu, 15 Feb 2018 09:21:13 -0800 (PST) Received: from localhost.localdomain ([154.145.114.50]) by smtp.gmail.com with ESMTPSA id j125sm14142363wmd.19.2018.02.15.09.21.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); 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charset="utf-8" Add an overlay device tree describing the Secure96 mezzanine adapter, parameterised using PCDs. This allows this image, and the accompanying driver to be incorporated into any platform that may have such a board connected to its 96board low speed (LS) connector. Note that this relies on runtime support for overlays, which is part of our FdtLib implementation. However, no overlay support is required in the device tree compiler, since this support is fairly new (and it is rather hard to pass phandle names via PCDs anyway). So instead, the accompanying driver retrieves the phandle of the GPIO programmatically, and pokes it into the overlay before applying it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/96boards/Secure96/DeviceTree/DeviceTree.inf | 40 +++++ Platform/96boards/Secure96/DeviceTree/Secure96.dts | 74 ++++++++++ Platform/96boards/Secure96/Secure96.dec | 56 +++++++ Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c | 153 +++++++++++++= +++++++ Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf | 51 +++++++ 5 files changed, 374 insertions(+) diff --git a/Platform/96boards/Secure96/DeviceTree/DeviceTree.inf b/Platfor= m/96boards/Secure96/DeviceTree/DeviceTree.inf new file mode 100644 index 000000000000..4bf087551a80 --- /dev/null +++ b/Platform/96boards/Secure96/DeviceTree/DeviceTree.inf @@ -0,0 +1,40 @@ +## @file +# +# Device tree overlay for the 96boards Secure96 Mezzanine board +# +# Copyright (c) 2018, Linaro Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Secure96DeviceTree + FILE_GUID =3D ae548d4c-9062-4eed-835f-f510f8fc48af # gSecure96DtbFi= leGuid + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + Secure96.dts + +[Packages] + MdePkg/MdePkg.dec + Platform/96boards/Secure96/Secure96.dec + +[FixedPcd] + gSecure96TokenSpaceGuid.PcdGpioLedPolarity + gSecure96TokenSpaceGuid.PcdGpioLedU1 + gSecure96TokenSpaceGuid.PcdGpioLedU2 + gSecure96TokenSpaceGuid.PcdGpioLedU3 + gSecure96TokenSpaceGuid.PcdGpioLedU4 + gSecure96TokenSpaceGuid.PcdGpioParent + gSecure96TokenSpaceGuid.PcdSha204I2cAddress + gSecure96TokenSpaceGuid.PcdEcc508I2cAddress + gSecure96TokenSpaceGuid.PcdSpiTpmCs diff --git a/Platform/96boards/Secure96/DeviceTree/Secure96.dts b/Platform/= 96boards/Secure96/DeviceTree/Secure96.dts new file mode 100644 index 000000000000..1506a41b98de --- /dev/null +++ b/Platform/96boards/Secure96/DeviceTree/Secure96.dts @@ -0,0 +1,74 @@ +/** @file + * Copyright (c) 2018, Linaro Limited. All rights reserved. + * + * This program and the accompanying materials are licensed and made + * available under the terms and conditions of the BSD License which + * accompanies this distribution. The full text of the license may be + * found at http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR + * IMPLIED. + */ + +#define GPIO_PARENT_PLACEHOLDER_PHANDLE 0x0 + +/dts-v1/; +/plugin/; + +/ { + fragment@0 { + target-path =3D "I2C_PARENT_PLACEHOLDER_STRING"; + __overlay__ { + atsha204a { + compatible =3D "atmel,atsha204a"; + reg =3D ; + }; + atecc508a { + compatible =3D "atmel,atecc508a"; + reg =3D ; + }; + }; + }; + + fragment@1 { + target-path =3D "SPI_PARENT_PLACEHOLDER_STRING"; + __overlay__ { + tpm { + compatible =3D "infineon,slb9670"; + reg =3D ; + spi-max-frequency =3D <22500000>; + }; + }; + }; + + fragment@2 { + target-path =3D "/"; + __overlay__ { + gpio-leds { + compatible =3D "gpio-leds"; + + secure96-u1 { + gpios =3D ; + }; + secure96-u2 { + gpios =3D ; + }; + secure96-u3 { + gpios =3D ; + }; + secure96-u4 { + gpios =3D ; + }; + }; + }; + }; +}; diff --git a/Platform/96boards/Secure96/Secure96.dec b/Platform/96boards/Se= cure96/Secure96.dec new file mode 100644 index 000000000000..e2699eb324d7 --- /dev/null +++ b/Platform/96boards/Secure96/Secure96.dec @@ -0,0 +1,56 @@ +## @file +# +# Device tree overlay for the 96boards Secure96 Mezzanine board +# +# Copyright (c) 2018, Linaro Ltd. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + DEC_SPECIFICATION =3D 0x0001001A + PACKAGE_NAME =3D Secure96 + PACKAGE_GUID =3D 3e7de94f-01ac-47f1-a8e6-3c4a4ce1338e + PACKAGE_VERSION =3D 0.1 + +[Guids] + # PCD scope GUID + gSecure96TokenSpaceGuid =3D { 0x76eb3f47, 0x4d9f, 0x455e, { 0x8f, 0xd9, = 0xcc, 0x48, 0x03, 0x87, 0xb8, 0x3e } } + + # file GUID of the Secure96 DTB overlay + gSecure96DtbFileGuid =3D { 0xae548d4c, 0x9062, 0x4eed, { 0x83, 0x5f, 0xf= 5, 0x10, 0xf8, 0xfc, 0x48, 0xaf } } + + # GUID to be installed by the platform as a protocol if the Secure96 mez= zanine is present + gSecure96HardwarePresent =3D { 0x87e1c994, 0xebd9, 0x41b7, { 0x82, 0x8a,= 0x4a, 0x92, 0x87, 0x14, 0x98, 0xa7 } } + +[PcdsFixedAtBuild] + # ASCII DT path to the GPIO parent node of the Secure 96 LEDs (e.g., "/g= pio@51000000") + gSecure96TokenSpaceGuid.PcdGpioParent|""|VOID*|0x00000001 + + # GPIO polarity for the Secure96 LEDs (0 =3D=3D GPIO_ACTIVE_HIGH, 1 =3D= =3D GPIO_ACTIVE_LOW) + gSecure96TokenSpaceGuid.PcdGpioLedPolarity|0|UINT32|0x00000002 + + # GPIO pin numbers for the Secure96 LEDs + gSecure96TokenSpaceGuid.PcdGpioLedU1|0|UINT32|0x00000003 + gSecure96TokenSpaceGuid.PcdGpioLedU2|0|UINT32|0x00000004 + gSecure96TokenSpaceGuid.PcdGpioLedU3|0|UINT32|0x00000005 + gSecure96TokenSpaceGuid.PcdGpioLedU4|0|UINT32|0x00000006 + + # ASCII DT path to the I2C parent node of the Secure 96 (e.g., "/i2c@512= 10000") + gSecure96TokenSpaceGuid.PcdI2cParent|""|VOID*|0x00000007 + + gSecure96TokenSpaceGuid.PcdSha204I2cAddress|0x60|UINT32|0x00000008 + gSecure96TokenSpaceGuid.PcdEcc508I2cAddress|0x61|UINT32|0x00000009 + + # ASCII DT path to the SPI parent node of the Secure 96 (e.g., "/spi@548= 10000") + gSecure96TokenSpaceGuid.PcdSpiParent|""|VOID*|0x0000000A + + # SPI CS number for the Secure96 TPM + gSecure96TokenSpaceGuid.PcdSpiTpmCs|0|UINT32|0x0000000B diff --git a/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c b/Platfor= m/96boards/Secure96/Secure96Dxe/Secure96Dxe.c new file mode 100644 index 000000000000..46c63fdfac57 --- /dev/null +++ b/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.c @@ -0,0 +1,153 @@ +/** @file + 96boards Secure96 mezzanine board DXE driver. + + Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+ + This program and the accompanying materials are licensed and made availa= ble + under the terms and conditions of the BSD License which accompanies this + distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. +**/ + +#include +#include +#include +#include +#include +#include + +STATIC CONST CHAR8 mLedNodes[][46] =3D { + "/fragment@2/__overlay__/gpio-leds/secure96-u1", + "/fragment@2/__overlay__/gpio-leds/secure96-u2", + "/fragment@2/__overlay__/gpio-leds/secure96-u3", + "/fragment@2/__overlay__/gpio-leds/secure96-u4", +}; + +STATIC +VOID +SetOverlayFragmentTarget ( + VOID *Overlay, + CONST CHAR8 *NodeName, + CONST CHAR8 *Target + ) +{ + INT32 Node; + INT32 Err; + + Node =3D fdt_path_offset (Overlay, NodeName); + ASSERT (Node > 0); + + Err =3D fdt_setprop (Overlay, Node, "target-path", Target, + AsciiStrLen (Target) + 1); + if (Err) { + DEBUG ((DEBUG_ERROR, "%a: fdt_setprop() failed - %a\n", + __FUNCTION__, fdt_strerror (Err))); + } +} + +STATIC +VOID +FixupOverlay ( + VOID *Dtb, + VOID *Overlay + ) +{ + INT32 Node; + UINT32 GpioPhandle; + UINTN Idx; + UINT32 *GpioProp; + INT32 Err; + + // + // Set the correct GPIO phandle in the LED nodes + // + Node =3D fdt_path_offset (Dtb, FixedPcdGetPtr (PcdGpioParent)); + ASSERT (Node > 0); + + GpioPhandle =3D fdt_get_phandle (Dtb, Node); + if (!GpioPhandle) { + // + // Node has no phandle yet -> create one + // + GpioPhandle =3D 1 + fdt_get_max_phandle (Dtb); + ASSERT (GpioPhandle >=3D 1); + + Err =3D fdt_setprop_u32 (Dtb, Node, "phandle", GpioPhandle); + if (Err) { + DEBUG ((DEBUG_ERROR, + "%a: fdt_setprop_u32(.., .., \"phandle\", 0x%x) failed - %a\n", + __FUNCTION__, GpioPhandle, fdt_strerror (Err))); + } + } + + for (Idx =3D 0; Idx < ARRAY_SIZE (mLedNodes); Idx++) { + Node =3D fdt_path_offset (Overlay, mLedNodes[Idx]); + ASSERT (Node > 0); + + GpioProp =3D fdt_getprop_w (Overlay, Node, "gpios", NULL); + ASSERT (GpioProp !=3D NULL); + + *GpioProp =3D cpu_to_fdt32 (GpioPhandle); + } + + SetOverlayFragmentTarget (Overlay, "/fragment@0", + FixedPcdGetPtr (PcdI2cParent)); + + SetOverlayFragmentTarget (Overlay, "/fragment@1", + FixedPcdGetPtr (PcdSpiParent)); +} + +EFI_STATUS +EFIAPI +Secure96DxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + VOID *Dtb; + VOID *Overlay; + UINTN OverlaySize; + INT32 Err; + + // + // Find the DTB in the configuration table array. If it isn't there, just + // bail without an error: we may be running on an ACPI platform even if + // this driver does not support it [yet]. + // + Status =3D EfiGetSystemConfigurationTable (&gFdtTableGuid, &Dtb); + if (Status =3D=3D EFI_NOT_FOUND) { + return EFI_SUCCESS; + } + ASSERT_EFI_ERROR (Status); + + // + // Load the raw overlay DTB image by its file GUID. + // + Status =3D GetSectionFromAnyFv (&gSecure96DtbFileGuid, + EFI_SECTION_RAW, 0, &Overlay, &OverlaySize); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + // + // Fix up unresolved references in the overlay. + // + FixupOverlay (Dtb, Overlay); + + // + // Merge the overlay with the DTB + // + Err =3D fdt_overlay_apply (Dtb, Overlay); + if (Err) { + DEBUG ((DEBUG_ERROR, "%a: fdt_overlay_apply() failed - %a\n", + __FUNCTION__, fdt_strerror (Err))); + return EFI_NOT_FOUND; + } + + return EFI_SUCCESS; +} diff --git a/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf b/Platf= orm/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf new file mode 100644 index 000000000000..9374f7992c25 --- /dev/null +++ b/Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf @@ -0,0 +1,51 @@ +## @file +# +# Copyright (c) 2018, Linaro, Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may = be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x0001001A + BASE_NAME =3D Secure96Dxe + FILE_GUID =3D 31519ec4-65f1-4790-b223-aa9330dd75fd + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D Secure96DxeEntryPoint + +[Sources] + Secure96Dxe.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Platform/96boards/Secure96/Secure96.dec + +[LibraryClasses] + BaseLib + DebugLib + DxeServicesLib + FdtLib + UefiDriverEntryPoint + UefiLib + +[Guids] + gFdtTableGuid + gSecure96DtbFileGuid + gSecure96HardwarePresent + +[FixedPcd] + gSecure96TokenSpaceGuid.PcdGpioParent + gSecure96TokenSpaceGuid.PcdI2cParent + gSecure96TokenSpaceGuid.PcdSpiParent + +[Depex] + gSecure96HardwarePresent --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 09:19:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 151871528174417.676488185090875; Thu, 15 Feb 2018 09:21:21 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 9544F21F0DA69; Thu, 15 Feb 2018 09:15:24 -0800 (PST) Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 67A0721CF1CE6 for ; Thu, 15 Feb 2018 09:15:22 -0800 (PST) Received: by mail-wm0-x244.google.com with SMTP id v123so2195095wmd.5 for ; Thu, 15 Feb 2018 09:21:15 -0800 (PST) Received: from localhost.localdomain ([154.145.114.50]) by smtp.gmail.com with ESMTPSA id j125sm14142363wmd.19.2018.02.15.09.21.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Feb 2018 09:21:12 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=QYmLPZQGxHt2IVC/aznl+oWrvDMsqQhT1JoEhsDhth4=; b=bmELpXGgOPHL5RzydqFrx2dyWQ55HT16XUZ7uxjO9w5b10ppH3n/dFYy7igK+OjC8h VovNtNjyaR13ZyE/yV8BRbTo18ia/BcJ/KZjpqnMVAtl9PgFk7Kh+zB7vjcrXRsl/dvm ihvoA607/5EJ1Kenhqrbl+iX/8REJovnacDBc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=QYmLPZQGxHt2IVC/aznl+oWrvDMsqQhT1JoEhsDhth4=; b=QdQJP0ymsDAqkwM5uglopUcGPKjjFD3ruoEw1EUgNw4KtKAZ96ppaw5kko1wJvo762 XWYg+T0anZn+4YbQ5Ym8iqEH3keratVo/6j2EgLqaaKBa4i9w5liYw5Q45WZ3BqQM2tG fsvEyiHDx0Ce2dixJGnkbaxW3Ot+dcOO96DCwJb+dg1GMchNEEKThksUzvzU+spCKSGG ZfnqbkNBCdbOoEQGBo3fvWpLCQWZiYAiol6yveIcdt12bte2dQBR6FK4ORlcFu98dvr3 pTgHVNdDwnby5epknQXvJDr/wmOx4qPynj+86BziBPBALF0RvWxY6rSLzOodoAJwNHID f/bw== X-Gm-Message-State: APf1xPBei8wVvTza4svjjBGTdCtfT839eFtLfZNwv4vFQ1G7ki8paVvm FlCCs1Z0vtOyi1LAP/RBsTaL0MKcdUU= X-Google-Smtp-Source: AH8x227naAhCWyQdpXMJxS2Rn52ZedqmDjyk9xMdlGUnCPPuyNPc/Alhp79hnRsVzrfXrVNe738jRw== X-Received: by 10.28.157.206 with SMTP id g197mr2514165wme.96.1518715273598; Thu, 15 Feb 2018 09:21:13 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 15 Feb 2018 17:20:53 +0000 Message-Id: <20180215172054.27452-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215172054.27452-1-ard.biesheuvel@linaro.org> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 4/5] Silicon/SynQuacer/PlatformDxe: add menu option to select mezzanine X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: joakim.bech@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 96boards mezzanines are not runtime discoverable, so it is up to the user to tell the firmware what is connected. So add a pulldown entry that allows a selection to be made: note that boards are only expected to have a single LS connector, so a pulldown is appropriate here. If Secure96 has been selected by the user, install the associated GUID as a protocol, which the Secure96Dxe (which installs the DT overlay into the device tree) has a depex on. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 8 +++= +++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 2 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni | 6 +++= +++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr | 8 +++= +++++ Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h | 6 +++= ++- 5 files changed, 29 insertions(+), 1 deletion(-) diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c = b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c index aab830dc3a5a..d57d1bbb52fa 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c @@ -327,5 +327,13 @@ PlatformDxeEntryPoint ( ASSERT_EFI_ERROR (Status); } =20 + if (mHiiSettings->InstalledMezzanineType =3D=3D MEZZANINE_SECURE96) { + Handle =3D NULL; + Status =3D gBS->InstallProtocolInterface (&Handle, + &gSecure96HardwarePresent, + EFI_NATIVE_INTERFACE, NULL); + ASSERT_EFI_ERROR (Status); + } + return EFI_SUCCESS; } diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.in= f b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf index 49d9deee57ea..f3f913609452 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf @@ -34,6 +34,7 @@ [Packages] EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec MdePkg/MdePkg.dec + Platform/96boards/Secure96/Secure96.dec Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec Silicon/Socionext/SynQuacer/Drivers/Net/NetsecDxe/NetsecDxe.dec Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -59,6 +60,7 @@ [Guids] gEfiHiiPlatformSetupFormsetGuid gFdtTableGuid gNetsecNonDiscoverableDeviceGuid + gSecure96HardwarePresent gSynQuacerNonDiscoverableI2cMasterGuid gSynQuacerNonDiscoverableRuntimeI2cMasterGuid gSynQuacerPlatformFormSetGuid diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii= .uni b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni index 2eca8bbba8c3..707540542616 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.uni @@ -33,3 +33,9 @@ =20 #string STR_EMMC_DISABLED #language en-US "Disabled" #string STR_EMMC_ENABLED #language en-US "Enabled" + +#string STR_MEZZANINE_SELECT_PROMPT #language en-US "96boards mezzanine" +#string STR_MEZZANINE_SELECT_HELP #language en-US "The type of mezzan= ine board plugged into the 96boards LS connector" + +#string STR_MEZZANINE_NONE #language en-US "None/Unknown" +#string STR_MEZZANINE_SECURE96 #language en-US "Secure96" diff --git a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii= .vfr b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr index ea35e902b2d7..6c348aa0a29b 100644 --- a/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr +++ b/Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxeHii.vfr @@ -70,6 +70,14 @@ formset option text =3D STRING_TOKEN(STR_EMMC_ENABLED), value =3D EMMC_ENA= BLED, flags =3D 0; endoneof; =20 + oneof varid =3D SynQuacerPlatformSettings.InstalledMezzanineType, + prompt =3D STRING_TOKEN(STR_MEZZANINE_SELECT_PROMPT), + help =3D STRING_TOKEN(STR_MEZZANINE_SELECT_HELP), + flags =3D NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED, + option text =3D STRING_TOKEN(STR_MEZZANINE_NONE), value =3D MEZZAN= INE_NONE, flags =3D DEFAULT; + option text =3D STRING_TOKEN(STR_MEZZANINE_SECURE96), value =3D ME= ZZANINE_SECURE96, flags =3D 0; + endoneof; + subtitle text =3D STRING_TOKEN(STR_NULL_STRING); =20 endform; diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h b/Sili= con/Socionext/SynQuacer/Include/Platform/VarStore.h index fbbcbd7d3eec..a723f78a738a 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/VarStore.h @@ -22,12 +22,16 @@ #define PCIE_MAX_SPEED_UNLIMITED 0x0 #define PCIE_MAX_SPEED_GEN1 0x1 =20 +#define MEZZANINE_NONE 0x0 +#define MEZZANINE_SECURE96 0x1 + typedef struct { UINT8 EnableEmmc; UINT8 PcieSlot0MaxSpeed; UINT8 PcieSlot1MaxSpeed; UINT8 PcieSlot2MaxSpeed; - UINT8 Reserved[4]; + UINT8 InstalledMezzanineType; + UINT8 Reserved[3]; } SYNQUACER_PLATFORM_VARSTORE_DATA; =20 #endif --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel From nobody Sun Apr 28 09:19:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1518715284163436.0943014503599; Thu, 15 Feb 2018 09:21:24 -0800 (PST) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 0C5AF21F0DA7E; Thu, 15 Feb 2018 09:15:26 -0800 (PST) Received: from mail-wr0-x243.google.com (mail-wr0-x243.google.com [IPv6:2a00:1450:400c:c0c::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 10FD721F0DA4A for ; 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Thu, 15 Feb 2018 09:21:15 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Thu, 15 Feb 2018 17:20:54 +0000 Message-Id: <20180215172054.27452-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180215172054.27452-1-ard.biesheuvel@linaro.org> References: <20180215172054.27452-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 5/5] Platform/Socionext/DeveloperBox: add Secure96 support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: joakim.bech@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Add the drivers and set the PCD values according to our integration of the LS connector on Developer Box so that, when selected in the menu, the device tree presented in the OS is augmented with nodes describing the various peripherals that are present on the Secure96 mezzanine board. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 21 ++++++++++++++++++++ Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 6 ++++++ 2 files changed, 27 insertions(+) diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc b/Platform/So= cionext/DeveloperBox/DeveloperBox.dsc index 1e39c29d7910..39bee17dccc1 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.dsc +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.dsc @@ -33,6 +33,9 @@ [Defines] [BuildOptions] RELEASE_*_*_CC_FLAGS =3D -DMDEPKG_NDEBUG -U_FORTIFY_SOURCE -D_FORTIFY_S= OURCE=3D0 =20 + # add ample padding to the DTC so we can apply 96boards mezzanine overla= ys + *_*_*_DTC_FLAGS =3D -p 1024 + [BuildOptions.common.EDKII.DXE_CORE,BuildOptions.common.EDKII.DXE_DRIVER,B= uildOptions.common.EDKII.UEFI_DRIVER,BuildOptions.common.EDKII.UEFI_APPLICA= TION] GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000 =20 @@ -396,6 +399,18 @@ [PcdsFixedAtBuild.common] !endif gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision|$(BUILD_NUMBER) =20 + # + # 96boards Secure96 mezzanine support + # + gSecure96TokenSpaceGuid.PcdGpioLedPolarity|0 + gSecure96TokenSpaceGuid.PcdGpioLedU1|20 + gSecure96TokenSpaceGuid.PcdGpioLedU2|19 + gSecure96TokenSpaceGuid.PcdGpioLedU3|22 + gSecure96TokenSpaceGuid.PcdGpioLedU4|21 + gSecure96TokenSpaceGuid.PcdGpioParent|"/gpio@51000000" + gSecure96TokenSpaceGuid.PcdI2cParent|"/i2c@51210000" + gSecure96TokenSpaceGuid.PcdSpiParent|"/spi@54810000" + [PcdsPatchableInModule] gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0 @@ -642,6 +657,12 @@ [Components.common] SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.= inf =20 # + # 96board mezzanine support + # + Platform/96boards/Secure96/DeviceTree/DeviceTree.inf + Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf + + # # I2C # Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf diff --git a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf b/Platform/So= cionext/DeveloperBox/DeveloperBox.fdf index c2bc5aa85739..35e2e64c8c93 100644 --- a/Platform/Socionext/DeveloperBox/DeveloperBox.fdf +++ b/Platform/Socionext/DeveloperBox/DeveloperBox.fdf @@ -237,6 +237,12 @@ [FV.FvMain] } =20 # + # 96board mezzanine support + # + INF RuleOverride =3D DTB Platform/96boards/Secure96/DeviceTree/DeviceTre= e.inf + INF Platform/96boards/Secure96/Secure96Dxe/Secure96Dxe.inf + + # # I2C # INF Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.= inf --=20 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel